1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select %s -o - | FileCheck %s
3---
4name:            v8s16_fpr
5alignment:       4
6legalized:       true
7regBankSelected: true
8tracksRegLiveness: true
9body:             |
10  bb.0:
11    liveins: $q1, $h0
12
13    ; CHECK-LABEL: name: v8s16_fpr
14    ; CHECK: liveins: $q1, $h0
15    ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
16    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
17    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
18    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.hsub
19    ; CHECK: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
20    ; CHECK: $q0 = COPY [[INSvi16lane]]
21    ; CHECK: RET_ReallyLR implicit $q0
22    %0:fpr(s16) = COPY $h0
23    %1:fpr(<8 x s16>) = COPY $q1
24    %3:gpr(s32) = G_CONSTANT i32 1
25    %2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %0(s16), %3(s32)
26    $q0 = COPY %2(<8 x s16>)
27    RET_ReallyLR implicit $q0
28
29...
30---
31name:            v4s32_fpr
32alignment:       4
33legalized:       true
34regBankSelected: true
35tracksRegLiveness: true
36body:             |
37  bb.0:
38    liveins: $q1, $s0
39
40    ; CHECK-LABEL: name: v4s32_fpr
41    ; CHECK: liveins: $q1, $s0
42    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
43    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
44    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
45    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub
46    ; CHECK: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
47    ; CHECK: $q0 = COPY [[INSvi32lane]]
48    ; CHECK: RET_ReallyLR implicit $q0
49    %0:fpr(s32) = COPY $s0
50    %1:fpr(<4 x s32>) = COPY $q1
51    %3:gpr(s32) = G_CONSTANT i32 1
52    %2:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
53    $q0 = COPY %2(<4 x s32>)
54    RET_ReallyLR implicit $q0
55
56...
57---
58name:            v4s32_gpr
59alignment:       4
60legalized:       true
61regBankSelected: true
62tracksRegLiveness: true
63body:             |
64  bb.0:
65    liveins: $q0, $w0
66
67    ; CHECK-LABEL: name: v4s32_gpr
68    ; CHECK: liveins: $q0, $w0
69    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
70    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
71    ; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[COPY1]], 1, [[COPY]]
72    ; CHECK: $q0 = COPY [[INSvi32gpr]]
73    ; CHECK: RET_ReallyLR implicit $q0
74    %0:gpr(s32) = COPY $w0
75    %1:fpr(<4 x s32>) = COPY $q0
76    %3:gpr(s32) = G_CONSTANT i32 1
77    %2:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
78    $q0 = COPY %2(<4 x s32>)
79    RET_ReallyLR implicit $q0
80
81...
82---
83name:            v2s64_fpr
84alignment:       4
85legalized:       true
86regBankSelected: true
87tracksRegLiveness: true
88body:             |
89  bb.0:
90    liveins: $d0, $q1
91
92    ; CHECK-LABEL: name: v2s64_fpr
93    ; CHECK: liveins: $d0, $q1
94    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
95    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
96    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
97    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
98    ; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
99    ; CHECK: $q0 = COPY [[INSvi64lane]]
100    ; CHECK: RET_ReallyLR implicit $q0
101    %0:fpr(s64) = COPY $d0
102    %1:fpr(<2 x s64>) = COPY $q1
103    %3:gpr(s32) = G_CONSTANT i32 1
104    %2:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s32)
105    $q0 = COPY %2(<2 x s64>)
106    RET_ReallyLR implicit $q0
107
108...
109---
110name:            v2s64_gpr
111alignment:       4
112legalized:       true
113regBankSelected: true
114tracksRegLiveness: true
115body:             |
116  bb.0:
117    liveins: $q0, $x0
118
119    ; CHECK-LABEL: name: v2s64_gpr
120    ; CHECK: liveins: $q0, $x0
121    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
122    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
123    ; CHECK: [[INSvi64gpr:%[0-9]+]]:fpr128 = INSvi64gpr [[COPY1]], 0, [[COPY]]
124    ; CHECK: $q0 = COPY [[INSvi64gpr]]
125    ; CHECK: RET_ReallyLR implicit $q0
126    %0:gpr(s64) = COPY $x0
127    %1:fpr(<2 x s64>) = COPY $q0
128    %3:gpr(s32) = G_CONSTANT i32 0
129    %2:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s32)
130    $q0 = COPY %2(<2 x s64>)
131    RET_ReallyLR implicit $q0
132
133...
134---
135name:            v2s32_fpr
136alignment:       4
137legalized:       true
138regBankSelected: true
139tracksRegLiveness: true
140body:             |
141  bb.0:
142    liveins: $d1, $s0
143
144    ; CHECK-LABEL: name: v2s32_fpr
145    ; CHECK: liveins: $d1, $s0
146    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
147    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
148    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
149    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
150    ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
151    ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.ssub
152    ; CHECK: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
153    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32lane]].dsub
154    ; CHECK: $d0 = COPY [[COPY2]]
155    ; CHECK: RET_ReallyLR implicit $d0
156    %0:fpr(s32) = COPY $s0
157    %1:fpr(<2 x s32>) = COPY $d1
158    %3:gpr(s32) = G_CONSTANT i32 1
159    %2:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
160    $d0 = COPY %2(<2 x s32>)
161    RET_ReallyLR implicit $d0
162
163...
164---
165name:            v2s32_gpr
166alignment:       4
167legalized:       true
168regBankSelected: true
169tracksRegLiveness: true
170body:             |
171  bb.0:
172    liveins: $d0, $w0
173
174    ; CHECK-LABEL: name: v2s32_gpr
175    ; CHECK: liveins: $d0, $w0
176    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
177    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
178    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
179    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
180    ; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[COPY]]
181    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
182    ; CHECK: $d0 = COPY [[COPY2]]
183    ; CHECK: RET_ReallyLR implicit $d0
184    %0:gpr(s32) = COPY $w0
185    %1:fpr(<2 x s32>) = COPY $d0
186    %3:gpr(s32) = G_CONSTANT i32 1
187    %2:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
188    $d0 = COPY %2(<2 x s32>)
189    RET_ReallyLR implicit $d0
190
191...
192