1; RUN: opt -mtriple=amdgcn-unknown-amdhsa -mcpu=tahiti -enable-new-pm=0 -analyze -divergence -use-gpu-divergence-analysis %s | FileCheck %s 2; RUN: opt -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx908 -enable-new-pm=0 -analyze -divergence -use-gpu-divergence-analysis %s | FileCheck %s 3; RUN: opt -mtriple amdgcn-unknown-amdhsa -mcpu=tahiti -passes='print<divergence>' -disable-output %s 2>&1 | FileCheck %s 4; RUN: opt -mtriple amdgcn-unknown-amdhsa -mcpu=gfx908 -passes='print<divergence>' -disable-output %s 2>&1 | FileCheck %s 5; Make sure nothing crashes on targets with or without AGPRs 6 7; CHECK: Divergence Analysis' for function 'inline_asm_1_sgpr_virtreg_output': 8; CHECK-NOT: DIVERGENT 9define i32 @inline_asm_1_sgpr_virtreg_output() { 10 %sgpr = call i32 asm "s_mov_b32 $0, 0", "=s"() 11 ret i32 %sgpr 12} 13 14; CHECK: Divergence Analysis' for function 'inline_asm_1_sgpr_physreg_output': 15; CHECK-NOT: DIVERGENT 16define i32 @inline_asm_1_sgpr_physreg_output() { 17 %sgpr = call i32 asm "s_mov_b32 s0, 0", "={s0}"() 18 ret i32 %sgpr 19} 20 21; CHECK: Divergence Analysis' for function 'inline_asm_1_vgpr_virtreg_output': 22; CHECK: DIVERGENT: %vgpr = call i32 asm "v_mov_b32 $0, 0", "=v"() 23define i32 @inline_asm_1_vgpr_virtreg_output() { 24 %vgpr = call i32 asm "v_mov_b32 $0, 0", "=v"() 25 ret i32 %vgpr 26} 27 28; CHECK: Divergence Analysis' for function 'inline_asm_1_vgpr_physreg_output': 29; CHECK: DIVERGENT: %vgpr = call i32 asm "v_mov_b32 v0, 0", "={v0}"() 30define i32 @inline_asm_1_vgpr_physreg_output() { 31 %vgpr = call i32 asm "v_mov_b32 v0, 0", "={v0}"() 32 ret i32 %vgpr 33} 34 35; CHECK: Divergence Analysis' for function 'inline_asm_1_agpr_virtreg_output': 36; CHECK: DIVERGENT: %vgpr = call i32 asm "; def $0", "=a"() 37define i32 @inline_asm_1_agpr_virtreg_output() { 38 %vgpr = call i32 asm "; def $0", "=a"() 39 ret i32 %vgpr 40} 41 42; CHECK: Divergence Analysis' for function 'inline_asm_1_agpr_physreg_output': 43; CHECK: DIVERGENT: %vgpr = call i32 asm "; def a0", "={a0}"() 44define i32 @inline_asm_1_agpr_physreg_output() { 45 %vgpr = call i32 asm "; def a0", "={a0}"() 46 ret i32 %vgpr 47} 48 49; CHECK: Divergence Analysis' for function 'inline_asm_2_sgpr_virtreg_output': 50; CHECK-NOT: DIVERGENT 51define void @inline_asm_2_sgpr_virtreg_output() { 52 %asm = call { i32, i32 } asm "; def $0, $1", "=s,=s"() 53 %sgpr0 = extractvalue { i32, i32 } %asm, 0 54 %sgpr1 = extractvalue { i32, i32 } %asm, 1 55 store i32 %sgpr0, i32 addrspace(1)* undef 56 store i32 %sgpr1, i32 addrspace(1)* undef 57 ret void 58} 59 60; One output is SGPR, one is VGPR. Infer divergent for the aggregate, but uniform on the SGPR extract 61; CHECK: Divergence Analysis' for function 'inline_asm_sgpr_vgpr_virtreg_output': 62; CHECK: DIVERGENT: %asm = call { i32, i32 } asm "; def $0, $1", "=s,=v"() 63; CHECK-NEXT: {{^[ \t]+}}%sgpr = extractvalue { i32, i32 } %asm, 0 64; CHECK-NEXT: DIVERGENT: %vgpr = extractvalue { i32, i32 } %asm, 1 65define void @inline_asm_sgpr_vgpr_virtreg_output() { 66 %asm = call { i32, i32 } asm "; def $0, $1", "=s,=v"() 67 %sgpr = extractvalue { i32, i32 } %asm, 0 68 %vgpr = extractvalue { i32, i32 } %asm, 1 69 store i32 %sgpr, i32 addrspace(1)* undef 70 store i32 %vgpr, i32 addrspace(1)* undef 71 ret void 72} 73 74; CHECK: Divergence Analysis' for function 'inline_asm_vgpr_sgpr_virtreg_output': 75; CHECK: DIVERGENT: %asm = call { i32, i32 } asm "; def $0, $1", "=v,=s"() 76; CHECK-NEXT: DIVERGENT: %vgpr = extractvalue { i32, i32 } %asm, 0 77; CHECK-NEXT: {{^[ \t]+}}%sgpr = extractvalue { i32, i32 } %asm, 1 78define void @inline_asm_vgpr_sgpr_virtreg_output() { 79 %asm = call { i32, i32 } asm "; def $0, $1", "=v,=s"() 80 %vgpr = extractvalue { i32, i32 } %asm, 0 81 %sgpr = extractvalue { i32, i32 } %asm, 1 82 store i32 %vgpr, i32 addrspace(1)* undef 83 store i32 %sgpr, i32 addrspace(1)* undef 84 ret void 85} 86 87; Have an extra output constraint 88; CHECK: Divergence Analysis' for function 'multi_sgpr_inline_asm_output_input_constraint': 89; CHECK-NOT: DIVERGENT 90define void @multi_sgpr_inline_asm_output_input_constraint() { 91 %asm = call { i32, i32 } asm "; def $0, $1", "=s,=s,s"(i32 1234) 92 %sgpr0 = extractvalue { i32, i32 } %asm, 0 93 %sgpr1 = extractvalue { i32, i32 } %asm, 1 94 store i32 %sgpr0, i32 addrspace(1)* undef 95 store i32 %sgpr1, i32 addrspace(1)* undef 96 ret void 97} 98 99; CHECK: Divergence Analysis' for function 'inline_asm_vgpr_sgpr_virtreg_output_input_constraint': 100; CHECK: DIVERGENT: %asm = call { i32, i32 } asm "; def $0, $1", "=v,=s,v"(i32 1234) 101; CHECK-NEXT: DIVERGENT: %vgpr = extractvalue { i32, i32 } %asm, 0 102; CHECK-NEXT: {{^[ \t]+}}%sgpr = extractvalue { i32, i32 } %asm, 1 103define void @inline_asm_vgpr_sgpr_virtreg_output_input_constraint() { 104 %asm = call { i32, i32 } asm "; def $0, $1", "=v,=s,v"(i32 1234) 105 %vgpr = extractvalue { i32, i32 } %asm, 0 106 %sgpr = extractvalue { i32, i32 } %asm, 1 107 store i32 %vgpr, i32 addrspace(1)* undef 108 store i32 %sgpr, i32 addrspace(1)* undef 109 ret void 110} 111