1; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=hawaii < %s | FileCheck -check-prefixes=ALL,CIFASTF64,NOFP16,NOFP16-NOFP32DENORM,SLOWFP32DENORMS %s 2; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefixes=ALL,CISLOWF64,NOFP16,NOFP16-NOFP32DENORM,SLOWFP32DENORMS %s 3; RUN: opt -cost-model -analyze -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti < %s | FileCheck -check-prefixes=ALL,SIFASTF64,NOFP32DENORM,NOFP16,NOFP16-NOFP32DENORM,SLOWFP32DENORMS %s 4; RUN: opt -cost-model -analyze -mtriple=amdgcn-mesa-mesa3d -mcpu=verde < %s | FileCheck -check-prefixes=ALL,SISLOWF64,NOFP32DENORM,NOFP16,NOFP16-NOFP32DENORM,SLOWFP32DENORMS %s 5; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=hawaii < %s | FileCheck -check-prefixes=ALL,NOFP16,NOFP16-FP32DENORM,SLOWFP32DENORMS %s 6; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=ALL,FASTFP32DENORMS,FP16 %s 7 8; RUN: opt -cost-model -cost-kind=code-size -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=hawaii < %s | FileCheck -check-prefixes=ALL,CIFASTF64,NOFP16,NOFP16-NOFP32DENORM %s 9; RUN: opt -cost-model -cost-kind=code-size -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefixes=ALL,CISLOWF64,NOFP16,NOFP16-NOFP32DENORM %s 10; RUN: opt -cost-model -cost-kind=code-size -analyze -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti < %s | FileCheck -check-prefixes=ALL,SIFASTF64,NOFP16,NOFP16-NOFP32DENORM %s 11; RUN: opt -cost-model -cost-kind=code-size -analyze -mtriple=amdgcn-mesa-mesa3d -mcpu=verde < %s | FileCheck -check-prefixes=ALL,SISLOWF64,NOFP16,NOFP16-NOFP32DENORM %s 12; RUN: opt -cost-model -cost-kind=code-size -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=hawaii < %s | FileCheck -check-prefixes=ALL,SLOWFP32DENORMS,NOFP16,NOFP16-FP32DENORM %s 13; RUN: opt -cost-model -cost-kind=code-size -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=ALL,FASTFP32DENORMS,FP16 %s 14 15; ALL: 'fdiv_f32_ieee' 16; ALL: estimated cost of 10 for {{.*}} fdiv float 17define amdgpu_kernel void @fdiv_f32_ieee(float addrspace(1)* %out, float addrspace(1)* %vaddr, float %b) #0 { 18 %vec = load float, float addrspace(1)* %vaddr 19 %add = fdiv float %vec, %b 20 store float %add, float addrspace(1)* %out 21 ret void 22} 23 24; ALL: 'fdiv_f32_ftzdaz' 25; ALL: estimated cost of 12 for {{.*}} fdiv float 26define amdgpu_kernel void @fdiv_f32_ftzdaz(float addrspace(1)* %out, float addrspace(1)* %vaddr, float %b) #1 { 27 %vec = load float, float addrspace(1)* %vaddr 28 %add = fdiv float %vec, %b 29 store float %add, float addrspace(1)* %out 30 ret void 31} 32 33; ALL: 'fdiv_v2f32_ieee' 34; ALL: estimated cost of 20 for {{.*}} fdiv <2 x float> 35define amdgpu_kernel void @fdiv_v2f32_ieee(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %vaddr, <2 x float> %b) #0 { 36 %vec = load <2 x float>, <2 x float> addrspace(1)* %vaddr 37 %add = fdiv <2 x float> %vec, %b 38 store <2 x float> %add, <2 x float> addrspace(1)* %out 39 ret void 40} 41 42; ALL: 'fdiv_v2f32_ftzdaz' 43; ALL: estimated cost of 24 for {{.*}} fdiv <2 x float> 44define amdgpu_kernel void @fdiv_v2f32_ftzdaz(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %vaddr, <2 x float> %b) #1 { 45 %vec = load <2 x float>, <2 x float> addrspace(1)* %vaddr 46 %add = fdiv <2 x float> %vec, %b 47 store <2 x float> %add, <2 x float> addrspace(1)* %out 48 ret void 49} 50 51; ALL: 'fdiv_v3f32_ieee' 52; Allow for 48/40 when v3f32 is illegal and TargetLowering thinks it needs widening, 53; and 36/30 when it is legal. 54; ALL: estimated cost of {{30|40}} for {{.*}} fdiv <3 x float> 55define amdgpu_kernel void @fdiv_v3f32_ieee(<3 x float> addrspace(1)* %out, <3 x float> addrspace(1)* %vaddr, <3 x float> %b) #0 { 56 %vec = load <3 x float>, <3 x float> addrspace(1)* %vaddr 57 %add = fdiv <3 x float> %vec, %b 58 store <3 x float> %add, <3 x float> addrspace(1)* %out 59 ret void 60} 61 62; ALL: 'fdiv_v3f32_ftzdaz' 63; Allow for 48/40 when v3f32 is illegal and TargetLowering thinks it needs widening, 64; and 36/30 when it is legal. 65; ALL: estimated cost of {{36|48}} for {{.*}} fdiv <3 x float> 66define amdgpu_kernel void @fdiv_v3f32_ftzdaz(<3 x float> addrspace(1)* %out, <3 x float> addrspace(1)* %vaddr, <3 x float> %b) #1 { 67 %vec = load <3 x float>, <3 x float> addrspace(1)* %vaddr 68 %add = fdiv <3 x float> %vec, %b 69 store <3 x float> %add, <3 x float> addrspace(1)* %out 70 ret void 71} 72 73; ALL: 'fdiv_v5f32_ieee' 74; Allow for 96/80 when v5f32 is illegal and TargetLowering thinks it needs widening, 75; and 60/50 when it is legal. 76; ALL: estimated cost of {{80|50}} for {{.*}} fdiv <5 x float> 77define amdgpu_kernel void @fdiv_v5f32_ieee(<5 x float> addrspace(1)* %out, <5 x float> addrspace(1)* %vaddr, <5 x float> %b) #0 { 78 %vec = load <5 x float>, <5 x float> addrspace(1)* %vaddr 79 %add = fdiv <5 x float> %vec, %b 80 store <5 x float> %add, <5 x float> addrspace(1)* %out 81 ret void 82} 83 84; ALL: 'fdiv_v5f32_ftzdaz' 85; Allow for 96/80 when v5f32 is illegal and TargetLowering thinks it needs widening, 86; and 60/50 when it is legal. 87; ALL: estimated cost of {{96|60}} for {{.*}} fdiv <5 x float> 88define amdgpu_kernel void @fdiv_v5f32_ftzdaz(<5 x float> addrspace(1)* %out, <5 x float> addrspace(1)* %vaddr, <5 x float> %b) #1 { 89 %vec = load <5 x float>, <5 x float> addrspace(1)* %vaddr 90 %add = fdiv <5 x float> %vec, %b 91 store <5 x float> %add, <5 x float> addrspace(1)* %out 92 ret void 93} 94 95; ALL: 'fdiv_f64' 96; CIFASTF64: estimated cost of 29 for {{.*}} fdiv double 97; CISLOWF64: estimated cost of 33 for {{.*}} fdiv double 98; SIFASTF64: estimated cost of 32 for {{.*}} fdiv double 99; SISLOWF64: estimated cost of 36 for {{.*}} fdiv double 100define amdgpu_kernel void @fdiv_f64(double addrspace(1)* %out, double addrspace(1)* %vaddr, double %b) #0 { 101 %vec = load double, double addrspace(1)* %vaddr 102 %add = fdiv double %vec, %b 103 store double %add, double addrspace(1)* %out 104 ret void 105} 106 107; ALL: 'fdiv_v2f64' 108; CIFASTF64: estimated cost of 58 for {{.*}} fdiv <2 x double> 109; CISLOWF64: estimated cost of 66 for {{.*}} fdiv <2 x double> 110; SIFASTF64: estimated cost of 64 for {{.*}} fdiv <2 x double> 111; SISLOWF64: estimated cost of 72 for {{.*}} fdiv <2 x double> 112define amdgpu_kernel void @fdiv_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %vaddr, <2 x double> %b) #0 { 113 %vec = load <2 x double>, <2 x double> addrspace(1)* %vaddr 114 %add = fdiv <2 x double> %vec, %b 115 store <2 x double> %add, <2 x double> addrspace(1)* %out 116 ret void 117} 118 119; ALL: 'fdiv_v3f64' 120; CIFASTF64: estimated cost of 87 for {{.*}} fdiv <3 x double> 121; CISLOWF64: estimated cost of 99 for {{.*}} fdiv <3 x double> 122; SIFASTF64: estimated cost of 96 for {{.*}} fdiv <3 x double> 123; SISLOWF64: estimated cost of 108 for {{.*}} fdiv <3 x double> 124define amdgpu_kernel void @fdiv_v3f64(<3 x double> addrspace(1)* %out, <3 x double> addrspace(1)* %vaddr, <3 x double> %b) #0 { 125 %vec = load <3 x double>, <3 x double> addrspace(1)* %vaddr 126 %add = fdiv <3 x double> %vec, %b 127 store <3 x double> %add, <3 x double> addrspace(1)* %out 128 ret void 129} 130 131; ALL: 'fdiv_f16_f32_ieee' 132; NOFP16: estimated cost of 10 for {{.*}} fdiv half 133; FP16: estimated cost of 10 for {{.*}} fdiv half 134define amdgpu_kernel void @fdiv_f16_f32_ieee(half addrspace(1)* %out, half addrspace(1)* %vaddr, half %b) #0 { 135 %vec = load half, half addrspace(1)* %vaddr 136 %add = fdiv half %vec, %b 137 store half %add, half addrspace(1)* %out 138 ret void 139} 140 141; ALL: 'fdiv_f16_f32_ftzdaz' 142; NOFP16: estimated cost of 12 for {{.*}} fdiv half 143; FP16: estimated cost of 10 for {{.*}} fdiv half 144define amdgpu_kernel void @fdiv_f16_f32_ftzdaz(half addrspace(1)* %out, half addrspace(1)* %vaddr, half %b) #1 { 145 %vec = load half, half addrspace(1)* %vaddr 146 %add = fdiv half %vec, %b 147 store half %add, half addrspace(1)* %out 148 ret void 149} 150 151; ALL: 'fdiv_v2f16_f32_ieee' 152; NOFP16: estimated cost of 20 for {{.*}} fdiv <2 x half> 153; FP16: estimated cost of 20 for {{.*}} fdiv <2 x half> 154define amdgpu_kernel void @fdiv_v2f16_f32_ieee(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %vaddr, <2 x half> %b) #0 { 155 %vec = load <2 x half>, <2 x half> addrspace(1)* %vaddr 156 %add = fdiv <2 x half> %vec, %b 157 store <2 x half> %add, <2 x half> addrspace(1)* %out 158 ret void 159} 160 161; ALL: 'fdiv_v2f16_f32_ftzdaz' 162; NOFP16: estimated cost of 24 for {{.*}} fdiv <2 x half> 163; FP16: estimated cost of 20 for {{.*}} fdiv <2 x half> 164define amdgpu_kernel void @fdiv_v2f16_f32_ftzdaz(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %vaddr, <2 x half> %b) #1 { 165 %vec = load <2 x half>, <2 x half> addrspace(1)* %vaddr 166 %add = fdiv <2 x half> %vec, %b 167 store <2 x half> %add, <2 x half> addrspace(1)* %out 168 ret void 169} 170 171; ALL: 'fdiv_v4f16_f32_ieee' 172; NOFP16: estimated cost of 40 for {{.*}} fdiv <4 x half> 173; FP16: estimated cost of 40 for {{.*}} fdiv <4 x half> 174define amdgpu_kernel void @fdiv_v4f16_f32_ieee(<4 x half> addrspace(1)* %out, <4 x half> addrspace(1)* %vaddr, <4 x half> %b) #0 { 175 %vec = load <4 x half>, <4 x half> addrspace(1)* %vaddr 176 %add = fdiv <4 x half> %vec, %b 177 store <4 x half> %add, <4 x half> addrspace(1)* %out 178 ret void 179} 180 181; ALL: 'fdiv_v4f16_f32_ftzdaz' 182; NOFP16: estimated cost of 48 for {{.*}} fdiv <4 x half> 183; FP16: estimated cost of 40 for {{.*}} fdiv <4 x half> 184define amdgpu_kernel void @fdiv_v4f16_f32_ftzdaz(<4 x half> addrspace(1)* %out, <4 x half> addrspace(1)* %vaddr, <4 x half> %b) #1 { 185 %vec = load <4 x half>, <4 x half> addrspace(1)* %vaddr 186 %add = fdiv <4 x half> %vec, %b 187 store <4 x half> %add, <4 x half> addrspace(1)* %out 188 ret void 189} 190 191; ALL: 'rcp_f32_ieee' 192; SLOWFP32DENORMS: estimated cost of 10 for {{.*}} fdiv float 193; FASTFP32DENORMS: estimated cost of 10 for {{.*}} fdiv float 194define amdgpu_kernel void @rcp_f32_ieee(float addrspace(1)* %out, float addrspace(1)* %vaddr) #0 { 195 %vec = load float, float addrspace(1)* %vaddr 196 %add = fdiv float 1.0, %vec 197 store float %add, float addrspace(1)* %out 198 ret void 199} 200 201; ALL: 'rcp_f32_ftzdaz' 202; ALL: estimated cost of 3 for {{.*}} fdiv float 203define amdgpu_kernel void @rcp_f32_ftzdaz(float addrspace(1)* %out, float addrspace(1)* %vaddr) #1 { 204 %vec = load float, float addrspace(1)* %vaddr 205 %add = fdiv float 1.0, %vec 206 store float %add, float addrspace(1)* %out 207 ret void 208} 209 210; ALL: 'rcp_f16_f32_ieee' 211; NOFP16: estimated cost of 10 for {{.*}} fdiv half 212; FP16: estimated cost of 3 for {{.*}} fdiv half 213define amdgpu_kernel void @rcp_f16_f32_ieee(half addrspace(1)* %out, half addrspace(1)* %vaddr) #0 { 214 %vec = load half, half addrspace(1)* %vaddr 215 %add = fdiv half 1.0, %vec 216 store half %add, half addrspace(1)* %out 217 ret void 218} 219 220; ALL: 'rcp_f16_f32_ftzdaz' 221; NOFP16: estimated cost of 3 for {{.*}} fdiv half 222; FP16: estimated cost of 3 for {{.*}} fdiv half 223define amdgpu_kernel void @rcp_f16_f32_ftzdaz(half addrspace(1)* %out, half addrspace(1)* %vaddr) #1 { 224 %vec = load half, half addrspace(1)* %vaddr 225 %add = fdiv half 1.0, %vec 226 store half %add, half addrspace(1)* %out 227 ret void 228} 229 230; ALL: 'rcp_f64' 231; CIFASTF64: estimated cost of 29 for {{.*}} fdiv double 232; CISLOWF64: estimated cost of 33 for {{.*}} fdiv double 233; SIFASTF64: estimated cost of 32 for {{.*}} fdiv double 234; SISLOWF64: estimated cost of 36 for {{.*}} fdiv double 235define amdgpu_kernel void @rcp_f64(double addrspace(1)* %out, double addrspace(1)* %vaddr) #0 { 236 %vec = load double, double addrspace(1)* %vaddr 237 %add = fdiv double 1.0, %vec 238 store double %add, double addrspace(1)* %out 239 ret void 240} 241 242; ALL: 'rcp_v2f32_ieee' 243; SLOWFP32DENORMS: estimated cost of 20 for {{.*}} fdiv <2 x float> 244; FASTFP32DENORMS: estimated cost of 20 for {{.*}} fdiv <2 x float> 245define amdgpu_kernel void @rcp_v2f32_ieee(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %vaddr) #0 { 246 %vec = load <2 x float>, <2 x float> addrspace(1)* %vaddr 247 %add = fdiv <2 x float> <float 1.0, float 1.0>, %vec 248 store <2 x float> %add, <2 x float> addrspace(1)* %out 249 ret void 250} 251 252; ALL: 'rcp_v2f32_ftzdaz' 253; ALL: estimated cost of 6 for {{.*}} fdiv <2 x float> 254define amdgpu_kernel void @rcp_v2f32_ftzdaz(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %vaddr) #1 { 255 %vec = load <2 x float>, <2 x float> addrspace(1)* %vaddr 256 %add = fdiv <2 x float> <float 1.0, float 1.0>, %vec 257 store <2 x float> %add, <2 x float> addrspace(1)* %out 258 ret void 259} 260 261; ALL: 'rcp_v2f16_f32_ieee' 262; NOFP16: estimated cost of 20 for {{.*}} fdiv <2 x half> 263; FP16: estimated cost of 6 for {{.*}} fdiv <2 x half> 264define amdgpu_kernel void @rcp_v2f16_f32_ieee(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %vaddr) #0 { 265 %vec = load <2 x half>, <2 x half> addrspace(1)* %vaddr 266 %add = fdiv <2 x half> <half 1.0, half 1.0>, %vec 267 store <2 x half> %add, <2 x half> addrspace(1)* %out 268 ret void 269} 270 271; ALL: 'rcp_v2f16_f32_ftzdaz' 272; NOFP16: estimated cost of 6 for {{.*}} fdiv <2 x half> 273; FP16: estimated cost of 6 for {{.*}} fdiv <2 x half> 274define amdgpu_kernel void @rcp_v2f16_f32_ftzdaz(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %vaddr) #1 { 275 %vec = load <2 x half>, <2 x half> addrspace(1)* %vaddr 276 %add = fdiv <2 x half> <half 1.0, half 1.0>, %vec 277 store <2 x half> %add, <2 x half> addrspace(1)* %out 278 ret void 279} 280 281attributes #0 = { nounwind "denormal-fp-math-f32"="ieee,ieee" } 282attributes #1 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } 283