1; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=hawaii < %s | FileCheck -check-prefixes=ALL,THRPTALL,CIFASTF64,NOFP16 %s
2; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefixes=ALL,THRPTALL,CISLOWF64,NOFP16  %s
3; RUN: opt -cost-model -analyze -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti < %s | FileCheck -check-prefixes=ALL,THRPTALL,SIFASTF64,NOFP16  %s
4; RUN: opt -cost-model -analyze -mtriple=amdgcn-mesa-mesa3d -mcpu=verde < %s | FileCheck -check-prefixes=ALL,THRPTALL,SISLOWF64,NOFP16  %s
5; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=ALL,THRPTALL,FP16,CISLOWF64 %s
6
7; RUN: opt -cost-model -cost-kind=code-size -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=hawaii < %s | FileCheck -check-prefixes=ALL,SIZEALL,SIZECI,SIZENOF16 %s
8; RUN: opt -cost-model -cost-kind=code-size -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefixes=ALL,SIZEALL,SIZECI,SIZENOF16 %s
9; RUN: opt -cost-model -cost-kind=code-size -analyze -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti < %s | FileCheck -check-prefixes=ALL,SIZEALL,SIZESI,SIZENOF16  %s
10; RUN: opt -cost-model -cost-kind=code-size -analyze -mtriple=amdgcn-mesa-mesa3d -mcpu=verde < %s | FileCheck -check-prefixes=ALL,SIZEALL,SIZESI,SIZENOF16  %s
11; RUN: opt -cost-model -cost-kind=code-size -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=ALL,SIZEALL,SIZECI,SIZEF16 %s
12; END.
13
14; ALL-LABEL: 'fdiv_f32_ieee'
15; THRPTALL: estimated cost of 14 for {{.*}} fdiv float
16; THRPTALL: estimated cost of 28 for {{.*}} fdiv <2 x float>
17; THRPTALL: estimated cost of 42 for {{.*}} fdiv <3 x float>
18; THRPTALL: estimated cost of 70 for {{.*}} fdiv <5 x float>
19; SIZEALL: estimated cost of 12 for {{.*}} fdiv float
20; SIZEALL: estimated cost of 24 for {{.*}} fdiv <2 x float>
21; SIZEALL: estimated cost of 36 for {{.*}} fdiv <3 x float>
22; SIZEALL: estimated cost of 60 for {{.*}} fdiv <5 x float>
23define amdgpu_kernel void @fdiv_f32_ieee() #0 {
24  %f32 = fdiv float undef, undef
25  %v2f32 = fdiv <2 x float> undef, undef
26  %v3f32 = fdiv <3 x float> undef, undef
27  %v5f32 = fdiv <5 x float> undef, undef
28  ret void
29}
30
31; ALL-LABEL: 'fdiv_f32_ftzdaz'
32; THRPTALL: estimated cost of 16 for {{.*}} fdiv float
33; SIZEALL: estimated cost of 14 for {{.*}} fdiv float
34; THRPTALL: estimated cost of 32 for {{.*}} fdiv <2 x float>
35; SIZEALL: estimated cost of 28 for {{.*}} fdiv <2 x float>
36; THRPTALL: estimated cost of 48 for {{.*}} fdiv <3 x float>
37; SIZEALL: estimated cost of 42 for {{.*}} fdiv <3 x float>
38; THRPTALL: estimated cost of 80 for {{.*}} fdiv <5 x float>
39; SIZEALL: estimated cost of 70 for {{.*}} fdiv <5 x float>
40define amdgpu_kernel void @fdiv_f32_ftzdaz() #1 {
41  %f32 = fdiv float undef, undef
42  %v2f32 = fdiv <2 x float> undef, undef
43  %v3f32 = fdiv <3 x float> undef, undef
44  %v5f32 = fdiv <5 x float> undef, undef
45  ret void
46}
47
48; ALL-LABEL: 'fdiv_f64'
49; CIFASTF64: estimated cost of 24 for {{.*}} fdiv double
50; CISLOWF64: estimated cost of 38 for {{.*}} fdiv double
51; SIFASTF64: estimated cost of 27 for {{.*}} fdiv double
52; SISLOWF64: estimated cost of 41 for {{.*}} fdiv double
53; SIZECI: estimated cost of 22 for {{.*}} fdiv double
54; SIZESI: estimated cost of 25 for {{.*}} fdiv double
55; CIFASTF64: estimated cost of 48 for {{.*}} fdiv <2 x double>
56; CISLOWF64: estimated cost of 76 for {{.*}} fdiv <2 x double>
57; SIFASTF64: estimated cost of 54 for {{.*}} fdiv <2 x double>
58; SISLOWF64: estimated cost of 82 for {{.*}} fdiv <2 x double>
59; SIZECI: estimated cost of 44 for {{.*}} fdiv <2 x double>
60; SIZESI: estimated cost of 50 for {{.*}} fdiv <2 x double>
61; CIFASTF64: estimated cost of 72 for {{.*}} fdiv <3 x double>
62; CISLOWF64: estimated cost of 114 for {{.*}} fdiv <3 x double>
63; SIFASTF64: estimated cost of 81 for {{.*}} fdiv <3 x double>
64; SISLOWF64: estimated cost of 123 for {{.*}} fdiv <3 x double>
65; SIZECI: estimated cost of 66 for {{.*}} fdiv <3 x double>
66; SIZESI: estimated cost of 75 for {{.*}} fdiv <3 x double>
67define amdgpu_kernel void @fdiv_f64() #0 {
68  %f64 = fdiv double undef, undef
69  %v2f64 = fdiv <2 x double> undef, undef
70  %v3f64 = fdiv <3 x double> undef, undef
71  ret void
72}
73
74; ALL-LABEL: 'fdiv_f16_f32ieee'
75; NOFP16: estimated cost of 14 for {{.*}} fdiv half
76; FP16: estimated cost of 12 for {{.*}} fdiv half
77; SIZENOF16: estimated cost of 12 for {{.*}} fdiv half
78; SIZEF16: estimated cost of 8 for {{.*}} fdiv half
79; NOFP16: estimated cost of 28 for {{.*}} fdiv <2 x half>
80; FP16: estimated cost of 24 for {{.*}} fdiv <2 x half>
81; SIZENOF16: estimated cost of 24 for {{.*}} fdiv <2 x half>
82; SIZEF16: estimated cost of 16 for {{.*}} fdiv <2 x half>
83; NOFP16: estimated cost of 56 for {{.*}} fdiv <4 x half>
84; FP16: estimated cost of 48 for {{.*}} fdiv <4 x half>
85; SIZENOF16: estimated cost of 48 for {{.*}} fdiv <4 x half>
86; SIZEF16: estimated cost of 32 for {{.*}} fdiv <4 x half>
87define amdgpu_kernel void @fdiv_f16_f32ieee() #0 {
88  %f16 = fdiv half undef, undef
89  %v2f16 = fdiv <2 x half> undef, undef
90  %v4f16 = fdiv <4 x half> undef, undef
91  ret void
92}
93
94; ALL-LABEL: 'fdiv_f16_f32ftzdaz'
95; NOFP16: estimated cost of 16 for {{.*}} fdiv half
96; FP16: estimated cost of 12 for {{.*}} fdiv half
97; SIZENOF16: estimated cost of 14 for {{.*}} fdiv half
98; SIZEF16: estimated cost of 8 for {{.*}} fdiv half
99; NOFP16: estimated cost of 32 for {{.*}} fdiv <2 x half>
100; FP16: estimated cost of 24 for {{.*}} fdiv <2 x half>
101; SIZENOF16: estimated cost of 28 for {{.*}} fdiv <2 x half>
102; SIZEF16: estimated cost of 16 for {{.*}} fdiv <2 x half>
103; NOFP16: estimated cost of 64 for {{.*}} fdiv <4 x half>
104; FP16: estimated cost of 48 for {{.*}} fdiv <4 x half>
105; SIZENOF16: estimated cost of 56 for {{.*}} fdiv <4 x half>
106; SIZEF16: estimated cost of 32 for {{.*}} fdiv <4 x half>
107define amdgpu_kernel void @fdiv_f16_f32ftzdaz() #1 {
108  %f16 = fdiv half undef, undef
109  %v2f16 = fdiv <2 x half> undef, undef
110  %v4f16 = fdiv <4 x half> undef, undef
111  ret void
112}
113
114; ALL-LABEL: 'rcp_ieee'
115; THRPTALL: estimated cost of 14 for {{.*}} fdiv float
116; SIZEALL: estimated cost of 12 for {{.*}} fdiv float
117; NOFP16: estimated cost of 14 for {{.*}} fdiv half
118; FP16: estimated cost of 4 for {{.*}} fdiv half
119; SIZENOF16: estimated cost of 12 for {{.*}} fdiv half
120; SIZEF16: estimated cost of 2 for {{.*}} fdiv half
121; CIFASTF64: estimated cost of 24 for {{.*}} fdiv double
122; CISLOWF64: estimated cost of 38 for {{.*}} fdiv double
123; SIFASTF64: estimated cost of 27 for {{.*}} fdiv double
124; SISLOWF64: estimated cost of 41 for {{.*}} fdiv double
125; SIZECI: estimated cost of 22 for {{.*}} fdiv double
126; SIZESI: estimated cost of 25 for {{.*}} fdiv double
127; THRPTALL: estimated cost of 28 for {{.*}} fdiv <2 x float>
128; SIZEALL: estimated cost of 24 for {{.*}} fdiv <2 x float>
129; NOFP16: estimated cost of 28 for {{.*}} fdiv <2 x half>
130; FP16: estimated cost of 8 for {{.*}} fdiv <2 x half>
131; SIZENOF16: estimated cost of 24 for {{.*}} fdiv <2 x half>
132; SIZEF16: estimated cost of 4 for {{.*}} fdiv <2 x half>
133define amdgpu_kernel void @rcp_ieee() #0 {
134  %f32 = fdiv float 1.0, undef
135  %f16 = fdiv half 1.0, undef
136  %f64 = fdiv double 1.0, undef
137  %v2f32 = fdiv <2 x float> <float 1.0, float 1.0>, undef
138  %v2f16 = fdiv <2 x half> <half 1.0, half 1.0>, undef
139  ret void
140}
141
142; ALL-LABEL: 'rcp_ftzdaz'
143; THRPTALL: estimated cost of 4 for {{.*}} fdiv float
144; SIZEALL: estimated cost of 2 for {{.*}} fdiv float
145; THRPTALL: estimated cost of 4 for {{.*}} fdiv half
146; SIZEALL: estimated cost of 2 for {{.*}} fdiv half
147; THRPTALL: estimated cost of 8 for {{.*}} fdiv <2 x float>
148; SIZEALL: estimated cost of 4 for {{.*}} fdiv <2 x float>
149; THRPTALL: estimated cost of 8 for {{.*}} fdiv <2 x half>
150; SIZEALL: estimated cost of 4 for {{.*}} fdiv <2 x half>
151define amdgpu_kernel void @rcp_ftzdaz() #1 {
152  %f32 = fdiv float 1.0, undef
153  %f16 = fdiv half 1.0, undef
154  %v2f32 = fdiv <2 x float> <float 1.0, float 1.0>, undef
155  %v2f16 = fdiv <2 x half> <half 1.0, half 1.0>, undef
156  ret void
157}
158
159attributes #0 = { nounwind "denormal-fp-math-f32"="ieee,ieee" }
160attributes #1 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
161