1 //===-- XCoreRegisterInfo.cpp - XCore Register Information ----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the XCore implementation of the MRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "XCoreRegisterInfo.h"
15 #include "XCore.h"
16 #include "XCoreMachineFunctionInfo.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineModuleInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/Type.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/raw_ostream.h"
30 #include "llvm/Target/TargetFrameLowering.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
34 
35 #define GET_REGINFO_TARGET_DESC
36 #include "XCoreGenRegisterInfo.inc"
37 
38 using namespace llvm;
39 
40 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
41   : XCoreGenRegisterInfo(XCore::LR), TII(tii) {
42 }
43 
44 // helper functions
45 static inline bool isImmUs(unsigned val) {
46   return val <= 11;
47 }
48 
49 static inline bool isImmU6(unsigned val) {
50   return val < (1 << 6);
51 }
52 
53 static inline bool isImmU16(unsigned val) {
54   return val < (1 << 16);
55 }
56 
57 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
58   return MF.getMMI().hasDebugInfo() ||
59     MF.getFunction()->needsUnwindTableEntry();
60 }
61 
62 const uint16_t* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
63                                                                          const {
64   static const uint16_t CalleeSavedRegs[] = {
65     XCore::R4, XCore::R5, XCore::R6, XCore::R7,
66     XCore::R8, XCore::R9, XCore::R10, XCore::LR,
67     0
68   };
69   return CalleeSavedRegs;
70 }
71 
72 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
73   BitVector Reserved(getNumRegs());
74   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
75 
76   Reserved.set(XCore::CP);
77   Reserved.set(XCore::DP);
78   Reserved.set(XCore::SP);
79   Reserved.set(XCore::LR);
80   if (TFI->hasFP(MF)) {
81     Reserved.set(XCore::R10);
82   }
83   return Reserved;
84 }
85 
86 bool
87 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
88   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
89 
90   // TODO can we estimate stack size?
91   return TFI->hasFP(MF);
92 }
93 
94 bool
95 XCoreRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
96   return requiresRegisterScavenging(MF);
97 }
98 
99 bool
100 XCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
101   return false;
102 }
103 
104 // This function eliminates ADJCALLSTACKDOWN,
105 // ADJCALLSTACKUP pseudo instructions
106 void XCoreRegisterInfo::
107 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
108                               MachineBasicBlock::iterator I) const {
109   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
110 
111   if (!TFI->hasReservedCallFrame(MF)) {
112     // Turn the adjcallstackdown instruction into 'extsp <amt>' and the
113     // adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
114     MachineInstr *Old = I;
115     uint64_t Amount = Old->getOperand(0).getImm();
116     if (Amount != 0) {
117       // We need to keep the stack aligned properly.  To do this, we round the
118       // amount of space needed for the outgoing arguments up to the next
119       // alignment boundary.
120       unsigned Align = TFI->getStackAlignment();
121       Amount = (Amount+Align-1)/Align*Align;
122 
123       assert(Amount%4 == 0);
124       Amount /= 4;
125 
126       bool isU6 = isImmU6(Amount);
127       if (!isU6 && !isImmU16(Amount)) {
128         // FIX could emit multiple instructions in this case.
129 #ifndef NDEBUG
130         errs() << "eliminateCallFramePseudoInstr size too big: "
131                << Amount << "\n";
132 #endif
133         llvm_unreachable(0);
134       }
135 
136       MachineInstr *New;
137       if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
138         int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
139         New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
140           .addImm(Amount);
141       } else {
142         assert(Old->getOpcode() == XCore::ADJCALLSTACKUP);
143         int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
144         New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
145           .addImm(Amount);
146       }
147 
148       // Replace the pseudo instruction with a new instruction...
149       MBB.insert(I, New);
150     }
151   }
152 
153   MBB.erase(I);
154 }
155 
156 void
157 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
158                                        int SPAdj, unsigned FIOperandNum,
159                                        RegScavenger *RS) const {
160   assert(SPAdj == 0 && "Unexpected");
161   MachineInstr &MI = *II;
162   DebugLoc dl = MI.getDebugLoc();
163   MachineOperand &FrameOp = MI.getOperand(FIOperandNum);
164   int FrameIndex = FrameOp.getIndex();
165 
166   MachineFunction &MF = *MI.getParent()->getParent();
167   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
168   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
169   int StackSize = MF.getFrameInfo()->getStackSize();
170 
171   #ifndef NDEBUG
172   DEBUG(errs() << "\nFunction         : "
173         << MF.getName() << "\n");
174   DEBUG(errs() << "<--------->\n");
175   DEBUG(MI.print(errs()));
176   DEBUG(errs() << "FrameIndex         : " << FrameIndex << "\n");
177   DEBUG(errs() << "FrameOffset        : " << Offset << "\n");
178   DEBUG(errs() << "StackSize          : " << StackSize << "\n");
179   #endif
180 
181   Offset += StackSize;
182 
183   unsigned FrameReg = getFrameRegister(MF);
184 
185   // Special handling of DBG_VALUE instructions.
186   if (MI.isDebugValue()) {
187     MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
188     MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
189     return;
190   }
191 
192   // fold constant into offset.
193   Offset += MI.getOperand(FIOperandNum + 1).getImm();
194   MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
195 
196   assert(Offset%4 == 0 && "Misaligned stack offset");
197 
198   DEBUG(errs() << "Offset             : " << Offset << "\n" << "<--------->\n");
199 
200   Offset/=4;
201 
202   bool FP = TFI->hasFP(MF);
203 
204   unsigned Reg = MI.getOperand(0).getReg();
205   bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
206 
207   assert(XCore::GRRegsRegClass.contains(Reg) && "Unexpected register operand");
208 
209   MachineBasicBlock &MBB = *MI.getParent();
210 
211   if (FP) {
212     bool isUs = isImmUs(Offset);
213 
214     if (!isUs) {
215       if (!RS)
216         report_fatal_error("eliminateFrameIndex Frame size too big: " +
217                            Twine(Offset));
218       unsigned ScratchReg = RS->scavengeRegister(&XCore::GRRegsRegClass, II,
219                                                  SPAdj);
220       loadConstant(MBB, II, ScratchReg, Offset, dl);
221       switch (MI.getOpcode()) {
222       case XCore::LDWFI:
223         BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
224               .addReg(FrameReg)
225               .addReg(ScratchReg, RegState::Kill);
226         break;
227       case XCore::STWFI:
228         BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
229               .addReg(Reg, getKillRegState(isKill))
230               .addReg(FrameReg)
231               .addReg(ScratchReg, RegState::Kill);
232         break;
233       case XCore::LDAWFI:
234         BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
235               .addReg(FrameReg)
236               .addReg(ScratchReg, RegState::Kill);
237         break;
238       default:
239         llvm_unreachable("Unexpected Opcode");
240       }
241     } else {
242       switch (MI.getOpcode()) {
243       case XCore::LDWFI:
244         BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
245               .addReg(FrameReg)
246               .addImm(Offset);
247         break;
248       case XCore::STWFI:
249         BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
250               .addReg(Reg, getKillRegState(isKill))
251               .addReg(FrameReg)
252               .addImm(Offset);
253         break;
254       case XCore::LDAWFI:
255         BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
256               .addReg(FrameReg)
257               .addImm(Offset);
258         break;
259       default:
260         llvm_unreachable("Unexpected Opcode");
261       }
262     }
263   } else {
264     bool isU6 = isImmU6(Offset);
265     if (!isU6 && !isImmU16(Offset))
266       report_fatal_error("eliminateFrameIndex Frame size too big: " +
267                          Twine(Offset));
268 
269     switch (MI.getOpcode()) {
270     int NewOpcode;
271     case XCore::LDWFI:
272       NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
273       BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
274             .addImm(Offset);
275       break;
276     case XCore::STWFI:
277       NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
278       BuildMI(MBB, II, dl, TII.get(NewOpcode))
279             .addReg(Reg, getKillRegState(isKill))
280             .addImm(Offset);
281       break;
282     case XCore::LDAWFI:
283       NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
284       BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
285             .addImm(Offset);
286       break;
287     default:
288       llvm_unreachable("Unexpected Opcode");
289     }
290   }
291   // Erase old instruction.
292   MBB.erase(II);
293 }
294 
295 void XCoreRegisterInfo::
296 loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
297             unsigned DstReg, int64_t Value, DebugLoc dl) const {
298   // TODO use mkmsk if possible.
299   if (!isImmU16(Value)) {
300     // TODO use constant pool.
301     report_fatal_error("loadConstant value too big " + Twine(Value));
302   }
303   int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
304   BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
305 }
306 
307 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
308   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
309 
310   return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
311 }
312