1 //===- XCoreRegisterInfo.cpp - XCore Register Information -------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the XCore implementation of the MRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "XCoreRegisterInfo.h"
15 #include "XCoreMachineFunctionInfo.h"
16 #include "XCore.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/Target/TargetFrameInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Type.h"
29 #include "llvm/Function.h"
30 #include "llvm/ADT/BitVector.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 
36 using namespace llvm;
37 
38 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
39   : XCoreGenRegisterInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
40     TII(tii) {
41 }
42 
43 // helper functions
44 static inline bool isImmUs(unsigned val) {
45   return val <= 11;
46 }
47 
48 static inline bool isImmU6(unsigned val) {
49   return val < (1 << 6);
50 }
51 
52 static inline bool isImmU16(unsigned val) {
53   return val < (1 << 16);
54 }
55 
56 static const unsigned XCore_ArgRegs[] = {
57   XCore::R0, XCore::R1, XCore::R2, XCore::R3
58 };
59 
60 const unsigned * XCoreRegisterInfo::getArgRegs(const MachineFunction *MF)
61 {
62   return XCore_ArgRegs;
63 }
64 
65 unsigned XCoreRegisterInfo::getNumArgRegs(const MachineFunction *MF)
66 {
67   return array_lengthof(XCore_ArgRegs);
68 }
69 
70 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF)
71 {
72   const MachineFrameInfo *MFI = MF.getFrameInfo();
73   MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
74   return (MMI && MMI->hasDebugInfo()) ||
75           !MF.getFunction()->doesNotThrow() ||
76           UnwindTablesMandatory;
77 }
78 
79 const unsigned* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
80                                                                          const {
81   static const unsigned CalleeSavedRegs[] = {
82     XCore::R4, XCore::R5, XCore::R6, XCore::R7,
83     XCore::R8, XCore::R9, XCore::R10, XCore::LR,
84     0
85   };
86   return CalleeSavedRegs;
87 }
88 
89 const TargetRegisterClass* const*
90 XCoreRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
91   static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
92     XCore::GRRegsRegisterClass, XCore::GRRegsRegisterClass,
93     XCore::GRRegsRegisterClass, XCore::GRRegsRegisterClass,
94     XCore::GRRegsRegisterClass, XCore::GRRegsRegisterClass,
95     XCore::GRRegsRegisterClass, XCore::RRegsRegisterClass,
96     0
97   };
98   return CalleeSavedRegClasses;
99 }
100 
101 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
102   BitVector Reserved(getNumRegs());
103   Reserved.set(XCore::CP);
104   Reserved.set(XCore::DP);
105   Reserved.set(XCore::SP);
106   Reserved.set(XCore::LR);
107   if (hasFP(MF)) {
108     Reserved.set(XCore::R10);
109   }
110   return Reserved;
111 }
112 
113 bool
114 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
115   // TODO can we estimate stack size?
116   return hasFP(MF);
117 }
118 
119 bool XCoreRegisterInfo::hasFP(const MachineFunction &MF) const {
120   return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
121 }
122 
123 // This function eliminates ADJCALLSTACKDOWN,
124 // ADJCALLSTACKUP pseudo instructions
125 void XCoreRegisterInfo::
126 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
127                               MachineBasicBlock::iterator I) const {
128   if (!hasReservedCallFrame(MF)) {
129     // Turn the adjcallstackdown instruction into 'extsp <amt>' and the
130     // adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
131     MachineInstr *Old = I;
132     uint64_t Amount = Old->getOperand(0).getImm();
133     if (Amount != 0) {
134       // We need to keep the stack aligned properly.  To do this, we round the
135       // amount of space needed for the outgoing arguments up to the next
136       // alignment boundary.
137       unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
138       Amount = (Amount+Align-1)/Align*Align;
139 
140       assert(Amount%4 == 0);
141       Amount /= 4;
142 
143       bool isU6 = isImmU6(Amount);
144 
145       if (!isU6 && !isImmU16(Amount)) {
146         // FIX could emit multiple instructions in this case.
147 #ifndef NDEBUG
148         errs() << "eliminateCallFramePseudoInstr size too big: "
149                << Amount << "\n";
150 #endif
151         llvm_unreachable(0);
152       }
153 
154       MachineInstr *New;
155       if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
156         int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
157         New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
158           .addImm(Amount);
159       } else {
160         assert(Old->getOpcode() == XCore::ADJCALLSTACKUP);
161         int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
162         New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
163           .addImm(Amount);
164       }
165 
166       // Replace the pseudo instruction with a new instruction...
167       MBB.insert(I, New);
168     }
169   }
170 
171   MBB.erase(I);
172 }
173 
174 unsigned
175 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
176                                        int SPAdj, int *Value,
177                                        RegScavenger *RS) const {
178   assert(SPAdj == 0 && "Unexpected");
179   MachineInstr &MI = *II;
180   DebugLoc dl = MI.getDebugLoc();
181   unsigned i = 0;
182 
183   while (!MI.getOperand(i).isFI()) {
184     ++i;
185     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
186   }
187 
188   MachineOperand &FrameOp = MI.getOperand(i);
189   int FrameIndex = FrameOp.getIndex();
190 
191   MachineFunction &MF = *MI.getParent()->getParent();
192   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
193   int StackSize = MF.getFrameInfo()->getStackSize();
194 
195   #ifndef NDEBUG
196   DEBUG(errs() << "\nFunction         : "
197         << MF.getFunction()->getName() << "\n");
198   DEBUG(errs() << "<--------->\n");
199   DEBUG(MI.print(errs()));
200   DEBUG(errs() << "FrameIndex         : " << FrameIndex << "\n");
201   DEBUG(errs() << "FrameOffset        : " << Offset << "\n");
202   DEBUG(errs() << "StackSize          : " << StackSize << "\n");
203   #endif
204 
205   Offset += StackSize;
206 
207   // fold constant into offset.
208   Offset += MI.getOperand(i + 1).getImm();
209   MI.getOperand(i + 1).ChangeToImmediate(0);
210 
211   assert(Offset%4 == 0 && "Misaligned stack offset");
212 
213   DEBUG(errs() << "Offset             : " << Offset << "\n" << "<--------->\n");
214 
215   Offset/=4;
216 
217   bool FP = hasFP(MF);
218 
219   unsigned Reg = MI.getOperand(0).getReg();
220   bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
221 
222   assert(XCore::GRRegsRegisterClass->contains(Reg) &&
223          "Unexpected register operand");
224 
225   MachineBasicBlock &MBB = *MI.getParent();
226 
227   if (FP) {
228     bool isUs = isImmUs(Offset);
229     unsigned FramePtr = XCore::R10;
230 
231     if (!isUs) {
232       if (!RS) {
233         std::string msg;
234         raw_string_ostream Msg(msg);
235         Msg << "eliminateFrameIndex Frame size too big: " << Offset;
236         llvm_report_error(Msg.str());
237       }
238       unsigned ScratchReg = RS->scavengeRegister(XCore::GRRegsRegisterClass, II,
239                                                  SPAdj);
240       loadConstant(MBB, II, ScratchReg, Offset, dl);
241       switch (MI.getOpcode()) {
242       case XCore::LDWFI:
243         BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
244               .addReg(FramePtr)
245               .addReg(ScratchReg, RegState::Kill);
246         break;
247       case XCore::STWFI:
248         BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
249               .addReg(Reg, getKillRegState(isKill))
250               .addReg(FramePtr)
251               .addReg(ScratchReg, RegState::Kill);
252         break;
253       case XCore::LDAWFI:
254         BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
255               .addReg(FramePtr)
256               .addReg(ScratchReg, RegState::Kill);
257         break;
258       default:
259         llvm_unreachable("Unexpected Opcode");
260       }
261     } else {
262       switch (MI.getOpcode()) {
263       case XCore::LDWFI:
264         BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
265               .addReg(FramePtr)
266               .addImm(Offset);
267         break;
268       case XCore::STWFI:
269         BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
270               .addReg(Reg, getKillRegState(isKill))
271               .addReg(FramePtr)
272               .addImm(Offset);
273         break;
274       case XCore::LDAWFI:
275         BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
276               .addReg(FramePtr)
277               .addImm(Offset);
278         break;
279       default:
280         llvm_unreachable("Unexpected Opcode");
281       }
282     }
283   } else {
284     bool isU6 = isImmU6(Offset);
285     if (!isU6 && !isImmU16(Offset)) {
286       std::string msg;
287       raw_string_ostream Msg(msg);
288       Msg << "eliminateFrameIndex Frame size too big: " << Offset;
289       llvm_report_error(Msg.str());
290     }
291 
292     switch (MI.getOpcode()) {
293     int NewOpcode;
294     case XCore::LDWFI:
295       NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
296       BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
297             .addImm(Offset);
298       break;
299     case XCore::STWFI:
300       NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
301       BuildMI(MBB, II, dl, TII.get(NewOpcode))
302             .addReg(Reg, getKillRegState(isKill))
303             .addImm(Offset);
304       break;
305     case XCore::LDAWFI:
306       NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
307       BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
308             .addImm(Offset);
309       break;
310     default:
311       llvm_unreachable("Unexpected Opcode");
312     }
313   }
314   // Erase old instruction.
315   MBB.erase(II);
316   return 0;
317 }
318 
319 void
320 XCoreRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
321                                                       RegScavenger *RS) const {
322   MachineFrameInfo *MFI = MF.getFrameInfo();
323   bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR);
324   const TargetRegisterClass *RC = XCore::GRRegsRegisterClass;
325   XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
326   if (LRUsed) {
327     MF.getRegInfo().setPhysRegUnused(XCore::LR);
328 
329     bool isVarArg = MF.getFunction()->isVarArg();
330     int FrameIdx;
331     if (! isVarArg) {
332       // A fixed offset of 0 allows us to save / restore LR using entsp / retsp.
333       FrameIdx = MFI->CreateFixedObject(RC->getSize(), 0, true, false);
334     } else {
335       FrameIdx = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(),
336                                         false);
337     }
338     XFI->setUsesLR(FrameIdx);
339     XFI->setLRSpillSlot(FrameIdx);
340   }
341   if (requiresRegisterScavenging(MF)) {
342     // Reserve a slot close to SP or frame pointer.
343     RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
344                                                        RC->getAlignment(),
345                                                        false));
346   }
347   if (hasFP(MF)) {
348     // A callee save register is used to hold the FP.
349     // This needs saving / restoring in the epilogue / prologue.
350     XFI->setFPSpillSlot(MFI->CreateStackObject(RC->getSize(),
351                                                RC->getAlignment(),
352                                                false));
353   }
354 }
355 
356 void XCoreRegisterInfo::
357 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
358 
359 }
360 
361 void XCoreRegisterInfo::
362 loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
363             unsigned DstReg, int64_t Value, DebugLoc dl) const {
364   // TODO use mkmsk if possible.
365   if (!isImmU16(Value)) {
366     // TODO use constant pool.
367     std::string msg;
368     raw_string_ostream Msg(msg);
369     Msg << "loadConstant value too big " << Value;
370     llvm_report_error(Msg.str());
371   }
372   int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
373   BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
374 }
375 
376 void XCoreRegisterInfo::
377 storeToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
378                   unsigned SrcReg, int Offset, DebugLoc dl) const {
379   assert(Offset%4 == 0 && "Misaligned stack offset");
380   Offset/=4;
381   bool isU6 = isImmU6(Offset);
382   if (!isU6 && !isImmU16(Offset)) {
383     std::string msg;
384     raw_string_ostream Msg(msg);
385     Msg << "storeToStack offset too big " << Offset;
386     llvm_report_error(Msg.str());
387   }
388   int Opcode = isU6 ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
389   BuildMI(MBB, I, dl, TII.get(Opcode))
390     .addReg(SrcReg)
391     .addImm(Offset);
392 }
393 
394 void XCoreRegisterInfo::
395 loadFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
396                   unsigned DstReg, int Offset, DebugLoc dl) const {
397   assert(Offset%4 == 0 && "Misaligned stack offset");
398   Offset/=4;
399   bool isU6 = isImmU6(Offset);
400   if (!isU6 && !isImmU16(Offset)) {
401     std::string msg;
402     raw_string_ostream Msg(msg);
403     Msg << "loadFromStack offset too big " << Offset;
404     llvm_report_error(Msg.str());
405   }
406   int Opcode = isU6 ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
407   BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
408     .addImm(Offset);
409 }
410 
411 void XCoreRegisterInfo::emitPrologue(MachineFunction &MF) const {
412   MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
413   MachineBasicBlock::iterator MBBI = MBB.begin();
414   MachineFrameInfo *MFI = MF.getFrameInfo();
415   MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
416   XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
417   DebugLoc dl = (MBBI != MBB.end() ?
418                  MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
419 
420   bool FP = hasFP(MF);
421 
422   // Work out frame sizes.
423   int FrameSize = MFI->getStackSize();
424 
425   assert(FrameSize%4 == 0 && "Misaligned frame size");
426 
427   FrameSize/=4;
428 
429   bool isU6 = isImmU6(FrameSize);
430 
431   if (!isU6 && !isImmU16(FrameSize)) {
432     // FIXME could emit multiple instructions.
433     std::string msg;
434     raw_string_ostream Msg(msg);
435     Msg << "emitPrologue Frame size too big: " << FrameSize;
436     llvm_report_error(Msg.str());
437   }
438   bool emitFrameMoves = needsFrameMoves(MF);
439 
440   // Do we need to allocate space on the stack?
441   if (FrameSize) {
442     bool saveLR = XFI->getUsesLR();
443     bool LRSavedOnEntry = false;
444     int Opcode;
445     if (saveLR && (MFI->getObjectOffset(XFI->getLRSpillSlot()) == 0)) {
446       Opcode = (isU6) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
447       MBB.addLiveIn(XCore::LR);
448       saveLR = false;
449       LRSavedOnEntry = true;
450     } else {
451       Opcode = (isU6) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
452     }
453     BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
454 
455     if (emitFrameMoves) {
456       std::vector<MachineMove> &Moves = MMI->getFrameMoves();
457 
458       // Show update of SP.
459       unsigned FrameLabelId = MMI->NextLabelID();
460       BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addImm(FrameLabelId);
461 
462       MachineLocation SPDst(MachineLocation::VirtualFP);
463       MachineLocation SPSrc(MachineLocation::VirtualFP, -FrameSize * 4);
464       Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
465 
466       if (LRSavedOnEntry) {
467         MachineLocation CSDst(MachineLocation::VirtualFP, 0);
468         MachineLocation CSSrc(XCore::LR);
469         Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
470       }
471     }
472     if (saveLR) {
473       int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot());
474       storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4, dl);
475       MBB.addLiveIn(XCore::LR);
476 
477       if (emitFrameMoves) {
478         unsigned SaveLRLabelId = MMI->NextLabelID();
479         BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addImm(SaveLRLabelId);
480         MachineLocation CSDst(MachineLocation::VirtualFP, LRSpillOffset);
481         MachineLocation CSSrc(XCore::LR);
482         MMI->getFrameMoves().push_back(MachineMove(SaveLRLabelId,
483                                                    CSDst, CSSrc));
484       }
485     }
486   }
487 
488   if (FP) {
489     // Save R10 to the stack.
490     int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot());
491     storeToStack(MBB, MBBI, XCore::R10, FPSpillOffset + FrameSize*4, dl);
492     // R10 is live-in. It is killed at the spill.
493     MBB.addLiveIn(XCore::R10);
494     if (emitFrameMoves) {
495       unsigned SaveR10LabelId = MMI->NextLabelID();
496       BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addImm(SaveR10LabelId);
497       MachineLocation CSDst(MachineLocation::VirtualFP, FPSpillOffset);
498       MachineLocation CSSrc(XCore::R10);
499       MMI->getFrameMoves().push_back(MachineMove(SaveR10LabelId,
500                                                  CSDst, CSSrc));
501     }
502     // Set the FP from the SP.
503     unsigned FramePtr = XCore::R10;
504     BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr)
505       .addImm(0);
506     if (emitFrameMoves) {
507       // Show FP is now valid.
508       unsigned FrameLabelId = MMI->NextLabelID();
509       BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addImm(FrameLabelId);
510       MachineLocation SPDst(FramePtr);
511       MachineLocation SPSrc(MachineLocation::VirtualFP);
512       MMI->getFrameMoves().push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
513     }
514   }
515 
516   if (emitFrameMoves) {
517     // Frame moves for callee saved.
518     std::vector<MachineMove> &Moves = MMI->getFrameMoves();
519     std::vector<std::pair<unsigned, CalleeSavedInfo> >&SpillLabels =
520         XFI->getSpillLabels();
521     for (unsigned I = 0, E = SpillLabels.size(); I != E; ++I) {
522       unsigned SpillLabel = SpillLabels[I].first;
523       CalleeSavedInfo &CSI = SpillLabels[I].second;
524       int Offset = MFI->getObjectOffset(CSI.getFrameIdx());
525       unsigned Reg = CSI.getReg();
526       MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
527       MachineLocation CSSrc(Reg);
528       Moves.push_back(MachineMove(SpillLabel, CSDst, CSSrc));
529     }
530   }
531 }
532 
533 void XCoreRegisterInfo::emitEpilogue(MachineFunction &MF,
534                                      MachineBasicBlock &MBB) const {
535   MachineFrameInfo *MFI            = MF.getFrameInfo();
536   MachineBasicBlock::iterator MBBI = prior(MBB.end());
537   DebugLoc dl = MBBI->getDebugLoc();
538 
539   bool FP = hasFP(MF);
540 
541   if (FP) {
542     // Restore the stack pointer.
543     unsigned FramePtr = XCore::R10;
544     BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r))
545       .addReg(FramePtr);
546   }
547 
548   // Work out frame sizes.
549   int FrameSize = MFI->getStackSize();
550 
551   assert(FrameSize%4 == 0 && "Misaligned frame size");
552 
553   FrameSize/=4;
554 
555   bool isU6 = isImmU6(FrameSize);
556 
557   if (!isU6 && !isImmU16(FrameSize)) {
558     // FIXME could emit multiple instructions.
559     std::string msg;
560     raw_string_ostream Msg(msg);
561     Msg << "emitEpilogue Frame size too big: " << FrameSize;
562     llvm_report_error(Msg.str());
563   }
564 
565   if (FrameSize) {
566     XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
567 
568     if (FP) {
569       // Restore R10
570       int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot());
571       FPSpillOffset += FrameSize*4;
572       loadFromStack(MBB, MBBI, XCore::R10, FPSpillOffset, dl);
573     }
574     bool restoreLR = XFI->getUsesLR();
575     if (restoreLR && MFI->getObjectOffset(XFI->getLRSpillSlot()) != 0) {
576       int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot());
577       LRSpillOffset += FrameSize*4;
578       loadFromStack(MBB, MBBI, XCore::LR, LRSpillOffset, dl);
579       restoreLR = false;
580     }
581     if (restoreLR) {
582       // Fold prologue into return instruction
583       assert(MBBI->getOpcode() == XCore::RETSP_u6
584         || MBBI->getOpcode() == XCore::RETSP_lu6);
585       int Opcode = (isU6) ? XCore::RETSP_u6 : XCore::RETSP_lu6;
586       BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
587       MBB.erase(MBBI);
588     } else {
589       int Opcode = (isU6) ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
590       BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(FrameSize);
591     }
592   }
593 }
594 
595 int XCoreRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
596   return XCoreGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
597 }
598 
599 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
600   bool FP = hasFP(MF);
601 
602   return FP ? XCore::R10 : XCore::SP;
603 }
604 
605 unsigned XCoreRegisterInfo::getRARegister() const {
606   return XCore::LR;
607 }
608 
609 void XCoreRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
610                                                                          const {
611   // Initial state of the frame pointer is SP.
612   MachineLocation Dst(MachineLocation::VirtualFP);
613   MachineLocation Src(XCore::SP, 0);
614   Moves.push_back(MachineMove(0, Dst, Src));
615 }
616 
617 #include "XCoreGenRegisterInfo.inc"
618 
619