1 //===-- XCoreRegisterInfo.cpp - XCore Register Information ----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the XCore implementation of the MRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "XCoreRegisterInfo.h"
15 #include "XCoreMachineFunctionInfo.h"
16 #include "XCore.h"
17 #include "llvm/Type.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineModuleInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/Target/TargetFrameLowering.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/STLExtras.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 
35 #define GET_REGINFO_TARGET_DESC
36 #include "XCoreGenRegisterInfo.inc"
37 
38 using namespace llvm;
39 
40 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
41   : XCoreGenRegisterInfo(XCore::LR), TII(tii) {
42 }
43 
44 // helper functions
45 static inline bool isImmUs(unsigned val) {
46   return val <= 11;
47 }
48 
49 static inline bool isImmU6(unsigned val) {
50   return val < (1 << 6);
51 }
52 
53 static inline bool isImmU16(unsigned val) {
54   return val < (1 << 16);
55 }
56 
57 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
58   return MF.getMMI().hasDebugInfo() ||
59     MF.getFunction()->needsUnwindTableEntry();
60 }
61 
62 const uint16_t* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
63                                                                          const {
64   static const uint16_t CalleeSavedRegs[] = {
65     XCore::R4, XCore::R5, XCore::R6, XCore::R7,
66     XCore::R8, XCore::R9, XCore::R10, XCore::LR,
67     0
68   };
69   return CalleeSavedRegs;
70 }
71 
72 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
73   BitVector Reserved(getNumRegs());
74   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
75 
76   Reserved.set(XCore::CP);
77   Reserved.set(XCore::DP);
78   Reserved.set(XCore::SP);
79   Reserved.set(XCore::LR);
80   if (TFI->hasFP(MF)) {
81     Reserved.set(XCore::R10);
82   }
83   return Reserved;
84 }
85 
86 bool
87 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
88   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
89 
90   // TODO can we estimate stack size?
91   return TFI->hasFP(MF);
92 }
93 
94 bool
95 XCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
96   return false;
97 }
98 
99 // This function eliminates ADJCALLSTACKDOWN,
100 // ADJCALLSTACKUP pseudo instructions
101 void XCoreRegisterInfo::
102 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
103                               MachineBasicBlock::iterator I) const {
104   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
105 
106   if (!TFI->hasReservedCallFrame(MF)) {
107     // Turn the adjcallstackdown instruction into 'extsp <amt>' and the
108     // adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
109     MachineInstr *Old = I;
110     uint64_t Amount = Old->getOperand(0).getImm();
111     if (Amount != 0) {
112       // We need to keep the stack aligned properly.  To do this, we round the
113       // amount of space needed for the outgoing arguments up to the next
114       // alignment boundary.
115       unsigned Align = TFI->getStackAlignment();
116       Amount = (Amount+Align-1)/Align*Align;
117 
118       assert(Amount%4 == 0);
119       Amount /= 4;
120 
121       bool isU6 = isImmU6(Amount);
122       if (!isU6 && !isImmU16(Amount)) {
123         // FIX could emit multiple instructions in this case.
124 #ifndef NDEBUG
125         errs() << "eliminateCallFramePseudoInstr size too big: "
126                << Amount << "\n";
127 #endif
128         llvm_unreachable(0);
129       }
130 
131       MachineInstr *New;
132       if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
133         int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
134         New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
135           .addImm(Amount);
136       } else {
137         assert(Old->getOpcode() == XCore::ADJCALLSTACKUP);
138         int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
139         New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
140           .addImm(Amount);
141       }
142 
143       // Replace the pseudo instruction with a new instruction...
144       MBB.insert(I, New);
145     }
146   }
147 
148   MBB.erase(I);
149 }
150 
151 void
152 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
153                                        int SPAdj, RegScavenger *RS) const {
154   assert(SPAdj == 0 && "Unexpected");
155   MachineInstr &MI = *II;
156   DebugLoc dl = MI.getDebugLoc();
157   unsigned i = 0;
158 
159   while (!MI.getOperand(i).isFI()) {
160     ++i;
161     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
162   }
163 
164   MachineOperand &FrameOp = MI.getOperand(i);
165   int FrameIndex = FrameOp.getIndex();
166 
167   MachineFunction &MF = *MI.getParent()->getParent();
168   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
169   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
170   int StackSize = MF.getFrameInfo()->getStackSize();
171 
172   #ifndef NDEBUG
173   DEBUG(errs() << "\nFunction         : "
174         << MF.getFunction()->getName() << "\n");
175   DEBUG(errs() << "<--------->\n");
176   DEBUG(MI.print(errs()));
177   DEBUG(errs() << "FrameIndex         : " << FrameIndex << "\n");
178   DEBUG(errs() << "FrameOffset        : " << Offset << "\n");
179   DEBUG(errs() << "StackSize          : " << StackSize << "\n");
180   #endif
181 
182   Offset += StackSize;
183 
184   unsigned FrameReg = getFrameRegister(MF);
185 
186   // Special handling of DBG_VALUE instructions.
187   if (MI.isDebugValue()) {
188     MI.getOperand(i).ChangeToRegister(FrameReg, false /*isDef*/);
189     MI.getOperand(i+1).ChangeToImmediate(Offset);
190     return;
191   }
192 
193   // fold constant into offset.
194   Offset += MI.getOperand(i + 1).getImm();
195   MI.getOperand(i + 1).ChangeToImmediate(0);
196 
197   assert(Offset%4 == 0 && "Misaligned stack offset");
198 
199   DEBUG(errs() << "Offset             : " << Offset << "\n" << "<--------->\n");
200 
201   Offset/=4;
202 
203   bool FP = TFI->hasFP(MF);
204 
205   unsigned Reg = MI.getOperand(0).getReg();
206   bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
207 
208   assert(XCore::GRRegsRegisterClass->contains(Reg) &&
209          "Unexpected register operand");
210 
211   MachineBasicBlock &MBB = *MI.getParent();
212 
213   if (FP) {
214     bool isUs = isImmUs(Offset);
215 
216     if (!isUs) {
217       if (!RS)
218         report_fatal_error("eliminateFrameIndex Frame size too big: " +
219                            Twine(Offset));
220       unsigned ScratchReg = RS->scavengeRegister(XCore::GRRegsRegisterClass, II,
221                                                  SPAdj);
222       loadConstant(MBB, II, ScratchReg, Offset, dl);
223       switch (MI.getOpcode()) {
224       case XCore::LDWFI:
225         BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
226               .addReg(FrameReg)
227               .addReg(ScratchReg, RegState::Kill);
228         break;
229       case XCore::STWFI:
230         BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
231               .addReg(Reg, getKillRegState(isKill))
232               .addReg(FrameReg)
233               .addReg(ScratchReg, RegState::Kill);
234         break;
235       case XCore::LDAWFI:
236         BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
237               .addReg(FrameReg)
238               .addReg(ScratchReg, RegState::Kill);
239         break;
240       default:
241         llvm_unreachable("Unexpected Opcode");
242       }
243     } else {
244       switch (MI.getOpcode()) {
245       case XCore::LDWFI:
246         BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
247               .addReg(FrameReg)
248               .addImm(Offset);
249         break;
250       case XCore::STWFI:
251         BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
252               .addReg(Reg, getKillRegState(isKill))
253               .addReg(FrameReg)
254               .addImm(Offset);
255         break;
256       case XCore::LDAWFI:
257         BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
258               .addReg(FrameReg)
259               .addImm(Offset);
260         break;
261       default:
262         llvm_unreachable("Unexpected Opcode");
263       }
264     }
265   } else {
266     bool isU6 = isImmU6(Offset);
267     if (!isU6 && !isImmU16(Offset))
268       report_fatal_error("eliminateFrameIndex Frame size too big: " +
269                          Twine(Offset));
270 
271     switch (MI.getOpcode()) {
272     int NewOpcode;
273     case XCore::LDWFI:
274       NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
275       BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
276             .addImm(Offset);
277       break;
278     case XCore::STWFI:
279       NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
280       BuildMI(MBB, II, dl, TII.get(NewOpcode))
281             .addReg(Reg, getKillRegState(isKill))
282             .addImm(Offset);
283       break;
284     case XCore::LDAWFI:
285       NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
286       BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
287             .addImm(Offset);
288       break;
289     default:
290       llvm_unreachable("Unexpected Opcode");
291     }
292   }
293   // Erase old instruction.
294   MBB.erase(II);
295 }
296 
297 void XCoreRegisterInfo::
298 loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
299             unsigned DstReg, int64_t Value, DebugLoc dl) const {
300   // TODO use mkmsk if possible.
301   if (!isImmU16(Value)) {
302     // TODO use constant pool.
303     report_fatal_error("loadConstant value too big " + Twine(Value));
304   }
305   int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
306   BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
307 }
308 
309 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
310   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
311 
312   return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
313 }
314