1 //===-- XCoreRegisterInfo.cpp - XCore Register Information ----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the XCore implementation of the MRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "XCoreRegisterInfo.h"
15 #include "XCore.h"
16 #include "XCoreInstrInfo.h"
17 #include "XCoreMachineFunctionInfo.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/RegisterScavenging.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/Type.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Target/TargetFrameLowering.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Target/TargetOptions.h"
35 
36 #define GET_REGINFO_TARGET_DESC
37 #include "XCoreGenRegisterInfo.inc"
38 
39 using namespace llvm;
40 
41 XCoreRegisterInfo::XCoreRegisterInfo()
42   : XCoreGenRegisterInfo(XCore::LR) {
43 }
44 
45 // helper functions
46 static inline bool isImmUs(unsigned val) {
47   return val <= 11;
48 }
49 
50 static inline bool isImmU6(unsigned val) {
51   return val < (1 << 6);
52 }
53 
54 static inline bool isImmU16(unsigned val) {
55   return val < (1 << 16);
56 }
57 
58 
59 static void InsertFPImmInst(MachineBasicBlock::iterator II,
60                             const XCoreInstrInfo &TII,
61                             unsigned Reg, unsigned FrameReg, int Offset ) {
62   MachineInstr &MI = *II;
63   MachineBasicBlock &MBB = *MI.getParent();
64   DebugLoc dl = MI.getDebugLoc();
65 
66   switch (MI.getOpcode()) {
67   case XCore::LDWFI:
68     BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
69           .addReg(FrameReg)
70           .addImm(Offset);
71     break;
72   case XCore::STWFI:
73     BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
74           .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
75           .addReg(FrameReg)
76           .addImm(Offset);
77     break;
78   case XCore::LDAWFI:
79     BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
80           .addReg(FrameReg)
81           .addImm(Offset);
82     break;
83   default:
84     llvm_unreachable("Unexpected Opcode");
85   }
86 }
87 
88 static void InsertFPConstInst(MachineBasicBlock::iterator II,
89                               const XCoreInstrInfo &TII,
90                               unsigned Reg, unsigned FrameReg,
91                               int Offset, RegScavenger *RS ) {
92   assert(RS && "requiresRegisterScavenging failed");
93   MachineInstr &MI = *II;
94   MachineBasicBlock &MBB = *MI.getParent();
95   DebugLoc dl = MI.getDebugLoc();
96 
97   unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
98   RS->setUsed(ScratchOffset);
99   TII.loadImmediate(MBB, II, ScratchOffset, Offset);
100 
101   switch (MI.getOpcode()) {
102   case XCore::LDWFI:
103     BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
104           .addReg(FrameReg)
105           .addReg(ScratchOffset, RegState::Kill);
106     break;
107   case XCore::STWFI:
108     BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
109           .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
110           .addReg(FrameReg)
111           .addReg(ScratchOffset, RegState::Kill);
112     break;
113   case XCore::LDAWFI:
114     BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
115           .addReg(FrameReg)
116           .addReg(ScratchOffset, RegState::Kill);
117     break;
118   default:
119     llvm_unreachable("Unexpected Opcode");
120   }
121 }
122 
123 static void InsertSPImmInst(MachineBasicBlock::iterator II,
124                             const XCoreInstrInfo &TII,
125                             unsigned Reg, int Offset) {
126   MachineInstr &MI = *II;
127   MachineBasicBlock &MBB = *MI.getParent();
128   DebugLoc dl = MI.getDebugLoc();
129   bool isU6 = isImmU6(Offset);
130   switch (MI.getOpcode()) {
131   int NewOpcode;
132   case XCore::LDWFI:
133     NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
134     BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
135           .addImm(Offset);
136     break;
137   case XCore::STWFI:
138     NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
139     BuildMI(MBB, II, dl, TII.get(NewOpcode))
140           .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
141           .addImm(Offset);
142     break;
143   case XCore::LDAWFI:
144     NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
145     BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
146           .addImm(Offset);
147     break;
148   default:
149     llvm_unreachable("Unexpected Opcode");
150   }
151 }
152 
153 static void InsertSPConstInst(MachineBasicBlock::iterator II,
154                                 const XCoreInstrInfo &TII,
155                                 unsigned Reg, int Offset, RegScavenger *RS ) {
156   assert(RS && "requiresRegisterScavenging failed");
157   MachineInstr &MI = *II;
158   MachineBasicBlock &MBB = *MI.getParent();
159   DebugLoc dl = MI.getDebugLoc();
160   unsigned OpCode = MI.getOpcode();
161 
162   unsigned ScratchBase;
163   if (OpCode==XCore::STWFI) {
164     ScratchBase = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
165     RS->setUsed(ScratchBase);
166   } else
167     ScratchBase = Reg;
168   BuildMI(MBB, II, dl, TII.get(XCore::LDAWSP_ru6), ScratchBase).addImm(0);
169   unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
170   RS->setUsed(ScratchOffset);
171   TII.loadImmediate(MBB, II, ScratchOffset, Offset);
172 
173   switch (OpCode) {
174   case XCore::LDWFI:
175     BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
176           .addReg(ScratchBase, RegState::Kill)
177           .addReg(ScratchOffset, RegState::Kill);
178     break;
179   case XCore::STWFI:
180     BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
181           .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
182           .addReg(ScratchBase, RegState::Kill)
183           .addReg(ScratchOffset, RegState::Kill);
184     break;
185   case XCore::LDAWFI:
186     BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
187           .addReg(ScratchBase, RegState::Kill)
188           .addReg(ScratchOffset, RegState::Kill);
189     break;
190   default:
191     llvm_unreachable("Unexpected Opcode");
192   }
193 }
194 
195 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
196   return MF.getMMI().hasDebugInfo() ||
197     MF.getFunction()->needsUnwindTableEntry();
198 }
199 
200 const uint16_t* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
201                                                                          const {
202   // The callee saved registers LR & FP are explicitly handled during
203   // emitPrologue & emitEpilogue and releated functions.
204   static const uint16_t CalleeSavedRegs[] = {
205     XCore::R4, XCore::R5, XCore::R6, XCore::R7,
206     XCore::R8, XCore::R9, XCore::R10,
207     0
208   };
209   static const uint16_t CalleeSavedRegsFP[] = {
210     XCore::R4, XCore::R5, XCore::R6, XCore::R7,
211     XCore::R8, XCore::R9,
212     0
213   };
214   const TargetFrameLowering *TFI = MF->getTarget().getFrameLowering();
215   if (TFI->hasFP(*MF))
216     return CalleeSavedRegsFP;
217   return CalleeSavedRegs;
218 }
219 
220 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
221   BitVector Reserved(getNumRegs());
222   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
223 
224   Reserved.set(XCore::CP);
225   Reserved.set(XCore::DP);
226   Reserved.set(XCore::SP);
227   Reserved.set(XCore::LR);
228   if (TFI->hasFP(MF)) {
229     Reserved.set(XCore::R10);
230   }
231   return Reserved;
232 }
233 
234 bool
235 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
236   return true;
237 }
238 
239 bool
240 XCoreRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
241   return true;
242 }
243 
244 bool
245 XCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
246   return false;
247 }
248 
249 void
250 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
251                                        int SPAdj, unsigned FIOperandNum,
252                                        RegScavenger *RS) const {
253   assert(SPAdj == 0 && "Unexpected");
254   MachineInstr &MI = *II;
255   MachineOperand &FrameOp = MI.getOperand(FIOperandNum);
256   int FrameIndex = FrameOp.getIndex();
257 
258   MachineFunction &MF = *MI.getParent()->getParent();
259   const XCoreInstrInfo &TII =
260           *static_cast<const XCoreInstrInfo*>(MF.getTarget().getInstrInfo());
261 
262   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
263   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
264   int StackSize = MF.getFrameInfo()->getStackSize();
265 
266   #ifndef NDEBUG
267   DEBUG(errs() << "\nFunction         : "
268         << MF.getName() << "\n");
269   DEBUG(errs() << "<--------->\n");
270   DEBUG(MI.print(errs()));
271   DEBUG(errs() << "FrameIndex         : " << FrameIndex << "\n");
272   DEBUG(errs() << "FrameOffset        : " << Offset << "\n");
273   DEBUG(errs() << "StackSize          : " << StackSize << "\n");
274   #endif
275 
276   Offset += StackSize;
277 
278   unsigned FrameReg = getFrameRegister(MF);
279 
280   // Special handling of DBG_VALUE instructions.
281   if (MI.isDebugValue()) {
282     MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
283     MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
284     return;
285   }
286 
287   // fold constant into offset.
288   Offset += MI.getOperand(FIOperandNum + 1).getImm();
289   MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
290 
291   assert(Offset%4 == 0 && "Misaligned stack offset");
292   DEBUG(errs() << "Offset             : " << Offset << "\n" << "<--------->\n");
293   Offset/=4;
294 
295   unsigned Reg = MI.getOperand(0).getReg();
296   assert(XCore::GRRegsRegClass.contains(Reg) && "Unexpected register operand");
297 
298   if (TFI->hasFP(MF)) {
299     if (isImmUs(Offset))
300       InsertFPImmInst(II, TII, Reg, FrameReg, Offset);
301     else
302       InsertFPConstInst(II, TII, Reg, FrameReg, Offset, RS);
303   } else {
304     if (isImmU16(Offset))
305       InsertSPImmInst(II, TII, Reg, Offset);
306     else
307       InsertSPConstInst(II, TII, Reg, Offset, RS);
308   }
309   // Erase old instruction.
310   MachineBasicBlock &MBB = *MI.getParent();
311   MBB.erase(II);
312 }
313 
314 
315 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
316   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
317 
318   return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
319 }
320