1 //===-- XCoreISelDAGToDAG.cpp - A dag to dag inst selector for XCore ------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines an instruction selector for the XCore target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "XCore.h"
15 #include "XCoreTargetMachine.h"
16 #include "llvm/DerivedTypes.h"
17 #include "llvm/Function.h"
18 #include "llvm/Intrinsics.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/LLVMContext.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include <queue>
34 #include <set>
35 using namespace llvm;
36 
37 /// XCoreDAGToDAGISel - XCore specific code to select XCore machine
38 /// instructions for SelectionDAG operations.
39 ///
40 namespace {
41   class XCoreDAGToDAGISel : public SelectionDAGISel {
42     const XCoreTargetLowering &Lowering;
43     const XCoreSubtarget &Subtarget;
44 
45   public:
46     XCoreDAGToDAGISel(XCoreTargetMachine &TM)
47       : SelectionDAGISel(TM),
48         Lowering(*TM.getTargetLowering()),
49         Subtarget(*TM.getSubtargetImpl()) { }
50 
51     SDNode *Select(SDNode *N);
52     SDNode *SelectBRIND(SDNode *N);
53 
54     /// getI32Imm - Return a target constant with the specified value, of type
55     /// i32.
56     inline SDValue getI32Imm(unsigned Imm) {
57       return CurDAG->getTargetConstant(Imm, MVT::i32);
58     }
59 
60     inline bool immMskBitp(SDNode *inN) const {
61       ConstantSDNode *N = cast<ConstantSDNode>(inN);
62       uint32_t value = (uint32_t)N->getZExtValue();
63       if (!isMask_32(value)) {
64         return false;
65       }
66       int msksize = 32 - CountLeadingZeros_32(value);
67       return (msksize >= 1 && msksize <= 8) ||
68               msksize == 16 || msksize == 24 || msksize == 32;
69     }
70 
71     // Complex Pattern Selectors.
72     bool SelectADDRspii(SDValue Addr, SDValue &Base, SDValue &Offset);
73     bool SelectADDRdpii(SDValue Addr, SDValue &Base, SDValue &Offset);
74     bool SelectADDRcpii(SDValue Addr, SDValue &Base, SDValue &Offset);
75 
76     virtual const char *getPassName() const {
77       return "XCore DAG->DAG Pattern Instruction Selection";
78     }
79 
80     // Include the pieces autogenerated from the target description.
81   #include "XCoreGenDAGISel.inc"
82   };
83 }  // end anonymous namespace
84 
85 /// createXCoreISelDag - This pass converts a legalized DAG into a
86 /// XCore-specific DAG, ready for instruction scheduling.
87 ///
88 FunctionPass *llvm::createXCoreISelDag(XCoreTargetMachine &TM) {
89   return new XCoreDAGToDAGISel(TM);
90 }
91 
92 bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Addr, SDValue &Base,
93                                        SDValue &Offset) {
94   FrameIndexSDNode *FIN = 0;
95   if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) {
96     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
97     Offset = CurDAG->getTargetConstant(0, MVT::i32);
98     return true;
99   }
100   if (Addr.getOpcode() == ISD::ADD) {
101     ConstantSDNode *CN = 0;
102     if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
103       && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
104       && (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {
105       // Constant positive word offset from frame index
106       Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
107       Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
108       return true;
109     }
110   }
111   return false;
112 }
113 
114 bool XCoreDAGToDAGISel::SelectADDRdpii(SDValue Addr, SDValue &Base,
115                                        SDValue &Offset) {
116   if (Addr.getOpcode() == XCoreISD::DPRelativeWrapper) {
117     Base = Addr.getOperand(0);
118     Offset = CurDAG->getTargetConstant(0, MVT::i32);
119     return true;
120   }
121   if (Addr.getOpcode() == ISD::ADD) {
122     ConstantSDNode *CN = 0;
123     if ((Addr.getOperand(0).getOpcode() == XCoreISD::DPRelativeWrapper)
124       && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
125       && (CN->getSExtValue() % 4 == 0)) {
126       // Constant word offset from a object in the data region
127       Base = Addr.getOperand(0).getOperand(0);
128       Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
129       return true;
130     }
131   }
132   return false;
133 }
134 
135 bool XCoreDAGToDAGISel::SelectADDRcpii(SDValue Addr, SDValue &Base,
136                                        SDValue &Offset) {
137   if (Addr.getOpcode() == XCoreISD::CPRelativeWrapper) {
138     Base = Addr.getOperand(0);
139     Offset = CurDAG->getTargetConstant(0, MVT::i32);
140     return true;
141   }
142   if (Addr.getOpcode() == ISD::ADD) {
143     ConstantSDNode *CN = 0;
144     if ((Addr.getOperand(0).getOpcode() == XCoreISD::CPRelativeWrapper)
145       && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
146       && (CN->getSExtValue() % 4 == 0)) {
147       // Constant word offset from a object in the data region
148       Base = Addr.getOperand(0).getOperand(0);
149       Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
150       return true;
151     }
152   }
153   return false;
154 }
155 
156 SDNode *XCoreDAGToDAGISel::Select(SDNode *N) {
157   DebugLoc dl = N->getDebugLoc();
158   switch (N->getOpcode()) {
159   default: break;
160   case ISD::Constant: {
161     uint64_t Val = cast<ConstantSDNode>(N)->getZExtValue();
162     if (immMskBitp(N)) {
163       // Transformation function: get the size of a mask
164       // Look for the first non-zero bit
165       SDValue MskSize = getI32Imm(32 - CountLeadingZeros_32(Val));
166       return CurDAG->getMachineNode(XCore::MKMSK_rus, dl,
167                                     MVT::i32, MskSize);
168     }
169     else if (!isUInt<16>(Val)) {
170       SDValue CPIdx =
171         CurDAG->getTargetConstantPool(ConstantInt::get(
172                               Type::getInt32Ty(*CurDAG->getContext()), Val),
173                                       TLI.getPointerTy());
174       return CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32,
175                                     MVT::Other, CPIdx,
176                                     CurDAG->getEntryNode());
177     }
178     break;
179   }
180   case XCoreISD::LADD: {
181     SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
182                         N->getOperand(2) };
183     return CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32,
184                                   Ops, 3);
185   }
186   case XCoreISD::LSUB: {
187     SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
188                         N->getOperand(2) };
189     return CurDAG->getMachineNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32,
190                                   Ops, 3);
191   }
192   case XCoreISD::MACCU: {
193     SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
194                       N->getOperand(2), N->getOperand(3) };
195     return CurDAG->getMachineNode(XCore::MACCU_l4r, dl, MVT::i32, MVT::i32,
196                                   Ops, 4);
197   }
198   case XCoreISD::MACCS: {
199     SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
200                       N->getOperand(2), N->getOperand(3) };
201     return CurDAG->getMachineNode(XCore::MACCS_l4r, dl, MVT::i32, MVT::i32,
202                                   Ops, 4);
203   }
204   case XCoreISD::LMUL: {
205     SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
206                       N->getOperand(2), N->getOperand(3) };
207     return CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, MVT::i32,
208                                   Ops, 4);
209   }
210   case ISD::BRIND:
211     if (SDNode *ResNode = SelectBRIND(N))
212       return ResNode;
213     break;
214   // Other cases are autogenerated.
215   }
216   return SelectCode(N);
217 }
218 
219 /// Given a chain return a new chain where any appearance of Old is replaced
220 /// by New. There must be at most one instruction between Old and Chain and
221 /// this instruction must be a TokenFactor. Returns an empty SDValue if
222 /// these conditions don't hold.
223 static SDValue
224 replaceInChain(SelectionDAG *CurDAG, SDValue Chain, SDValue Old, SDValue New)
225 {
226   if (Chain == Old)
227     return New;
228   if (Chain->getOpcode() != ISD::TokenFactor)
229     return SDValue();
230   SmallVector<SDValue, 8> Ops;
231   bool found = false;
232   for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) {
233     if (Chain->getOperand(i) == Old) {
234       Ops.push_back(New);
235       found = true;
236     } else {
237       Ops.push_back(Chain->getOperand(i));
238     }
239   }
240   if (!found)
241     return SDValue();
242   return CurDAG->getNode(ISD::TokenFactor, Chain->getDebugLoc(), MVT::Other,
243                          &Ops[0], Ops.size());
244 }
245 
246 SDNode *XCoreDAGToDAGISel::SelectBRIND(SDNode *N) {
247   DebugLoc dl = N->getDebugLoc();
248   // (brind (int_xcore_checkevent (addr)))
249   SDValue Chain = N->getOperand(0);
250   SDValue Addr = N->getOperand(1);
251   if (Addr->getOpcode() != ISD::INTRINSIC_W_CHAIN)
252     return 0;
253   unsigned IntNo = cast<ConstantSDNode>(Addr->getOperand(1))->getZExtValue();
254   if (IntNo != Intrinsic::xcore_checkevent)
255     return 0;
256   SDValue nextAddr = Addr->getOperand(2);
257   SDValue CheckEventChainOut(Addr.getNode(), 1);
258   if (!CheckEventChainOut.use_empty()) {
259     // If the chain out of the checkevent intrinsic is an operand of the
260     // indirect branch or used in a TokenFactor which is the operand of the
261     // indirect branch then build a new chain which uses the chain coming into
262     // the checkevent intrinsic instead.
263     SDValue CheckEventChainIn = Addr->getOperand(0);
264     SDValue NewChain = replaceInChain(CurDAG, Chain, CheckEventChainOut,
265                                       CheckEventChainIn);
266     if (!NewChain.getNode())
267       return 0;
268     Chain = NewChain;
269   }
270   // Enable events on the thread using setsr 1 and then disable them immediately
271   // after with clrsr 1. If any resources owned by the thread are ready an event
272   // will be taken. If no resource is ready we branch to the address which was
273   // the operand to the checkevent intrinsic.
274   SDValue constOne = getI32Imm(1);
275   SDValue Glue =
276     SDValue(CurDAG->getMachineNode(XCore::SETSR_branch_u6, dl, MVT::Glue,
277                                    constOne, Chain), 0);
278   Glue =
279     SDValue(CurDAG->getMachineNode(XCore::CLRSR_branch_u6, dl, MVT::Glue,
280                                    constOne, Glue), 0);
281   if (nextAddr->getOpcode() == XCoreISD::PCRelativeWrapper &&
282       nextAddr->getOperand(0)->getOpcode() == ISD::TargetBlockAddress) {
283     return CurDAG->SelectNodeTo(N, XCore::BRFU_lu6, MVT::Other,
284                                 nextAddr->getOperand(0), Glue);
285   }
286   return CurDAG->SelectNodeTo(N, XCore::BAU_1r, MVT::Other, nextAddr, Glue);
287 }
288