1 //===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// 10 /// \file 11 /// \brief This file is part of the XCore Disassembler. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 #include "XCore.h" 16 #include "XCoreRegisterInfo.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/MemoryObject.h" 23 #include "llvm/Support/TargetRegistry.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "xcore-disassembler" 28 29 typedef MCDisassembler::DecodeStatus DecodeStatus; 30 31 namespace { 32 33 /// \brief A disassembler class for XCore. 34 class XCoreDisassembler : public MCDisassembler { 35 public: 36 XCoreDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 37 MCDisassembler(STI, Ctx) {} 38 39 /// \brief See MCDisassembler. 40 DecodeStatus getInstruction(MCInst &instr, uint64_t &size, 41 const MemoryObject ®ion, uint64_t address, 42 raw_ostream &vStream, 43 raw_ostream &cStream) const override; 44 }; 45 } 46 47 static bool readInstruction16(const MemoryObject ®ion, 48 uint64_t address, 49 uint64_t &size, 50 uint16_t &insn) { 51 uint8_t Bytes[4]; 52 53 // We want to read exactly 2 Bytes of data. 54 if (region.readBytes(address, 2, Bytes) == -1) { 55 size = 0; 56 return false; 57 } 58 // Encoded as a little-endian 16-bit word in the stream. 59 insn = (Bytes[0] << 0) | (Bytes[1] << 8); 60 return true; 61 } 62 63 static bool readInstruction32(const MemoryObject ®ion, 64 uint64_t address, 65 uint64_t &size, 66 uint32_t &insn) { 67 uint8_t Bytes[4]; 68 69 // We want to read exactly 4 Bytes of data. 70 if (region.readBytes(address, 4, Bytes) == -1) { 71 size = 0; 72 return false; 73 } 74 // Encoded as a little-endian 32-bit word in the stream. 75 insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 76 (Bytes[3] << 24); 77 return true; 78 } 79 80 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 81 const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D); 82 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 83 return *(RegInfo->getRegClass(RC).begin() + RegNo); 84 } 85 86 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, 87 unsigned RegNo, 88 uint64_t Address, 89 const void *Decoder); 90 91 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, 92 unsigned RegNo, 93 uint64_t Address, 94 const void *Decoder); 95 96 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, 97 uint64_t Address, const void *Decoder); 98 99 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val, 100 uint64_t Address, const void *Decoder); 101 102 static DecodeStatus Decode2RInstruction(MCInst &Inst, 103 unsigned Insn, 104 uint64_t Address, 105 const void *Decoder); 106 107 static DecodeStatus Decode2RImmInstruction(MCInst &Inst, 108 unsigned Insn, 109 uint64_t Address, 110 const void *Decoder); 111 112 static DecodeStatus DecodeR2RInstruction(MCInst &Inst, 113 unsigned Insn, 114 uint64_t Address, 115 const void *Decoder); 116 117 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, 118 unsigned Insn, 119 uint64_t Address, 120 const void *Decoder); 121 122 static DecodeStatus DecodeRUSInstruction(MCInst &Inst, 123 unsigned Insn, 124 uint64_t Address, 125 const void *Decoder); 126 127 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst, 128 unsigned Insn, 129 uint64_t Address, 130 const void *Decoder); 131 132 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst, 133 unsigned Insn, 134 uint64_t Address, 135 const void *Decoder); 136 137 static DecodeStatus DecodeL2RInstruction(MCInst &Inst, 138 unsigned Insn, 139 uint64_t Address, 140 const void *Decoder); 141 142 static DecodeStatus DecodeLR2RInstruction(MCInst &Inst, 143 unsigned Insn, 144 uint64_t Address, 145 const void *Decoder); 146 147 static DecodeStatus Decode3RInstruction(MCInst &Inst, 148 unsigned Insn, 149 uint64_t Address, 150 const void *Decoder); 151 152 static DecodeStatus Decode3RImmInstruction(MCInst &Inst, 153 unsigned Insn, 154 uint64_t Address, 155 const void *Decoder); 156 157 static DecodeStatus Decode2RUSInstruction(MCInst &Inst, 158 unsigned Insn, 159 uint64_t Address, 160 const void *Decoder); 161 162 static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst, 163 unsigned Insn, 164 uint64_t Address, 165 const void *Decoder); 166 167 static DecodeStatus DecodeL3RInstruction(MCInst &Inst, 168 unsigned Insn, 169 uint64_t Address, 170 const void *Decoder); 171 172 static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst, 173 unsigned Insn, 174 uint64_t Address, 175 const void *Decoder); 176 177 static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst, 178 unsigned Insn, 179 uint64_t Address, 180 const void *Decoder); 181 182 static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst, 183 unsigned Insn, 184 uint64_t Address, 185 const void *Decoder); 186 187 static DecodeStatus DecodeL6RInstruction(MCInst &Inst, 188 unsigned Insn, 189 uint64_t Address, 190 const void *Decoder); 191 192 static DecodeStatus DecodeL5RInstruction(MCInst &Inst, 193 unsigned Insn, 194 uint64_t Address, 195 const void *Decoder); 196 197 static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst, 198 unsigned Insn, 199 uint64_t Address, 200 const void *Decoder); 201 202 static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, 203 unsigned Insn, 204 uint64_t Address, 205 const void *Decoder); 206 207 #include "XCoreGenDisassemblerTables.inc" 208 209 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, 210 unsigned RegNo, 211 uint64_t Address, 212 const void *Decoder) 213 { 214 if (RegNo > 11) 215 return MCDisassembler::Fail; 216 unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo); 217 Inst.addOperand(MCOperand::CreateReg(Reg)); 218 return MCDisassembler::Success; 219 } 220 221 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, 222 unsigned RegNo, 223 uint64_t Address, 224 const void *Decoder) 225 { 226 if (RegNo > 15) 227 return MCDisassembler::Fail; 228 unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo); 229 Inst.addOperand(MCOperand::CreateReg(Reg)); 230 return MCDisassembler::Success; 231 } 232 233 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, 234 uint64_t Address, const void *Decoder) { 235 if (Val > 11) 236 return MCDisassembler::Fail; 237 static unsigned Values[] = { 238 32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32 239 }; 240 Inst.addOperand(MCOperand::CreateImm(Values[Val])); 241 return MCDisassembler::Success; 242 } 243 244 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder) { 246 Inst.addOperand(MCOperand::CreateImm(-(int64_t)Val)); 247 return MCDisassembler::Success; 248 } 249 250 static DecodeStatus 251 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { 252 unsigned Combined = fieldFromInstruction(Insn, 6, 5); 253 if (Combined < 27) 254 return MCDisassembler::Fail; 255 if (fieldFromInstruction(Insn, 5, 1)) { 256 if (Combined == 31) 257 return MCDisassembler::Fail; 258 Combined += 5; 259 } 260 Combined -= 27; 261 unsigned Op1High = Combined % 3; 262 unsigned Op2High = Combined / 3; 263 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2); 264 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2); 265 return MCDisassembler::Success; 266 } 267 268 static DecodeStatus 269 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, 270 unsigned &Op3) { 271 unsigned Combined = fieldFromInstruction(Insn, 6, 5); 272 if (Combined >= 27) 273 return MCDisassembler::Fail; 274 275 unsigned Op1High = Combined % 3; 276 unsigned Op2High = (Combined / 3) % 3; 277 unsigned Op3High = Combined / 9; 278 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2); 279 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2); 280 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2); 281 return MCDisassembler::Success; 282 } 283 284 static DecodeStatus 285 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, 286 const void *Decoder) { 287 // Try and decode as a 3R instruction. 288 unsigned Opcode = fieldFromInstruction(Insn, 11, 5); 289 switch (Opcode) { 290 case 0x0: 291 Inst.setOpcode(XCore::STW_2rus); 292 return Decode2RUSInstruction(Inst, Insn, Address, Decoder); 293 case 0x1: 294 Inst.setOpcode(XCore::LDW_2rus); 295 return Decode2RUSInstruction(Inst, Insn, Address, Decoder); 296 case 0x2: 297 Inst.setOpcode(XCore::ADD_3r); 298 return Decode3RInstruction(Inst, Insn, Address, Decoder); 299 case 0x3: 300 Inst.setOpcode(XCore::SUB_3r); 301 return Decode3RInstruction(Inst, Insn, Address, Decoder); 302 case 0x4: 303 Inst.setOpcode(XCore::SHL_3r); 304 return Decode3RInstruction(Inst, Insn, Address, Decoder); 305 case 0x5: 306 Inst.setOpcode(XCore::SHR_3r); 307 return Decode3RInstruction(Inst, Insn, Address, Decoder); 308 case 0x6: 309 Inst.setOpcode(XCore::EQ_3r); 310 return Decode3RInstruction(Inst, Insn, Address, Decoder); 311 case 0x7: 312 Inst.setOpcode(XCore::AND_3r); 313 return Decode3RInstruction(Inst, Insn, Address, Decoder); 314 case 0x8: 315 Inst.setOpcode(XCore::OR_3r); 316 return Decode3RInstruction(Inst, Insn, Address, Decoder); 317 case 0x9: 318 Inst.setOpcode(XCore::LDW_3r); 319 return Decode3RInstruction(Inst, Insn, Address, Decoder); 320 case 0x10: 321 Inst.setOpcode(XCore::LD16S_3r); 322 return Decode3RInstruction(Inst, Insn, Address, Decoder); 323 case 0x11: 324 Inst.setOpcode(XCore::LD8U_3r); 325 return Decode3RInstruction(Inst, Insn, Address, Decoder); 326 case 0x12: 327 Inst.setOpcode(XCore::ADD_2rus); 328 return Decode2RUSInstruction(Inst, Insn, Address, Decoder); 329 case 0x13: 330 Inst.setOpcode(XCore::SUB_2rus); 331 return Decode2RUSInstruction(Inst, Insn, Address, Decoder); 332 case 0x14: 333 Inst.setOpcode(XCore::SHL_2rus); 334 return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder); 335 case 0x15: 336 Inst.setOpcode(XCore::SHR_2rus); 337 return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder); 338 case 0x16: 339 Inst.setOpcode(XCore::EQ_2rus); 340 return Decode2RUSInstruction(Inst, Insn, Address, Decoder); 341 case 0x17: 342 Inst.setOpcode(XCore::TSETR_3r); 343 return Decode3RImmInstruction(Inst, Insn, Address, Decoder); 344 case 0x18: 345 Inst.setOpcode(XCore::LSS_3r); 346 return Decode3RInstruction(Inst, Insn, Address, Decoder); 347 case 0x19: 348 Inst.setOpcode(XCore::LSU_3r); 349 return Decode3RInstruction(Inst, Insn, Address, Decoder); 350 } 351 return MCDisassembler::Fail; 352 } 353 354 static DecodeStatus 355 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 356 const void *Decoder) { 357 unsigned Op1, Op2; 358 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 359 if (S != MCDisassembler::Success) 360 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 361 362 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 363 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 364 return S; 365 } 366 367 static DecodeStatus 368 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 369 const void *Decoder) { 370 unsigned Op1, Op2; 371 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 372 if (S != MCDisassembler::Success) 373 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 374 375 Inst.addOperand(MCOperand::CreateImm(Op1)); 376 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 377 return S; 378 } 379 380 static DecodeStatus 381 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 382 const void *Decoder) { 383 unsigned Op1, Op2; 384 DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1); 385 if (S != MCDisassembler::Success) 386 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 387 388 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 389 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 390 return S; 391 } 392 393 static DecodeStatus 394 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 395 const void *Decoder) { 396 unsigned Op1, Op2; 397 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 398 if (S != MCDisassembler::Success) 399 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 400 401 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 402 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 403 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 404 return S; 405 } 406 407 static DecodeStatus 408 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 409 const void *Decoder) { 410 unsigned Op1, Op2; 411 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 412 if (S != MCDisassembler::Success) 413 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 414 415 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 416 Inst.addOperand(MCOperand::CreateImm(Op2)); 417 return S; 418 } 419 420 static DecodeStatus 421 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 422 const void *Decoder) { 423 unsigned Op1, Op2; 424 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 425 if (S != MCDisassembler::Success) 426 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 427 428 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 429 DecodeBitpOperand(Inst, Op2, Address, Decoder); 430 return S; 431 } 432 433 static DecodeStatus 434 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 435 const void *Decoder) { 436 unsigned Op1, Op2; 437 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 438 if (S != MCDisassembler::Success) 439 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 440 441 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 442 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 443 DecodeBitpOperand(Inst, Op2, Address, Decoder); 444 return S; 445 } 446 447 static DecodeStatus 448 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, 449 const void *Decoder) { 450 // Try and decode as a L3R / L2RUS instruction. 451 unsigned Opcode = fieldFromInstruction(Insn, 16, 4) | 452 fieldFromInstruction(Insn, 27, 5) << 4; 453 switch (Opcode) { 454 case 0x0c: 455 Inst.setOpcode(XCore::STW_l3r); 456 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 457 case 0x1c: 458 Inst.setOpcode(XCore::XOR_l3r); 459 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 460 case 0x2c: 461 Inst.setOpcode(XCore::ASHR_l3r); 462 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 463 case 0x3c: 464 Inst.setOpcode(XCore::LDAWF_l3r); 465 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 466 case 0x4c: 467 Inst.setOpcode(XCore::LDAWB_l3r); 468 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 469 case 0x5c: 470 Inst.setOpcode(XCore::LDA16F_l3r); 471 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 472 case 0x6c: 473 Inst.setOpcode(XCore::LDA16B_l3r); 474 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 475 case 0x7c: 476 Inst.setOpcode(XCore::MUL_l3r); 477 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 478 case 0x8c: 479 Inst.setOpcode(XCore::DIVS_l3r); 480 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 481 case 0x9c: 482 Inst.setOpcode(XCore::DIVU_l3r); 483 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 484 case 0x10c: 485 Inst.setOpcode(XCore::ST16_l3r); 486 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 487 case 0x11c: 488 Inst.setOpcode(XCore::ST8_l3r); 489 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 490 case 0x12c: 491 Inst.setOpcode(XCore::ASHR_l2rus); 492 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); 493 case 0x12d: 494 Inst.setOpcode(XCore::OUTPW_l2rus); 495 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); 496 case 0x12e: 497 Inst.setOpcode(XCore::INPW_l2rus); 498 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); 499 case 0x13c: 500 Inst.setOpcode(XCore::LDAWF_l2rus); 501 return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder); 502 case 0x14c: 503 Inst.setOpcode(XCore::LDAWB_l2rus); 504 return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder); 505 case 0x15c: 506 Inst.setOpcode(XCore::CRC_l3r); 507 return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder); 508 case 0x18c: 509 Inst.setOpcode(XCore::REMS_l3r); 510 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 511 case 0x19c: 512 Inst.setOpcode(XCore::REMU_l3r); 513 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 514 } 515 return MCDisassembler::Fail; 516 } 517 518 static DecodeStatus 519 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 520 const void *Decoder) { 521 unsigned Op1, Op2; 522 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16), 523 Op1, Op2); 524 if (S != MCDisassembler::Success) 525 return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder); 526 527 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 528 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 529 return S; 530 } 531 532 static DecodeStatus 533 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 534 const void *Decoder) { 535 unsigned Op1, Op2; 536 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16), 537 Op1, Op2); 538 if (S != MCDisassembler::Success) 539 return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder); 540 541 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 542 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 543 return S; 544 } 545 546 static DecodeStatus 547 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 548 const void *Decoder) { 549 unsigned Op1, Op2, Op3; 550 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); 551 if (S == MCDisassembler::Success) { 552 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 553 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 554 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 555 } 556 return S; 557 } 558 559 static DecodeStatus 560 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 561 const void *Decoder) { 562 unsigned Op1, Op2, Op3; 563 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); 564 if (S == MCDisassembler::Success) { 565 Inst.addOperand(MCOperand::CreateImm(Op1)); 566 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 567 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 568 } 569 return S; 570 } 571 572 static DecodeStatus 573 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 574 const void *Decoder) { 575 unsigned Op1, Op2, Op3; 576 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); 577 if (S == MCDisassembler::Success) { 578 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 579 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 580 Inst.addOperand(MCOperand::CreateImm(Op3)); 581 } 582 return S; 583 } 584 585 static DecodeStatus 586 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 587 const void *Decoder) { 588 unsigned Op1, Op2, Op3; 589 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); 590 if (S == MCDisassembler::Success) { 591 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 592 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 593 DecodeBitpOperand(Inst, Op3, Address, Decoder); 594 } 595 return S; 596 } 597 598 static DecodeStatus 599 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 600 const void *Decoder) { 601 unsigned Op1, Op2, Op3; 602 DecodeStatus S = 603 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 604 if (S == MCDisassembler::Success) { 605 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 606 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 607 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 608 } 609 return S; 610 } 611 612 static DecodeStatus 613 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 614 const void *Decoder) { 615 unsigned Op1, Op2, Op3; 616 DecodeStatus S = 617 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 618 if (S == MCDisassembler::Success) { 619 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 620 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 621 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 622 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 623 } 624 return S; 625 } 626 627 static DecodeStatus 628 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 629 const void *Decoder) { 630 unsigned Op1, Op2, Op3; 631 DecodeStatus S = 632 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 633 if (S == MCDisassembler::Success) { 634 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 635 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 636 Inst.addOperand(MCOperand::CreateImm(Op3)); 637 } 638 return S; 639 } 640 641 static DecodeStatus 642 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 643 const void *Decoder) { 644 unsigned Op1, Op2, Op3; 645 DecodeStatus S = 646 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 647 if (S == MCDisassembler::Success) { 648 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 649 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 650 DecodeBitpOperand(Inst, Op3, Address, Decoder); 651 } 652 return S; 653 } 654 655 static DecodeStatus 656 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 657 const void *Decoder) { 658 unsigned Op1, Op2, Op3, Op4, Op5, Op6; 659 DecodeStatus S = 660 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 661 if (S != MCDisassembler::Success) 662 return S; 663 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6); 664 if (S != MCDisassembler::Success) 665 return S; 666 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 667 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 668 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 669 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 670 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); 671 DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder); 672 return S; 673 } 674 675 static DecodeStatus 676 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, 677 const void *Decoder) { 678 // Try and decode as a L6R instruction. 679 Inst.clear(); 680 unsigned Opcode = fieldFromInstruction(Insn, 27, 5); 681 switch (Opcode) { 682 case 0x00: 683 Inst.setOpcode(XCore::LMUL_l6r); 684 return DecodeL6RInstruction(Inst, Insn, Address, Decoder); 685 } 686 return MCDisassembler::Fail; 687 } 688 689 static DecodeStatus 690 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 691 const void *Decoder) { 692 unsigned Op1, Op2, Op3, Op4, Op5; 693 DecodeStatus S = 694 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 695 if (S != MCDisassembler::Success) 696 return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder); 697 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5); 698 if (S != MCDisassembler::Success) 699 return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder); 700 701 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 702 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 703 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 704 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 705 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); 706 return S; 707 } 708 709 static DecodeStatus 710 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 711 const void *Decoder) { 712 unsigned Op1, Op2, Op3; 713 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); 714 DecodeStatus S = 715 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 716 if (S == MCDisassembler::Success) { 717 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 718 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 719 } 720 if (S == MCDisassembler::Success) { 721 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 722 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 723 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 724 } 725 return S; 726 } 727 728 static DecodeStatus 729 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 730 const void *Decoder) { 731 unsigned Op1, Op2, Op3; 732 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); 733 DecodeStatus S = 734 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 735 if (S == MCDisassembler::Success) { 736 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 737 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 738 } 739 if (S == MCDisassembler::Success) { 740 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 741 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 742 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 743 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 744 } 745 return S; 746 } 747 748 MCDisassembler::DecodeStatus 749 XCoreDisassembler::getInstruction(MCInst &instr, 750 uint64_t &Size, 751 const MemoryObject &Region, 752 uint64_t Address, 753 raw_ostream &vStream, 754 raw_ostream &cStream) const { 755 uint16_t insn16; 756 757 if (!readInstruction16(Region, Address, Size, insn16)) { 758 return Fail; 759 } 760 761 // Calling the auto-generated decoder function. 762 DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16, 763 Address, this, STI); 764 if (Result != Fail) { 765 Size = 2; 766 return Result; 767 } 768 769 uint32_t insn32; 770 771 if (!readInstruction32(Region, Address, Size, insn32)) { 772 return Fail; 773 } 774 775 // Calling the auto-generated decoder function. 776 Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI); 777 if (Result != Fail) { 778 Size = 4; 779 return Result; 780 } 781 782 return Fail; 783 } 784 785 namespace llvm { 786 extern Target TheXCoreTarget; 787 } 788 789 static MCDisassembler *createXCoreDisassembler(const Target &T, 790 const MCSubtargetInfo &STI, 791 MCContext &Ctx) { 792 return new XCoreDisassembler(STI, Ctx); 793 } 794 795 extern "C" void LLVMInitializeXCoreDisassembler() { 796 // Register the disassembler. 797 TargetRegistry::RegisterMCDisassembler(TheXCoreTarget, 798 createXCoreDisassembler); 799 } 800