1 //===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// 10 /// \file 11 /// \brief This file is part of the XCore Disassembler. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 #include "XCore.h" 16 #include "XCoreRegisterInfo.h" 17 #include "llvm/MC/MCDisassembler.h" 18 #include "llvm/MC/MCFixedLenDisassembler.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/Support/MemoryObject.h" 22 #include "llvm/Support/TargetRegistry.h" 23 24 using namespace llvm; 25 26 typedef MCDisassembler::DecodeStatus DecodeStatus; 27 28 namespace { 29 30 /// \brief A disassembler class for XCore. 31 class XCoreDisassembler : public MCDisassembler { 32 const MCRegisterInfo *RegInfo; 33 public: 34 XCoreDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) : 35 MCDisassembler(STI), RegInfo(Info) {} 36 37 /// \brief See MCDisassembler. 38 virtual DecodeStatus getInstruction(MCInst &instr, 39 uint64_t &size, 40 const MemoryObject ®ion, 41 uint64_t address, 42 raw_ostream &vStream, 43 raw_ostream &cStream) const; 44 45 const MCRegisterInfo *getRegInfo() const { return RegInfo; } 46 }; 47 } 48 49 static bool readInstruction16(const MemoryObject ®ion, 50 uint64_t address, 51 uint64_t &size, 52 uint16_t &insn) { 53 uint8_t Bytes[4]; 54 55 // We want to read exactly 2 Bytes of data. 56 if (region.readBytes(address, 2, Bytes, NULL) == -1) { 57 size = 0; 58 return false; 59 } 60 // Encoded as a little-endian 16-bit word in the stream. 61 insn = (Bytes[0] << 0) | (Bytes[1] << 8); 62 return true; 63 } 64 65 static bool readInstruction32(const MemoryObject ®ion, 66 uint64_t address, 67 uint64_t &size, 68 uint32_t &insn) { 69 uint8_t Bytes[4]; 70 71 // We want to read exactly 4 Bytes of data. 72 if (region.readBytes(address, 4, Bytes, NULL) == -1) { 73 size = 0; 74 return false; 75 } 76 // Encoded as a little-endian 32-bit word in the stream. 77 insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 78 (Bytes[3] << 24); 79 return true; 80 } 81 82 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 83 const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D); 84 return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo); 85 } 86 87 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, 88 unsigned RegNo, 89 uint64_t Address, 90 const void *Decoder); 91 92 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, 93 uint64_t Address, const void *Decoder); 94 95 static DecodeStatus DecodeMEMiiOperand(MCInst &Inst, unsigned Val, 96 uint64_t Address, const void *Decoder); 97 98 static DecodeStatus Decode2RInstruction(MCInst &Inst, 99 unsigned Insn, 100 uint64_t Address, 101 const void *Decoder); 102 103 static DecodeStatus DecodeR2RInstruction(MCInst &Inst, 104 unsigned Insn, 105 uint64_t Address, 106 const void *Decoder); 107 108 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, 109 unsigned Insn, 110 uint64_t Address, 111 const void *Decoder); 112 113 static DecodeStatus DecodeRUSInstruction(MCInst &Inst, 114 unsigned Insn, 115 uint64_t Address, 116 const void *Decoder); 117 118 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst, 119 unsigned Insn, 120 uint64_t Address, 121 const void *Decoder); 122 123 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst, 124 unsigned Insn, 125 uint64_t Address, 126 const void *Decoder); 127 128 static DecodeStatus DecodeL2RInstruction(MCInst &Inst, 129 unsigned Insn, 130 uint64_t Address, 131 const void *Decoder); 132 133 static DecodeStatus DecodeLR2RInstruction(MCInst &Inst, 134 unsigned Insn, 135 uint64_t Address, 136 const void *Decoder); 137 138 static DecodeStatus Decode3RInstruction(MCInst &Inst, 139 unsigned Insn, 140 uint64_t Address, 141 const void *Decoder); 142 143 static DecodeStatus Decode2RUSInstruction(MCInst &Inst, 144 unsigned Insn, 145 uint64_t Address, 146 const void *Decoder); 147 148 static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst, 149 unsigned Insn, 150 uint64_t Address, 151 const void *Decoder); 152 153 static DecodeStatus DecodeL3RInstruction(MCInst &Inst, 154 unsigned Insn, 155 uint64_t Address, 156 const void *Decoder); 157 158 static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst, 159 unsigned Insn, 160 uint64_t Address, 161 const void *Decoder); 162 163 static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst, 164 unsigned Insn, 165 uint64_t Address, 166 const void *Decoder); 167 168 static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst, 169 unsigned Insn, 170 uint64_t Address, 171 const void *Decoder); 172 173 static DecodeStatus DecodeL6RInstruction(MCInst &Inst, 174 unsigned Insn, 175 uint64_t Address, 176 const void *Decoder); 177 178 static DecodeStatus DecodeL5RInstruction(MCInst &Inst, 179 unsigned Insn, 180 uint64_t Address, 181 const void *Decoder); 182 183 static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst, 184 unsigned Insn, 185 uint64_t Address, 186 const void *Decoder); 187 188 static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, 189 unsigned Insn, 190 uint64_t Address, 191 const void *Decoder); 192 193 #include "XCoreGenDisassemblerTables.inc" 194 195 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, 196 unsigned RegNo, 197 uint64_t Address, 198 const void *Decoder) 199 { 200 if (RegNo > 11) 201 return MCDisassembler::Fail; 202 unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo); 203 Inst.addOperand(MCOperand::CreateReg(Reg)); 204 return MCDisassembler::Success; 205 } 206 207 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, 208 uint64_t Address, const void *Decoder) { 209 if (Val > 11) 210 return MCDisassembler::Fail; 211 static unsigned Values[] = { 212 32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32 213 }; 214 Inst.addOperand(MCOperand::CreateImm(Values[Val])); 215 return MCDisassembler::Success; 216 } 217 218 static DecodeStatus DecodeMEMiiOperand(MCInst &Inst, unsigned Val, 219 uint64_t Address, const void *Decoder) { 220 Inst.addOperand(MCOperand::CreateImm(Val)); 221 Inst.addOperand(MCOperand::CreateImm(0)); 222 return MCDisassembler::Success; 223 } 224 225 static DecodeStatus 226 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { 227 unsigned Combined = fieldFromInstruction(Insn, 6, 5); 228 if (Combined < 27) 229 return MCDisassembler::Fail; 230 if (fieldFromInstruction(Insn, 5, 1)) { 231 if (Combined == 31) 232 return MCDisassembler::Fail; 233 Combined += 5; 234 } 235 Combined -= 27; 236 unsigned Op1High = Combined % 3; 237 unsigned Op2High = Combined / 3; 238 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2); 239 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2); 240 return MCDisassembler::Success; 241 } 242 243 static DecodeStatus 244 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, 245 unsigned &Op3) { 246 unsigned Combined = fieldFromInstruction(Insn, 6, 5); 247 if (Combined >= 27) 248 return MCDisassembler::Fail; 249 250 unsigned Op1High = Combined % 3; 251 unsigned Op2High = (Combined / 3) % 3; 252 unsigned Op3High = Combined / 9; 253 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2); 254 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2); 255 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2); 256 return MCDisassembler::Success; 257 } 258 259 static DecodeStatus 260 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, 261 const void *Decoder) { 262 // Try and decode as a 3R instruction. 263 unsigned Opcode = fieldFromInstruction(Insn, 11, 5); 264 switch (Opcode) { 265 case 0x0: 266 Inst.setOpcode(XCore::STW_2rus); 267 return Decode2RUSInstruction(Inst, Insn, Address, Decoder); 268 case 0x1: 269 Inst.setOpcode(XCore::LDW_2rus); 270 return Decode2RUSInstruction(Inst, Insn, Address, Decoder); 271 case 0x2: 272 Inst.setOpcode(XCore::ADD_3r); 273 return Decode3RInstruction(Inst, Insn, Address, Decoder); 274 case 0x3: 275 Inst.setOpcode(XCore::SUB_3r); 276 return Decode3RInstruction(Inst, Insn, Address, Decoder); 277 case 0x4: 278 Inst.setOpcode(XCore::SHL_3r); 279 return Decode3RInstruction(Inst, Insn, Address, Decoder); 280 case 0x5: 281 Inst.setOpcode(XCore::SHR_3r); 282 return Decode3RInstruction(Inst, Insn, Address, Decoder); 283 case 0x6: 284 Inst.setOpcode(XCore::EQ_3r); 285 return Decode3RInstruction(Inst, Insn, Address, Decoder); 286 case 0x7: 287 Inst.setOpcode(XCore::AND_3r); 288 return Decode3RInstruction(Inst, Insn, Address, Decoder); 289 case 0x8: 290 Inst.setOpcode(XCore::OR_3r); 291 return Decode3RInstruction(Inst, Insn, Address, Decoder); 292 case 0x9: 293 Inst.setOpcode(XCore::LDW_3r); 294 return Decode3RInstruction(Inst, Insn, Address, Decoder); 295 case 0x10: 296 Inst.setOpcode(XCore::LD16S_3r); 297 return Decode3RInstruction(Inst, Insn, Address, Decoder); 298 case 0x11: 299 Inst.setOpcode(XCore::LD8U_3r); 300 return Decode3RInstruction(Inst, Insn, Address, Decoder); 301 case 0x12: 302 Inst.setOpcode(XCore::ADD_2rus); 303 return Decode2RUSInstruction(Inst, Insn, Address, Decoder); 304 case 0x13: 305 Inst.setOpcode(XCore::SUB_2rus); 306 return Decode2RUSInstruction(Inst, Insn, Address, Decoder); 307 case 0x14: 308 Inst.setOpcode(XCore::SHL_2rus); 309 return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder); 310 case 0x15: 311 Inst.setOpcode(XCore::SHR_2rus); 312 return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder); 313 case 0x16: 314 Inst.setOpcode(XCore::EQ_2rus); 315 return Decode2RUSInstruction(Inst, Insn, Address, Decoder); 316 case 0x18: 317 Inst.setOpcode(XCore::LSS_3r); 318 return Decode3RInstruction(Inst, Insn, Address, Decoder); 319 case 0x19: 320 Inst.setOpcode(XCore::LSU_3r); 321 return Decode3RInstruction(Inst, Insn, Address, Decoder); 322 } 323 return MCDisassembler::Fail; 324 } 325 326 static DecodeStatus 327 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 328 const void *Decoder) { 329 unsigned Op1, Op2; 330 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 331 if (S != MCDisassembler::Success) 332 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 333 334 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 335 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 336 return S; 337 } 338 339 static DecodeStatus 340 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 341 const void *Decoder) { 342 unsigned Op1, Op2; 343 DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1); 344 if (S != MCDisassembler::Success) 345 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 346 347 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 348 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 349 return S; 350 } 351 352 static DecodeStatus 353 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 354 const void *Decoder) { 355 unsigned Op1, Op2; 356 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 357 if (S != MCDisassembler::Success) 358 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 359 360 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 361 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 362 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 363 return S; 364 } 365 366 static DecodeStatus 367 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 368 const void *Decoder) { 369 unsigned Op1, Op2; 370 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 371 if (S != MCDisassembler::Success) 372 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 373 374 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 375 Inst.addOperand(MCOperand::CreateImm(Op2)); 376 return S; 377 } 378 379 static DecodeStatus 380 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 381 const void *Decoder) { 382 unsigned Op1, Op2; 383 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 384 if (S != MCDisassembler::Success) 385 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 386 387 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 388 DecodeBitpOperand(Inst, Op2, Address, Decoder); 389 return S; 390 } 391 392 static DecodeStatus 393 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 394 const void *Decoder) { 395 unsigned Op1, Op2; 396 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 397 if (S != MCDisassembler::Success) 398 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 399 400 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 401 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 402 DecodeBitpOperand(Inst, Op2, Address, Decoder); 403 return S; 404 } 405 406 static DecodeStatus 407 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, 408 const void *Decoder) { 409 // Try and decode as a L3R / L2RUS instruction. 410 unsigned Opcode = fieldFromInstruction(Insn, 16, 4) | 411 fieldFromInstruction(Insn, 27, 5) << 4; 412 switch (Opcode) { 413 case 0x0c: 414 Inst.setOpcode(XCore::STW_l3r); 415 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 416 case 0x1c: 417 Inst.setOpcode(XCore::XOR_l3r); 418 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 419 case 0x2c: 420 Inst.setOpcode(XCore::ASHR_l3r); 421 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 422 case 0x3c: 423 Inst.setOpcode(XCore::LDAWF_l3r); 424 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 425 case 0x4c: 426 Inst.setOpcode(XCore::LDAWB_l3r); 427 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 428 case 0x5c: 429 Inst.setOpcode(XCore::LDA16F_l3r); 430 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 431 case 0x6c: 432 Inst.setOpcode(XCore::LDA16B_l3r); 433 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 434 case 0x7c: 435 Inst.setOpcode(XCore::MUL_l3r); 436 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 437 case 0x8c: 438 Inst.setOpcode(XCore::DIVS_l3r); 439 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 440 case 0x9c: 441 Inst.setOpcode(XCore::DIVU_l3r); 442 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 443 case 0x10c: 444 Inst.setOpcode(XCore::ST16_l3r); 445 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 446 case 0x11c: 447 Inst.setOpcode(XCore::ST8_l3r); 448 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 449 case 0x12c: 450 Inst.setOpcode(XCore::ASHR_l2rus); 451 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); 452 case 0x12d: 453 Inst.setOpcode(XCore::OUTPW_l2rus); 454 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); 455 case 0x12e: 456 Inst.setOpcode(XCore::INPW_l2rus); 457 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); 458 case 0x13c: 459 Inst.setOpcode(XCore::LDAWF_l2rus); 460 return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder); 461 case 0x14c: 462 Inst.setOpcode(XCore::LDAWB_l2rus); 463 return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder); 464 case 0x15c: 465 Inst.setOpcode(XCore::CRC_l3r); 466 return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder); 467 case 0x18c: 468 Inst.setOpcode(XCore::REMS_l3r); 469 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 470 case 0x19c: 471 Inst.setOpcode(XCore::REMU_l3r); 472 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 473 } 474 return MCDisassembler::Fail; 475 } 476 477 static DecodeStatus 478 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 479 const void *Decoder) { 480 unsigned Op1, Op2; 481 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16), 482 Op1, Op2); 483 if (S != MCDisassembler::Success) 484 return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder); 485 486 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 487 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 488 return S; 489 } 490 491 static DecodeStatus 492 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 493 const void *Decoder) { 494 unsigned Op1, Op2; 495 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16), 496 Op1, Op2); 497 if (S != MCDisassembler::Success) 498 return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder); 499 500 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 501 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 502 return S; 503 } 504 505 static DecodeStatus 506 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 507 const void *Decoder) { 508 unsigned Op1, Op2, Op3; 509 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); 510 if (S == MCDisassembler::Success) { 511 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 512 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 513 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 514 } 515 return S; 516 } 517 518 static DecodeStatus 519 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 520 const void *Decoder) { 521 unsigned Op1, Op2, Op3; 522 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); 523 if (S == MCDisassembler::Success) { 524 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 525 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 526 Inst.addOperand(MCOperand::CreateImm(Op3)); 527 } 528 return S; 529 } 530 531 static DecodeStatus 532 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 533 const void *Decoder) { 534 unsigned Op1, Op2, Op3; 535 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); 536 if (S == MCDisassembler::Success) { 537 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 538 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 539 DecodeBitpOperand(Inst, Op3, Address, Decoder); 540 } 541 return S; 542 } 543 544 static DecodeStatus 545 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 546 const void *Decoder) { 547 unsigned Op1, Op2, Op3; 548 DecodeStatus S = 549 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 550 if (S == MCDisassembler::Success) { 551 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 552 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 553 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 554 } 555 return S; 556 } 557 558 static DecodeStatus 559 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 560 const void *Decoder) { 561 unsigned Op1, Op2, Op3; 562 DecodeStatus S = 563 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 564 if (S == MCDisassembler::Success) { 565 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 566 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 567 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 568 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 569 } 570 return S; 571 } 572 573 static DecodeStatus 574 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 575 const void *Decoder) { 576 unsigned Op1, Op2, Op3; 577 DecodeStatus S = 578 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 579 if (S == MCDisassembler::Success) { 580 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 581 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 582 Inst.addOperand(MCOperand::CreateImm(Op3)); 583 } 584 return S; 585 } 586 587 static DecodeStatus 588 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 589 const void *Decoder) { 590 unsigned Op1, Op2, Op3; 591 DecodeStatus S = 592 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 593 if (S == MCDisassembler::Success) { 594 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 595 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 596 DecodeBitpOperand(Inst, Op3, Address, Decoder); 597 } 598 return S; 599 } 600 601 static DecodeStatus 602 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 603 const void *Decoder) { 604 unsigned Op1, Op2, Op3, Op4, Op5, Op6; 605 DecodeStatus S = 606 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 607 if (S != MCDisassembler::Success) 608 return S; 609 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6); 610 if (S != MCDisassembler::Success) 611 return S; 612 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 613 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 614 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 615 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 616 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); 617 DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder); 618 return S; 619 } 620 621 static DecodeStatus 622 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, 623 const void *Decoder) { 624 // Try and decode as a L6R instruction. 625 Inst.clear(); 626 unsigned Opcode = fieldFromInstruction(Insn, 27, 5); 627 switch (Opcode) { 628 case 0x00: 629 Inst.setOpcode(XCore::LMUL_l6r); 630 return DecodeL6RInstruction(Inst, Insn, Address, Decoder); 631 } 632 return MCDisassembler::Fail; 633 } 634 635 static DecodeStatus 636 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 637 const void *Decoder) { 638 unsigned Op1, Op2, Op3, Op4, Op5; 639 DecodeStatus S = 640 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 641 if (S != MCDisassembler::Success) 642 return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder); 643 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5); 644 if (S != MCDisassembler::Success) 645 return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder); 646 647 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 648 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 649 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 650 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 651 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); 652 return S; 653 } 654 655 static DecodeStatus 656 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 657 const void *Decoder) { 658 unsigned Op1, Op2, Op3; 659 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); 660 DecodeStatus S = 661 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 662 if (S == MCDisassembler::Success) { 663 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 664 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 665 } 666 if (S == MCDisassembler::Success) { 667 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 668 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 669 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 670 } 671 return S; 672 } 673 674 static DecodeStatus 675 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 676 const void *Decoder) { 677 unsigned Op1, Op2, Op3; 678 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); 679 DecodeStatus S = 680 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 681 if (S == MCDisassembler::Success) { 682 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 683 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 684 } 685 if (S == MCDisassembler::Success) { 686 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 687 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 688 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 689 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 690 } 691 return S; 692 } 693 694 MCDisassembler::DecodeStatus 695 XCoreDisassembler::getInstruction(MCInst &instr, 696 uint64_t &Size, 697 const MemoryObject &Region, 698 uint64_t Address, 699 raw_ostream &vStream, 700 raw_ostream &cStream) const { 701 uint16_t insn16; 702 703 if (!readInstruction16(Region, Address, Size, insn16)) { 704 return Fail; 705 } 706 707 // Calling the auto-generated decoder function. 708 DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16, 709 Address, this, STI); 710 if (Result != Fail) { 711 Size = 2; 712 return Result; 713 } 714 715 uint32_t insn32; 716 717 if (!readInstruction32(Region, Address, Size, insn32)) { 718 return Fail; 719 } 720 721 // Calling the auto-generated decoder function. 722 Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI); 723 if (Result != Fail) { 724 Size = 4; 725 return Result; 726 } 727 728 return Fail; 729 } 730 731 namespace llvm { 732 extern Target TheXCoreTarget; 733 } 734 735 static MCDisassembler *createXCoreDisassembler(const Target &T, 736 const MCSubtargetInfo &STI) { 737 return new XCoreDisassembler(STI, T.createMCRegInfo("")); 738 } 739 740 extern "C" void LLVMInitializeXCoreDisassembler() { 741 // Register the disassembler. 742 TargetRegistry::RegisterMCDisassembler(TheXCoreTarget, 743 createXCoreDisassembler); 744 } 745