1 //===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// 10 /// \file 11 /// \brief This file is part of the XCore Disassembler. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 #include "XCore.h" 16 #include "XCoreRegisterInfo.h" 17 #include "llvm/MC/MCDisassembler.h" 18 #include "llvm/MC/MCFixedLenDisassembler.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/Support/MemoryObject.h" 22 #include "llvm/Support/TargetRegistry.h" 23 24 using namespace llvm; 25 26 typedef MCDisassembler::DecodeStatus DecodeStatus; 27 28 namespace { 29 30 /// \brief A disassembler class for XCore. 31 class XCoreDisassembler : public MCDisassembler { 32 const MCRegisterInfo *RegInfo; 33 public: 34 XCoreDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) : 35 MCDisassembler(STI), RegInfo(Info) {} 36 37 /// \brief See MCDisassembler. 38 virtual DecodeStatus getInstruction(MCInst &instr, 39 uint64_t &size, 40 const MemoryObject ®ion, 41 uint64_t address, 42 raw_ostream &vStream, 43 raw_ostream &cStream) const; 44 45 const MCRegisterInfo *getRegInfo() const { return RegInfo; } 46 }; 47 } 48 49 static bool readInstruction16(const MemoryObject ®ion, 50 uint64_t address, 51 uint64_t &size, 52 uint16_t &insn) { 53 uint8_t Bytes[4]; 54 55 // We want to read exactly 2 Bytes of data. 56 if (region.readBytes(address, 2, Bytes, NULL) == -1) { 57 size = 0; 58 return false; 59 } 60 // Encoded as a little-endian 16-bit word in the stream. 61 insn = (Bytes[0] << 0) | (Bytes[1] << 8); 62 return true; 63 } 64 65 static bool readInstruction32(const MemoryObject ®ion, 66 uint64_t address, 67 uint64_t &size, 68 uint32_t &insn) { 69 uint8_t Bytes[4]; 70 71 // We want to read exactly 4 Bytes of data. 72 if (region.readBytes(address, 4, Bytes, NULL) == -1) { 73 size = 0; 74 return false; 75 } 76 // Encoded as a little-endian 32-bit word in the stream. 77 insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 78 (Bytes[3] << 24); 79 return true; 80 } 81 82 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 83 const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D); 84 return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo); 85 } 86 87 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, 88 unsigned RegNo, 89 uint64_t Address, 90 const void *Decoder); 91 92 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, 93 unsigned RegNo, 94 uint64_t Address, 95 const void *Decoder); 96 97 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, 98 uint64_t Address, const void *Decoder); 99 100 static DecodeStatus DecodeMEMiiOperand(MCInst &Inst, unsigned Val, 101 uint64_t Address, const void *Decoder); 102 103 static DecodeStatus Decode2RInstruction(MCInst &Inst, 104 unsigned Insn, 105 uint64_t Address, 106 const void *Decoder); 107 108 static DecodeStatus Decode2RImmInstruction(MCInst &Inst, 109 unsigned Insn, 110 uint64_t Address, 111 const void *Decoder); 112 113 static DecodeStatus DecodeR2RInstruction(MCInst &Inst, 114 unsigned Insn, 115 uint64_t Address, 116 const void *Decoder); 117 118 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, 119 unsigned Insn, 120 uint64_t Address, 121 const void *Decoder); 122 123 static DecodeStatus DecodeRUSInstruction(MCInst &Inst, 124 unsigned Insn, 125 uint64_t Address, 126 const void *Decoder); 127 128 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst, 129 unsigned Insn, 130 uint64_t Address, 131 const void *Decoder); 132 133 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst, 134 unsigned Insn, 135 uint64_t Address, 136 const void *Decoder); 137 138 static DecodeStatus DecodeL2RInstruction(MCInst &Inst, 139 unsigned Insn, 140 uint64_t Address, 141 const void *Decoder); 142 143 static DecodeStatus DecodeLR2RInstruction(MCInst &Inst, 144 unsigned Insn, 145 uint64_t Address, 146 const void *Decoder); 147 148 static DecodeStatus Decode3RInstruction(MCInst &Inst, 149 unsigned Insn, 150 uint64_t Address, 151 const void *Decoder); 152 153 static DecodeStatus Decode3RImmInstruction(MCInst &Inst, 154 unsigned Insn, 155 uint64_t Address, 156 const void *Decoder); 157 158 static DecodeStatus Decode2RUSInstruction(MCInst &Inst, 159 unsigned Insn, 160 uint64_t Address, 161 const void *Decoder); 162 163 static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst, 164 unsigned Insn, 165 uint64_t Address, 166 const void *Decoder); 167 168 static DecodeStatus DecodeL3RInstruction(MCInst &Inst, 169 unsigned Insn, 170 uint64_t Address, 171 const void *Decoder); 172 173 static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst, 174 unsigned Insn, 175 uint64_t Address, 176 const void *Decoder); 177 178 static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst, 179 unsigned Insn, 180 uint64_t Address, 181 const void *Decoder); 182 183 static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst, 184 unsigned Insn, 185 uint64_t Address, 186 const void *Decoder); 187 188 static DecodeStatus DecodeL6RInstruction(MCInst &Inst, 189 unsigned Insn, 190 uint64_t Address, 191 const void *Decoder); 192 193 static DecodeStatus DecodeL5RInstruction(MCInst &Inst, 194 unsigned Insn, 195 uint64_t Address, 196 const void *Decoder); 197 198 static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst, 199 unsigned Insn, 200 uint64_t Address, 201 const void *Decoder); 202 203 static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, 204 unsigned Insn, 205 uint64_t Address, 206 const void *Decoder); 207 208 #include "XCoreGenDisassemblerTables.inc" 209 210 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, 211 unsigned RegNo, 212 uint64_t Address, 213 const void *Decoder) 214 { 215 if (RegNo > 11) 216 return MCDisassembler::Fail; 217 unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo); 218 Inst.addOperand(MCOperand::CreateReg(Reg)); 219 return MCDisassembler::Success; 220 } 221 222 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, 223 unsigned RegNo, 224 uint64_t Address, 225 const void *Decoder) 226 { 227 if (RegNo > 15) 228 return MCDisassembler::Fail; 229 unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo); 230 Inst.addOperand(MCOperand::CreateReg(Reg)); 231 return MCDisassembler::Success; 232 } 233 234 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, 235 uint64_t Address, const void *Decoder) { 236 if (Val > 11) 237 return MCDisassembler::Fail; 238 static unsigned Values[] = { 239 32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32 240 }; 241 Inst.addOperand(MCOperand::CreateImm(Values[Val])); 242 return MCDisassembler::Success; 243 } 244 245 static DecodeStatus DecodeMEMiiOperand(MCInst &Inst, unsigned Val, 246 uint64_t Address, const void *Decoder) { 247 Inst.addOperand(MCOperand::CreateImm(Val)); 248 Inst.addOperand(MCOperand::CreateImm(0)); 249 return MCDisassembler::Success; 250 } 251 252 static DecodeStatus 253 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { 254 unsigned Combined = fieldFromInstruction(Insn, 6, 5); 255 if (Combined < 27) 256 return MCDisassembler::Fail; 257 if (fieldFromInstruction(Insn, 5, 1)) { 258 if (Combined == 31) 259 return MCDisassembler::Fail; 260 Combined += 5; 261 } 262 Combined -= 27; 263 unsigned Op1High = Combined % 3; 264 unsigned Op2High = Combined / 3; 265 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2); 266 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2); 267 return MCDisassembler::Success; 268 } 269 270 static DecodeStatus 271 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, 272 unsigned &Op3) { 273 unsigned Combined = fieldFromInstruction(Insn, 6, 5); 274 if (Combined >= 27) 275 return MCDisassembler::Fail; 276 277 unsigned Op1High = Combined % 3; 278 unsigned Op2High = (Combined / 3) % 3; 279 unsigned Op3High = Combined / 9; 280 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2); 281 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2); 282 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2); 283 return MCDisassembler::Success; 284 } 285 286 static DecodeStatus 287 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, 288 const void *Decoder) { 289 // Try and decode as a 3R instruction. 290 unsigned Opcode = fieldFromInstruction(Insn, 11, 5); 291 switch (Opcode) { 292 case 0x0: 293 Inst.setOpcode(XCore::STW_2rus); 294 return Decode2RUSInstruction(Inst, Insn, Address, Decoder); 295 case 0x1: 296 Inst.setOpcode(XCore::LDW_2rus); 297 return Decode2RUSInstruction(Inst, Insn, Address, Decoder); 298 case 0x2: 299 Inst.setOpcode(XCore::ADD_3r); 300 return Decode3RInstruction(Inst, Insn, Address, Decoder); 301 case 0x3: 302 Inst.setOpcode(XCore::SUB_3r); 303 return Decode3RInstruction(Inst, Insn, Address, Decoder); 304 case 0x4: 305 Inst.setOpcode(XCore::SHL_3r); 306 return Decode3RInstruction(Inst, Insn, Address, Decoder); 307 case 0x5: 308 Inst.setOpcode(XCore::SHR_3r); 309 return Decode3RInstruction(Inst, Insn, Address, Decoder); 310 case 0x6: 311 Inst.setOpcode(XCore::EQ_3r); 312 return Decode3RInstruction(Inst, Insn, Address, Decoder); 313 case 0x7: 314 Inst.setOpcode(XCore::AND_3r); 315 return Decode3RInstruction(Inst, Insn, Address, Decoder); 316 case 0x8: 317 Inst.setOpcode(XCore::OR_3r); 318 return Decode3RInstruction(Inst, Insn, Address, Decoder); 319 case 0x9: 320 Inst.setOpcode(XCore::LDW_3r); 321 return Decode3RInstruction(Inst, Insn, Address, Decoder); 322 case 0x10: 323 Inst.setOpcode(XCore::LD16S_3r); 324 return Decode3RInstruction(Inst, Insn, Address, Decoder); 325 case 0x11: 326 Inst.setOpcode(XCore::LD8U_3r); 327 return Decode3RInstruction(Inst, Insn, Address, Decoder); 328 case 0x12: 329 Inst.setOpcode(XCore::ADD_2rus); 330 return Decode2RUSInstruction(Inst, Insn, Address, Decoder); 331 case 0x13: 332 Inst.setOpcode(XCore::SUB_2rus); 333 return Decode2RUSInstruction(Inst, Insn, Address, Decoder); 334 case 0x14: 335 Inst.setOpcode(XCore::SHL_2rus); 336 return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder); 337 case 0x15: 338 Inst.setOpcode(XCore::SHR_2rus); 339 return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder); 340 case 0x16: 341 Inst.setOpcode(XCore::EQ_2rus); 342 return Decode2RUSInstruction(Inst, Insn, Address, Decoder); 343 case 0x17: 344 Inst.setOpcode(XCore::TSETR_3r); 345 return Decode3RImmInstruction(Inst, Insn, Address, Decoder); 346 case 0x18: 347 Inst.setOpcode(XCore::LSS_3r); 348 return Decode3RInstruction(Inst, Insn, Address, Decoder); 349 case 0x19: 350 Inst.setOpcode(XCore::LSU_3r); 351 return Decode3RInstruction(Inst, Insn, Address, Decoder); 352 } 353 return MCDisassembler::Fail; 354 } 355 356 static DecodeStatus 357 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 358 const void *Decoder) { 359 unsigned Op1, Op2; 360 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 361 if (S != MCDisassembler::Success) 362 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 363 364 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 365 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 366 return S; 367 } 368 369 static DecodeStatus 370 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 371 const void *Decoder) { 372 unsigned Op1, Op2; 373 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 374 if (S != MCDisassembler::Success) 375 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 376 377 Inst.addOperand(MCOperand::CreateImm(Op1)); 378 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 379 return S; 380 } 381 382 static DecodeStatus 383 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 384 const void *Decoder) { 385 unsigned Op1, Op2; 386 DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1); 387 if (S != MCDisassembler::Success) 388 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 389 390 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 391 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 392 return S; 393 } 394 395 static DecodeStatus 396 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 397 const void *Decoder) { 398 unsigned Op1, Op2; 399 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 400 if (S != MCDisassembler::Success) 401 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 402 403 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 404 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 405 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 406 return S; 407 } 408 409 static DecodeStatus 410 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 411 const void *Decoder) { 412 unsigned Op1, Op2; 413 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 414 if (S != MCDisassembler::Success) 415 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 416 417 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 418 Inst.addOperand(MCOperand::CreateImm(Op2)); 419 return S; 420 } 421 422 static DecodeStatus 423 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 424 const void *Decoder) { 425 unsigned Op1, Op2; 426 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 427 if (S != MCDisassembler::Success) 428 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 429 430 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 431 DecodeBitpOperand(Inst, Op2, Address, Decoder); 432 return S; 433 } 434 435 static DecodeStatus 436 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 437 const void *Decoder) { 438 unsigned Op1, Op2; 439 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); 440 if (S != MCDisassembler::Success) 441 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder); 442 443 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 444 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 445 DecodeBitpOperand(Inst, Op2, Address, Decoder); 446 return S; 447 } 448 449 static DecodeStatus 450 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, 451 const void *Decoder) { 452 // Try and decode as a L3R / L2RUS instruction. 453 unsigned Opcode = fieldFromInstruction(Insn, 16, 4) | 454 fieldFromInstruction(Insn, 27, 5) << 4; 455 switch (Opcode) { 456 case 0x0c: 457 Inst.setOpcode(XCore::STW_l3r); 458 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 459 case 0x1c: 460 Inst.setOpcode(XCore::XOR_l3r); 461 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 462 case 0x2c: 463 Inst.setOpcode(XCore::ASHR_l3r); 464 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 465 case 0x3c: 466 Inst.setOpcode(XCore::LDAWF_l3r); 467 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 468 case 0x4c: 469 Inst.setOpcode(XCore::LDAWB_l3r); 470 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 471 case 0x5c: 472 Inst.setOpcode(XCore::LDA16F_l3r); 473 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 474 case 0x6c: 475 Inst.setOpcode(XCore::LDA16B_l3r); 476 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 477 case 0x7c: 478 Inst.setOpcode(XCore::MUL_l3r); 479 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 480 case 0x8c: 481 Inst.setOpcode(XCore::DIVS_l3r); 482 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 483 case 0x9c: 484 Inst.setOpcode(XCore::DIVU_l3r); 485 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 486 case 0x10c: 487 Inst.setOpcode(XCore::ST16_l3r); 488 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 489 case 0x11c: 490 Inst.setOpcode(XCore::ST8_l3r); 491 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 492 case 0x12c: 493 Inst.setOpcode(XCore::ASHR_l2rus); 494 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); 495 case 0x12d: 496 Inst.setOpcode(XCore::OUTPW_l2rus); 497 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); 498 case 0x12e: 499 Inst.setOpcode(XCore::INPW_l2rus); 500 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder); 501 case 0x13c: 502 Inst.setOpcode(XCore::LDAWF_l2rus); 503 return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder); 504 case 0x14c: 505 Inst.setOpcode(XCore::LDAWB_l2rus); 506 return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder); 507 case 0x15c: 508 Inst.setOpcode(XCore::CRC_l3r); 509 return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder); 510 case 0x18c: 511 Inst.setOpcode(XCore::REMS_l3r); 512 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 513 case 0x19c: 514 Inst.setOpcode(XCore::REMU_l3r); 515 return DecodeL3RInstruction(Inst, Insn, Address, Decoder); 516 } 517 return MCDisassembler::Fail; 518 } 519 520 static DecodeStatus 521 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 522 const void *Decoder) { 523 unsigned Op1, Op2; 524 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16), 525 Op1, Op2); 526 if (S != MCDisassembler::Success) 527 return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder); 528 529 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 530 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 531 return S; 532 } 533 534 static DecodeStatus 535 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 536 const void *Decoder) { 537 unsigned Op1, Op2; 538 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16), 539 Op1, Op2); 540 if (S != MCDisassembler::Success) 541 return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder); 542 543 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 544 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 545 return S; 546 } 547 548 static DecodeStatus 549 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 550 const void *Decoder) { 551 unsigned Op1, Op2, Op3; 552 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); 553 if (S == MCDisassembler::Success) { 554 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 555 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 556 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 557 } 558 return S; 559 } 560 561 static DecodeStatus 562 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 563 const void *Decoder) { 564 unsigned Op1, Op2, Op3; 565 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); 566 if (S == MCDisassembler::Success) { 567 Inst.addOperand(MCOperand::CreateImm(Op1)); 568 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 569 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 570 } 571 return S; 572 } 573 574 static DecodeStatus 575 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 576 const void *Decoder) { 577 unsigned Op1, Op2, Op3; 578 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); 579 if (S == MCDisassembler::Success) { 580 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 581 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 582 Inst.addOperand(MCOperand::CreateImm(Op3)); 583 } 584 return S; 585 } 586 587 static DecodeStatus 588 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 589 const void *Decoder) { 590 unsigned Op1, Op2, Op3; 591 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); 592 if (S == MCDisassembler::Success) { 593 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 594 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 595 DecodeBitpOperand(Inst, Op3, Address, Decoder); 596 } 597 return S; 598 } 599 600 static DecodeStatus 601 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 602 const void *Decoder) { 603 unsigned Op1, Op2, Op3; 604 DecodeStatus S = 605 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 606 if (S == MCDisassembler::Success) { 607 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 608 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 609 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 610 } 611 return S; 612 } 613 614 static DecodeStatus 615 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 616 const void *Decoder) { 617 unsigned Op1, Op2, Op3; 618 DecodeStatus S = 619 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 620 if (S == MCDisassembler::Success) { 621 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 622 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 623 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 624 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 625 } 626 return S; 627 } 628 629 static DecodeStatus 630 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 631 const void *Decoder) { 632 unsigned Op1, Op2, Op3; 633 DecodeStatus S = 634 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 635 if (S == MCDisassembler::Success) { 636 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 637 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 638 Inst.addOperand(MCOperand::CreateImm(Op3)); 639 } 640 return S; 641 } 642 643 static DecodeStatus 644 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 645 const void *Decoder) { 646 unsigned Op1, Op2, Op3; 647 DecodeStatus S = 648 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 649 if (S == MCDisassembler::Success) { 650 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 651 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 652 DecodeBitpOperand(Inst, Op3, Address, Decoder); 653 } 654 return S; 655 } 656 657 static DecodeStatus 658 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 659 const void *Decoder) { 660 unsigned Op1, Op2, Op3, Op4, Op5, Op6; 661 DecodeStatus S = 662 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 663 if (S != MCDisassembler::Success) 664 return S; 665 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6); 666 if (S != MCDisassembler::Success) 667 return S; 668 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 669 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 670 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 671 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 672 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); 673 DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder); 674 return S; 675 } 676 677 static DecodeStatus 678 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, 679 const void *Decoder) { 680 // Try and decode as a L6R instruction. 681 Inst.clear(); 682 unsigned Opcode = fieldFromInstruction(Insn, 27, 5); 683 switch (Opcode) { 684 case 0x00: 685 Inst.setOpcode(XCore::LMUL_l6r); 686 return DecodeL6RInstruction(Inst, Insn, Address, Decoder); 687 } 688 return MCDisassembler::Fail; 689 } 690 691 static DecodeStatus 692 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 693 const void *Decoder) { 694 unsigned Op1, Op2, Op3, Op4, Op5; 695 DecodeStatus S = 696 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 697 if (S != MCDisassembler::Success) 698 return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder); 699 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5); 700 if (S != MCDisassembler::Success) 701 return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder); 702 703 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 704 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 705 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 706 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 707 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); 708 return S; 709 } 710 711 static DecodeStatus 712 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 713 const void *Decoder) { 714 unsigned Op1, Op2, Op3; 715 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); 716 DecodeStatus S = 717 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 718 if (S == MCDisassembler::Success) { 719 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 720 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 721 } 722 if (S == MCDisassembler::Success) { 723 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 724 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 725 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 726 } 727 return S; 728 } 729 730 static DecodeStatus 731 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 732 const void *Decoder) { 733 unsigned Op1, Op2, Op3; 734 unsigned Op4 = fieldFromInstruction(Insn, 16, 4); 735 DecodeStatus S = 736 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); 737 if (S == MCDisassembler::Success) { 738 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 739 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 740 } 741 if (S == MCDisassembler::Success) { 742 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); 743 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); 744 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); 745 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 746 } 747 return S; 748 } 749 750 MCDisassembler::DecodeStatus 751 XCoreDisassembler::getInstruction(MCInst &instr, 752 uint64_t &Size, 753 const MemoryObject &Region, 754 uint64_t Address, 755 raw_ostream &vStream, 756 raw_ostream &cStream) const { 757 uint16_t insn16; 758 759 if (!readInstruction16(Region, Address, Size, insn16)) { 760 return Fail; 761 } 762 763 // Calling the auto-generated decoder function. 764 DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16, 765 Address, this, STI); 766 if (Result != Fail) { 767 Size = 2; 768 return Result; 769 } 770 771 uint32_t insn32; 772 773 if (!readInstruction32(Region, Address, Size, insn32)) { 774 return Fail; 775 } 776 777 // Calling the auto-generated decoder function. 778 Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI); 779 if (Result != Fail) { 780 Size = 4; 781 return Result; 782 } 783 784 return Fail; 785 } 786 787 namespace llvm { 788 extern Target TheXCoreTarget; 789 } 790 791 static MCDisassembler *createXCoreDisassembler(const Target &T, 792 const MCSubtargetInfo &STI) { 793 return new XCoreDisassembler(STI, T.createMCRegInfo("")); 794 } 795 796 extern "C" void LLVMInitializeXCoreDisassembler() { 797 // Register the disassembler. 798 TargetRegistry::RegisterMCDisassembler(TheXCoreTarget, 799 createXCoreDisassembler); 800 } 801