1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/InstIterator.h" 47 #include "llvm/IR/IntrinsicInst.h" 48 #include "llvm/Support/Debug.h" 49 50 using namespace llvm; 51 52 #define DEBUG_TYPE "x86tti" 53 54 //===----------------------------------------------------------------------===// 55 // 56 // X86 cost model. 57 // 58 //===----------------------------------------------------------------------===// 59 60 TargetTransformInfo::PopcntSupportKind 61 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 62 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 63 // TODO: Currently the __builtin_popcount() implementation using SSE3 64 // instructions is inefficient. Once the problem is fixed, we should 65 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 66 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 67 } 68 69 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 70 TargetTransformInfo::CacheLevel Level) const { 71 switch (Level) { 72 case TargetTransformInfo::CacheLevel::L1D: 73 // - Penryn 74 // - Nehalem 75 // - Westmere 76 // - Sandy Bridge 77 // - Ivy Bridge 78 // - Haswell 79 // - Broadwell 80 // - Skylake 81 // - Kabylake 82 return 32 * 1024; // 32 KByte 83 case TargetTransformInfo::CacheLevel::L2D: 84 // - Penryn 85 // - Nehalem 86 // - Westmere 87 // - Sandy Bridge 88 // - Ivy Bridge 89 // - Haswell 90 // - Broadwell 91 // - Skylake 92 // - Kabylake 93 return 256 * 1024; // 256 KByte 94 } 95 96 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 97 } 98 99 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 100 TargetTransformInfo::CacheLevel Level) const { 101 // - Penryn 102 // - Nehalem 103 // - Westmere 104 // - Sandy Bridge 105 // - Ivy Bridge 106 // - Haswell 107 // - Broadwell 108 // - Skylake 109 // - Kabylake 110 switch (Level) { 111 case TargetTransformInfo::CacheLevel::L1D: 112 LLVM_FALLTHROUGH; 113 case TargetTransformInfo::CacheLevel::L2D: 114 return 8; 115 } 116 117 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 118 } 119 120 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 121 bool Vector = (ClassID == 1); 122 if (Vector && !ST->hasSSE1()) 123 return 0; 124 125 if (ST->is64Bit()) { 126 if (Vector && ST->hasAVX512()) 127 return 32; 128 return 16; 129 } 130 return 8; 131 } 132 133 TypeSize 134 X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { 135 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 136 switch (K) { 137 case TargetTransformInfo::RGK_Scalar: 138 return TypeSize::getFixed(ST->is64Bit() ? 64 : 32); 139 case TargetTransformInfo::RGK_FixedWidthVector: 140 if (ST->hasAVX512() && PreferVectorWidth >= 512) 141 return TypeSize::getFixed(512); 142 if (ST->hasAVX() && PreferVectorWidth >= 256) 143 return TypeSize::getFixed(256); 144 if (ST->hasSSE1() && PreferVectorWidth >= 128) 145 return TypeSize::getFixed(128); 146 return TypeSize::getFixed(0); 147 case TargetTransformInfo::RGK_ScalableVector: 148 return TypeSize::getScalable(0); 149 } 150 151 llvm_unreachable("Unsupported register kind"); 152 } 153 154 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 155 return getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector) 156 .getFixedSize(); 157 } 158 159 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 160 // If the loop will not be vectorized, don't interleave the loop. 161 // Let regular unroll to unroll the loop, which saves the overflow 162 // check and memory check cost. 163 if (VF == 1) 164 return 1; 165 166 if (ST->isAtom()) 167 return 1; 168 169 // Sandybridge and Haswell have multiple execution ports and pipelined 170 // vector units. 171 if (ST->hasAVX()) 172 return 4; 173 174 return 2; 175 } 176 177 InstructionCost X86TTIImpl::getArithmeticInstrCost( 178 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, 179 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 180 TTI::OperandValueProperties Opd1PropInfo, 181 TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, 182 const Instruction *CxtI) { 183 // TODO: Handle more cost kinds. 184 if (CostKind != TTI::TCK_RecipThroughput) 185 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, 186 Op2Info, Opd1PropInfo, 187 Opd2PropInfo, Args, CxtI); 188 189 // vXi8 multiplications are always promoted to vXi16. 190 if (Opcode == Instruction::Mul && Ty->isVectorTy() && 191 Ty->getScalarSizeInBits() == 8) { 192 Type *WideVecTy = 193 VectorType::getExtendedElementVectorType(cast<VectorType>(Ty)); 194 return getCastInstrCost(Instruction::ZExt, WideVecTy, Ty, 195 TargetTransformInfo::CastContextHint::None, 196 CostKind) + 197 getCastInstrCost(Instruction::Trunc, Ty, WideVecTy, 198 TargetTransformInfo::CastContextHint::None, 199 CostKind) + 200 getArithmeticInstrCost(Opcode, WideVecTy, CostKind, Op1Info, Op2Info, 201 Opd1PropInfo, Opd2PropInfo); 202 } 203 204 // Legalize the type. 205 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 206 207 int ISD = TLI->InstructionOpcodeToISD(Opcode); 208 assert(ISD && "Invalid opcode"); 209 210 if (ISD == ISD::MUL && Args.size() == 2 && LT.second.isVector() && 211 LT.second.getScalarType() == MVT::i32) { 212 // Check if the operands can be represented as a smaller datatype. 213 bool Op1Signed = false, Op2Signed = false; 214 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 215 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 216 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 217 218 // If both are representable as i15 and at least one is constant, 219 // zero-extended, or sign-extended from vXi16 (or less pre-SSE41) then we 220 // can treat this as PMADDWD which has the same costs as a vXi16 multiply. 221 if (OpMinSize <= 15 && !ST->isPMADDWDSlow()) { 222 bool Op1Constant = 223 isa<ConstantDataVector>(Args[0]) || isa<ConstantVector>(Args[0]); 224 bool Op2Constant = 225 isa<ConstantDataVector>(Args[1]) || isa<ConstantVector>(Args[1]); 226 bool Op1Sext = isa<SExtInst>(Args[0]) && 227 (Op1MinSize == 15 || (Op1MinSize < 15 && !ST->hasSSE41())); 228 bool Op2Sext = isa<SExtInst>(Args[1]) && 229 (Op2MinSize == 15 || (Op2MinSize < 15 && !ST->hasSSE41())); 230 231 bool IsZeroExtended = !Op1Signed || !Op2Signed; 232 bool IsConstant = Op1Constant || Op2Constant; 233 bool IsSext = Op1Sext || Op2Sext; 234 if (IsConstant || IsZeroExtended || IsSext) 235 LT.second = 236 MVT::getVectorVT(MVT::i16, 2 * LT.second.getVectorNumElements()); 237 } 238 } 239 240 // Vector multiply by pow2 will be simplified to shifts. 241 if (ISD == ISD::MUL && 242 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 243 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 244 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) 245 return getArithmeticInstrCost(Instruction::Shl, Ty, CostKind, Op1Info, 246 Op2Info, TargetTransformInfo::OP_None, 247 TargetTransformInfo::OP_None); 248 249 // On X86, vector signed division by constants power-of-two are 250 // normally expanded to the sequence SRA + SRL + ADD + SRA. 251 // The OperandValue properties may not be the same as that of the previous 252 // operation; conservatively assume OP_None. 253 if ((ISD == ISD::SDIV || ISD == ISD::SREM) && 254 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 255 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 256 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 257 InstructionCost Cost = 258 2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Op1Info, 259 Op2Info, TargetTransformInfo::OP_None, 260 TargetTransformInfo::OP_None); 261 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 262 Op2Info, TargetTransformInfo::OP_None, 263 TargetTransformInfo::OP_None); 264 Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind, Op1Info, 265 Op2Info, TargetTransformInfo::OP_None, 266 TargetTransformInfo::OP_None); 267 268 if (ISD == ISD::SREM) { 269 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 270 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info, 271 Op2Info); 272 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info, 273 Op2Info); 274 } 275 276 return Cost; 277 } 278 279 // Vector unsigned division/remainder will be simplified to shifts/masks. 280 if ((ISD == ISD::UDIV || ISD == ISD::UREM) && 281 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 282 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 283 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 284 if (ISD == ISD::UDIV) 285 return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 286 Op2Info, TargetTransformInfo::OP_None, 287 TargetTransformInfo::OP_None); 288 // UREM 289 return getArithmeticInstrCost(Instruction::And, Ty, CostKind, Op1Info, 290 Op2Info, TargetTransformInfo::OP_None, 291 TargetTransformInfo::OP_None); 292 } 293 294 static const CostTblEntry GLMCostTable[] = { 295 { ISD::FDIV, MVT::f32, 18 }, // divss 296 { ISD::FDIV, MVT::v4f32, 35 }, // divps 297 { ISD::FDIV, MVT::f64, 33 }, // divsd 298 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 299 }; 300 301 if (ST->useGLMDivSqrtCosts()) 302 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 303 LT.second)) 304 return LT.first * Entry->Cost; 305 306 static const CostTblEntry SLMCostTable[] = { 307 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 308 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 309 { ISD::FMUL, MVT::f64, 2 }, // mulsd 310 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 311 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 312 { ISD::FDIV, MVT::f32, 17 }, // divss 313 { ISD::FDIV, MVT::v4f32, 39 }, // divps 314 { ISD::FDIV, MVT::f64, 32 }, // divsd 315 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 316 { ISD::FADD, MVT::v2f64, 2 }, // addpd 317 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 318 // v2i64/v4i64 mul is custom lowered as a series of long: 319 // multiplies(3), shifts(3) and adds(2) 320 // slm muldq version throughput is 2 and addq throughput 4 321 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 322 // 3X4 (addq throughput) = 17 323 { ISD::MUL, MVT::v2i64, 17 }, 324 // slm addq\subq throughput is 4 325 { ISD::ADD, MVT::v2i64, 4 }, 326 { ISD::SUB, MVT::v2i64, 4 }, 327 }; 328 329 if (ST->useSLMArithCosts()) { 330 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 331 // Check if the operands can be shrinked into a smaller datatype. 332 // TODO: Merge this into generiic vXi32 MUL patterns above. 333 bool Op1Signed = false; 334 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 335 bool Op2Signed = false; 336 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 337 338 bool SignedMode = Op1Signed || Op2Signed; 339 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 340 341 if (OpMinSize <= 7) 342 return LT.first * 3; // pmullw/sext 343 if (!SignedMode && OpMinSize <= 8) 344 return LT.first * 3; // pmullw/zext 345 if (OpMinSize <= 15) 346 return LT.first * 5; // pmullw/pmulhw/pshuf 347 if (!SignedMode && OpMinSize <= 16) 348 return LT.first * 5; // pmullw/pmulhw/pshuf 349 } 350 351 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 352 LT.second)) { 353 return LT.first * Entry->Cost; 354 } 355 } 356 357 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 358 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 359 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 360 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 361 }; 362 363 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 364 ST->hasBWI()) { 365 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 366 LT.second)) 367 return LT.first * Entry->Cost; 368 } 369 370 static const CostTblEntry AVX512UniformConstCostTable[] = { 371 { ISD::SRA, MVT::v2i64, 1 }, 372 { ISD::SRA, MVT::v4i64, 1 }, 373 { ISD::SRA, MVT::v8i64, 1 }, 374 375 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 376 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 377 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 378 379 { ISD::SDIV, MVT::v16i32, 6 }, // pmuludq sequence 380 { ISD::SREM, MVT::v16i32, 8 }, // pmuludq+mul+sub sequence 381 { ISD::UDIV, MVT::v16i32, 5 }, // pmuludq sequence 382 { ISD::UREM, MVT::v16i32, 7 }, // pmuludq+mul+sub sequence 383 }; 384 385 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 386 ST->hasAVX512()) { 387 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 388 LT.second)) 389 return LT.first * Entry->Cost; 390 } 391 392 static const CostTblEntry AVX2UniformConstCostTable[] = { 393 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 394 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 395 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 396 397 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 398 399 { ISD::SDIV, MVT::v8i32, 6 }, // pmuludq sequence 400 { ISD::SREM, MVT::v8i32, 8 }, // pmuludq+mul+sub sequence 401 { ISD::UDIV, MVT::v8i32, 5 }, // pmuludq sequence 402 { ISD::UREM, MVT::v8i32, 7 }, // pmuludq+mul+sub sequence 403 }; 404 405 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 406 ST->hasAVX2()) { 407 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 408 LT.second)) 409 return LT.first * Entry->Cost; 410 } 411 412 static const CostTblEntry SSE2UniformConstCostTable[] = { 413 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 414 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 415 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 416 417 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 418 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 419 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 420 421 { ISD::SDIV, MVT::v8i32, 12+2 }, // 2*pmuludq sequence + split. 422 { ISD::SREM, MVT::v8i32, 16+2 }, // 2*pmuludq+mul+sub sequence + split. 423 { ISD::SDIV, MVT::v4i32, 6 }, // pmuludq sequence 424 { ISD::SREM, MVT::v4i32, 8 }, // pmuludq+mul+sub sequence 425 { ISD::UDIV, MVT::v8i32, 10+2 }, // 2*pmuludq sequence + split. 426 { ISD::UREM, MVT::v8i32, 14+2 }, // 2*pmuludq+mul+sub sequence + split. 427 { ISD::UDIV, MVT::v4i32, 5 }, // pmuludq sequence 428 { ISD::UREM, MVT::v4i32, 7 }, // pmuludq+mul+sub sequence 429 }; 430 431 // XOP has faster vXi8 shifts. 432 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 433 ST->hasSSE2() && !ST->hasXOP()) { 434 if (const auto *Entry = 435 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 436 return LT.first * Entry->Cost; 437 } 438 439 static const CostTblEntry AVX512BWConstCostTable[] = { 440 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 441 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 442 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 443 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 444 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 445 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 446 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 447 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 448 }; 449 450 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 451 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 452 ST->hasBWI()) { 453 if (const auto *Entry = 454 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 455 return LT.first * Entry->Cost; 456 } 457 458 static const CostTblEntry AVX512ConstCostTable[] = { 459 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 460 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 461 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 462 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 463 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 464 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 465 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 466 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 467 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 468 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 469 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 470 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 471 }; 472 473 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 474 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 475 ST->hasAVX512()) { 476 if (const auto *Entry = 477 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 478 return LT.first * Entry->Cost; 479 } 480 481 static const CostTblEntry AVX2ConstCostTable[] = { 482 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 483 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 484 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 485 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 486 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 487 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 488 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 489 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 490 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 491 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 492 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 493 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 494 }; 495 496 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 497 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 498 ST->hasAVX2()) { 499 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 500 return LT.first * Entry->Cost; 501 } 502 503 static const CostTblEntry SSE2ConstCostTable[] = { 504 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 505 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 506 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 507 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 508 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 509 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 510 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 511 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 512 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 513 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 514 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 515 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 516 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 517 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 518 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 519 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 520 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 521 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 522 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 523 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 524 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 525 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 526 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 527 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 528 }; 529 530 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 531 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 532 ST->hasSSE2()) { 533 // pmuldq sequence. 534 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 535 return LT.first * 32; 536 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 537 return LT.first * 38; 538 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 539 return LT.first * 15; 540 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 541 return LT.first * 20; 542 543 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 544 return LT.first * Entry->Cost; 545 } 546 547 static const CostTblEntry AVX512BWShiftCostTable[] = { 548 { ISD::SHL, MVT::v16i8, 4 }, // extend/vpsllvw/pack sequence. 549 { ISD::SRL, MVT::v16i8, 4 }, // extend/vpsrlvw/pack sequence. 550 { ISD::SRA, MVT::v16i8, 4 }, // extend/vpsravw/pack sequence. 551 { ISD::SHL, MVT::v32i8, 4 }, // extend/vpsllvw/pack sequence. 552 { ISD::SRL, MVT::v32i8, 4 }, // extend/vpsrlvw/pack sequence. 553 { ISD::SRA, MVT::v32i8, 6 }, // extend/vpsravw/pack sequence. 554 { ISD::SHL, MVT::v64i8, 6 }, // extend/vpsllvw/pack sequence. 555 { ISD::SRL, MVT::v64i8, 7 }, // extend/vpsrlvw/pack sequence. 556 { ISD::SRA, MVT::v64i8, 15 }, // extend/vpsravw/pack sequence. 557 558 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 559 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 560 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 561 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 562 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 563 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 564 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 565 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 566 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 567 }; 568 569 if (ST->hasBWI()) 570 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 571 return LT.first * Entry->Cost; 572 573 static const CostTblEntry AVX2UniformCostTable[] = { 574 // Uniform splats are cheaper for the following instructions. 575 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 576 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 577 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 578 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 579 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 580 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 581 582 { ISD::SHL, MVT::v8i32, 1 }, // pslld 583 { ISD::SRL, MVT::v8i32, 1 }, // psrld 584 { ISD::SRA, MVT::v8i32, 1 }, // psrad 585 { ISD::SHL, MVT::v4i64, 1 }, // psllq 586 { ISD::SRL, MVT::v4i64, 1 }, // psrlq 587 }; 588 589 if (ST->hasAVX2() && 590 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 591 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 592 if (const auto *Entry = 593 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 594 return LT.first * Entry->Cost; 595 } 596 597 static const CostTblEntry SSE2UniformCostTable[] = { 598 // Uniform splats are cheaper for the following instructions. 599 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 600 { ISD::SHL, MVT::v4i32, 1 }, // pslld 601 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 602 603 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 604 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 605 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 606 607 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 608 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 609 }; 610 611 if (ST->hasSSE2() && 612 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 613 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 614 if (const auto *Entry = 615 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 616 return LT.first * Entry->Cost; 617 } 618 619 static const CostTblEntry AVX512DQCostTable[] = { 620 { ISD::MUL, MVT::v2i64, 2 }, // pmullq 621 { ISD::MUL, MVT::v4i64, 2 }, // pmullq 622 { ISD::MUL, MVT::v8i64, 2 } // pmullq 623 }; 624 625 // Look for AVX512DQ lowering tricks for custom cases. 626 if (ST->hasDQI()) 627 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 628 return LT.first * Entry->Cost; 629 630 static const CostTblEntry AVX512BWCostTable[] = { 631 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 632 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 633 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 634 }; 635 636 // Look for AVX512BW lowering tricks for custom cases. 637 if (ST->hasBWI()) 638 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 639 return LT.first * Entry->Cost; 640 641 static const CostTblEntry AVX512CostTable[] = { 642 { ISD::SHL, MVT::v4i32, 1 }, 643 { ISD::SRL, MVT::v4i32, 1 }, 644 { ISD::SRA, MVT::v4i32, 1 }, 645 { ISD::SHL, MVT::v8i32, 1 }, 646 { ISD::SRL, MVT::v8i32, 1 }, 647 { ISD::SRA, MVT::v8i32, 1 }, 648 { ISD::SHL, MVT::v16i32, 1 }, 649 { ISD::SRL, MVT::v16i32, 1 }, 650 { ISD::SRA, MVT::v16i32, 1 }, 651 652 { ISD::SHL, MVT::v2i64, 1 }, 653 { ISD::SRL, MVT::v2i64, 1 }, 654 { ISD::SHL, MVT::v4i64, 1 }, 655 { ISD::SRL, MVT::v4i64, 1 }, 656 { ISD::SHL, MVT::v8i64, 1 }, 657 { ISD::SRL, MVT::v8i64, 1 }, 658 659 { ISD::SRA, MVT::v2i64, 1 }, 660 { ISD::SRA, MVT::v4i64, 1 }, 661 { ISD::SRA, MVT::v8i64, 1 }, 662 663 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 664 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 665 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 666 { ISD::MUL, MVT::v8i64, 6 }, // 3*pmuludq/3*shift/2*add 667 { ISD::MUL, MVT::i64, 1 }, // Skylake from http://www.agner.org/ 668 669 { ISD::FNEG, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 670 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 671 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 672 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 673 { ISD::FDIV, MVT::f64, 4 }, // Skylake from http://www.agner.org/ 674 { ISD::FDIV, MVT::v2f64, 4 }, // Skylake from http://www.agner.org/ 675 { ISD::FDIV, MVT::v4f64, 8 }, // Skylake from http://www.agner.org/ 676 { ISD::FDIV, MVT::v8f64, 16 }, // Skylake from http://www.agner.org/ 677 678 { ISD::FNEG, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 679 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 680 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 681 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 682 { ISD::FDIV, MVT::f32, 3 }, // Skylake from http://www.agner.org/ 683 { ISD::FDIV, MVT::v4f32, 3 }, // Skylake from http://www.agner.org/ 684 { ISD::FDIV, MVT::v8f32, 5 }, // Skylake from http://www.agner.org/ 685 { ISD::FDIV, MVT::v16f32, 10 }, // Skylake from http://www.agner.org/ 686 }; 687 688 if (ST->hasAVX512()) 689 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 690 return LT.first * Entry->Cost; 691 692 static const CostTblEntry AVX2ShiftCostTable[] = { 693 // Shifts on vXi64/vXi32 on AVX2 is legal even though we declare to 694 // customize them to detect the cases where shift amount is a scalar one. 695 { ISD::SHL, MVT::v4i32, 2 }, // vpsllvd (Haswell from agner.org) 696 { ISD::SRL, MVT::v4i32, 2 }, // vpsrlvd (Haswell from agner.org) 697 { ISD::SRA, MVT::v4i32, 2 }, // vpsravd (Haswell from agner.org) 698 { ISD::SHL, MVT::v8i32, 2 }, // vpsllvd (Haswell from agner.org) 699 { ISD::SRL, MVT::v8i32, 2 }, // vpsrlvd (Haswell from agner.org) 700 { ISD::SRA, MVT::v8i32, 2 }, // vpsravd (Haswell from agner.org) 701 { ISD::SHL, MVT::v2i64, 1 }, // vpsllvq (Haswell from agner.org) 702 { ISD::SRL, MVT::v2i64, 1 }, // vpsrlvq (Haswell from agner.org) 703 { ISD::SHL, MVT::v4i64, 1 }, // vpsllvq (Haswell from agner.org) 704 { ISD::SRL, MVT::v4i64, 1 }, // vpsrlvq (Haswell from agner.org) 705 }; 706 707 if (ST->hasAVX512()) { 708 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 709 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 710 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 711 // On AVX512, a packed v32i16 shift left by a constant build_vector 712 // is lowered into a vector multiply (vpmullw). 713 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 714 Op1Info, Op2Info, 715 TargetTransformInfo::OP_None, 716 TargetTransformInfo::OP_None); 717 } 718 719 // Look for AVX2 lowering tricks (XOP is always better at v4i32 shifts). 720 if (ST->hasAVX2() && !(ST->hasXOP() && LT.second == MVT::v4i32)) { 721 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 722 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 723 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 724 // On AVX2, a packed v16i16 shift left by a constant build_vector 725 // is lowered into a vector multiply (vpmullw). 726 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 727 Op1Info, Op2Info, 728 TargetTransformInfo::OP_None, 729 TargetTransformInfo::OP_None); 730 731 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 732 return LT.first * Entry->Cost; 733 } 734 735 static const CostTblEntry XOPShiftCostTable[] = { 736 // 128bit shifts take 1cy, but right shifts require negation beforehand. 737 { ISD::SHL, MVT::v16i8, 1 }, 738 { ISD::SRL, MVT::v16i8, 2 }, 739 { ISD::SRA, MVT::v16i8, 2 }, 740 { ISD::SHL, MVT::v8i16, 1 }, 741 { ISD::SRL, MVT::v8i16, 2 }, 742 { ISD::SRA, MVT::v8i16, 2 }, 743 { ISD::SHL, MVT::v4i32, 1 }, 744 { ISD::SRL, MVT::v4i32, 2 }, 745 { ISD::SRA, MVT::v4i32, 2 }, 746 { ISD::SHL, MVT::v2i64, 1 }, 747 { ISD::SRL, MVT::v2i64, 2 }, 748 { ISD::SRA, MVT::v2i64, 2 }, 749 // 256bit shifts require splitting if AVX2 didn't catch them above. 750 { ISD::SHL, MVT::v32i8, 2+2 }, 751 { ISD::SRL, MVT::v32i8, 4+2 }, 752 { ISD::SRA, MVT::v32i8, 4+2 }, 753 { ISD::SHL, MVT::v16i16, 2+2 }, 754 { ISD::SRL, MVT::v16i16, 4+2 }, 755 { ISD::SRA, MVT::v16i16, 4+2 }, 756 { ISD::SHL, MVT::v8i32, 2+2 }, 757 { ISD::SRL, MVT::v8i32, 4+2 }, 758 { ISD::SRA, MVT::v8i32, 4+2 }, 759 { ISD::SHL, MVT::v4i64, 2+2 }, 760 { ISD::SRL, MVT::v4i64, 4+2 }, 761 { ISD::SRA, MVT::v4i64, 4+2 }, 762 }; 763 764 // Look for XOP lowering tricks. 765 if (ST->hasXOP()) { 766 // If the right shift is constant then we'll fold the negation so 767 // it's as cheap as a left shift. 768 int ShiftISD = ISD; 769 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 770 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 771 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 772 ShiftISD = ISD::SHL; 773 if (const auto *Entry = 774 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 775 return LT.first * Entry->Cost; 776 } 777 778 static const CostTblEntry SSE2UniformShiftCostTable[] = { 779 // Uniform splats are cheaper for the following instructions. 780 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 781 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 782 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 783 784 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 785 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 786 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 787 788 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 789 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 790 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 791 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 792 }; 793 794 if (ST->hasSSE2() && 795 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 796 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 797 798 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 799 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 800 return LT.first * 4; // 2*psrad + shuffle. 801 802 if (const auto *Entry = 803 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 804 return LT.first * Entry->Cost; 805 } 806 807 if (ISD == ISD::SHL && 808 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 809 MVT VT = LT.second; 810 // Vector shift left by non uniform constant can be lowered 811 // into vector multiply. 812 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 813 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 814 ISD = ISD::MUL; 815 } 816 817 static const CostTblEntry AVX2CostTable[] = { 818 { ISD::SHL, MVT::v16i8, 6 }, // vpblendvb sequence. 819 { ISD::SHL, MVT::v32i8, 6 }, // vpblendvb sequence. 820 { ISD::SHL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 821 { ISD::SHL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 822 { ISD::SHL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 823 { ISD::SHL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 824 825 { ISD::SRL, MVT::v16i8, 6 }, // vpblendvb sequence. 826 { ISD::SRL, MVT::v32i8, 6 }, // vpblendvb sequence. 827 { ISD::SRL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 828 { ISD::SRL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 829 { ISD::SRL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 830 { ISD::SRL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 831 832 { ISD::SRA, MVT::v16i8, 17 }, // vpblendvb sequence. 833 { ISD::SRA, MVT::v32i8, 17 }, // vpblendvb sequence. 834 { ISD::SRA, MVT::v64i8, 34 }, // 2*vpblendvb sequence. 835 { ISD::SRA, MVT::v8i16, 5 }, // extend/vpsravd/pack sequence. 836 { ISD::SRA, MVT::v16i16, 7 }, // extend/vpsravd/pack sequence. 837 { ISD::SRA, MVT::v32i16, 14 }, // 2*extend/vpsravd/pack sequence. 838 { ISD::SRA, MVT::v2i64, 2 }, // srl/xor/sub sequence. 839 { ISD::SRA, MVT::v4i64, 2 }, // srl/xor/sub sequence. 840 841 { ISD::SUB, MVT::v32i8, 1 }, // psubb 842 { ISD::ADD, MVT::v32i8, 1 }, // paddb 843 { ISD::SUB, MVT::v16i16, 1 }, // psubw 844 { ISD::ADD, MVT::v16i16, 1 }, // paddw 845 { ISD::SUB, MVT::v8i32, 1 }, // psubd 846 { ISD::ADD, MVT::v8i32, 1 }, // paddd 847 { ISD::SUB, MVT::v4i64, 1 }, // psubq 848 { ISD::ADD, MVT::v4i64, 1 }, // paddq 849 850 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 851 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 852 { ISD::MUL, MVT::v4i64, 6 }, // 3*pmuludq/3*shift/2*add 853 854 { ISD::FNEG, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 855 { ISD::FNEG, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 856 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 857 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 858 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 859 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 860 { ISD::FMUL, MVT::f64, 1 }, // Haswell from http://www.agner.org/ 861 { ISD::FMUL, MVT::v2f64, 1 }, // Haswell from http://www.agner.org/ 862 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 863 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 864 865 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 866 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 867 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 868 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 869 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 870 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 871 }; 872 873 // Look for AVX2 lowering tricks for custom cases. 874 if (ST->hasAVX2()) 875 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 876 return LT.first * Entry->Cost; 877 878 static const CostTblEntry AVX1CostTable[] = { 879 // We don't have to scalarize unsupported ops. We can issue two half-sized 880 // operations and we only need to extract the upper YMM half. 881 // Two ops + 1 extract + 1 insert = 4. 882 { ISD::MUL, MVT::v16i16, 4 }, 883 { ISD::MUL, MVT::v8i32, 5 }, // BTVER2 from http://www.agner.org/ 884 { ISD::MUL, MVT::v4i64, 12 }, 885 886 { ISD::SUB, MVT::v32i8, 4 }, 887 { ISD::ADD, MVT::v32i8, 4 }, 888 { ISD::SUB, MVT::v16i16, 4 }, 889 { ISD::ADD, MVT::v16i16, 4 }, 890 { ISD::SUB, MVT::v8i32, 4 }, 891 { ISD::ADD, MVT::v8i32, 4 }, 892 { ISD::SUB, MVT::v4i64, 4 }, 893 { ISD::ADD, MVT::v4i64, 4 }, 894 895 { ISD::SHL, MVT::v32i8, 22 }, // pblendvb sequence + split. 896 { ISD::SHL, MVT::v8i16, 6 }, // pblendvb sequence. 897 { ISD::SHL, MVT::v16i16, 13 }, // pblendvb sequence + split. 898 { ISD::SHL, MVT::v4i32, 3 }, // pslld/paddd/cvttps2dq/pmulld 899 { ISD::SHL, MVT::v8i32, 9 }, // pslld/paddd/cvttps2dq/pmulld + split 900 { ISD::SHL, MVT::v2i64, 2 }, // Shift each lane + blend. 901 { ISD::SHL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 902 903 { ISD::SRL, MVT::v32i8, 23 }, // pblendvb sequence + split. 904 { ISD::SRL, MVT::v16i16, 28 }, // pblendvb sequence + split. 905 { ISD::SRL, MVT::v4i32, 6 }, // Shift each lane + blend. 906 { ISD::SRL, MVT::v8i32, 14 }, // Shift each lane + blend + split. 907 { ISD::SRL, MVT::v2i64, 2 }, // Shift each lane + blend. 908 { ISD::SRL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 909 910 { ISD::SRA, MVT::v32i8, 44 }, // pblendvb sequence + split. 911 { ISD::SRA, MVT::v16i16, 28 }, // pblendvb sequence + split. 912 { ISD::SRA, MVT::v4i32, 6 }, // Shift each lane + blend. 913 { ISD::SRA, MVT::v8i32, 14 }, // Shift each lane + blend + split. 914 { ISD::SRA, MVT::v2i64, 5 }, // Shift each lane + blend. 915 { ISD::SRA, MVT::v4i64, 12 }, // Shift each lane + blend + split. 916 917 { ISD::FNEG, MVT::v4f64, 2 }, // BTVER2 from http://www.agner.org/ 918 { ISD::FNEG, MVT::v8f32, 2 }, // BTVER2 from http://www.agner.org/ 919 920 { ISD::FMUL, MVT::f64, 2 }, // BTVER2 from http://www.agner.org/ 921 { ISD::FMUL, MVT::v2f64, 2 }, // BTVER2 from http://www.agner.org/ 922 { ISD::FMUL, MVT::v4f64, 4 }, // BTVER2 from http://www.agner.org/ 923 924 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 925 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 926 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 927 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 928 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 929 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 930 }; 931 932 if (ST->hasAVX()) 933 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 934 return LT.first * Entry->Cost; 935 936 static const CostTblEntry SSE42CostTable[] = { 937 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 938 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 939 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 940 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 941 942 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 943 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 944 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 945 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 946 947 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 948 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 949 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 950 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 951 952 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 953 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 954 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 955 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 956 957 { ISD::MUL, MVT::v2i64, 6 } // 3*pmuludq/3*shift/2*add 958 }; 959 960 if (ST->hasSSE42()) 961 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 962 return LT.first * Entry->Cost; 963 964 static const CostTblEntry SSE41CostTable[] = { 965 { ISD::SHL, MVT::v16i8, 10 }, // pblendvb sequence. 966 { ISD::SHL, MVT::v8i16, 11 }, // pblendvb sequence. 967 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 968 969 { ISD::SRL, MVT::v16i8, 11 }, // pblendvb sequence. 970 { ISD::SRL, MVT::v8i16, 13 }, // pblendvb sequence. 971 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 972 973 { ISD::SRA, MVT::v16i8, 21 }, // pblendvb sequence. 974 { ISD::SRA, MVT::v8i16, 13 }, // pblendvb sequence. 975 976 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 977 }; 978 979 if (ST->hasSSE41()) 980 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 981 return LT.first * Entry->Cost; 982 983 static const CostTblEntry SSE2CostTable[] = { 984 // We don't correctly identify costs of casts because they are marked as 985 // custom. 986 { ISD::SHL, MVT::v16i8, 13 }, // cmpgtb sequence. 987 { ISD::SHL, MVT::v8i16, 25 }, // cmpgtw sequence. 988 { ISD::SHL, MVT::v4i32, 16 }, // pslld/paddd/cvttps2dq/pmuludq. 989 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 990 991 { ISD::SRL, MVT::v16i8, 14 }, // cmpgtb sequence. 992 { ISD::SRL, MVT::v8i16, 16 }, // cmpgtw sequence. 993 { ISD::SRL, MVT::v4i32, 12 }, // Shift each lane + blend. 994 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 995 996 { ISD::SRA, MVT::v16i8, 27 }, // unpacked cmpgtb sequence. 997 { ISD::SRA, MVT::v8i16, 16 }, // cmpgtw sequence. 998 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 999 { ISD::SRA, MVT::v2i64, 8 }, // srl/xor/sub splat+shuffle sequence. 1000 1001 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 1002 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 1003 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 1004 1005 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 1006 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 1007 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 1008 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 1009 1010 { ISD::FNEG, MVT::f32, 1 }, // Pentium IV from http://www.agner.org/ 1011 { ISD::FNEG, MVT::f64, 1 }, // Pentium IV from http://www.agner.org/ 1012 { ISD::FNEG, MVT::v4f32, 1 }, // Pentium IV from http://www.agner.org/ 1013 { ISD::FNEG, MVT::v2f64, 1 }, // Pentium IV from http://www.agner.org/ 1014 1015 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 1016 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 1017 1018 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 1019 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 1020 }; 1021 1022 if (ST->hasSSE2()) 1023 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 1024 return LT.first * Entry->Cost; 1025 1026 static const CostTblEntry SSE1CostTable[] = { 1027 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 1028 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 1029 1030 { ISD::FNEG, MVT::f32, 2 }, // Pentium III from http://www.agner.org/ 1031 { ISD::FNEG, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1032 1033 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1034 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1035 1036 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1037 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1038 }; 1039 1040 if (ST->hasSSE1()) 1041 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 1042 return LT.first * Entry->Cost; 1043 1044 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 1045 { ISD::ADD, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1046 { ISD::SUB, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1047 { ISD::MUL, MVT::i64, 2 }, // Nehalem from http://www.agner.org/ 1048 }; 1049 1050 if (ST->is64Bit()) 1051 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, LT.second)) 1052 return LT.first * Entry->Cost; 1053 1054 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 1055 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1056 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1057 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1058 1059 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1060 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1061 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1062 }; 1063 1064 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, LT.second)) 1065 return LT.first * Entry->Cost; 1066 1067 // It is not a good idea to vectorize division. We have to scalarize it and 1068 // in the process we will often end up having to spilling regular 1069 // registers. The overhead of division is going to dominate most kernels 1070 // anyways so try hard to prevent vectorization of division - it is 1071 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 1072 // to hide "20 cycles" for each lane. 1073 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 1074 ISD == ISD::UDIV || ISD == ISD::UREM)) { 1075 InstructionCost ScalarCost = getArithmeticInstrCost( 1076 Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info, 1077 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 1078 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 1079 } 1080 1081 // Fallback to the default implementation. 1082 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info); 1083 } 1084 1085 InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, 1086 VectorType *BaseTp, 1087 ArrayRef<int> Mask, int Index, 1088 VectorType *SubTp, 1089 ArrayRef<const Value *> Args) { 1090 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 1091 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 1092 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 1093 1094 Kind = improveShuffleKindFromMask(Kind, Mask); 1095 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 1096 if (Kind == TTI::SK_Transpose) 1097 Kind = TTI::SK_PermuteTwoSrc; 1098 1099 // For Broadcasts we are splatting the first element from the first input 1100 // register, so only need to reference that input and all the output 1101 // registers are the same. 1102 if (Kind == TTI::SK_Broadcast) 1103 LT.first = 1; 1104 1105 // Subvector extractions are free if they start at the beginning of a 1106 // vector and cheap if the subvectors are aligned. 1107 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 1108 int NumElts = LT.second.getVectorNumElements(); 1109 if ((Index % NumElts) == 0) 1110 return 0; 1111 std::pair<InstructionCost, MVT> SubLT = 1112 TLI->getTypeLegalizationCost(DL, SubTp); 1113 if (SubLT.second.isVector()) { 1114 int NumSubElts = SubLT.second.getVectorNumElements(); 1115 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1116 return SubLT.first; 1117 // Handle some cases for widening legalization. For now we only handle 1118 // cases where the original subvector was naturally aligned and evenly 1119 // fit in its legalized subvector type. 1120 // FIXME: Remove some of the alignment restrictions. 1121 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 1122 // vectors. 1123 int OrigSubElts = cast<FixedVectorType>(SubTp)->getNumElements(); 1124 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 1125 (NumSubElts % OrigSubElts) == 0 && 1126 LT.second.getVectorElementType() == 1127 SubLT.second.getVectorElementType() && 1128 LT.second.getVectorElementType().getSizeInBits() == 1129 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 1130 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 1131 "Unexpected number of elements!"); 1132 auto *VecTy = FixedVectorType::get(BaseTp->getElementType(), 1133 LT.second.getVectorNumElements()); 1134 auto *SubTy = FixedVectorType::get(BaseTp->getElementType(), 1135 SubLT.second.getVectorNumElements()); 1136 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 1137 InstructionCost ExtractCost = getShuffleCost( 1138 TTI::SK_ExtractSubvector, VecTy, None, ExtractIndex, SubTy); 1139 1140 // If the original size is 32-bits or more, we can use pshufd. Otherwise 1141 // if we have SSSE3 we can use pshufb. 1142 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 1143 return ExtractCost + 1; // pshufd or pshufb 1144 1145 assert(SubTp->getPrimitiveSizeInBits() == 16 && 1146 "Unexpected vector size"); 1147 1148 return ExtractCost + 2; // worst case pshufhw + pshufd 1149 } 1150 } 1151 } 1152 1153 // Subvector insertions are cheap if the subvectors are aligned. 1154 // Note that in general, the insertion starting at the beginning of a vector 1155 // isn't free, because we need to preserve the rest of the wide vector. 1156 if (Kind == TTI::SK_InsertSubvector && LT.second.isVector()) { 1157 int NumElts = LT.second.getVectorNumElements(); 1158 std::pair<InstructionCost, MVT> SubLT = 1159 TLI->getTypeLegalizationCost(DL, SubTp); 1160 if (SubLT.second.isVector()) { 1161 int NumSubElts = SubLT.second.getVectorNumElements(); 1162 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1163 return SubLT.first; 1164 } 1165 1166 // If the insertion isn't aligned, treat it like a 2-op shuffle. 1167 Kind = TTI::SK_PermuteTwoSrc; 1168 } 1169 1170 // Handle some common (illegal) sub-vector types as they are often very cheap 1171 // to shuffle even on targets without PSHUFB. 1172 EVT VT = TLI->getValueType(DL, BaseTp); 1173 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 1174 !ST->hasSSSE3()) { 1175 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 1176 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 1177 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1178 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1179 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1180 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1181 1182 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1183 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1184 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1185 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1186 1187 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1188 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1189 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1190 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1191 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1192 1193 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1194 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1195 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1196 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1197 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1198 }; 1199 1200 if (ST->hasSSE2()) 1201 if (const auto *Entry = 1202 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1203 return Entry->Cost; 1204 } 1205 1206 // We are going to permute multiple sources and the result will be in multiple 1207 // destinations. Providing an accurate cost only for splits where the element 1208 // type remains the same. 1209 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1210 MVT LegalVT = LT.second; 1211 if (LegalVT.isVector() && 1212 LegalVT.getVectorElementType().getSizeInBits() == 1213 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1214 LegalVT.getVectorNumElements() < 1215 cast<FixedVectorType>(BaseTp)->getNumElements()) { 1216 1217 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1218 unsigned LegalVTSize = LegalVT.getStoreSize(); 1219 // Number of source vectors after legalization: 1220 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1221 // Number of destination vectors after legalization: 1222 InstructionCost NumOfDests = LT.first; 1223 1224 auto *SingleOpTy = FixedVectorType::get(BaseTp->getElementType(), 1225 LegalVT.getVectorNumElements()); 1226 1227 InstructionCost NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1228 return NumOfShuffles * getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 1229 None, 0, nullptr); 1230 } 1231 1232 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1233 } 1234 1235 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1236 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1237 // We assume that source and destination have the same vector type. 1238 InstructionCost NumOfDests = LT.first; 1239 InstructionCost NumOfShufflesPerDest = LT.first * 2 - 1; 1240 LT.first = NumOfDests * NumOfShufflesPerDest; 1241 } 1242 1243 static const CostTblEntry AVX512FP16ShuffleTbl[] = { 1244 {TTI::SK_Broadcast, MVT::v32f16, 1}, // vpbroadcastw 1245 {TTI::SK_Broadcast, MVT::v16f16, 1}, // vpbroadcastw 1246 {TTI::SK_Broadcast, MVT::v8f16, 1}, // vpbroadcastw 1247 1248 {TTI::SK_Reverse, MVT::v32f16, 2}, // vpermw 1249 {TTI::SK_Reverse, MVT::v16f16, 2}, // vpermw 1250 {TTI::SK_Reverse, MVT::v8f16, 1}, // vpshufb 1251 1252 {TTI::SK_PermuteSingleSrc, MVT::v32f16, 2}, // vpermw 1253 {TTI::SK_PermuteSingleSrc, MVT::v16f16, 2}, // vpermw 1254 {TTI::SK_PermuteSingleSrc, MVT::v8f16, 1}, // vpshufb 1255 1256 {TTI::SK_PermuteTwoSrc, MVT::v32f16, 2}, // vpermt2w 1257 {TTI::SK_PermuteTwoSrc, MVT::v16f16, 2}, // vpermt2w 1258 {TTI::SK_PermuteTwoSrc, MVT::v8f16, 2} // vpermt2w 1259 }; 1260 1261 if (!ST->useSoftFloat() && ST->hasFP16()) 1262 if (const auto *Entry = 1263 CostTableLookup(AVX512FP16ShuffleTbl, Kind, LT.second)) 1264 return LT.first * Entry->Cost; 1265 1266 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1267 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1268 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1269 1270 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1271 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1272 1273 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b 1274 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b 1275 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2} // vpermt2b 1276 }; 1277 1278 if (ST->hasVBMI()) 1279 if (const auto *Entry = 1280 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1281 return LT.first * Entry->Cost; 1282 1283 static const CostTblEntry AVX512BWShuffleTbl[] = { 1284 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1285 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1286 1287 {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw 1288 {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw 1289 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1290 1291 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw 1292 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw 1293 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1294 1295 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w 1296 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w 1297 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2}, // vpermt2w 1298 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1299 1300 {TTI::SK_Select, MVT::v32i16, 1}, // vblendmw 1301 {TTI::SK_Select, MVT::v64i8, 1}, // vblendmb 1302 }; 1303 1304 if (ST->hasBWI()) 1305 if (const auto *Entry = 1306 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1307 return LT.first * Entry->Cost; 1308 1309 static const CostTblEntry AVX512ShuffleTbl[] = { 1310 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1311 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1312 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1313 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1314 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1315 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1316 1317 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1318 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1319 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1320 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1321 {TTI::SK_Reverse, MVT::v32i16, 7}, // per mca 1322 {TTI::SK_Reverse, MVT::v64i8, 7}, // per mca 1323 1324 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1325 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1326 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1327 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1328 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1329 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1330 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1331 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1332 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1333 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1334 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1335 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1336 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1337 1338 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1339 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1340 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1341 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1342 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1343 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1344 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1345 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1346 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1347 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1348 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1349 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1350 1351 // FIXME: This just applies the type legalization cost rules above 1352 // assuming these completely split. 1353 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1354 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1355 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1356 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1357 1358 {TTI::SK_Select, MVT::v32i16, 1}, // vpternlogq 1359 {TTI::SK_Select, MVT::v64i8, 1}, // vpternlogq 1360 {TTI::SK_Select, MVT::v8f64, 1}, // vblendmpd 1361 {TTI::SK_Select, MVT::v16f32, 1}, // vblendmps 1362 {TTI::SK_Select, MVT::v8i64, 1}, // vblendmq 1363 {TTI::SK_Select, MVT::v16i32, 1}, // vblendmd 1364 }; 1365 1366 if (ST->hasAVX512()) 1367 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1368 return LT.first * Entry->Cost; 1369 1370 static const CostTblEntry AVX2ShuffleTbl[] = { 1371 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1372 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1373 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1374 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1375 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1376 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1377 1378 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1379 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1380 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1381 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1382 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1383 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1384 1385 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1386 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1387 1388 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1389 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1390 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1391 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1392 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1393 // + vpblendvb 1394 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1395 // + vpblendvb 1396 1397 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1398 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1399 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1400 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1401 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1402 // + vpblendvb 1403 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1404 // + vpblendvb 1405 }; 1406 1407 if (ST->hasAVX2()) 1408 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1409 return LT.first * Entry->Cost; 1410 1411 static const CostTblEntry XOPShuffleTbl[] = { 1412 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1413 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1414 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1415 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1416 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1417 // + vinsertf128 1418 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1419 // + vinsertf128 1420 1421 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1422 // + vinsertf128 1423 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1424 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1425 // + vinsertf128 1426 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1427 }; 1428 1429 if (ST->hasXOP()) 1430 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1431 return LT.first * Entry->Cost; 1432 1433 static const CostTblEntry AVX1ShuffleTbl[] = { 1434 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1435 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1436 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1437 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1438 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1439 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1440 1441 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1442 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1443 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1444 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1445 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1446 // + vinsertf128 1447 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1448 // + vinsertf128 1449 1450 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1451 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1452 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1453 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1454 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1455 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1456 1457 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1458 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1459 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1460 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1461 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1462 // + 2*por + vinsertf128 1463 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1464 // + 2*por + vinsertf128 1465 1466 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1467 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1468 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1469 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1470 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1471 // + 4*por + vinsertf128 1472 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1473 // + 4*por + vinsertf128 1474 }; 1475 1476 if (ST->hasAVX()) 1477 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1478 return LT.first * Entry->Cost; 1479 1480 static const CostTblEntry SSE41ShuffleTbl[] = { 1481 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1482 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1483 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1484 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1485 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1486 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1487 }; 1488 1489 if (ST->hasSSE41()) 1490 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1491 return LT.first * Entry->Cost; 1492 1493 static const CostTblEntry SSSE3ShuffleTbl[] = { 1494 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1495 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1496 1497 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1498 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1499 1500 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1501 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1502 1503 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1504 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1505 1506 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1507 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1508 }; 1509 1510 if (ST->hasSSSE3()) 1511 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1512 return LT.first * Entry->Cost; 1513 1514 static const CostTblEntry SSE2ShuffleTbl[] = { 1515 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1516 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1517 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1518 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1519 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1520 1521 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1522 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1523 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1524 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1525 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1526 // + 2*pshufd + 2*unpck + packus 1527 1528 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1529 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1530 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1531 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1532 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1533 1534 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1535 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1536 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1537 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1538 // + pshufd/unpck 1539 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1540 // + 2*pshufd + 2*unpck + 2*packus 1541 1542 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1543 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1544 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1545 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1546 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1547 }; 1548 1549 static const CostTblEntry SSE3BroadcastLoadTbl[] = { 1550 {TTI::SK_Broadcast, MVT::v2f64, 0}, // broadcast handled by movddup 1551 }; 1552 1553 if (ST->hasSSE2()) { 1554 bool IsLoad = 1555 llvm::any_of(Args, [](const auto &V) { return isa<LoadInst>(V); }); 1556 if (ST->hasSSE3() && IsLoad) 1557 if (const auto *Entry = 1558 CostTableLookup(SSE3BroadcastLoadTbl, Kind, LT.second)) { 1559 assert(isLegalBroadcastLoad(BaseTp->getElementType(), 1560 LT.second.getVectorElementCount()) && 1561 "Table entry missing from isLegalBroadcastLoad()"); 1562 return LT.first * Entry->Cost; 1563 } 1564 1565 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1566 return LT.first * Entry->Cost; 1567 } 1568 1569 static const CostTblEntry SSE1ShuffleTbl[] = { 1570 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1571 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1572 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1573 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1574 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1575 }; 1576 1577 if (ST->hasSSE1()) 1578 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1579 return LT.first * Entry->Cost; 1580 1581 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1582 } 1583 1584 InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, 1585 Type *Src, 1586 TTI::CastContextHint CCH, 1587 TTI::TargetCostKind CostKind, 1588 const Instruction *I) { 1589 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1590 assert(ISD && "Invalid opcode"); 1591 1592 // TODO: Allow non-throughput costs that aren't binary. 1593 auto AdjustCost = [&CostKind](InstructionCost Cost) -> InstructionCost { 1594 if (CostKind != TTI::TCK_RecipThroughput) 1595 return Cost == 0 ? 0 : 1; 1596 return Cost; 1597 }; 1598 1599 // The cost tables include both specific, custom (non-legal) src/dst type 1600 // conversions and generic, legalized types. We test for customs first, before 1601 // falling back to legalization. 1602 // FIXME: Need a better design of the cost table to handle non-simple types of 1603 // potential massive combinations (elem_num x src_type x dst_type). 1604 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1605 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1606 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1607 1608 // Mask sign extend has an instruction. 1609 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1610 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v2i1, 1 }, 1611 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1612 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v2i1, 1 }, 1613 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1614 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v4i1, 1 }, 1615 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1616 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v4i1, 1 }, 1617 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1618 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v8i1, 1 }, 1619 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1620 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1621 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1622 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1623 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1624 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1625 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v64i1, 1 }, 1626 1627 // Mask zero extend is a sext + shift. 1628 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1629 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v2i1, 2 }, 1630 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1631 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v2i1, 2 }, 1632 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1633 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v4i1, 2 }, 1634 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1635 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v4i1, 2 }, 1636 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1637 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v8i1, 2 }, 1638 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1639 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1640 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1641 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1642 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1643 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1644 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v64i1, 2 }, 1645 1646 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, 1647 { ISD::TRUNCATE, MVT::v2i1, MVT::v16i8, 2 }, 1648 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, 1649 { ISD::TRUNCATE, MVT::v2i1, MVT::v8i16, 2 }, 1650 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, 1651 { ISD::TRUNCATE, MVT::v4i1, MVT::v16i8, 2 }, 1652 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, 1653 { ISD::TRUNCATE, MVT::v4i1, MVT::v8i16, 2 }, 1654 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, 1655 { ISD::TRUNCATE, MVT::v8i1, MVT::v16i8, 2 }, 1656 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, 1657 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, 1658 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, 1659 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, 1660 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, 1661 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, 1662 { ISD::TRUNCATE, MVT::v64i1, MVT::v32i16, 2 }, 1663 1664 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, 1665 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm 1666 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // vpmovwb 1667 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // vpmovwb 1668 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // vpmovwb 1669 }; 1670 1671 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1672 // Mask sign extend has an instruction. 1673 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, 1674 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v2i1, 1 }, 1675 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, 1676 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, 1677 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, 1678 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v16i1, 1 }, 1679 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, 1680 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, 1681 1682 // Mask zero extend is a sext + shift. 1683 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, 1684 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v2i1, 2 }, 1685 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, 1686 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, 1687 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, 1688 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v16i1, 2 }, 1689 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, 1690 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1691 1692 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, 1693 { ISD::TRUNCATE, MVT::v2i1, MVT::v4i32, 2 }, 1694 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, 1695 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, 1696 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1697 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, 1698 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, 1699 { ISD::TRUNCATE, MVT::v16i1, MVT::v8i64, 2 }, 1700 1701 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1702 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1703 1704 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1705 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1706 1707 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1708 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1709 1710 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1711 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1712 }; 1713 1714 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1715 // 256-bit wide vectors. 1716 1717 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1718 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1719 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1720 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1721 1722 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1723 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1724 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1725 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd 1726 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1727 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1728 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1729 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd 1730 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd 1731 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd 1732 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd 1733 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd 1734 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq 1735 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq 1736 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq 1737 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 2 }, // vpmovdb 1738 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 2 }, // vpmovdb 1739 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, // vpmovdb 1740 { ISD::TRUNCATE, MVT::v32i8, MVT::v16i32, 2 }, // vpmovdb 1741 { ISD::TRUNCATE, MVT::v64i8, MVT::v16i32, 2 }, // vpmovdb 1742 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, // vpmovdw 1743 { ISD::TRUNCATE, MVT::v32i16, MVT::v16i32, 2 }, // vpmovdw 1744 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 2 }, // vpmovqb 1745 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 1 }, // vpshufb 1746 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, // vpmovqb 1747 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i64, 2 }, // vpmovqb 1748 { ISD::TRUNCATE, MVT::v32i8, MVT::v8i64, 2 }, // vpmovqb 1749 { ISD::TRUNCATE, MVT::v64i8, MVT::v8i64, 2 }, // vpmovqb 1750 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, // vpmovqw 1751 { ISD::TRUNCATE, MVT::v16i16, MVT::v8i64, 2 }, // vpmovqw 1752 { ISD::TRUNCATE, MVT::v32i16, MVT::v8i64, 2 }, // vpmovqw 1753 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, // vpmovqd 1754 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd 1755 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb 1756 1757 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32 1758 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, 1759 { ISD::TRUNCATE, MVT::v64i8, MVT::v32i16, 8 }, 1760 1761 // Sign extend is zmm vpternlogd+vptruncdb. 1762 // Zero extend is zmm broadcast load+vptruncdw. 1763 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 }, 1764 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 }, 1765 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, 1766 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, 1767 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, 1768 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, 1769 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 }, 1770 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 }, 1771 1772 // Sign extend is zmm vpternlogd+vptruncdw. 1773 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw. 1774 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 }, 1775 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1776 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 }, 1777 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1778 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 }, 1779 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1780 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 }, 1781 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1782 1783 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd 1784 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld 1785 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd 1786 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld 1787 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd 1788 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld 1789 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq 1790 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq 1791 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq 1792 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq 1793 1794 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd 1795 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld 1796 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq 1797 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq 1798 1799 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1800 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1801 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1802 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1803 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1804 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1805 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1806 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1807 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1808 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1809 1810 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1811 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1812 1813 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1814 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1815 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, 1816 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, 1817 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1818 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, 1819 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1820 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1821 1822 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1823 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1824 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, 1825 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, 1826 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1827 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, 1828 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1829 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1830 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1831 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1832 1833 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2 }, 1834 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f64, 7 }, 1835 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f64,15 }, 1836 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f32,11 }, 1837 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f64,31 }, 1838 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, 1839 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f64, 7 }, 1840 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f32, 5 }, 1841 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f64,15 }, 1842 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 1 }, 1843 { ISD::FP_TO_SINT, MVT::v16i32, MVT::v16f64, 3 }, 1844 1845 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1846 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, 1847 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, 1848 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1849 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, 1850 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, 1851 }; 1852 1853 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1854 // Mask sign extend has an instruction. 1855 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1856 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v2i1, 1 }, 1857 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1858 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v2i1, 1 }, 1859 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1860 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v4i1, 1 }, 1861 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1862 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v4i1, 1 }, 1863 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1864 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v8i1, 1 }, 1865 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1866 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1867 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1868 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1869 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v32i1, 1 }, 1870 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v64i1, 1 }, 1871 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v64i1, 1 }, 1872 1873 // Mask zero extend is a sext + shift. 1874 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1875 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v2i1, 2 }, 1876 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1877 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v2i1, 2 }, 1878 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1879 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v4i1, 2 }, 1880 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1881 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v4i1, 2 }, 1882 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1883 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v8i1, 2 }, 1884 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1885 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1886 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1887 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1888 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v32i1, 2 }, 1889 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v64i1, 2 }, 1890 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v64i1, 2 }, 1891 1892 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, 1893 { ISD::TRUNCATE, MVT::v2i1, MVT::v16i8, 2 }, 1894 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, 1895 { ISD::TRUNCATE, MVT::v2i1, MVT::v8i16, 2 }, 1896 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, 1897 { ISD::TRUNCATE, MVT::v4i1, MVT::v16i8, 2 }, 1898 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, 1899 { ISD::TRUNCATE, MVT::v4i1, MVT::v8i16, 2 }, 1900 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, 1901 { ISD::TRUNCATE, MVT::v8i1, MVT::v16i8, 2 }, 1902 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, 1903 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, 1904 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, 1905 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, 1906 { ISD::TRUNCATE, MVT::v32i1, MVT::v16i16, 2 }, 1907 { ISD::TRUNCATE, MVT::v64i1, MVT::v32i8, 2 }, 1908 { ISD::TRUNCATE, MVT::v64i1, MVT::v16i16, 2 }, 1909 1910 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, 1911 }; 1912 1913 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1914 // Mask sign extend has an instruction. 1915 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, 1916 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v2i1, 1 }, 1917 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, 1918 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i1, 1 }, 1919 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, 1920 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i1, 1 }, 1921 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i1, 1 }, 1922 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, 1923 1924 // Mask zero extend is a sext + shift. 1925 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, 1926 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v2i1, 2 }, 1927 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, 1928 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i1, 2 }, 1929 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, 1930 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i1, 2 }, 1931 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i1, 2 }, 1932 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, 1933 1934 { ISD::TRUNCATE, MVT::v16i1, MVT::v4i64, 2 }, 1935 { ISD::TRUNCATE, MVT::v16i1, MVT::v8i32, 2 }, 1936 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, 1937 { ISD::TRUNCATE, MVT::v2i1, MVT::v4i32, 2 }, 1938 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, 1939 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, 1940 { ISD::TRUNCATE, MVT::v8i1, MVT::v4i64, 2 }, 1941 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1942 1943 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1944 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1945 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1946 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1947 1948 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1949 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1950 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1951 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1952 1953 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v4f32, 1 }, 1954 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1955 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1956 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1957 1958 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v4f32, 1 }, 1959 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1960 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1961 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1962 }; 1963 1964 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 1965 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1966 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1967 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1968 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 8 }, // split+2*v8i8 1969 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1970 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1971 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1972 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16 1973 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // vpslld+vptestmd 1974 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd 1975 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // vpslld+vptestmd 1976 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // vpsllq+vptestmq 1977 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // vpsllq+vptestmq 1978 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // vpmovqd 1979 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, // vpmovqb 1980 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, // vpmovqw 1981 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, // vpmovwb 1982 1983 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb 1984 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb 1985 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 }, 1986 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 }, 1987 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 }, 1988 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 }, 1989 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 }, 1990 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 }, 1991 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 }, 1992 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 }, 1993 1994 // sign extend is vpcmpeq+maskedmove+vpmovdw 1995 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw 1996 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1997 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 }, 1998 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1999 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 }, 2000 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 2001 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 }, 2002 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 }, 2003 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 }, 2004 2005 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd 2006 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld 2007 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd 2008 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld 2009 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd 2010 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld 2011 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq 2012 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq 2013 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq 2014 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq 2015 2016 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 1 }, 2017 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 1 }, 2018 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 1 }, 2019 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 1 }, 2020 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 2021 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 2022 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 1 }, 2023 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 1 }, 2024 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 2025 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 2026 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 2027 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 2028 2029 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2030 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 1 }, 2031 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2032 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 1 }, 2033 2034 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 2035 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 2036 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2037 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 1 }, 2038 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2039 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 1 }, 2040 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 2041 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 2042 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 2043 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 2044 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 2045 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 2046 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 2047 2048 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v8f32, 2 }, 2049 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2 }, 2050 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f32, 5 }, 2051 2052 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 2053 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 2054 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 2055 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 1 }, 2056 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 2057 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 2058 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 2059 }; 2060 2061 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 2062 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 2063 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 2064 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 2065 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 2066 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 2067 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 2068 2069 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 2 }, 2070 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 2 }, 2071 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 2 }, 2072 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 2 }, 2073 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 2074 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 2075 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 2 }, 2076 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 2 }, 2077 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 2078 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 2079 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 2080 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 2081 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 2082 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 2083 2084 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 2085 2086 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 4 }, 2087 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 4 }, 2088 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i16, 1 }, 2089 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 1 }, 2090 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 1 }, 2091 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i32, 4 }, 2092 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i64, 4 }, 2093 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 1 }, 2094 { ISD::TRUNCATE, MVT::v8i16, MVT::v2i64, 1 }, 2095 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i64, 5 }, 2096 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, 2097 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 2098 2099 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 2100 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 2101 2102 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v8f32, 1 }, 2103 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 1 }, 2104 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 1 }, 2105 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 3 }, 2106 2107 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 3 }, 2108 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 3 }, 2109 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v8f32, 1 }, 2110 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 3 }, 2111 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 2112 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4 }, 2113 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 3 }, 2114 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v4f64, 4 }, 2115 2116 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 2 }, 2117 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 2 }, 2118 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 2 }, 2119 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 2120 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 2121 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 2122 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 3 }, 2123 2124 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 2 }, 2125 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 2 }, 2126 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 2 }, 2127 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 2128 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 2129 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 2130 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 2 }, 2131 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2132 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 2133 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 }, 2134 }; 2135 2136 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 2137 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 2138 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 2139 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 2140 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 2141 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 2142 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 2143 2144 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 3 }, 2145 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 3 }, 2146 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 3 }, 2147 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 3 }, 2148 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 2149 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 2150 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 3 }, 2151 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 3 }, 2152 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 2153 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 2154 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 2155 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 2156 2157 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 4 }, 2158 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 5 }, 2159 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 4 }, 2160 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 9 }, 2161 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, 11 }, 2162 2163 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 2164 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, 2165 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // and+extract+packuswb 2166 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i32, 5 }, 2167 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2168 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i64, 5 }, 2169 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i64, 3 }, // and+extract+2*packusdw 2170 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 2171 2172 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 2173 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 2174 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 2175 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 4 }, 2176 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v16i8, 2 }, 2177 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 2178 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v8i16, 2 }, 2179 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2180 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 2181 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 }, 2182 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 5 }, 2183 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 8 }, 2184 2185 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 2186 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 2187 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 2188 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 4 }, 2189 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v16i8, 2 }, 2190 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 2191 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v8i16, 2 }, 2192 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 4 }, 2193 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 4 }, 2194 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 2195 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 2196 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 2197 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 10 }, 2198 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 10 }, 2199 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 18 }, 2200 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 2201 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 10 }, 2202 2203 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v8f32, 2 }, 2204 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f64, 2 }, 2205 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v8f32, 2 }, 2206 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v4f64, 2 }, 2207 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 2 }, 2208 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f64, 2 }, 2209 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v8f32, 2 }, 2210 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v4f64, 2 }, 2211 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 2 }, 2212 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 2 }, 2213 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 5 }, 2214 2215 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v8f32, 2 }, 2216 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f64, 2 }, 2217 { ISD::FP_TO_UINT, MVT::v32i8, MVT::v8f32, 2 }, 2218 { ISD::FP_TO_UINT, MVT::v32i8, MVT::v4f64, 2 }, 2219 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 2 }, 2220 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f64, 2 }, 2221 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v8f32, 2 }, 2222 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v4f64, 2 }, 2223 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 3 }, 2224 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 2225 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 6 }, 2226 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 7 }, 2227 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v4f64, 7 }, 2228 2229 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 2230 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 2231 }; 2232 2233 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 2234 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8, 1 }, 2235 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8, 1 }, 2236 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8, 1 }, 2237 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8, 1 }, 2238 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2239 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2240 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16, 1 }, 2241 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16, 1 }, 2242 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2243 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2244 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2245 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2246 2247 // These truncates end up widening elements. 2248 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 1 }, // PMOVXZBQ 2249 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 1 }, // PMOVXZWQ 2250 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 1 }, // PMOVXZBD 2251 2252 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 2 }, 2253 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 2 }, 2254 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 2 }, 2255 2256 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 1 }, 2257 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 1 }, 2258 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 1 }, 2259 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 1 }, 2260 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 1 }, 2261 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2262 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 1 }, 2263 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2264 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 2265 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 1 }, 2266 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2267 2268 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 1 }, 2269 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 1 }, 2270 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 2271 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 2272 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 1 }, 2273 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2274 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 1 }, 2275 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2276 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 3 }, 2277 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 3 }, 2278 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 2 }, 2279 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 12 }, 2280 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 22 }, 2281 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 4 }, 2282 2283 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 1 }, 2284 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 1 }, 2285 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 1 }, 2286 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 1 }, 2287 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f32, 2 }, 2288 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v2f64, 2 }, 2289 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f32, 1 }, 2290 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v2f64, 1 }, 2291 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, 2292 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v2f64, 1 }, 2293 2294 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 1 }, 2295 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 2296 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 1 }, 2297 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 2298 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f32, 2 }, 2299 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v2f64, 2 }, 2300 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f32, 1 }, 2301 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v2f64, 1 }, 2302 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 4 }, 2303 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 2304 }; 2305 2306 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 2307 // These are somewhat magic numbers justified by comparing the 2308 // output of llvm-mca for our various supported scheduler models 2309 // and basing it off the worst case scenario. 2310 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 3 }, 2311 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 3 }, 2312 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 3 }, 2313 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 3 }, 2314 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 3 }, 2315 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 4 }, 2316 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 3 }, 2317 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 4 }, 2318 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 3 }, 2319 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4 }, 2320 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 8 }, 2321 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 8 }, 2322 2323 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 3 }, 2324 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 3 }, 2325 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 8 }, 2326 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 9 }, 2327 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 4 }, 2328 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 4 }, 2329 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 4 }, 2330 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 4 }, 2331 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 7 }, 2332 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 7 }, 2333 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 2334 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 15 }, 2335 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 18 }, 2336 2337 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 4 }, 2338 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 4 }, 2339 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 4 }, 2340 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 4 }, 2341 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f32, 6 }, 2342 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v2f64, 6 }, 2343 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f32, 5 }, 2344 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v2f64, 5 }, 2345 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 4 }, 2346 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v2f64, 4 }, 2347 2348 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 4 }, 2349 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 2350 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 4 }, 2351 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 15 }, 2352 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f32, 6 }, 2353 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v2f64, 6 }, 2354 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f32, 5 }, 2355 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v2f64, 5 }, 2356 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 8 }, 2357 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 8 }, 2358 2359 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8, 4 }, 2360 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8, 4 }, 2361 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8, 2 }, 2362 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8, 3 }, 2363 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2364 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8, 2 }, 2365 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16, 2 }, 2366 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16, 3 }, 2367 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2368 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16, 2 }, 2369 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2370 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32, 2 }, 2371 2372 // These truncates are really widening elements. 2373 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 1 }, // PSHUFD 2374 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // PUNPCKLWD+DQ 2375 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // PUNPCKLBW+WD+PSHUFD 2376 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 1 }, // PUNPCKLWD 2377 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // PUNPCKLBW+WD 2378 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 1 }, // PUNPCKLBW 2379 2380 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i16, 2 }, // PAND+PACKUSWB 2381 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 2382 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 3 }, // PAND+2*PACKUSWB 2383 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 2384 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 2385 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 3 }, 2386 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2387 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32,10 }, 2388 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 2389 { ISD::TRUNCATE, MVT::v8i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 2390 { ISD::TRUNCATE, MVT::v4i32, MVT::v2i64, 1 }, // PSHUFD 2391 }; 2392 2393 // Attempt to map directly to (simple) MVT types to let us match custom entries. 2394 EVT SrcTy = TLI->getValueType(DL, Src); 2395 EVT DstTy = TLI->getValueType(DL, Dst); 2396 2397 // The function getSimpleVT only handles simple value types. 2398 if (SrcTy.isSimple() && DstTy.isSimple()) { 2399 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 2400 MVT SimpleDstTy = DstTy.getSimpleVT(); 2401 2402 if (ST->useAVX512Regs()) { 2403 if (ST->hasBWI()) 2404 if (const auto *Entry = ConvertCostTableLookup( 2405 AVX512BWConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2406 return AdjustCost(Entry->Cost); 2407 2408 if (ST->hasDQI()) 2409 if (const auto *Entry = ConvertCostTableLookup( 2410 AVX512DQConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2411 return AdjustCost(Entry->Cost); 2412 2413 if (ST->hasAVX512()) 2414 if (const auto *Entry = ConvertCostTableLookup( 2415 AVX512FConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2416 return AdjustCost(Entry->Cost); 2417 } 2418 2419 if (ST->hasBWI()) 2420 if (const auto *Entry = ConvertCostTableLookup( 2421 AVX512BWVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2422 return AdjustCost(Entry->Cost); 2423 2424 if (ST->hasDQI()) 2425 if (const auto *Entry = ConvertCostTableLookup( 2426 AVX512DQVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2427 return AdjustCost(Entry->Cost); 2428 2429 if (ST->hasAVX512()) 2430 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2431 SimpleDstTy, SimpleSrcTy)) 2432 return AdjustCost(Entry->Cost); 2433 2434 if (ST->hasAVX2()) { 2435 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2436 SimpleDstTy, SimpleSrcTy)) 2437 return AdjustCost(Entry->Cost); 2438 } 2439 2440 if (ST->hasAVX()) { 2441 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2442 SimpleDstTy, SimpleSrcTy)) 2443 return AdjustCost(Entry->Cost); 2444 } 2445 2446 if (ST->hasSSE41()) { 2447 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2448 SimpleDstTy, SimpleSrcTy)) 2449 return AdjustCost(Entry->Cost); 2450 } 2451 2452 if (ST->hasSSE2()) { 2453 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2454 SimpleDstTy, SimpleSrcTy)) 2455 return AdjustCost(Entry->Cost); 2456 } 2457 } 2458 2459 // Fall back to legalized types. 2460 std::pair<InstructionCost, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 2461 std::pair<InstructionCost, MVT> LTDest = 2462 TLI->getTypeLegalizationCost(DL, Dst); 2463 2464 if (ST->useAVX512Regs()) { 2465 if (ST->hasBWI()) 2466 if (const auto *Entry = ConvertCostTableLookup( 2467 AVX512BWConversionTbl, ISD, LTDest.second, LTSrc.second)) 2468 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2469 2470 if (ST->hasDQI()) 2471 if (const auto *Entry = ConvertCostTableLookup( 2472 AVX512DQConversionTbl, ISD, LTDest.second, LTSrc.second)) 2473 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2474 2475 if (ST->hasAVX512()) 2476 if (const auto *Entry = ConvertCostTableLookup( 2477 AVX512FConversionTbl, ISD, LTDest.second, LTSrc.second)) 2478 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2479 } 2480 2481 if (ST->hasBWI()) 2482 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 2483 LTDest.second, LTSrc.second)) 2484 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2485 2486 if (ST->hasDQI()) 2487 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 2488 LTDest.second, LTSrc.second)) 2489 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2490 2491 if (ST->hasAVX512()) 2492 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2493 LTDest.second, LTSrc.second)) 2494 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2495 2496 if (ST->hasAVX2()) 2497 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2498 LTDest.second, LTSrc.second)) 2499 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2500 2501 if (ST->hasAVX()) 2502 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2503 LTDest.second, LTSrc.second)) 2504 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2505 2506 if (ST->hasSSE41()) 2507 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2508 LTDest.second, LTSrc.second)) 2509 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2510 2511 if (ST->hasSSE2()) 2512 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2513 LTDest.second, LTSrc.second)) 2514 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2515 2516 // Fallback, for i8/i16 sitofp/uitofp cases we need to extend to i32 for 2517 // sitofp. 2518 if ((ISD == ISD::SINT_TO_FP || ISD == ISD::UINT_TO_FP) && 2519 1 < Src->getScalarSizeInBits() && Src->getScalarSizeInBits() < 32) { 2520 Type *ExtSrc = Src->getWithNewBitWidth(32); 2521 unsigned ExtOpc = 2522 (ISD == ISD::SINT_TO_FP) ? Instruction::SExt : Instruction::ZExt; 2523 2524 // For scalar loads the extend would be free. 2525 InstructionCost ExtCost = 0; 2526 if (!(Src->isIntegerTy() && I && isa<LoadInst>(I->getOperand(0)))) 2527 ExtCost = getCastInstrCost(ExtOpc, ExtSrc, Src, CCH, CostKind); 2528 2529 return ExtCost + getCastInstrCost(Instruction::SIToFP, Dst, ExtSrc, 2530 TTI::CastContextHint::None, CostKind); 2531 } 2532 2533 // Fallback for fptosi/fptoui i8/i16 cases we need to truncate from fptosi 2534 // i32. 2535 if ((ISD == ISD::FP_TO_SINT || ISD == ISD::FP_TO_UINT) && 2536 1 < Dst->getScalarSizeInBits() && Dst->getScalarSizeInBits() < 32) { 2537 Type *TruncDst = Dst->getWithNewBitWidth(32); 2538 return getCastInstrCost(Instruction::FPToSI, TruncDst, Src, CCH, CostKind) + 2539 getCastInstrCost(Instruction::Trunc, Dst, TruncDst, 2540 TTI::CastContextHint::None, CostKind); 2541 } 2542 2543 return AdjustCost( 2544 BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I)); 2545 } 2546 2547 InstructionCost X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 2548 Type *CondTy, 2549 CmpInst::Predicate VecPred, 2550 TTI::TargetCostKind CostKind, 2551 const Instruction *I) { 2552 // TODO: Handle other cost kinds. 2553 if (CostKind != TTI::TCK_RecipThroughput) 2554 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, 2555 I); 2556 2557 // Legalize the type. 2558 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2559 2560 MVT MTy = LT.second; 2561 2562 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2563 assert(ISD && "Invalid opcode"); 2564 2565 unsigned ExtraCost = 0; 2566 if (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp) { 2567 // Some vector comparison predicates cost extra instructions. 2568 // TODO: Should we invert this and assume worst case cmp costs 2569 // and reduce for particular predicates? 2570 if (MTy.isVector() && 2571 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 2572 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 2573 ST->hasBWI())) { 2574 // Fallback to I if a specific predicate wasn't specified. 2575 CmpInst::Predicate Pred = VecPred; 2576 if (I && (Pred == CmpInst::BAD_ICMP_PREDICATE || 2577 Pred == CmpInst::BAD_FCMP_PREDICATE)) 2578 Pred = cast<CmpInst>(I)->getPredicate(); 2579 2580 switch (Pred) { 2581 case CmpInst::Predicate::ICMP_NE: 2582 // xor(cmpeq(x,y),-1) 2583 ExtraCost = 1; 2584 break; 2585 case CmpInst::Predicate::ICMP_SGE: 2586 case CmpInst::Predicate::ICMP_SLE: 2587 // xor(cmpgt(x,y),-1) 2588 ExtraCost = 1; 2589 break; 2590 case CmpInst::Predicate::ICMP_ULT: 2591 case CmpInst::Predicate::ICMP_UGT: 2592 // cmpgt(xor(x,signbit),xor(y,signbit)) 2593 // xor(cmpeq(pmaxu(x,y),x),-1) 2594 ExtraCost = 2; 2595 break; 2596 case CmpInst::Predicate::ICMP_ULE: 2597 case CmpInst::Predicate::ICMP_UGE: 2598 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 2599 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 2600 // cmpeq(psubus(x,y),0) 2601 // cmpeq(pminu(x,y),x) 2602 ExtraCost = 1; 2603 } else { 2604 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 2605 ExtraCost = 3; 2606 } 2607 break; 2608 case CmpInst::Predicate::BAD_ICMP_PREDICATE: 2609 case CmpInst::Predicate::BAD_FCMP_PREDICATE: 2610 // Assume worst case scenario and add the maximum extra cost. 2611 ExtraCost = 3; 2612 break; 2613 default: 2614 break; 2615 } 2616 } 2617 } 2618 2619 static const CostTblEntry SLMCostTbl[] = { 2620 // slm pcmpeq/pcmpgt throughput is 2 2621 { ISD::SETCC, MVT::v2i64, 2 }, 2622 }; 2623 2624 static const CostTblEntry AVX512BWCostTbl[] = { 2625 { ISD::SETCC, MVT::v32i16, 1 }, 2626 { ISD::SETCC, MVT::v64i8, 1 }, 2627 2628 { ISD::SELECT, MVT::v32i16, 1 }, 2629 { ISD::SELECT, MVT::v64i8, 1 }, 2630 }; 2631 2632 static const CostTblEntry AVX512CostTbl[] = { 2633 { ISD::SETCC, MVT::v8i64, 1 }, 2634 { ISD::SETCC, MVT::v16i32, 1 }, 2635 { ISD::SETCC, MVT::v8f64, 1 }, 2636 { ISD::SETCC, MVT::v16f32, 1 }, 2637 2638 { ISD::SELECT, MVT::v8i64, 1 }, 2639 { ISD::SELECT, MVT::v16i32, 1 }, 2640 { ISD::SELECT, MVT::v8f64, 1 }, 2641 { ISD::SELECT, MVT::v16f32, 1 }, 2642 2643 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 2644 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 2645 2646 { ISD::SELECT, MVT::v32i16, 2 }, // FIXME: should be 3 2647 { ISD::SELECT, MVT::v64i8, 2 }, // FIXME: should be 3 2648 }; 2649 2650 static const CostTblEntry AVX2CostTbl[] = { 2651 { ISD::SETCC, MVT::v4i64, 1 }, 2652 { ISD::SETCC, MVT::v8i32, 1 }, 2653 { ISD::SETCC, MVT::v16i16, 1 }, 2654 { ISD::SETCC, MVT::v32i8, 1 }, 2655 2656 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 2657 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 2658 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 2659 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 2660 }; 2661 2662 static const CostTblEntry AVX1CostTbl[] = { 2663 { ISD::SETCC, MVT::v4f64, 1 }, 2664 { ISD::SETCC, MVT::v8f32, 1 }, 2665 // AVX1 does not support 8-wide integer compare. 2666 { ISD::SETCC, MVT::v4i64, 4 }, 2667 { ISD::SETCC, MVT::v8i32, 4 }, 2668 { ISD::SETCC, MVT::v16i16, 4 }, 2669 { ISD::SETCC, MVT::v32i8, 4 }, 2670 2671 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 2672 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 2673 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 2674 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 2675 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 2676 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 2677 }; 2678 2679 static const CostTblEntry SSE42CostTbl[] = { 2680 { ISD::SETCC, MVT::v2f64, 1 }, 2681 { ISD::SETCC, MVT::v4f32, 1 }, 2682 { ISD::SETCC, MVT::v2i64, 1 }, 2683 }; 2684 2685 static const CostTblEntry SSE41CostTbl[] = { 2686 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 2687 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 2688 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 2689 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 2690 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 2691 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 2692 }; 2693 2694 static const CostTblEntry SSE2CostTbl[] = { 2695 { ISD::SETCC, MVT::v2f64, 2 }, 2696 { ISD::SETCC, MVT::f64, 1 }, 2697 { ISD::SETCC, MVT::v2i64, 5 }, // pcmpeqd/pcmpgtd expansion 2698 { ISD::SETCC, MVT::v4i32, 1 }, 2699 { ISD::SETCC, MVT::v8i16, 1 }, 2700 { ISD::SETCC, MVT::v16i8, 1 }, 2701 2702 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 2703 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 2704 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 2705 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 2706 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 2707 }; 2708 2709 static const CostTblEntry SSE1CostTbl[] = { 2710 { ISD::SETCC, MVT::v4f32, 2 }, 2711 { ISD::SETCC, MVT::f32, 1 }, 2712 2713 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 2714 }; 2715 2716 if (ST->useSLMArithCosts()) 2717 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2718 return LT.first * (ExtraCost + Entry->Cost); 2719 2720 if (ST->hasBWI()) 2721 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2722 return LT.first * (ExtraCost + Entry->Cost); 2723 2724 if (ST->hasAVX512()) 2725 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2726 return LT.first * (ExtraCost + Entry->Cost); 2727 2728 if (ST->hasAVX2()) 2729 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2730 return LT.first * (ExtraCost + Entry->Cost); 2731 2732 if (ST->hasAVX()) 2733 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2734 return LT.first * (ExtraCost + Entry->Cost); 2735 2736 if (ST->hasSSE42()) 2737 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2738 return LT.first * (ExtraCost + Entry->Cost); 2739 2740 if (ST->hasSSE41()) 2741 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2742 return LT.first * (ExtraCost + Entry->Cost); 2743 2744 if (ST->hasSSE2()) 2745 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2746 return LT.first * (ExtraCost + Entry->Cost); 2747 2748 if (ST->hasSSE1()) 2749 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2750 return LT.first * (ExtraCost + Entry->Cost); 2751 2752 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I); 2753 } 2754 2755 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2756 2757 InstructionCost 2758 X86TTIImpl::getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 2759 TTI::TargetCostKind CostKind) { 2760 2761 // Costs should match the codegen from: 2762 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2763 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2764 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2765 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2766 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2767 2768 // TODO: Overflow intrinsics (*ADDO, *SUBO, *MULO) with vector types are not 2769 // specialized in these tables yet. 2770 static const CostTblEntry AVX512BITALGCostTbl[] = { 2771 { ISD::CTPOP, MVT::v32i16, 1 }, 2772 { ISD::CTPOP, MVT::v64i8, 1 }, 2773 { ISD::CTPOP, MVT::v16i16, 1 }, 2774 { ISD::CTPOP, MVT::v32i8, 1 }, 2775 { ISD::CTPOP, MVT::v8i16, 1 }, 2776 { ISD::CTPOP, MVT::v16i8, 1 }, 2777 }; 2778 static const CostTblEntry AVX512VPOPCNTDQCostTbl[] = { 2779 { ISD::CTPOP, MVT::v8i64, 1 }, 2780 { ISD::CTPOP, MVT::v16i32, 1 }, 2781 { ISD::CTPOP, MVT::v4i64, 1 }, 2782 { ISD::CTPOP, MVT::v8i32, 1 }, 2783 { ISD::CTPOP, MVT::v2i64, 1 }, 2784 { ISD::CTPOP, MVT::v4i32, 1 }, 2785 }; 2786 static const CostTblEntry AVX512CDCostTbl[] = { 2787 { ISD::CTLZ, MVT::v8i64, 1 }, 2788 { ISD::CTLZ, MVT::v16i32, 1 }, 2789 { ISD::CTLZ, MVT::v32i16, 8 }, 2790 { ISD::CTLZ, MVT::v64i8, 20 }, 2791 { ISD::CTLZ, MVT::v4i64, 1 }, 2792 { ISD::CTLZ, MVT::v8i32, 1 }, 2793 { ISD::CTLZ, MVT::v16i16, 4 }, 2794 { ISD::CTLZ, MVT::v32i8, 10 }, 2795 { ISD::CTLZ, MVT::v2i64, 1 }, 2796 { ISD::CTLZ, MVT::v4i32, 1 }, 2797 { ISD::CTLZ, MVT::v8i16, 4 }, 2798 { ISD::CTLZ, MVT::v16i8, 4 }, 2799 }; 2800 static const CostTblEntry AVX512BWCostTbl[] = { 2801 { ISD::ABS, MVT::v32i16, 1 }, 2802 { ISD::ABS, MVT::v64i8, 1 }, 2803 { ISD::BITREVERSE, MVT::v8i64, 3 }, 2804 { ISD::BITREVERSE, MVT::v16i32, 3 }, 2805 { ISD::BITREVERSE, MVT::v32i16, 3 }, 2806 { ISD::BITREVERSE, MVT::v64i8, 2 }, 2807 { ISD::BSWAP, MVT::v8i64, 1 }, 2808 { ISD::BSWAP, MVT::v16i32, 1 }, 2809 { ISD::BSWAP, MVT::v32i16, 1 }, 2810 { ISD::CTLZ, MVT::v8i64, 23 }, 2811 { ISD::CTLZ, MVT::v16i32, 22 }, 2812 { ISD::CTLZ, MVT::v32i16, 18 }, 2813 { ISD::CTLZ, MVT::v64i8, 17 }, 2814 { ISD::CTPOP, MVT::v8i64, 7 }, 2815 { ISD::CTPOP, MVT::v16i32, 11 }, 2816 { ISD::CTPOP, MVT::v32i16, 9 }, 2817 { ISD::CTPOP, MVT::v64i8, 6 }, 2818 { ISD::CTTZ, MVT::v8i64, 10 }, 2819 { ISD::CTTZ, MVT::v16i32, 14 }, 2820 { ISD::CTTZ, MVT::v32i16, 12 }, 2821 { ISD::CTTZ, MVT::v64i8, 9 }, 2822 { ISD::SADDSAT, MVT::v32i16, 1 }, 2823 { ISD::SADDSAT, MVT::v64i8, 1 }, 2824 { ISD::SMAX, MVT::v32i16, 1 }, 2825 { ISD::SMAX, MVT::v64i8, 1 }, 2826 { ISD::SMIN, MVT::v32i16, 1 }, 2827 { ISD::SMIN, MVT::v64i8, 1 }, 2828 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2829 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2830 { ISD::UADDSAT, MVT::v32i16, 1 }, 2831 { ISD::UADDSAT, MVT::v64i8, 1 }, 2832 { ISD::UMAX, MVT::v32i16, 1 }, 2833 { ISD::UMAX, MVT::v64i8, 1 }, 2834 { ISD::UMIN, MVT::v32i16, 1 }, 2835 { ISD::UMIN, MVT::v64i8, 1 }, 2836 { ISD::USUBSAT, MVT::v32i16, 1 }, 2837 { ISD::USUBSAT, MVT::v64i8, 1 }, 2838 }; 2839 static const CostTblEntry AVX512CostTbl[] = { 2840 { ISD::ABS, MVT::v8i64, 1 }, 2841 { ISD::ABS, MVT::v16i32, 1 }, 2842 { ISD::ABS, MVT::v32i16, 2 }, 2843 { ISD::ABS, MVT::v64i8, 2 }, 2844 { ISD::ABS, MVT::v4i64, 1 }, 2845 { ISD::ABS, MVT::v2i64, 1 }, 2846 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2847 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2848 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2849 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2850 { ISD::BSWAP, MVT::v8i64, 4 }, 2851 { ISD::BSWAP, MVT::v16i32, 4 }, 2852 { ISD::BSWAP, MVT::v32i16, 4 }, 2853 { ISD::CTLZ, MVT::v8i64, 29 }, 2854 { ISD::CTLZ, MVT::v16i32, 35 }, 2855 { ISD::CTLZ, MVT::v32i16, 28 }, 2856 { ISD::CTLZ, MVT::v64i8, 18 }, 2857 { ISD::CTPOP, MVT::v8i64, 16 }, 2858 { ISD::CTPOP, MVT::v16i32, 24 }, 2859 { ISD::CTPOP, MVT::v32i16, 18 }, 2860 { ISD::CTPOP, MVT::v64i8, 12 }, 2861 { ISD::CTTZ, MVT::v8i64, 20 }, 2862 { ISD::CTTZ, MVT::v16i32, 28 }, 2863 { ISD::CTTZ, MVT::v32i16, 24 }, 2864 { ISD::CTTZ, MVT::v64i8, 18 }, 2865 { ISD::SMAX, MVT::v8i64, 1 }, 2866 { ISD::SMAX, MVT::v16i32, 1 }, 2867 { ISD::SMAX, MVT::v32i16, 2 }, 2868 { ISD::SMAX, MVT::v64i8, 2 }, 2869 { ISD::SMAX, MVT::v4i64, 1 }, 2870 { ISD::SMAX, MVT::v2i64, 1 }, 2871 { ISD::SMIN, MVT::v8i64, 1 }, 2872 { ISD::SMIN, MVT::v16i32, 1 }, 2873 { ISD::SMIN, MVT::v32i16, 2 }, 2874 { ISD::SMIN, MVT::v64i8, 2 }, 2875 { ISD::SMIN, MVT::v4i64, 1 }, 2876 { ISD::SMIN, MVT::v2i64, 1 }, 2877 { ISD::UMAX, MVT::v8i64, 1 }, 2878 { ISD::UMAX, MVT::v16i32, 1 }, 2879 { ISD::UMAX, MVT::v32i16, 2 }, 2880 { ISD::UMAX, MVT::v64i8, 2 }, 2881 { ISD::UMAX, MVT::v4i64, 1 }, 2882 { ISD::UMAX, MVT::v2i64, 1 }, 2883 { ISD::UMIN, MVT::v8i64, 1 }, 2884 { ISD::UMIN, MVT::v16i32, 1 }, 2885 { ISD::UMIN, MVT::v32i16, 2 }, 2886 { ISD::UMIN, MVT::v64i8, 2 }, 2887 { ISD::UMIN, MVT::v4i64, 1 }, 2888 { ISD::UMIN, MVT::v2i64, 1 }, 2889 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2890 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2891 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2892 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2893 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2894 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2895 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2896 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2897 { ISD::SADDSAT, MVT::v32i16, 2 }, 2898 { ISD::SADDSAT, MVT::v64i8, 2 }, 2899 { ISD::SSUBSAT, MVT::v32i16, 2 }, 2900 { ISD::SSUBSAT, MVT::v64i8, 2 }, 2901 { ISD::UADDSAT, MVT::v32i16, 2 }, 2902 { ISD::UADDSAT, MVT::v64i8, 2 }, 2903 { ISD::USUBSAT, MVT::v32i16, 2 }, 2904 { ISD::USUBSAT, MVT::v64i8, 2 }, 2905 { ISD::FMAXNUM, MVT::f32, 2 }, 2906 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2907 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2908 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2909 { ISD::FMAXNUM, MVT::f64, 2 }, 2910 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2911 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2912 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2913 }; 2914 static const CostTblEntry XOPCostTbl[] = { 2915 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2916 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2917 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2918 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2919 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2920 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2921 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2922 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2923 { ISD::BITREVERSE, MVT::i64, 3 }, 2924 { ISD::BITREVERSE, MVT::i32, 3 }, 2925 { ISD::BITREVERSE, MVT::i16, 3 }, 2926 { ISD::BITREVERSE, MVT::i8, 3 } 2927 }; 2928 static const CostTblEntry AVX2CostTbl[] = { 2929 { ISD::ABS, MVT::v4i64, 2 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2930 { ISD::ABS, MVT::v8i32, 1 }, 2931 { ISD::ABS, MVT::v16i16, 1 }, 2932 { ISD::ABS, MVT::v32i8, 1 }, 2933 { ISD::BITREVERSE, MVT::v2i64, 3 }, 2934 { ISD::BITREVERSE, MVT::v4i64, 3 }, 2935 { ISD::BITREVERSE, MVT::v4i32, 3 }, 2936 { ISD::BITREVERSE, MVT::v8i32, 3 }, 2937 { ISD::BITREVERSE, MVT::v8i16, 3 }, 2938 { ISD::BITREVERSE, MVT::v16i16, 3 }, 2939 { ISD::BITREVERSE, MVT::v16i8, 3 }, 2940 { ISD::BITREVERSE, MVT::v32i8, 3 }, 2941 { ISD::BSWAP, MVT::v4i64, 1 }, 2942 { ISD::BSWAP, MVT::v8i32, 1 }, 2943 { ISD::BSWAP, MVT::v16i16, 1 }, 2944 { ISD::CTLZ, MVT::v2i64, 7 }, 2945 { ISD::CTLZ, MVT::v4i64, 7 }, 2946 { ISD::CTLZ, MVT::v4i32, 5 }, 2947 { ISD::CTLZ, MVT::v8i32, 5 }, 2948 { ISD::CTLZ, MVT::v8i16, 4 }, 2949 { ISD::CTLZ, MVT::v16i16, 4 }, 2950 { ISD::CTLZ, MVT::v16i8, 3 }, 2951 { ISD::CTLZ, MVT::v32i8, 3 }, 2952 { ISD::CTPOP, MVT::v2i64, 3 }, 2953 { ISD::CTPOP, MVT::v4i64, 3 }, 2954 { ISD::CTPOP, MVT::v4i32, 7 }, 2955 { ISD::CTPOP, MVT::v8i32, 7 }, 2956 { ISD::CTPOP, MVT::v8i16, 3 }, 2957 { ISD::CTPOP, MVT::v16i16, 3 }, 2958 { ISD::CTPOP, MVT::v16i8, 2 }, 2959 { ISD::CTPOP, MVT::v32i8, 2 }, 2960 { ISD::CTTZ, MVT::v2i64, 4 }, 2961 { ISD::CTTZ, MVT::v4i64, 4 }, 2962 { ISD::CTTZ, MVT::v4i32, 7 }, 2963 { ISD::CTTZ, MVT::v8i32, 7 }, 2964 { ISD::CTTZ, MVT::v8i16, 4 }, 2965 { ISD::CTTZ, MVT::v16i16, 4 }, 2966 { ISD::CTTZ, MVT::v16i8, 3 }, 2967 { ISD::CTTZ, MVT::v32i8, 3 }, 2968 { ISD::SADDSAT, MVT::v16i16, 1 }, 2969 { ISD::SADDSAT, MVT::v32i8, 1 }, 2970 { ISD::SMAX, MVT::v8i32, 1 }, 2971 { ISD::SMAX, MVT::v16i16, 1 }, 2972 { ISD::SMAX, MVT::v32i8, 1 }, 2973 { ISD::SMIN, MVT::v8i32, 1 }, 2974 { ISD::SMIN, MVT::v16i16, 1 }, 2975 { ISD::SMIN, MVT::v32i8, 1 }, 2976 { ISD::SSUBSAT, MVT::v16i16, 1 }, 2977 { ISD::SSUBSAT, MVT::v32i8, 1 }, 2978 { ISD::UADDSAT, MVT::v16i16, 1 }, 2979 { ISD::UADDSAT, MVT::v32i8, 1 }, 2980 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 2981 { ISD::UMAX, MVT::v8i32, 1 }, 2982 { ISD::UMAX, MVT::v16i16, 1 }, 2983 { ISD::UMAX, MVT::v32i8, 1 }, 2984 { ISD::UMIN, MVT::v8i32, 1 }, 2985 { ISD::UMIN, MVT::v16i16, 1 }, 2986 { ISD::UMIN, MVT::v32i8, 1 }, 2987 { ISD::USUBSAT, MVT::v16i16, 1 }, 2988 { ISD::USUBSAT, MVT::v32i8, 1 }, 2989 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2990 { ISD::FMAXNUM, MVT::v8f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2991 { ISD::FMAXNUM, MVT::v4f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2992 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2993 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2994 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2995 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2996 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2997 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2998 }; 2999 static const CostTblEntry AVX1CostTbl[] = { 3000 { ISD::ABS, MVT::v4i64, 5 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 3001 { ISD::ABS, MVT::v8i32, 3 }, 3002 { ISD::ABS, MVT::v16i16, 3 }, 3003 { ISD::ABS, MVT::v32i8, 3 }, 3004 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 3005 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 3006 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 3007 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 3008 { ISD::BSWAP, MVT::v4i64, 4 }, 3009 { ISD::BSWAP, MVT::v8i32, 4 }, 3010 { ISD::BSWAP, MVT::v16i16, 4 }, 3011 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 3012 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 3013 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 3014 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 3015 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 3016 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 3017 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 3018 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 3019 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 3020 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 3021 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 3022 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 3023 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3024 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3025 { ISD::SMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3026 { ISD::SMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3027 { ISD::SMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3028 { ISD::SMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3029 { ISD::SMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3030 { ISD::SMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3031 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3032 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3033 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3034 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3035 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 3036 { ISD::UMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3037 { ISD::UMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3038 { ISD::UMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3039 { ISD::UMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3040 { ISD::UMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3041 { ISD::UMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3042 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3043 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3044 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 3045 { ISD::FMAXNUM, MVT::f32, 3 }, // MAXSS + CMPUNORDSS + BLENDVPS 3046 { ISD::FMAXNUM, MVT::v4f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 3047 { ISD::FMAXNUM, MVT::v8f32, 5 }, // MAXPS + CMPUNORDPS + BLENDVPS + ? 3048 { ISD::FMAXNUM, MVT::f64, 3 }, // MAXSD + CMPUNORDSD + BLENDVPD 3049 { ISD::FMAXNUM, MVT::v2f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 3050 { ISD::FMAXNUM, MVT::v4f64, 5 }, // MAXPD + CMPUNORDPD + BLENDVPD + ? 3051 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 3052 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 3053 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 3054 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 3055 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 3056 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 3057 }; 3058 static const CostTblEntry GLMCostTbl[] = { 3059 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 3060 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 3061 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 3062 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 3063 }; 3064 static const CostTblEntry SLMCostTbl[] = { 3065 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 3066 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 3067 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 3068 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 3069 }; 3070 static const CostTblEntry SSE42CostTbl[] = { 3071 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 3072 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 3073 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 3074 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 3075 }; 3076 static const CostTblEntry SSE41CostTbl[] = { 3077 { ISD::ABS, MVT::v2i64, 2 }, // BLENDVPD(X,PSUBQ(0,X),X) 3078 { ISD::SMAX, MVT::v4i32, 1 }, 3079 { ISD::SMAX, MVT::v16i8, 1 }, 3080 { ISD::SMIN, MVT::v4i32, 1 }, 3081 { ISD::SMIN, MVT::v16i8, 1 }, 3082 { ISD::UMAX, MVT::v4i32, 1 }, 3083 { ISD::UMAX, MVT::v8i16, 1 }, 3084 { ISD::UMIN, MVT::v4i32, 1 }, 3085 { ISD::UMIN, MVT::v8i16, 1 }, 3086 }; 3087 static const CostTblEntry SSSE3CostTbl[] = { 3088 { ISD::ABS, MVT::v4i32, 1 }, 3089 { ISD::ABS, MVT::v8i16, 1 }, 3090 { ISD::ABS, MVT::v16i8, 1 }, 3091 { ISD::BITREVERSE, MVT::v2i64, 5 }, 3092 { ISD::BITREVERSE, MVT::v4i32, 5 }, 3093 { ISD::BITREVERSE, MVT::v8i16, 5 }, 3094 { ISD::BITREVERSE, MVT::v16i8, 5 }, 3095 { ISD::BSWAP, MVT::v2i64, 1 }, 3096 { ISD::BSWAP, MVT::v4i32, 1 }, 3097 { ISD::BSWAP, MVT::v8i16, 1 }, 3098 { ISD::CTLZ, MVT::v2i64, 23 }, 3099 { ISD::CTLZ, MVT::v4i32, 18 }, 3100 { ISD::CTLZ, MVT::v8i16, 14 }, 3101 { ISD::CTLZ, MVT::v16i8, 9 }, 3102 { ISD::CTPOP, MVT::v2i64, 7 }, 3103 { ISD::CTPOP, MVT::v4i32, 11 }, 3104 { ISD::CTPOP, MVT::v8i16, 9 }, 3105 { ISD::CTPOP, MVT::v16i8, 6 }, 3106 { ISD::CTTZ, MVT::v2i64, 10 }, 3107 { ISD::CTTZ, MVT::v4i32, 14 }, 3108 { ISD::CTTZ, MVT::v8i16, 12 }, 3109 { ISD::CTTZ, MVT::v16i8, 9 } 3110 }; 3111 static const CostTblEntry SSE2CostTbl[] = { 3112 { ISD::ABS, MVT::v2i64, 4 }, 3113 { ISD::ABS, MVT::v4i32, 3 }, 3114 { ISD::ABS, MVT::v8i16, 2 }, 3115 { ISD::ABS, MVT::v16i8, 2 }, 3116 { ISD::BITREVERSE, MVT::v2i64, 29 }, 3117 { ISD::BITREVERSE, MVT::v4i32, 27 }, 3118 { ISD::BITREVERSE, MVT::v8i16, 27 }, 3119 { ISD::BITREVERSE, MVT::v16i8, 20 }, 3120 { ISD::BSWAP, MVT::v2i64, 7 }, 3121 { ISD::BSWAP, MVT::v4i32, 7 }, 3122 { ISD::BSWAP, MVT::v8i16, 7 }, 3123 { ISD::CTLZ, MVT::v2i64, 25 }, 3124 { ISD::CTLZ, MVT::v4i32, 26 }, 3125 { ISD::CTLZ, MVT::v8i16, 20 }, 3126 { ISD::CTLZ, MVT::v16i8, 17 }, 3127 { ISD::CTPOP, MVT::v2i64, 12 }, 3128 { ISD::CTPOP, MVT::v4i32, 15 }, 3129 { ISD::CTPOP, MVT::v8i16, 13 }, 3130 { ISD::CTPOP, MVT::v16i8, 10 }, 3131 { ISD::CTTZ, MVT::v2i64, 14 }, 3132 { ISD::CTTZ, MVT::v4i32, 18 }, 3133 { ISD::CTTZ, MVT::v8i16, 16 }, 3134 { ISD::CTTZ, MVT::v16i8, 13 }, 3135 { ISD::SADDSAT, MVT::v8i16, 1 }, 3136 { ISD::SADDSAT, MVT::v16i8, 1 }, 3137 { ISD::SMAX, MVT::v8i16, 1 }, 3138 { ISD::SMIN, MVT::v8i16, 1 }, 3139 { ISD::SSUBSAT, MVT::v8i16, 1 }, 3140 { ISD::SSUBSAT, MVT::v16i8, 1 }, 3141 { ISD::UADDSAT, MVT::v8i16, 1 }, 3142 { ISD::UADDSAT, MVT::v16i8, 1 }, 3143 { ISD::UMAX, MVT::v8i16, 2 }, 3144 { ISD::UMAX, MVT::v16i8, 1 }, 3145 { ISD::UMIN, MVT::v8i16, 2 }, 3146 { ISD::UMIN, MVT::v16i8, 1 }, 3147 { ISD::USUBSAT, MVT::v8i16, 1 }, 3148 { ISD::USUBSAT, MVT::v16i8, 1 }, 3149 { ISD::FMAXNUM, MVT::f64, 4 }, 3150 { ISD::FMAXNUM, MVT::v2f64, 4 }, 3151 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 3152 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 3153 }; 3154 static const CostTblEntry SSE1CostTbl[] = { 3155 { ISD::FMAXNUM, MVT::f32, 4 }, 3156 { ISD::FMAXNUM, MVT::v4f32, 4 }, 3157 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 3158 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 3159 }; 3160 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 3161 { ISD::CTTZ, MVT::i64, 1 }, 3162 }; 3163 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 3164 { ISD::CTTZ, MVT::i32, 1 }, 3165 { ISD::CTTZ, MVT::i16, 1 }, 3166 { ISD::CTTZ, MVT::i8, 1 }, 3167 }; 3168 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 3169 { ISD::CTLZ, MVT::i64, 1 }, 3170 }; 3171 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 3172 { ISD::CTLZ, MVT::i32, 1 }, 3173 { ISD::CTLZ, MVT::i16, 1 }, 3174 { ISD::CTLZ, MVT::i8, 1 }, 3175 }; 3176 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 3177 { ISD::CTPOP, MVT::i64, 1 }, 3178 }; 3179 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 3180 { ISD::CTPOP, MVT::i32, 1 }, 3181 { ISD::CTPOP, MVT::i16, 1 }, 3182 { ISD::CTPOP, MVT::i8, 1 }, 3183 }; 3184 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 3185 { ISD::ABS, MVT::i64, 2 }, // SUB+CMOV 3186 { ISD::BITREVERSE, MVT::i64, 14 }, 3187 { ISD::BSWAP, MVT::i64, 1 }, 3188 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 3189 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 3190 { ISD::CTPOP, MVT::i64, 10 }, 3191 { ISD::SADDO, MVT::i64, 1 }, 3192 { ISD::UADDO, MVT::i64, 1 }, 3193 { ISD::UMULO, MVT::i64, 2 }, // mulq + seto 3194 }; 3195 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 3196 { ISD::ABS, MVT::i32, 2 }, // SUB+CMOV 3197 { ISD::ABS, MVT::i16, 2 }, // SUB+CMOV 3198 { ISD::BITREVERSE, MVT::i32, 14 }, 3199 { ISD::BITREVERSE, MVT::i16, 14 }, 3200 { ISD::BITREVERSE, MVT::i8, 11 }, 3201 { ISD::BSWAP, MVT::i32, 1 }, 3202 { ISD::BSWAP, MVT::i16, 1 }, // ROL 3203 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 3204 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 3205 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 3206 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 3207 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 3208 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 3209 { ISD::CTPOP, MVT::i32, 8 }, 3210 { ISD::CTPOP, MVT::i16, 9 }, 3211 { ISD::CTPOP, MVT::i8, 7 }, 3212 { ISD::SADDO, MVT::i32, 1 }, 3213 { ISD::SADDO, MVT::i16, 1 }, 3214 { ISD::SADDO, MVT::i8, 1 }, 3215 { ISD::UADDO, MVT::i32, 1 }, 3216 { ISD::UADDO, MVT::i16, 1 }, 3217 { ISD::UADDO, MVT::i8, 1 }, 3218 { ISD::UMULO, MVT::i32, 2 }, // mul + seto 3219 { ISD::UMULO, MVT::i16, 2 }, 3220 { ISD::UMULO, MVT::i8, 2 }, 3221 }; 3222 3223 Type *RetTy = ICA.getReturnType(); 3224 Type *OpTy = RetTy; 3225 Intrinsic::ID IID = ICA.getID(); 3226 unsigned ISD = ISD::DELETED_NODE; 3227 switch (IID) { 3228 default: 3229 break; 3230 case Intrinsic::abs: 3231 ISD = ISD::ABS; 3232 break; 3233 case Intrinsic::bitreverse: 3234 ISD = ISD::BITREVERSE; 3235 break; 3236 case Intrinsic::bswap: 3237 ISD = ISD::BSWAP; 3238 break; 3239 case Intrinsic::ctlz: 3240 ISD = ISD::CTLZ; 3241 break; 3242 case Intrinsic::ctpop: 3243 ISD = ISD::CTPOP; 3244 break; 3245 case Intrinsic::cttz: 3246 ISD = ISD::CTTZ; 3247 break; 3248 case Intrinsic::maxnum: 3249 case Intrinsic::minnum: 3250 // FMINNUM has same costs so don't duplicate. 3251 ISD = ISD::FMAXNUM; 3252 break; 3253 case Intrinsic::sadd_sat: 3254 ISD = ISD::SADDSAT; 3255 break; 3256 case Intrinsic::smax: 3257 ISD = ISD::SMAX; 3258 break; 3259 case Intrinsic::smin: 3260 ISD = ISD::SMIN; 3261 break; 3262 case Intrinsic::ssub_sat: 3263 ISD = ISD::SSUBSAT; 3264 break; 3265 case Intrinsic::uadd_sat: 3266 ISD = ISD::UADDSAT; 3267 break; 3268 case Intrinsic::umax: 3269 ISD = ISD::UMAX; 3270 break; 3271 case Intrinsic::umin: 3272 ISD = ISD::UMIN; 3273 break; 3274 case Intrinsic::usub_sat: 3275 ISD = ISD::USUBSAT; 3276 break; 3277 case Intrinsic::sqrt: 3278 ISD = ISD::FSQRT; 3279 break; 3280 case Intrinsic::sadd_with_overflow: 3281 case Intrinsic::ssub_with_overflow: 3282 // SSUBO has same costs so don't duplicate. 3283 ISD = ISD::SADDO; 3284 OpTy = RetTy->getContainedType(0); 3285 break; 3286 case Intrinsic::uadd_with_overflow: 3287 case Intrinsic::usub_with_overflow: 3288 // USUBO has same costs so don't duplicate. 3289 ISD = ISD::UADDO; 3290 OpTy = RetTy->getContainedType(0); 3291 break; 3292 case Intrinsic::umul_with_overflow: 3293 case Intrinsic::smul_with_overflow: 3294 // SMULO has same costs so don't duplicate. 3295 ISD = ISD::UMULO; 3296 OpTy = RetTy->getContainedType(0); 3297 break; 3298 } 3299 3300 if (ISD != ISD::DELETED_NODE) { 3301 // Legalize the type. 3302 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 3303 MVT MTy = LT.second; 3304 3305 // Attempt to lookup cost. 3306 if (ISD == ISD::BITREVERSE && ST->hasGFNI() && ST->hasSSSE3() && 3307 MTy.isVector()) { 3308 // With PSHUFB the code is very similar for all types. If we have integer 3309 // byte operations, we just need a GF2P8AFFINEQB for vXi8. For other types 3310 // we also need a PSHUFB. 3311 unsigned Cost = MTy.getVectorElementType() == MVT::i8 ? 1 : 2; 3312 3313 // Without byte operations, we need twice as many GF2P8AFFINEQB and PSHUFB 3314 // instructions. We also need an extract and an insert. 3315 if (!(MTy.is128BitVector() || (ST->hasAVX2() && MTy.is256BitVector()) || 3316 (ST->hasBWI() && MTy.is512BitVector()))) 3317 Cost = Cost * 2 + 2; 3318 3319 return LT.first * Cost; 3320 } 3321 3322 auto adjustTableCost = [](const CostTblEntry &Entry, 3323 InstructionCost LegalizationCost, 3324 FastMathFlags FMF) { 3325 // If there are no NANs to deal with, then these are reduced to a 3326 // single MIN** or MAX** instruction instead of the MIN/CMP/SELECT that we 3327 // assume is used in the non-fast case. 3328 if (Entry.ISD == ISD::FMAXNUM || Entry.ISD == ISD::FMINNUM) { 3329 if (FMF.noNaNs()) 3330 return LegalizationCost * 1; 3331 } 3332 return LegalizationCost * (int)Entry.Cost; 3333 }; 3334 3335 if (ST->useGLMDivSqrtCosts()) 3336 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 3337 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3338 3339 if (ST->useSLMArithCosts()) 3340 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 3341 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3342 3343 if (ST->hasBITALG()) 3344 if (const auto *Entry = CostTableLookup(AVX512BITALGCostTbl, ISD, MTy)) 3345 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3346 3347 if (ST->hasVPOPCNTDQ()) 3348 if (const auto *Entry = CostTableLookup(AVX512VPOPCNTDQCostTbl, ISD, MTy)) 3349 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3350 3351 if (ST->hasCDI()) 3352 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 3353 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3354 3355 if (ST->hasBWI()) 3356 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3357 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3358 3359 if (ST->hasAVX512()) 3360 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3361 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3362 3363 if (ST->hasXOP()) 3364 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3365 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3366 3367 if (ST->hasAVX2()) 3368 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3369 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3370 3371 if (ST->hasAVX()) 3372 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3373 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3374 3375 if (ST->hasSSE42()) 3376 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3377 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3378 3379 if (ST->hasSSE41()) 3380 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3381 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3382 3383 if (ST->hasSSSE3()) 3384 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 3385 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3386 3387 if (ST->hasSSE2()) 3388 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3389 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3390 3391 if (ST->hasSSE1()) 3392 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3393 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3394 3395 if (ST->hasBMI()) { 3396 if (ST->is64Bit()) 3397 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 3398 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3399 3400 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 3401 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3402 } 3403 3404 if (ST->hasLZCNT()) { 3405 if (ST->is64Bit()) 3406 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 3407 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3408 3409 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 3410 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3411 } 3412 3413 if (ST->hasPOPCNT()) { 3414 if (ST->is64Bit()) 3415 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 3416 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3417 3418 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 3419 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3420 } 3421 3422 if (ISD == ISD::BSWAP && ST->hasMOVBE() && ST->hasFastMOVBE()) { 3423 if (const Instruction *II = ICA.getInst()) { 3424 if (II->hasOneUse() && isa<StoreInst>(II->user_back())) 3425 return TTI::TCC_Free; 3426 if (auto *LI = dyn_cast<LoadInst>(II->getOperand(0))) { 3427 if (LI->hasOneUse()) 3428 return TTI::TCC_Free; 3429 } 3430 } 3431 } 3432 3433 if (ST->is64Bit()) 3434 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3435 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3436 3437 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3438 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3439 } 3440 3441 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3442 } 3443 3444 InstructionCost 3445 X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 3446 TTI::TargetCostKind CostKind) { 3447 if (ICA.isTypeBasedOnly()) 3448 return getTypeBasedIntrinsicInstrCost(ICA, CostKind); 3449 3450 static const CostTblEntry AVX512BWCostTbl[] = { 3451 { ISD::ROTL, MVT::v32i16, 2 }, 3452 { ISD::ROTL, MVT::v16i16, 2 }, 3453 { ISD::ROTL, MVT::v8i16, 2 }, 3454 { ISD::ROTL, MVT::v64i8, 5 }, 3455 { ISD::ROTL, MVT::v32i8, 5 }, 3456 { ISD::ROTL, MVT::v16i8, 5 }, 3457 { ISD::ROTR, MVT::v32i16, 2 }, 3458 { ISD::ROTR, MVT::v16i16, 2 }, 3459 { ISD::ROTR, MVT::v8i16, 2 }, 3460 { ISD::ROTR, MVT::v64i8, 5 }, 3461 { ISD::ROTR, MVT::v32i8, 5 }, 3462 { ISD::ROTR, MVT::v16i8, 5 } 3463 }; 3464 static const CostTblEntry AVX512CostTbl[] = { 3465 { ISD::ROTL, MVT::v8i64, 1 }, 3466 { ISD::ROTL, MVT::v4i64, 1 }, 3467 { ISD::ROTL, MVT::v2i64, 1 }, 3468 { ISD::ROTL, MVT::v16i32, 1 }, 3469 { ISD::ROTL, MVT::v8i32, 1 }, 3470 { ISD::ROTL, MVT::v4i32, 1 }, 3471 { ISD::ROTR, MVT::v8i64, 1 }, 3472 { ISD::ROTR, MVT::v4i64, 1 }, 3473 { ISD::ROTR, MVT::v2i64, 1 }, 3474 { ISD::ROTR, MVT::v16i32, 1 }, 3475 { ISD::ROTR, MVT::v8i32, 1 }, 3476 { ISD::ROTR, MVT::v4i32, 1 } 3477 }; 3478 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 3479 static const CostTblEntry XOPCostTbl[] = { 3480 { ISD::ROTL, MVT::v4i64, 4 }, 3481 { ISD::ROTL, MVT::v8i32, 4 }, 3482 { ISD::ROTL, MVT::v16i16, 4 }, 3483 { ISD::ROTL, MVT::v32i8, 4 }, 3484 { ISD::ROTL, MVT::v2i64, 1 }, 3485 { ISD::ROTL, MVT::v4i32, 1 }, 3486 { ISD::ROTL, MVT::v8i16, 1 }, 3487 { ISD::ROTL, MVT::v16i8, 1 }, 3488 { ISD::ROTR, MVT::v4i64, 6 }, 3489 { ISD::ROTR, MVT::v8i32, 6 }, 3490 { ISD::ROTR, MVT::v16i16, 6 }, 3491 { ISD::ROTR, MVT::v32i8, 6 }, 3492 { ISD::ROTR, MVT::v2i64, 2 }, 3493 { ISD::ROTR, MVT::v4i32, 2 }, 3494 { ISD::ROTR, MVT::v8i16, 2 }, 3495 { ISD::ROTR, MVT::v16i8, 2 } 3496 }; 3497 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 3498 { ISD::ROTL, MVT::i64, 1 }, 3499 { ISD::ROTR, MVT::i64, 1 }, 3500 { ISD::FSHL, MVT::i64, 4 } 3501 }; 3502 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 3503 { ISD::ROTL, MVT::i32, 1 }, 3504 { ISD::ROTL, MVT::i16, 1 }, 3505 { ISD::ROTL, MVT::i8, 1 }, 3506 { ISD::ROTR, MVT::i32, 1 }, 3507 { ISD::ROTR, MVT::i16, 1 }, 3508 { ISD::ROTR, MVT::i8, 1 }, 3509 { ISD::FSHL, MVT::i32, 4 }, 3510 { ISD::FSHL, MVT::i16, 4 }, 3511 { ISD::FSHL, MVT::i8, 4 } 3512 }; 3513 3514 Intrinsic::ID IID = ICA.getID(); 3515 Type *RetTy = ICA.getReturnType(); 3516 const SmallVectorImpl<const Value *> &Args = ICA.getArgs(); 3517 unsigned ISD = ISD::DELETED_NODE; 3518 switch (IID) { 3519 default: 3520 break; 3521 case Intrinsic::fshl: 3522 ISD = ISD::FSHL; 3523 if (Args[0] == Args[1]) 3524 ISD = ISD::ROTL; 3525 break; 3526 case Intrinsic::fshr: 3527 // FSHR has same costs so don't duplicate. 3528 ISD = ISD::FSHL; 3529 if (Args[0] == Args[1]) 3530 ISD = ISD::ROTR; 3531 break; 3532 } 3533 3534 if (ISD != ISD::DELETED_NODE) { 3535 // Legalize the type. 3536 std::pair<InstructionCost, MVT> LT = 3537 TLI->getTypeLegalizationCost(DL, RetTy); 3538 MVT MTy = LT.second; 3539 3540 // Attempt to lookup cost. 3541 if (ST->hasBWI()) 3542 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3543 return LT.first * Entry->Cost; 3544 3545 if (ST->hasAVX512()) 3546 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3547 return LT.first * Entry->Cost; 3548 3549 if (ST->hasXOP()) 3550 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3551 return LT.first * Entry->Cost; 3552 3553 if (ST->is64Bit()) 3554 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3555 return LT.first * Entry->Cost; 3556 3557 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3558 return LT.first * Entry->Cost; 3559 } 3560 3561 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3562 } 3563 3564 InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, 3565 unsigned Index) { 3566 static const CostTblEntry SLMCostTbl[] = { 3567 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 3568 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 3569 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 3570 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 3571 }; 3572 3573 assert(Val->isVectorTy() && "This must be a vector type"); 3574 Type *ScalarType = Val->getScalarType(); 3575 int RegisterFileMoveCost = 0; 3576 3577 // Non-immediate extraction/insertion can be handled as a sequence of 3578 // aliased loads+stores via the stack. 3579 if (Index == -1U && (Opcode == Instruction::ExtractElement || 3580 Opcode == Instruction::InsertElement)) { 3581 // TODO: On some SSE41+ targets, we expand to cmp+splat+select patterns: 3582 // inselt N0, N1, N2 --> select (SplatN2 == {0,1,2...}) ? SplatN1 : N0. 3583 3584 // TODO: Move this to BasicTTIImpl.h? We'd need better gep + index handling. 3585 assert(isa<FixedVectorType>(Val) && "Fixed vector type expected"); 3586 Align VecAlign = DL.getPrefTypeAlign(Val); 3587 Align SclAlign = DL.getPrefTypeAlign(ScalarType); 3588 3589 // Extract - store vector to stack, load scalar. 3590 if (Opcode == Instruction::ExtractElement) { 3591 return getMemoryOpCost(Instruction::Store, Val, VecAlign, 0, 3592 TTI::TargetCostKind::TCK_RecipThroughput) + 3593 getMemoryOpCost(Instruction::Load, ScalarType, SclAlign, 0, 3594 TTI::TargetCostKind::TCK_RecipThroughput); 3595 } 3596 // Insert - store vector to stack, store scalar, load vector. 3597 if (Opcode == Instruction::InsertElement) { 3598 return getMemoryOpCost(Instruction::Store, Val, VecAlign, 0, 3599 TTI::TargetCostKind::TCK_RecipThroughput) + 3600 getMemoryOpCost(Instruction::Store, ScalarType, SclAlign, 0, 3601 TTI::TargetCostKind::TCK_RecipThroughput) + 3602 getMemoryOpCost(Instruction::Load, Val, VecAlign, 0, 3603 TTI::TargetCostKind::TCK_RecipThroughput); 3604 } 3605 } 3606 3607 if (Index != -1U && (Opcode == Instruction::ExtractElement || 3608 Opcode == Instruction::InsertElement)) { 3609 // Extraction of vXi1 elements are now efficiently handled by MOVMSK. 3610 if (Opcode == Instruction::ExtractElement && 3611 ScalarType->getScalarSizeInBits() == 1 && 3612 cast<FixedVectorType>(Val)->getNumElements() > 1) 3613 return 1; 3614 3615 // Legalize the type. 3616 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 3617 3618 // This type is legalized to a scalar type. 3619 if (!LT.second.isVector()) 3620 return 0; 3621 3622 // The type may be split. Normalize the index to the new type. 3623 unsigned SizeInBits = LT.second.getSizeInBits(); 3624 unsigned NumElts = LT.second.getVectorNumElements(); 3625 unsigned SubNumElts = NumElts; 3626 Index = Index % NumElts; 3627 3628 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 3629 // For inserts, we also need to insert the subvector back. 3630 if (SizeInBits > 128) { 3631 assert((SizeInBits % 128) == 0 && "Illegal vector"); 3632 unsigned NumSubVecs = SizeInBits / 128; 3633 SubNumElts = NumElts / NumSubVecs; 3634 if (SubNumElts <= Index) { 3635 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 3636 Index %= SubNumElts; 3637 } 3638 } 3639 3640 if (Index == 0) { 3641 // Floating point scalars are already located in index #0. 3642 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 3643 // true for all. 3644 if (ScalarType->isFloatingPointTy()) 3645 return RegisterFileMoveCost; 3646 3647 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 3648 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 3649 return 1 + RegisterFileMoveCost; 3650 } 3651 3652 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3653 assert(ISD && "Unexpected vector opcode"); 3654 MVT MScalarTy = LT.second.getScalarType(); 3655 if (ST->useSLMArithCosts()) 3656 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 3657 return Entry->Cost + RegisterFileMoveCost; 3658 3659 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 3660 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3661 (MScalarTy.isInteger() && ST->hasSSE41())) 3662 return 1 + RegisterFileMoveCost; 3663 3664 // Assume insertps is relatively cheap on all targets. 3665 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 3666 Opcode == Instruction::InsertElement) 3667 return 1 + RegisterFileMoveCost; 3668 3669 // For extractions we just need to shuffle the element to index 0, which 3670 // should be very cheap (assume cost = 1). For insertions we need to shuffle 3671 // the elements to its destination. In both cases we must handle the 3672 // subvector move(s). 3673 // If the vector type is already less than 128-bits then don't reduce it. 3674 // TODO: Under what circumstances should we shuffle using the full width? 3675 InstructionCost ShuffleCost = 1; 3676 if (Opcode == Instruction::InsertElement) { 3677 auto *SubTy = cast<VectorType>(Val); 3678 EVT VT = TLI->getValueType(DL, Val); 3679 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 3680 SubTy = FixedVectorType::get(ScalarType, SubNumElts); 3681 ShuffleCost = 3682 getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, None, 0, SubTy); 3683 } 3684 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 3685 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 3686 } 3687 3688 // Add to the base cost if we know that the extracted element of a vector is 3689 // destined to be moved to and used in the integer register file. 3690 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 3691 RegisterFileMoveCost += 1; 3692 3693 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 3694 } 3695 3696 InstructionCost X86TTIImpl::getScalarizationOverhead(VectorType *Ty, 3697 const APInt &DemandedElts, 3698 bool Insert, 3699 bool Extract) { 3700 InstructionCost Cost = 0; 3701 3702 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much 3703 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT. 3704 if (Insert) { 3705 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3706 MVT MScalarTy = LT.second.getScalarType(); 3707 unsigned SizeInBits = LT.second.getSizeInBits(); 3708 3709 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3710 (MScalarTy.isInteger() && ST->hasSSE41()) || 3711 (MScalarTy == MVT::f32 && ST->hasSSE41())) { 3712 // For types we can insert directly, insertion into 128-bit sub vectors is 3713 // cheap, followed by a cheap chain of concatenations. 3714 if (SizeInBits <= 128) { 3715 Cost += 3716 BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, false); 3717 } else { 3718 // In each 128-lane, if at least one index is demanded but not all 3719 // indices are demanded and this 128-lane is not the first 128-lane of 3720 // the legalized-vector, then this 128-lane needs a extracti128; If in 3721 // each 128-lane, there is at least one demanded index, this 128-lane 3722 // needs a inserti128. 3723 3724 // The following cases will help you build a better understanding: 3725 // Assume we insert several elements into a v8i32 vector in avx2, 3726 // Case#1: inserting into 1th index needs vpinsrd + inserti128. 3727 // Case#2: inserting into 5th index needs extracti128 + vpinsrd + 3728 // inserti128. 3729 // Case#3: inserting into 4,5,6,7 index needs 4*vpinsrd + inserti128. 3730 const int CostValue = *LT.first.getValue(); 3731 assert(CostValue >= 0 && "Negative cost!"); 3732 unsigned Num128Lanes = SizeInBits / 128 * CostValue; 3733 unsigned NumElts = LT.second.getVectorNumElements() * CostValue; 3734 APInt WidenedDemandedElts = DemandedElts.zextOrSelf(NumElts); 3735 unsigned Scale = NumElts / Num128Lanes; 3736 // We iterate each 128-lane, and check if we need a 3737 // extracti128/inserti128 for this 128-lane. 3738 for (unsigned I = 0; I < NumElts; I += Scale) { 3739 APInt Mask = WidenedDemandedElts.getBitsSet(NumElts, I, I + Scale); 3740 APInt MaskedDE = Mask & WidenedDemandedElts; 3741 unsigned Population = MaskedDE.countPopulation(); 3742 Cost += (Population > 0 && Population != Scale && 3743 I % LT.second.getVectorNumElements() != 0); 3744 Cost += Population > 0; 3745 } 3746 Cost += DemandedElts.countPopulation(); 3747 3748 // For vXf32 cases, insertion into the 0'th index in each v4f32 3749 // 128-bit vector is free. 3750 // NOTE: This assumes legalization widens vXf32 vectors. 3751 if (MScalarTy == MVT::f32) 3752 for (unsigned i = 0, e = cast<FixedVectorType>(Ty)->getNumElements(); 3753 i < e; i += 4) 3754 if (DemandedElts[i]) 3755 Cost--; 3756 } 3757 } else if (LT.second.isVector()) { 3758 // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded 3759 // integer element as a SCALAR_TO_VECTOR, then we build the vector as a 3760 // series of UNPCK followed by CONCAT_VECTORS - all of these can be 3761 // considered cheap. 3762 if (Ty->isIntOrIntVectorTy()) 3763 Cost += DemandedElts.countPopulation(); 3764 3765 // Get the smaller of the legalized or original pow2-extended number of 3766 // vector elements, which represents the number of unpacks we'll end up 3767 // performing. 3768 unsigned NumElts = LT.second.getVectorNumElements(); 3769 unsigned Pow2Elts = 3770 PowerOf2Ceil(cast<FixedVectorType>(Ty)->getNumElements()); 3771 Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first; 3772 } 3773 } 3774 3775 // TODO: Use default extraction for now, but we should investigate extending this 3776 // to handle repeated subvector extraction. 3777 if (Extract) 3778 Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, false, Extract); 3779 3780 return Cost; 3781 } 3782 3783 InstructionCost 3784 X86TTIImpl::getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, 3785 int VF, const APInt &DemandedDstElts, 3786 TTI::TargetCostKind CostKind) { 3787 const unsigned EltTyBits = DL.getTypeSizeInBits(EltTy); 3788 // We don't differentiate element types here, only element bit width. 3789 EltTy = IntegerType::getIntNTy(EltTy->getContext(), EltTyBits); 3790 3791 auto bailout = [&]() { 3792 return BaseT::getReplicationShuffleCost(EltTy, ReplicationFactor, VF, 3793 DemandedDstElts, CostKind); 3794 }; 3795 3796 // For now, only deal with AVX512 cases. 3797 if (!ST->hasAVX512()) 3798 return bailout(); 3799 3800 // Do we have a native shuffle for this element type, or should we promote? 3801 unsigned PromEltTyBits = EltTyBits; 3802 switch (EltTyBits) { 3803 case 32: 3804 case 64: 3805 break; // AVX512F. 3806 case 16: 3807 if (!ST->hasBWI()) 3808 PromEltTyBits = 32; // promote to i32, AVX512F. 3809 break; // AVX512BW 3810 case 8: 3811 if (!ST->hasVBMI()) 3812 PromEltTyBits = 32; // promote to i32, AVX512F. 3813 break; // AVX512VBMI 3814 case 1: 3815 // There is no support for shuffling i1 elements. We *must* promote. 3816 if (ST->hasBWI()) { 3817 if (ST->hasVBMI()) 3818 PromEltTyBits = 8; // promote to i8, AVX512VBMI. 3819 else 3820 PromEltTyBits = 16; // promote to i16, AVX512BW. 3821 break; 3822 } 3823 if (ST->hasDQI()) { 3824 PromEltTyBits = 32; // promote to i32, AVX512F. 3825 break; 3826 } 3827 return bailout(); 3828 default: 3829 return bailout(); 3830 } 3831 auto *PromEltTy = IntegerType::getIntNTy(EltTy->getContext(), PromEltTyBits); 3832 3833 auto *SrcVecTy = FixedVectorType::get(EltTy, VF); 3834 auto *PromSrcVecTy = FixedVectorType::get(PromEltTy, VF); 3835 3836 int NumDstElements = VF * ReplicationFactor; 3837 auto *PromDstVecTy = FixedVectorType::get(PromEltTy, NumDstElements); 3838 auto *DstVecTy = FixedVectorType::get(EltTy, NumDstElements); 3839 3840 // Legalize the types. 3841 MVT LegalSrcVecTy = TLI->getTypeLegalizationCost(DL, SrcVecTy).second; 3842 MVT LegalPromSrcVecTy = TLI->getTypeLegalizationCost(DL, PromSrcVecTy).second; 3843 MVT LegalPromDstVecTy = TLI->getTypeLegalizationCost(DL, PromDstVecTy).second; 3844 MVT LegalDstVecTy = TLI->getTypeLegalizationCost(DL, DstVecTy).second; 3845 // They should have legalized into vector types. 3846 if (!LegalSrcVecTy.isVector() || !LegalPromSrcVecTy.isVector() || 3847 !LegalPromDstVecTy.isVector() || !LegalDstVecTy.isVector()) 3848 return bailout(); 3849 3850 if (PromEltTyBits != EltTyBits) { 3851 // If we have to perform the shuffle with wider elt type than our data type, 3852 // then we will first need to anyext (we don't care about the new bits) 3853 // the source elements, and then truncate Dst elements. 3854 InstructionCost PromotionCost; 3855 PromotionCost += getCastInstrCost( 3856 Instruction::SExt, /*Dst=*/PromSrcVecTy, /*Src=*/SrcVecTy, 3857 TargetTransformInfo::CastContextHint::None, CostKind); 3858 PromotionCost += 3859 getCastInstrCost(Instruction::Trunc, /*Dst=*/DstVecTy, 3860 /*Src=*/PromDstVecTy, 3861 TargetTransformInfo::CastContextHint::None, CostKind); 3862 return PromotionCost + getReplicationShuffleCost(PromEltTy, 3863 ReplicationFactor, VF, 3864 DemandedDstElts, CostKind); 3865 } 3866 3867 assert(LegalSrcVecTy.getScalarSizeInBits() == EltTyBits && 3868 LegalSrcVecTy.getScalarType() == LegalDstVecTy.getScalarType() && 3869 "We expect that the legalization doesn't affect the element width, " 3870 "doesn't coalesce/split elements."); 3871 3872 unsigned NumEltsPerDstVec = LegalDstVecTy.getVectorNumElements(); 3873 unsigned NumDstVectors = 3874 divideCeil(DstVecTy->getNumElements(), NumEltsPerDstVec); 3875 3876 auto *SingleDstVecTy = FixedVectorType::get(EltTy, NumEltsPerDstVec); 3877 3878 // Not all the produced Dst elements may be demanded. In our case, 3879 // given that a single Dst vector is formed by a single shuffle, 3880 // if all elements that will form a single Dst vector aren't demanded, 3881 // then we won't need to do that shuffle, so adjust the cost accordingly. 3882 APInt DemandedDstVectors = APIntOps::ScaleBitMask( 3883 DemandedDstElts.zextOrSelf(NumDstVectors * NumEltsPerDstVec), 3884 NumDstVectors); 3885 unsigned NumDstVectorsDemanded = DemandedDstVectors.countPopulation(); 3886 3887 InstructionCost SingleShuffleCost = 3888 getShuffleCost(TTI::SK_PermuteSingleSrc, SingleDstVecTy, 3889 /*Mask=*/None, /*Index=*/0, /*SubTp=*/nullptr); 3890 return NumDstVectorsDemanded * SingleShuffleCost; 3891 } 3892 3893 InstructionCost X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 3894 MaybeAlign Alignment, 3895 unsigned AddressSpace, 3896 TTI::TargetCostKind CostKind, 3897 const Instruction *I) { 3898 // TODO: Handle other cost kinds. 3899 if (CostKind != TTI::TCK_RecipThroughput) { 3900 if (auto *SI = dyn_cast_or_null<StoreInst>(I)) { 3901 // Store instruction with index and scale costs 2 Uops. 3902 // Check the preceding GEP to identify non-const indices. 3903 if (auto *GEP = dyn_cast<GetElementPtrInst>(SI->getPointerOperand())) { 3904 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3905 return TTI::TCC_Basic * 2; 3906 } 3907 } 3908 return TTI::TCC_Basic; 3909 } 3910 3911 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 3912 "Invalid Opcode"); 3913 // Type legalization can't handle structs 3914 if (TLI->getValueType(DL, Src, true) == MVT::Other) 3915 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3916 CostKind); 3917 3918 // Legalize the type. 3919 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 3920 3921 auto *VTy = dyn_cast<FixedVectorType>(Src); 3922 3923 // Handle the simple case of non-vectors. 3924 // NOTE: this assumes that legalization never creates vector from scalars! 3925 if (!VTy || !LT.second.isVector()) 3926 // Each load/store unit costs 1. 3927 return LT.first * 1; 3928 3929 bool IsLoad = Opcode == Instruction::Load; 3930 3931 Type *EltTy = VTy->getElementType(); 3932 3933 const int EltTyBits = DL.getTypeSizeInBits(EltTy); 3934 3935 InstructionCost Cost = 0; 3936 3937 // Source of truth: how many elements were there in the original IR vector? 3938 const unsigned SrcNumElt = VTy->getNumElements(); 3939 3940 // How far have we gotten? 3941 int NumEltRemaining = SrcNumElt; 3942 // Note that we intentionally capture by-reference, NumEltRemaining changes. 3943 auto NumEltDone = [&]() { return SrcNumElt - NumEltRemaining; }; 3944 3945 const int MaxLegalOpSizeBytes = divideCeil(LT.second.getSizeInBits(), 8); 3946 3947 // Note that even if we can store 64 bits of an XMM, we still operate on XMM. 3948 const unsigned XMMBits = 128; 3949 if (XMMBits % EltTyBits != 0) 3950 // Vector size must be a multiple of the element size. I.e. no padding. 3951 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3952 CostKind); 3953 const int NumEltPerXMM = XMMBits / EltTyBits; 3954 3955 auto *XMMVecTy = FixedVectorType::get(EltTy, NumEltPerXMM); 3956 3957 for (int CurrOpSizeBytes = MaxLegalOpSizeBytes, SubVecEltsLeft = 0; 3958 NumEltRemaining > 0; CurrOpSizeBytes /= 2) { 3959 // How many elements would a single op deal with at once? 3960 if ((8 * CurrOpSizeBytes) % EltTyBits != 0) 3961 // Vector size must be a multiple of the element size. I.e. no padding. 3962 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3963 CostKind); 3964 int CurrNumEltPerOp = (8 * CurrOpSizeBytes) / EltTyBits; 3965 3966 assert(CurrOpSizeBytes > 0 && CurrNumEltPerOp > 0 && "How'd we get here?"); 3967 assert((((NumEltRemaining * EltTyBits) < (2 * 8 * CurrOpSizeBytes)) || 3968 (CurrOpSizeBytes == MaxLegalOpSizeBytes)) && 3969 "Unless we haven't halved the op size yet, " 3970 "we have less than two op's sized units of work left."); 3971 3972 auto *CurrVecTy = CurrNumEltPerOp > NumEltPerXMM 3973 ? FixedVectorType::get(EltTy, CurrNumEltPerOp) 3974 : XMMVecTy; 3975 3976 assert(CurrVecTy->getNumElements() % CurrNumEltPerOp == 0 && 3977 "After halving sizes, the vector elt count is no longer a multiple " 3978 "of number of elements per operation?"); 3979 auto *CoalescedVecTy = 3980 CurrNumEltPerOp == 1 3981 ? CurrVecTy 3982 : FixedVectorType::get( 3983 IntegerType::get(Src->getContext(), 3984 EltTyBits * CurrNumEltPerOp), 3985 CurrVecTy->getNumElements() / CurrNumEltPerOp); 3986 assert(DL.getTypeSizeInBits(CoalescedVecTy) == 3987 DL.getTypeSizeInBits(CurrVecTy) && 3988 "coalesciing elements doesn't change vector width."); 3989 3990 while (NumEltRemaining > 0) { 3991 assert(SubVecEltsLeft >= 0 && "Subreg element count overconsumtion?"); 3992 3993 // Can we use this vector size, as per the remaining element count? 3994 // Iff the vector is naturally aligned, we can do a wide load regardless. 3995 if (NumEltRemaining < CurrNumEltPerOp && 3996 (!IsLoad || Alignment.valueOrOne() < CurrOpSizeBytes) && 3997 CurrOpSizeBytes != 1) 3998 break; // Try smalled vector size. 3999 4000 bool Is0thSubVec = (NumEltDone() % LT.second.getVectorNumElements()) == 0; 4001 4002 // If we have fully processed the previous reg, we need to replenish it. 4003 if (SubVecEltsLeft == 0) { 4004 SubVecEltsLeft += CurrVecTy->getNumElements(); 4005 // And that's free only for the 0'th subvector of a legalized vector. 4006 if (!Is0thSubVec) 4007 Cost += getShuffleCost(IsLoad ? TTI::ShuffleKind::SK_InsertSubvector 4008 : TTI::ShuffleKind::SK_ExtractSubvector, 4009 VTy, None, NumEltDone(), CurrVecTy); 4010 } 4011 4012 // While we can directly load/store ZMM, YMM, and 64-bit halves of XMM, 4013 // for smaller widths (32/16/8) we have to insert/extract them separately. 4014 // Again, it's free for the 0'th subreg (if op is 32/64 bit wide, 4015 // but let's pretend that it is also true for 16/8 bit wide ops...) 4016 if (CurrOpSizeBytes <= 32 / 8 && !Is0thSubVec) { 4017 int NumEltDoneInCurrXMM = NumEltDone() % NumEltPerXMM; 4018 assert(NumEltDoneInCurrXMM % CurrNumEltPerOp == 0 && ""); 4019 int CoalescedVecEltIdx = NumEltDoneInCurrXMM / CurrNumEltPerOp; 4020 APInt DemandedElts = 4021 APInt::getBitsSet(CoalescedVecTy->getNumElements(), 4022 CoalescedVecEltIdx, CoalescedVecEltIdx + 1); 4023 assert(DemandedElts.countPopulation() == 1 && "Inserting single value"); 4024 Cost += getScalarizationOverhead(CoalescedVecTy, DemandedElts, IsLoad, 4025 !IsLoad); 4026 } 4027 4028 // This isn't exactly right. We're using slow unaligned 32-byte accesses 4029 // as a proxy for a double-pumped AVX memory interface such as on 4030 // Sandybridge. 4031 if (CurrOpSizeBytes == 32 && ST->isUnalignedMem32Slow()) 4032 Cost += 2; 4033 else 4034 Cost += 1; 4035 4036 SubVecEltsLeft -= CurrNumEltPerOp; 4037 NumEltRemaining -= CurrNumEltPerOp; 4038 Alignment = commonAlignment(Alignment.valueOrOne(), CurrOpSizeBytes); 4039 } 4040 } 4041 4042 assert(NumEltRemaining <= 0 && "Should have processed all the elements."); 4043 4044 return Cost; 4045 } 4046 4047 InstructionCost 4048 X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, Align Alignment, 4049 unsigned AddressSpace, 4050 TTI::TargetCostKind CostKind) { 4051 bool IsLoad = (Instruction::Load == Opcode); 4052 bool IsStore = (Instruction::Store == Opcode); 4053 4054 auto *SrcVTy = dyn_cast<FixedVectorType>(SrcTy); 4055 if (!SrcVTy) 4056 // To calculate scalar take the regular cost, without mask 4057 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace, CostKind); 4058 4059 unsigned NumElem = SrcVTy->getNumElements(); 4060 auto *MaskTy = 4061 FixedVectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 4062 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, Alignment)) || 4063 (IsStore && !isLegalMaskedStore(SrcVTy, Alignment))) { 4064 // Scalarization 4065 APInt DemandedElts = APInt::getAllOnes(NumElem); 4066 InstructionCost MaskSplitCost = 4067 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 4068 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 4069 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr, 4070 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4071 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 4072 InstructionCost MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 4073 InstructionCost ValueSplitCost = 4074 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore); 4075 InstructionCost MemopCost = 4076 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4077 Alignment, AddressSpace, CostKind); 4078 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 4079 } 4080 4081 // Legalize the type. 4082 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 4083 auto VT = TLI->getValueType(DL, SrcVTy); 4084 InstructionCost Cost = 0; 4085 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 4086 LT.second.getVectorNumElements() == NumElem) 4087 // Promotion requires extend/truncate for data and a shuffle for mask. 4088 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, None, 0, nullptr) + 4089 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, None, 0, nullptr); 4090 4091 else if (LT.first * LT.second.getVectorNumElements() > NumElem) { 4092 auto *NewMaskTy = FixedVectorType::get(MaskTy->getElementType(), 4093 LT.second.getVectorNumElements()); 4094 // Expanding requires fill mask with zeroes 4095 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, None, 0, MaskTy); 4096 } 4097 4098 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 4099 if (!ST->hasAVX512()) 4100 return Cost + LT.first * (IsLoad ? 2 : 8); 4101 4102 // AVX-512 masked load/store is cheapper 4103 return Cost + LT.first; 4104 } 4105 4106 InstructionCost X86TTIImpl::getAddressComputationCost(Type *Ty, 4107 ScalarEvolution *SE, 4108 const SCEV *Ptr) { 4109 // Address computations in vectorized code with non-consecutive addresses will 4110 // likely result in more instructions compared to scalar code where the 4111 // computation can more often be merged into the index mode. The resulting 4112 // extra micro-ops can significantly decrease throughput. 4113 const unsigned NumVectorInstToHideOverhead = 10; 4114 4115 // Cost modeling of Strided Access Computation is hidden by the indexing 4116 // modes of X86 regardless of the stride value. We dont believe that there 4117 // is a difference between constant strided access in gerenal and constant 4118 // strided value which is less than or equal to 64. 4119 // Even in the case of (loop invariant) stride whose value is not known at 4120 // compile time, the address computation will not incur more than one extra 4121 // ADD instruction. 4122 if (Ty->isVectorTy() && SE && !ST->hasAVX2()) { 4123 // TODO: AVX2 is the current cut-off because we don't have correct 4124 // interleaving costs for prior ISA's. 4125 if (!BaseT::isStridedAccess(Ptr)) 4126 return NumVectorInstToHideOverhead; 4127 if (!BaseT::getConstantStrideStep(SE, Ptr)) 4128 return 1; 4129 } 4130 4131 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 4132 } 4133 4134 InstructionCost 4135 X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 4136 Optional<FastMathFlags> FMF, 4137 TTI::TargetCostKind CostKind) { 4138 if (TTI::requiresOrderedReduction(FMF)) 4139 return BaseT::getArithmeticReductionCost(Opcode, ValTy, FMF, CostKind); 4140 4141 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 4142 // and make it as the cost. 4143 4144 static const CostTblEntry SLMCostTblNoPairWise[] = { 4145 { ISD::FADD, MVT::v2f64, 3 }, 4146 { ISD::ADD, MVT::v2i64, 5 }, 4147 }; 4148 4149 static const CostTblEntry SSE2CostTblNoPairWise[] = { 4150 { ISD::FADD, MVT::v2f64, 2 }, 4151 { ISD::FADD, MVT::v2f32, 2 }, 4152 { ISD::FADD, MVT::v4f32, 4 }, 4153 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 4154 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 4155 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 4156 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 4157 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 4158 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 4159 { ISD::ADD, MVT::v2i8, 2 }, 4160 { ISD::ADD, MVT::v4i8, 2 }, 4161 { ISD::ADD, MVT::v8i8, 2 }, 4162 { ISD::ADD, MVT::v16i8, 3 }, 4163 }; 4164 4165 static const CostTblEntry AVX1CostTblNoPairWise[] = { 4166 { ISD::FADD, MVT::v4f64, 3 }, 4167 { ISD::FADD, MVT::v4f32, 3 }, 4168 { ISD::FADD, MVT::v8f32, 4 }, 4169 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 4170 { ISD::ADD, MVT::v4i64, 3 }, 4171 { ISD::ADD, MVT::v8i32, 5 }, 4172 { ISD::ADD, MVT::v16i16, 5 }, 4173 { ISD::ADD, MVT::v32i8, 4 }, 4174 }; 4175 4176 int ISD = TLI->InstructionOpcodeToISD(Opcode); 4177 assert(ISD && "Invalid opcode"); 4178 4179 // Before legalizing the type, give a chance to look up illegal narrow types 4180 // in the table. 4181 // FIXME: Is there a better way to do this? 4182 EVT VT = TLI->getValueType(DL, ValTy); 4183 if (VT.isSimple()) { 4184 MVT MTy = VT.getSimpleVT(); 4185 if (ST->useSLMArithCosts()) 4186 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 4187 return Entry->Cost; 4188 4189 if (ST->hasAVX()) 4190 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4191 return Entry->Cost; 4192 4193 if (ST->hasSSE2()) 4194 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4195 return Entry->Cost; 4196 } 4197 4198 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 4199 4200 MVT MTy = LT.second; 4201 4202 auto *ValVTy = cast<FixedVectorType>(ValTy); 4203 4204 // Special case: vXi8 mul reductions are performed as vXi16. 4205 if (ISD == ISD::MUL && MTy.getScalarType() == MVT::i8) { 4206 auto *WideSclTy = IntegerType::get(ValVTy->getContext(), 16); 4207 auto *WideVecTy = FixedVectorType::get(WideSclTy, ValVTy->getNumElements()); 4208 return getCastInstrCost(Instruction::ZExt, WideVecTy, ValTy, 4209 TargetTransformInfo::CastContextHint::None, 4210 CostKind) + 4211 getArithmeticReductionCost(Opcode, WideVecTy, FMF, CostKind); 4212 } 4213 4214 InstructionCost ArithmeticCost = 0; 4215 if (LT.first != 1 && MTy.isVector() && 4216 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4217 // Type needs to be split. We need LT.first - 1 arithmetic ops. 4218 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 4219 MTy.getVectorNumElements()); 4220 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 4221 ArithmeticCost *= LT.first - 1; 4222 } 4223 4224 if (ST->useSLMArithCosts()) 4225 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 4226 return ArithmeticCost + Entry->Cost; 4227 4228 if (ST->hasAVX()) 4229 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4230 return ArithmeticCost + Entry->Cost; 4231 4232 if (ST->hasSSE2()) 4233 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4234 return ArithmeticCost + Entry->Cost; 4235 4236 // FIXME: These assume a naive kshift+binop lowering, which is probably 4237 // conservative in most cases. 4238 static const CostTblEntry AVX512BoolReduction[] = { 4239 { ISD::AND, MVT::v2i1, 3 }, 4240 { ISD::AND, MVT::v4i1, 5 }, 4241 { ISD::AND, MVT::v8i1, 7 }, 4242 { ISD::AND, MVT::v16i1, 9 }, 4243 { ISD::AND, MVT::v32i1, 11 }, 4244 { ISD::AND, MVT::v64i1, 13 }, 4245 { ISD::OR, MVT::v2i1, 3 }, 4246 { ISD::OR, MVT::v4i1, 5 }, 4247 { ISD::OR, MVT::v8i1, 7 }, 4248 { ISD::OR, MVT::v16i1, 9 }, 4249 { ISD::OR, MVT::v32i1, 11 }, 4250 { ISD::OR, MVT::v64i1, 13 }, 4251 }; 4252 4253 static const CostTblEntry AVX2BoolReduction[] = { 4254 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 4255 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 4256 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 4257 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 4258 }; 4259 4260 static const CostTblEntry AVX1BoolReduction[] = { 4261 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 4262 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 4263 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 4264 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 4265 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 4266 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 4267 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 4268 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 4269 }; 4270 4271 static const CostTblEntry SSE2BoolReduction[] = { 4272 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 4273 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 4274 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 4275 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 4276 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 4277 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 4278 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 4279 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 4280 }; 4281 4282 // Handle bool allof/anyof patterns. 4283 if (ValVTy->getElementType()->isIntegerTy(1)) { 4284 InstructionCost ArithmeticCost = 0; 4285 if (LT.first != 1 && MTy.isVector() && 4286 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4287 // Type needs to be split. We need LT.first - 1 arithmetic ops. 4288 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 4289 MTy.getVectorNumElements()); 4290 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 4291 ArithmeticCost *= LT.first - 1; 4292 } 4293 4294 if (ST->hasAVX512()) 4295 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 4296 return ArithmeticCost + Entry->Cost; 4297 if (ST->hasAVX2()) 4298 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 4299 return ArithmeticCost + Entry->Cost; 4300 if (ST->hasAVX()) 4301 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 4302 return ArithmeticCost + Entry->Cost; 4303 if (ST->hasSSE2()) 4304 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 4305 return ArithmeticCost + Entry->Cost; 4306 4307 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, FMF, CostKind); 4308 } 4309 4310 unsigned NumVecElts = ValVTy->getNumElements(); 4311 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 4312 4313 // Special case power of 2 reductions where the scalar type isn't changed 4314 // by type legalization. 4315 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 4316 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, FMF, CostKind); 4317 4318 InstructionCost ReductionCost = 0; 4319 4320 auto *Ty = ValVTy; 4321 if (LT.first != 1 && MTy.isVector() && 4322 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4323 // Type needs to be split. We need LT.first - 1 arithmetic ops. 4324 Ty = FixedVectorType::get(ValVTy->getElementType(), 4325 MTy.getVectorNumElements()); 4326 ReductionCost = getArithmeticInstrCost(Opcode, Ty, CostKind); 4327 ReductionCost *= LT.first - 1; 4328 NumVecElts = MTy.getVectorNumElements(); 4329 } 4330 4331 // Now handle reduction with the legal type, taking into account size changes 4332 // at each level. 4333 while (NumVecElts > 1) { 4334 // Determine the size of the remaining vector we need to reduce. 4335 unsigned Size = NumVecElts * ScalarSize; 4336 NumVecElts /= 2; 4337 // If we're reducing from 256/512 bits, use an extract_subvector. 4338 if (Size > 128) { 4339 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 4340 ReductionCost += 4341 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 4342 Ty = SubTy; 4343 } else if (Size == 128) { 4344 // Reducing from 128 bits is a permute of v2f64/v2i64. 4345 FixedVectorType *ShufTy; 4346 if (ValVTy->isFloatingPointTy()) 4347 ShufTy = 4348 FixedVectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 4349 else 4350 ShufTy = 4351 FixedVectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 4352 ReductionCost += 4353 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4354 } else if (Size == 64) { 4355 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 4356 FixedVectorType *ShufTy; 4357 if (ValVTy->isFloatingPointTy()) 4358 ShufTy = 4359 FixedVectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 4360 else 4361 ShufTy = 4362 FixedVectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 4363 ReductionCost += 4364 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4365 } else { 4366 // Reducing from smaller size is a shift by immediate. 4367 auto *ShiftTy = FixedVectorType::get( 4368 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 4369 ReductionCost += getArithmeticInstrCost( 4370 Instruction::LShr, ShiftTy, CostKind, 4371 TargetTransformInfo::OK_AnyValue, 4372 TargetTransformInfo::OK_UniformConstantValue, 4373 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 4374 } 4375 4376 // Add the arithmetic op for this level. 4377 ReductionCost += getArithmeticInstrCost(Opcode, Ty, CostKind); 4378 } 4379 4380 // Add the final extract element to the cost. 4381 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 4382 } 4383 4384 InstructionCost X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, 4385 bool IsUnsigned) { 4386 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 4387 4388 MVT MTy = LT.second; 4389 4390 int ISD; 4391 if (Ty->isIntOrIntVectorTy()) { 4392 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 4393 } else { 4394 assert(Ty->isFPOrFPVectorTy() && 4395 "Expected float point or integer vector type."); 4396 ISD = ISD::FMINNUM; 4397 } 4398 4399 static const CostTblEntry SSE1CostTbl[] = { 4400 {ISD::FMINNUM, MVT::v4f32, 1}, 4401 }; 4402 4403 static const CostTblEntry SSE2CostTbl[] = { 4404 {ISD::FMINNUM, MVT::v2f64, 1}, 4405 {ISD::SMIN, MVT::v8i16, 1}, 4406 {ISD::UMIN, MVT::v16i8, 1}, 4407 }; 4408 4409 static const CostTblEntry SSE41CostTbl[] = { 4410 {ISD::SMIN, MVT::v4i32, 1}, 4411 {ISD::UMIN, MVT::v4i32, 1}, 4412 {ISD::UMIN, MVT::v8i16, 1}, 4413 {ISD::SMIN, MVT::v16i8, 1}, 4414 }; 4415 4416 static const CostTblEntry SSE42CostTbl[] = { 4417 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 4418 }; 4419 4420 static const CostTblEntry AVX1CostTbl[] = { 4421 {ISD::FMINNUM, MVT::v8f32, 1}, 4422 {ISD::FMINNUM, MVT::v4f64, 1}, 4423 {ISD::SMIN, MVT::v8i32, 3}, 4424 {ISD::UMIN, MVT::v8i32, 3}, 4425 {ISD::SMIN, MVT::v16i16, 3}, 4426 {ISD::UMIN, MVT::v16i16, 3}, 4427 {ISD::SMIN, MVT::v32i8, 3}, 4428 {ISD::UMIN, MVT::v32i8, 3}, 4429 }; 4430 4431 static const CostTblEntry AVX2CostTbl[] = { 4432 {ISD::SMIN, MVT::v8i32, 1}, 4433 {ISD::UMIN, MVT::v8i32, 1}, 4434 {ISD::SMIN, MVT::v16i16, 1}, 4435 {ISD::UMIN, MVT::v16i16, 1}, 4436 {ISD::SMIN, MVT::v32i8, 1}, 4437 {ISD::UMIN, MVT::v32i8, 1}, 4438 }; 4439 4440 static const CostTblEntry AVX512CostTbl[] = { 4441 {ISD::FMINNUM, MVT::v16f32, 1}, 4442 {ISD::FMINNUM, MVT::v8f64, 1}, 4443 {ISD::SMIN, MVT::v2i64, 1}, 4444 {ISD::UMIN, MVT::v2i64, 1}, 4445 {ISD::SMIN, MVT::v4i64, 1}, 4446 {ISD::UMIN, MVT::v4i64, 1}, 4447 {ISD::SMIN, MVT::v8i64, 1}, 4448 {ISD::UMIN, MVT::v8i64, 1}, 4449 {ISD::SMIN, MVT::v16i32, 1}, 4450 {ISD::UMIN, MVT::v16i32, 1}, 4451 }; 4452 4453 static const CostTblEntry AVX512BWCostTbl[] = { 4454 {ISD::SMIN, MVT::v32i16, 1}, 4455 {ISD::UMIN, MVT::v32i16, 1}, 4456 {ISD::SMIN, MVT::v64i8, 1}, 4457 {ISD::UMIN, MVT::v64i8, 1}, 4458 }; 4459 4460 // If we have a native MIN/MAX instruction for this type, use it. 4461 if (ST->hasBWI()) 4462 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 4463 return LT.first * Entry->Cost; 4464 4465 if (ST->hasAVX512()) 4466 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 4467 return LT.first * Entry->Cost; 4468 4469 if (ST->hasAVX2()) 4470 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 4471 return LT.first * Entry->Cost; 4472 4473 if (ST->hasAVX()) 4474 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 4475 return LT.first * Entry->Cost; 4476 4477 if (ST->hasSSE42()) 4478 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 4479 return LT.first * Entry->Cost; 4480 4481 if (ST->hasSSE41()) 4482 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 4483 return LT.first * Entry->Cost; 4484 4485 if (ST->hasSSE2()) 4486 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 4487 return LT.first * Entry->Cost; 4488 4489 if (ST->hasSSE1()) 4490 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 4491 return LT.first * Entry->Cost; 4492 4493 unsigned CmpOpcode; 4494 if (Ty->isFPOrFPVectorTy()) { 4495 CmpOpcode = Instruction::FCmp; 4496 } else { 4497 assert(Ty->isIntOrIntVectorTy() && 4498 "expecting floating point or integer type for min/max reduction"); 4499 CmpOpcode = Instruction::ICmp; 4500 } 4501 4502 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4503 // Otherwise fall back to cmp+select. 4504 InstructionCost Result = 4505 getCmpSelInstrCost(CmpOpcode, Ty, CondTy, CmpInst::BAD_ICMP_PREDICATE, 4506 CostKind) + 4507 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, 4508 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4509 return Result; 4510 } 4511 4512 InstructionCost 4513 X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 4514 bool IsUnsigned, 4515 TTI::TargetCostKind CostKind) { 4516 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 4517 4518 MVT MTy = LT.second; 4519 4520 int ISD; 4521 if (ValTy->isIntOrIntVectorTy()) { 4522 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 4523 } else { 4524 assert(ValTy->isFPOrFPVectorTy() && 4525 "Expected float point or integer vector type."); 4526 ISD = ISD::FMINNUM; 4527 } 4528 4529 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 4530 // and make it as the cost. 4531 4532 static const CostTblEntry SSE2CostTblNoPairWise[] = { 4533 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 4534 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 4535 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 4536 }; 4537 4538 static const CostTblEntry SSE41CostTblNoPairWise[] = { 4539 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 4540 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 4541 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 4542 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 4543 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 4544 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 4545 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 4546 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 4547 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 4548 {ISD::SMIN, MVT::v16i8, 6}, 4549 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 4550 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 4551 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 4552 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 4553 }; 4554 4555 static const CostTblEntry AVX1CostTblNoPairWise[] = { 4556 {ISD::SMIN, MVT::v16i16, 6}, 4557 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 4558 {ISD::SMIN, MVT::v32i8, 8}, 4559 {ISD::UMIN, MVT::v32i8, 8}, 4560 }; 4561 4562 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 4563 {ISD::SMIN, MVT::v32i16, 8}, 4564 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 4565 {ISD::SMIN, MVT::v64i8, 10}, 4566 {ISD::UMIN, MVT::v64i8, 10}, 4567 }; 4568 4569 // Before legalizing the type, give a chance to look up illegal narrow types 4570 // in the table. 4571 // FIXME: Is there a better way to do this? 4572 EVT VT = TLI->getValueType(DL, ValTy); 4573 if (VT.isSimple()) { 4574 MVT MTy = VT.getSimpleVT(); 4575 if (ST->hasBWI()) 4576 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4577 return Entry->Cost; 4578 4579 if (ST->hasAVX()) 4580 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4581 return Entry->Cost; 4582 4583 if (ST->hasSSE41()) 4584 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4585 return Entry->Cost; 4586 4587 if (ST->hasSSE2()) 4588 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4589 return Entry->Cost; 4590 } 4591 4592 auto *ValVTy = cast<FixedVectorType>(ValTy); 4593 unsigned NumVecElts = ValVTy->getNumElements(); 4594 4595 auto *Ty = ValVTy; 4596 InstructionCost MinMaxCost = 0; 4597 if (LT.first != 1 && MTy.isVector() && 4598 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4599 // Type needs to be split. We need LT.first - 1 operations ops. 4600 Ty = FixedVectorType::get(ValVTy->getElementType(), 4601 MTy.getVectorNumElements()); 4602 auto *SubCondTy = FixedVectorType::get(CondTy->getElementType(), 4603 MTy.getVectorNumElements()); 4604 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4605 MinMaxCost *= LT.first - 1; 4606 NumVecElts = MTy.getVectorNumElements(); 4607 } 4608 4609 if (ST->hasBWI()) 4610 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4611 return MinMaxCost + Entry->Cost; 4612 4613 if (ST->hasAVX()) 4614 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4615 return MinMaxCost + Entry->Cost; 4616 4617 if (ST->hasSSE41()) 4618 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4619 return MinMaxCost + Entry->Cost; 4620 4621 if (ST->hasSSE2()) 4622 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4623 return MinMaxCost + Entry->Cost; 4624 4625 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 4626 4627 // Special case power of 2 reductions where the scalar type isn't changed 4628 // by type legalization. 4629 if (!isPowerOf2_32(ValVTy->getNumElements()) || 4630 ScalarSize != MTy.getScalarSizeInBits()) 4631 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsUnsigned, CostKind); 4632 4633 // Now handle reduction with the legal type, taking into account size changes 4634 // at each level. 4635 while (NumVecElts > 1) { 4636 // Determine the size of the remaining vector we need to reduce. 4637 unsigned Size = NumVecElts * ScalarSize; 4638 NumVecElts /= 2; 4639 // If we're reducing from 256/512 bits, use an extract_subvector. 4640 if (Size > 128) { 4641 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 4642 MinMaxCost += 4643 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 4644 Ty = SubTy; 4645 } else if (Size == 128) { 4646 // Reducing from 128 bits is a permute of v2f64/v2i64. 4647 VectorType *ShufTy; 4648 if (ValTy->isFloatingPointTy()) 4649 ShufTy = 4650 FixedVectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 4651 else 4652 ShufTy = FixedVectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 4653 MinMaxCost += 4654 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4655 } else if (Size == 64) { 4656 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 4657 FixedVectorType *ShufTy; 4658 if (ValTy->isFloatingPointTy()) 4659 ShufTy = FixedVectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 4660 else 4661 ShufTy = FixedVectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 4662 MinMaxCost += 4663 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4664 } else { 4665 // Reducing from smaller size is a shift by immediate. 4666 auto *ShiftTy = FixedVectorType::get( 4667 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 4668 MinMaxCost += getArithmeticInstrCost( 4669 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, 4670 TargetTransformInfo::OK_AnyValue, 4671 TargetTransformInfo::OK_UniformConstantValue, 4672 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 4673 } 4674 4675 // Add the arithmetic op for this level. 4676 auto *SubCondTy = 4677 FixedVectorType::get(CondTy->getElementType(), Ty->getNumElements()); 4678 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4679 } 4680 4681 // Add the final extract element to the cost. 4682 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 4683 } 4684 4685 /// Calculate the cost of materializing a 64-bit value. This helper 4686 /// method might only calculate a fraction of a larger immediate. Therefore it 4687 /// is valid to return a cost of ZERO. 4688 InstructionCost X86TTIImpl::getIntImmCost(int64_t Val) { 4689 if (Val == 0) 4690 return TTI::TCC_Free; 4691 4692 if (isInt<32>(Val)) 4693 return TTI::TCC_Basic; 4694 4695 return 2 * TTI::TCC_Basic; 4696 } 4697 4698 InstructionCost X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 4699 TTI::TargetCostKind CostKind) { 4700 assert(Ty->isIntegerTy()); 4701 4702 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4703 if (BitSize == 0) 4704 return ~0U; 4705 4706 // Never hoist constants larger than 128bit, because this might lead to 4707 // incorrect code generation or assertions in codegen. 4708 // Fixme: Create a cost model for types larger than i128 once the codegen 4709 // issues have been fixed. 4710 if (BitSize > 128) 4711 return TTI::TCC_Free; 4712 4713 if (Imm == 0) 4714 return TTI::TCC_Free; 4715 4716 // Sign-extend all constants to a multiple of 64-bit. 4717 APInt ImmVal = Imm; 4718 if (BitSize % 64 != 0) 4719 ImmVal = Imm.sext(alignTo(BitSize, 64)); 4720 4721 // Split the constant into 64-bit chunks and calculate the cost for each 4722 // chunk. 4723 InstructionCost Cost = 0; 4724 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 4725 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 4726 int64_t Val = Tmp.getSExtValue(); 4727 Cost += getIntImmCost(Val); 4728 } 4729 // We need at least one instruction to materialize the constant. 4730 return std::max<InstructionCost>(1, Cost); 4731 } 4732 4733 InstructionCost X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, 4734 const APInt &Imm, Type *Ty, 4735 TTI::TargetCostKind CostKind, 4736 Instruction *Inst) { 4737 assert(Ty->isIntegerTy()); 4738 4739 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4740 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4741 // here, so that constant hoisting will ignore this constant. 4742 if (BitSize == 0) 4743 return TTI::TCC_Free; 4744 4745 unsigned ImmIdx = ~0U; 4746 switch (Opcode) { 4747 default: 4748 return TTI::TCC_Free; 4749 case Instruction::GetElementPtr: 4750 // Always hoist the base address of a GetElementPtr. This prevents the 4751 // creation of new constants for every base constant that gets constant 4752 // folded with the offset. 4753 if (Idx == 0) 4754 return 2 * TTI::TCC_Basic; 4755 return TTI::TCC_Free; 4756 case Instruction::Store: 4757 ImmIdx = 0; 4758 break; 4759 case Instruction::ICmp: 4760 // This is an imperfect hack to prevent constant hoisting of 4761 // compares that might be trying to check if a 64-bit value fits in 4762 // 32-bits. The backend can optimize these cases using a right shift by 32. 4763 // Ideally we would check the compare predicate here. There also other 4764 // similar immediates the backend can use shifts for. 4765 if (Idx == 1 && Imm.getBitWidth() == 64) { 4766 uint64_t ImmVal = Imm.getZExtValue(); 4767 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 4768 return TTI::TCC_Free; 4769 } 4770 ImmIdx = 1; 4771 break; 4772 case Instruction::And: 4773 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 4774 // by using a 32-bit operation with implicit zero extension. Detect such 4775 // immediates here as the normal path expects bit 31 to be sign extended. 4776 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 4777 return TTI::TCC_Free; 4778 ImmIdx = 1; 4779 break; 4780 case Instruction::Add: 4781 case Instruction::Sub: 4782 // For add/sub, we can use the opposite instruction for INT32_MIN. 4783 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 4784 return TTI::TCC_Free; 4785 ImmIdx = 1; 4786 break; 4787 case Instruction::UDiv: 4788 case Instruction::SDiv: 4789 case Instruction::URem: 4790 case Instruction::SRem: 4791 // Division by constant is typically expanded later into a different 4792 // instruction sequence. This completely changes the constants. 4793 // Report them as "free" to stop ConstantHoist from marking them as opaque. 4794 return TTI::TCC_Free; 4795 case Instruction::Mul: 4796 case Instruction::Or: 4797 case Instruction::Xor: 4798 ImmIdx = 1; 4799 break; 4800 // Always return TCC_Free for the shift value of a shift instruction. 4801 case Instruction::Shl: 4802 case Instruction::LShr: 4803 case Instruction::AShr: 4804 if (Idx == 1) 4805 return TTI::TCC_Free; 4806 break; 4807 case Instruction::Trunc: 4808 case Instruction::ZExt: 4809 case Instruction::SExt: 4810 case Instruction::IntToPtr: 4811 case Instruction::PtrToInt: 4812 case Instruction::BitCast: 4813 case Instruction::PHI: 4814 case Instruction::Call: 4815 case Instruction::Select: 4816 case Instruction::Ret: 4817 case Instruction::Load: 4818 break; 4819 } 4820 4821 if (Idx == ImmIdx) { 4822 int NumConstants = divideCeil(BitSize, 64); 4823 InstructionCost Cost = X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4824 return (Cost <= NumConstants * TTI::TCC_Basic) 4825 ? static_cast<int>(TTI::TCC_Free) 4826 : Cost; 4827 } 4828 4829 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4830 } 4831 4832 InstructionCost X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 4833 const APInt &Imm, Type *Ty, 4834 TTI::TargetCostKind CostKind) { 4835 assert(Ty->isIntegerTy()); 4836 4837 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4838 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4839 // here, so that constant hoisting will ignore this constant. 4840 if (BitSize == 0) 4841 return TTI::TCC_Free; 4842 4843 switch (IID) { 4844 default: 4845 return TTI::TCC_Free; 4846 case Intrinsic::sadd_with_overflow: 4847 case Intrinsic::uadd_with_overflow: 4848 case Intrinsic::ssub_with_overflow: 4849 case Intrinsic::usub_with_overflow: 4850 case Intrinsic::smul_with_overflow: 4851 case Intrinsic::umul_with_overflow: 4852 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 4853 return TTI::TCC_Free; 4854 break; 4855 case Intrinsic::experimental_stackmap: 4856 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4857 return TTI::TCC_Free; 4858 break; 4859 case Intrinsic::experimental_patchpoint_void: 4860 case Intrinsic::experimental_patchpoint_i64: 4861 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4862 return TTI::TCC_Free; 4863 break; 4864 } 4865 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4866 } 4867 4868 InstructionCost X86TTIImpl::getCFInstrCost(unsigned Opcode, 4869 TTI::TargetCostKind CostKind, 4870 const Instruction *I) { 4871 if (CostKind != TTI::TCK_RecipThroughput) 4872 return Opcode == Instruction::PHI ? 0 : 1; 4873 // Branches are assumed to be predicted. 4874 return 0; 4875 } 4876 4877 int X86TTIImpl::getGatherOverhead() const { 4878 // Some CPUs have more overhead for gather. The specified overhead is relative 4879 // to the Load operation. "2" is the number provided by Intel architects. This 4880 // parameter is used for cost estimation of Gather Op and comparison with 4881 // other alternatives. 4882 // TODO: Remove the explicit hasAVX512()?, That would mean we would only 4883 // enable gather with a -march. 4884 if (ST->hasAVX512() || (ST->hasAVX2() && ST->hasFastGather())) 4885 return 2; 4886 4887 return 1024; 4888 } 4889 4890 int X86TTIImpl::getScatterOverhead() const { 4891 if (ST->hasAVX512()) 4892 return 2; 4893 4894 return 1024; 4895 } 4896 4897 // Return an average cost of Gather / Scatter instruction, maybe improved later. 4898 // FIXME: Add TargetCostKind support. 4899 InstructionCost X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, 4900 const Value *Ptr, Align Alignment, 4901 unsigned AddressSpace) { 4902 4903 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 4904 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4905 4906 // Try to reduce index size from 64 bit (default for GEP) 4907 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 4908 // operation will use 16 x 64 indices which do not fit in a zmm and needs 4909 // to split. Also check that the base pointer is the same for all lanes, 4910 // and that there's at most one variable index. 4911 auto getIndexSizeInBits = [](const Value *Ptr, const DataLayout &DL) { 4912 unsigned IndexSize = DL.getPointerSizeInBits(); 4913 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 4914 if (IndexSize < 64 || !GEP) 4915 return IndexSize; 4916 4917 unsigned NumOfVarIndices = 0; 4918 const Value *Ptrs = GEP->getPointerOperand(); 4919 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 4920 return IndexSize; 4921 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 4922 if (isa<Constant>(GEP->getOperand(i))) 4923 continue; 4924 Type *IndxTy = GEP->getOperand(i)->getType(); 4925 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 4926 IndxTy = IndexVTy->getElementType(); 4927 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 4928 !isa<SExtInst>(GEP->getOperand(i))) || 4929 ++NumOfVarIndices > 1) 4930 return IndexSize; // 64 4931 } 4932 return (unsigned)32; 4933 }; 4934 4935 // Trying to reduce IndexSize to 32 bits for vector 16. 4936 // By default the IndexSize is equal to pointer size. 4937 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 4938 ? getIndexSizeInBits(Ptr, DL) 4939 : DL.getPointerSizeInBits(); 4940 4941 auto *IndexVTy = FixedVectorType::get( 4942 IntegerType::get(SrcVTy->getContext(), IndexSize), VF); 4943 std::pair<InstructionCost, MVT> IdxsLT = 4944 TLI->getTypeLegalizationCost(DL, IndexVTy); 4945 std::pair<InstructionCost, MVT> SrcLT = 4946 TLI->getTypeLegalizationCost(DL, SrcVTy); 4947 InstructionCost::CostType SplitFactor = 4948 *std::max(IdxsLT.first, SrcLT.first).getValue(); 4949 if (SplitFactor > 1) { 4950 // Handle splitting of vector of pointers 4951 auto *SplitSrcTy = 4952 FixedVectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 4953 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 4954 AddressSpace); 4955 } 4956 4957 // The gather / scatter cost is given by Intel architects. It is a rough 4958 // number since we are looking at one instruction in a time. 4959 const int GSOverhead = (Opcode == Instruction::Load) 4960 ? getGatherOverhead() 4961 : getScatterOverhead(); 4962 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4963 MaybeAlign(Alignment), AddressSpace, 4964 TTI::TCK_RecipThroughput); 4965 } 4966 4967 /// Return the cost of full scalarization of gather / scatter operation. 4968 /// 4969 /// Opcode - Load or Store instruction. 4970 /// SrcVTy - The type of the data vector that should be gathered or scattered. 4971 /// VariableMask - The mask is non-constant at compile time. 4972 /// Alignment - Alignment for one element. 4973 /// AddressSpace - pointer[s] address space. 4974 /// 4975 /// FIXME: Add TargetCostKind support. 4976 InstructionCost X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 4977 bool VariableMask, Align Alignment, 4978 unsigned AddressSpace) { 4979 Type *ScalarTy = SrcVTy->getScalarType(); 4980 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4981 APInt DemandedElts = APInt::getAllOnes(VF); 4982 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4983 4984 InstructionCost MaskUnpackCost = 0; 4985 if (VariableMask) { 4986 auto *MaskTy = 4987 FixedVectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 4988 MaskUnpackCost = getScalarizationOverhead( 4989 MaskTy, DemandedElts, /*Insert=*/false, /*Extract=*/true); 4990 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 4991 Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), nullptr, 4992 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4993 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 4994 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 4995 } 4996 4997 InstructionCost AddressUnpackCost = getScalarizationOverhead( 4998 FixedVectorType::get(ScalarTy->getPointerTo(), VF), DemandedElts, 4999 /*Insert=*/false, /*Extract=*/true); 5000 5001 // The cost of the scalar loads/stores. 5002 InstructionCost MemoryOpCost = 5003 VF * getMemoryOpCost(Opcode, ScalarTy, MaybeAlign(Alignment), 5004 AddressSpace, CostKind); 5005 5006 // The cost of forming the vector from loaded scalars/ 5007 // scalarizing the vector to perform scalar stores. 5008 InstructionCost InsertExtractCost = 5009 getScalarizationOverhead(cast<FixedVectorType>(SrcVTy), DemandedElts, 5010 /*Insert=*/Opcode == Instruction::Load, 5011 /*Extract=*/Opcode == Instruction::Store); 5012 5013 return AddressUnpackCost + MemoryOpCost + MaskUnpackCost + InsertExtractCost; 5014 } 5015 5016 /// Calculate the cost of Gather / Scatter operation 5017 InstructionCost X86TTIImpl::getGatherScatterOpCost( 5018 unsigned Opcode, Type *SrcVTy, const Value *Ptr, bool VariableMask, 5019 Align Alignment, TTI::TargetCostKind CostKind, 5020 const Instruction *I = nullptr) { 5021 if (CostKind != TTI::TCK_RecipThroughput) { 5022 if ((Opcode == Instruction::Load && 5023 isLegalMaskedGather(SrcVTy, Align(Alignment)) && 5024 !forceScalarizeMaskedGather(cast<VectorType>(SrcVTy), 5025 Align(Alignment))) || 5026 (Opcode == Instruction::Store && 5027 isLegalMaskedScatter(SrcVTy, Align(Alignment)) && 5028 !forceScalarizeMaskedScatter(cast<VectorType>(SrcVTy), 5029 Align(Alignment)))) 5030 return 1; 5031 return BaseT::getGatherScatterOpCost(Opcode, SrcVTy, Ptr, VariableMask, 5032 Alignment, CostKind, I); 5033 } 5034 5035 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 5036 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 5037 if (!PtrTy && Ptr->getType()->isVectorTy()) 5038 PtrTy = dyn_cast<PointerType>( 5039 cast<VectorType>(Ptr->getType())->getElementType()); 5040 assert(PtrTy && "Unexpected type for Ptr argument"); 5041 unsigned AddressSpace = PtrTy->getAddressSpace(); 5042 5043 if ((Opcode == Instruction::Load && 5044 (!isLegalMaskedGather(SrcVTy, Align(Alignment)) || 5045 forceScalarizeMaskedGather(cast<VectorType>(SrcVTy), 5046 Align(Alignment)))) || 5047 (Opcode == Instruction::Store && 5048 (!isLegalMaskedScatter(SrcVTy, Align(Alignment)) || 5049 forceScalarizeMaskedScatter(cast<VectorType>(SrcVTy), 5050 Align(Alignment))))) 5051 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 5052 AddressSpace); 5053 5054 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 5055 } 5056 5057 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 5058 TargetTransformInfo::LSRCost &C2) { 5059 // X86 specific here are "instruction number 1st priority". 5060 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 5061 C1.NumIVMuls, C1.NumBaseAdds, 5062 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 5063 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 5064 C2.NumIVMuls, C2.NumBaseAdds, 5065 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 5066 } 5067 5068 bool X86TTIImpl::canMacroFuseCmp() { 5069 return ST->hasMacroFusion() || ST->hasBranchFusion(); 5070 } 5071 5072 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, Align Alignment) { 5073 if (!ST->hasAVX()) 5074 return false; 5075 5076 // The backend can't handle a single element vector. 5077 if (isa<VectorType>(DataTy) && 5078 cast<FixedVectorType>(DataTy)->getNumElements() == 1) 5079 return false; 5080 Type *ScalarTy = DataTy->getScalarType(); 5081 5082 if (ScalarTy->isPointerTy()) 5083 return true; 5084 5085 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 5086 return true; 5087 5088 if (ScalarTy->isHalfTy() && ST->hasBWI() && ST->hasFP16()) 5089 return true; 5090 5091 if (!ScalarTy->isIntegerTy()) 5092 return false; 5093 5094 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 5095 return IntWidth == 32 || IntWidth == 64 || 5096 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 5097 } 5098 5099 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, Align Alignment) { 5100 return isLegalMaskedLoad(DataType, Alignment); 5101 } 5102 5103 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 5104 unsigned DataSize = DL.getTypeStoreSize(DataType); 5105 // The only supported nontemporal loads are for aligned vectors of 16 or 32 5106 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 5107 // (the equivalent stores only require AVX). 5108 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 5109 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 5110 5111 return false; 5112 } 5113 5114 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 5115 unsigned DataSize = DL.getTypeStoreSize(DataType); 5116 5117 // SSE4A supports nontemporal stores of float and double at arbitrary 5118 // alignment. 5119 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 5120 return true; 5121 5122 // Besides the SSE4A subtarget exception above, only aligned stores are 5123 // available nontemporaly on any other subtarget. And only stores with a size 5124 // of 4..32 bytes (powers of 2, only) are permitted. 5125 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 5126 !isPowerOf2_32(DataSize)) 5127 return false; 5128 5129 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 5130 // loads require AVX2). 5131 if (DataSize == 32) 5132 return ST->hasAVX(); 5133 if (DataSize == 16) 5134 return ST->hasSSE1(); 5135 return true; 5136 } 5137 5138 bool X86TTIImpl::isLegalBroadcastLoad(Type *ElementTy, 5139 ElementCount NumElements) const { 5140 // movddup 5141 return ST->hasSSE3() && !NumElements.isScalable() && 5142 NumElements.getFixedValue() == 2 && 5143 ElementTy == Type::getDoubleTy(ElementTy->getContext()); 5144 } 5145 5146 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 5147 if (!isa<VectorType>(DataTy)) 5148 return false; 5149 5150 if (!ST->hasAVX512()) 5151 return false; 5152 5153 // The backend can't handle a single element vector. 5154 if (cast<FixedVectorType>(DataTy)->getNumElements() == 1) 5155 return false; 5156 5157 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 5158 5159 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 5160 return true; 5161 5162 if (!ScalarTy->isIntegerTy()) 5163 return false; 5164 5165 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 5166 return IntWidth == 32 || IntWidth == 64 || 5167 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 5168 } 5169 5170 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 5171 return isLegalMaskedExpandLoad(DataTy); 5172 } 5173 5174 bool X86TTIImpl::supportsGather() const { 5175 // Some CPUs have better gather performance than others. 5176 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 5177 // enable gather with a -march. 5178 return ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()); 5179 } 5180 5181 bool X86TTIImpl::forceScalarizeMaskedGather(VectorType *VTy, Align Alignment) { 5182 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 5183 // Vector-4 of gather/scatter instruction does not exist on KNL. We can extend 5184 // it to 8 elements, but zeroing upper bits of the mask vector will add more 5185 // instructions. Right now we give the scalar cost of vector-4 for KNL. TODO: 5186 // Check, maybe the gather/scatter instruction is better in the VariableMask 5187 // case. 5188 unsigned NumElts = cast<FixedVectorType>(VTy)->getNumElements(); 5189 return NumElts == 1 || 5190 (ST->hasAVX512() && (NumElts == 2 || (NumElts == 4 && !ST->hasVLX()))); 5191 } 5192 5193 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, Align Alignment) { 5194 if (!supportsGather()) 5195 return false; 5196 Type *ScalarTy = DataTy->getScalarType(); 5197 if (ScalarTy->isPointerTy()) 5198 return true; 5199 5200 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 5201 return true; 5202 5203 if (!ScalarTy->isIntegerTy()) 5204 return false; 5205 5206 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 5207 return IntWidth == 32 || IntWidth == 64; 5208 } 5209 5210 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, Align Alignment) { 5211 // AVX2 doesn't support scatter 5212 if (!ST->hasAVX512()) 5213 return false; 5214 return isLegalMaskedGather(DataType, Alignment); 5215 } 5216 5217 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 5218 EVT VT = TLI->getValueType(DL, DataType); 5219 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 5220 } 5221 5222 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 5223 return false; 5224 } 5225 5226 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 5227 const Function *Callee) const { 5228 const TargetMachine &TM = getTLI()->getTargetMachine(); 5229 5230 // Work this as a subsetting of subtarget features. 5231 const FeatureBitset &CallerBits = 5232 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 5233 const FeatureBitset &CalleeBits = 5234 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 5235 5236 // Check whether features are the same (apart from the ignore list). 5237 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 5238 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 5239 if (RealCallerBits == RealCalleeBits) 5240 return true; 5241 5242 // If the features are a subset, we need to additionally check for calls 5243 // that may become ABI-incompatible as a result of inlining. 5244 if ((RealCallerBits & RealCalleeBits) != RealCalleeBits) 5245 return false; 5246 5247 for (const Instruction &I : instructions(Callee)) { 5248 if (const auto *CB = dyn_cast<CallBase>(&I)) { 5249 SmallVector<Type *, 8> Types; 5250 for (Value *Arg : CB->args()) 5251 Types.push_back(Arg->getType()); 5252 if (!CB->getType()->isVoidTy()) 5253 Types.push_back(CB->getType()); 5254 5255 // Simple types are always ABI compatible. 5256 auto IsSimpleTy = [](Type *Ty) { 5257 return !Ty->isVectorTy() && !Ty->isAggregateType(); 5258 }; 5259 if (all_of(Types, IsSimpleTy)) 5260 continue; 5261 5262 if (Function *NestedCallee = CB->getCalledFunction()) { 5263 // Assume that intrinsics are always ABI compatible. 5264 if (NestedCallee->isIntrinsic()) 5265 continue; 5266 5267 // Do a precise compatibility check. 5268 if (!areTypesABICompatible(Caller, NestedCallee, Types)) 5269 return false; 5270 } else { 5271 // We don't know the target features of the callee, 5272 // assume it is incompatible. 5273 return false; 5274 } 5275 } 5276 } 5277 return true; 5278 } 5279 5280 bool X86TTIImpl::areTypesABICompatible(const Function *Caller, 5281 const Function *Callee, 5282 const ArrayRef<Type *> &Types) const { 5283 if (!BaseT::areTypesABICompatible(Caller, Callee, Types)) 5284 return false; 5285 5286 // If we get here, we know the target features match. If one function 5287 // considers 512-bit vectors legal and the other does not, consider them 5288 // incompatible. 5289 const TargetMachine &TM = getTLI()->getTargetMachine(); 5290 5291 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 5292 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs()) 5293 return true; 5294 5295 // Consider the arguments compatible if they aren't vectors or aggregates. 5296 // FIXME: Look at the size of vectors. 5297 // FIXME: Look at the element types of aggregates to see if there are vectors. 5298 return llvm::none_of(Types, 5299 [](Type *T) { return T->isVectorTy() || T->isAggregateType(); }); 5300 } 5301 5302 X86TTIImpl::TTI::MemCmpExpansionOptions 5303 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 5304 TTI::MemCmpExpansionOptions Options; 5305 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 5306 Options.NumLoadsPerBlock = 2; 5307 // All GPR and vector loads can be unaligned. 5308 Options.AllowOverlappingLoads = true; 5309 if (IsZeroCmp) { 5310 // Only enable vector loads for equality comparison. Right now the vector 5311 // version is not as fast for three way compare (see #33329). 5312 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 5313 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 5314 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 5315 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 5316 } 5317 if (ST->is64Bit()) { 5318 Options.LoadSizes.push_back(8); 5319 } 5320 Options.LoadSizes.push_back(4); 5321 Options.LoadSizes.push_back(2); 5322 Options.LoadSizes.push_back(1); 5323 return Options; 5324 } 5325 5326 bool X86TTIImpl::prefersVectorizedAddressing() const { 5327 return supportsGather(); 5328 } 5329 5330 bool X86TTIImpl::supportsEfficientVectorElementLoadStore() const { 5331 return false; 5332 } 5333 5334 bool X86TTIImpl::enableInterleavedAccessVectorization() { 5335 // TODO: We expect this to be beneficial regardless of arch, 5336 // but there are currently some unexplained performance artifacts on Atom. 5337 // As a temporary solution, disable on Atom. 5338 return !(ST->isAtom()); 5339 } 5340 5341 // Get estimation for interleaved load/store operations and strided load. 5342 // \p Indices contains indices for strided load. 5343 // \p Factor - the factor of interleaving. 5344 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 5345 InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX512( 5346 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 5347 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 5348 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 5349 // VecTy for interleave memop is <VF*Factor x Elt>. 5350 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 5351 // VecTy = <12 x i32>. 5352 5353 // Calculate the number of memory operations (NumOfMemOps), required 5354 // for load/store the VecTy. 5355 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 5356 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 5357 unsigned LegalVTSize = LegalVT.getStoreSize(); 5358 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 5359 5360 // Get the cost of one memory operation. 5361 auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(), 5362 LegalVT.getVectorNumElements()); 5363 InstructionCost MemOpCost; 5364 bool UseMaskedMemOp = UseMaskForCond || UseMaskForGaps; 5365 if (UseMaskedMemOp) 5366 MemOpCost = getMaskedMemoryOpCost(Opcode, SingleMemOpTy, Alignment, 5367 AddressSpace, CostKind); 5368 else 5369 MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, MaybeAlign(Alignment), 5370 AddressSpace, CostKind); 5371 5372 unsigned VF = VecTy->getNumElements() / Factor; 5373 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 5374 5375 InstructionCost MaskCost; 5376 if (UseMaskedMemOp) { 5377 APInt DemandedLoadStoreElts = APInt::getZero(VecTy->getNumElements()); 5378 for (unsigned Index : Indices) { 5379 assert(Index < Factor && "Invalid index for interleaved memory op"); 5380 for (unsigned Elm = 0; Elm < VF; Elm++) 5381 DemandedLoadStoreElts.setBit(Index + Elm * Factor); 5382 } 5383 5384 Type *I1Type = Type::getInt1Ty(VecTy->getContext()); 5385 5386 MaskCost = getReplicationShuffleCost( 5387 I1Type, Factor, VF, 5388 UseMaskForGaps ? DemandedLoadStoreElts 5389 : APInt::getAllOnes(VecTy->getNumElements()), 5390 CostKind); 5391 5392 // The Gaps mask is invariant and created outside the loop, therefore the 5393 // cost of creating it is not accounted for here. However if we have both 5394 // a MaskForGaps and some other mask that guards the execution of the 5395 // memory access, we need to account for the cost of And-ing the two masks 5396 // inside the loop. 5397 if (UseMaskForGaps) { 5398 auto *MaskVT = FixedVectorType::get(I1Type, VecTy->getNumElements()); 5399 MaskCost += getArithmeticInstrCost(BinaryOperator::And, MaskVT, CostKind); 5400 } 5401 } 5402 5403 if (Opcode == Instruction::Load) { 5404 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 5405 // contain the cost of the optimized shuffle sequence that the 5406 // X86InterleavedAccess pass will generate. 5407 // The cost of loads and stores are computed separately from the table. 5408 5409 // X86InterleavedAccess support only the following interleaved-access group. 5410 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 5411 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 5412 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 5413 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 5414 }; 5415 5416 if (const auto *Entry = 5417 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 5418 return MaskCost + NumOfMemOps * MemOpCost + Entry->Cost; 5419 //If an entry does not exist, fallback to the default implementation. 5420 5421 // Kind of shuffle depends on number of loaded values. 5422 // If we load the entire data in one register, we can use a 1-src shuffle. 5423 // Otherwise, we'll merge 2 sources in each operation. 5424 TTI::ShuffleKind ShuffleKind = 5425 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 5426 5427 InstructionCost ShuffleCost = 5428 getShuffleCost(ShuffleKind, SingleMemOpTy, None, 0, nullptr); 5429 5430 unsigned NumOfLoadsInInterleaveGrp = 5431 Indices.size() ? Indices.size() : Factor; 5432 auto *ResultTy = FixedVectorType::get(VecTy->getElementType(), 5433 VecTy->getNumElements() / Factor); 5434 InstructionCost NumOfResults = 5435 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 5436 NumOfLoadsInInterleaveGrp; 5437 5438 // About a half of the loads may be folded in shuffles when we have only 5439 // one result. If we have more than one result, or the loads are masked, 5440 // we do not fold loads at all. 5441 unsigned NumOfUnfoldedLoads = 5442 UseMaskedMemOp || NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 5443 5444 // Get a number of shuffle operations per result. 5445 unsigned NumOfShufflesPerResult = 5446 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 5447 5448 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 5449 // When we have more than one destination, we need additional instructions 5450 // to keep sources. 5451 InstructionCost NumOfMoves = 0; 5452 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 5453 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 5454 5455 InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 5456 MaskCost + NumOfUnfoldedLoads * MemOpCost + 5457 NumOfMoves; 5458 5459 return Cost; 5460 } 5461 5462 // Store. 5463 assert(Opcode == Instruction::Store && 5464 "Expected Store Instruction at this point"); 5465 // X86InterleavedAccess support only the following interleaved-access group. 5466 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 5467 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 5468 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 5469 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 5470 5471 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 5472 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 5473 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 5474 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 5475 }; 5476 5477 if (const auto *Entry = 5478 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 5479 return MaskCost + NumOfMemOps * MemOpCost + Entry->Cost; 5480 //If an entry does not exist, fallback to the default implementation. 5481 5482 // There is no strided stores meanwhile. And store can't be folded in 5483 // shuffle. 5484 unsigned NumOfSources = Factor; // The number of values to be merged. 5485 InstructionCost ShuffleCost = 5486 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, None, 0, nullptr); 5487 unsigned NumOfShufflesPerStore = NumOfSources - 1; 5488 5489 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 5490 // We need additional instructions to keep sources. 5491 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 5492 InstructionCost Cost = 5493 MaskCost + 5494 NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 5495 NumOfMoves; 5496 return Cost; 5497 } 5498 5499 InstructionCost X86TTIImpl::getInterleavedMemoryOpCost( 5500 unsigned Opcode, Type *BaseTy, unsigned Factor, ArrayRef<unsigned> Indices, 5501 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, 5502 bool UseMaskForCond, bool UseMaskForGaps) { 5503 auto *VecTy = cast<FixedVectorType>(BaseTy); 5504 5505 auto isSupportedOnAVX512 = [&](Type *VecTy, bool HasBW) { 5506 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 5507 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 5508 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 5509 return true; 5510 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8) || 5511 (!ST->useSoftFloat() && ST->hasFP16() && EltTy->isHalfTy())) 5512 return HasBW; 5513 return false; 5514 }; 5515 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 5516 return getInterleavedMemoryOpCostAVX512( 5517 Opcode, VecTy, Factor, Indices, Alignment, 5518 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 5519 5520 if (UseMaskForCond || UseMaskForGaps) 5521 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5522 Alignment, AddressSpace, CostKind, 5523 UseMaskForCond, UseMaskForGaps); 5524 5525 // Get estimation for interleaved load/store operations for SSE-AVX2. 5526 // As opposed to AVX-512, SSE-AVX2 do not have generic shuffles that allow 5527 // computing the cost using a generic formula as a function of generic 5528 // shuffles. We therefore use a lookup table instead, filled according to 5529 // the instruction sequences that codegen currently generates. 5530 5531 // VecTy for interleave memop is <VF*Factor x Elt>. 5532 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 5533 // VecTy = <12 x i32>. 5534 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 5535 5536 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 5537 // the VF=2, while v2i128 is an unsupported MVT vector type 5538 // (see MachineValueType.h::getVectorVT()). 5539 if (!LegalVT.isVector()) 5540 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5541 Alignment, AddressSpace, CostKind); 5542 5543 unsigned VF = VecTy->getNumElements() / Factor; 5544 Type *ScalarTy = VecTy->getElementType(); 5545 // Deduplicate entries, model floats/pointers as appropriately-sized integers. 5546 if (!ScalarTy->isIntegerTy()) 5547 ScalarTy = 5548 Type::getIntNTy(ScalarTy->getContext(), DL.getTypeSizeInBits(ScalarTy)); 5549 5550 // Get the cost of all the memory operations. 5551 // FIXME: discount dead loads. 5552 InstructionCost MemOpCosts = getMemoryOpCost( 5553 Opcode, VecTy, MaybeAlign(Alignment), AddressSpace, CostKind); 5554 5555 auto *VT = FixedVectorType::get(ScalarTy, VF); 5556 EVT ETy = TLI->getValueType(DL, VT); 5557 if (!ETy.isSimple()) 5558 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5559 Alignment, AddressSpace, CostKind); 5560 5561 // TODO: Complete for other data-types and strides. 5562 // Each combination of Stride, element bit width and VF results in a different 5563 // sequence; The cost tables are therefore accessed with: 5564 // Factor (stride) and VectorType=VFxiN. 5565 // The Cost accounts only for the shuffle sequence; 5566 // The cost of the loads/stores is accounted for separately. 5567 // 5568 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 5569 {2, MVT::v2i8, 2}, // (load 4i8 and) deinterleave into 2 x 2i8 5570 {2, MVT::v4i8, 2}, // (load 8i8 and) deinterleave into 2 x 4i8 5571 {2, MVT::v8i8, 2}, // (load 16i8 and) deinterleave into 2 x 8i8 5572 {2, MVT::v16i8, 4}, // (load 32i8 and) deinterleave into 2 x 16i8 5573 {2, MVT::v32i8, 6}, // (load 64i8 and) deinterleave into 2 x 32i8 5574 5575 {2, MVT::v8i16, 6}, // (load 16i16 and) deinterleave into 2 x 8i16 5576 {2, MVT::v16i16, 9}, // (load 32i16 and) deinterleave into 2 x 16i16 5577 {2, MVT::v32i16, 18}, // (load 64i16 and) deinterleave into 2 x 32i16 5578 5579 {2, MVT::v8i32, 4}, // (load 16i32 and) deinterleave into 2 x 8i32 5580 {2, MVT::v16i32, 8}, // (load 32i32 and) deinterleave into 2 x 16i32 5581 {2, MVT::v32i32, 16}, // (load 64i32 and) deinterleave into 2 x 32i32 5582 5583 {2, MVT::v4i64, 4}, // (load 8i64 and) deinterleave into 2 x 4i64 5584 {2, MVT::v8i64, 8}, // (load 16i64 and) deinterleave into 2 x 8i64 5585 {2, MVT::v16i64, 16}, // (load 32i64 and) deinterleave into 2 x 16i64 5586 {2, MVT::v32i64, 32}, // (load 64i64 and) deinterleave into 2 x 32i64 5587 5588 {3, MVT::v2i8, 3}, // (load 6i8 and) deinterleave into 3 x 2i8 5589 {3, MVT::v4i8, 3}, // (load 12i8 and) deinterleave into 3 x 4i8 5590 {3, MVT::v8i8, 6}, // (load 24i8 and) deinterleave into 3 x 8i8 5591 {3, MVT::v16i8, 11}, // (load 48i8 and) deinterleave into 3 x 16i8 5592 {3, MVT::v32i8, 14}, // (load 96i8 and) deinterleave into 3 x 32i8 5593 5594 {3, MVT::v2i16, 5}, // (load 6i16 and) deinterleave into 3 x 2i16 5595 {3, MVT::v4i16, 7}, // (load 12i16 and) deinterleave into 3 x 4i16 5596 {3, MVT::v8i16, 9}, // (load 24i16 and) deinterleave into 3 x 8i16 5597 {3, MVT::v16i16, 28}, // (load 48i16 and) deinterleave into 3 x 16i16 5598 {3, MVT::v32i16, 56}, // (load 96i16 and) deinterleave into 3 x 32i16 5599 5600 {3, MVT::v2i32, 3}, // (load 6i32 and) deinterleave into 3 x 2i32 5601 {3, MVT::v4i32, 3}, // (load 12i32 and) deinterleave into 3 x 4i32 5602 {3, MVT::v8i32, 7}, // (load 24i32 and) deinterleave into 3 x 8i32 5603 {3, MVT::v16i32, 14}, // (load 48i32 and) deinterleave into 3 x 16i32 5604 {3, MVT::v32i32, 32}, // (load 96i32 and) deinterleave into 3 x 32i32 5605 5606 {3, MVT::v2i64, 1}, // (load 6i64 and) deinterleave into 3 x 2i64 5607 {3, MVT::v4i64, 5}, // (load 12i64 and) deinterleave into 3 x 4i64 5608 {3, MVT::v8i64, 10}, // (load 24i64 and) deinterleave into 3 x 8i64 5609 {3, MVT::v16i64, 20}, // (load 48i64 and) deinterleave into 3 x 16i64 5610 5611 {4, MVT::v2i8, 4}, // (load 8i8 and) deinterleave into 4 x 2i8 5612 {4, MVT::v4i8, 4}, // (load 16i8 and) deinterleave into 4 x 4i8 5613 {4, MVT::v8i8, 12}, // (load 32i8 and) deinterleave into 4 x 8i8 5614 {4, MVT::v16i8, 24}, // (load 64i8 and) deinterleave into 4 x 16i8 5615 {4, MVT::v32i8, 56}, // (load 128i8 and) deinterleave into 4 x 32i8 5616 5617 {4, MVT::v2i16, 6}, // (load 8i16 and) deinterleave into 4 x 2i16 5618 {4, MVT::v4i16, 17}, // (load 16i16 and) deinterleave into 4 x 4i16 5619 {4, MVT::v8i16, 33}, // (load 32i16 and) deinterleave into 4 x 8i16 5620 {4, MVT::v16i16, 75}, // (load 64i16 and) deinterleave into 4 x 16i16 5621 {4, MVT::v32i16, 150}, // (load 128i16 and) deinterleave into 4 x 32i16 5622 5623 {4, MVT::v2i32, 4}, // (load 8i32 and) deinterleave into 4 x 2i32 5624 {4, MVT::v4i32, 8}, // (load 16i32 and) deinterleave into 4 x 4i32 5625 {4, MVT::v8i32, 16}, // (load 32i32 and) deinterleave into 4 x 8i32 5626 {4, MVT::v16i32, 32}, // (load 64i32 and) deinterleave into 4 x 16i32 5627 {4, MVT::v32i32, 68}, // (load 128i32 and) deinterleave into 4 x 32i32 5628 5629 {4, MVT::v2i64, 6}, // (load 8i64 and) deinterleave into 4 x 2i64 5630 {4, MVT::v4i64, 8}, // (load 16i64 and) deinterleave into 4 x 4i64 5631 {4, MVT::v8i64, 20}, // (load 32i64 and) deinterleave into 4 x 8i64 5632 {4, MVT::v16i64, 40}, // (load 64i64 and) deinterleave into 4 x 16i64 5633 5634 {6, MVT::v2i8, 6}, // (load 12i8 and) deinterleave into 6 x 2i8 5635 {6, MVT::v4i8, 14}, // (load 24i8 and) deinterleave into 6 x 4i8 5636 {6, MVT::v8i8, 18}, // (load 48i8 and) deinterleave into 6 x 8i8 5637 {6, MVT::v16i8, 43}, // (load 96i8 and) deinterleave into 6 x 16i8 5638 {6, MVT::v32i8, 82}, // (load 192i8 and) deinterleave into 6 x 32i8 5639 5640 {6, MVT::v2i16, 13}, // (load 12i16 and) deinterleave into 6 x 2i16 5641 {6, MVT::v4i16, 9}, // (load 24i16 and) deinterleave into 6 x 4i16 5642 {6, MVT::v8i16, 39}, // (load 48i16 and) deinterleave into 6 x 8i16 5643 {6, MVT::v16i16, 106}, // (load 96i16 and) deinterleave into 6 x 16i16 5644 {6, MVT::v32i16, 212}, // (load 192i16 and) deinterleave into 6 x 32i16 5645 5646 {6, MVT::v2i32, 6}, // (load 12i32 and) deinterleave into 6 x 2i32 5647 {6, MVT::v4i32, 15}, // (load 24i32 and) deinterleave into 6 x 4i32 5648 {6, MVT::v8i32, 31}, // (load 48i32 and) deinterleave into 6 x 8i32 5649 {6, MVT::v16i32, 64}, // (load 96i32 and) deinterleave into 6 x 16i32 5650 5651 {6, MVT::v2i64, 6}, // (load 12i64 and) deinterleave into 6 x 2i64 5652 {6, MVT::v4i64, 18}, // (load 24i64 and) deinterleave into 6 x 4i64 5653 {6, MVT::v8i64, 36}, // (load 48i64 and) deinterleave into 6 x 8i64 5654 5655 {8, MVT::v8i32, 40} // (load 64i32 and) deinterleave into 8 x 8i32 5656 }; 5657 5658 static const CostTblEntry SSSE3InterleavedLoadTbl[] = { 5659 {2, MVT::v4i16, 2}, // (load 8i16 and) deinterleave into 2 x 4i16 5660 }; 5661 5662 static const CostTblEntry SSE2InterleavedLoadTbl[] = { 5663 {2, MVT::v2i16, 2}, // (load 4i16 and) deinterleave into 2 x 2i16 5664 {2, MVT::v4i16, 7}, // (load 8i16 and) deinterleave into 2 x 4i16 5665 5666 {2, MVT::v2i32, 2}, // (load 4i32 and) deinterleave into 2 x 2i32 5667 {2, MVT::v4i32, 2}, // (load 8i32 and) deinterleave into 2 x 4i32 5668 5669 {2, MVT::v2i64, 2}, // (load 4i64 and) deinterleave into 2 x 2i64 5670 }; 5671 5672 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 5673 {2, MVT::v16i8, 3}, // interleave 2 x 16i8 into 32i8 (and store) 5674 {2, MVT::v32i8, 4}, // interleave 2 x 32i8 into 64i8 (and store) 5675 5676 {2, MVT::v8i16, 3}, // interleave 2 x 8i16 into 16i16 (and store) 5677 {2, MVT::v16i16, 4}, // interleave 2 x 16i16 into 32i16 (and store) 5678 {2, MVT::v32i16, 8}, // interleave 2 x 32i16 into 64i16 (and store) 5679 5680 {2, MVT::v4i32, 2}, // interleave 2 x 4i32 into 8i32 (and store) 5681 {2, MVT::v8i32, 4}, // interleave 2 x 8i32 into 16i32 (and store) 5682 {2, MVT::v16i32, 8}, // interleave 2 x 16i32 into 32i32 (and store) 5683 {2, MVT::v32i32, 16}, // interleave 2 x 32i32 into 64i32 (and store) 5684 5685 {2, MVT::v2i64, 2}, // interleave 2 x 2i64 into 4i64 (and store) 5686 {2, MVT::v4i64, 4}, // interleave 2 x 4i64 into 8i64 (and store) 5687 {2, MVT::v8i64, 8}, // interleave 2 x 8i64 into 16i64 (and store) 5688 {2, MVT::v16i64, 16}, // interleave 2 x 16i64 into 32i64 (and store) 5689 {2, MVT::v32i64, 32}, // interleave 2 x 32i64 into 64i64 (and store) 5690 5691 {3, MVT::v2i8, 4}, // interleave 3 x 2i8 into 6i8 (and store) 5692 {3, MVT::v4i8, 4}, // interleave 3 x 4i8 into 12i8 (and store) 5693 {3, MVT::v8i8, 6}, // interleave 3 x 8i8 into 24i8 (and store) 5694 {3, MVT::v16i8, 11}, // interleave 3 x 16i8 into 48i8 (and store) 5695 {3, MVT::v32i8, 13}, // interleave 3 x 32i8 into 96i8 (and store) 5696 5697 {3, MVT::v2i16, 4}, // interleave 3 x 2i16 into 6i16 (and store) 5698 {3, MVT::v4i16, 6}, // interleave 3 x 4i16 into 12i16 (and store) 5699 {3, MVT::v8i16, 12}, // interleave 3 x 8i16 into 24i16 (and store) 5700 {3, MVT::v16i16, 27}, // interleave 3 x 16i16 into 48i16 (and store) 5701 {3, MVT::v32i16, 54}, // interleave 3 x 32i16 into 96i16 (and store) 5702 5703 {3, MVT::v2i32, 4}, // interleave 3 x 2i32 into 6i32 (and store) 5704 {3, MVT::v4i32, 5}, // interleave 3 x 4i32 into 12i32 (and store) 5705 {3, MVT::v8i32, 11}, // interleave 3 x 8i32 into 24i32 (and store) 5706 {3, MVT::v16i32, 22}, // interleave 3 x 16i32 into 48i32 (and store) 5707 {3, MVT::v32i32, 48}, // interleave 3 x 32i32 into 96i32 (and store) 5708 5709 {3, MVT::v2i64, 4}, // interleave 3 x 2i64 into 6i64 (and store) 5710 {3, MVT::v4i64, 6}, // interleave 3 x 4i64 into 12i64 (and store) 5711 {3, MVT::v8i64, 12}, // interleave 3 x 8i64 into 24i64 (and store) 5712 {3, MVT::v16i64, 24}, // interleave 3 x 16i64 into 48i64 (and store) 5713 5714 {4, MVT::v2i8, 4}, // interleave 4 x 2i8 into 8i8 (and store) 5715 {4, MVT::v4i8, 4}, // interleave 4 x 4i8 into 16i8 (and store) 5716 {4, MVT::v8i8, 4}, // interleave 4 x 8i8 into 32i8 (and store) 5717 {4, MVT::v16i8, 8}, // interleave 4 x 16i8 into 64i8 (and store) 5718 {4, MVT::v32i8, 12}, // interleave 4 x 32i8 into 128i8 (and store) 5719 5720 {4, MVT::v2i16, 2}, // interleave 4 x 2i16 into 8i16 (and store) 5721 {4, MVT::v4i16, 6}, // interleave 4 x 4i16 into 16i16 (and store) 5722 {4, MVT::v8i16, 10}, // interleave 4 x 8i16 into 32i16 (and store) 5723 {4, MVT::v16i16, 32}, // interleave 4 x 16i16 into 64i16 (and store) 5724 {4, MVT::v32i16, 64}, // interleave 4 x 32i16 into 128i16 (and store) 5725 5726 {4, MVT::v2i32, 5}, // interleave 4 x 2i32 into 8i32 (and store) 5727 {4, MVT::v4i32, 6}, // interleave 4 x 4i32 into 16i32 (and store) 5728 {4, MVT::v8i32, 16}, // interleave 4 x 8i32 into 32i32 (and store) 5729 {4, MVT::v16i32, 32}, // interleave 4 x 16i32 into 64i32 (and store) 5730 {4, MVT::v32i32, 64}, // interleave 4 x 32i32 into 128i32 (and store) 5731 5732 {4, MVT::v2i64, 6}, // interleave 4 x 2i64 into 8i64 (and store) 5733 {4, MVT::v4i64, 8}, // interleave 4 x 4i64 into 16i64 (and store) 5734 {4, MVT::v8i64, 20}, // interleave 4 x 8i64 into 32i64 (and store) 5735 {4, MVT::v16i64, 40}, // interleave 4 x 16i64 into 64i64 (and store) 5736 5737 {6, MVT::v2i8, 7}, // interleave 6 x 2i8 into 12i8 (and store) 5738 {6, MVT::v4i8, 9}, // interleave 6 x 4i8 into 24i8 (and store) 5739 {6, MVT::v8i8, 16}, // interleave 6 x 8i8 into 48i8 (and store) 5740 {6, MVT::v16i8, 27}, // interleave 6 x 16i8 into 96i8 (and store) 5741 {6, MVT::v32i8, 90}, // interleave 6 x 32i8 into 192i8 (and store) 5742 5743 {6, MVT::v2i16, 10}, // interleave 6 x 2i16 into 12i16 (and store) 5744 {6, MVT::v4i16, 15}, // interleave 6 x 4i16 into 24i16 (and store) 5745 {6, MVT::v8i16, 21}, // interleave 6 x 8i16 into 48i16 (and store) 5746 {6, MVT::v16i16, 58}, // interleave 6 x 16i16 into 96i16 (and store) 5747 {6, MVT::v32i16, 90}, // interleave 6 x 32i16 into 192i16 (and store) 5748 5749 {6, MVT::v2i32, 9}, // interleave 6 x 2i32 into 12i32 (and store) 5750 {6, MVT::v4i32, 12}, // interleave 6 x 4i32 into 24i32 (and store) 5751 {6, MVT::v8i32, 33}, // interleave 6 x 8i32 into 48i32 (and store) 5752 {6, MVT::v16i32, 66}, // interleave 6 x 16i32 into 96i32 (and store) 5753 5754 {6, MVT::v2i64, 8}, // interleave 6 x 2i64 into 12i64 (and store) 5755 {6, MVT::v4i64, 15}, // interleave 6 x 4i64 into 24i64 (and store) 5756 {6, MVT::v8i64, 30}, // interleave 6 x 8i64 into 48i64 (and store) 5757 }; 5758 5759 static const CostTblEntry SSE2InterleavedStoreTbl[] = { 5760 {2, MVT::v2i8, 1}, // interleave 2 x 2i8 into 4i8 (and store) 5761 {2, MVT::v4i8, 1}, // interleave 2 x 4i8 into 8i8 (and store) 5762 {2, MVT::v8i8, 1}, // interleave 2 x 8i8 into 16i8 (and store) 5763 5764 {2, MVT::v2i16, 1}, // interleave 2 x 2i16 into 4i16 (and store) 5765 {2, MVT::v4i16, 1}, // interleave 2 x 4i16 into 8i16 (and store) 5766 5767 {2, MVT::v2i32, 1}, // interleave 2 x 2i32 into 4i32 (and store) 5768 }; 5769 5770 if (Opcode == Instruction::Load) { 5771 auto GetDiscountedCost = [Factor, NumMembers = Indices.size(), 5772 MemOpCosts](const CostTblEntry *Entry) { 5773 // NOTE: this is just an approximation! 5774 // It can over/under -estimate the cost! 5775 return MemOpCosts + divideCeil(NumMembers * Entry->Cost, Factor); 5776 }; 5777 5778 if (ST->hasAVX2()) 5779 if (const auto *Entry = CostTableLookup(AVX2InterleavedLoadTbl, Factor, 5780 ETy.getSimpleVT())) 5781 return GetDiscountedCost(Entry); 5782 5783 if (ST->hasSSSE3()) 5784 if (const auto *Entry = CostTableLookup(SSSE3InterleavedLoadTbl, Factor, 5785 ETy.getSimpleVT())) 5786 return GetDiscountedCost(Entry); 5787 5788 if (ST->hasSSE2()) 5789 if (const auto *Entry = CostTableLookup(SSE2InterleavedLoadTbl, Factor, 5790 ETy.getSimpleVT())) 5791 return GetDiscountedCost(Entry); 5792 } else { 5793 assert(Opcode == Instruction::Store && 5794 "Expected Store Instruction at this point"); 5795 assert((!Indices.size() || Indices.size() == Factor) && 5796 "Interleaved store only supports fully-interleaved groups."); 5797 if (ST->hasAVX2()) 5798 if (const auto *Entry = CostTableLookup(AVX2InterleavedStoreTbl, Factor, 5799 ETy.getSimpleVT())) 5800 return MemOpCosts + Entry->Cost; 5801 5802 if (ST->hasSSE2()) 5803 if (const auto *Entry = CostTableLookup(SSE2InterleavedStoreTbl, Factor, 5804 ETy.getSimpleVT())) 5805 return MemOpCosts + Entry->Cost; 5806 } 5807 5808 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5809 Alignment, AddressSpace, CostKind, 5810 UseMaskForCond, UseMaskForGaps); 5811 } 5812