1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // X86 cost model. 56 // 57 //===----------------------------------------------------------------------===// 58 59 TargetTransformInfo::PopcntSupportKind 60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 61 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 62 // TODO: Currently the __builtin_popcount() implementation using SSE3 63 // instructions is inefficient. Once the problem is fixed, we should 64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 66 } 67 68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 69 TargetTransformInfo::CacheLevel Level) const { 70 switch (Level) { 71 case TargetTransformInfo::CacheLevel::L1D: 72 // - Penryn 73 // - Nehalem 74 // - Westmere 75 // - Sandy Bridge 76 // - Ivy Bridge 77 // - Haswell 78 // - Broadwell 79 // - Skylake 80 // - Kabylake 81 return 32 * 1024; // 32 KByte 82 case TargetTransformInfo::CacheLevel::L2D: 83 // - Penryn 84 // - Nehalem 85 // - Westmere 86 // - Sandy Bridge 87 // - Ivy Bridge 88 // - Haswell 89 // - Broadwell 90 // - Skylake 91 // - Kabylake 92 return 256 * 1024; // 256 KByte 93 } 94 95 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 96 } 97 98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 99 TargetTransformInfo::CacheLevel Level) const { 100 // - Penryn 101 // - Nehalem 102 // - Westmere 103 // - Sandy Bridge 104 // - Ivy Bridge 105 // - Haswell 106 // - Broadwell 107 // - Skylake 108 // - Kabylake 109 switch (Level) { 110 case TargetTransformInfo::CacheLevel::L1D: 111 LLVM_FALLTHROUGH; 112 case TargetTransformInfo::CacheLevel::L2D: 113 return 8; 114 } 115 116 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 117 } 118 119 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 120 bool Vector = (ClassID == 1); 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const { 133 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 134 if (Vector) { 135 if (ST->hasAVX512() && PreferVectorWidth >= 512) 136 return 512; 137 if (ST->hasAVX() && PreferVectorWidth >= 256) 138 return 256; 139 if (ST->hasSSE1() && PreferVectorWidth >= 128) 140 return 128; 141 return 0; 142 } 143 144 if (ST->is64Bit()) 145 return 64; 146 147 return 32; 148 } 149 150 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 151 return getRegisterBitWidth(true); 152 } 153 154 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 155 // If the loop will not be vectorized, don't interleave the loop. 156 // Let regular unroll to unroll the loop, which saves the overflow 157 // check and memory check cost. 158 if (VF == 1) 159 return 1; 160 161 if (ST->isAtom()) 162 return 1; 163 164 // Sandybridge and Haswell have multiple execution ports and pipelined 165 // vector units. 166 if (ST->hasAVX()) 167 return 4; 168 169 return 2; 170 } 171 172 int X86TTIImpl::getArithmeticInstrCost(unsigned Opcode, Type *Ty, 173 TTI::TargetCostKind CostKind, 174 TTI::OperandValueKind Op1Info, 175 TTI::OperandValueKind Op2Info, 176 TTI::OperandValueProperties Opd1PropInfo, 177 TTI::OperandValueProperties Opd2PropInfo, 178 ArrayRef<const Value *> Args, 179 const Instruction *CxtI) { 180 // TODO: Handle more cost kinds. 181 if (CostKind != TTI::TCK_RecipThroughput) 182 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, 183 Op2Info, Opd1PropInfo, 184 Opd2PropInfo, Args, CxtI); 185 // Legalize the type. 186 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 187 188 int ISD = TLI->InstructionOpcodeToISD(Opcode); 189 assert(ISD && "Invalid opcode"); 190 191 static const CostTblEntry GLMCostTable[] = { 192 { ISD::FDIV, MVT::f32, 18 }, // divss 193 { ISD::FDIV, MVT::v4f32, 35 }, // divps 194 { ISD::FDIV, MVT::f64, 33 }, // divsd 195 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 196 }; 197 198 if (ST->useGLMDivSqrtCosts()) 199 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 200 LT.second)) 201 return LT.first * Entry->Cost; 202 203 static const CostTblEntry SLMCostTable[] = { 204 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 205 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 206 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. 207 { ISD::FMUL, MVT::f64, 2 }, // mulsd 208 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 209 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 210 { ISD::FDIV, MVT::f32, 17 }, // divss 211 { ISD::FDIV, MVT::v4f32, 39 }, // divps 212 { ISD::FDIV, MVT::f64, 32 }, // divsd 213 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 214 { ISD::FADD, MVT::v2f64, 2 }, // addpd 215 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 216 // v2i64/v4i64 mul is custom lowered as a series of long: 217 // multiplies(3), shifts(3) and adds(2) 218 // slm muldq version throughput is 2 and addq throughput 4 219 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 220 // 3X4 (addq throughput) = 17 221 { ISD::MUL, MVT::v2i64, 17 }, 222 // slm addq\subq throughput is 4 223 { ISD::ADD, MVT::v2i64, 4 }, 224 { ISD::SUB, MVT::v2i64, 4 }, 225 }; 226 227 if (ST->isSLM()) { 228 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 229 // Check if the operands can be shrinked into a smaller datatype. 230 bool Op1Signed = false; 231 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 232 bool Op2Signed = false; 233 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 234 235 bool signedMode = Op1Signed | Op2Signed; 236 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 237 238 if (OpMinSize <= 7) 239 return LT.first * 3; // pmullw/sext 240 if (!signedMode && OpMinSize <= 8) 241 return LT.first * 3; // pmullw/zext 242 if (OpMinSize <= 15) 243 return LT.first * 5; // pmullw/pmulhw/pshuf 244 if (!signedMode && OpMinSize <= 16) 245 return LT.first * 5; // pmullw/pmulhw/pshuf 246 } 247 248 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 249 LT.second)) { 250 return LT.first * Entry->Cost; 251 } 252 } 253 254 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 255 ISD == ISD::UREM) && 256 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 257 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 258 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 259 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 260 // On X86, vector signed division by constants power-of-two are 261 // normally expanded to the sequence SRA + SRL + ADD + SRA. 262 // The OperandValue properties may not be the same as that of the previous 263 // operation; conservatively assume OP_None. 264 int Cost = 265 2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Op1Info, 266 Op2Info, 267 TargetTransformInfo::OP_None, 268 TargetTransformInfo::OP_None); 269 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 270 Op2Info, 271 TargetTransformInfo::OP_None, 272 TargetTransformInfo::OP_None); 273 Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind, Op1Info, 274 Op2Info, 275 TargetTransformInfo::OP_None, 276 TargetTransformInfo::OP_None); 277 278 if (ISD == ISD::SREM) { 279 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 280 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info, 281 Op2Info); 282 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info, 283 Op2Info); 284 } 285 286 return Cost; 287 } 288 289 // Vector unsigned division/remainder will be simplified to shifts/masks. 290 if (ISD == ISD::UDIV) 291 return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, 292 Op1Info, Op2Info, 293 TargetTransformInfo::OP_None, 294 TargetTransformInfo::OP_None); 295 296 else // UREM 297 return getArithmeticInstrCost(Instruction::And, Ty, CostKind, 298 Op1Info, Op2Info, 299 TargetTransformInfo::OP_None, 300 TargetTransformInfo::OP_None); 301 } 302 303 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 304 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 305 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 306 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 307 }; 308 309 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 310 ST->hasBWI()) { 311 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 312 LT.second)) 313 return LT.first * Entry->Cost; 314 } 315 316 static const CostTblEntry AVX512UniformConstCostTable[] = { 317 { ISD::SRA, MVT::v2i64, 1 }, 318 { ISD::SRA, MVT::v4i64, 1 }, 319 { ISD::SRA, MVT::v8i64, 1 }, 320 321 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 322 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 323 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 324 }; 325 326 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 327 ST->hasAVX512()) { 328 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 329 LT.second)) 330 return LT.first * Entry->Cost; 331 } 332 333 static const CostTblEntry AVX2UniformConstCostTable[] = { 334 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 335 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 336 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 337 338 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 339 }; 340 341 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 342 ST->hasAVX2()) { 343 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 344 LT.second)) 345 return LT.first * Entry->Cost; 346 } 347 348 static const CostTblEntry SSE2UniformConstCostTable[] = { 349 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 350 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 351 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 352 353 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 354 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 355 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 356 }; 357 358 // XOP has faster vXi8 shifts. 359 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 360 ST->hasSSE2() && !ST->hasXOP()) { 361 if (const auto *Entry = 362 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 363 return LT.first * Entry->Cost; 364 } 365 366 static const CostTblEntry AVX512BWConstCostTable[] = { 367 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 368 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 369 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 370 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 371 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 372 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 373 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 374 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 375 }; 376 377 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 378 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 379 ST->hasBWI()) { 380 if (const auto *Entry = 381 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 382 return LT.first * Entry->Cost; 383 } 384 385 static const CostTblEntry AVX512ConstCostTable[] = { 386 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 387 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 388 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 389 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 390 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 391 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 392 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 393 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 394 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 395 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 396 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 397 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 398 }; 399 400 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 401 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 402 ST->hasAVX512()) { 403 if (const auto *Entry = 404 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 405 return LT.first * Entry->Cost; 406 } 407 408 static const CostTblEntry AVX2ConstCostTable[] = { 409 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 410 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 411 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 412 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 413 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 414 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 415 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 416 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 417 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 418 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 419 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 420 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 421 }; 422 423 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 424 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 425 ST->hasAVX2()) { 426 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 427 return LT.first * Entry->Cost; 428 } 429 430 static const CostTblEntry SSE2ConstCostTable[] = { 431 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 432 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 433 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 434 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 435 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 436 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 437 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 438 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 439 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 440 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 441 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 442 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 443 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 444 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 445 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 446 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 447 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 448 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 449 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 450 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 451 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 452 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 453 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 454 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 455 }; 456 457 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 458 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 459 ST->hasSSE2()) { 460 // pmuldq sequence. 461 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 462 return LT.first * 32; 463 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 464 return LT.first * 38; 465 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 466 return LT.first * 15; 467 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 468 return LT.first * 20; 469 470 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 471 return LT.first * Entry->Cost; 472 } 473 474 static const CostTblEntry AVX512BWShiftCostTable[] = { 475 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 476 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 477 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 478 479 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 480 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 481 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 482 483 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 484 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 485 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 486 }; 487 488 if (ST->hasBWI()) 489 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 490 return LT.first * Entry->Cost; 491 492 static const CostTblEntry AVX2UniformCostTable[] = { 493 // Uniform splats are cheaper for the following instructions. 494 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 495 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 496 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 497 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 498 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 499 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 500 }; 501 502 if (ST->hasAVX2() && 503 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 504 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 505 if (const auto *Entry = 506 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 507 return LT.first * Entry->Cost; 508 } 509 510 static const CostTblEntry SSE2UniformCostTable[] = { 511 // Uniform splats are cheaper for the following instructions. 512 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 513 { ISD::SHL, MVT::v4i32, 1 }, // pslld 514 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 515 516 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 517 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 518 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 519 520 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 521 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 522 }; 523 524 if (ST->hasSSE2() && 525 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 526 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 527 if (const auto *Entry = 528 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 529 return LT.first * Entry->Cost; 530 } 531 532 static const CostTblEntry AVX512DQCostTable[] = { 533 { ISD::MUL, MVT::v2i64, 1 }, 534 { ISD::MUL, MVT::v4i64, 1 }, 535 { ISD::MUL, MVT::v8i64, 1 } 536 }; 537 538 // Look for AVX512DQ lowering tricks for custom cases. 539 if (ST->hasDQI()) 540 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 541 return LT.first * Entry->Cost; 542 543 static const CostTblEntry AVX512BWCostTable[] = { 544 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 545 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 546 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 547 548 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence. 549 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence. 550 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence. 551 }; 552 553 // Look for AVX512BW lowering tricks for custom cases. 554 if (ST->hasBWI()) 555 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 556 return LT.first * Entry->Cost; 557 558 static const CostTblEntry AVX512CostTable[] = { 559 { ISD::SHL, MVT::v16i32, 1 }, 560 { ISD::SRL, MVT::v16i32, 1 }, 561 { ISD::SRA, MVT::v16i32, 1 }, 562 563 { ISD::SHL, MVT::v8i64, 1 }, 564 { ISD::SRL, MVT::v8i64, 1 }, 565 566 { ISD::SRA, MVT::v2i64, 1 }, 567 { ISD::SRA, MVT::v4i64, 1 }, 568 { ISD::SRA, MVT::v8i64, 1 }, 569 570 { ISD::MUL, MVT::v64i8, 26 }, // extend/pmullw/trunc sequence. 571 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence. 572 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence. 573 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 574 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 575 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 576 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add 577 578 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 579 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 580 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 581 582 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 583 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 584 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 585 }; 586 587 if (ST->hasAVX512()) 588 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 589 return LT.first * Entry->Cost; 590 591 static const CostTblEntry AVX2ShiftCostTable[] = { 592 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 593 // customize them to detect the cases where shift amount is a scalar one. 594 { ISD::SHL, MVT::v4i32, 1 }, 595 { ISD::SRL, MVT::v4i32, 1 }, 596 { ISD::SRA, MVT::v4i32, 1 }, 597 { ISD::SHL, MVT::v8i32, 1 }, 598 { ISD::SRL, MVT::v8i32, 1 }, 599 { ISD::SRA, MVT::v8i32, 1 }, 600 { ISD::SHL, MVT::v2i64, 1 }, 601 { ISD::SRL, MVT::v2i64, 1 }, 602 { ISD::SHL, MVT::v4i64, 1 }, 603 { ISD::SRL, MVT::v4i64, 1 }, 604 }; 605 606 if (ST->hasAVX512()) { 607 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 608 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 609 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 610 // On AVX512, a packed v32i16 shift left by a constant build_vector 611 // is lowered into a vector multiply (vpmullw). 612 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 613 Op1Info, Op2Info, 614 TargetTransformInfo::OP_None, 615 TargetTransformInfo::OP_None); 616 } 617 618 // Look for AVX2 lowering tricks. 619 if (ST->hasAVX2()) { 620 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 621 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 622 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 623 // On AVX2, a packed v16i16 shift left by a constant build_vector 624 // is lowered into a vector multiply (vpmullw). 625 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 626 Op1Info, Op2Info, 627 TargetTransformInfo::OP_None, 628 TargetTransformInfo::OP_None); 629 630 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 631 return LT.first * Entry->Cost; 632 } 633 634 static const CostTblEntry XOPShiftCostTable[] = { 635 // 128bit shifts take 1cy, but right shifts require negation beforehand. 636 { ISD::SHL, MVT::v16i8, 1 }, 637 { ISD::SRL, MVT::v16i8, 2 }, 638 { ISD::SRA, MVT::v16i8, 2 }, 639 { ISD::SHL, MVT::v8i16, 1 }, 640 { ISD::SRL, MVT::v8i16, 2 }, 641 { ISD::SRA, MVT::v8i16, 2 }, 642 { ISD::SHL, MVT::v4i32, 1 }, 643 { ISD::SRL, MVT::v4i32, 2 }, 644 { ISD::SRA, MVT::v4i32, 2 }, 645 { ISD::SHL, MVT::v2i64, 1 }, 646 { ISD::SRL, MVT::v2i64, 2 }, 647 { ISD::SRA, MVT::v2i64, 2 }, 648 // 256bit shifts require splitting if AVX2 didn't catch them above. 649 { ISD::SHL, MVT::v32i8, 2+2 }, 650 { ISD::SRL, MVT::v32i8, 4+2 }, 651 { ISD::SRA, MVT::v32i8, 4+2 }, 652 { ISD::SHL, MVT::v16i16, 2+2 }, 653 { ISD::SRL, MVT::v16i16, 4+2 }, 654 { ISD::SRA, MVT::v16i16, 4+2 }, 655 { ISD::SHL, MVT::v8i32, 2+2 }, 656 { ISD::SRL, MVT::v8i32, 4+2 }, 657 { ISD::SRA, MVT::v8i32, 4+2 }, 658 { ISD::SHL, MVT::v4i64, 2+2 }, 659 { ISD::SRL, MVT::v4i64, 4+2 }, 660 { ISD::SRA, MVT::v4i64, 4+2 }, 661 }; 662 663 // Look for XOP lowering tricks. 664 if (ST->hasXOP()) { 665 // If the right shift is constant then we'll fold the negation so 666 // it's as cheap as a left shift. 667 int ShiftISD = ISD; 668 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 669 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 670 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 671 ShiftISD = ISD::SHL; 672 if (const auto *Entry = 673 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 674 return LT.first * Entry->Cost; 675 } 676 677 static const CostTblEntry SSE2UniformShiftCostTable[] = { 678 // Uniform splats are cheaper for the following instructions. 679 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 680 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 681 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 682 683 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 684 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 685 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 686 687 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 688 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 689 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 690 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 691 }; 692 693 if (ST->hasSSE2() && 694 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 695 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 696 697 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 698 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 699 return LT.first * 4; // 2*psrad + shuffle. 700 701 if (const auto *Entry = 702 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 703 return LT.first * Entry->Cost; 704 } 705 706 if (ISD == ISD::SHL && 707 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 708 MVT VT = LT.second; 709 // Vector shift left by non uniform constant can be lowered 710 // into vector multiply. 711 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 712 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 713 ISD = ISD::MUL; 714 } 715 716 static const CostTblEntry AVX2CostTable[] = { 717 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. 718 { ISD::SHL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. 719 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 720 { ISD::SHL, MVT::v32i16, 20 }, // 2*extend/vpsrlvd/pack sequence. 721 722 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. 723 { ISD::SRL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. 724 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 725 { ISD::SRL, MVT::v32i16, 20 }, // 2*extend/vpsrlvd/pack sequence. 726 727 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. 728 { ISD::SRA, MVT::v64i8, 48 }, // 2*vpblendvb sequence. 729 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. 730 { ISD::SRA, MVT::v32i16, 20 }, // 2*extend/vpsravd/pack sequence. 731 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. 732 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 733 734 { ISD::SUB, MVT::v32i8, 1 }, // psubb 735 { ISD::ADD, MVT::v32i8, 1 }, // paddb 736 { ISD::SUB, MVT::v16i16, 1 }, // psubw 737 { ISD::ADD, MVT::v16i16, 1 }, // paddw 738 { ISD::SUB, MVT::v8i32, 1 }, // psubd 739 { ISD::ADD, MVT::v8i32, 1 }, // paddd 740 { ISD::SUB, MVT::v4i64, 1 }, // psubq 741 { ISD::ADD, MVT::v4i64, 1 }, // paddq 742 743 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence. 744 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence. 745 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 746 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 747 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add 748 749 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 750 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 751 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 752 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 753 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 754 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 755 756 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 757 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 758 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 759 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 760 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 761 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 762 }; 763 764 // Look for AVX2 lowering tricks for custom cases. 765 if (ST->hasAVX2()) 766 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 767 return LT.first * Entry->Cost; 768 769 static const CostTblEntry AVX1CostTable[] = { 770 // We don't have to scalarize unsupported ops. We can issue two half-sized 771 // operations and we only need to extract the upper YMM half. 772 // Two ops + 1 extract + 1 insert = 4. 773 { ISD::MUL, MVT::v16i16, 4 }, 774 { ISD::MUL, MVT::v8i32, 4 }, 775 { ISD::SUB, MVT::v32i8, 4 }, 776 { ISD::ADD, MVT::v32i8, 4 }, 777 { ISD::SUB, MVT::v16i16, 4 }, 778 { ISD::ADD, MVT::v16i16, 4 }, 779 { ISD::SUB, MVT::v8i32, 4 }, 780 { ISD::ADD, MVT::v8i32, 4 }, 781 { ISD::SUB, MVT::v4i64, 4 }, 782 { ISD::ADD, MVT::v4i64, 4 }, 783 784 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 785 // are lowered as a series of long multiplies(3), shifts(3) and adds(2) 786 // Because we believe v4i64 to be a legal type, we must also include the 787 // extract+insert in the cost table. Therefore, the cost here is 18 788 // instead of 8. 789 { ISD::MUL, MVT::v4i64, 18 }, 790 791 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence. 792 793 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 794 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 795 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 796 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 797 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 798 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 799 }; 800 801 if (ST->hasAVX()) 802 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 803 return LT.first * Entry->Cost; 804 805 static const CostTblEntry SSE42CostTable[] = { 806 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 807 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 808 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 809 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 810 811 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 812 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 813 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 814 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 815 816 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 817 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 818 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 819 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 820 821 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 822 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 823 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 824 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 825 }; 826 827 if (ST->hasSSE42()) 828 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 829 return LT.first * Entry->Cost; 830 831 static const CostTblEntry SSE41CostTable[] = { 832 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 833 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split. 834 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 835 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 836 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 837 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split 838 839 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 840 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split. 841 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 842 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 843 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 844 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split. 845 846 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 847 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split. 848 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 849 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 850 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 851 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split. 852 853 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 854 }; 855 856 if (ST->hasSSE41()) 857 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 858 return LT.first * Entry->Cost; 859 860 static const CostTblEntry SSE2CostTable[] = { 861 // We don't correctly identify costs of casts because they are marked as 862 // custom. 863 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 864 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 865 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 866 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 867 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 868 869 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 870 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 871 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 872 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 873 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 874 875 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 876 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 877 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 878 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 879 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split. 880 881 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence. 882 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 883 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 884 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 885 886 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 887 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 888 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 889 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 890 891 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 892 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 893 894 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 895 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 896 }; 897 898 if (ST->hasSSE2()) 899 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 900 return LT.first * Entry->Cost; 901 902 static const CostTblEntry SSE1CostTable[] = { 903 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 904 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 905 906 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 907 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 908 909 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 910 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 911 912 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 913 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 914 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 915 916 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 917 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 918 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 919 }; 920 921 if (ST->hasSSE1()) 922 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 923 return LT.first * Entry->Cost; 924 925 // It is not a good idea to vectorize division. We have to scalarize it and 926 // in the process we will often end up having to spilling regular 927 // registers. The overhead of division is going to dominate most kernels 928 // anyways so try hard to prevent vectorization of division - it is 929 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 930 // to hide "20 cycles" for each lane. 931 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 932 ISD == ISD::UDIV || ISD == ISD::UREM)) { 933 int ScalarCost = getArithmeticInstrCost( 934 Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info, 935 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 936 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 937 } 938 939 // Fallback to the default implementation. 940 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info); 941 } 942 943 int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, VectorType *BaseTp, 944 int Index, VectorType *SubTp) { 945 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 946 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 947 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 948 949 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 950 if (Kind == TTI::SK_Transpose) 951 Kind = TTI::SK_PermuteTwoSrc; 952 953 // For Broadcasts we are splatting the first element from the first input 954 // register, so only need to reference that input and all the output 955 // registers are the same. 956 if (Kind == TTI::SK_Broadcast) 957 LT.first = 1; 958 959 // Subvector extractions are free if they start at the beginning of a 960 // vector and cheap if the subvectors are aligned. 961 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 962 int NumElts = LT.second.getVectorNumElements(); 963 if ((Index % NumElts) == 0) 964 return 0; 965 std::pair<int, MVT> SubLT = TLI->getTypeLegalizationCost(DL, SubTp); 966 if (SubLT.second.isVector()) { 967 int NumSubElts = SubLT.second.getVectorNumElements(); 968 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 969 return SubLT.first; 970 // Handle some cases for widening legalization. For now we only handle 971 // cases where the original subvector was naturally aligned and evenly 972 // fit in its legalized subvector type. 973 // FIXME: Remove some of the alignment restrictions. 974 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 975 // vectors. 976 int OrigSubElts = cast<VectorType>(SubTp)->getNumElements(); 977 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 978 (NumSubElts % OrigSubElts) == 0 && 979 LT.second.getVectorElementType() == 980 SubLT.second.getVectorElementType() && 981 LT.second.getVectorElementType().getSizeInBits() == 982 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 983 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 984 "Unexpected number of elements!"); 985 auto *VecTy = FixedVectorType::get(BaseTp->getElementType(), 986 LT.second.getVectorNumElements()); 987 auto *SubTy = FixedVectorType::get(BaseTp->getElementType(), 988 SubLT.second.getVectorNumElements()); 989 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 990 int ExtractCost = getShuffleCost(TTI::SK_ExtractSubvector, VecTy, 991 ExtractIndex, SubTy); 992 993 // If the original size is 32-bits or more, we can use pshufd. Otherwise 994 // if we have SSSE3 we can use pshufb. 995 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 996 return ExtractCost + 1; // pshufd or pshufb 997 998 assert(SubTp->getPrimitiveSizeInBits() == 16 && 999 "Unexpected vector size"); 1000 1001 return ExtractCost + 2; // worst case pshufhw + pshufd 1002 } 1003 } 1004 } 1005 1006 // Handle some common (illegal) sub-vector types as they are often very cheap 1007 // to shuffle even on targets without PSHUFB. 1008 EVT VT = TLI->getValueType(DL, BaseTp); 1009 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 1010 !ST->hasSSSE3()) { 1011 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 1012 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 1013 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1014 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1015 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1016 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1017 1018 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1019 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1020 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1021 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1022 1023 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1024 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1025 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1026 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1027 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1028 1029 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1030 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1031 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1032 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1033 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1034 }; 1035 1036 if (ST->hasSSE2()) 1037 if (const auto *Entry = 1038 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1039 return Entry->Cost; 1040 } 1041 1042 // We are going to permute multiple sources and the result will be in multiple 1043 // destinations. Providing an accurate cost only for splits where the element 1044 // type remains the same. 1045 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1046 MVT LegalVT = LT.second; 1047 if (LegalVT.isVector() && 1048 LegalVT.getVectorElementType().getSizeInBits() == 1049 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1050 LegalVT.getVectorNumElements() < BaseTp->getNumElements()) { 1051 1052 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1053 unsigned LegalVTSize = LegalVT.getStoreSize(); 1054 // Number of source vectors after legalization: 1055 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1056 // Number of destination vectors after legalization: 1057 unsigned NumOfDests = LT.first; 1058 1059 auto *SingleOpTy = FixedVectorType::get(BaseTp->getElementType(), 1060 LegalVT.getVectorNumElements()); 1061 1062 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1063 return NumOfShuffles * 1064 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 0, nullptr); 1065 } 1066 1067 return BaseT::getShuffleCost(Kind, BaseTp, Index, SubTp); 1068 } 1069 1070 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1071 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1072 // We assume that source and destination have the same vector type. 1073 int NumOfDests = LT.first; 1074 int NumOfShufflesPerDest = LT.first * 2 - 1; 1075 LT.first = NumOfDests * NumOfShufflesPerDest; 1076 } 1077 1078 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1079 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1080 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1081 1082 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1083 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1084 1085 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b 1086 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b 1087 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2} // vpermt2b 1088 }; 1089 1090 if (ST->hasVBMI()) 1091 if (const auto *Entry = 1092 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1093 return LT.first * Entry->Cost; 1094 1095 static const CostTblEntry AVX512BWShuffleTbl[] = { 1096 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1097 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1098 1099 {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw 1100 {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw 1101 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1102 1103 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw 1104 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw 1105 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1106 1107 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w 1108 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w 1109 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2}, // vpermt2w 1110 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1111 }; 1112 1113 if (ST->hasBWI()) 1114 if (const auto *Entry = 1115 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1116 return LT.first * Entry->Cost; 1117 1118 static const CostTblEntry AVX512ShuffleTbl[] = { 1119 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1120 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1121 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1122 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1123 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1124 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1125 1126 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1127 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1128 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1129 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1130 1131 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1132 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1133 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1134 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1135 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1136 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1137 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1138 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1139 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1140 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1141 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1142 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1143 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1144 1145 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1146 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1147 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1148 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1149 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1150 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1151 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1152 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1153 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1154 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1155 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1156 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1157 1158 // FIXME: This just applies the type legalization cost rules above 1159 // assuming these completely split. 1160 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1161 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1162 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1163 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1164 }; 1165 1166 if (ST->hasAVX512()) 1167 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1168 return LT.first * Entry->Cost; 1169 1170 static const CostTblEntry AVX2ShuffleTbl[] = { 1171 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1172 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1173 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1174 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1175 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1176 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1177 1178 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1179 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1180 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1181 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1182 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1183 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1184 1185 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1186 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1187 1188 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1189 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1190 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1191 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1192 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1193 // + vpblendvb 1194 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1195 // + vpblendvb 1196 1197 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1198 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1199 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1200 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1201 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1202 // + vpblendvb 1203 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1204 // + vpblendvb 1205 }; 1206 1207 if (ST->hasAVX2()) 1208 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1209 return LT.first * Entry->Cost; 1210 1211 static const CostTblEntry XOPShuffleTbl[] = { 1212 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1213 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1214 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1215 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1216 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1217 // + vinsertf128 1218 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1219 // + vinsertf128 1220 1221 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1222 // + vinsertf128 1223 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1224 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1225 // + vinsertf128 1226 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1227 }; 1228 1229 if (ST->hasXOP()) 1230 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1231 return LT.first * Entry->Cost; 1232 1233 static const CostTblEntry AVX1ShuffleTbl[] = { 1234 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1235 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1236 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1237 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1238 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1239 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1240 1241 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1242 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1243 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1244 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1245 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1246 // + vinsertf128 1247 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1248 // + vinsertf128 1249 1250 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1251 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1252 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1253 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1254 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1255 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1256 1257 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1258 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1259 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1260 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1261 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1262 // + 2*por + vinsertf128 1263 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1264 // + 2*por + vinsertf128 1265 1266 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1267 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1268 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1269 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1270 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1271 // + 4*por + vinsertf128 1272 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1273 // + 4*por + vinsertf128 1274 }; 1275 1276 if (ST->hasAVX()) 1277 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1278 return LT.first * Entry->Cost; 1279 1280 static const CostTblEntry SSE41ShuffleTbl[] = { 1281 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1282 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1283 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1284 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1285 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1286 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1287 }; 1288 1289 if (ST->hasSSE41()) 1290 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1291 return LT.first * Entry->Cost; 1292 1293 static const CostTblEntry SSSE3ShuffleTbl[] = { 1294 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1295 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1296 1297 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1298 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1299 1300 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1301 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1302 1303 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1304 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1305 1306 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1307 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1308 }; 1309 1310 if (ST->hasSSSE3()) 1311 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1312 return LT.first * Entry->Cost; 1313 1314 static const CostTblEntry SSE2ShuffleTbl[] = { 1315 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1316 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1317 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1318 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1319 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1320 1321 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1322 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1323 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1324 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1325 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1326 // + 2*pshufd + 2*unpck + packus 1327 1328 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1329 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1330 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1331 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1332 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1333 1334 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1335 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1336 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1337 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1338 // + pshufd/unpck 1339 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1340 // + 2*pshufd + 2*unpck + 2*packus 1341 1342 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1343 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1344 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1345 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1346 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1347 }; 1348 1349 if (ST->hasSSE2()) 1350 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1351 return LT.first * Entry->Cost; 1352 1353 static const CostTblEntry SSE1ShuffleTbl[] = { 1354 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1355 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1356 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1357 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1358 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1359 }; 1360 1361 if (ST->hasSSE1()) 1362 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1363 return LT.first * Entry->Cost; 1364 1365 return BaseT::getShuffleCost(Kind, BaseTp, Index, SubTp); 1366 } 1367 1368 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 1369 TTI::TargetCostKind CostKind, 1370 const Instruction *I) { 1371 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1372 assert(ISD && "Invalid opcode"); 1373 1374 // TODO: Allow non-throughput costs that aren't binary. 1375 auto AdjustCost = [&CostKind](int Cost) { 1376 if (CostKind != TTI::TCK_RecipThroughput) 1377 return Cost == 0 ? 0 : 1; 1378 return Cost; 1379 }; 1380 1381 // FIXME: Need a better design of the cost table to handle non-simple types of 1382 // potential massive combinations (elem_num x src_type x dst_type). 1383 1384 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1385 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1386 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1387 1388 // Mask sign extend has an instruction. 1389 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1390 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1391 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1392 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1393 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1394 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1395 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1396 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1397 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1398 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1399 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1400 1401 // Mask zero extend is a sext + shift. 1402 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1403 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1404 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1405 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1406 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1407 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1408 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1409 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1410 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1411 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1412 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1413 1414 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, 1415 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm 1416 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // widen to zmm 1417 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // widen to zmm 1418 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // widen to zmm 1419 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // widen to zmm 1420 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // widen to zmm 1421 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // widen to zmm 1422 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // widen to zmm 1423 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // widen to zmm 1424 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // widen to zmm 1425 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, 1426 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, 1427 }; 1428 1429 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1430 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1431 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1432 1433 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1434 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1435 1436 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1437 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1438 1439 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1440 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1441 }; 1442 1443 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1444 // 256-bit wide vectors. 1445 1446 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1447 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1448 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1449 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1450 1451 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1452 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1453 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1454 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd 1455 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1456 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1457 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1458 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd 1459 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd 1460 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd 1461 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd 1462 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd 1463 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq 1464 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq 1465 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq 1466 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, 1467 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, 1468 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, 1469 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, 1470 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 1471 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd 1472 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb 1473 1474 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32 1475 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, 1476 1477 // Sign extend is zmm vpternlogd+vptruncdb. 1478 // Zero extend is zmm broadcast load+vptruncdw. 1479 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 }, 1480 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 }, 1481 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, 1482 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, 1483 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, 1484 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, 1485 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 }, 1486 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 }, 1487 1488 // Sign extend is zmm vpternlogd+vptruncdw. 1489 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw. 1490 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 }, 1491 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1492 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 }, 1493 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1494 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 }, 1495 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1496 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 }, 1497 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1498 1499 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd 1500 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld 1501 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd 1502 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld 1503 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd 1504 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld 1505 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq 1506 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq 1507 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq 1508 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq 1509 1510 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd 1511 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld 1512 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq 1513 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq 1514 1515 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1516 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1517 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1518 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1519 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1520 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1521 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1522 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1523 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1524 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1525 1526 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1527 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1528 1529 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1530 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1531 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1532 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1533 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1534 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1535 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1536 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1537 1538 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1539 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1540 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1541 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1542 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1543 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1544 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1545 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1546 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1547 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1548 1549 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f64, 3 }, 1550 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, 1551 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 3 }, 1552 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 3 }, 1553 1554 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1555 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, 1556 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, 1557 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1558 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, 1559 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, 1560 }; 1561 1562 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1563 // Mask sign extend has an instruction. 1564 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1565 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1566 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1567 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1568 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1569 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1570 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1571 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1572 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1573 1574 // Mask zero extend is a sext + shift. 1575 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1576 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1577 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1578 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1579 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1580 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1581 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1582 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1583 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1584 1585 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, 1586 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // vpsllw+vptestmb 1587 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // vpsllw+vptestmw 1588 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // vpsllw+vptestmb 1589 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // vpsllw+vptestmw 1590 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // vpsllw+vptestmb 1591 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // vpsllw+vptestmw 1592 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // vpsllw+vptestmb 1593 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // vpsllw+vptestmw 1594 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // vpsllw+vptestmb 1595 }; 1596 1597 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1598 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1599 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1600 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1601 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1602 1603 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1604 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1605 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1606 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1607 1608 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1609 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1610 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1611 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1612 1613 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1614 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1615 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1616 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1617 }; 1618 1619 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 1620 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1621 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1622 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1623 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 8 }, // split+2*v8i8 1624 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1625 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1626 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1627 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16 1628 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // vpslld+vptestmd 1629 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd 1630 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // vpslld+vptestmd 1631 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // vpsllq+vptestmq 1632 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // vpsllq+vptestmq 1633 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // vpmovqd 1634 1635 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb 1636 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb 1637 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 }, 1638 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 }, 1639 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 }, 1640 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 }, 1641 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 }, 1642 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 }, 1643 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 }, 1644 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 }, 1645 1646 // sign extend is vpcmpeq+maskedmove+vpmovdw 1647 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw 1648 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1649 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 }, 1650 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1651 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 }, 1652 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1653 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 }, 1654 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 }, 1655 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 }, 1656 1657 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd 1658 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld 1659 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd 1660 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld 1661 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd 1662 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld 1663 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq 1664 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq 1665 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq 1666 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq 1667 1668 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1669 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1670 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1671 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1672 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1673 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1674 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1675 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1676 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1677 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1678 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1679 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1680 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1681 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1682 1683 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 1684 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1685 1686 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 3 }, 1687 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 3 }, 1688 1689 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 1690 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 1691 1692 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1693 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1694 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 1 }, 1695 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1696 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1697 }; 1698 1699 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1700 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1701 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1702 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1703 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1704 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1705 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1706 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1707 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1708 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1709 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1710 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1711 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1712 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1713 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1714 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1715 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1716 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1717 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1718 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1719 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1720 1721 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1722 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1723 1724 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 1725 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 1726 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 1727 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1728 1729 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1730 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1731 1732 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1733 }; 1734 1735 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1736 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1737 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1738 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1739 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1740 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1741 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1742 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1743 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1744 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1745 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1746 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1747 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1748 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 4 }, 1749 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1750 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1751 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1752 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1753 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1754 1755 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 4 }, 1756 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 5 }, 1757 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 4 }, 1758 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 9 }, 1759 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, 11 }, 1760 1761 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 1762 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1763 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1764 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1765 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 1766 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1767 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 11 }, 1768 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 9 }, 1769 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 }, 1770 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 11 }, 1771 1772 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1773 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1774 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1775 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1776 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1777 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1778 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1779 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1780 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1781 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1782 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1783 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1784 1785 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1786 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1787 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1788 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1789 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1790 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1791 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1792 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1793 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1794 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 }, 1795 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 1796 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1797 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 1798 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1799 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1800 // The generic code to compute the scalar overhead is currently broken. 1801 // Workaround this limitation by estimating the scalarization overhead 1802 // here. We have roughly 10 instructions per scalar element. 1803 // Multiply that by the vector width. 1804 // FIXME: remove that when PR19268 is fixed. 1805 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1806 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1807 1808 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 4 }, 1809 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f64, 3 }, 1810 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f64, 2 }, 1811 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 3 }, 1812 1813 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f64, 3 }, 1814 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f64, 2 }, 1815 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 4 }, 1816 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 3 }, 1817 // This node is expanded into scalarized operations but BasicTTI is overly 1818 // optimistic estimating its cost. It computes 3 per element (one 1819 // vector-extract, one scalar conversion and one vector-insert). The 1820 // problem is that the inserts form a read-modify-write chain so latency 1821 // should be factored in too. Inflating the cost per element by 1. 1822 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, 1823 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 1824 1825 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 1826 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 1827 }; 1828 1829 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 1830 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1831 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1832 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1833 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1834 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1835 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1836 1837 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1838 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 }, 1839 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1840 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1841 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1842 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1843 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1844 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1845 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1846 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1847 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1848 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1849 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1850 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1851 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1852 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1853 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1854 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1855 1856 // These truncates end up widening elements. 1857 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 1 }, // PMOVXZBQ 1858 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 1 }, // PMOVXZWQ 1859 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 1 }, // PMOVXZBD 1860 1861 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 1 }, 1862 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 1 }, 1863 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 1864 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 1865 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 1866 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 1867 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 1868 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 1869 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 1 }, // PSHUFB 1870 1871 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 1872 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 1873 1874 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 3 }, 1875 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 3 }, 1876 1877 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 3 }, 1878 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 3 }, 1879 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, 1880 }; 1881 1882 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 1883 // These are somewhat magic numbers justified by looking at the output of 1884 // Intel's IACA, running some kernels and making sure when we take 1885 // legalization into account the throughput will be overestimated. 1886 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1887 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1888 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1889 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1890 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1891 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 2*10 }, 1892 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2*10 }, 1893 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1894 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 1895 1896 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1897 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1898 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1899 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1900 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1901 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, 1902 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 }, 1903 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1904 1905 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 4 }, 1906 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 2 }, 1907 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, 1908 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, 1909 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, 1910 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 4 }, 1911 1912 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 1 }, 1913 1914 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 6 }, 1915 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 }, 1916 1917 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 1918 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 1919 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 4 }, 1920 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 4 }, 1921 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 }, 1922 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 2 }, 1923 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 }, 1924 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 4 }, 1925 1926 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1927 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 1928 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 1929 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 1930 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1931 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 1932 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1933 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 1934 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1935 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1936 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1937 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1938 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 1939 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 1940 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1941 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 1942 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1943 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 1944 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1945 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1946 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 1947 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 1948 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1949 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 1950 1951 // These truncates are really widening elements. 1952 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 1 }, // PSHUFD 1953 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // PUNPCKLWD+DQ 1954 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // PUNPCKLBW+WD+PSHUFD 1955 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 1 }, // PUNPCKLWD 1956 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // PUNPCKLBW+WD 1957 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 1 }, // PUNPCKLBW 1958 1959 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // PAND+PACKUSWB 1960 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // PAND+PACKUSWB 1961 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // PAND+PACKUSWB 1962 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 1963 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 3 }, // PAND+2*PACKUSWB 1964 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 1965 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 1966 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 1967 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1968 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 1969 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1970 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 1971 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 1972 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 1973 { ISD::TRUNCATE, MVT::v2i32, MVT::v2i64, 1 }, // PSHUFD 1974 }; 1975 1976 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 1977 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst); 1978 1979 if (ST->hasSSE2() && !ST->hasAVX()) { 1980 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1981 LTDest.second, LTSrc.second)) 1982 return AdjustCost(LTSrc.first * Entry->Cost); 1983 } 1984 1985 EVT SrcTy = TLI->getValueType(DL, Src); 1986 EVT DstTy = TLI->getValueType(DL, Dst); 1987 1988 // The function getSimpleVT only handles simple value types. 1989 if (!SrcTy.isSimple() || !DstTy.isSimple()) 1990 return AdjustCost(BaseT::getCastInstrCost(Opcode, Dst, Src, CostKind)); 1991 1992 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 1993 MVT SimpleDstTy = DstTy.getSimpleVT(); 1994 1995 if (ST->useAVX512Regs()) { 1996 if (ST->hasBWI()) 1997 if (const auto *Entry = ConvertCostTableLookup(AVX512BWConversionTbl, ISD, 1998 SimpleDstTy, SimpleSrcTy)) 1999 return AdjustCost(Entry->Cost); 2000 2001 if (ST->hasDQI()) 2002 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 2003 SimpleDstTy, SimpleSrcTy)) 2004 return AdjustCost(Entry->Cost); 2005 2006 if (ST->hasAVX512()) 2007 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 2008 SimpleDstTy, SimpleSrcTy)) 2009 return AdjustCost(Entry->Cost); 2010 } 2011 2012 if (ST->hasBWI()) 2013 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 2014 SimpleDstTy, SimpleSrcTy)) 2015 return AdjustCost(Entry->Cost); 2016 2017 if (ST->hasDQI()) 2018 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 2019 SimpleDstTy, SimpleSrcTy)) 2020 return AdjustCost(Entry->Cost); 2021 2022 if (ST->hasAVX512()) 2023 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2024 SimpleDstTy, SimpleSrcTy)) 2025 return AdjustCost(Entry->Cost); 2026 2027 if (ST->hasAVX2()) { 2028 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2029 SimpleDstTy, SimpleSrcTy)) 2030 return AdjustCost(Entry->Cost); 2031 } 2032 2033 if (ST->hasAVX()) { 2034 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2035 SimpleDstTy, SimpleSrcTy)) 2036 return AdjustCost(Entry->Cost); 2037 } 2038 2039 if (ST->hasSSE41()) { 2040 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2041 SimpleDstTy, SimpleSrcTy)) 2042 return AdjustCost(Entry->Cost); 2043 } 2044 2045 if (ST->hasSSE2()) { 2046 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2047 SimpleDstTy, SimpleSrcTy)) 2048 return AdjustCost(Entry->Cost); 2049 } 2050 2051 return AdjustCost(BaseT::getCastInstrCost(Opcode, Dst, Src, CostKind, I)); 2052 } 2053 2054 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 2055 TTI::TargetCostKind CostKind, 2056 const Instruction *I) { 2057 // TODO: Handle other cost kinds. 2058 if (CostKind != TTI::TCK_RecipThroughput) 2059 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, CostKind, I); 2060 2061 // Legalize the type. 2062 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2063 2064 MVT MTy = LT.second; 2065 2066 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2067 assert(ISD && "Invalid opcode"); 2068 2069 unsigned ExtraCost = 0; 2070 if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) { 2071 // Some vector comparison predicates cost extra instructions. 2072 if (MTy.isVector() && 2073 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 2074 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 2075 ST->hasBWI())) { 2076 switch (cast<CmpInst>(I)->getPredicate()) { 2077 case CmpInst::Predicate::ICMP_NE: 2078 // xor(cmpeq(x,y),-1) 2079 ExtraCost = 1; 2080 break; 2081 case CmpInst::Predicate::ICMP_SGE: 2082 case CmpInst::Predicate::ICMP_SLE: 2083 // xor(cmpgt(x,y),-1) 2084 ExtraCost = 1; 2085 break; 2086 case CmpInst::Predicate::ICMP_ULT: 2087 case CmpInst::Predicate::ICMP_UGT: 2088 // cmpgt(xor(x,signbit),xor(y,signbit)) 2089 // xor(cmpeq(pmaxu(x,y),x),-1) 2090 ExtraCost = 2; 2091 break; 2092 case CmpInst::Predicate::ICMP_ULE: 2093 case CmpInst::Predicate::ICMP_UGE: 2094 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 2095 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 2096 // cmpeq(psubus(x,y),0) 2097 // cmpeq(pminu(x,y),x) 2098 ExtraCost = 1; 2099 } else { 2100 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 2101 ExtraCost = 3; 2102 } 2103 break; 2104 default: 2105 break; 2106 } 2107 } 2108 } 2109 2110 static const CostTblEntry SLMCostTbl[] = { 2111 // slm pcmpeq/pcmpgt throughput is 2 2112 { ISD::SETCC, MVT::v2i64, 2 }, 2113 }; 2114 2115 static const CostTblEntry AVX512BWCostTbl[] = { 2116 { ISD::SETCC, MVT::v32i16, 1 }, 2117 { ISD::SETCC, MVT::v64i8, 1 }, 2118 2119 { ISD::SELECT, MVT::v32i16, 1 }, 2120 { ISD::SELECT, MVT::v64i8, 1 }, 2121 }; 2122 2123 static const CostTblEntry AVX512CostTbl[] = { 2124 { ISD::SETCC, MVT::v8i64, 1 }, 2125 { ISD::SETCC, MVT::v16i32, 1 }, 2126 { ISD::SETCC, MVT::v8f64, 1 }, 2127 { ISD::SETCC, MVT::v16f32, 1 }, 2128 2129 { ISD::SELECT, MVT::v8i64, 1 }, 2130 { ISD::SELECT, MVT::v16i32, 1 }, 2131 { ISD::SELECT, MVT::v8f64, 1 }, 2132 { ISD::SELECT, MVT::v16f32, 1 }, 2133 2134 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 2135 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 2136 2137 { ISD::SELECT, MVT::v32i16, 2 }, // FIXME: should be 3 2138 { ISD::SELECT, MVT::v64i8, 2 }, // FIXME: should be 3 2139 }; 2140 2141 static const CostTblEntry AVX2CostTbl[] = { 2142 { ISD::SETCC, MVT::v4i64, 1 }, 2143 { ISD::SETCC, MVT::v8i32, 1 }, 2144 { ISD::SETCC, MVT::v16i16, 1 }, 2145 { ISD::SETCC, MVT::v32i8, 1 }, 2146 2147 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 2148 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 2149 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 2150 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 2151 }; 2152 2153 static const CostTblEntry AVX1CostTbl[] = { 2154 { ISD::SETCC, MVT::v4f64, 1 }, 2155 { ISD::SETCC, MVT::v8f32, 1 }, 2156 // AVX1 does not support 8-wide integer compare. 2157 { ISD::SETCC, MVT::v4i64, 4 }, 2158 { ISD::SETCC, MVT::v8i32, 4 }, 2159 { ISD::SETCC, MVT::v16i16, 4 }, 2160 { ISD::SETCC, MVT::v32i8, 4 }, 2161 2162 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 2163 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 2164 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 2165 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 2166 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 2167 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 2168 }; 2169 2170 static const CostTblEntry SSE42CostTbl[] = { 2171 { ISD::SETCC, MVT::v2f64, 1 }, 2172 { ISD::SETCC, MVT::v4f32, 1 }, 2173 { ISD::SETCC, MVT::v2i64, 1 }, 2174 }; 2175 2176 static const CostTblEntry SSE41CostTbl[] = { 2177 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 2178 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 2179 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 2180 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 2181 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 2182 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 2183 }; 2184 2185 static const CostTblEntry SSE2CostTbl[] = { 2186 { ISD::SETCC, MVT::v2f64, 2 }, 2187 { ISD::SETCC, MVT::f64, 1 }, 2188 { ISD::SETCC, MVT::v2i64, 8 }, 2189 { ISD::SETCC, MVT::v4i32, 1 }, 2190 { ISD::SETCC, MVT::v8i16, 1 }, 2191 { ISD::SETCC, MVT::v16i8, 1 }, 2192 2193 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 2194 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 2195 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 2196 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 2197 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 2198 }; 2199 2200 static const CostTblEntry SSE1CostTbl[] = { 2201 { ISD::SETCC, MVT::v4f32, 2 }, 2202 { ISD::SETCC, MVT::f32, 1 }, 2203 2204 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 2205 }; 2206 2207 if (ST->isSLM()) 2208 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2209 return LT.first * (ExtraCost + Entry->Cost); 2210 2211 if (ST->hasBWI()) 2212 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2213 return LT.first * (ExtraCost + Entry->Cost); 2214 2215 if (ST->hasAVX512()) 2216 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2217 return LT.first * (ExtraCost + Entry->Cost); 2218 2219 if (ST->hasAVX2()) 2220 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2221 return LT.first * (ExtraCost + Entry->Cost); 2222 2223 if (ST->hasAVX()) 2224 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2225 return LT.first * (ExtraCost + Entry->Cost); 2226 2227 if (ST->hasSSE42()) 2228 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2229 return LT.first * (ExtraCost + Entry->Cost); 2230 2231 if (ST->hasSSE41()) 2232 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2233 return LT.first * (ExtraCost + Entry->Cost); 2234 2235 if (ST->hasSSE2()) 2236 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2237 return LT.first * (ExtraCost + Entry->Cost); 2238 2239 if (ST->hasSSE1()) 2240 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2241 return LT.first * (ExtraCost + Entry->Cost); 2242 2243 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, CostKind, I); 2244 } 2245 2246 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2247 2248 int X86TTIImpl::getTypeBasedIntrinsicInstrCost( 2249 const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) { 2250 2251 // Costs should match the codegen from: 2252 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2253 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2254 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2255 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2256 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2257 static const CostTblEntry AVX512CDCostTbl[] = { 2258 { ISD::CTLZ, MVT::v8i64, 1 }, 2259 { ISD::CTLZ, MVT::v16i32, 1 }, 2260 { ISD::CTLZ, MVT::v32i16, 8 }, 2261 { ISD::CTLZ, MVT::v64i8, 20 }, 2262 { ISD::CTLZ, MVT::v4i64, 1 }, 2263 { ISD::CTLZ, MVT::v8i32, 1 }, 2264 { ISD::CTLZ, MVT::v16i16, 4 }, 2265 { ISD::CTLZ, MVT::v32i8, 10 }, 2266 { ISD::CTLZ, MVT::v2i64, 1 }, 2267 { ISD::CTLZ, MVT::v4i32, 1 }, 2268 { ISD::CTLZ, MVT::v8i16, 4 }, 2269 { ISD::CTLZ, MVT::v16i8, 4 }, 2270 }; 2271 static const CostTblEntry AVX512BWCostTbl[] = { 2272 { ISD::BITREVERSE, MVT::v8i64, 5 }, 2273 { ISD::BITREVERSE, MVT::v16i32, 5 }, 2274 { ISD::BITREVERSE, MVT::v32i16, 5 }, 2275 { ISD::BITREVERSE, MVT::v64i8, 5 }, 2276 { ISD::CTLZ, MVT::v8i64, 23 }, 2277 { ISD::CTLZ, MVT::v16i32, 22 }, 2278 { ISD::CTLZ, MVT::v32i16, 18 }, 2279 { ISD::CTLZ, MVT::v64i8, 17 }, 2280 { ISD::CTPOP, MVT::v8i64, 7 }, 2281 { ISD::CTPOP, MVT::v16i32, 11 }, 2282 { ISD::CTPOP, MVT::v32i16, 9 }, 2283 { ISD::CTPOP, MVT::v64i8, 6 }, 2284 { ISD::CTTZ, MVT::v8i64, 10 }, 2285 { ISD::CTTZ, MVT::v16i32, 14 }, 2286 { ISD::CTTZ, MVT::v32i16, 12 }, 2287 { ISD::CTTZ, MVT::v64i8, 9 }, 2288 { ISD::SADDSAT, MVT::v32i16, 1 }, 2289 { ISD::SADDSAT, MVT::v64i8, 1 }, 2290 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2291 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2292 { ISD::UADDSAT, MVT::v32i16, 1 }, 2293 { ISD::UADDSAT, MVT::v64i8, 1 }, 2294 { ISD::USUBSAT, MVT::v32i16, 1 }, 2295 { ISD::USUBSAT, MVT::v64i8, 1 }, 2296 }; 2297 static const CostTblEntry AVX512CostTbl[] = { 2298 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2299 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2300 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2301 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2302 { ISD::CTLZ, MVT::v8i64, 29 }, 2303 { ISD::CTLZ, MVT::v16i32, 35 }, 2304 { ISD::CTLZ, MVT::v32i16, 28 }, 2305 { ISD::CTLZ, MVT::v64i8, 18 }, 2306 { ISD::CTPOP, MVT::v8i64, 16 }, 2307 { ISD::CTPOP, MVT::v16i32, 24 }, 2308 { ISD::CTPOP, MVT::v32i16, 18 }, 2309 { ISD::CTPOP, MVT::v64i8, 12 }, 2310 { ISD::CTTZ, MVT::v8i64, 20 }, 2311 { ISD::CTTZ, MVT::v16i32, 28 }, 2312 { ISD::CTTZ, MVT::v32i16, 24 }, 2313 { ISD::CTTZ, MVT::v64i8, 18 }, 2314 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2315 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2316 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2317 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2318 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2319 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2320 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2321 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2322 { ISD::SADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2323 { ISD::SADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2324 { ISD::SSUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2325 { ISD::SSUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2326 { ISD::UADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2327 { ISD::UADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2328 { ISD::USUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2329 { ISD::USUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2330 { ISD::FMAXNUM, MVT::f32, 2 }, 2331 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2332 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2333 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2334 { ISD::FMAXNUM, MVT::f64, 2 }, 2335 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2336 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2337 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2338 }; 2339 static const CostTblEntry XOPCostTbl[] = { 2340 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2341 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2342 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2343 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2344 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2345 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2346 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2347 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2348 { ISD::BITREVERSE, MVT::i64, 3 }, 2349 { ISD::BITREVERSE, MVT::i32, 3 }, 2350 { ISD::BITREVERSE, MVT::i16, 3 }, 2351 { ISD::BITREVERSE, MVT::i8, 3 } 2352 }; 2353 static const CostTblEntry AVX2CostTbl[] = { 2354 { ISD::BITREVERSE, MVT::v4i64, 5 }, 2355 { ISD::BITREVERSE, MVT::v8i32, 5 }, 2356 { ISD::BITREVERSE, MVT::v16i16, 5 }, 2357 { ISD::BITREVERSE, MVT::v32i8, 5 }, 2358 { ISD::BSWAP, MVT::v4i64, 1 }, 2359 { ISD::BSWAP, MVT::v8i32, 1 }, 2360 { ISD::BSWAP, MVT::v16i16, 1 }, 2361 { ISD::CTLZ, MVT::v4i64, 23 }, 2362 { ISD::CTLZ, MVT::v8i32, 18 }, 2363 { ISD::CTLZ, MVT::v16i16, 14 }, 2364 { ISD::CTLZ, MVT::v32i8, 9 }, 2365 { ISD::CTPOP, MVT::v4i64, 7 }, 2366 { ISD::CTPOP, MVT::v8i32, 11 }, 2367 { ISD::CTPOP, MVT::v16i16, 9 }, 2368 { ISD::CTPOP, MVT::v32i8, 6 }, 2369 { ISD::CTTZ, MVT::v4i64, 10 }, 2370 { ISD::CTTZ, MVT::v8i32, 14 }, 2371 { ISD::CTTZ, MVT::v16i16, 12 }, 2372 { ISD::CTTZ, MVT::v32i8, 9 }, 2373 { ISD::SADDSAT, MVT::v16i16, 1 }, 2374 { ISD::SADDSAT, MVT::v32i8, 1 }, 2375 { ISD::SSUBSAT, MVT::v16i16, 1 }, 2376 { ISD::SSUBSAT, MVT::v32i8, 1 }, 2377 { ISD::UADDSAT, MVT::v16i16, 1 }, 2378 { ISD::UADDSAT, MVT::v32i8, 1 }, 2379 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 2380 { ISD::USUBSAT, MVT::v16i16, 1 }, 2381 { ISD::USUBSAT, MVT::v32i8, 1 }, 2382 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2383 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2384 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2385 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2386 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2387 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2388 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2389 }; 2390 static const CostTblEntry AVX1CostTbl[] = { 2391 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 2392 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 2393 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 2394 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 2395 { ISD::BSWAP, MVT::v4i64, 4 }, 2396 { ISD::BSWAP, MVT::v8i32, 4 }, 2397 { ISD::BSWAP, MVT::v16i16, 4 }, 2398 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 2399 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 2400 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 2401 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2402 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 2403 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 2404 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 2405 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 2406 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 2407 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 2408 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 2409 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2410 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2411 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2412 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2413 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2414 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2415 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2416 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 2417 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2418 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2419 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 2420 { ISD::FMAXNUM, MVT::f32, 3 }, 2421 { ISD::FMAXNUM, MVT::v4f32, 3 }, 2422 { ISD::FMAXNUM, MVT::v8f32, 5 }, 2423 { ISD::FMAXNUM, MVT::f64, 3 }, 2424 { ISD::FMAXNUM, MVT::v2f64, 3 }, 2425 { ISD::FMAXNUM, MVT::v4f64, 5 }, 2426 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 2427 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 2428 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 2429 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 2430 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 2431 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 2432 }; 2433 static const CostTblEntry GLMCostTbl[] = { 2434 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 2435 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 2436 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 2437 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 2438 }; 2439 static const CostTblEntry SLMCostTbl[] = { 2440 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 2441 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 2442 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 2443 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 2444 }; 2445 static const CostTblEntry SSE42CostTbl[] = { 2446 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 2447 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 2448 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 2449 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 2450 }; 2451 static const CostTblEntry SSSE3CostTbl[] = { 2452 { ISD::BITREVERSE, MVT::v2i64, 5 }, 2453 { ISD::BITREVERSE, MVT::v4i32, 5 }, 2454 { ISD::BITREVERSE, MVT::v8i16, 5 }, 2455 { ISD::BITREVERSE, MVT::v16i8, 5 }, 2456 { ISD::BSWAP, MVT::v2i64, 1 }, 2457 { ISD::BSWAP, MVT::v4i32, 1 }, 2458 { ISD::BSWAP, MVT::v8i16, 1 }, 2459 { ISD::CTLZ, MVT::v2i64, 23 }, 2460 { ISD::CTLZ, MVT::v4i32, 18 }, 2461 { ISD::CTLZ, MVT::v8i16, 14 }, 2462 { ISD::CTLZ, MVT::v16i8, 9 }, 2463 { ISD::CTPOP, MVT::v2i64, 7 }, 2464 { ISD::CTPOP, MVT::v4i32, 11 }, 2465 { ISD::CTPOP, MVT::v8i16, 9 }, 2466 { ISD::CTPOP, MVT::v16i8, 6 }, 2467 { ISD::CTTZ, MVT::v2i64, 10 }, 2468 { ISD::CTTZ, MVT::v4i32, 14 }, 2469 { ISD::CTTZ, MVT::v8i16, 12 }, 2470 { ISD::CTTZ, MVT::v16i8, 9 } 2471 }; 2472 static const CostTblEntry SSE2CostTbl[] = { 2473 { ISD::BITREVERSE, MVT::v2i64, 29 }, 2474 { ISD::BITREVERSE, MVT::v4i32, 27 }, 2475 { ISD::BITREVERSE, MVT::v8i16, 27 }, 2476 { ISD::BITREVERSE, MVT::v16i8, 20 }, 2477 { ISD::BSWAP, MVT::v2i64, 7 }, 2478 { ISD::BSWAP, MVT::v4i32, 7 }, 2479 { ISD::BSWAP, MVT::v8i16, 7 }, 2480 { ISD::CTLZ, MVT::v2i64, 25 }, 2481 { ISD::CTLZ, MVT::v4i32, 26 }, 2482 { ISD::CTLZ, MVT::v8i16, 20 }, 2483 { ISD::CTLZ, MVT::v16i8, 17 }, 2484 { ISD::CTPOP, MVT::v2i64, 12 }, 2485 { ISD::CTPOP, MVT::v4i32, 15 }, 2486 { ISD::CTPOP, MVT::v8i16, 13 }, 2487 { ISD::CTPOP, MVT::v16i8, 10 }, 2488 { ISD::CTTZ, MVT::v2i64, 14 }, 2489 { ISD::CTTZ, MVT::v4i32, 18 }, 2490 { ISD::CTTZ, MVT::v8i16, 16 }, 2491 { ISD::CTTZ, MVT::v16i8, 13 }, 2492 { ISD::SADDSAT, MVT::v8i16, 1 }, 2493 { ISD::SADDSAT, MVT::v16i8, 1 }, 2494 { ISD::SSUBSAT, MVT::v8i16, 1 }, 2495 { ISD::SSUBSAT, MVT::v16i8, 1 }, 2496 { ISD::UADDSAT, MVT::v8i16, 1 }, 2497 { ISD::UADDSAT, MVT::v16i8, 1 }, 2498 { ISD::USUBSAT, MVT::v8i16, 1 }, 2499 { ISD::USUBSAT, MVT::v16i8, 1 }, 2500 { ISD::FMAXNUM, MVT::f64, 4 }, 2501 { ISD::FMAXNUM, MVT::v2f64, 4 }, 2502 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 2503 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 2504 }; 2505 static const CostTblEntry SSE1CostTbl[] = { 2506 { ISD::FMAXNUM, MVT::f32, 4 }, 2507 { ISD::FMAXNUM, MVT::v4f32, 4 }, 2508 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 2509 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 2510 }; 2511 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 2512 { ISD::CTTZ, MVT::i64, 1 }, 2513 }; 2514 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 2515 { ISD::CTTZ, MVT::i32, 1 }, 2516 { ISD::CTTZ, MVT::i16, 1 }, 2517 { ISD::CTTZ, MVT::i8, 1 }, 2518 }; 2519 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 2520 { ISD::CTLZ, MVT::i64, 1 }, 2521 }; 2522 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 2523 { ISD::CTLZ, MVT::i32, 1 }, 2524 { ISD::CTLZ, MVT::i16, 1 }, 2525 { ISD::CTLZ, MVT::i8, 1 }, 2526 }; 2527 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 2528 { ISD::CTPOP, MVT::i64, 1 }, 2529 }; 2530 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 2531 { ISD::CTPOP, MVT::i32, 1 }, 2532 { ISD::CTPOP, MVT::i16, 1 }, 2533 { ISD::CTPOP, MVT::i8, 1 }, 2534 }; 2535 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2536 { ISD::BITREVERSE, MVT::i64, 14 }, 2537 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 2538 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 2539 { ISD::CTPOP, MVT::i64, 10 }, 2540 { ISD::SADDO, MVT::i64, 1 }, 2541 { ISD::UADDO, MVT::i64, 1 }, 2542 }; 2543 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2544 { ISD::BITREVERSE, MVT::i32, 14 }, 2545 { ISD::BITREVERSE, MVT::i16, 14 }, 2546 { ISD::BITREVERSE, MVT::i8, 11 }, 2547 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 2548 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 2549 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 2550 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 2551 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 2552 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 2553 { ISD::CTPOP, MVT::i32, 8 }, 2554 { ISD::CTPOP, MVT::i16, 9 }, 2555 { ISD::CTPOP, MVT::i8, 7 }, 2556 { ISD::SADDO, MVT::i32, 1 }, 2557 { ISD::SADDO, MVT::i16, 1 }, 2558 { ISD::SADDO, MVT::i8, 1 }, 2559 { ISD::UADDO, MVT::i32, 1 }, 2560 { ISD::UADDO, MVT::i16, 1 }, 2561 { ISD::UADDO, MVT::i8, 1 }, 2562 }; 2563 2564 Type *RetTy = ICA.getReturnType(); 2565 Type *OpTy = RetTy; 2566 Intrinsic::ID IID = ICA.getID(); 2567 unsigned ISD = ISD::DELETED_NODE; 2568 switch (IID) { 2569 default: 2570 break; 2571 case Intrinsic::bitreverse: 2572 ISD = ISD::BITREVERSE; 2573 break; 2574 case Intrinsic::bswap: 2575 ISD = ISD::BSWAP; 2576 break; 2577 case Intrinsic::ctlz: 2578 ISD = ISD::CTLZ; 2579 break; 2580 case Intrinsic::ctpop: 2581 ISD = ISD::CTPOP; 2582 break; 2583 case Intrinsic::cttz: 2584 ISD = ISD::CTTZ; 2585 break; 2586 case Intrinsic::maxnum: 2587 case Intrinsic::minnum: 2588 // FMINNUM has same costs so don't duplicate. 2589 ISD = ISD::FMAXNUM; 2590 break; 2591 case Intrinsic::sadd_sat: 2592 ISD = ISD::SADDSAT; 2593 break; 2594 case Intrinsic::ssub_sat: 2595 ISD = ISD::SSUBSAT; 2596 break; 2597 case Intrinsic::uadd_sat: 2598 ISD = ISD::UADDSAT; 2599 break; 2600 case Intrinsic::usub_sat: 2601 ISD = ISD::USUBSAT; 2602 break; 2603 case Intrinsic::sqrt: 2604 ISD = ISD::FSQRT; 2605 break; 2606 case Intrinsic::sadd_with_overflow: 2607 case Intrinsic::ssub_with_overflow: 2608 // SSUBO has same costs so don't duplicate. 2609 ISD = ISD::SADDO; 2610 OpTy = RetTy->getContainedType(0); 2611 break; 2612 case Intrinsic::uadd_with_overflow: 2613 case Intrinsic::usub_with_overflow: 2614 // USUBO has same costs so don't duplicate. 2615 ISD = ISD::UADDO; 2616 OpTy = RetTy->getContainedType(0); 2617 break; 2618 } 2619 2620 if (ISD != ISD::DELETED_NODE) { 2621 // Legalize the type. 2622 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 2623 MVT MTy = LT.second; 2624 2625 // Attempt to lookup cost. 2626 if (ST->useGLMDivSqrtCosts()) 2627 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 2628 return LT.first * Entry->Cost; 2629 2630 if (ST->isSLM()) 2631 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2632 return LT.first * Entry->Cost; 2633 2634 if (ST->hasCDI()) 2635 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 2636 return LT.first * Entry->Cost; 2637 2638 if (ST->hasBWI()) 2639 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2640 return LT.first * Entry->Cost; 2641 2642 if (ST->hasAVX512()) 2643 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2644 return LT.first * Entry->Cost; 2645 2646 if (ST->hasXOP()) 2647 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2648 return LT.first * Entry->Cost; 2649 2650 if (ST->hasAVX2()) 2651 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2652 return LT.first * Entry->Cost; 2653 2654 if (ST->hasAVX()) 2655 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2656 return LT.first * Entry->Cost; 2657 2658 if (ST->hasSSE42()) 2659 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2660 return LT.first * Entry->Cost; 2661 2662 if (ST->hasSSSE3()) 2663 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 2664 return LT.first * Entry->Cost; 2665 2666 if (ST->hasSSE2()) 2667 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2668 return LT.first * Entry->Cost; 2669 2670 if (ST->hasSSE1()) 2671 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2672 return LT.first * Entry->Cost; 2673 2674 if (ST->hasBMI()) { 2675 if (ST->is64Bit()) 2676 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 2677 return LT.first * Entry->Cost; 2678 2679 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 2680 return LT.first * Entry->Cost; 2681 } 2682 2683 if (ST->hasLZCNT()) { 2684 if (ST->is64Bit()) 2685 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 2686 return LT.first * Entry->Cost; 2687 2688 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 2689 return LT.first * Entry->Cost; 2690 } 2691 2692 if (ST->hasPOPCNT()) { 2693 if (ST->is64Bit()) 2694 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 2695 return LT.first * Entry->Cost; 2696 2697 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 2698 return LT.first * Entry->Cost; 2699 } 2700 2701 // TODO - add BMI (TZCNT) scalar handling 2702 2703 if (ST->is64Bit()) 2704 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2705 return LT.first * Entry->Cost; 2706 2707 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2708 return LT.first * Entry->Cost; 2709 } 2710 2711 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 2712 } 2713 2714 int X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 2715 TTI::TargetCostKind CostKind) { 2716 if (CostKind != TTI::TCK_RecipThroughput) 2717 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 2718 2719 if (ICA.isTypeBasedOnly()) 2720 return getTypeBasedIntrinsicInstrCost(ICA, CostKind); 2721 2722 static const CostTblEntry AVX512CostTbl[] = { 2723 { ISD::ROTL, MVT::v8i64, 1 }, 2724 { ISD::ROTL, MVT::v4i64, 1 }, 2725 { ISD::ROTL, MVT::v2i64, 1 }, 2726 { ISD::ROTL, MVT::v16i32, 1 }, 2727 { ISD::ROTL, MVT::v8i32, 1 }, 2728 { ISD::ROTL, MVT::v4i32, 1 }, 2729 { ISD::ROTR, MVT::v8i64, 1 }, 2730 { ISD::ROTR, MVT::v4i64, 1 }, 2731 { ISD::ROTR, MVT::v2i64, 1 }, 2732 { ISD::ROTR, MVT::v16i32, 1 }, 2733 { ISD::ROTR, MVT::v8i32, 1 }, 2734 { ISD::ROTR, MVT::v4i32, 1 } 2735 }; 2736 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 2737 static const CostTblEntry XOPCostTbl[] = { 2738 { ISD::ROTL, MVT::v4i64, 4 }, 2739 { ISD::ROTL, MVT::v8i32, 4 }, 2740 { ISD::ROTL, MVT::v16i16, 4 }, 2741 { ISD::ROTL, MVT::v32i8, 4 }, 2742 { ISD::ROTL, MVT::v2i64, 1 }, 2743 { ISD::ROTL, MVT::v4i32, 1 }, 2744 { ISD::ROTL, MVT::v8i16, 1 }, 2745 { ISD::ROTL, MVT::v16i8, 1 }, 2746 { ISD::ROTR, MVT::v4i64, 6 }, 2747 { ISD::ROTR, MVT::v8i32, 6 }, 2748 { ISD::ROTR, MVT::v16i16, 6 }, 2749 { ISD::ROTR, MVT::v32i8, 6 }, 2750 { ISD::ROTR, MVT::v2i64, 2 }, 2751 { ISD::ROTR, MVT::v4i32, 2 }, 2752 { ISD::ROTR, MVT::v8i16, 2 }, 2753 { ISD::ROTR, MVT::v16i8, 2 } 2754 }; 2755 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2756 { ISD::ROTL, MVT::i64, 1 }, 2757 { ISD::ROTR, MVT::i64, 1 }, 2758 { ISD::FSHL, MVT::i64, 4 } 2759 }; 2760 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2761 { ISD::ROTL, MVT::i32, 1 }, 2762 { ISD::ROTL, MVT::i16, 1 }, 2763 { ISD::ROTL, MVT::i8, 1 }, 2764 { ISD::ROTR, MVT::i32, 1 }, 2765 { ISD::ROTR, MVT::i16, 1 }, 2766 { ISD::ROTR, MVT::i8, 1 }, 2767 { ISD::FSHL, MVT::i32, 4 }, 2768 { ISD::FSHL, MVT::i16, 4 }, 2769 { ISD::FSHL, MVT::i8, 4 } 2770 }; 2771 2772 Intrinsic::ID IID = ICA.getID(); 2773 Type *RetTy = ICA.getReturnType(); 2774 const SmallVectorImpl<Value *> &Args = ICA.getArgs(); 2775 unsigned ISD = ISD::DELETED_NODE; 2776 switch (IID) { 2777 default: 2778 break; 2779 case Intrinsic::fshl: 2780 ISD = ISD::FSHL; 2781 if (Args[0] == Args[1]) 2782 ISD = ISD::ROTL; 2783 break; 2784 case Intrinsic::fshr: 2785 // FSHR has same costs so don't duplicate. 2786 ISD = ISD::FSHL; 2787 if (Args[0] == Args[1]) 2788 ISD = ISD::ROTR; 2789 break; 2790 } 2791 2792 if (ISD != ISD::DELETED_NODE) { 2793 // Legalize the type. 2794 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 2795 MVT MTy = LT.second; 2796 2797 // Attempt to lookup cost. 2798 if (ST->hasAVX512()) 2799 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2800 return LT.first * Entry->Cost; 2801 2802 if (ST->hasXOP()) 2803 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2804 return LT.first * Entry->Cost; 2805 2806 if (ST->is64Bit()) 2807 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2808 return LT.first * Entry->Cost; 2809 2810 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2811 return LT.first * Entry->Cost; 2812 } 2813 2814 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 2815 } 2816 2817 int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { 2818 static const CostTblEntry SLMCostTbl[] = { 2819 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 2820 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 2821 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 2822 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 2823 }; 2824 2825 assert(Val->isVectorTy() && "This must be a vector type"); 2826 Type *ScalarType = Val->getScalarType(); 2827 int RegisterFileMoveCost = 0; 2828 2829 if (Index != -1U && (Opcode == Instruction::ExtractElement || 2830 Opcode == Instruction::InsertElement)) { 2831 // Legalize the type. 2832 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 2833 2834 // This type is legalized to a scalar type. 2835 if (!LT.second.isVector()) 2836 return 0; 2837 2838 // The type may be split. Normalize the index to the new type. 2839 unsigned NumElts = LT.second.getVectorNumElements(); 2840 unsigned SubNumElts = NumElts; 2841 Index = Index % NumElts; 2842 2843 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 2844 // For inserts, we also need to insert the subvector back. 2845 if (LT.second.getSizeInBits() > 128) { 2846 assert((LT.second.getSizeInBits() % 128) == 0 && "Illegal vector"); 2847 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 2848 SubNumElts = NumElts / NumSubVecs; 2849 if (SubNumElts <= Index) { 2850 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 2851 Index %= SubNumElts; 2852 } 2853 } 2854 2855 if (Index == 0) { 2856 // Floating point scalars are already located in index #0. 2857 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 2858 // true for all. 2859 if (ScalarType->isFloatingPointTy()) 2860 return RegisterFileMoveCost; 2861 2862 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 2863 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 2864 return 1 + RegisterFileMoveCost; 2865 } 2866 2867 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2868 assert(ISD && "Unexpected vector opcode"); 2869 MVT MScalarTy = LT.second.getScalarType(); 2870 if (ST->isSLM()) 2871 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 2872 return Entry->Cost + RegisterFileMoveCost; 2873 2874 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 2875 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 2876 (MScalarTy.isInteger() && ST->hasSSE41())) 2877 return 1 + RegisterFileMoveCost; 2878 2879 // Assume insertps is relatively cheap on all targets. 2880 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 2881 Opcode == Instruction::InsertElement) 2882 return 1 + RegisterFileMoveCost; 2883 2884 // For extractions we just need to shuffle the element to index 0, which 2885 // should be very cheap (assume cost = 1). For insertions we need to shuffle 2886 // the elements to its destination. In both cases we must handle the 2887 // subvector move(s). 2888 // If the vector type is already less than 128-bits then don't reduce it. 2889 // TODO: Under what circumstances should we shuffle using the full width? 2890 int ShuffleCost = 1; 2891 if (Opcode == Instruction::InsertElement) { 2892 auto *SubTy = cast<VectorType>(Val); 2893 EVT VT = TLI->getValueType(DL, Val); 2894 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 2895 SubTy = FixedVectorType::get(ScalarType, SubNumElts); 2896 ShuffleCost = getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, 0, SubTy); 2897 } 2898 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 2899 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 2900 } 2901 2902 // Add to the base cost if we know that the extracted element of a vector is 2903 // destined to be moved to and used in the integer register file. 2904 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 2905 RegisterFileMoveCost += 1; 2906 2907 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 2908 } 2909 2910 unsigned X86TTIImpl::getScalarizationOverhead(VectorType *Ty, 2911 const APInt &DemandedElts, 2912 bool Insert, bool Extract) { 2913 unsigned Cost = 0; 2914 2915 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much 2916 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT. 2917 if (Insert) { 2918 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 2919 MVT MScalarTy = LT.second.getScalarType(); 2920 2921 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 2922 (MScalarTy.isInteger() && ST->hasSSE41()) || 2923 (MScalarTy == MVT::f32 && ST->hasSSE41())) { 2924 // For types we can insert directly, insertion into 128-bit sub vectors is 2925 // cheap, followed by a cheap chain of concatenations. 2926 if (LT.second.getSizeInBits() <= 128) { 2927 Cost += 2928 BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, false); 2929 } else { 2930 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 2931 Cost += (PowerOf2Ceil(NumSubVecs) - 1) * LT.first; 2932 Cost += DemandedElts.countPopulation(); 2933 2934 // For vXf32 cases, insertion into the 0'th index in each v4f32 2935 // 128-bit vector is free. 2936 // NOTE: This assumes legalization widens vXf32 vectors. 2937 if (MScalarTy == MVT::f32) 2938 for (unsigned i = 0, e = Ty->getNumElements(); i < e; i += 4) 2939 if (DemandedElts[i]) 2940 Cost--; 2941 } 2942 } else if (LT.second.isVector()) { 2943 // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded 2944 // integer element as a SCALAR_TO_VECTOR, then we build the vector as a 2945 // series of UNPCK followed by CONCAT_VECTORS - all of these can be 2946 // considered cheap. 2947 if (Ty->isIntOrIntVectorTy()) 2948 Cost += DemandedElts.countPopulation(); 2949 2950 // Get the smaller of the legalized or original pow2-extended number of 2951 // vector elements, which represents the number of unpacks we'll end up 2952 // performing. 2953 unsigned NumElts = LT.second.getVectorNumElements(); 2954 unsigned Pow2Elts = PowerOf2Ceil(Ty->getNumElements()); 2955 Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first; 2956 } 2957 } 2958 2959 // TODO: Use default extraction for now, but we should investigate extending this 2960 // to handle repeated subvector extraction. 2961 if (Extract) 2962 Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, false, Extract); 2963 2964 return Cost; 2965 } 2966 2967 int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 2968 MaybeAlign Alignment, unsigned AddressSpace, 2969 TTI::TargetCostKind CostKind, 2970 const Instruction *I) { 2971 // TODO: Handle other cost kinds. 2972 if (CostKind != TTI::TCK_RecipThroughput) { 2973 if (isa_and_nonnull<StoreInst>(I)) { 2974 Value *Ptr = I->getOperand(1); 2975 // Store instruction with index and scale costs 2 Uops. 2976 // Check the preceding GEP to identify non-const indices. 2977 if (auto *GEP = dyn_cast<GetElementPtrInst>(Ptr)) { 2978 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 2979 return TTI::TCC_Basic * 2; 2980 } 2981 } 2982 return TTI::TCC_Basic; 2983 } 2984 2985 // Handle non-power-of-two vectors such as <3 x float> 2986 if (VectorType *VTy = dyn_cast<VectorType>(Src)) { 2987 unsigned NumElem = VTy->getNumElements(); 2988 2989 // Handle a few common cases: 2990 // <3 x float> 2991 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 2992 // Cost = 64 bit store + extract + 32 bit store. 2993 return 3; 2994 2995 // <3 x double> 2996 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 2997 // Cost = 128 bit store + unpack + 64 bit store. 2998 return 3; 2999 3000 // Assume that all other non-power-of-two numbers are scalarized. 3001 if (!isPowerOf2_32(NumElem)) { 3002 APInt DemandedElts = APInt::getAllOnesValue(NumElem); 3003 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment, 3004 AddressSpace, CostKind); 3005 int SplitCost = getScalarizationOverhead(VTy, DemandedElts, 3006 Opcode == Instruction::Load, 3007 Opcode == Instruction::Store); 3008 return NumElem * Cost + SplitCost; 3009 } 3010 } 3011 3012 // Type legalization can't handle structs 3013 if (TLI->getValueType(DL, Src, true) == MVT::Other) 3014 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3015 CostKind); 3016 3017 // Legalize the type. 3018 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 3019 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 3020 "Invalid Opcode"); 3021 3022 // Each load/store unit costs 1. 3023 int Cost = LT.first * 1; 3024 3025 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a 3026 // proxy for a double-pumped AVX memory interface such as on Sandybridge. 3027 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow()) 3028 Cost *= 2; 3029 3030 return Cost; 3031 } 3032 3033 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, 3034 unsigned Alignment, 3035 unsigned AddressSpace, 3036 TTI::TargetCostKind CostKind) { 3037 bool IsLoad = (Instruction::Load == Opcode); 3038 bool IsStore = (Instruction::Store == Opcode); 3039 3040 VectorType *SrcVTy = dyn_cast<VectorType>(SrcTy); 3041 if (!SrcVTy) 3042 // To calculate scalar take the regular cost, without mask 3043 return getMemoryOpCost(Opcode, SrcTy, MaybeAlign(Alignment), AddressSpace, 3044 CostKind); 3045 3046 unsigned NumElem = SrcVTy->getNumElements(); 3047 auto *MaskTy = 3048 FixedVectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 3049 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, MaybeAlign(Alignment))) || 3050 (IsStore && !isLegalMaskedStore(SrcVTy, MaybeAlign(Alignment))) || 3051 !isPowerOf2_32(NumElem)) { 3052 // Scalarization 3053 APInt DemandedElts = APInt::getAllOnesValue(NumElem); 3054 int MaskSplitCost = 3055 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 3056 int ScalarCompareCost = getCmpSelInstrCost( 3057 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr, 3058 CostKind); 3059 int BranchCost = getCFInstrCost(Instruction::Br, CostKind); 3060 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 3061 int ValueSplitCost = 3062 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore); 3063 int MemopCost = 3064 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3065 MaybeAlign(Alignment), AddressSpace, 3066 CostKind); 3067 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 3068 } 3069 3070 // Legalize the type. 3071 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3072 auto VT = TLI->getValueType(DL, SrcVTy); 3073 int Cost = 0; 3074 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 3075 LT.second.getVectorNumElements() == NumElem) 3076 // Promotion requires expand/truncate for data and a shuffle for mask. 3077 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, 0, nullptr) + 3078 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, 0, nullptr); 3079 3080 else if (LT.second.getVectorNumElements() > NumElem) { 3081 auto *NewMaskTy = FixedVectorType::get(MaskTy->getElementType(), 3082 LT.second.getVectorNumElements()); 3083 // Expanding requires fill mask with zeroes 3084 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, 0, MaskTy); 3085 } 3086 3087 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 3088 if (!ST->hasAVX512()) 3089 return Cost + LT.first * (IsLoad ? 2 : 8); 3090 3091 // AVX-512 masked load/store is cheapper 3092 return Cost + LT.first; 3093 } 3094 3095 int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE, 3096 const SCEV *Ptr) { 3097 // Address computations in vectorized code with non-consecutive addresses will 3098 // likely result in more instructions compared to scalar code where the 3099 // computation can more often be merged into the index mode. The resulting 3100 // extra micro-ops can significantly decrease throughput. 3101 const unsigned NumVectorInstToHideOverhead = 10; 3102 3103 // Cost modeling of Strided Access Computation is hidden by the indexing 3104 // modes of X86 regardless of the stride value. We dont believe that there 3105 // is a difference between constant strided access in gerenal and constant 3106 // strided value which is less than or equal to 64. 3107 // Even in the case of (loop invariant) stride whose value is not known at 3108 // compile time, the address computation will not incur more than one extra 3109 // ADD instruction. 3110 if (Ty->isVectorTy() && SE) { 3111 if (!BaseT::isStridedAccess(Ptr)) 3112 return NumVectorInstToHideOverhead; 3113 if (!BaseT::getConstantStrideStep(SE, Ptr)) 3114 return 1; 3115 } 3116 3117 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 3118 } 3119 3120 int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 3121 bool IsPairwise, 3122 TTI::TargetCostKind CostKind) { 3123 // Just use the default implementation for pair reductions. 3124 if (IsPairwise) 3125 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise, CostKind); 3126 3127 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3128 // and make it as the cost. 3129 3130 static const CostTblEntry SLMCostTblNoPairWise[] = { 3131 { ISD::FADD, MVT::v2f64, 3 }, 3132 { ISD::ADD, MVT::v2i64, 5 }, 3133 }; 3134 3135 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3136 { ISD::FADD, MVT::v2f64, 2 }, 3137 { ISD::FADD, MVT::v4f32, 4 }, 3138 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 3139 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 3140 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 3141 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 3142 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 3143 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 3144 { ISD::ADD, MVT::v2i8, 2 }, 3145 { ISD::ADD, MVT::v4i8, 2 }, 3146 { ISD::ADD, MVT::v8i8, 2 }, 3147 { ISD::ADD, MVT::v16i8, 3 }, 3148 }; 3149 3150 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3151 { ISD::FADD, MVT::v4f64, 3 }, 3152 { ISD::FADD, MVT::v4f32, 3 }, 3153 { ISD::FADD, MVT::v8f32, 4 }, 3154 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 3155 { ISD::ADD, MVT::v4i64, 3 }, 3156 { ISD::ADD, MVT::v8i32, 5 }, 3157 { ISD::ADD, MVT::v16i16, 5 }, 3158 { ISD::ADD, MVT::v32i8, 4 }, 3159 }; 3160 3161 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3162 assert(ISD && "Invalid opcode"); 3163 3164 // Before legalizing the type, give a chance to look up illegal narrow types 3165 // in the table. 3166 // FIXME: Is there a better way to do this? 3167 EVT VT = TLI->getValueType(DL, ValTy); 3168 if (VT.isSimple()) { 3169 MVT MTy = VT.getSimpleVT(); 3170 if (ST->isSLM()) 3171 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3172 return Entry->Cost; 3173 3174 if (ST->hasAVX()) 3175 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3176 return Entry->Cost; 3177 3178 if (ST->hasSSE2()) 3179 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3180 return Entry->Cost; 3181 } 3182 3183 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3184 3185 MVT MTy = LT.second; 3186 3187 auto *ValVTy = cast<VectorType>(ValTy); 3188 3189 unsigned ArithmeticCost = 0; 3190 if (LT.first != 1 && MTy.isVector() && 3191 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3192 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3193 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3194 MTy.getVectorNumElements()); 3195 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3196 ArithmeticCost *= LT.first - 1; 3197 } 3198 3199 if (ST->isSLM()) 3200 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3201 return ArithmeticCost + Entry->Cost; 3202 3203 if (ST->hasAVX()) 3204 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3205 return ArithmeticCost + Entry->Cost; 3206 3207 if (ST->hasSSE2()) 3208 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3209 return ArithmeticCost + Entry->Cost; 3210 3211 // FIXME: These assume a naive kshift+binop lowering, which is probably 3212 // conservative in most cases. 3213 static const CostTblEntry AVX512BoolReduction[] = { 3214 { ISD::AND, MVT::v2i1, 3 }, 3215 { ISD::AND, MVT::v4i1, 5 }, 3216 { ISD::AND, MVT::v8i1, 7 }, 3217 { ISD::AND, MVT::v16i1, 9 }, 3218 { ISD::AND, MVT::v32i1, 11 }, 3219 { ISD::AND, MVT::v64i1, 13 }, 3220 { ISD::OR, MVT::v2i1, 3 }, 3221 { ISD::OR, MVT::v4i1, 5 }, 3222 { ISD::OR, MVT::v8i1, 7 }, 3223 { ISD::OR, MVT::v16i1, 9 }, 3224 { ISD::OR, MVT::v32i1, 11 }, 3225 { ISD::OR, MVT::v64i1, 13 }, 3226 }; 3227 3228 static const CostTblEntry AVX2BoolReduction[] = { 3229 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 3230 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 3231 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 3232 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 3233 }; 3234 3235 static const CostTblEntry AVX1BoolReduction[] = { 3236 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 3237 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 3238 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3239 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3240 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 3241 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 3242 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3243 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3244 }; 3245 3246 static const CostTblEntry SSE2BoolReduction[] = { 3247 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 3248 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 3249 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 3250 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 3251 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 3252 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 3253 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 3254 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 3255 }; 3256 3257 // Handle bool allof/anyof patterns. 3258 if (ValVTy->getElementType()->isIntegerTy(1)) { 3259 unsigned ArithmeticCost = 0; 3260 if (LT.first != 1 && MTy.isVector() && 3261 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3262 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3263 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3264 MTy.getVectorNumElements()); 3265 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3266 ArithmeticCost *= LT.first - 1; 3267 } 3268 3269 if (ST->hasAVX512()) 3270 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 3271 return ArithmeticCost + Entry->Cost; 3272 if (ST->hasAVX2()) 3273 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 3274 return ArithmeticCost + Entry->Cost; 3275 if (ST->hasAVX()) 3276 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 3277 return ArithmeticCost + Entry->Cost; 3278 if (ST->hasSSE2()) 3279 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 3280 return ArithmeticCost + Entry->Cost; 3281 3282 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise, 3283 CostKind); 3284 } 3285 3286 unsigned NumVecElts = ValVTy->getNumElements(); 3287 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 3288 3289 // Special case power of 2 reductions where the scalar type isn't changed 3290 // by type legalization. 3291 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 3292 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise, 3293 CostKind); 3294 3295 unsigned ReductionCost = 0; 3296 3297 auto *Ty = ValVTy; 3298 if (LT.first != 1 && MTy.isVector() && 3299 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3300 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3301 Ty = FixedVectorType::get(ValVTy->getElementType(), 3302 MTy.getVectorNumElements()); 3303 ReductionCost = getArithmeticInstrCost(Opcode, Ty, CostKind); 3304 ReductionCost *= LT.first - 1; 3305 NumVecElts = MTy.getVectorNumElements(); 3306 } 3307 3308 // Now handle reduction with the legal type, taking into account size changes 3309 // at each level. 3310 while (NumVecElts > 1) { 3311 // Determine the size of the remaining vector we need to reduce. 3312 unsigned Size = NumVecElts * ScalarSize; 3313 NumVecElts /= 2; 3314 // If we're reducing from 256/512 bits, use an extract_subvector. 3315 if (Size > 128) { 3316 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 3317 ReductionCost += 3318 getShuffleCost(TTI::SK_ExtractSubvector, Ty, NumVecElts, SubTy); 3319 Ty = SubTy; 3320 } else if (Size == 128) { 3321 // Reducing from 128 bits is a permute of v2f64/v2i64. 3322 FixedVectorType *ShufTy; 3323 if (ValVTy->isFloatingPointTy()) 3324 ShufTy = 3325 FixedVectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 3326 else 3327 ShufTy = 3328 FixedVectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 3329 ReductionCost += 3330 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3331 } else if (Size == 64) { 3332 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3333 FixedVectorType *ShufTy; 3334 if (ValVTy->isFloatingPointTy()) 3335 ShufTy = 3336 FixedVectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 3337 else 3338 ShufTy = 3339 FixedVectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 3340 ReductionCost += 3341 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3342 } else { 3343 // Reducing from smaller size is a shift by immediate. 3344 auto *ShiftTy = FixedVectorType::get( 3345 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 3346 ReductionCost += getArithmeticInstrCost( 3347 Instruction::LShr, ShiftTy, CostKind, 3348 TargetTransformInfo::OK_AnyValue, 3349 TargetTransformInfo::OK_UniformConstantValue, 3350 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3351 } 3352 3353 // Add the arithmetic op for this level. 3354 ReductionCost += getArithmeticInstrCost(Opcode, Ty, CostKind); 3355 } 3356 3357 // Add the final extract element to the cost. 3358 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3359 } 3360 3361 int X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, bool IsUnsigned) { 3362 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3363 3364 MVT MTy = LT.second; 3365 3366 int ISD; 3367 if (Ty->isIntOrIntVectorTy()) { 3368 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3369 } else { 3370 assert(Ty->isFPOrFPVectorTy() && 3371 "Expected float point or integer vector type."); 3372 ISD = ISD::FMINNUM; 3373 } 3374 3375 static const CostTblEntry SSE1CostTbl[] = { 3376 {ISD::FMINNUM, MVT::v4f32, 1}, 3377 }; 3378 3379 static const CostTblEntry SSE2CostTbl[] = { 3380 {ISD::FMINNUM, MVT::v2f64, 1}, 3381 {ISD::SMIN, MVT::v8i16, 1}, 3382 {ISD::UMIN, MVT::v16i8, 1}, 3383 }; 3384 3385 static const CostTblEntry SSE41CostTbl[] = { 3386 {ISD::SMIN, MVT::v4i32, 1}, 3387 {ISD::UMIN, MVT::v4i32, 1}, 3388 {ISD::UMIN, MVT::v8i16, 1}, 3389 {ISD::SMIN, MVT::v16i8, 1}, 3390 }; 3391 3392 static const CostTblEntry SSE42CostTbl[] = { 3393 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 3394 }; 3395 3396 static const CostTblEntry AVX1CostTbl[] = { 3397 {ISD::FMINNUM, MVT::v8f32, 1}, 3398 {ISD::FMINNUM, MVT::v4f64, 1}, 3399 {ISD::SMIN, MVT::v8i32, 3}, 3400 {ISD::UMIN, MVT::v8i32, 3}, 3401 {ISD::SMIN, MVT::v16i16, 3}, 3402 {ISD::UMIN, MVT::v16i16, 3}, 3403 {ISD::SMIN, MVT::v32i8, 3}, 3404 {ISD::UMIN, MVT::v32i8, 3}, 3405 }; 3406 3407 static const CostTblEntry AVX2CostTbl[] = { 3408 {ISD::SMIN, MVT::v8i32, 1}, 3409 {ISD::UMIN, MVT::v8i32, 1}, 3410 {ISD::SMIN, MVT::v16i16, 1}, 3411 {ISD::UMIN, MVT::v16i16, 1}, 3412 {ISD::SMIN, MVT::v32i8, 1}, 3413 {ISD::UMIN, MVT::v32i8, 1}, 3414 }; 3415 3416 static const CostTblEntry AVX512CostTbl[] = { 3417 {ISD::FMINNUM, MVT::v16f32, 1}, 3418 {ISD::FMINNUM, MVT::v8f64, 1}, 3419 {ISD::SMIN, MVT::v2i64, 1}, 3420 {ISD::UMIN, MVT::v2i64, 1}, 3421 {ISD::SMIN, MVT::v4i64, 1}, 3422 {ISD::UMIN, MVT::v4i64, 1}, 3423 {ISD::SMIN, MVT::v8i64, 1}, 3424 {ISD::UMIN, MVT::v8i64, 1}, 3425 {ISD::SMIN, MVT::v16i32, 1}, 3426 {ISD::UMIN, MVT::v16i32, 1}, 3427 }; 3428 3429 static const CostTblEntry AVX512BWCostTbl[] = { 3430 {ISD::SMIN, MVT::v32i16, 1}, 3431 {ISD::UMIN, MVT::v32i16, 1}, 3432 {ISD::SMIN, MVT::v64i8, 1}, 3433 {ISD::UMIN, MVT::v64i8, 1}, 3434 }; 3435 3436 // If we have a native MIN/MAX instruction for this type, use it. 3437 if (ST->hasBWI()) 3438 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3439 return LT.first * Entry->Cost; 3440 3441 if (ST->hasAVX512()) 3442 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3443 return LT.first * Entry->Cost; 3444 3445 if (ST->hasAVX2()) 3446 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3447 return LT.first * Entry->Cost; 3448 3449 if (ST->hasAVX()) 3450 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3451 return LT.first * Entry->Cost; 3452 3453 if (ST->hasSSE42()) 3454 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3455 return LT.first * Entry->Cost; 3456 3457 if (ST->hasSSE41()) 3458 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3459 return LT.first * Entry->Cost; 3460 3461 if (ST->hasSSE2()) 3462 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3463 return LT.first * Entry->Cost; 3464 3465 if (ST->hasSSE1()) 3466 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3467 return LT.first * Entry->Cost; 3468 3469 unsigned CmpOpcode; 3470 if (Ty->isFPOrFPVectorTy()) { 3471 CmpOpcode = Instruction::FCmp; 3472 } else { 3473 assert(Ty->isIntOrIntVectorTy() && 3474 "expecting floating point or integer type for min/max reduction"); 3475 CmpOpcode = Instruction::ICmp; 3476 } 3477 3478 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 3479 // Otherwise fall back to cmp+select. 3480 return getCmpSelInstrCost(CmpOpcode, Ty, CondTy, CostKind) + 3481 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, CostKind); 3482 } 3483 3484 int X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 3485 bool IsPairwise, bool IsUnsigned, 3486 TTI::TargetCostKind CostKind) { 3487 // Just use the default implementation for pair reductions. 3488 if (IsPairwise) 3489 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned, 3490 CostKind); 3491 3492 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3493 3494 MVT MTy = LT.second; 3495 3496 int ISD; 3497 if (ValTy->isIntOrIntVectorTy()) { 3498 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3499 } else { 3500 assert(ValTy->isFPOrFPVectorTy() && 3501 "Expected float point or integer vector type."); 3502 ISD = ISD::FMINNUM; 3503 } 3504 3505 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3506 // and make it as the cost. 3507 3508 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3509 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 3510 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 3511 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 3512 }; 3513 3514 static const CostTblEntry SSE41CostTblNoPairWise[] = { 3515 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 3516 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 3517 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 3518 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 3519 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 3520 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 3521 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 3522 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 3523 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 3524 {ISD::SMIN, MVT::v16i8, 6}, 3525 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 3526 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 3527 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 3528 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 3529 }; 3530 3531 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3532 {ISD::SMIN, MVT::v16i16, 6}, 3533 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 3534 {ISD::SMIN, MVT::v32i8, 8}, 3535 {ISD::UMIN, MVT::v32i8, 8}, 3536 }; 3537 3538 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 3539 {ISD::SMIN, MVT::v32i16, 8}, 3540 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 3541 {ISD::SMIN, MVT::v64i8, 10}, 3542 {ISD::UMIN, MVT::v64i8, 10}, 3543 }; 3544 3545 // Before legalizing the type, give a chance to look up illegal narrow types 3546 // in the table. 3547 // FIXME: Is there a better way to do this? 3548 EVT VT = TLI->getValueType(DL, ValTy); 3549 if (VT.isSimple()) { 3550 MVT MTy = VT.getSimpleVT(); 3551 if (ST->hasBWI()) 3552 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3553 return Entry->Cost; 3554 3555 if (ST->hasAVX()) 3556 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3557 return Entry->Cost; 3558 3559 if (ST->hasSSE41()) 3560 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3561 return Entry->Cost; 3562 3563 if (ST->hasSSE2()) 3564 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3565 return Entry->Cost; 3566 } 3567 3568 auto *ValVTy = cast<VectorType>(ValTy); 3569 unsigned NumVecElts = ValVTy->getNumElements(); 3570 3571 auto *Ty = ValVTy; 3572 unsigned MinMaxCost = 0; 3573 if (LT.first != 1 && MTy.isVector() && 3574 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3575 // Type needs to be split. We need LT.first - 1 operations ops. 3576 Ty = FixedVectorType::get(ValVTy->getElementType(), 3577 MTy.getVectorNumElements()); 3578 auto *SubCondTy = FixedVectorType::get(CondTy->getElementType(), 3579 MTy.getVectorNumElements()); 3580 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3581 MinMaxCost *= LT.first - 1; 3582 NumVecElts = MTy.getVectorNumElements(); 3583 } 3584 3585 if (ST->hasBWI()) 3586 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3587 return MinMaxCost + Entry->Cost; 3588 3589 if (ST->hasAVX()) 3590 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3591 return MinMaxCost + Entry->Cost; 3592 3593 if (ST->hasSSE41()) 3594 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3595 return MinMaxCost + Entry->Cost; 3596 3597 if (ST->hasSSE2()) 3598 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3599 return MinMaxCost + Entry->Cost; 3600 3601 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 3602 3603 // Special case power of 2 reductions where the scalar type isn't changed 3604 // by type legalization. 3605 if (!isPowerOf2_32(ValVTy->getNumElements()) || 3606 ScalarSize != MTy.getScalarSizeInBits()) 3607 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned, 3608 CostKind); 3609 3610 // Now handle reduction with the legal type, taking into account size changes 3611 // at each level. 3612 while (NumVecElts > 1) { 3613 // Determine the size of the remaining vector we need to reduce. 3614 unsigned Size = NumVecElts * ScalarSize; 3615 NumVecElts /= 2; 3616 // If we're reducing from 256/512 bits, use an extract_subvector. 3617 if (Size > 128) { 3618 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 3619 MinMaxCost += 3620 getShuffleCost(TTI::SK_ExtractSubvector, Ty, NumVecElts, SubTy); 3621 Ty = SubTy; 3622 } else if (Size == 128) { 3623 // Reducing from 128 bits is a permute of v2f64/v2i64. 3624 VectorType *ShufTy; 3625 if (ValTy->isFloatingPointTy()) 3626 ShufTy = 3627 FixedVectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 3628 else 3629 ShufTy = FixedVectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 3630 MinMaxCost += 3631 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3632 } else if (Size == 64) { 3633 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3634 FixedVectorType *ShufTy; 3635 if (ValTy->isFloatingPointTy()) 3636 ShufTy = FixedVectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 3637 else 3638 ShufTy = FixedVectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 3639 MinMaxCost += 3640 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3641 } else { 3642 // Reducing from smaller size is a shift by immediate. 3643 auto *ShiftTy = FixedVectorType::get( 3644 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 3645 MinMaxCost += getArithmeticInstrCost( 3646 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, 3647 TargetTransformInfo::OK_AnyValue, 3648 TargetTransformInfo::OK_UniformConstantValue, 3649 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3650 } 3651 3652 // Add the arithmetic op for this level. 3653 auto *SubCondTy = 3654 FixedVectorType::get(CondTy->getElementType(), Ty->getNumElements()); 3655 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3656 } 3657 3658 // Add the final extract element to the cost. 3659 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3660 } 3661 3662 /// Calculate the cost of materializing a 64-bit value. This helper 3663 /// method might only calculate a fraction of a larger immediate. Therefore it 3664 /// is valid to return a cost of ZERO. 3665 int X86TTIImpl::getIntImmCost(int64_t Val) { 3666 if (Val == 0) 3667 return TTI::TCC_Free; 3668 3669 if (isInt<32>(Val)) 3670 return TTI::TCC_Basic; 3671 3672 return 2 * TTI::TCC_Basic; 3673 } 3674 3675 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 3676 TTI::TargetCostKind CostKind) { 3677 assert(Ty->isIntegerTy()); 3678 3679 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3680 if (BitSize == 0) 3681 return ~0U; 3682 3683 // Never hoist constants larger than 128bit, because this might lead to 3684 // incorrect code generation or assertions in codegen. 3685 // Fixme: Create a cost model for types larger than i128 once the codegen 3686 // issues have been fixed. 3687 if (BitSize > 128) 3688 return TTI::TCC_Free; 3689 3690 if (Imm == 0) 3691 return TTI::TCC_Free; 3692 3693 // Sign-extend all constants to a multiple of 64-bit. 3694 APInt ImmVal = Imm; 3695 if (BitSize % 64 != 0) 3696 ImmVal = Imm.sext(alignTo(BitSize, 64)); 3697 3698 // Split the constant into 64-bit chunks and calculate the cost for each 3699 // chunk. 3700 int Cost = 0; 3701 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 3702 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 3703 int64_t Val = Tmp.getSExtValue(); 3704 Cost += getIntImmCost(Val); 3705 } 3706 // We need at least one instruction to materialize the constant. 3707 return std::max(1, Cost); 3708 } 3709 3710 int X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, 3711 Type *Ty, TTI::TargetCostKind CostKind) { 3712 assert(Ty->isIntegerTy()); 3713 3714 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3715 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3716 // here, so that constant hoisting will ignore this constant. 3717 if (BitSize == 0) 3718 return TTI::TCC_Free; 3719 3720 unsigned ImmIdx = ~0U; 3721 switch (Opcode) { 3722 default: 3723 return TTI::TCC_Free; 3724 case Instruction::GetElementPtr: 3725 // Always hoist the base address of a GetElementPtr. This prevents the 3726 // creation of new constants for every base constant that gets constant 3727 // folded with the offset. 3728 if (Idx == 0) 3729 return 2 * TTI::TCC_Basic; 3730 return TTI::TCC_Free; 3731 case Instruction::Store: 3732 ImmIdx = 0; 3733 break; 3734 case Instruction::ICmp: 3735 // This is an imperfect hack to prevent constant hoisting of 3736 // compares that might be trying to check if a 64-bit value fits in 3737 // 32-bits. The backend can optimize these cases using a right shift by 32. 3738 // Ideally we would check the compare predicate here. There also other 3739 // similar immediates the backend can use shifts for. 3740 if (Idx == 1 && Imm.getBitWidth() == 64) { 3741 uint64_t ImmVal = Imm.getZExtValue(); 3742 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 3743 return TTI::TCC_Free; 3744 } 3745 ImmIdx = 1; 3746 break; 3747 case Instruction::And: 3748 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 3749 // by using a 32-bit operation with implicit zero extension. Detect such 3750 // immediates here as the normal path expects bit 31 to be sign extended. 3751 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 3752 return TTI::TCC_Free; 3753 ImmIdx = 1; 3754 break; 3755 case Instruction::Add: 3756 case Instruction::Sub: 3757 // For add/sub, we can use the opposite instruction for INT32_MIN. 3758 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 3759 return TTI::TCC_Free; 3760 ImmIdx = 1; 3761 break; 3762 case Instruction::UDiv: 3763 case Instruction::SDiv: 3764 case Instruction::URem: 3765 case Instruction::SRem: 3766 // Division by constant is typically expanded later into a different 3767 // instruction sequence. This completely changes the constants. 3768 // Report them as "free" to stop ConstantHoist from marking them as opaque. 3769 return TTI::TCC_Free; 3770 case Instruction::Mul: 3771 case Instruction::Or: 3772 case Instruction::Xor: 3773 ImmIdx = 1; 3774 break; 3775 // Always return TCC_Free for the shift value of a shift instruction. 3776 case Instruction::Shl: 3777 case Instruction::LShr: 3778 case Instruction::AShr: 3779 if (Idx == 1) 3780 return TTI::TCC_Free; 3781 break; 3782 case Instruction::Trunc: 3783 case Instruction::ZExt: 3784 case Instruction::SExt: 3785 case Instruction::IntToPtr: 3786 case Instruction::PtrToInt: 3787 case Instruction::BitCast: 3788 case Instruction::PHI: 3789 case Instruction::Call: 3790 case Instruction::Select: 3791 case Instruction::Ret: 3792 case Instruction::Load: 3793 break; 3794 } 3795 3796 if (Idx == ImmIdx) { 3797 int NumConstants = divideCeil(BitSize, 64); 3798 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 3799 return (Cost <= NumConstants * TTI::TCC_Basic) 3800 ? static_cast<int>(TTI::TCC_Free) 3801 : Cost; 3802 } 3803 3804 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 3805 } 3806 3807 int X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 3808 const APInt &Imm, Type *Ty, 3809 TTI::TargetCostKind CostKind) { 3810 assert(Ty->isIntegerTy()); 3811 3812 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3813 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3814 // here, so that constant hoisting will ignore this constant. 3815 if (BitSize == 0) 3816 return TTI::TCC_Free; 3817 3818 switch (IID) { 3819 default: 3820 return TTI::TCC_Free; 3821 case Intrinsic::sadd_with_overflow: 3822 case Intrinsic::uadd_with_overflow: 3823 case Intrinsic::ssub_with_overflow: 3824 case Intrinsic::usub_with_overflow: 3825 case Intrinsic::smul_with_overflow: 3826 case Intrinsic::umul_with_overflow: 3827 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 3828 return TTI::TCC_Free; 3829 break; 3830 case Intrinsic::experimental_stackmap: 3831 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 3832 return TTI::TCC_Free; 3833 break; 3834 case Intrinsic::experimental_patchpoint_void: 3835 case Intrinsic::experimental_patchpoint_i64: 3836 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 3837 return TTI::TCC_Free; 3838 break; 3839 } 3840 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 3841 } 3842 3843 unsigned 3844 X86TTIImpl::getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind) { 3845 if (CostKind != TTI::TCK_RecipThroughput) 3846 return Opcode == Instruction::PHI ? 0 : 1; 3847 // Branches are assumed to be predicted. 3848 return CostKind == TTI::TCK_RecipThroughput ? 0 : 1; 3849 } 3850 3851 // Return an average cost of Gather / Scatter instruction, maybe improved later 3852 int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, Value *Ptr, 3853 unsigned Alignment, unsigned AddressSpace) { 3854 3855 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 3856 unsigned VF = cast<VectorType>(SrcVTy)->getNumElements(); 3857 3858 // Try to reduce index size from 64 bit (default for GEP) 3859 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 3860 // operation will use 16 x 64 indices which do not fit in a zmm and needs 3861 // to split. Also check that the base pointer is the same for all lanes, 3862 // and that there's at most one variable index. 3863 auto getIndexSizeInBits = [](Value *Ptr, const DataLayout& DL) { 3864 unsigned IndexSize = DL.getPointerSizeInBits(); 3865 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 3866 if (IndexSize < 64 || !GEP) 3867 return IndexSize; 3868 3869 unsigned NumOfVarIndices = 0; 3870 Value *Ptrs = GEP->getPointerOperand(); 3871 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 3872 return IndexSize; 3873 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 3874 if (isa<Constant>(GEP->getOperand(i))) 3875 continue; 3876 Type *IndxTy = GEP->getOperand(i)->getType(); 3877 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 3878 IndxTy = IndexVTy->getElementType(); 3879 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 3880 !isa<SExtInst>(GEP->getOperand(i))) || 3881 ++NumOfVarIndices > 1) 3882 return IndexSize; // 64 3883 } 3884 return (unsigned)32; 3885 }; 3886 3887 3888 // Trying to reduce IndexSize to 32 bits for vector 16. 3889 // By default the IndexSize is equal to pointer size. 3890 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 3891 ? getIndexSizeInBits(Ptr, DL) 3892 : DL.getPointerSizeInBits(); 3893 3894 auto *IndexVTy = FixedVectorType::get( 3895 IntegerType::get(SrcVTy->getContext(), IndexSize), VF); 3896 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy); 3897 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3898 int SplitFactor = std::max(IdxsLT.first, SrcLT.first); 3899 if (SplitFactor > 1) { 3900 // Handle splitting of vector of pointers 3901 auto *SplitSrcTy = 3902 FixedVectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 3903 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 3904 AddressSpace); 3905 } 3906 3907 // The gather / scatter cost is given by Intel architects. It is a rough 3908 // number since we are looking at one instruction in a time. 3909 const int GSOverhead = (Opcode == Instruction::Load) 3910 ? ST->getGatherOverhead() 3911 : ST->getScatterOverhead(); 3912 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3913 MaybeAlign(Alignment), AddressSpace, 3914 TTI::TCK_RecipThroughput); 3915 } 3916 3917 /// Return the cost of full scalarization of gather / scatter operation. 3918 /// 3919 /// Opcode - Load or Store instruction. 3920 /// SrcVTy - The type of the data vector that should be gathered or scattered. 3921 /// VariableMask - The mask is non-constant at compile time. 3922 /// Alignment - Alignment for one element. 3923 /// AddressSpace - pointer[s] address space. 3924 /// 3925 int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 3926 bool VariableMask, unsigned Alignment, 3927 unsigned AddressSpace) { 3928 unsigned VF = cast<VectorType>(SrcVTy)->getNumElements(); 3929 APInt DemandedElts = APInt::getAllOnesValue(VF); 3930 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 3931 3932 int MaskUnpackCost = 0; 3933 if (VariableMask) { 3934 auto *MaskTy = 3935 FixedVectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 3936 MaskUnpackCost = 3937 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 3938 int ScalarCompareCost = 3939 getCmpSelInstrCost(Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), 3940 nullptr, CostKind); 3941 int BranchCost = getCFInstrCost(Instruction::Br, CostKind); 3942 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 3943 } 3944 3945 // The cost of the scalar loads/stores. 3946 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3947 MaybeAlign(Alignment), AddressSpace, 3948 CostKind); 3949 3950 int InsertExtractCost = 0; 3951 if (Opcode == Instruction::Load) 3952 for (unsigned i = 0; i < VF; ++i) 3953 // Add the cost of inserting each scalar load into the vector 3954 InsertExtractCost += 3955 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 3956 else 3957 for (unsigned i = 0; i < VF; ++i) 3958 // Add the cost of extracting each element out of the data vector 3959 InsertExtractCost += 3960 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 3961 3962 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 3963 } 3964 3965 /// Calculate the cost of Gather / Scatter operation 3966 int X86TTIImpl::getGatherScatterOpCost( 3967 unsigned Opcode, Type *SrcVTy, Value *Ptr, bool VariableMask, 3968 unsigned Alignment, TTI::TargetCostKind CostKind, 3969 const Instruction *I = nullptr) { 3970 3971 if (CostKind != TTI::TCK_RecipThroughput) 3972 return 1; 3973 3974 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 3975 unsigned VF = cast<VectorType>(SrcVTy)->getNumElements(); 3976 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 3977 if (!PtrTy && Ptr->getType()->isVectorTy()) 3978 PtrTy = dyn_cast<PointerType>( 3979 cast<VectorType>(Ptr->getType())->getElementType()); 3980 assert(PtrTy && "Unexpected type for Ptr argument"); 3981 unsigned AddressSpace = PtrTy->getAddressSpace(); 3982 3983 bool Scalarize = false; 3984 if ((Opcode == Instruction::Load && 3985 !isLegalMaskedGather(SrcVTy, MaybeAlign(Alignment))) || 3986 (Opcode == Instruction::Store && 3987 !isLegalMaskedScatter(SrcVTy, MaybeAlign(Alignment)))) 3988 Scalarize = true; 3989 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 3990 // Vector-4 of gather/scatter instruction does not exist on KNL. 3991 // We can extend it to 8 elements, but zeroing upper bits of 3992 // the mask vector will add more instructions. Right now we give the scalar 3993 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 3994 // is better in the VariableMask case. 3995 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 3996 Scalarize = true; 3997 3998 if (Scalarize) 3999 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 4000 AddressSpace); 4001 4002 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 4003 } 4004 4005 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 4006 TargetTransformInfo::LSRCost &C2) { 4007 // X86 specific here are "instruction number 1st priority". 4008 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 4009 C1.NumIVMuls, C1.NumBaseAdds, 4010 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 4011 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 4012 C2.NumIVMuls, C2.NumBaseAdds, 4013 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 4014 } 4015 4016 bool X86TTIImpl::canMacroFuseCmp() { 4017 return ST->hasMacroFusion() || ST->hasBranchFusion(); 4018 } 4019 4020 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, MaybeAlign Alignment) { 4021 if (!ST->hasAVX()) 4022 return false; 4023 4024 // The backend can't handle a single element vector. 4025 if (isa<VectorType>(DataTy) && 4026 cast<VectorType>(DataTy)->getNumElements() == 1) 4027 return false; 4028 Type *ScalarTy = DataTy->getScalarType(); 4029 4030 if (ScalarTy->isPointerTy()) 4031 return true; 4032 4033 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4034 return true; 4035 4036 if (!ScalarTy->isIntegerTy()) 4037 return false; 4038 4039 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4040 return IntWidth == 32 || IntWidth == 64 || 4041 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 4042 } 4043 4044 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, MaybeAlign Alignment) { 4045 return isLegalMaskedLoad(DataType, Alignment); 4046 } 4047 4048 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 4049 unsigned DataSize = DL.getTypeStoreSize(DataType); 4050 // The only supported nontemporal loads are for aligned vectors of 16 or 32 4051 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 4052 // (the equivalent stores only require AVX). 4053 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 4054 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 4055 4056 return false; 4057 } 4058 4059 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 4060 unsigned DataSize = DL.getTypeStoreSize(DataType); 4061 4062 // SSE4A supports nontemporal stores of float and double at arbitrary 4063 // alignment. 4064 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 4065 return true; 4066 4067 // Besides the SSE4A subtarget exception above, only aligned stores are 4068 // available nontemporaly on any other subtarget. And only stores with a size 4069 // of 4..32 bytes (powers of 2, only) are permitted. 4070 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 4071 !isPowerOf2_32(DataSize)) 4072 return false; 4073 4074 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 4075 // loads require AVX2). 4076 if (DataSize == 32) 4077 return ST->hasAVX(); 4078 else if (DataSize == 16) 4079 return ST->hasSSE1(); 4080 return true; 4081 } 4082 4083 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 4084 if (!isa<VectorType>(DataTy)) 4085 return false; 4086 4087 if (!ST->hasAVX512()) 4088 return false; 4089 4090 // The backend can't handle a single element vector. 4091 if (cast<VectorType>(DataTy)->getNumElements() == 1) 4092 return false; 4093 4094 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 4095 4096 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4097 return true; 4098 4099 if (!ScalarTy->isIntegerTy()) 4100 return false; 4101 4102 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4103 return IntWidth == 32 || IntWidth == 64 || 4104 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 4105 } 4106 4107 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 4108 return isLegalMaskedExpandLoad(DataTy); 4109 } 4110 4111 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, MaybeAlign Alignment) { 4112 // Some CPUs have better gather performance than others. 4113 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 4114 // enable gather with a -march. 4115 if (!(ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()))) 4116 return false; 4117 4118 // This function is called now in two cases: from the Loop Vectorizer 4119 // and from the Scalarizer. 4120 // When the Loop Vectorizer asks about legality of the feature, 4121 // the vectorization factor is not calculated yet. The Loop Vectorizer 4122 // sends a scalar type and the decision is based on the width of the 4123 // scalar element. 4124 // Later on, the cost model will estimate usage this intrinsic based on 4125 // the vector type. 4126 // The Scalarizer asks again about legality. It sends a vector type. 4127 // In this case we can reject non-power-of-2 vectors. 4128 // We also reject single element vectors as the type legalizer can't 4129 // scalarize it. 4130 if (auto *DataVTy = dyn_cast<VectorType>(DataTy)) { 4131 unsigned NumElts = DataVTy->getNumElements(); 4132 if (NumElts == 1 || !isPowerOf2_32(NumElts)) 4133 return false; 4134 } 4135 Type *ScalarTy = DataTy->getScalarType(); 4136 if (ScalarTy->isPointerTy()) 4137 return true; 4138 4139 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4140 return true; 4141 4142 if (!ScalarTy->isIntegerTy()) 4143 return false; 4144 4145 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4146 return IntWidth == 32 || IntWidth == 64; 4147 } 4148 4149 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, MaybeAlign Alignment) { 4150 // AVX2 doesn't support scatter 4151 if (!ST->hasAVX512()) 4152 return false; 4153 return isLegalMaskedGather(DataType, Alignment); 4154 } 4155 4156 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 4157 EVT VT = TLI->getValueType(DL, DataType); 4158 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 4159 } 4160 4161 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 4162 return false; 4163 } 4164 4165 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 4166 const Function *Callee) const { 4167 const TargetMachine &TM = getTLI()->getTargetMachine(); 4168 4169 // Work this as a subsetting of subtarget features. 4170 const FeatureBitset &CallerBits = 4171 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 4172 const FeatureBitset &CalleeBits = 4173 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 4174 4175 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 4176 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 4177 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 4178 } 4179 4180 bool X86TTIImpl::areFunctionArgsABICompatible( 4181 const Function *Caller, const Function *Callee, 4182 SmallPtrSetImpl<Argument *> &Args) const { 4183 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args)) 4184 return false; 4185 4186 // If we get here, we know the target features match. If one function 4187 // considers 512-bit vectors legal and the other does not, consider them 4188 // incompatible. 4189 const TargetMachine &TM = getTLI()->getTargetMachine(); 4190 4191 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 4192 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs()) 4193 return true; 4194 4195 // Consider the arguments compatible if they aren't vectors or aggregates. 4196 // FIXME: Look at the size of vectors. 4197 // FIXME: Look at the element types of aggregates to see if there are vectors. 4198 // FIXME: The API of this function seems intended to allow arguments 4199 // to be removed from the set, but the caller doesn't check if the set 4200 // becomes empty so that may not work in practice. 4201 return llvm::none_of(Args, [](Argument *A) { 4202 auto *EltTy = cast<PointerType>(A->getType())->getElementType(); 4203 return EltTy->isVectorTy() || EltTy->isAggregateType(); 4204 }); 4205 } 4206 4207 X86TTIImpl::TTI::MemCmpExpansionOptions 4208 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 4209 TTI::MemCmpExpansionOptions Options; 4210 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 4211 Options.NumLoadsPerBlock = 2; 4212 // All GPR and vector loads can be unaligned. 4213 Options.AllowOverlappingLoads = true; 4214 if (IsZeroCmp) { 4215 // Only enable vector loads for equality comparison. Right now the vector 4216 // version is not as fast for three way compare (see #33329). 4217 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 4218 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 4219 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 4220 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 4221 } 4222 if (ST->is64Bit()) { 4223 Options.LoadSizes.push_back(8); 4224 } 4225 Options.LoadSizes.push_back(4); 4226 Options.LoadSizes.push_back(2); 4227 Options.LoadSizes.push_back(1); 4228 return Options; 4229 } 4230 4231 bool X86TTIImpl::enableInterleavedAccessVectorization() { 4232 // TODO: We expect this to be beneficial regardless of arch, 4233 // but there are currently some unexplained performance artifacts on Atom. 4234 // As a temporary solution, disable on Atom. 4235 return !(ST->isAtom()); 4236 } 4237 4238 // Get estimation for interleaved load/store operations for AVX2. 4239 // \p Factor is the interleaved-access factor (stride) - number of 4240 // (interleaved) elements in the group. 4241 // \p Indices contains the indices for a strided load: when the 4242 // interleaved load has gaps they indicate which elements are used. 4243 // If Indices is empty (or if the number of indices is equal to the size 4244 // of the interleaved-access as given in \p Factor) the access has no gaps. 4245 // 4246 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 4247 // computing the cost using a generic formula as a function of generic 4248 // shuffles. We therefore use a lookup table instead, filled according to 4249 // the instruction sequences that codegen currently generates. 4250 int X86TTIImpl::getInterleavedMemoryOpCostAVX2(unsigned Opcode, Type *VecTy, 4251 unsigned Factor, 4252 ArrayRef<unsigned> Indices, 4253 unsigned Alignment, 4254 unsigned AddressSpace, 4255 TTI::TargetCostKind CostKind, 4256 bool UseMaskForCond, 4257 bool UseMaskForGaps) { 4258 4259 if (UseMaskForCond || UseMaskForGaps) 4260 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4261 Alignment, AddressSpace, CostKind, 4262 UseMaskForCond, UseMaskForGaps); 4263 4264 // We currently Support only fully-interleaved groups, with no gaps. 4265 // TODO: Support also strided loads (interleaved-groups with gaps). 4266 if (Indices.size() && Indices.size() != Factor) 4267 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4268 Alignment, AddressSpace, 4269 CostKind); 4270 4271 // VecTy for interleave memop is <VF*Factor x Elt>. 4272 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4273 // VecTy = <12 x i32>. 4274 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4275 4276 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 4277 // the VF=2, while v2i128 is an unsupported MVT vector type 4278 // (see MachineValueType.h::getVectorVT()). 4279 if (!LegalVT.isVector()) 4280 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4281 Alignment, AddressSpace, 4282 CostKind); 4283 4284 unsigned VF = cast<VectorType>(VecTy)->getNumElements() / Factor; 4285 Type *ScalarTy = cast<VectorType>(VecTy)->getElementType(); 4286 4287 // Calculate the number of memory operations (NumOfMemOps), required 4288 // for load/store the VecTy. 4289 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4290 unsigned LegalVTSize = LegalVT.getStoreSize(); 4291 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4292 4293 // Get the cost of one memory operation. 4294 auto *SingleMemOpTy = 4295 FixedVectorType::get(cast<VectorType>(VecTy)->getElementType(), 4296 LegalVT.getVectorNumElements()); 4297 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 4298 MaybeAlign(Alignment), AddressSpace, 4299 CostKind); 4300 4301 auto *VT = FixedVectorType::get(ScalarTy, VF); 4302 EVT ETy = TLI->getValueType(DL, VT); 4303 if (!ETy.isSimple()) 4304 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4305 Alignment, AddressSpace, 4306 CostKind); 4307 4308 // TODO: Complete for other data-types and strides. 4309 // Each combination of Stride, ElementTy and VF results in a different 4310 // sequence; The cost tables are therefore accessed with: 4311 // Factor (stride) and VectorType=VFxElemType. 4312 // The Cost accounts only for the shuffle sequence; 4313 // The cost of the loads/stores is accounted for separately. 4314 // 4315 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 4316 { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64 4317 { 2, MVT::v4f64, 6 }, //(load 8f64 and) deinterleave into 2 x 4f64 4318 4319 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8 4320 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8 4321 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8 4322 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8 4323 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8 4324 { 3, MVT::v8f32, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32 4325 4326 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8 4327 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8 4328 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8 4329 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8 4330 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8 4331 4332 { 8, MVT::v8f32, 40 } //(load 64f32 and)deinterleave into 8 x 8f32 4333 }; 4334 4335 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 4336 { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store) 4337 { 2, MVT::v4f64, 6 }, //interleave into 2 x 4f64 into 8f64 (and store) 4338 4339 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store) 4340 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store) 4341 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store) 4342 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store) 4343 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store) 4344 4345 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store) 4346 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store) 4347 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store) 4348 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store) 4349 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store) 4350 }; 4351 4352 if (Opcode == Instruction::Load) { 4353 if (const auto *Entry = 4354 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 4355 return NumOfMemOps * MemOpCost + Entry->Cost; 4356 } else { 4357 assert(Opcode == Instruction::Store && 4358 "Expected Store Instruction at this point"); 4359 if (const auto *Entry = 4360 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 4361 return NumOfMemOps * MemOpCost + Entry->Cost; 4362 } 4363 4364 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4365 Alignment, AddressSpace, CostKind); 4366 } 4367 4368 // Get estimation for interleaved load/store operations and strided load. 4369 // \p Indices contains indices for strided load. 4370 // \p Factor - the factor of interleaving. 4371 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 4372 int X86TTIImpl::getInterleavedMemoryOpCostAVX512(unsigned Opcode, Type *VecTy, 4373 unsigned Factor, 4374 ArrayRef<unsigned> Indices, 4375 unsigned Alignment, 4376 unsigned AddressSpace, 4377 TTI::TargetCostKind CostKind, 4378 bool UseMaskForCond, 4379 bool UseMaskForGaps) { 4380 4381 if (UseMaskForCond || UseMaskForGaps) 4382 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4383 Alignment, AddressSpace, CostKind, 4384 UseMaskForCond, UseMaskForGaps); 4385 4386 // VecTy for interleave memop is <VF*Factor x Elt>. 4387 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4388 // VecTy = <12 x i32>. 4389 4390 // Calculate the number of memory operations (NumOfMemOps), required 4391 // for load/store the VecTy. 4392 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4393 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4394 unsigned LegalVTSize = LegalVT.getStoreSize(); 4395 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4396 4397 // Get the cost of one memory operation. 4398 auto *SingleMemOpTy = 4399 FixedVectorType::get(cast<VectorType>(VecTy)->getElementType(), 4400 LegalVT.getVectorNumElements()); 4401 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 4402 MaybeAlign(Alignment), AddressSpace, 4403 CostKind); 4404 4405 unsigned VF = cast<VectorType>(VecTy)->getNumElements() / Factor; 4406 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 4407 4408 if (Opcode == Instruction::Load) { 4409 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 4410 // contain the cost of the optimized shuffle sequence that the 4411 // X86InterleavedAccess pass will generate. 4412 // The cost of loads and stores are computed separately from the table. 4413 4414 // X86InterleavedAccess support only the following interleaved-access group. 4415 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 4416 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 4417 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 4418 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 4419 }; 4420 4421 if (const auto *Entry = 4422 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 4423 return NumOfMemOps * MemOpCost + Entry->Cost; 4424 //If an entry does not exist, fallback to the default implementation. 4425 4426 // Kind of shuffle depends on number of loaded values. 4427 // If we load the entire data in one register, we can use a 1-src shuffle. 4428 // Otherwise, we'll merge 2 sources in each operation. 4429 TTI::ShuffleKind ShuffleKind = 4430 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 4431 4432 unsigned ShuffleCost = 4433 getShuffleCost(ShuffleKind, SingleMemOpTy, 0, nullptr); 4434 4435 unsigned NumOfLoadsInInterleaveGrp = 4436 Indices.size() ? Indices.size() : Factor; 4437 auto *ResultTy = FixedVectorType::get( 4438 cast<VectorType>(VecTy)->getElementType(), 4439 cast<VectorType>(VecTy)->getNumElements() / Factor); 4440 unsigned NumOfResults = 4441 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 4442 NumOfLoadsInInterleaveGrp; 4443 4444 // About a half of the loads may be folded in shuffles when we have only 4445 // one result. If we have more than one result, we do not fold loads at all. 4446 unsigned NumOfUnfoldedLoads = 4447 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 4448 4449 // Get a number of shuffle operations per result. 4450 unsigned NumOfShufflesPerResult = 4451 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 4452 4453 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4454 // When we have more than one destination, we need additional instructions 4455 // to keep sources. 4456 unsigned NumOfMoves = 0; 4457 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 4458 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 4459 4460 int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 4461 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 4462 4463 return Cost; 4464 } 4465 4466 // Store. 4467 assert(Opcode == Instruction::Store && 4468 "Expected Store Instruction at this point"); 4469 // X86InterleavedAccess support only the following interleaved-access group. 4470 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 4471 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 4472 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 4473 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 4474 4475 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 4476 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 4477 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 4478 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 4479 }; 4480 4481 if (const auto *Entry = 4482 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 4483 return NumOfMemOps * MemOpCost + Entry->Cost; 4484 //If an entry does not exist, fallback to the default implementation. 4485 4486 // There is no strided stores meanwhile. And store can't be folded in 4487 // shuffle. 4488 unsigned NumOfSources = Factor; // The number of values to be merged. 4489 unsigned ShuffleCost = 4490 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, 0, nullptr); 4491 unsigned NumOfShufflesPerStore = NumOfSources - 1; 4492 4493 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4494 // We need additional instructions to keep sources. 4495 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 4496 int Cost = NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 4497 NumOfMoves; 4498 return Cost; 4499 } 4500 4501 int X86TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, 4502 unsigned Factor, 4503 ArrayRef<unsigned> Indices, 4504 unsigned Alignment, 4505 unsigned AddressSpace, 4506 TTI::TargetCostKind CostKind, 4507 bool UseMaskForCond, 4508 bool UseMaskForGaps) { 4509 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 4510 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 4511 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 4512 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 4513 return true; 4514 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 4515 return HasBW; 4516 return false; 4517 }; 4518 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 4519 return getInterleavedMemoryOpCostAVX512(Opcode, VecTy, Factor, Indices, 4520 Alignment, AddressSpace, CostKind, 4521 UseMaskForCond, UseMaskForGaps); 4522 if (ST->hasAVX2()) 4523 return getInterleavedMemoryOpCostAVX2(Opcode, VecTy, Factor, Indices, 4524 Alignment, AddressSpace, CostKind, 4525 UseMaskForCond, UseMaskForGaps); 4526 4527 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4528 Alignment, AddressSpace, CostKind, 4529 UseMaskForCond, UseMaskForGaps); 4530 } 4531