1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // X86 cost model. 56 // 57 //===----------------------------------------------------------------------===// 58 59 TargetTransformInfo::PopcntSupportKind 60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 61 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 62 // TODO: Currently the __builtin_popcount() implementation using SSE3 63 // instructions is inefficient. Once the problem is fixed, we should 64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 66 } 67 68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 69 TargetTransformInfo::CacheLevel Level) const { 70 switch (Level) { 71 case TargetTransformInfo::CacheLevel::L1D: 72 // - Penryn 73 // - Nehalem 74 // - Westmere 75 // - Sandy Bridge 76 // - Ivy Bridge 77 // - Haswell 78 // - Broadwell 79 // - Skylake 80 // - Kabylake 81 return 32 * 1024; // 32 KByte 82 case TargetTransformInfo::CacheLevel::L2D: 83 // - Penryn 84 // - Nehalem 85 // - Westmere 86 // - Sandy Bridge 87 // - Ivy Bridge 88 // - Haswell 89 // - Broadwell 90 // - Skylake 91 // - Kabylake 92 return 256 * 1024; // 256 KByte 93 } 94 95 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 96 } 97 98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 99 TargetTransformInfo::CacheLevel Level) const { 100 // - Penryn 101 // - Nehalem 102 // - Westmere 103 // - Sandy Bridge 104 // - Ivy Bridge 105 // - Haswell 106 // - Broadwell 107 // - Skylake 108 // - Kabylake 109 switch (Level) { 110 case TargetTransformInfo::CacheLevel::L1D: 111 LLVM_FALLTHROUGH; 112 case TargetTransformInfo::CacheLevel::L2D: 113 return 8; 114 } 115 116 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 117 } 118 119 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 120 bool Vector = (ClassID == 1); 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const { 133 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 134 if (Vector) { 135 if (ST->hasAVX512() && PreferVectorWidth >= 512) 136 return 512; 137 if (ST->hasAVX() && PreferVectorWidth >= 256) 138 return 256; 139 if (ST->hasSSE1() && PreferVectorWidth >= 128) 140 return 128; 141 return 0; 142 } 143 144 if (ST->is64Bit()) 145 return 64; 146 147 return 32; 148 } 149 150 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 151 return getRegisterBitWidth(true); 152 } 153 154 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 155 // If the loop will not be vectorized, don't interleave the loop. 156 // Let regular unroll to unroll the loop, which saves the overflow 157 // check and memory check cost. 158 if (VF == 1) 159 return 1; 160 161 if (ST->isAtom()) 162 return 1; 163 164 // Sandybridge and Haswell have multiple execution ports and pipelined 165 // vector units. 166 if (ST->hasAVX()) 167 return 4; 168 169 return 2; 170 } 171 172 int X86TTIImpl::getArithmeticInstrCost(unsigned Opcode, Type *Ty, 173 TTI::TargetCostKind CostKind, 174 TTI::OperandValueKind Op1Info, 175 TTI::OperandValueKind Op2Info, 176 TTI::OperandValueProperties Opd1PropInfo, 177 TTI::OperandValueProperties Opd2PropInfo, 178 ArrayRef<const Value *> Args, 179 const Instruction *CxtI) { 180 // Legalize the type. 181 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 182 183 int ISD = TLI->InstructionOpcodeToISD(Opcode); 184 assert(ISD && "Invalid opcode"); 185 186 static const CostTblEntry GLMCostTable[] = { 187 { ISD::FDIV, MVT::f32, 18 }, // divss 188 { ISD::FDIV, MVT::v4f32, 35 }, // divps 189 { ISD::FDIV, MVT::f64, 33 }, // divsd 190 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 191 }; 192 193 if (ST->useGLMDivSqrtCosts()) 194 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 195 LT.second)) 196 return LT.first * Entry->Cost; 197 198 static const CostTblEntry SLMCostTable[] = { 199 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 200 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 201 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. 202 { ISD::FMUL, MVT::f64, 2 }, // mulsd 203 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 204 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 205 { ISD::FDIV, MVT::f32, 17 }, // divss 206 { ISD::FDIV, MVT::v4f32, 39 }, // divps 207 { ISD::FDIV, MVT::f64, 32 }, // divsd 208 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 209 { ISD::FADD, MVT::v2f64, 2 }, // addpd 210 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 211 // v2i64/v4i64 mul is custom lowered as a series of long: 212 // multiplies(3), shifts(3) and adds(2) 213 // slm muldq version throughput is 2 and addq throughput 4 214 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 215 // 3X4 (addq throughput) = 17 216 { ISD::MUL, MVT::v2i64, 17 }, 217 // slm addq\subq throughput is 4 218 { ISD::ADD, MVT::v2i64, 4 }, 219 { ISD::SUB, MVT::v2i64, 4 }, 220 }; 221 222 if (ST->isSLM()) { 223 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 224 // Check if the operands can be shrinked into a smaller datatype. 225 bool Op1Signed = false; 226 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 227 bool Op2Signed = false; 228 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 229 230 bool signedMode = Op1Signed | Op2Signed; 231 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 232 233 if (OpMinSize <= 7) 234 return LT.first * 3; // pmullw/sext 235 if (!signedMode && OpMinSize <= 8) 236 return LT.first * 3; // pmullw/zext 237 if (OpMinSize <= 15) 238 return LT.first * 5; // pmullw/pmulhw/pshuf 239 if (!signedMode && OpMinSize <= 16) 240 return LT.first * 5; // pmullw/pmulhw/pshuf 241 } 242 243 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 244 LT.second)) { 245 return LT.first * Entry->Cost; 246 } 247 } 248 249 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 250 ISD == ISD::UREM) && 251 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 252 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 253 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 254 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 255 // On X86, vector signed division by constants power-of-two are 256 // normally expanded to the sequence SRA + SRL + ADD + SRA. 257 // The OperandValue properties may not be the same as that of the previous 258 // operation; conservatively assume OP_None. 259 int Cost = 260 2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Op1Info, 261 Op2Info, 262 TargetTransformInfo::OP_None, 263 TargetTransformInfo::OP_None); 264 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 265 Op2Info, 266 TargetTransformInfo::OP_None, 267 TargetTransformInfo::OP_None); 268 Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind, Op1Info, 269 Op2Info, 270 TargetTransformInfo::OP_None, 271 TargetTransformInfo::OP_None); 272 273 if (ISD == ISD::SREM) { 274 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 275 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info, 276 Op2Info); 277 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info, 278 Op2Info); 279 } 280 281 return Cost; 282 } 283 284 // Vector unsigned division/remainder will be simplified to shifts/masks. 285 if (ISD == ISD::UDIV) 286 return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, 287 Op1Info, Op2Info, 288 TargetTransformInfo::OP_None, 289 TargetTransformInfo::OP_None); 290 291 else // UREM 292 return getArithmeticInstrCost(Instruction::And, Ty, CostKind, 293 Op1Info, Op2Info, 294 TargetTransformInfo::OP_None, 295 TargetTransformInfo::OP_None); 296 } 297 298 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 299 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 300 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 301 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 302 }; 303 304 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 305 ST->hasBWI()) { 306 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 307 LT.second)) 308 return LT.first * Entry->Cost; 309 } 310 311 static const CostTblEntry AVX512UniformConstCostTable[] = { 312 { ISD::SRA, MVT::v2i64, 1 }, 313 { ISD::SRA, MVT::v4i64, 1 }, 314 { ISD::SRA, MVT::v8i64, 1 }, 315 316 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 317 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 318 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 319 }; 320 321 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 322 ST->hasAVX512()) { 323 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 324 LT.second)) 325 return LT.first * Entry->Cost; 326 } 327 328 static const CostTblEntry AVX2UniformConstCostTable[] = { 329 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 330 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 331 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 332 333 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 334 }; 335 336 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 337 ST->hasAVX2()) { 338 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 339 LT.second)) 340 return LT.first * Entry->Cost; 341 } 342 343 static const CostTblEntry SSE2UniformConstCostTable[] = { 344 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 345 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 346 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 347 348 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 349 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 350 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 351 }; 352 353 // XOP has faster vXi8 shifts. 354 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 355 ST->hasSSE2() && !ST->hasXOP()) { 356 if (const auto *Entry = 357 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 358 return LT.first * Entry->Cost; 359 } 360 361 static const CostTblEntry AVX512BWConstCostTable[] = { 362 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 363 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 364 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 365 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 366 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 367 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 368 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 369 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 370 }; 371 372 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 373 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 374 ST->hasBWI()) { 375 if (const auto *Entry = 376 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 377 return LT.first * Entry->Cost; 378 } 379 380 static const CostTblEntry AVX512ConstCostTable[] = { 381 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 382 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 383 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 384 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 385 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 386 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 387 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 388 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 389 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 390 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 391 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 392 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 393 }; 394 395 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 396 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 397 ST->hasAVX512()) { 398 if (const auto *Entry = 399 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 400 return LT.first * Entry->Cost; 401 } 402 403 static const CostTblEntry AVX2ConstCostTable[] = { 404 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 405 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 406 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 407 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 408 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 409 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 410 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 411 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 412 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 413 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 414 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 415 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 416 }; 417 418 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 419 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 420 ST->hasAVX2()) { 421 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 422 return LT.first * Entry->Cost; 423 } 424 425 static const CostTblEntry SSE2ConstCostTable[] = { 426 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 427 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 428 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 429 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 430 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 431 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 432 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 433 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 434 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 435 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 436 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 437 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 438 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 439 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 440 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 441 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 442 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 443 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 444 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 445 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 446 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 447 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 448 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 449 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 450 }; 451 452 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 453 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 454 ST->hasSSE2()) { 455 // pmuldq sequence. 456 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 457 return LT.first * 32; 458 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 459 return LT.first * 38; 460 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 461 return LT.first * 15; 462 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 463 return LT.first * 20; 464 465 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 466 return LT.first * Entry->Cost; 467 } 468 469 static const CostTblEntry AVX512BWShiftCostTable[] = { 470 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 471 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 472 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 473 474 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 475 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 476 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 477 478 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 479 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 480 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 481 }; 482 483 if (ST->hasBWI()) 484 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 485 return LT.first * Entry->Cost; 486 487 static const CostTblEntry AVX2UniformCostTable[] = { 488 // Uniform splats are cheaper for the following instructions. 489 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 490 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 491 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 492 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 493 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 494 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 495 }; 496 497 if (ST->hasAVX2() && 498 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 499 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 500 if (const auto *Entry = 501 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 502 return LT.first * Entry->Cost; 503 } 504 505 static const CostTblEntry SSE2UniformCostTable[] = { 506 // Uniform splats are cheaper for the following instructions. 507 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 508 { ISD::SHL, MVT::v4i32, 1 }, // pslld 509 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 510 511 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 512 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 513 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 514 515 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 516 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 517 }; 518 519 if (ST->hasSSE2() && 520 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 521 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 522 if (const auto *Entry = 523 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 524 return LT.first * Entry->Cost; 525 } 526 527 static const CostTblEntry AVX512DQCostTable[] = { 528 { ISD::MUL, MVT::v2i64, 1 }, 529 { ISD::MUL, MVT::v4i64, 1 }, 530 { ISD::MUL, MVT::v8i64, 1 } 531 }; 532 533 // Look for AVX512DQ lowering tricks for custom cases. 534 if (ST->hasDQI()) 535 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 536 return LT.first * Entry->Cost; 537 538 static const CostTblEntry AVX512BWCostTable[] = { 539 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 540 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 541 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 542 543 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence. 544 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence. 545 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence. 546 }; 547 548 // Look for AVX512BW lowering tricks for custom cases. 549 if (ST->hasBWI()) 550 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 551 return LT.first * Entry->Cost; 552 553 static const CostTblEntry AVX512CostTable[] = { 554 { ISD::SHL, MVT::v16i32, 1 }, 555 { ISD::SRL, MVT::v16i32, 1 }, 556 { ISD::SRA, MVT::v16i32, 1 }, 557 558 { ISD::SHL, MVT::v8i64, 1 }, 559 { ISD::SRL, MVT::v8i64, 1 }, 560 561 { ISD::SRA, MVT::v2i64, 1 }, 562 { ISD::SRA, MVT::v4i64, 1 }, 563 { ISD::SRA, MVT::v8i64, 1 }, 564 565 { ISD::MUL, MVT::v64i8, 26 }, // extend/pmullw/trunc sequence. 566 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence. 567 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence. 568 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 569 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 570 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 571 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add 572 573 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 574 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 575 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 576 577 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 578 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 579 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 580 }; 581 582 if (ST->hasAVX512()) 583 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 584 return LT.first * Entry->Cost; 585 586 static const CostTblEntry AVX2ShiftCostTable[] = { 587 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 588 // customize them to detect the cases where shift amount is a scalar one. 589 { ISD::SHL, MVT::v4i32, 1 }, 590 { ISD::SRL, MVT::v4i32, 1 }, 591 { ISD::SRA, MVT::v4i32, 1 }, 592 { ISD::SHL, MVT::v8i32, 1 }, 593 { ISD::SRL, MVT::v8i32, 1 }, 594 { ISD::SRA, MVT::v8i32, 1 }, 595 { ISD::SHL, MVT::v2i64, 1 }, 596 { ISD::SRL, MVT::v2i64, 1 }, 597 { ISD::SHL, MVT::v4i64, 1 }, 598 { ISD::SRL, MVT::v4i64, 1 }, 599 }; 600 601 if (ST->hasAVX512()) { 602 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 603 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 604 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 605 // On AVX512, a packed v32i16 shift left by a constant build_vector 606 // is lowered into a vector multiply (vpmullw). 607 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 608 Op1Info, Op2Info, 609 TargetTransformInfo::OP_None, 610 TargetTransformInfo::OP_None); 611 } 612 613 // Look for AVX2 lowering tricks. 614 if (ST->hasAVX2()) { 615 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 616 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 617 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 618 // On AVX2, a packed v16i16 shift left by a constant build_vector 619 // is lowered into a vector multiply (vpmullw). 620 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 621 Op1Info, Op2Info, 622 TargetTransformInfo::OP_None, 623 TargetTransformInfo::OP_None); 624 625 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 626 return LT.first * Entry->Cost; 627 } 628 629 static const CostTblEntry XOPShiftCostTable[] = { 630 // 128bit shifts take 1cy, but right shifts require negation beforehand. 631 { ISD::SHL, MVT::v16i8, 1 }, 632 { ISD::SRL, MVT::v16i8, 2 }, 633 { ISD::SRA, MVT::v16i8, 2 }, 634 { ISD::SHL, MVT::v8i16, 1 }, 635 { ISD::SRL, MVT::v8i16, 2 }, 636 { ISD::SRA, MVT::v8i16, 2 }, 637 { ISD::SHL, MVT::v4i32, 1 }, 638 { ISD::SRL, MVT::v4i32, 2 }, 639 { ISD::SRA, MVT::v4i32, 2 }, 640 { ISD::SHL, MVT::v2i64, 1 }, 641 { ISD::SRL, MVT::v2i64, 2 }, 642 { ISD::SRA, MVT::v2i64, 2 }, 643 // 256bit shifts require splitting if AVX2 didn't catch them above. 644 { ISD::SHL, MVT::v32i8, 2+2 }, 645 { ISD::SRL, MVT::v32i8, 4+2 }, 646 { ISD::SRA, MVT::v32i8, 4+2 }, 647 { ISD::SHL, MVT::v16i16, 2+2 }, 648 { ISD::SRL, MVT::v16i16, 4+2 }, 649 { ISD::SRA, MVT::v16i16, 4+2 }, 650 { ISD::SHL, MVT::v8i32, 2+2 }, 651 { ISD::SRL, MVT::v8i32, 4+2 }, 652 { ISD::SRA, MVT::v8i32, 4+2 }, 653 { ISD::SHL, MVT::v4i64, 2+2 }, 654 { ISD::SRL, MVT::v4i64, 4+2 }, 655 { ISD::SRA, MVT::v4i64, 4+2 }, 656 }; 657 658 // Look for XOP lowering tricks. 659 if (ST->hasXOP()) { 660 // If the right shift is constant then we'll fold the negation so 661 // it's as cheap as a left shift. 662 int ShiftISD = ISD; 663 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 664 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 665 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 666 ShiftISD = ISD::SHL; 667 if (const auto *Entry = 668 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 669 return LT.first * Entry->Cost; 670 } 671 672 static const CostTblEntry SSE2UniformShiftCostTable[] = { 673 // Uniform splats are cheaper for the following instructions. 674 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 675 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 676 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 677 678 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 679 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 680 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 681 682 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 683 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 684 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 685 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 686 }; 687 688 if (ST->hasSSE2() && 689 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 690 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 691 692 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 693 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 694 return LT.first * 4; // 2*psrad + shuffle. 695 696 if (const auto *Entry = 697 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 698 return LT.first * Entry->Cost; 699 } 700 701 if (ISD == ISD::SHL && 702 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 703 MVT VT = LT.second; 704 // Vector shift left by non uniform constant can be lowered 705 // into vector multiply. 706 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 707 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 708 ISD = ISD::MUL; 709 } 710 711 static const CostTblEntry AVX2CostTable[] = { 712 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. 713 { ISD::SHL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. 714 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 715 { ISD::SHL, MVT::v32i16, 20 }, // 2*extend/vpsrlvd/pack sequence. 716 717 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. 718 { ISD::SRL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. 719 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 720 { ISD::SRL, MVT::v32i16, 20 }, // 2*extend/vpsrlvd/pack sequence. 721 722 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. 723 { ISD::SRA, MVT::v64i8, 48 }, // 2*vpblendvb sequence. 724 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. 725 { ISD::SRA, MVT::v32i16, 20 }, // 2*extend/vpsravd/pack sequence. 726 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. 727 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 728 729 { ISD::SUB, MVT::v32i8, 1 }, // psubb 730 { ISD::ADD, MVT::v32i8, 1 }, // paddb 731 { ISD::SUB, MVT::v16i16, 1 }, // psubw 732 { ISD::ADD, MVT::v16i16, 1 }, // paddw 733 { ISD::SUB, MVT::v8i32, 1 }, // psubd 734 { ISD::ADD, MVT::v8i32, 1 }, // paddd 735 { ISD::SUB, MVT::v4i64, 1 }, // psubq 736 { ISD::ADD, MVT::v4i64, 1 }, // paddq 737 738 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence. 739 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence. 740 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 741 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 742 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add 743 744 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 745 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 746 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 747 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 748 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 749 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 750 751 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 752 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 753 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 754 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 755 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 756 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 757 }; 758 759 // Look for AVX2 lowering tricks for custom cases. 760 if (ST->hasAVX2()) 761 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 762 return LT.first * Entry->Cost; 763 764 static const CostTblEntry AVX1CostTable[] = { 765 // We don't have to scalarize unsupported ops. We can issue two half-sized 766 // operations and we only need to extract the upper YMM half. 767 // Two ops + 1 extract + 1 insert = 4. 768 { ISD::MUL, MVT::v16i16, 4 }, 769 { ISD::MUL, MVT::v8i32, 4 }, 770 { ISD::SUB, MVT::v32i8, 4 }, 771 { ISD::ADD, MVT::v32i8, 4 }, 772 { ISD::SUB, MVT::v16i16, 4 }, 773 { ISD::ADD, MVT::v16i16, 4 }, 774 { ISD::SUB, MVT::v8i32, 4 }, 775 { ISD::ADD, MVT::v8i32, 4 }, 776 { ISD::SUB, MVT::v4i64, 4 }, 777 { ISD::ADD, MVT::v4i64, 4 }, 778 779 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 780 // are lowered as a series of long multiplies(3), shifts(3) and adds(2) 781 // Because we believe v4i64 to be a legal type, we must also include the 782 // extract+insert in the cost table. Therefore, the cost here is 18 783 // instead of 8. 784 { ISD::MUL, MVT::v4i64, 18 }, 785 786 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence. 787 788 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 789 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 790 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 791 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 792 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 793 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 794 }; 795 796 if (ST->hasAVX()) 797 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 798 return LT.first * Entry->Cost; 799 800 static const CostTblEntry SSE42CostTable[] = { 801 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 802 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 803 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 804 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 805 806 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 807 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 808 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 809 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 810 811 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 812 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 813 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 814 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 815 816 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 817 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 818 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 819 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 820 }; 821 822 if (ST->hasSSE42()) 823 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 824 return LT.first * Entry->Cost; 825 826 static const CostTblEntry SSE41CostTable[] = { 827 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 828 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split. 829 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 830 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 831 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 832 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split 833 834 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 835 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split. 836 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 837 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 838 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 839 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split. 840 841 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 842 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split. 843 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 844 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 845 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 846 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split. 847 848 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 849 }; 850 851 if (ST->hasSSE41()) 852 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 853 return LT.first * Entry->Cost; 854 855 static const CostTblEntry SSE2CostTable[] = { 856 // We don't correctly identify costs of casts because they are marked as 857 // custom. 858 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 859 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 860 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 861 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 862 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 863 864 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 865 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 866 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 867 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 868 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 869 870 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 871 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 872 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 873 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 874 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split. 875 876 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence. 877 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 878 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 879 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 880 881 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 882 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 883 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 884 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 885 886 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 887 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 888 889 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 890 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 891 }; 892 893 if (ST->hasSSE2()) 894 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 895 return LT.first * Entry->Cost; 896 897 static const CostTblEntry SSE1CostTable[] = { 898 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 899 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 900 901 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 902 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 903 904 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 905 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 906 907 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 908 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 909 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 910 911 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 912 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 913 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 914 }; 915 916 if (ST->hasSSE1()) 917 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 918 return LT.first * Entry->Cost; 919 920 // It is not a good idea to vectorize division. We have to scalarize it and 921 // in the process we will often end up having to spilling regular 922 // registers. The overhead of division is going to dominate most kernels 923 // anyways so try hard to prevent vectorization of division - it is 924 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 925 // to hide "20 cycles" for each lane. 926 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 927 ISD == ISD::UDIV || ISD == ISD::UREM)) { 928 int ScalarCost = getArithmeticInstrCost( 929 Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info, 930 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 931 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 932 } 933 934 // Fallback to the default implementation. 935 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info); 936 } 937 938 int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, VectorType *BaseTp, 939 int Index, VectorType *SubTp) { 940 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 941 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 942 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 943 944 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 945 if (Kind == TTI::SK_Transpose) 946 Kind = TTI::SK_PermuteTwoSrc; 947 948 // For Broadcasts we are splatting the first element from the first input 949 // register, so only need to reference that input and all the output 950 // registers are the same. 951 if (Kind == TTI::SK_Broadcast) 952 LT.first = 1; 953 954 // Subvector extractions are free if they start at the beginning of a 955 // vector and cheap if the subvectors are aligned. 956 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 957 int NumElts = LT.second.getVectorNumElements(); 958 if ((Index % NumElts) == 0) 959 return 0; 960 std::pair<int, MVT> SubLT = TLI->getTypeLegalizationCost(DL, SubTp); 961 if (SubLT.second.isVector()) { 962 int NumSubElts = SubLT.second.getVectorNumElements(); 963 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 964 return SubLT.first; 965 // Handle some cases for widening legalization. For now we only handle 966 // cases where the original subvector was naturally aligned and evenly 967 // fit in its legalized subvector type. 968 // FIXME: Remove some of the alignment restrictions. 969 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 970 // vectors. 971 int OrigSubElts = cast<VectorType>(SubTp)->getNumElements(); 972 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 973 (NumSubElts % OrigSubElts) == 0 && 974 LT.second.getVectorElementType() == 975 SubLT.second.getVectorElementType() && 976 LT.second.getVectorElementType().getSizeInBits() == 977 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 978 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 979 "Unexpected number of elements!"); 980 VectorType *VecTy = VectorType::get(BaseTp->getElementType(), 981 LT.second.getVectorNumElements()); 982 VectorType *SubTy = 983 VectorType::get(BaseTp->getElementType(), 984 SubLT.second.getVectorNumElements()); 985 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 986 int ExtractCost = getShuffleCost(TTI::SK_ExtractSubvector, VecTy, 987 ExtractIndex, SubTy); 988 989 // If the original size is 32-bits or more, we can use pshufd. Otherwise 990 // if we have SSSE3 we can use pshufb. 991 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 992 return ExtractCost + 1; // pshufd or pshufb 993 994 assert(SubTp->getPrimitiveSizeInBits() == 16 && 995 "Unexpected vector size"); 996 997 return ExtractCost + 2; // worst case pshufhw + pshufd 998 } 999 } 1000 } 1001 1002 // Handle some common (illegal) sub-vector types as they are often very cheap 1003 // to shuffle even on targets without PSHUFB. 1004 EVT VT = TLI->getValueType(DL, BaseTp); 1005 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 1006 !ST->hasSSSE3()) { 1007 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 1008 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 1009 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1010 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1011 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1012 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1013 1014 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1015 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1016 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1017 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1018 1019 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1020 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1021 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1022 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1023 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1024 1025 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1026 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1027 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1028 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1029 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1030 }; 1031 1032 if (ST->hasSSE2()) 1033 if (const auto *Entry = 1034 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1035 return Entry->Cost; 1036 } 1037 1038 // We are going to permute multiple sources and the result will be in multiple 1039 // destinations. Providing an accurate cost only for splits where the element 1040 // type remains the same. 1041 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1042 MVT LegalVT = LT.second; 1043 if (LegalVT.isVector() && 1044 LegalVT.getVectorElementType().getSizeInBits() == 1045 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1046 LegalVT.getVectorNumElements() < BaseTp->getNumElements()) { 1047 1048 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1049 unsigned LegalVTSize = LegalVT.getStoreSize(); 1050 // Number of source vectors after legalization: 1051 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1052 // Number of destination vectors after legalization: 1053 unsigned NumOfDests = LT.first; 1054 1055 VectorType *SingleOpTy = 1056 VectorType::get(BaseTp->getElementType(), 1057 LegalVT.getVectorNumElements()); 1058 1059 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1060 return NumOfShuffles * 1061 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 0, nullptr); 1062 } 1063 1064 return BaseT::getShuffleCost(Kind, BaseTp, Index, SubTp); 1065 } 1066 1067 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1068 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1069 // We assume that source and destination have the same vector type. 1070 int NumOfDests = LT.first; 1071 int NumOfShufflesPerDest = LT.first * 2 - 1; 1072 LT.first = NumOfDests * NumOfShufflesPerDest; 1073 } 1074 1075 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1076 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1077 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1078 1079 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1080 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1081 1082 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b 1083 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b 1084 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2} // vpermt2b 1085 }; 1086 1087 if (ST->hasVBMI()) 1088 if (const auto *Entry = 1089 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1090 return LT.first * Entry->Cost; 1091 1092 static const CostTblEntry AVX512BWShuffleTbl[] = { 1093 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1094 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1095 1096 {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw 1097 {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw 1098 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1099 1100 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw 1101 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw 1102 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1103 1104 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w 1105 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w 1106 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2}, // vpermt2w 1107 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1108 }; 1109 1110 if (ST->hasBWI()) 1111 if (const auto *Entry = 1112 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1113 return LT.first * Entry->Cost; 1114 1115 static const CostTblEntry AVX512ShuffleTbl[] = { 1116 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1117 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1118 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1119 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1120 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1121 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1122 1123 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1124 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1125 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1126 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1127 1128 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1129 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1130 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1131 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1132 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1133 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1134 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1135 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1136 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1137 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1138 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1139 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1140 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1141 1142 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1143 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1144 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1145 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1146 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1147 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1148 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1149 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1150 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1151 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1152 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1153 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1154 1155 // FIXME: This just applies the type legalization cost rules above 1156 // assuming these completely split. 1157 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1158 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1159 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1160 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1161 }; 1162 1163 if (ST->hasAVX512()) 1164 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1165 return LT.first * Entry->Cost; 1166 1167 static const CostTblEntry AVX2ShuffleTbl[] = { 1168 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1169 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1170 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1171 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1172 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1173 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1174 1175 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1176 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1177 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1178 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1179 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1180 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1181 1182 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1183 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1184 1185 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1186 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1187 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1188 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1189 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1190 // + vpblendvb 1191 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1192 // + vpblendvb 1193 1194 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1195 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1196 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1197 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1198 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1199 // + vpblendvb 1200 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1201 // + vpblendvb 1202 }; 1203 1204 if (ST->hasAVX2()) 1205 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1206 return LT.first * Entry->Cost; 1207 1208 static const CostTblEntry XOPShuffleTbl[] = { 1209 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1210 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1211 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1212 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1213 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1214 // + vinsertf128 1215 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1216 // + vinsertf128 1217 1218 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1219 // + vinsertf128 1220 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1221 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1222 // + vinsertf128 1223 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1224 }; 1225 1226 if (ST->hasXOP()) 1227 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1228 return LT.first * Entry->Cost; 1229 1230 static const CostTblEntry AVX1ShuffleTbl[] = { 1231 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1232 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1233 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1234 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1235 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1236 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1237 1238 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1239 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1240 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1241 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1242 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1243 // + vinsertf128 1244 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1245 // + vinsertf128 1246 1247 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1248 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1249 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1250 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1251 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1252 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1253 1254 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1255 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1256 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1257 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1258 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1259 // + 2*por + vinsertf128 1260 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1261 // + 2*por + vinsertf128 1262 1263 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1264 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1265 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1266 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1267 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1268 // + 4*por + vinsertf128 1269 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1270 // + 4*por + vinsertf128 1271 }; 1272 1273 if (ST->hasAVX()) 1274 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1275 return LT.first * Entry->Cost; 1276 1277 static const CostTblEntry SSE41ShuffleTbl[] = { 1278 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1279 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1280 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1281 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1282 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1283 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1284 }; 1285 1286 if (ST->hasSSE41()) 1287 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1288 return LT.first * Entry->Cost; 1289 1290 static const CostTblEntry SSSE3ShuffleTbl[] = { 1291 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1292 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1293 1294 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1295 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1296 1297 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1298 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1299 1300 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1301 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1302 1303 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1304 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1305 }; 1306 1307 if (ST->hasSSSE3()) 1308 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1309 return LT.first * Entry->Cost; 1310 1311 static const CostTblEntry SSE2ShuffleTbl[] = { 1312 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1313 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1314 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1315 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1316 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1317 1318 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1319 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1320 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1321 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1322 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1323 // + 2*pshufd + 2*unpck + packus 1324 1325 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1326 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1327 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1328 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1329 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1330 1331 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1332 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1333 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1334 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1335 // + pshufd/unpck 1336 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1337 // + 2*pshufd + 2*unpck + 2*packus 1338 1339 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1340 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1341 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1342 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1343 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1344 }; 1345 1346 if (ST->hasSSE2()) 1347 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1348 return LT.first * Entry->Cost; 1349 1350 static const CostTblEntry SSE1ShuffleTbl[] = { 1351 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1352 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1353 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1354 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1355 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1356 }; 1357 1358 if (ST->hasSSE1()) 1359 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1360 return LT.first * Entry->Cost; 1361 1362 return BaseT::getShuffleCost(Kind, BaseTp, Index, SubTp); 1363 } 1364 1365 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 1366 TTI::TargetCostKind CostKind, 1367 const Instruction *I) { 1368 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1369 assert(ISD && "Invalid opcode"); 1370 1371 // TODO: Allow non-throughput costs that aren't binary. 1372 auto AdjustCost = [&CostKind](int Cost) { 1373 if (CostKind != TTI::TCK_RecipThroughput) 1374 return Cost == 0 ? 0 : 1; 1375 return Cost; 1376 }; 1377 1378 // FIXME: Need a better design of the cost table to handle non-simple types of 1379 // potential massive combinations (elem_num x src_type x dst_type). 1380 1381 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1382 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1383 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1384 1385 // Mask sign extend has an instruction. 1386 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1387 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1388 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1389 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1390 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1391 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1392 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1393 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1394 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1395 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1396 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1397 1398 // Mask zero extend is a sext + shift. 1399 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1400 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1401 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1402 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1403 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1404 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1405 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1406 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1407 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1408 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1409 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1410 1411 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, 1412 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm 1413 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // widen to zmm 1414 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // widen to zmm 1415 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // widen to zmm 1416 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // widen to zmm 1417 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // widen to zmm 1418 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // widen to zmm 1419 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // widen to zmm 1420 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // widen to zmm 1421 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // widen to zmm 1422 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, 1423 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, 1424 }; 1425 1426 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1427 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1428 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1429 1430 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1431 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1432 1433 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1434 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1435 1436 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1437 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1438 }; 1439 1440 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1441 // 256-bit wide vectors. 1442 1443 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1444 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1445 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1446 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1447 1448 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1449 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1450 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1451 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd 1452 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1453 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1454 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1455 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd 1456 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd 1457 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd 1458 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd 1459 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd 1460 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq 1461 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq 1462 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq 1463 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, 1464 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, 1465 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, 1466 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, 1467 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 1468 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd 1469 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb 1470 1471 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32 1472 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, 1473 1474 // Sign extend is zmm vpternlogd+vptruncdb. 1475 // Zero extend is zmm broadcast load+vptruncdw. 1476 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 }, 1477 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 }, 1478 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, 1479 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, 1480 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, 1481 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, 1482 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 }, 1483 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 }, 1484 1485 // Sign extend is zmm vpternlogd+vptruncdw. 1486 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw. 1487 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 }, 1488 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1489 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 }, 1490 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1491 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 }, 1492 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1493 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 }, 1494 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1495 1496 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd 1497 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld 1498 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd 1499 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld 1500 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd 1501 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld 1502 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq 1503 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq 1504 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq 1505 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq 1506 1507 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd 1508 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld 1509 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq 1510 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq 1511 1512 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1513 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1514 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1515 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1516 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1517 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1518 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1519 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1520 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1521 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1522 1523 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1524 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1525 1526 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1527 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1528 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1529 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1530 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1531 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1532 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1533 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1534 1535 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1536 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1537 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1538 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1539 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1540 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1541 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1542 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1543 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1544 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1545 1546 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f64, 3 }, 1547 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, 1548 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 3 }, 1549 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 3 }, 1550 1551 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1552 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, 1553 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, 1554 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1555 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, 1556 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, 1557 }; 1558 1559 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1560 // Mask sign extend has an instruction. 1561 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1562 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1563 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1564 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1565 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1566 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1567 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1568 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1569 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1570 1571 // Mask zero extend is a sext + shift. 1572 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1573 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1574 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1575 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1576 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1577 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1578 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1579 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1580 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1581 1582 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, 1583 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // vpsllw+vptestmb 1584 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // vpsllw+vptestmw 1585 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // vpsllw+vptestmb 1586 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // vpsllw+vptestmw 1587 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // vpsllw+vptestmb 1588 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // vpsllw+vptestmw 1589 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // vpsllw+vptestmb 1590 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // vpsllw+vptestmw 1591 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // vpsllw+vptestmb 1592 }; 1593 1594 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1595 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1596 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1597 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1598 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1599 1600 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1601 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1602 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1603 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1604 1605 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1606 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1607 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1608 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1609 1610 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1611 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1612 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1613 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1614 }; 1615 1616 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 1617 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1618 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1619 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1620 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 8 }, // split+2*v8i8 1621 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1622 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1623 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1624 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16 1625 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // vpslld+vptestmd 1626 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd 1627 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // vpslld+vptestmd 1628 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // vpsllq+vptestmq 1629 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // vpsllq+vptestmq 1630 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // vpmovqd 1631 1632 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb 1633 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb 1634 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 }, 1635 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 }, 1636 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 }, 1637 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 }, 1638 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 }, 1639 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 }, 1640 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 }, 1641 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 }, 1642 1643 // sign extend is vpcmpeq+maskedmove+vpmovdw 1644 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw 1645 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1646 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 }, 1647 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1648 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 }, 1649 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1650 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 }, 1651 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 }, 1652 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 }, 1653 1654 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd 1655 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld 1656 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd 1657 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld 1658 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd 1659 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld 1660 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq 1661 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq 1662 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq 1663 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq 1664 1665 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1666 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1667 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1668 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1669 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1670 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1671 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1672 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1673 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1674 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1675 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1676 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1677 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1678 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1679 1680 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 1681 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1682 1683 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 3 }, 1684 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 3 }, 1685 1686 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 1687 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 1688 1689 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1690 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1691 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 1 }, 1692 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1693 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1694 }; 1695 1696 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1697 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1698 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1699 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1700 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1701 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1702 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1703 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1704 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1705 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1706 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1707 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1708 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1709 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1710 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1711 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1712 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1713 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1714 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1715 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1716 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1717 1718 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1719 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1720 1721 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 1722 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 1723 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 1724 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1725 1726 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1727 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1728 1729 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1730 }; 1731 1732 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1733 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1734 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1735 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1736 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1737 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1738 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1739 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1740 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1741 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1742 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1743 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1744 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1745 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 4 }, 1746 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1747 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1748 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1749 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1750 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1751 1752 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 4 }, 1753 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 5 }, 1754 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 4 }, 1755 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 9 }, 1756 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, 11 }, 1757 1758 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 1759 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1760 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1761 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1762 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 1763 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1764 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 11 }, 1765 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 9 }, 1766 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 }, 1767 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 11 }, 1768 1769 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1770 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1771 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1772 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1773 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1774 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1775 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1776 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1777 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1778 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1779 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1780 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1781 1782 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1783 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1784 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1785 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1786 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1787 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1788 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1789 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1790 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1791 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 }, 1792 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 1793 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1794 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 1795 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1796 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1797 // The generic code to compute the scalar overhead is currently broken. 1798 // Workaround this limitation by estimating the scalarization overhead 1799 // here. We have roughly 10 instructions per scalar element. 1800 // Multiply that by the vector width. 1801 // FIXME: remove that when PR19268 is fixed. 1802 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1803 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1804 1805 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 4 }, 1806 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f64, 3 }, 1807 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f64, 2 }, 1808 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 3 }, 1809 1810 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f64, 3 }, 1811 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f64, 2 }, 1812 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 4 }, 1813 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 3 }, 1814 // This node is expanded into scalarized operations but BasicTTI is overly 1815 // optimistic estimating its cost. It computes 3 per element (one 1816 // vector-extract, one scalar conversion and one vector-insert). The 1817 // problem is that the inserts form a read-modify-write chain so latency 1818 // should be factored in too. Inflating the cost per element by 1. 1819 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, 1820 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 1821 1822 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 1823 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 1824 }; 1825 1826 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 1827 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1828 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1829 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1830 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1831 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1832 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1833 1834 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1835 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 }, 1836 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1837 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1838 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1839 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1840 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1841 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1842 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1843 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1844 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1845 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1846 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1847 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1848 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1849 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1850 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1851 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1852 1853 // These truncates end up widening elements. 1854 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 1 }, // PMOVXZBQ 1855 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 1 }, // PMOVXZWQ 1856 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 1 }, // PMOVXZBD 1857 1858 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 1 }, 1859 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 1 }, 1860 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 1861 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 1862 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 1863 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 1864 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 1865 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 1866 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 1 }, // PSHUFB 1867 1868 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 1869 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 1870 1871 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 3 }, 1872 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 3 }, 1873 1874 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 3 }, 1875 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 3 }, 1876 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, 1877 }; 1878 1879 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 1880 // These are somewhat magic numbers justified by looking at the output of 1881 // Intel's IACA, running some kernels and making sure when we take 1882 // legalization into account the throughput will be overestimated. 1883 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1884 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1885 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1886 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1887 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1888 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 2*10 }, 1889 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2*10 }, 1890 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1891 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 1892 1893 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1894 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1895 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1896 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1897 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1898 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, 1899 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 }, 1900 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1901 1902 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 4 }, 1903 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 2 }, 1904 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, 1905 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, 1906 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, 1907 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 4 }, 1908 1909 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 1 }, 1910 1911 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 6 }, 1912 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 }, 1913 1914 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 1915 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 1916 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 4 }, 1917 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 4 }, 1918 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 }, 1919 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 2 }, 1920 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 }, 1921 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 4 }, 1922 1923 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1924 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 1925 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 1926 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 1927 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1928 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 1929 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1930 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 1931 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1932 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1933 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1934 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1935 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 1936 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 1937 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1938 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 1939 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1940 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 1941 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1942 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1943 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 1944 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 1945 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1946 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 1947 1948 // These truncates are really widening elements. 1949 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 1 }, // PSHUFD 1950 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // PUNPCKLWD+DQ 1951 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // PUNPCKLBW+WD+PSHUFD 1952 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 1 }, // PUNPCKLWD 1953 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // PUNPCKLBW+WD 1954 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 1 }, // PUNPCKLBW 1955 1956 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // PAND+PACKUSWB 1957 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // PAND+PACKUSWB 1958 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // PAND+PACKUSWB 1959 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 1960 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 3 }, // PAND+2*PACKUSWB 1961 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 1962 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 1963 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 1964 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1965 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 1966 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1967 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 1968 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 1969 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 1970 { ISD::TRUNCATE, MVT::v2i32, MVT::v2i64, 1 }, // PSHUFD 1971 }; 1972 1973 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 1974 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst); 1975 1976 if (ST->hasSSE2() && !ST->hasAVX()) { 1977 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1978 LTDest.second, LTSrc.second)) 1979 return AdjustCost(LTSrc.first * Entry->Cost); 1980 } 1981 1982 EVT SrcTy = TLI->getValueType(DL, Src); 1983 EVT DstTy = TLI->getValueType(DL, Dst); 1984 1985 // The function getSimpleVT only handles simple value types. 1986 if (!SrcTy.isSimple() || !DstTy.isSimple()) 1987 return AdjustCost(BaseT::getCastInstrCost(Opcode, Dst, Src, CostKind)); 1988 1989 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 1990 MVT SimpleDstTy = DstTy.getSimpleVT(); 1991 1992 if (ST->useAVX512Regs()) { 1993 if (ST->hasBWI()) 1994 if (const auto *Entry = ConvertCostTableLookup(AVX512BWConversionTbl, ISD, 1995 SimpleDstTy, SimpleSrcTy)) 1996 return AdjustCost(Entry->Cost); 1997 1998 if (ST->hasDQI()) 1999 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 2000 SimpleDstTy, SimpleSrcTy)) 2001 return AdjustCost(Entry->Cost); 2002 2003 if (ST->hasAVX512()) 2004 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 2005 SimpleDstTy, SimpleSrcTy)) 2006 return AdjustCost(Entry->Cost); 2007 } 2008 2009 if (ST->hasBWI()) 2010 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 2011 SimpleDstTy, SimpleSrcTy)) 2012 return AdjustCost(Entry->Cost); 2013 2014 if (ST->hasDQI()) 2015 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 2016 SimpleDstTy, SimpleSrcTy)) 2017 return AdjustCost(Entry->Cost); 2018 2019 if (ST->hasAVX512()) 2020 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2021 SimpleDstTy, SimpleSrcTy)) 2022 return AdjustCost(Entry->Cost); 2023 2024 if (ST->hasAVX2()) { 2025 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2026 SimpleDstTy, SimpleSrcTy)) 2027 return AdjustCost(Entry->Cost); 2028 } 2029 2030 if (ST->hasAVX()) { 2031 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2032 SimpleDstTy, SimpleSrcTy)) 2033 return AdjustCost(Entry->Cost); 2034 } 2035 2036 if (ST->hasSSE41()) { 2037 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2038 SimpleDstTy, SimpleSrcTy)) 2039 return AdjustCost(Entry->Cost); 2040 } 2041 2042 if (ST->hasSSE2()) { 2043 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2044 SimpleDstTy, SimpleSrcTy)) 2045 return AdjustCost(Entry->Cost); 2046 } 2047 2048 return AdjustCost(BaseT::getCastInstrCost(Opcode, Dst, Src, CostKind, I)); 2049 } 2050 2051 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 2052 TTI::TargetCostKind CostKind, 2053 const Instruction *I) { 2054 // Legalize the type. 2055 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2056 2057 MVT MTy = LT.second; 2058 2059 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2060 assert(ISD && "Invalid opcode"); 2061 2062 unsigned ExtraCost = 0; 2063 if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) { 2064 // Some vector comparison predicates cost extra instructions. 2065 if (MTy.isVector() && 2066 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 2067 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 2068 ST->hasBWI())) { 2069 switch (cast<CmpInst>(I)->getPredicate()) { 2070 case CmpInst::Predicate::ICMP_NE: 2071 // xor(cmpeq(x,y),-1) 2072 ExtraCost = 1; 2073 break; 2074 case CmpInst::Predicate::ICMP_SGE: 2075 case CmpInst::Predicate::ICMP_SLE: 2076 // xor(cmpgt(x,y),-1) 2077 ExtraCost = 1; 2078 break; 2079 case CmpInst::Predicate::ICMP_ULT: 2080 case CmpInst::Predicate::ICMP_UGT: 2081 // cmpgt(xor(x,signbit),xor(y,signbit)) 2082 // xor(cmpeq(pmaxu(x,y),x),-1) 2083 ExtraCost = 2; 2084 break; 2085 case CmpInst::Predicate::ICMP_ULE: 2086 case CmpInst::Predicate::ICMP_UGE: 2087 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 2088 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 2089 // cmpeq(psubus(x,y),0) 2090 // cmpeq(pminu(x,y),x) 2091 ExtraCost = 1; 2092 } else { 2093 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 2094 ExtraCost = 3; 2095 } 2096 break; 2097 default: 2098 break; 2099 } 2100 } 2101 } 2102 2103 static const CostTblEntry SLMCostTbl[] = { 2104 // slm pcmpeq/pcmpgt throughput is 2 2105 { ISD::SETCC, MVT::v2i64, 2 }, 2106 }; 2107 2108 static const CostTblEntry AVX512BWCostTbl[] = { 2109 { ISD::SETCC, MVT::v32i16, 1 }, 2110 { ISD::SETCC, MVT::v64i8, 1 }, 2111 2112 { ISD::SELECT, MVT::v32i16, 1 }, 2113 { ISD::SELECT, MVT::v64i8, 1 }, 2114 }; 2115 2116 static const CostTblEntry AVX512CostTbl[] = { 2117 { ISD::SETCC, MVT::v8i64, 1 }, 2118 { ISD::SETCC, MVT::v16i32, 1 }, 2119 { ISD::SETCC, MVT::v8f64, 1 }, 2120 { ISD::SETCC, MVT::v16f32, 1 }, 2121 2122 { ISD::SELECT, MVT::v8i64, 1 }, 2123 { ISD::SELECT, MVT::v16i32, 1 }, 2124 { ISD::SELECT, MVT::v8f64, 1 }, 2125 { ISD::SELECT, MVT::v16f32, 1 }, 2126 2127 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 2128 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 2129 2130 { ISD::SELECT, MVT::v32i16, 2 }, // FIXME: should be 3 2131 { ISD::SELECT, MVT::v64i8, 2 }, // FIXME: should be 3 2132 }; 2133 2134 static const CostTblEntry AVX2CostTbl[] = { 2135 { ISD::SETCC, MVT::v4i64, 1 }, 2136 { ISD::SETCC, MVT::v8i32, 1 }, 2137 { ISD::SETCC, MVT::v16i16, 1 }, 2138 { ISD::SETCC, MVT::v32i8, 1 }, 2139 2140 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 2141 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 2142 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 2143 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 2144 }; 2145 2146 static const CostTblEntry AVX1CostTbl[] = { 2147 { ISD::SETCC, MVT::v4f64, 1 }, 2148 { ISD::SETCC, MVT::v8f32, 1 }, 2149 // AVX1 does not support 8-wide integer compare. 2150 { ISD::SETCC, MVT::v4i64, 4 }, 2151 { ISD::SETCC, MVT::v8i32, 4 }, 2152 { ISD::SETCC, MVT::v16i16, 4 }, 2153 { ISD::SETCC, MVT::v32i8, 4 }, 2154 2155 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 2156 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 2157 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 2158 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 2159 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 2160 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 2161 }; 2162 2163 static const CostTblEntry SSE42CostTbl[] = { 2164 { ISD::SETCC, MVT::v2f64, 1 }, 2165 { ISD::SETCC, MVT::v4f32, 1 }, 2166 { ISD::SETCC, MVT::v2i64, 1 }, 2167 }; 2168 2169 static const CostTblEntry SSE41CostTbl[] = { 2170 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 2171 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 2172 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 2173 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 2174 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 2175 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 2176 }; 2177 2178 static const CostTblEntry SSE2CostTbl[] = { 2179 { ISD::SETCC, MVT::v2f64, 2 }, 2180 { ISD::SETCC, MVT::f64, 1 }, 2181 { ISD::SETCC, MVT::v2i64, 8 }, 2182 { ISD::SETCC, MVT::v4i32, 1 }, 2183 { ISD::SETCC, MVT::v8i16, 1 }, 2184 { ISD::SETCC, MVT::v16i8, 1 }, 2185 2186 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 2187 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 2188 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 2189 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 2190 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 2191 }; 2192 2193 static const CostTblEntry SSE1CostTbl[] = { 2194 { ISD::SETCC, MVT::v4f32, 2 }, 2195 { ISD::SETCC, MVT::f32, 1 }, 2196 2197 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 2198 }; 2199 2200 if (ST->isSLM()) 2201 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2202 return LT.first * (ExtraCost + Entry->Cost); 2203 2204 if (ST->hasBWI()) 2205 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2206 return LT.first * (ExtraCost + Entry->Cost); 2207 2208 if (ST->hasAVX512()) 2209 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2210 return LT.first * (ExtraCost + Entry->Cost); 2211 2212 if (ST->hasAVX2()) 2213 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2214 return LT.first * (ExtraCost + Entry->Cost); 2215 2216 if (ST->hasAVX()) 2217 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2218 return LT.first * (ExtraCost + Entry->Cost); 2219 2220 if (ST->hasSSE42()) 2221 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2222 return LT.first * (ExtraCost + Entry->Cost); 2223 2224 if (ST->hasSSE41()) 2225 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2226 return LT.first * (ExtraCost + Entry->Cost); 2227 2228 if (ST->hasSSE2()) 2229 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2230 return LT.first * (ExtraCost + Entry->Cost); 2231 2232 if (ST->hasSSE1()) 2233 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2234 return LT.first * (ExtraCost + Entry->Cost); 2235 2236 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, CostKind, I); 2237 } 2238 2239 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2240 2241 int X86TTIImpl::getTypeBasedIntrinsicInstrCost( 2242 const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) { 2243 2244 // Costs should match the codegen from: 2245 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2246 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2247 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2248 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2249 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2250 static const CostTblEntry AVX512CDCostTbl[] = { 2251 { ISD::CTLZ, MVT::v8i64, 1 }, 2252 { ISD::CTLZ, MVT::v16i32, 1 }, 2253 { ISD::CTLZ, MVT::v32i16, 8 }, 2254 { ISD::CTLZ, MVT::v64i8, 20 }, 2255 { ISD::CTLZ, MVT::v4i64, 1 }, 2256 { ISD::CTLZ, MVT::v8i32, 1 }, 2257 { ISD::CTLZ, MVT::v16i16, 4 }, 2258 { ISD::CTLZ, MVT::v32i8, 10 }, 2259 { ISD::CTLZ, MVT::v2i64, 1 }, 2260 { ISD::CTLZ, MVT::v4i32, 1 }, 2261 { ISD::CTLZ, MVT::v8i16, 4 }, 2262 { ISD::CTLZ, MVT::v16i8, 4 }, 2263 }; 2264 static const CostTblEntry AVX512BWCostTbl[] = { 2265 { ISD::BITREVERSE, MVT::v8i64, 5 }, 2266 { ISD::BITREVERSE, MVT::v16i32, 5 }, 2267 { ISD::BITREVERSE, MVT::v32i16, 5 }, 2268 { ISD::BITREVERSE, MVT::v64i8, 5 }, 2269 { ISD::CTLZ, MVT::v8i64, 23 }, 2270 { ISD::CTLZ, MVT::v16i32, 22 }, 2271 { ISD::CTLZ, MVT::v32i16, 18 }, 2272 { ISD::CTLZ, MVT::v64i8, 17 }, 2273 { ISD::CTPOP, MVT::v8i64, 7 }, 2274 { ISD::CTPOP, MVT::v16i32, 11 }, 2275 { ISD::CTPOP, MVT::v32i16, 9 }, 2276 { ISD::CTPOP, MVT::v64i8, 6 }, 2277 { ISD::CTTZ, MVT::v8i64, 10 }, 2278 { ISD::CTTZ, MVT::v16i32, 14 }, 2279 { ISD::CTTZ, MVT::v32i16, 12 }, 2280 { ISD::CTTZ, MVT::v64i8, 9 }, 2281 { ISD::SADDSAT, MVT::v32i16, 1 }, 2282 { ISD::SADDSAT, MVT::v64i8, 1 }, 2283 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2284 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2285 { ISD::UADDSAT, MVT::v32i16, 1 }, 2286 { ISD::UADDSAT, MVT::v64i8, 1 }, 2287 { ISD::USUBSAT, MVT::v32i16, 1 }, 2288 { ISD::USUBSAT, MVT::v64i8, 1 }, 2289 }; 2290 static const CostTblEntry AVX512CostTbl[] = { 2291 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2292 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2293 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2294 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2295 { ISD::CTLZ, MVT::v8i64, 29 }, 2296 { ISD::CTLZ, MVT::v16i32, 35 }, 2297 { ISD::CTLZ, MVT::v32i16, 28 }, 2298 { ISD::CTLZ, MVT::v64i8, 18 }, 2299 { ISD::CTPOP, MVT::v8i64, 16 }, 2300 { ISD::CTPOP, MVT::v16i32, 24 }, 2301 { ISD::CTPOP, MVT::v32i16, 18 }, 2302 { ISD::CTPOP, MVT::v64i8, 12 }, 2303 { ISD::CTTZ, MVT::v8i64, 20 }, 2304 { ISD::CTTZ, MVT::v16i32, 28 }, 2305 { ISD::CTTZ, MVT::v32i16, 24 }, 2306 { ISD::CTTZ, MVT::v64i8, 18 }, 2307 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2308 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2309 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2310 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2311 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2312 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2313 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2314 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2315 { ISD::SADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2316 { ISD::SADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2317 { ISD::SSUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2318 { ISD::SSUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2319 { ISD::UADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2320 { ISD::UADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2321 { ISD::USUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2322 { ISD::USUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2323 { ISD::FMAXNUM, MVT::f32, 2 }, 2324 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2325 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2326 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2327 { ISD::FMAXNUM, MVT::f64, 2 }, 2328 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2329 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2330 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2331 }; 2332 static const CostTblEntry XOPCostTbl[] = { 2333 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2334 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2335 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2336 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2337 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2338 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2339 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2340 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2341 { ISD::BITREVERSE, MVT::i64, 3 }, 2342 { ISD::BITREVERSE, MVT::i32, 3 }, 2343 { ISD::BITREVERSE, MVT::i16, 3 }, 2344 { ISD::BITREVERSE, MVT::i8, 3 } 2345 }; 2346 static const CostTblEntry AVX2CostTbl[] = { 2347 { ISD::BITREVERSE, MVT::v4i64, 5 }, 2348 { ISD::BITREVERSE, MVT::v8i32, 5 }, 2349 { ISD::BITREVERSE, MVT::v16i16, 5 }, 2350 { ISD::BITREVERSE, MVT::v32i8, 5 }, 2351 { ISD::BSWAP, MVT::v4i64, 1 }, 2352 { ISD::BSWAP, MVT::v8i32, 1 }, 2353 { ISD::BSWAP, MVT::v16i16, 1 }, 2354 { ISD::CTLZ, MVT::v4i64, 23 }, 2355 { ISD::CTLZ, MVT::v8i32, 18 }, 2356 { ISD::CTLZ, MVT::v16i16, 14 }, 2357 { ISD::CTLZ, MVT::v32i8, 9 }, 2358 { ISD::CTPOP, MVT::v4i64, 7 }, 2359 { ISD::CTPOP, MVT::v8i32, 11 }, 2360 { ISD::CTPOP, MVT::v16i16, 9 }, 2361 { ISD::CTPOP, MVT::v32i8, 6 }, 2362 { ISD::CTTZ, MVT::v4i64, 10 }, 2363 { ISD::CTTZ, MVT::v8i32, 14 }, 2364 { ISD::CTTZ, MVT::v16i16, 12 }, 2365 { ISD::CTTZ, MVT::v32i8, 9 }, 2366 { ISD::SADDSAT, MVT::v16i16, 1 }, 2367 { ISD::SADDSAT, MVT::v32i8, 1 }, 2368 { ISD::SSUBSAT, MVT::v16i16, 1 }, 2369 { ISD::SSUBSAT, MVT::v32i8, 1 }, 2370 { ISD::UADDSAT, MVT::v16i16, 1 }, 2371 { ISD::UADDSAT, MVT::v32i8, 1 }, 2372 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 2373 { ISD::USUBSAT, MVT::v16i16, 1 }, 2374 { ISD::USUBSAT, MVT::v32i8, 1 }, 2375 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2376 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2377 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2378 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2379 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2380 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2381 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2382 }; 2383 static const CostTblEntry AVX1CostTbl[] = { 2384 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 2385 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 2386 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 2387 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 2388 { ISD::BSWAP, MVT::v4i64, 4 }, 2389 { ISD::BSWAP, MVT::v8i32, 4 }, 2390 { ISD::BSWAP, MVT::v16i16, 4 }, 2391 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 2392 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 2393 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 2394 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2395 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 2396 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 2397 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 2398 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 2399 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 2400 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 2401 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 2402 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2403 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2404 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2405 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2406 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2407 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2408 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2409 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 2410 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2411 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2412 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 2413 { ISD::FMAXNUM, MVT::f32, 3 }, 2414 { ISD::FMAXNUM, MVT::v4f32, 3 }, 2415 { ISD::FMAXNUM, MVT::v8f32, 5 }, 2416 { ISD::FMAXNUM, MVT::f64, 3 }, 2417 { ISD::FMAXNUM, MVT::v2f64, 3 }, 2418 { ISD::FMAXNUM, MVT::v4f64, 5 }, 2419 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 2420 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 2421 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 2422 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 2423 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 2424 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 2425 }; 2426 static const CostTblEntry GLMCostTbl[] = { 2427 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 2428 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 2429 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 2430 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 2431 }; 2432 static const CostTblEntry SLMCostTbl[] = { 2433 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 2434 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 2435 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 2436 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 2437 }; 2438 static const CostTblEntry SSE42CostTbl[] = { 2439 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 2440 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 2441 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 2442 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 2443 }; 2444 static const CostTblEntry SSSE3CostTbl[] = { 2445 { ISD::BITREVERSE, MVT::v2i64, 5 }, 2446 { ISD::BITREVERSE, MVT::v4i32, 5 }, 2447 { ISD::BITREVERSE, MVT::v8i16, 5 }, 2448 { ISD::BITREVERSE, MVT::v16i8, 5 }, 2449 { ISD::BSWAP, MVT::v2i64, 1 }, 2450 { ISD::BSWAP, MVT::v4i32, 1 }, 2451 { ISD::BSWAP, MVT::v8i16, 1 }, 2452 { ISD::CTLZ, MVT::v2i64, 23 }, 2453 { ISD::CTLZ, MVT::v4i32, 18 }, 2454 { ISD::CTLZ, MVT::v8i16, 14 }, 2455 { ISD::CTLZ, MVT::v16i8, 9 }, 2456 { ISD::CTPOP, MVT::v2i64, 7 }, 2457 { ISD::CTPOP, MVT::v4i32, 11 }, 2458 { ISD::CTPOP, MVT::v8i16, 9 }, 2459 { ISD::CTPOP, MVT::v16i8, 6 }, 2460 { ISD::CTTZ, MVT::v2i64, 10 }, 2461 { ISD::CTTZ, MVT::v4i32, 14 }, 2462 { ISD::CTTZ, MVT::v8i16, 12 }, 2463 { ISD::CTTZ, MVT::v16i8, 9 } 2464 }; 2465 static const CostTblEntry SSE2CostTbl[] = { 2466 { ISD::BITREVERSE, MVT::v2i64, 29 }, 2467 { ISD::BITREVERSE, MVT::v4i32, 27 }, 2468 { ISD::BITREVERSE, MVT::v8i16, 27 }, 2469 { ISD::BITREVERSE, MVT::v16i8, 20 }, 2470 { ISD::BSWAP, MVT::v2i64, 7 }, 2471 { ISD::BSWAP, MVT::v4i32, 7 }, 2472 { ISD::BSWAP, MVT::v8i16, 7 }, 2473 { ISD::CTLZ, MVT::v2i64, 25 }, 2474 { ISD::CTLZ, MVT::v4i32, 26 }, 2475 { ISD::CTLZ, MVT::v8i16, 20 }, 2476 { ISD::CTLZ, MVT::v16i8, 17 }, 2477 { ISD::CTPOP, MVT::v2i64, 12 }, 2478 { ISD::CTPOP, MVT::v4i32, 15 }, 2479 { ISD::CTPOP, MVT::v8i16, 13 }, 2480 { ISD::CTPOP, MVT::v16i8, 10 }, 2481 { ISD::CTTZ, MVT::v2i64, 14 }, 2482 { ISD::CTTZ, MVT::v4i32, 18 }, 2483 { ISD::CTTZ, MVT::v8i16, 16 }, 2484 { ISD::CTTZ, MVT::v16i8, 13 }, 2485 { ISD::SADDSAT, MVT::v8i16, 1 }, 2486 { ISD::SADDSAT, MVT::v16i8, 1 }, 2487 { ISD::SSUBSAT, MVT::v8i16, 1 }, 2488 { ISD::SSUBSAT, MVT::v16i8, 1 }, 2489 { ISD::UADDSAT, MVT::v8i16, 1 }, 2490 { ISD::UADDSAT, MVT::v16i8, 1 }, 2491 { ISD::USUBSAT, MVT::v8i16, 1 }, 2492 { ISD::USUBSAT, MVT::v16i8, 1 }, 2493 { ISD::FMAXNUM, MVT::f64, 4 }, 2494 { ISD::FMAXNUM, MVT::v2f64, 4 }, 2495 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 2496 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 2497 }; 2498 static const CostTblEntry SSE1CostTbl[] = { 2499 { ISD::FMAXNUM, MVT::f32, 4 }, 2500 { ISD::FMAXNUM, MVT::v4f32, 4 }, 2501 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 2502 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 2503 }; 2504 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 2505 { ISD::CTTZ, MVT::i64, 1 }, 2506 }; 2507 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 2508 { ISD::CTTZ, MVT::i32, 1 }, 2509 { ISD::CTTZ, MVT::i16, 1 }, 2510 { ISD::CTTZ, MVT::i8, 1 }, 2511 }; 2512 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 2513 { ISD::CTLZ, MVT::i64, 1 }, 2514 }; 2515 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 2516 { ISD::CTLZ, MVT::i32, 1 }, 2517 { ISD::CTLZ, MVT::i16, 1 }, 2518 { ISD::CTLZ, MVT::i8, 1 }, 2519 }; 2520 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 2521 { ISD::CTPOP, MVT::i64, 1 }, 2522 }; 2523 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 2524 { ISD::CTPOP, MVT::i32, 1 }, 2525 { ISD::CTPOP, MVT::i16, 1 }, 2526 { ISD::CTPOP, MVT::i8, 1 }, 2527 }; 2528 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2529 { ISD::BITREVERSE, MVT::i64, 14 }, 2530 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 2531 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 2532 { ISD::CTPOP, MVT::i64, 10 }, 2533 { ISD::SADDO, MVT::i64, 1 }, 2534 { ISD::UADDO, MVT::i64, 1 }, 2535 }; 2536 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2537 { ISD::BITREVERSE, MVT::i32, 14 }, 2538 { ISD::BITREVERSE, MVT::i16, 14 }, 2539 { ISD::BITREVERSE, MVT::i8, 11 }, 2540 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 2541 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 2542 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 2543 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 2544 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 2545 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 2546 { ISD::CTPOP, MVT::i32, 8 }, 2547 { ISD::CTPOP, MVT::i16, 9 }, 2548 { ISD::CTPOP, MVT::i8, 7 }, 2549 { ISD::SADDO, MVT::i32, 1 }, 2550 { ISD::SADDO, MVT::i16, 1 }, 2551 { ISD::SADDO, MVT::i8, 1 }, 2552 { ISD::UADDO, MVT::i32, 1 }, 2553 { ISD::UADDO, MVT::i16, 1 }, 2554 { ISD::UADDO, MVT::i8, 1 }, 2555 }; 2556 2557 Type *RetTy = ICA.getReturnType(); 2558 Type *OpTy = RetTy; 2559 Intrinsic::ID IID = ICA.getID(); 2560 unsigned ISD = ISD::DELETED_NODE; 2561 switch (IID) { 2562 default: 2563 break; 2564 case Intrinsic::bitreverse: 2565 ISD = ISD::BITREVERSE; 2566 break; 2567 case Intrinsic::bswap: 2568 ISD = ISD::BSWAP; 2569 break; 2570 case Intrinsic::ctlz: 2571 ISD = ISD::CTLZ; 2572 break; 2573 case Intrinsic::ctpop: 2574 ISD = ISD::CTPOP; 2575 break; 2576 case Intrinsic::cttz: 2577 ISD = ISD::CTTZ; 2578 break; 2579 case Intrinsic::maxnum: 2580 case Intrinsic::minnum: 2581 // FMINNUM has same costs so don't duplicate. 2582 ISD = ISD::FMAXNUM; 2583 break; 2584 case Intrinsic::sadd_sat: 2585 ISD = ISD::SADDSAT; 2586 break; 2587 case Intrinsic::ssub_sat: 2588 ISD = ISD::SSUBSAT; 2589 break; 2590 case Intrinsic::uadd_sat: 2591 ISD = ISD::UADDSAT; 2592 break; 2593 case Intrinsic::usub_sat: 2594 ISD = ISD::USUBSAT; 2595 break; 2596 case Intrinsic::sqrt: 2597 ISD = ISD::FSQRT; 2598 break; 2599 case Intrinsic::sadd_with_overflow: 2600 case Intrinsic::ssub_with_overflow: 2601 // SSUBO has same costs so don't duplicate. 2602 ISD = ISD::SADDO; 2603 OpTy = RetTy->getContainedType(0); 2604 break; 2605 case Intrinsic::uadd_with_overflow: 2606 case Intrinsic::usub_with_overflow: 2607 // USUBO has same costs so don't duplicate. 2608 ISD = ISD::UADDO; 2609 OpTy = RetTy->getContainedType(0); 2610 break; 2611 } 2612 2613 if (ISD != ISD::DELETED_NODE) { 2614 // Legalize the type. 2615 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 2616 MVT MTy = LT.second; 2617 2618 // Attempt to lookup cost. 2619 if (ST->useGLMDivSqrtCosts()) 2620 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 2621 return LT.first * Entry->Cost; 2622 2623 if (ST->isSLM()) 2624 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2625 return LT.first * Entry->Cost; 2626 2627 if (ST->hasCDI()) 2628 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 2629 return LT.first * Entry->Cost; 2630 2631 if (ST->hasBWI()) 2632 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2633 return LT.first * Entry->Cost; 2634 2635 if (ST->hasAVX512()) 2636 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2637 return LT.first * Entry->Cost; 2638 2639 if (ST->hasXOP()) 2640 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2641 return LT.first * Entry->Cost; 2642 2643 if (ST->hasAVX2()) 2644 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2645 return LT.first * Entry->Cost; 2646 2647 if (ST->hasAVX()) 2648 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2649 return LT.first * Entry->Cost; 2650 2651 if (ST->hasSSE42()) 2652 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2653 return LT.first * Entry->Cost; 2654 2655 if (ST->hasSSSE3()) 2656 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 2657 return LT.first * Entry->Cost; 2658 2659 if (ST->hasSSE2()) 2660 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2661 return LT.first * Entry->Cost; 2662 2663 if (ST->hasSSE1()) 2664 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2665 return LT.first * Entry->Cost; 2666 2667 if (ST->hasBMI()) { 2668 if (ST->is64Bit()) 2669 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 2670 return LT.first * Entry->Cost; 2671 2672 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 2673 return LT.first * Entry->Cost; 2674 } 2675 2676 if (ST->hasLZCNT()) { 2677 if (ST->is64Bit()) 2678 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 2679 return LT.first * Entry->Cost; 2680 2681 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 2682 return LT.first * Entry->Cost; 2683 } 2684 2685 if (ST->hasPOPCNT()) { 2686 if (ST->is64Bit()) 2687 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 2688 return LT.first * Entry->Cost; 2689 2690 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 2691 return LT.first * Entry->Cost; 2692 } 2693 2694 // TODO - add BMI (TZCNT) scalar handling 2695 2696 if (ST->is64Bit()) 2697 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2698 return LT.first * Entry->Cost; 2699 2700 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2701 return LT.first * Entry->Cost; 2702 } 2703 2704 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 2705 } 2706 2707 int X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 2708 TTI::TargetCostKind CostKind) { 2709 if (CostKind != TTI::TCK_RecipThroughput) 2710 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 2711 2712 if (ICA.isTypeBasedOnly()) 2713 return getTypeBasedIntrinsicInstrCost(ICA, CostKind); 2714 2715 static const CostTblEntry AVX512CostTbl[] = { 2716 { ISD::ROTL, MVT::v8i64, 1 }, 2717 { ISD::ROTL, MVT::v4i64, 1 }, 2718 { ISD::ROTL, MVT::v2i64, 1 }, 2719 { ISD::ROTL, MVT::v16i32, 1 }, 2720 { ISD::ROTL, MVT::v8i32, 1 }, 2721 { ISD::ROTL, MVT::v4i32, 1 }, 2722 { ISD::ROTR, MVT::v8i64, 1 }, 2723 { ISD::ROTR, MVT::v4i64, 1 }, 2724 { ISD::ROTR, MVT::v2i64, 1 }, 2725 { ISD::ROTR, MVT::v16i32, 1 }, 2726 { ISD::ROTR, MVT::v8i32, 1 }, 2727 { ISD::ROTR, MVT::v4i32, 1 } 2728 }; 2729 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 2730 static const CostTblEntry XOPCostTbl[] = { 2731 { ISD::ROTL, MVT::v4i64, 4 }, 2732 { ISD::ROTL, MVT::v8i32, 4 }, 2733 { ISD::ROTL, MVT::v16i16, 4 }, 2734 { ISD::ROTL, MVT::v32i8, 4 }, 2735 { ISD::ROTL, MVT::v2i64, 1 }, 2736 { ISD::ROTL, MVT::v4i32, 1 }, 2737 { ISD::ROTL, MVT::v8i16, 1 }, 2738 { ISD::ROTL, MVT::v16i8, 1 }, 2739 { ISD::ROTR, MVT::v4i64, 6 }, 2740 { ISD::ROTR, MVT::v8i32, 6 }, 2741 { ISD::ROTR, MVT::v16i16, 6 }, 2742 { ISD::ROTR, MVT::v32i8, 6 }, 2743 { ISD::ROTR, MVT::v2i64, 2 }, 2744 { ISD::ROTR, MVT::v4i32, 2 }, 2745 { ISD::ROTR, MVT::v8i16, 2 }, 2746 { ISD::ROTR, MVT::v16i8, 2 } 2747 }; 2748 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2749 { ISD::ROTL, MVT::i64, 1 }, 2750 { ISD::ROTR, MVT::i64, 1 }, 2751 { ISD::FSHL, MVT::i64, 4 } 2752 }; 2753 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2754 { ISD::ROTL, MVT::i32, 1 }, 2755 { ISD::ROTL, MVT::i16, 1 }, 2756 { ISD::ROTL, MVT::i8, 1 }, 2757 { ISD::ROTR, MVT::i32, 1 }, 2758 { ISD::ROTR, MVT::i16, 1 }, 2759 { ISD::ROTR, MVT::i8, 1 }, 2760 { ISD::FSHL, MVT::i32, 4 }, 2761 { ISD::FSHL, MVT::i16, 4 }, 2762 { ISD::FSHL, MVT::i8, 4 } 2763 }; 2764 2765 Intrinsic::ID IID = ICA.getID(); 2766 Type *RetTy = ICA.getReturnType(); 2767 const SmallVectorImpl<Value *> &Args = ICA.getArgs(); 2768 unsigned ISD = ISD::DELETED_NODE; 2769 switch (IID) { 2770 default: 2771 break; 2772 case Intrinsic::fshl: 2773 ISD = ISD::FSHL; 2774 if (Args[0] == Args[1]) 2775 ISD = ISD::ROTL; 2776 break; 2777 case Intrinsic::fshr: 2778 // FSHR has same costs so don't duplicate. 2779 ISD = ISD::FSHL; 2780 if (Args[0] == Args[1]) 2781 ISD = ISD::ROTR; 2782 break; 2783 } 2784 2785 if (ISD != ISD::DELETED_NODE) { 2786 // Legalize the type. 2787 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 2788 MVT MTy = LT.second; 2789 2790 // Attempt to lookup cost. 2791 if (ST->hasAVX512()) 2792 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2793 return LT.first * Entry->Cost; 2794 2795 if (ST->hasXOP()) 2796 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2797 return LT.first * Entry->Cost; 2798 2799 if (ST->is64Bit()) 2800 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2801 return LT.first * Entry->Cost; 2802 2803 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2804 return LT.first * Entry->Cost; 2805 } 2806 2807 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 2808 } 2809 2810 int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { 2811 static const CostTblEntry SLMCostTbl[] = { 2812 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 2813 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 2814 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 2815 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 2816 }; 2817 2818 assert(Val->isVectorTy() && "This must be a vector type"); 2819 Type *ScalarType = Val->getScalarType(); 2820 int RegisterFileMoveCost = 0; 2821 2822 if (Index != -1U && (Opcode == Instruction::ExtractElement || 2823 Opcode == Instruction::InsertElement)) { 2824 // Legalize the type. 2825 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 2826 2827 // This type is legalized to a scalar type. 2828 if (!LT.second.isVector()) 2829 return 0; 2830 2831 // The type may be split. Normalize the index to the new type. 2832 unsigned NumElts = LT.second.getVectorNumElements(); 2833 unsigned SubNumElts = NumElts; 2834 Index = Index % NumElts; 2835 2836 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 2837 // For inserts, we also need to insert the subvector back. 2838 if (LT.second.getSizeInBits() > 128) { 2839 assert((LT.second.getSizeInBits() % 128) == 0 && "Illegal vector"); 2840 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 2841 SubNumElts = NumElts / NumSubVecs; 2842 if (SubNumElts <= Index) { 2843 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 2844 Index %= SubNumElts; 2845 } 2846 } 2847 2848 if (Index == 0) { 2849 // Floating point scalars are already located in index #0. 2850 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 2851 // true for all. 2852 if (ScalarType->isFloatingPointTy()) 2853 return RegisterFileMoveCost; 2854 2855 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 2856 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 2857 return 1 + RegisterFileMoveCost; 2858 } 2859 2860 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2861 assert(ISD && "Unexpected vector opcode"); 2862 MVT MScalarTy = LT.second.getScalarType(); 2863 if (ST->isSLM()) 2864 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 2865 return Entry->Cost + RegisterFileMoveCost; 2866 2867 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 2868 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 2869 (MScalarTy.isInteger() && ST->hasSSE41())) 2870 return 1 + RegisterFileMoveCost; 2871 2872 // Assume insertps is relatively cheap on all targets. 2873 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 2874 Opcode == Instruction::InsertElement) 2875 return 1 + RegisterFileMoveCost; 2876 2877 // For extractions we just need to shuffle the element to index 0, which 2878 // should be very cheap (assume cost = 1). For insertions we need to shuffle 2879 // the elements to its destination. In both cases we must handle the 2880 // subvector move(s). 2881 // If the vector type is already less than 128-bits then don't reduce it. 2882 // TODO: Under what circumstances should we shuffle using the full width? 2883 int ShuffleCost = 1; 2884 if (Opcode == Instruction::InsertElement) { 2885 auto *SubTy = cast<VectorType>(Val); 2886 EVT VT = TLI->getValueType(DL, Val); 2887 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 2888 SubTy = VectorType::get(ScalarType, SubNumElts); 2889 ShuffleCost = getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, 0, SubTy); 2890 } 2891 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 2892 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 2893 } 2894 2895 // Add to the base cost if we know that the extracted element of a vector is 2896 // destined to be moved to and used in the integer register file. 2897 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 2898 RegisterFileMoveCost += 1; 2899 2900 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 2901 } 2902 2903 unsigned X86TTIImpl::getScalarizationOverhead(VectorType *Ty, 2904 const APInt &DemandedElts, 2905 bool Insert, bool Extract) { 2906 unsigned Cost = 0; 2907 2908 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much 2909 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT. 2910 if (Insert) { 2911 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 2912 MVT MScalarTy = LT.second.getScalarType(); 2913 2914 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 2915 (MScalarTy.isInteger() && ST->hasSSE41()) || 2916 (MScalarTy == MVT::f32 && ST->hasSSE41())) { 2917 // For types we can insert directly, insertion into 128-bit sub vectors is 2918 // cheap, followed by a cheap chain of concatenations. 2919 if (LT.second.getSizeInBits() <= 128) { 2920 Cost += 2921 BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, false); 2922 } else { 2923 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 2924 Cost += (PowerOf2Ceil(NumSubVecs) - 1) * LT.first; 2925 Cost += DemandedElts.countPopulation(); 2926 2927 // For vXf32 cases, insertion into the 0'th index in each v4f32 2928 // 128-bit vector is free. 2929 // NOTE: This assumes legalization widens vXf32 vectors. 2930 if (MScalarTy == MVT::f32) 2931 for (unsigned i = 0, e = Ty->getNumElements(); i < e; i += 4) 2932 if (DemandedElts[i]) 2933 Cost--; 2934 } 2935 } else if (LT.second.isVector()) { 2936 // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded 2937 // integer element as a SCALAR_TO_VECTOR, then we build the vector as a 2938 // series of UNPCK followed by CONCAT_VECTORS - all of these can be 2939 // considered cheap. 2940 if (Ty->isIntOrIntVectorTy()) 2941 Cost += DemandedElts.countPopulation(); 2942 2943 // Get the smaller of the legalized or original pow2-extended number of 2944 // vector elements, which represents the number of unpacks we'll end up 2945 // performing. 2946 unsigned NumElts = LT.second.getVectorNumElements(); 2947 unsigned Pow2Elts = PowerOf2Ceil(Ty->getNumElements()); 2948 Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first; 2949 } 2950 } 2951 2952 // TODO: Use default extraction for now, but we should investigate extending this 2953 // to handle repeated subvector extraction. 2954 if (Extract) 2955 Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, false, Extract); 2956 2957 return Cost; 2958 } 2959 2960 int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 2961 MaybeAlign Alignment, unsigned AddressSpace, 2962 TTI::TargetCostKind CostKind, 2963 const Instruction *I) { 2964 // TODO: Handle other cost kinds. 2965 if (CostKind != TTI::TCK_RecipThroughput) { 2966 if (isa_and_nonnull<StoreInst>(I)) { 2967 Value *Ptr = I->getOperand(1); 2968 // Store instruction with index and scale costs 2 Uops. 2969 // Check the preceding GEP to identify non-const indices. 2970 if (auto *GEP = dyn_cast<GetElementPtrInst>(Ptr)) { 2971 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 2972 return TTI::TCC_Basic * 2; 2973 } 2974 } 2975 return TTI::TCC_Basic; 2976 } 2977 2978 // Handle non-power-of-two vectors such as <3 x float> 2979 if (VectorType *VTy = dyn_cast<VectorType>(Src)) { 2980 unsigned NumElem = VTy->getNumElements(); 2981 2982 // Handle a few common cases: 2983 // <3 x float> 2984 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 2985 // Cost = 64 bit store + extract + 32 bit store. 2986 return 3; 2987 2988 // <3 x double> 2989 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 2990 // Cost = 128 bit store + unpack + 64 bit store. 2991 return 3; 2992 2993 // Assume that all other non-power-of-two numbers are scalarized. 2994 if (!isPowerOf2_32(NumElem)) { 2995 APInt DemandedElts = APInt::getAllOnesValue(NumElem); 2996 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment, 2997 AddressSpace, CostKind); 2998 int SplitCost = getScalarizationOverhead(VTy, DemandedElts, 2999 Opcode == Instruction::Load, 3000 Opcode == Instruction::Store); 3001 return NumElem * Cost + SplitCost; 3002 } 3003 } 3004 3005 // Legalize the type. 3006 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 3007 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 3008 "Invalid Opcode"); 3009 3010 // Each load/store unit costs 1. 3011 int Cost = LT.first * 1; 3012 3013 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a 3014 // proxy for a double-pumped AVX memory interface such as on Sandybridge. 3015 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow()) 3016 Cost *= 2; 3017 3018 return Cost; 3019 } 3020 3021 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, 3022 unsigned Alignment, 3023 unsigned AddressSpace, 3024 TTI::TargetCostKind CostKind) { 3025 bool IsLoad = (Instruction::Load == Opcode); 3026 bool IsStore = (Instruction::Store == Opcode); 3027 3028 VectorType *SrcVTy = dyn_cast<VectorType>(SrcTy); 3029 if (!SrcVTy) 3030 // To calculate scalar take the regular cost, without mask 3031 return getMemoryOpCost(Opcode, SrcTy, MaybeAlign(Alignment), AddressSpace, 3032 CostKind); 3033 3034 unsigned NumElem = SrcVTy->getNumElements(); 3035 VectorType *MaskTy = 3036 VectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 3037 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, MaybeAlign(Alignment))) || 3038 (IsStore && !isLegalMaskedStore(SrcVTy, MaybeAlign(Alignment))) || 3039 !isPowerOf2_32(NumElem)) { 3040 // Scalarization 3041 APInt DemandedElts = APInt::getAllOnesValue(NumElem); 3042 int MaskSplitCost = 3043 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 3044 int ScalarCompareCost = getCmpSelInstrCost( 3045 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr, 3046 CostKind); 3047 int BranchCost = getCFInstrCost(Instruction::Br, CostKind); 3048 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 3049 int ValueSplitCost = 3050 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore); 3051 int MemopCost = 3052 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3053 MaybeAlign(Alignment), AddressSpace, 3054 CostKind); 3055 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 3056 } 3057 3058 // Legalize the type. 3059 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3060 auto VT = TLI->getValueType(DL, SrcVTy); 3061 int Cost = 0; 3062 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 3063 LT.second.getVectorNumElements() == NumElem) 3064 // Promotion requires expand/truncate for data and a shuffle for mask. 3065 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, 0, nullptr) + 3066 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, 0, nullptr); 3067 3068 else if (LT.second.getVectorNumElements() > NumElem) { 3069 VectorType *NewMaskTy = VectorType::get(MaskTy->getElementType(), 3070 LT.second.getVectorNumElements()); 3071 // Expanding requires fill mask with zeroes 3072 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, 0, MaskTy); 3073 } 3074 3075 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 3076 if (!ST->hasAVX512()) 3077 return Cost + LT.first * (IsLoad ? 2 : 8); 3078 3079 // AVX-512 masked load/store is cheapper 3080 return Cost + LT.first; 3081 } 3082 3083 int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE, 3084 const SCEV *Ptr) { 3085 // Address computations in vectorized code with non-consecutive addresses will 3086 // likely result in more instructions compared to scalar code where the 3087 // computation can more often be merged into the index mode. The resulting 3088 // extra micro-ops can significantly decrease throughput. 3089 const unsigned NumVectorInstToHideOverhead = 10; 3090 3091 // Cost modeling of Strided Access Computation is hidden by the indexing 3092 // modes of X86 regardless of the stride value. We dont believe that there 3093 // is a difference between constant strided access in gerenal and constant 3094 // strided value which is less than or equal to 64. 3095 // Even in the case of (loop invariant) stride whose value is not known at 3096 // compile time, the address computation will not incur more than one extra 3097 // ADD instruction. 3098 if (Ty->isVectorTy() && SE) { 3099 if (!BaseT::isStridedAccess(Ptr)) 3100 return NumVectorInstToHideOverhead; 3101 if (!BaseT::getConstantStrideStep(SE, Ptr)) 3102 return 1; 3103 } 3104 3105 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 3106 } 3107 3108 int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 3109 bool IsPairwise, 3110 TTI::TargetCostKind CostKind) { 3111 // Just use the default implementation for pair reductions. 3112 if (IsPairwise) 3113 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise, CostKind); 3114 3115 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3116 // and make it as the cost. 3117 3118 static const CostTblEntry SLMCostTblNoPairWise[] = { 3119 { ISD::FADD, MVT::v2f64, 3 }, 3120 { ISD::ADD, MVT::v2i64, 5 }, 3121 }; 3122 3123 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3124 { ISD::FADD, MVT::v2f64, 2 }, 3125 { ISD::FADD, MVT::v4f32, 4 }, 3126 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 3127 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 3128 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 3129 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 3130 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 3131 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 3132 { ISD::ADD, MVT::v2i8, 2 }, 3133 { ISD::ADD, MVT::v4i8, 2 }, 3134 { ISD::ADD, MVT::v8i8, 2 }, 3135 { ISD::ADD, MVT::v16i8, 3 }, 3136 }; 3137 3138 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3139 { ISD::FADD, MVT::v4f64, 3 }, 3140 { ISD::FADD, MVT::v4f32, 3 }, 3141 { ISD::FADD, MVT::v8f32, 4 }, 3142 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 3143 { ISD::ADD, MVT::v4i64, 3 }, 3144 { ISD::ADD, MVT::v8i32, 5 }, 3145 { ISD::ADD, MVT::v16i16, 5 }, 3146 { ISD::ADD, MVT::v32i8, 4 }, 3147 }; 3148 3149 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3150 assert(ISD && "Invalid opcode"); 3151 3152 // Before legalizing the type, give a chance to look up illegal narrow types 3153 // in the table. 3154 // FIXME: Is there a better way to do this? 3155 EVT VT = TLI->getValueType(DL, ValTy); 3156 if (VT.isSimple()) { 3157 MVT MTy = VT.getSimpleVT(); 3158 if (ST->isSLM()) 3159 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3160 return Entry->Cost; 3161 3162 if (ST->hasAVX()) 3163 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3164 return Entry->Cost; 3165 3166 if (ST->hasSSE2()) 3167 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3168 return Entry->Cost; 3169 } 3170 3171 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3172 3173 MVT MTy = LT.second; 3174 3175 auto *ValVTy = cast<VectorType>(ValTy); 3176 3177 unsigned ArithmeticCost = 0; 3178 if (LT.first != 1 && MTy.isVector() && 3179 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3180 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3181 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3182 MTy.getVectorNumElements()); 3183 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3184 ArithmeticCost *= LT.first - 1; 3185 } 3186 3187 if (ST->isSLM()) 3188 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3189 return ArithmeticCost + Entry->Cost; 3190 3191 if (ST->hasAVX()) 3192 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3193 return ArithmeticCost + Entry->Cost; 3194 3195 if (ST->hasSSE2()) 3196 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3197 return ArithmeticCost + Entry->Cost; 3198 3199 // FIXME: These assume a naive kshift+binop lowering, which is probably 3200 // conservative in most cases. 3201 static const CostTblEntry AVX512BoolReduction[] = { 3202 { ISD::AND, MVT::v2i1, 3 }, 3203 { ISD::AND, MVT::v4i1, 5 }, 3204 { ISD::AND, MVT::v8i1, 7 }, 3205 { ISD::AND, MVT::v16i1, 9 }, 3206 { ISD::AND, MVT::v32i1, 11 }, 3207 { ISD::AND, MVT::v64i1, 13 }, 3208 { ISD::OR, MVT::v2i1, 3 }, 3209 { ISD::OR, MVT::v4i1, 5 }, 3210 { ISD::OR, MVT::v8i1, 7 }, 3211 { ISD::OR, MVT::v16i1, 9 }, 3212 { ISD::OR, MVT::v32i1, 11 }, 3213 { ISD::OR, MVT::v64i1, 13 }, 3214 }; 3215 3216 static const CostTblEntry AVX2BoolReduction[] = { 3217 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 3218 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 3219 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 3220 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 3221 }; 3222 3223 static const CostTblEntry AVX1BoolReduction[] = { 3224 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 3225 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 3226 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3227 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3228 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 3229 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 3230 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3231 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3232 }; 3233 3234 static const CostTblEntry SSE2BoolReduction[] = { 3235 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 3236 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 3237 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 3238 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 3239 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 3240 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 3241 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 3242 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 3243 }; 3244 3245 // Handle bool allof/anyof patterns. 3246 if (ValVTy->getElementType()->isIntegerTy(1)) { 3247 unsigned ArithmeticCost = 0; 3248 if (LT.first != 1 && MTy.isVector() && 3249 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3250 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3251 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3252 MTy.getVectorNumElements()); 3253 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3254 ArithmeticCost *= LT.first - 1; 3255 } 3256 3257 if (ST->hasAVX512()) 3258 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 3259 return ArithmeticCost + Entry->Cost; 3260 if (ST->hasAVX2()) 3261 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 3262 return ArithmeticCost + Entry->Cost; 3263 if (ST->hasAVX()) 3264 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 3265 return ArithmeticCost + Entry->Cost; 3266 if (ST->hasSSE2()) 3267 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 3268 return ArithmeticCost + Entry->Cost; 3269 3270 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise, 3271 CostKind); 3272 } 3273 3274 unsigned NumVecElts = ValVTy->getNumElements(); 3275 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 3276 3277 // Special case power of 2 reductions where the scalar type isn't changed 3278 // by type legalization. 3279 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 3280 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise, 3281 CostKind); 3282 3283 unsigned ReductionCost = 0; 3284 3285 auto *Ty = ValVTy; 3286 if (LT.first != 1 && MTy.isVector() && 3287 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3288 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3289 Ty = VectorType::get(ValVTy->getElementType(), MTy.getVectorNumElements()); 3290 ReductionCost = getArithmeticInstrCost(Opcode, Ty, CostKind); 3291 ReductionCost *= LT.first - 1; 3292 NumVecElts = MTy.getVectorNumElements(); 3293 } 3294 3295 // Now handle reduction with the legal type, taking into account size changes 3296 // at each level. 3297 while (NumVecElts > 1) { 3298 // Determine the size of the remaining vector we need to reduce. 3299 unsigned Size = NumVecElts * ScalarSize; 3300 NumVecElts /= 2; 3301 // If we're reducing from 256/512 bits, use an extract_subvector. 3302 if (Size > 128) { 3303 auto *SubTy = VectorType::get(ValVTy->getElementType(), NumVecElts); 3304 ReductionCost += 3305 getShuffleCost(TTI::SK_ExtractSubvector, Ty, NumVecElts, SubTy); 3306 Ty = SubTy; 3307 } else if (Size == 128) { 3308 // Reducing from 128 bits is a permute of v2f64/v2i64. 3309 VectorType *ShufTy; 3310 if (ValVTy->isFloatingPointTy()) 3311 ShufTy = VectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 3312 else 3313 ShufTy = VectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 3314 ReductionCost += 3315 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3316 } else if (Size == 64) { 3317 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3318 VectorType *ShufTy; 3319 if (ValVTy->isFloatingPointTy()) 3320 ShufTy = VectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 3321 else 3322 ShufTy = VectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 3323 ReductionCost += 3324 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3325 } else { 3326 // Reducing from smaller size is a shift by immediate. 3327 auto *ShiftTy = FixedVectorType::get( 3328 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 3329 ReductionCost += getArithmeticInstrCost( 3330 Instruction::LShr, ShiftTy, CostKind, 3331 TargetTransformInfo::OK_AnyValue, 3332 TargetTransformInfo::OK_UniformConstantValue, 3333 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3334 } 3335 3336 // Add the arithmetic op for this level. 3337 ReductionCost += getArithmeticInstrCost(Opcode, Ty, CostKind); 3338 } 3339 3340 // Add the final extract element to the cost. 3341 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3342 } 3343 3344 int X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, bool IsUnsigned) { 3345 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3346 3347 MVT MTy = LT.second; 3348 3349 int ISD; 3350 if (Ty->isIntOrIntVectorTy()) { 3351 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3352 } else { 3353 assert(Ty->isFPOrFPVectorTy() && 3354 "Expected float point or integer vector type."); 3355 ISD = ISD::FMINNUM; 3356 } 3357 3358 static const CostTblEntry SSE1CostTbl[] = { 3359 {ISD::FMINNUM, MVT::v4f32, 1}, 3360 }; 3361 3362 static const CostTblEntry SSE2CostTbl[] = { 3363 {ISD::FMINNUM, MVT::v2f64, 1}, 3364 {ISD::SMIN, MVT::v8i16, 1}, 3365 {ISD::UMIN, MVT::v16i8, 1}, 3366 }; 3367 3368 static const CostTblEntry SSE41CostTbl[] = { 3369 {ISD::SMIN, MVT::v4i32, 1}, 3370 {ISD::UMIN, MVT::v4i32, 1}, 3371 {ISD::UMIN, MVT::v8i16, 1}, 3372 {ISD::SMIN, MVT::v16i8, 1}, 3373 }; 3374 3375 static const CostTblEntry SSE42CostTbl[] = { 3376 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 3377 }; 3378 3379 static const CostTblEntry AVX1CostTbl[] = { 3380 {ISD::FMINNUM, MVT::v8f32, 1}, 3381 {ISD::FMINNUM, MVT::v4f64, 1}, 3382 {ISD::SMIN, MVT::v8i32, 3}, 3383 {ISD::UMIN, MVT::v8i32, 3}, 3384 {ISD::SMIN, MVT::v16i16, 3}, 3385 {ISD::UMIN, MVT::v16i16, 3}, 3386 {ISD::SMIN, MVT::v32i8, 3}, 3387 {ISD::UMIN, MVT::v32i8, 3}, 3388 }; 3389 3390 static const CostTblEntry AVX2CostTbl[] = { 3391 {ISD::SMIN, MVT::v8i32, 1}, 3392 {ISD::UMIN, MVT::v8i32, 1}, 3393 {ISD::SMIN, MVT::v16i16, 1}, 3394 {ISD::UMIN, MVT::v16i16, 1}, 3395 {ISD::SMIN, MVT::v32i8, 1}, 3396 {ISD::UMIN, MVT::v32i8, 1}, 3397 }; 3398 3399 static const CostTblEntry AVX512CostTbl[] = { 3400 {ISD::FMINNUM, MVT::v16f32, 1}, 3401 {ISD::FMINNUM, MVT::v8f64, 1}, 3402 {ISD::SMIN, MVT::v2i64, 1}, 3403 {ISD::UMIN, MVT::v2i64, 1}, 3404 {ISD::SMIN, MVT::v4i64, 1}, 3405 {ISD::UMIN, MVT::v4i64, 1}, 3406 {ISD::SMIN, MVT::v8i64, 1}, 3407 {ISD::UMIN, MVT::v8i64, 1}, 3408 {ISD::SMIN, MVT::v16i32, 1}, 3409 {ISD::UMIN, MVT::v16i32, 1}, 3410 }; 3411 3412 static const CostTblEntry AVX512BWCostTbl[] = { 3413 {ISD::SMIN, MVT::v32i16, 1}, 3414 {ISD::UMIN, MVT::v32i16, 1}, 3415 {ISD::SMIN, MVT::v64i8, 1}, 3416 {ISD::UMIN, MVT::v64i8, 1}, 3417 }; 3418 3419 // If we have a native MIN/MAX instruction for this type, use it. 3420 if (ST->hasBWI()) 3421 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3422 return LT.first * Entry->Cost; 3423 3424 if (ST->hasAVX512()) 3425 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3426 return LT.first * Entry->Cost; 3427 3428 if (ST->hasAVX2()) 3429 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3430 return LT.first * Entry->Cost; 3431 3432 if (ST->hasAVX()) 3433 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3434 return LT.first * Entry->Cost; 3435 3436 if (ST->hasSSE42()) 3437 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3438 return LT.first * Entry->Cost; 3439 3440 if (ST->hasSSE41()) 3441 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3442 return LT.first * Entry->Cost; 3443 3444 if (ST->hasSSE2()) 3445 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3446 return LT.first * Entry->Cost; 3447 3448 if (ST->hasSSE1()) 3449 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3450 return LT.first * Entry->Cost; 3451 3452 unsigned CmpOpcode; 3453 if (Ty->isFPOrFPVectorTy()) { 3454 CmpOpcode = Instruction::FCmp; 3455 } else { 3456 assert(Ty->isIntOrIntVectorTy() && 3457 "expecting floating point or integer type for min/max reduction"); 3458 CmpOpcode = Instruction::ICmp; 3459 } 3460 3461 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 3462 // Otherwise fall back to cmp+select. 3463 return getCmpSelInstrCost(CmpOpcode, Ty, CondTy, CostKind) + 3464 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, CostKind); 3465 } 3466 3467 int X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 3468 bool IsPairwise, bool IsUnsigned, 3469 TTI::TargetCostKind CostKind) { 3470 // Just use the default implementation for pair reductions. 3471 if (IsPairwise) 3472 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned, 3473 CostKind); 3474 3475 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3476 3477 MVT MTy = LT.second; 3478 3479 int ISD; 3480 if (ValTy->isIntOrIntVectorTy()) { 3481 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3482 } else { 3483 assert(ValTy->isFPOrFPVectorTy() && 3484 "Expected float point or integer vector type."); 3485 ISD = ISD::FMINNUM; 3486 } 3487 3488 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3489 // and make it as the cost. 3490 3491 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3492 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 3493 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 3494 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 3495 }; 3496 3497 static const CostTblEntry SSE41CostTblNoPairWise[] = { 3498 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 3499 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 3500 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 3501 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 3502 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 3503 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 3504 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 3505 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 3506 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 3507 {ISD::SMIN, MVT::v16i8, 6}, 3508 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 3509 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 3510 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 3511 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 3512 }; 3513 3514 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3515 {ISD::SMIN, MVT::v16i16, 6}, 3516 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 3517 {ISD::SMIN, MVT::v32i8, 8}, 3518 {ISD::UMIN, MVT::v32i8, 8}, 3519 }; 3520 3521 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 3522 {ISD::SMIN, MVT::v32i16, 8}, 3523 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 3524 {ISD::SMIN, MVT::v64i8, 10}, 3525 {ISD::UMIN, MVT::v64i8, 10}, 3526 }; 3527 3528 // Before legalizing the type, give a chance to look up illegal narrow types 3529 // in the table. 3530 // FIXME: Is there a better way to do this? 3531 EVT VT = TLI->getValueType(DL, ValTy); 3532 if (VT.isSimple()) { 3533 MVT MTy = VT.getSimpleVT(); 3534 if (ST->hasBWI()) 3535 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3536 return Entry->Cost; 3537 3538 if (ST->hasAVX()) 3539 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3540 return Entry->Cost; 3541 3542 if (ST->hasSSE41()) 3543 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3544 return Entry->Cost; 3545 3546 if (ST->hasSSE2()) 3547 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3548 return Entry->Cost; 3549 } 3550 3551 auto *ValVTy = cast<VectorType>(ValTy); 3552 unsigned NumVecElts = ValVTy->getNumElements(); 3553 3554 auto *Ty = ValVTy; 3555 unsigned MinMaxCost = 0; 3556 if (LT.first != 1 && MTy.isVector() && 3557 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3558 // Type needs to be split. We need LT.first - 1 operations ops. 3559 Ty = VectorType::get(ValVTy->getElementType(), MTy.getVectorNumElements()); 3560 auto *SubCondTy = VectorType::get( 3561 cast<VectorType>(CondTy)->getElementType(), MTy.getVectorNumElements()); 3562 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3563 MinMaxCost *= LT.first - 1; 3564 NumVecElts = MTy.getVectorNumElements(); 3565 } 3566 3567 if (ST->hasBWI()) 3568 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3569 return MinMaxCost + Entry->Cost; 3570 3571 if (ST->hasAVX()) 3572 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3573 return MinMaxCost + Entry->Cost; 3574 3575 if (ST->hasSSE41()) 3576 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3577 return MinMaxCost + Entry->Cost; 3578 3579 if (ST->hasSSE2()) 3580 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3581 return MinMaxCost + Entry->Cost; 3582 3583 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 3584 3585 // Special case power of 2 reductions where the scalar type isn't changed 3586 // by type legalization. 3587 if (!isPowerOf2_32(ValVTy->getNumElements()) || 3588 ScalarSize != MTy.getScalarSizeInBits()) 3589 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned, 3590 CostKind); 3591 3592 // Now handle reduction with the legal type, taking into account size changes 3593 // at each level. 3594 while (NumVecElts > 1) { 3595 // Determine the size of the remaining vector we need to reduce. 3596 unsigned Size = NumVecElts * ScalarSize; 3597 NumVecElts /= 2; 3598 // If we're reducing from 256/512 bits, use an extract_subvector. 3599 if (Size > 128) { 3600 auto *SubTy = VectorType::get(ValVTy->getElementType(), NumVecElts); 3601 MinMaxCost += 3602 getShuffleCost(TTI::SK_ExtractSubvector, Ty, NumVecElts, SubTy); 3603 Ty = SubTy; 3604 } else if (Size == 128) { 3605 // Reducing from 128 bits is a permute of v2f64/v2i64. 3606 VectorType *ShufTy; 3607 if (ValTy->isFloatingPointTy()) 3608 ShufTy = VectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 3609 else 3610 ShufTy = VectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 3611 MinMaxCost += 3612 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3613 } else if (Size == 64) { 3614 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3615 VectorType *ShufTy; 3616 if (ValTy->isFloatingPointTy()) 3617 ShufTy = VectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 3618 else 3619 ShufTy = VectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 3620 MinMaxCost += 3621 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3622 } else { 3623 // Reducing from smaller size is a shift by immediate. 3624 VectorType *ShiftTy = VectorType::get( 3625 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 3626 MinMaxCost += getArithmeticInstrCost( 3627 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, 3628 TargetTransformInfo::OK_AnyValue, 3629 TargetTransformInfo::OK_UniformConstantValue, 3630 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3631 } 3632 3633 // Add the arithmetic op for this level. 3634 auto *SubCondTy = 3635 FixedVectorType::get(CondTy->getElementType(), Ty->getNumElements()); 3636 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3637 } 3638 3639 // Add the final extract element to the cost. 3640 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3641 } 3642 3643 /// Calculate the cost of materializing a 64-bit value. This helper 3644 /// method might only calculate a fraction of a larger immediate. Therefore it 3645 /// is valid to return a cost of ZERO. 3646 int X86TTIImpl::getIntImmCost(int64_t Val) { 3647 if (Val == 0) 3648 return TTI::TCC_Free; 3649 3650 if (isInt<32>(Val)) 3651 return TTI::TCC_Basic; 3652 3653 return 2 * TTI::TCC_Basic; 3654 } 3655 3656 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 3657 TTI::TargetCostKind CostKind) { 3658 assert(Ty->isIntegerTy()); 3659 3660 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3661 if (BitSize == 0) 3662 return ~0U; 3663 3664 // Never hoist constants larger than 128bit, because this might lead to 3665 // incorrect code generation or assertions in codegen. 3666 // Fixme: Create a cost model for types larger than i128 once the codegen 3667 // issues have been fixed. 3668 if (BitSize > 128) 3669 return TTI::TCC_Free; 3670 3671 if (Imm == 0) 3672 return TTI::TCC_Free; 3673 3674 // Sign-extend all constants to a multiple of 64-bit. 3675 APInt ImmVal = Imm; 3676 if (BitSize % 64 != 0) 3677 ImmVal = Imm.sext(alignTo(BitSize, 64)); 3678 3679 // Split the constant into 64-bit chunks and calculate the cost for each 3680 // chunk. 3681 int Cost = 0; 3682 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 3683 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 3684 int64_t Val = Tmp.getSExtValue(); 3685 Cost += getIntImmCost(Val); 3686 } 3687 // We need at least one instruction to materialize the constant. 3688 return std::max(1, Cost); 3689 } 3690 3691 int X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, 3692 Type *Ty, TTI::TargetCostKind CostKind) { 3693 assert(Ty->isIntegerTy()); 3694 3695 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3696 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3697 // here, so that constant hoisting will ignore this constant. 3698 if (BitSize == 0) 3699 return TTI::TCC_Free; 3700 3701 unsigned ImmIdx = ~0U; 3702 switch (Opcode) { 3703 default: 3704 return TTI::TCC_Free; 3705 case Instruction::GetElementPtr: 3706 // Always hoist the base address of a GetElementPtr. This prevents the 3707 // creation of new constants for every base constant that gets constant 3708 // folded with the offset. 3709 if (Idx == 0) 3710 return 2 * TTI::TCC_Basic; 3711 return TTI::TCC_Free; 3712 case Instruction::Store: 3713 ImmIdx = 0; 3714 break; 3715 case Instruction::ICmp: 3716 // This is an imperfect hack to prevent constant hoisting of 3717 // compares that might be trying to check if a 64-bit value fits in 3718 // 32-bits. The backend can optimize these cases using a right shift by 32. 3719 // Ideally we would check the compare predicate here. There also other 3720 // similar immediates the backend can use shifts for. 3721 if (Idx == 1 && Imm.getBitWidth() == 64) { 3722 uint64_t ImmVal = Imm.getZExtValue(); 3723 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 3724 return TTI::TCC_Free; 3725 } 3726 ImmIdx = 1; 3727 break; 3728 case Instruction::And: 3729 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 3730 // by using a 32-bit operation with implicit zero extension. Detect such 3731 // immediates here as the normal path expects bit 31 to be sign extended. 3732 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 3733 return TTI::TCC_Free; 3734 ImmIdx = 1; 3735 break; 3736 case Instruction::Add: 3737 case Instruction::Sub: 3738 // For add/sub, we can use the opposite instruction for INT32_MIN. 3739 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 3740 return TTI::TCC_Free; 3741 ImmIdx = 1; 3742 break; 3743 case Instruction::UDiv: 3744 case Instruction::SDiv: 3745 case Instruction::URem: 3746 case Instruction::SRem: 3747 // Division by constant is typically expanded later into a different 3748 // instruction sequence. This completely changes the constants. 3749 // Report them as "free" to stop ConstantHoist from marking them as opaque. 3750 return TTI::TCC_Free; 3751 case Instruction::Mul: 3752 case Instruction::Or: 3753 case Instruction::Xor: 3754 ImmIdx = 1; 3755 break; 3756 // Always return TCC_Free for the shift value of a shift instruction. 3757 case Instruction::Shl: 3758 case Instruction::LShr: 3759 case Instruction::AShr: 3760 if (Idx == 1) 3761 return TTI::TCC_Free; 3762 break; 3763 case Instruction::Trunc: 3764 case Instruction::ZExt: 3765 case Instruction::SExt: 3766 case Instruction::IntToPtr: 3767 case Instruction::PtrToInt: 3768 case Instruction::BitCast: 3769 case Instruction::PHI: 3770 case Instruction::Call: 3771 case Instruction::Select: 3772 case Instruction::Ret: 3773 case Instruction::Load: 3774 break; 3775 } 3776 3777 if (Idx == ImmIdx) { 3778 int NumConstants = divideCeil(BitSize, 64); 3779 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 3780 return (Cost <= NumConstants * TTI::TCC_Basic) 3781 ? static_cast<int>(TTI::TCC_Free) 3782 : Cost; 3783 } 3784 3785 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 3786 } 3787 3788 int X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 3789 const APInt &Imm, Type *Ty, 3790 TTI::TargetCostKind CostKind) { 3791 assert(Ty->isIntegerTy()); 3792 3793 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3794 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3795 // here, so that constant hoisting will ignore this constant. 3796 if (BitSize == 0) 3797 return TTI::TCC_Free; 3798 3799 switch (IID) { 3800 default: 3801 return TTI::TCC_Free; 3802 case Intrinsic::sadd_with_overflow: 3803 case Intrinsic::uadd_with_overflow: 3804 case Intrinsic::ssub_with_overflow: 3805 case Intrinsic::usub_with_overflow: 3806 case Intrinsic::smul_with_overflow: 3807 case Intrinsic::umul_with_overflow: 3808 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 3809 return TTI::TCC_Free; 3810 break; 3811 case Intrinsic::experimental_stackmap: 3812 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 3813 return TTI::TCC_Free; 3814 break; 3815 case Intrinsic::experimental_patchpoint_void: 3816 case Intrinsic::experimental_patchpoint_i64: 3817 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 3818 return TTI::TCC_Free; 3819 break; 3820 } 3821 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 3822 } 3823 3824 // Return an average cost of Gather / Scatter instruction, maybe improved later 3825 int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, Value *Ptr, 3826 unsigned Alignment, unsigned AddressSpace) { 3827 3828 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 3829 unsigned VF = cast<VectorType>(SrcVTy)->getNumElements(); 3830 3831 // Try to reduce index size from 64 bit (default for GEP) 3832 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 3833 // operation will use 16 x 64 indices which do not fit in a zmm and needs 3834 // to split. Also check that the base pointer is the same for all lanes, 3835 // and that there's at most one variable index. 3836 auto getIndexSizeInBits = [](Value *Ptr, const DataLayout& DL) { 3837 unsigned IndexSize = DL.getPointerSizeInBits(); 3838 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 3839 if (IndexSize < 64 || !GEP) 3840 return IndexSize; 3841 3842 unsigned NumOfVarIndices = 0; 3843 Value *Ptrs = GEP->getPointerOperand(); 3844 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 3845 return IndexSize; 3846 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 3847 if (isa<Constant>(GEP->getOperand(i))) 3848 continue; 3849 Type *IndxTy = GEP->getOperand(i)->getType(); 3850 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 3851 IndxTy = IndexVTy->getElementType(); 3852 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 3853 !isa<SExtInst>(GEP->getOperand(i))) || 3854 ++NumOfVarIndices > 1) 3855 return IndexSize; // 64 3856 } 3857 return (unsigned)32; 3858 }; 3859 3860 3861 // Trying to reduce IndexSize to 32 bits for vector 16. 3862 // By default the IndexSize is equal to pointer size. 3863 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 3864 ? getIndexSizeInBits(Ptr, DL) 3865 : DL.getPointerSizeInBits(); 3866 3867 auto *IndexVTy = FixedVectorType::get( 3868 IntegerType::get(SrcVTy->getContext(), IndexSize), VF); 3869 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy); 3870 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3871 int SplitFactor = std::max(IdxsLT.first, SrcLT.first); 3872 if (SplitFactor > 1) { 3873 // Handle splitting of vector of pointers 3874 auto *SplitSrcTy = 3875 FixedVectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 3876 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 3877 AddressSpace); 3878 } 3879 3880 // The gather / scatter cost is given by Intel architects. It is a rough 3881 // number since we are looking at one instruction in a time. 3882 const int GSOverhead = (Opcode == Instruction::Load) 3883 ? ST->getGatherOverhead() 3884 : ST->getScatterOverhead(); 3885 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3886 MaybeAlign(Alignment), AddressSpace, 3887 TTI::TCK_RecipThroughput); 3888 } 3889 3890 /// Return the cost of full scalarization of gather / scatter operation. 3891 /// 3892 /// Opcode - Load or Store instruction. 3893 /// SrcVTy - The type of the data vector that should be gathered or scattered. 3894 /// VariableMask - The mask is non-constant at compile time. 3895 /// Alignment - Alignment for one element. 3896 /// AddressSpace - pointer[s] address space. 3897 /// 3898 int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 3899 bool VariableMask, unsigned Alignment, 3900 unsigned AddressSpace) { 3901 unsigned VF = cast<VectorType>(SrcVTy)->getNumElements(); 3902 APInt DemandedElts = APInt::getAllOnesValue(VF); 3903 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 3904 3905 int MaskUnpackCost = 0; 3906 if (VariableMask) { 3907 VectorType *MaskTy = 3908 VectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 3909 MaskUnpackCost = 3910 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 3911 int ScalarCompareCost = 3912 getCmpSelInstrCost(Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), 3913 nullptr, CostKind); 3914 int BranchCost = getCFInstrCost(Instruction::Br, CostKind); 3915 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 3916 } 3917 3918 // The cost of the scalar loads/stores. 3919 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3920 MaybeAlign(Alignment), AddressSpace, 3921 CostKind); 3922 3923 int InsertExtractCost = 0; 3924 if (Opcode == Instruction::Load) 3925 for (unsigned i = 0; i < VF; ++i) 3926 // Add the cost of inserting each scalar load into the vector 3927 InsertExtractCost += 3928 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 3929 else 3930 for (unsigned i = 0; i < VF; ++i) 3931 // Add the cost of extracting each element out of the data vector 3932 InsertExtractCost += 3933 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 3934 3935 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 3936 } 3937 3938 /// Calculate the cost of Gather / Scatter operation 3939 int X86TTIImpl::getGatherScatterOpCost( 3940 unsigned Opcode, Type *SrcVTy, Value *Ptr, bool VariableMask, 3941 unsigned Alignment, TTI::TargetCostKind CostKind, 3942 const Instruction *I = nullptr) { 3943 3944 if (CostKind != TTI::TCK_RecipThroughput) 3945 return 1; 3946 3947 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 3948 unsigned VF = cast<VectorType>(SrcVTy)->getNumElements(); 3949 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 3950 if (!PtrTy && Ptr->getType()->isVectorTy()) 3951 PtrTy = dyn_cast<PointerType>( 3952 cast<VectorType>(Ptr->getType())->getElementType()); 3953 assert(PtrTy && "Unexpected type for Ptr argument"); 3954 unsigned AddressSpace = PtrTy->getAddressSpace(); 3955 3956 bool Scalarize = false; 3957 if ((Opcode == Instruction::Load && 3958 !isLegalMaskedGather(SrcVTy, MaybeAlign(Alignment))) || 3959 (Opcode == Instruction::Store && 3960 !isLegalMaskedScatter(SrcVTy, MaybeAlign(Alignment)))) 3961 Scalarize = true; 3962 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 3963 // Vector-4 of gather/scatter instruction does not exist on KNL. 3964 // We can extend it to 8 elements, but zeroing upper bits of 3965 // the mask vector will add more instructions. Right now we give the scalar 3966 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 3967 // is better in the VariableMask case. 3968 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 3969 Scalarize = true; 3970 3971 if (Scalarize) 3972 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 3973 AddressSpace); 3974 3975 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 3976 } 3977 3978 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 3979 TargetTransformInfo::LSRCost &C2) { 3980 // X86 specific here are "instruction number 1st priority". 3981 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 3982 C1.NumIVMuls, C1.NumBaseAdds, 3983 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 3984 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 3985 C2.NumIVMuls, C2.NumBaseAdds, 3986 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 3987 } 3988 3989 bool X86TTIImpl::canMacroFuseCmp() { 3990 return ST->hasMacroFusion() || ST->hasBranchFusion(); 3991 } 3992 3993 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, MaybeAlign Alignment) { 3994 if (!ST->hasAVX()) 3995 return false; 3996 3997 // The backend can't handle a single element vector. 3998 if (isa<VectorType>(DataTy) && 3999 cast<VectorType>(DataTy)->getNumElements() == 1) 4000 return false; 4001 Type *ScalarTy = DataTy->getScalarType(); 4002 4003 if (ScalarTy->isPointerTy()) 4004 return true; 4005 4006 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4007 return true; 4008 4009 if (!ScalarTy->isIntegerTy()) 4010 return false; 4011 4012 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4013 return IntWidth == 32 || IntWidth == 64 || 4014 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 4015 } 4016 4017 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, MaybeAlign Alignment) { 4018 return isLegalMaskedLoad(DataType, Alignment); 4019 } 4020 4021 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 4022 unsigned DataSize = DL.getTypeStoreSize(DataType); 4023 // The only supported nontemporal loads are for aligned vectors of 16 or 32 4024 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 4025 // (the equivalent stores only require AVX). 4026 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 4027 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 4028 4029 return false; 4030 } 4031 4032 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 4033 unsigned DataSize = DL.getTypeStoreSize(DataType); 4034 4035 // SSE4A supports nontemporal stores of float and double at arbitrary 4036 // alignment. 4037 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 4038 return true; 4039 4040 // Besides the SSE4A subtarget exception above, only aligned stores are 4041 // available nontemporaly on any other subtarget. And only stores with a size 4042 // of 4..32 bytes (powers of 2, only) are permitted. 4043 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 4044 !isPowerOf2_32(DataSize)) 4045 return false; 4046 4047 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 4048 // loads require AVX2). 4049 if (DataSize == 32) 4050 return ST->hasAVX(); 4051 else if (DataSize == 16) 4052 return ST->hasSSE1(); 4053 return true; 4054 } 4055 4056 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 4057 if (!isa<VectorType>(DataTy)) 4058 return false; 4059 4060 if (!ST->hasAVX512()) 4061 return false; 4062 4063 // The backend can't handle a single element vector. 4064 if (cast<VectorType>(DataTy)->getNumElements() == 1) 4065 return false; 4066 4067 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 4068 4069 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4070 return true; 4071 4072 if (!ScalarTy->isIntegerTy()) 4073 return false; 4074 4075 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4076 return IntWidth == 32 || IntWidth == 64 || 4077 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 4078 } 4079 4080 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 4081 return isLegalMaskedExpandLoad(DataTy); 4082 } 4083 4084 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, MaybeAlign Alignment) { 4085 // Some CPUs have better gather performance than others. 4086 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 4087 // enable gather with a -march. 4088 if (!(ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()))) 4089 return false; 4090 4091 // This function is called now in two cases: from the Loop Vectorizer 4092 // and from the Scalarizer. 4093 // When the Loop Vectorizer asks about legality of the feature, 4094 // the vectorization factor is not calculated yet. The Loop Vectorizer 4095 // sends a scalar type and the decision is based on the width of the 4096 // scalar element. 4097 // Later on, the cost model will estimate usage this intrinsic based on 4098 // the vector type. 4099 // The Scalarizer asks again about legality. It sends a vector type. 4100 // In this case we can reject non-power-of-2 vectors. 4101 // We also reject single element vectors as the type legalizer can't 4102 // scalarize it. 4103 if (auto *DataVTy = dyn_cast<VectorType>(DataTy)) { 4104 unsigned NumElts = DataVTy->getNumElements(); 4105 if (NumElts == 1 || !isPowerOf2_32(NumElts)) 4106 return false; 4107 } 4108 Type *ScalarTy = DataTy->getScalarType(); 4109 if (ScalarTy->isPointerTy()) 4110 return true; 4111 4112 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4113 return true; 4114 4115 if (!ScalarTy->isIntegerTy()) 4116 return false; 4117 4118 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4119 return IntWidth == 32 || IntWidth == 64; 4120 } 4121 4122 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, MaybeAlign Alignment) { 4123 // AVX2 doesn't support scatter 4124 if (!ST->hasAVX512()) 4125 return false; 4126 return isLegalMaskedGather(DataType, Alignment); 4127 } 4128 4129 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 4130 EVT VT = TLI->getValueType(DL, DataType); 4131 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 4132 } 4133 4134 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 4135 return false; 4136 } 4137 4138 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 4139 const Function *Callee) const { 4140 const TargetMachine &TM = getTLI()->getTargetMachine(); 4141 4142 // Work this as a subsetting of subtarget features. 4143 const FeatureBitset &CallerBits = 4144 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 4145 const FeatureBitset &CalleeBits = 4146 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 4147 4148 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 4149 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 4150 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 4151 } 4152 4153 bool X86TTIImpl::areFunctionArgsABICompatible( 4154 const Function *Caller, const Function *Callee, 4155 SmallPtrSetImpl<Argument *> &Args) const { 4156 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args)) 4157 return false; 4158 4159 // If we get here, we know the target features match. If one function 4160 // considers 512-bit vectors legal and the other does not, consider them 4161 // incompatible. 4162 const TargetMachine &TM = getTLI()->getTargetMachine(); 4163 4164 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 4165 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs()) 4166 return true; 4167 4168 // Consider the arguments compatible if they aren't vectors or aggregates. 4169 // FIXME: Look at the size of vectors. 4170 // FIXME: Look at the element types of aggregates to see if there are vectors. 4171 // FIXME: The API of this function seems intended to allow arguments 4172 // to be removed from the set, but the caller doesn't check if the set 4173 // becomes empty so that may not work in practice. 4174 return llvm::none_of(Args, [](Argument *A) { 4175 auto *EltTy = cast<PointerType>(A->getType())->getElementType(); 4176 return EltTy->isVectorTy() || EltTy->isAggregateType(); 4177 }); 4178 } 4179 4180 X86TTIImpl::TTI::MemCmpExpansionOptions 4181 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 4182 TTI::MemCmpExpansionOptions Options; 4183 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 4184 Options.NumLoadsPerBlock = 2; 4185 // All GPR and vector loads can be unaligned. 4186 Options.AllowOverlappingLoads = true; 4187 if (IsZeroCmp) { 4188 // Only enable vector loads for equality comparison. Right now the vector 4189 // version is not as fast for three way compare (see #33329). 4190 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 4191 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 4192 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 4193 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 4194 } 4195 if (ST->is64Bit()) { 4196 Options.LoadSizes.push_back(8); 4197 } 4198 Options.LoadSizes.push_back(4); 4199 Options.LoadSizes.push_back(2); 4200 Options.LoadSizes.push_back(1); 4201 return Options; 4202 } 4203 4204 bool X86TTIImpl::enableInterleavedAccessVectorization() { 4205 // TODO: We expect this to be beneficial regardless of arch, 4206 // but there are currently some unexplained performance artifacts on Atom. 4207 // As a temporary solution, disable on Atom. 4208 return !(ST->isAtom()); 4209 } 4210 4211 // Get estimation for interleaved load/store operations for AVX2. 4212 // \p Factor is the interleaved-access factor (stride) - number of 4213 // (interleaved) elements in the group. 4214 // \p Indices contains the indices for a strided load: when the 4215 // interleaved load has gaps they indicate which elements are used. 4216 // If Indices is empty (or if the number of indices is equal to the size 4217 // of the interleaved-access as given in \p Factor) the access has no gaps. 4218 // 4219 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 4220 // computing the cost using a generic formula as a function of generic 4221 // shuffles. We therefore use a lookup table instead, filled according to 4222 // the instruction sequences that codegen currently generates. 4223 int X86TTIImpl::getInterleavedMemoryOpCostAVX2(unsigned Opcode, Type *VecTy, 4224 unsigned Factor, 4225 ArrayRef<unsigned> Indices, 4226 unsigned Alignment, 4227 unsigned AddressSpace, 4228 TTI::TargetCostKind CostKind, 4229 bool UseMaskForCond, 4230 bool UseMaskForGaps) { 4231 4232 if (UseMaskForCond || UseMaskForGaps) 4233 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4234 Alignment, AddressSpace, CostKind, 4235 UseMaskForCond, UseMaskForGaps); 4236 4237 // We currently Support only fully-interleaved groups, with no gaps. 4238 // TODO: Support also strided loads (interleaved-groups with gaps). 4239 if (Indices.size() && Indices.size() != Factor) 4240 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4241 Alignment, AddressSpace, 4242 CostKind); 4243 4244 // VecTy for interleave memop is <VF*Factor x Elt>. 4245 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4246 // VecTy = <12 x i32>. 4247 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4248 4249 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 4250 // the VF=2, while v2i128 is an unsupported MVT vector type 4251 // (see MachineValueType.h::getVectorVT()). 4252 if (!LegalVT.isVector()) 4253 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4254 Alignment, AddressSpace, 4255 CostKind); 4256 4257 unsigned VF = cast<VectorType>(VecTy)->getNumElements() / Factor; 4258 Type *ScalarTy = cast<VectorType>(VecTy)->getElementType(); 4259 4260 // Calculate the number of memory operations (NumOfMemOps), required 4261 // for load/store the VecTy. 4262 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4263 unsigned LegalVTSize = LegalVT.getStoreSize(); 4264 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4265 4266 // Get the cost of one memory operation. 4267 auto *SingleMemOpTy = 4268 FixedVectorType::get(cast<VectorType>(VecTy)->getElementType(), 4269 LegalVT.getVectorNumElements()); 4270 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 4271 MaybeAlign(Alignment), AddressSpace, 4272 CostKind); 4273 4274 auto *VT = FixedVectorType::get(ScalarTy, VF); 4275 EVT ETy = TLI->getValueType(DL, VT); 4276 if (!ETy.isSimple()) 4277 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4278 Alignment, AddressSpace, 4279 CostKind); 4280 4281 // TODO: Complete for other data-types and strides. 4282 // Each combination of Stride, ElementTy and VF results in a different 4283 // sequence; The cost tables are therefore accessed with: 4284 // Factor (stride) and VectorType=VFxElemType. 4285 // The Cost accounts only for the shuffle sequence; 4286 // The cost of the loads/stores is accounted for separately. 4287 // 4288 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 4289 { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64 4290 { 2, MVT::v4f64, 6 }, //(load 8f64 and) deinterleave into 2 x 4f64 4291 4292 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8 4293 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8 4294 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8 4295 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8 4296 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8 4297 { 3, MVT::v8f32, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32 4298 4299 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8 4300 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8 4301 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8 4302 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8 4303 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8 4304 4305 { 8, MVT::v8f32, 40 } //(load 64f32 and)deinterleave into 8 x 8f32 4306 }; 4307 4308 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 4309 { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store) 4310 { 2, MVT::v4f64, 6 }, //interleave into 2 x 4f64 into 8f64 (and store) 4311 4312 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store) 4313 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store) 4314 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store) 4315 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store) 4316 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store) 4317 4318 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store) 4319 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store) 4320 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store) 4321 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store) 4322 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store) 4323 }; 4324 4325 if (Opcode == Instruction::Load) { 4326 if (const auto *Entry = 4327 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 4328 return NumOfMemOps * MemOpCost + Entry->Cost; 4329 } else { 4330 assert(Opcode == Instruction::Store && 4331 "Expected Store Instruction at this point"); 4332 if (const auto *Entry = 4333 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 4334 return NumOfMemOps * MemOpCost + Entry->Cost; 4335 } 4336 4337 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4338 Alignment, AddressSpace, CostKind); 4339 } 4340 4341 // Get estimation for interleaved load/store operations and strided load. 4342 // \p Indices contains indices for strided load. 4343 // \p Factor - the factor of interleaving. 4344 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 4345 int X86TTIImpl::getInterleavedMemoryOpCostAVX512(unsigned Opcode, Type *VecTy, 4346 unsigned Factor, 4347 ArrayRef<unsigned> Indices, 4348 unsigned Alignment, 4349 unsigned AddressSpace, 4350 TTI::TargetCostKind CostKind, 4351 bool UseMaskForCond, 4352 bool UseMaskForGaps) { 4353 4354 if (UseMaskForCond || UseMaskForGaps) 4355 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4356 Alignment, AddressSpace, CostKind, 4357 UseMaskForCond, UseMaskForGaps); 4358 4359 // VecTy for interleave memop is <VF*Factor x Elt>. 4360 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4361 // VecTy = <12 x i32>. 4362 4363 // Calculate the number of memory operations (NumOfMemOps), required 4364 // for load/store the VecTy. 4365 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4366 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4367 unsigned LegalVTSize = LegalVT.getStoreSize(); 4368 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4369 4370 // Get the cost of one memory operation. 4371 auto *SingleMemOpTy = 4372 VectorType::get(cast<VectorType>(VecTy)->getElementType(), 4373 LegalVT.getVectorNumElements()); 4374 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 4375 MaybeAlign(Alignment), AddressSpace, 4376 CostKind); 4377 4378 unsigned VF = cast<VectorType>(VecTy)->getNumElements() / Factor; 4379 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 4380 4381 if (Opcode == Instruction::Load) { 4382 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 4383 // contain the cost of the optimized shuffle sequence that the 4384 // X86InterleavedAccess pass will generate. 4385 // The cost of loads and stores are computed separately from the table. 4386 4387 // X86InterleavedAccess support only the following interleaved-access group. 4388 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 4389 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 4390 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 4391 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 4392 }; 4393 4394 if (const auto *Entry = 4395 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 4396 return NumOfMemOps * MemOpCost + Entry->Cost; 4397 //If an entry does not exist, fallback to the default implementation. 4398 4399 // Kind of shuffle depends on number of loaded values. 4400 // If we load the entire data in one register, we can use a 1-src shuffle. 4401 // Otherwise, we'll merge 2 sources in each operation. 4402 TTI::ShuffleKind ShuffleKind = 4403 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 4404 4405 unsigned ShuffleCost = 4406 getShuffleCost(ShuffleKind, SingleMemOpTy, 0, nullptr); 4407 4408 unsigned NumOfLoadsInInterleaveGrp = 4409 Indices.size() ? Indices.size() : Factor; 4410 auto *ResultTy = FixedVectorType::get( 4411 cast<VectorType>(VecTy)->getElementType(), 4412 cast<VectorType>(VecTy)->getNumElements() / Factor); 4413 unsigned NumOfResults = 4414 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 4415 NumOfLoadsInInterleaveGrp; 4416 4417 // About a half of the loads may be folded in shuffles when we have only 4418 // one result. If we have more than one result, we do not fold loads at all. 4419 unsigned NumOfUnfoldedLoads = 4420 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 4421 4422 // Get a number of shuffle operations per result. 4423 unsigned NumOfShufflesPerResult = 4424 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 4425 4426 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4427 // When we have more than one destination, we need additional instructions 4428 // to keep sources. 4429 unsigned NumOfMoves = 0; 4430 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 4431 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 4432 4433 int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 4434 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 4435 4436 return Cost; 4437 } 4438 4439 // Store. 4440 assert(Opcode == Instruction::Store && 4441 "Expected Store Instruction at this point"); 4442 // X86InterleavedAccess support only the following interleaved-access group. 4443 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 4444 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 4445 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 4446 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 4447 4448 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 4449 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 4450 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 4451 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 4452 }; 4453 4454 if (const auto *Entry = 4455 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 4456 return NumOfMemOps * MemOpCost + Entry->Cost; 4457 //If an entry does not exist, fallback to the default implementation. 4458 4459 // There is no strided stores meanwhile. And store can't be folded in 4460 // shuffle. 4461 unsigned NumOfSources = Factor; // The number of values to be merged. 4462 unsigned ShuffleCost = 4463 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, 0, nullptr); 4464 unsigned NumOfShufflesPerStore = NumOfSources - 1; 4465 4466 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4467 // We need additional instructions to keep sources. 4468 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 4469 int Cost = NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 4470 NumOfMoves; 4471 return Cost; 4472 } 4473 4474 int X86TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, 4475 unsigned Factor, 4476 ArrayRef<unsigned> Indices, 4477 unsigned Alignment, 4478 unsigned AddressSpace, 4479 TTI::TargetCostKind CostKind, 4480 bool UseMaskForCond, 4481 bool UseMaskForGaps) { 4482 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 4483 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 4484 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 4485 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 4486 return true; 4487 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 4488 return HasBW; 4489 return false; 4490 }; 4491 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 4492 return getInterleavedMemoryOpCostAVX512(Opcode, VecTy, Factor, Indices, 4493 Alignment, AddressSpace, CostKind, 4494 UseMaskForCond, UseMaskForGaps); 4495 if (ST->hasAVX2()) 4496 return getInterleavedMemoryOpCostAVX2(Opcode, VecTy, Factor, Indices, 4497 Alignment, AddressSpace, CostKind, 4498 UseMaskForCond, UseMaskForGaps); 4499 4500 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4501 Alignment, AddressSpace, CostKind, 4502 UseMaskForCond, UseMaskForGaps); 4503 } 4504