1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // X86 cost model. 56 // 57 //===----------------------------------------------------------------------===// 58 59 TargetTransformInfo::PopcntSupportKind 60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 61 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 62 // TODO: Currently the __builtin_popcount() implementation using SSE3 63 // instructions is inefficient. Once the problem is fixed, we should 64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 66 } 67 68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 69 TargetTransformInfo::CacheLevel Level) const { 70 switch (Level) { 71 case TargetTransformInfo::CacheLevel::L1D: 72 // - Penryn 73 // - Nehalem 74 // - Westmere 75 // - Sandy Bridge 76 // - Ivy Bridge 77 // - Haswell 78 // - Broadwell 79 // - Skylake 80 // - Kabylake 81 return 32 * 1024; // 32 KByte 82 case TargetTransformInfo::CacheLevel::L2D: 83 // - Penryn 84 // - Nehalem 85 // - Westmere 86 // - Sandy Bridge 87 // - Ivy Bridge 88 // - Haswell 89 // - Broadwell 90 // - Skylake 91 // - Kabylake 92 return 256 * 1024; // 256 KByte 93 } 94 95 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 96 } 97 98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 99 TargetTransformInfo::CacheLevel Level) const { 100 // - Penryn 101 // - Nehalem 102 // - Westmere 103 // - Sandy Bridge 104 // - Ivy Bridge 105 // - Haswell 106 // - Broadwell 107 // - Skylake 108 // - Kabylake 109 switch (Level) { 110 case TargetTransformInfo::CacheLevel::L1D: 111 LLVM_FALLTHROUGH; 112 case TargetTransformInfo::CacheLevel::L2D: 113 return 8; 114 } 115 116 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 117 } 118 119 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 120 bool Vector = (ClassID == 1); 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 TypeSize 133 X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { 134 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 135 switch (K) { 136 case TargetTransformInfo::RGK_Scalar: 137 return TypeSize::getFixed(ST->is64Bit() ? 64 : 32); 138 case TargetTransformInfo::RGK_FixedWidthVector: 139 if (ST->hasAVX512() && PreferVectorWidth >= 512) 140 return TypeSize::getFixed(512); 141 if (ST->hasAVX() && PreferVectorWidth >= 256) 142 return TypeSize::getFixed(256); 143 if (ST->hasSSE1() && PreferVectorWidth >= 128) 144 return TypeSize::getFixed(128); 145 return TypeSize::getFixed(0); 146 case TargetTransformInfo::RGK_ScalableVector: 147 return TypeSize::getScalable(0); 148 } 149 150 llvm_unreachable("Unsupported register kind"); 151 } 152 153 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 154 return getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector) 155 .getFixedSize(); 156 } 157 158 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 159 // If the loop will not be vectorized, don't interleave the loop. 160 // Let regular unroll to unroll the loop, which saves the overflow 161 // check and memory check cost. 162 if (VF == 1) 163 return 1; 164 165 if (ST->isAtom()) 166 return 1; 167 168 // Sandybridge and Haswell have multiple execution ports and pipelined 169 // vector units. 170 if (ST->hasAVX()) 171 return 4; 172 173 return 2; 174 } 175 176 InstructionCost X86TTIImpl::getArithmeticInstrCost( 177 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, 178 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 179 TTI::OperandValueProperties Opd1PropInfo, 180 TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, 181 const Instruction *CxtI) { 182 // TODO: Handle more cost kinds. 183 if (CostKind != TTI::TCK_RecipThroughput) 184 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, 185 Op2Info, Opd1PropInfo, 186 Opd2PropInfo, Args, CxtI); 187 188 // vXi8 multiplications are always promoted to vXi16. 189 if (Opcode == Instruction::Mul && Ty->isVectorTy() && 190 Ty->getScalarSizeInBits() == 8) { 191 Type *WideVecTy = 192 VectorType::getExtendedElementVectorType(cast<VectorType>(Ty)); 193 return getCastInstrCost(Instruction::ZExt, WideVecTy, Ty, 194 TargetTransformInfo::CastContextHint::None, 195 CostKind) + 196 getCastInstrCost(Instruction::Trunc, Ty, WideVecTy, 197 TargetTransformInfo::CastContextHint::None, 198 CostKind) + 199 getArithmeticInstrCost(Opcode, WideVecTy, CostKind, Op1Info, Op2Info, 200 Opd1PropInfo, Opd2PropInfo); 201 } 202 203 // Legalize the type. 204 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 205 206 int ISD = TLI->InstructionOpcodeToISD(Opcode); 207 assert(ISD && "Invalid opcode"); 208 209 if (ISD == ISD::MUL && Args.size() == 2 && LT.second.isVector() && 210 LT.second.getScalarType() == MVT::i32) { 211 // Check if the operands can be represented as a smaller datatype. 212 bool Op1Signed = false, Op2Signed = false; 213 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 214 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 215 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 216 217 // If both are representable as i15 and at least one is constant, 218 // zero-extended, or sign-extended from vXi16 (or less pre-SSE41) then we 219 // can treat this as PMADDWD which has the same costs as a vXi16 multiply. 220 if (OpMinSize <= 15 && !ST->isPMADDWDSlow()) { 221 bool Op1Constant = 222 isa<ConstantDataVector>(Args[0]) || isa<ConstantVector>(Args[0]); 223 bool Op2Constant = 224 isa<ConstantDataVector>(Args[1]) || isa<ConstantVector>(Args[1]); 225 bool Op1Sext = isa<SExtInst>(Args[0]) && 226 (Op1MinSize == 15 || (Op1MinSize < 15 && !ST->hasSSE41())); 227 bool Op2Sext = isa<SExtInst>(Args[1]) && 228 (Op2MinSize == 15 || (Op2MinSize < 15 && !ST->hasSSE41())); 229 230 bool IsZeroExtended = !Op1Signed || !Op2Signed; 231 bool IsConstant = Op1Constant || Op2Constant; 232 bool IsSext = Op1Sext || Op2Sext; 233 if (IsConstant || IsZeroExtended || IsSext) 234 LT.second = 235 MVT::getVectorVT(MVT::i16, 2 * LT.second.getVectorNumElements()); 236 } 237 } 238 239 if ((ISD == ISD::MUL || ISD == ISD::SDIV || ISD == ISD::SREM || 240 ISD == ISD::UDIV || ISD == ISD::UREM) && 241 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 242 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 243 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 244 // Vector multiply by pow2 will be simplified to shifts. 245 if (ISD == ISD::MUL) { 246 InstructionCost Cost = getArithmeticInstrCost( 247 Instruction::Shl, Ty, CostKind, Op1Info, Op2Info, 248 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 249 return Cost; 250 } 251 252 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 253 // On X86, vector signed division by constants power-of-two are 254 // normally expanded to the sequence SRA + SRL + ADD + SRA. 255 // The OperandValue properties may not be the same as that of the previous 256 // operation; conservatively assume OP_None. 257 InstructionCost Cost = 258 2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Op1Info, 259 Op2Info, TargetTransformInfo::OP_None, 260 TargetTransformInfo::OP_None); 261 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 262 Op2Info, TargetTransformInfo::OP_None, 263 TargetTransformInfo::OP_None); 264 Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind, Op1Info, 265 Op2Info, TargetTransformInfo::OP_None, 266 TargetTransformInfo::OP_None); 267 268 if (ISD == ISD::SREM) { 269 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 270 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info, 271 Op2Info); 272 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info, 273 Op2Info); 274 } 275 276 return Cost; 277 } 278 279 // Vector unsigned division/remainder will be simplified to shifts/masks. 280 if (ISD == ISD::UDIV) 281 return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 282 Op2Info, TargetTransformInfo::OP_None, 283 TargetTransformInfo::OP_None); 284 // UREM 285 return getArithmeticInstrCost(Instruction::And, Ty, CostKind, Op1Info, 286 Op2Info, TargetTransformInfo::OP_None, 287 TargetTransformInfo::OP_None); 288 } 289 290 static const CostTblEntry GLMCostTable[] = { 291 { ISD::FDIV, MVT::f32, 18 }, // divss 292 { ISD::FDIV, MVT::v4f32, 35 }, // divps 293 { ISD::FDIV, MVT::f64, 33 }, // divsd 294 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 295 }; 296 297 if (ST->useGLMDivSqrtCosts()) 298 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 299 LT.second)) 300 return LT.first * Entry->Cost; 301 302 static const CostTblEntry SLMCostTable[] = { 303 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 304 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 305 { ISD::FMUL, MVT::f64, 2 }, // mulsd 306 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 307 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 308 { ISD::FDIV, MVT::f32, 17 }, // divss 309 { ISD::FDIV, MVT::v4f32, 39 }, // divps 310 { ISD::FDIV, MVT::f64, 32 }, // divsd 311 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 312 { ISD::FADD, MVT::v2f64, 2 }, // addpd 313 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 314 // v2i64/v4i64 mul is custom lowered as a series of long: 315 // multiplies(3), shifts(3) and adds(2) 316 // slm muldq version throughput is 2 and addq throughput 4 317 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 318 // 3X4 (addq throughput) = 17 319 { ISD::MUL, MVT::v2i64, 17 }, 320 // slm addq\subq throughput is 4 321 { ISD::ADD, MVT::v2i64, 4 }, 322 { ISD::SUB, MVT::v2i64, 4 }, 323 }; 324 325 if (ST->useSLMArithCosts()) { 326 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 327 // Check if the operands can be shrinked into a smaller datatype. 328 // TODO: Merge this into generiic vXi32 MUL patterns above. 329 bool Op1Signed = false; 330 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 331 bool Op2Signed = false; 332 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 333 334 bool SignedMode = Op1Signed || Op2Signed; 335 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 336 337 if (OpMinSize <= 7) 338 return LT.first * 3; // pmullw/sext 339 if (!SignedMode && OpMinSize <= 8) 340 return LT.first * 3; // pmullw/zext 341 if (OpMinSize <= 15) 342 return LT.first * 5; // pmullw/pmulhw/pshuf 343 if (!SignedMode && OpMinSize <= 16) 344 return LT.first * 5; // pmullw/pmulhw/pshuf 345 } 346 347 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 348 LT.second)) { 349 return LT.first * Entry->Cost; 350 } 351 } 352 353 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 354 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 355 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 356 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 357 }; 358 359 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 360 ST->hasBWI()) { 361 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 362 LT.second)) 363 return LT.first * Entry->Cost; 364 } 365 366 static const CostTblEntry AVX512UniformConstCostTable[] = { 367 { ISD::SRA, MVT::v2i64, 1 }, 368 { ISD::SRA, MVT::v4i64, 1 }, 369 { ISD::SRA, MVT::v8i64, 1 }, 370 371 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 372 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 373 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 374 375 { ISD::SDIV, MVT::v16i32, 6 }, // pmuludq sequence 376 { ISD::SREM, MVT::v16i32, 8 }, // pmuludq+mul+sub sequence 377 { ISD::UDIV, MVT::v16i32, 5 }, // pmuludq sequence 378 { ISD::UREM, MVT::v16i32, 7 }, // pmuludq+mul+sub sequence 379 }; 380 381 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 382 ST->hasAVX512()) { 383 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 384 LT.second)) 385 return LT.first * Entry->Cost; 386 } 387 388 static const CostTblEntry AVX2UniformConstCostTable[] = { 389 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 390 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 391 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 392 393 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 394 395 { ISD::SDIV, MVT::v8i32, 6 }, // pmuludq sequence 396 { ISD::SREM, MVT::v8i32, 8 }, // pmuludq+mul+sub sequence 397 { ISD::UDIV, MVT::v8i32, 5 }, // pmuludq sequence 398 { ISD::UREM, MVT::v8i32, 7 }, // pmuludq+mul+sub sequence 399 }; 400 401 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 402 ST->hasAVX2()) { 403 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 404 LT.second)) 405 return LT.first * Entry->Cost; 406 } 407 408 static const CostTblEntry SSE2UniformConstCostTable[] = { 409 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 410 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 411 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 412 413 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 414 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 415 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 416 417 { ISD::SDIV, MVT::v8i32, 12+2 }, // 2*pmuludq sequence + split. 418 { ISD::SREM, MVT::v8i32, 16+2 }, // 2*pmuludq+mul+sub sequence + split. 419 { ISD::SDIV, MVT::v4i32, 6 }, // pmuludq sequence 420 { ISD::SREM, MVT::v4i32, 8 }, // pmuludq+mul+sub sequence 421 { ISD::UDIV, MVT::v8i32, 10+2 }, // 2*pmuludq sequence + split. 422 { ISD::UREM, MVT::v8i32, 14+2 }, // 2*pmuludq+mul+sub sequence + split. 423 { ISD::UDIV, MVT::v4i32, 5 }, // pmuludq sequence 424 { ISD::UREM, MVT::v4i32, 7 }, // pmuludq+mul+sub sequence 425 }; 426 427 // XOP has faster vXi8 shifts. 428 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 429 ST->hasSSE2() && !ST->hasXOP()) { 430 if (const auto *Entry = 431 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 432 return LT.first * Entry->Cost; 433 } 434 435 static const CostTblEntry AVX512BWConstCostTable[] = { 436 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 437 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 438 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 439 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 440 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 441 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 442 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 443 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 444 }; 445 446 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 447 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 448 ST->hasBWI()) { 449 if (const auto *Entry = 450 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 451 return LT.first * Entry->Cost; 452 } 453 454 static const CostTblEntry AVX512ConstCostTable[] = { 455 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 456 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 457 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 458 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 459 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 460 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 461 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 462 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 463 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 464 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 465 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 466 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 467 }; 468 469 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 470 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 471 ST->hasAVX512()) { 472 if (const auto *Entry = 473 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 474 return LT.first * Entry->Cost; 475 } 476 477 static const CostTblEntry AVX2ConstCostTable[] = { 478 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 479 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 480 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 481 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 482 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 483 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 484 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 485 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 486 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 487 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 488 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 489 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 490 }; 491 492 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 493 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 494 ST->hasAVX2()) { 495 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 496 return LT.first * Entry->Cost; 497 } 498 499 static const CostTblEntry SSE2ConstCostTable[] = { 500 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 501 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 502 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 503 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 504 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 505 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 506 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 507 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 508 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 509 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 510 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 511 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 512 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 513 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 514 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 515 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 516 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 517 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 518 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 519 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 520 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 521 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 522 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 523 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 524 }; 525 526 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 527 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 528 ST->hasSSE2()) { 529 // pmuldq sequence. 530 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 531 return LT.first * 32; 532 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 533 return LT.first * 38; 534 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 535 return LT.first * 15; 536 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 537 return LT.first * 20; 538 539 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 540 return LT.first * Entry->Cost; 541 } 542 543 static const CostTblEntry AVX512BWShiftCostTable[] = { 544 { ISD::SHL, MVT::v16i8, 4 }, // extend/vpsllvw/pack sequence. 545 { ISD::SRL, MVT::v16i8, 4 }, // extend/vpsrlvw/pack sequence. 546 { ISD::SRA, MVT::v16i8, 4 }, // extend/vpsravw/pack sequence. 547 { ISD::SHL, MVT::v32i8, 4 }, // extend/vpsllvw/pack sequence. 548 { ISD::SRL, MVT::v32i8, 4 }, // extend/vpsrlvw/pack sequence. 549 { ISD::SRA, MVT::v32i8, 6 }, // extend/vpsravw/pack sequence. 550 { ISD::SHL, MVT::v64i8, 6 }, // extend/vpsllvw/pack sequence. 551 { ISD::SRL, MVT::v64i8, 7 }, // extend/vpsrlvw/pack sequence. 552 { ISD::SRA, MVT::v64i8, 15 }, // extend/vpsravw/pack sequence. 553 554 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 555 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 556 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 557 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 558 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 559 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 560 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 561 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 562 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 563 }; 564 565 if (ST->hasBWI()) 566 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 567 return LT.first * Entry->Cost; 568 569 static const CostTblEntry AVX2UniformCostTable[] = { 570 // Uniform splats are cheaper for the following instructions. 571 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 572 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 573 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 574 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 575 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 576 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 577 578 { ISD::SHL, MVT::v8i32, 1 }, // pslld 579 { ISD::SRL, MVT::v8i32, 1 }, // psrld 580 { ISD::SRA, MVT::v8i32, 1 }, // psrad 581 { ISD::SHL, MVT::v4i64, 1 }, // psllq 582 { ISD::SRL, MVT::v4i64, 1 }, // psrlq 583 }; 584 585 if (ST->hasAVX2() && 586 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 587 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 588 if (const auto *Entry = 589 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 590 return LT.first * Entry->Cost; 591 } 592 593 static const CostTblEntry SSE2UniformCostTable[] = { 594 // Uniform splats are cheaper for the following instructions. 595 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 596 { ISD::SHL, MVT::v4i32, 1 }, // pslld 597 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 598 599 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 600 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 601 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 602 603 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 604 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 605 }; 606 607 if (ST->hasSSE2() && 608 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 609 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 610 if (const auto *Entry = 611 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 612 return LT.first * Entry->Cost; 613 } 614 615 static const CostTblEntry AVX512DQCostTable[] = { 616 { ISD::MUL, MVT::v2i64, 2 }, // pmullq 617 { ISD::MUL, MVT::v4i64, 2 }, // pmullq 618 { ISD::MUL, MVT::v8i64, 2 } // pmullq 619 }; 620 621 // Look for AVX512DQ lowering tricks for custom cases. 622 if (ST->hasDQI()) 623 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 624 return LT.first * Entry->Cost; 625 626 static const CostTblEntry AVX512BWCostTable[] = { 627 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 628 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 629 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 630 }; 631 632 // Look for AVX512BW lowering tricks for custom cases. 633 if (ST->hasBWI()) 634 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 635 return LT.first * Entry->Cost; 636 637 static const CostTblEntry AVX512CostTable[] = { 638 { ISD::SHL, MVT::v4i32, 1 }, 639 { ISD::SRL, MVT::v4i32, 1 }, 640 { ISD::SRA, MVT::v4i32, 1 }, 641 { ISD::SHL, MVT::v8i32, 1 }, 642 { ISD::SRL, MVT::v8i32, 1 }, 643 { ISD::SRA, MVT::v8i32, 1 }, 644 { ISD::SHL, MVT::v16i32, 1 }, 645 { ISD::SRL, MVT::v16i32, 1 }, 646 { ISD::SRA, MVT::v16i32, 1 }, 647 648 { ISD::SHL, MVT::v2i64, 1 }, 649 { ISD::SRL, MVT::v2i64, 1 }, 650 { ISD::SHL, MVT::v4i64, 1 }, 651 { ISD::SRL, MVT::v4i64, 1 }, 652 { ISD::SHL, MVT::v8i64, 1 }, 653 { ISD::SRL, MVT::v8i64, 1 }, 654 655 { ISD::SRA, MVT::v2i64, 1 }, 656 { ISD::SRA, MVT::v4i64, 1 }, 657 { ISD::SRA, MVT::v8i64, 1 }, 658 659 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 660 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 661 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 662 { ISD::MUL, MVT::v8i64, 6 }, // 3*pmuludq/3*shift/2*add 663 664 { ISD::FNEG, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 665 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 666 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 667 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 668 { ISD::FDIV, MVT::f64, 4 }, // Skylake from http://www.agner.org/ 669 { ISD::FDIV, MVT::v2f64, 4 }, // Skylake from http://www.agner.org/ 670 { ISD::FDIV, MVT::v4f64, 8 }, // Skylake from http://www.agner.org/ 671 { ISD::FDIV, MVT::v8f64, 16 }, // Skylake from http://www.agner.org/ 672 673 { ISD::FNEG, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 674 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 675 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 676 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 677 { ISD::FDIV, MVT::f32, 3 }, // Skylake from http://www.agner.org/ 678 { ISD::FDIV, MVT::v4f32, 3 }, // Skylake from http://www.agner.org/ 679 { ISD::FDIV, MVT::v8f32, 5 }, // Skylake from http://www.agner.org/ 680 { ISD::FDIV, MVT::v16f32, 10 }, // Skylake from http://www.agner.org/ 681 }; 682 683 if (ST->hasAVX512()) 684 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 685 return LT.first * Entry->Cost; 686 687 static const CostTblEntry AVX2ShiftCostTable[] = { 688 // Shifts on vXi64/vXi32 on AVX2 is legal even though we declare to 689 // customize them to detect the cases where shift amount is a scalar one. 690 { ISD::SHL, MVT::v4i32, 2 }, // vpsllvd (Haswell from agner.org) 691 { ISD::SRL, MVT::v4i32, 2 }, // vpsrlvd (Haswell from agner.org) 692 { ISD::SRA, MVT::v4i32, 2 }, // vpsravd (Haswell from agner.org) 693 { ISD::SHL, MVT::v8i32, 2 }, // vpsllvd (Haswell from agner.org) 694 { ISD::SRL, MVT::v8i32, 2 }, // vpsrlvd (Haswell from agner.org) 695 { ISD::SRA, MVT::v8i32, 2 }, // vpsravd (Haswell from agner.org) 696 { ISD::SHL, MVT::v2i64, 1 }, // vpsllvq (Haswell from agner.org) 697 { ISD::SRL, MVT::v2i64, 1 }, // vpsrlvq (Haswell from agner.org) 698 { ISD::SHL, MVT::v4i64, 1 }, // vpsllvq (Haswell from agner.org) 699 { ISD::SRL, MVT::v4i64, 1 }, // vpsrlvq (Haswell from agner.org) 700 }; 701 702 if (ST->hasAVX512()) { 703 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 704 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 705 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 706 // On AVX512, a packed v32i16 shift left by a constant build_vector 707 // is lowered into a vector multiply (vpmullw). 708 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 709 Op1Info, Op2Info, 710 TargetTransformInfo::OP_None, 711 TargetTransformInfo::OP_None); 712 } 713 714 // Look for AVX2 lowering tricks (XOP is always better at v4i32 shifts). 715 if (ST->hasAVX2() && !(ST->hasXOP() && LT.second == MVT::v4i32)) { 716 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 717 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 718 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 719 // On AVX2, a packed v16i16 shift left by a constant build_vector 720 // is lowered into a vector multiply (vpmullw). 721 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 722 Op1Info, Op2Info, 723 TargetTransformInfo::OP_None, 724 TargetTransformInfo::OP_None); 725 726 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 727 return LT.first * Entry->Cost; 728 } 729 730 static const CostTblEntry XOPShiftCostTable[] = { 731 // 128bit shifts take 1cy, but right shifts require negation beforehand. 732 { ISD::SHL, MVT::v16i8, 1 }, 733 { ISD::SRL, MVT::v16i8, 2 }, 734 { ISD::SRA, MVT::v16i8, 2 }, 735 { ISD::SHL, MVT::v8i16, 1 }, 736 { ISD::SRL, MVT::v8i16, 2 }, 737 { ISD::SRA, MVT::v8i16, 2 }, 738 { ISD::SHL, MVT::v4i32, 1 }, 739 { ISD::SRL, MVT::v4i32, 2 }, 740 { ISD::SRA, MVT::v4i32, 2 }, 741 { ISD::SHL, MVT::v2i64, 1 }, 742 { ISD::SRL, MVT::v2i64, 2 }, 743 { ISD::SRA, MVT::v2i64, 2 }, 744 // 256bit shifts require splitting if AVX2 didn't catch them above. 745 { ISD::SHL, MVT::v32i8, 2+2 }, 746 { ISD::SRL, MVT::v32i8, 4+2 }, 747 { ISD::SRA, MVT::v32i8, 4+2 }, 748 { ISD::SHL, MVT::v16i16, 2+2 }, 749 { ISD::SRL, MVT::v16i16, 4+2 }, 750 { ISD::SRA, MVT::v16i16, 4+2 }, 751 { ISD::SHL, MVT::v8i32, 2+2 }, 752 { ISD::SRL, MVT::v8i32, 4+2 }, 753 { ISD::SRA, MVT::v8i32, 4+2 }, 754 { ISD::SHL, MVT::v4i64, 2+2 }, 755 { ISD::SRL, MVT::v4i64, 4+2 }, 756 { ISD::SRA, MVT::v4i64, 4+2 }, 757 }; 758 759 // Look for XOP lowering tricks. 760 if (ST->hasXOP()) { 761 // If the right shift is constant then we'll fold the negation so 762 // it's as cheap as a left shift. 763 int ShiftISD = ISD; 764 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 765 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 766 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 767 ShiftISD = ISD::SHL; 768 if (const auto *Entry = 769 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 770 return LT.first * Entry->Cost; 771 } 772 773 static const CostTblEntry SSE2UniformShiftCostTable[] = { 774 // Uniform splats are cheaper for the following instructions. 775 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 776 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 777 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 778 779 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 780 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 781 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 782 783 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 784 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 785 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 786 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 787 }; 788 789 if (ST->hasSSE2() && 790 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 791 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 792 793 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 794 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 795 return LT.first * 4; // 2*psrad + shuffle. 796 797 if (const auto *Entry = 798 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 799 return LT.first * Entry->Cost; 800 } 801 802 if (ISD == ISD::SHL && 803 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 804 MVT VT = LT.second; 805 // Vector shift left by non uniform constant can be lowered 806 // into vector multiply. 807 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 808 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 809 ISD = ISD::MUL; 810 } 811 812 static const CostTblEntry AVX2CostTable[] = { 813 { ISD::SHL, MVT::v16i8, 6 }, // vpblendvb sequence. 814 { ISD::SHL, MVT::v32i8, 6 }, // vpblendvb sequence. 815 { ISD::SHL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 816 { ISD::SHL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 817 { ISD::SHL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 818 { ISD::SHL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 819 820 { ISD::SRL, MVT::v16i8, 6 }, // vpblendvb sequence. 821 { ISD::SRL, MVT::v32i8, 6 }, // vpblendvb sequence. 822 { ISD::SRL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 823 { ISD::SRL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 824 { ISD::SRL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 825 { ISD::SRL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 826 827 { ISD::SRA, MVT::v16i8, 17 }, // vpblendvb sequence. 828 { ISD::SRA, MVT::v32i8, 17 }, // vpblendvb sequence. 829 { ISD::SRA, MVT::v64i8, 34 }, // 2*vpblendvb sequence. 830 { ISD::SRA, MVT::v8i16, 5 }, // extend/vpsravd/pack sequence. 831 { ISD::SRA, MVT::v16i16, 7 }, // extend/vpsravd/pack sequence. 832 { ISD::SRA, MVT::v32i16, 14 }, // 2*extend/vpsravd/pack sequence. 833 { ISD::SRA, MVT::v2i64, 2 }, // srl/xor/sub sequence. 834 { ISD::SRA, MVT::v4i64, 2 }, // srl/xor/sub sequence. 835 836 { ISD::SUB, MVT::v32i8, 1 }, // psubb 837 { ISD::ADD, MVT::v32i8, 1 }, // paddb 838 { ISD::SUB, MVT::v16i16, 1 }, // psubw 839 { ISD::ADD, MVT::v16i16, 1 }, // paddw 840 { ISD::SUB, MVT::v8i32, 1 }, // psubd 841 { ISD::ADD, MVT::v8i32, 1 }, // paddd 842 { ISD::SUB, MVT::v4i64, 1 }, // psubq 843 { ISD::ADD, MVT::v4i64, 1 }, // paddq 844 845 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 846 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 847 { ISD::MUL, MVT::v4i64, 6 }, // 3*pmuludq/3*shift/2*add 848 849 { ISD::FNEG, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 850 { ISD::FNEG, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 851 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 852 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 853 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 854 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 855 { ISD::FMUL, MVT::f64, 1 }, // Haswell from http://www.agner.org/ 856 { ISD::FMUL, MVT::v2f64, 1 }, // Haswell from http://www.agner.org/ 857 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 858 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 859 860 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 861 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 862 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 863 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 864 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 865 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 866 }; 867 868 // Look for AVX2 lowering tricks for custom cases. 869 if (ST->hasAVX2()) 870 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 871 return LT.first * Entry->Cost; 872 873 static const CostTblEntry AVX1CostTable[] = { 874 // We don't have to scalarize unsupported ops. We can issue two half-sized 875 // operations and we only need to extract the upper YMM half. 876 // Two ops + 1 extract + 1 insert = 4. 877 { ISD::MUL, MVT::v16i16, 4 }, 878 { ISD::MUL, MVT::v8i32, 5 }, // BTVER2 from http://www.agner.org/ 879 { ISD::MUL, MVT::v4i64, 12 }, 880 881 { ISD::SUB, MVT::v32i8, 4 }, 882 { ISD::ADD, MVT::v32i8, 4 }, 883 { ISD::SUB, MVT::v16i16, 4 }, 884 { ISD::ADD, MVT::v16i16, 4 }, 885 { ISD::SUB, MVT::v8i32, 4 }, 886 { ISD::ADD, MVT::v8i32, 4 }, 887 { ISD::SUB, MVT::v4i64, 4 }, 888 { ISD::ADD, MVT::v4i64, 4 }, 889 890 { ISD::SHL, MVT::v32i8, 22 }, // pblendvb sequence + split. 891 { ISD::SHL, MVT::v8i16, 6 }, // pblendvb sequence. 892 { ISD::SHL, MVT::v16i16, 13 }, // pblendvb sequence + split. 893 { ISD::SHL, MVT::v4i32, 3 }, // pslld/paddd/cvttps2dq/pmulld 894 { ISD::SHL, MVT::v8i32, 9 }, // pslld/paddd/cvttps2dq/pmulld + split 895 { ISD::SHL, MVT::v2i64, 2 }, // Shift each lane + blend. 896 { ISD::SHL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 897 898 { ISD::SRL, MVT::v32i8, 23 }, // pblendvb sequence + split. 899 { ISD::SRL, MVT::v16i16, 28 }, // pblendvb sequence + split. 900 { ISD::SRL, MVT::v4i32, 6 }, // Shift each lane + blend. 901 { ISD::SRL, MVT::v8i32, 14 }, // Shift each lane + blend + split. 902 { ISD::SRL, MVT::v2i64, 2 }, // Shift each lane + blend. 903 { ISD::SRL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 904 905 { ISD::SRA, MVT::v32i8, 44 }, // pblendvb sequence + split. 906 { ISD::SRA, MVT::v16i16, 28 }, // pblendvb sequence + split. 907 { ISD::SRA, MVT::v4i32, 6 }, // Shift each lane + blend. 908 { ISD::SRA, MVT::v8i32, 14 }, // Shift each lane + blend + split. 909 { ISD::SRA, MVT::v2i64, 5 }, // Shift each lane + blend. 910 { ISD::SRA, MVT::v4i64, 12 }, // Shift each lane + blend + split. 911 912 { ISD::FNEG, MVT::v4f64, 2 }, // BTVER2 from http://www.agner.org/ 913 { ISD::FNEG, MVT::v8f32, 2 }, // BTVER2 from http://www.agner.org/ 914 915 { ISD::FMUL, MVT::f64, 2 }, // BTVER2 from http://www.agner.org/ 916 { ISD::FMUL, MVT::v2f64, 2 }, // BTVER2 from http://www.agner.org/ 917 { ISD::FMUL, MVT::v4f64, 4 }, // BTVER2 from http://www.agner.org/ 918 919 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 920 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 921 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 922 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 923 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 924 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 925 }; 926 927 if (ST->hasAVX()) 928 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 929 return LT.first * Entry->Cost; 930 931 static const CostTblEntry SSE42CostTable[] = { 932 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 933 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 934 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 935 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 936 937 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 938 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 939 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 940 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 941 942 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 943 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 944 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 945 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 946 947 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 948 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 949 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 950 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 951 952 { ISD::MUL, MVT::v2i64, 6 } // 3*pmuludq/3*shift/2*add 953 }; 954 955 if (ST->hasSSE42()) 956 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 957 return LT.first * Entry->Cost; 958 959 static const CostTblEntry SSE41CostTable[] = { 960 { ISD::SHL, MVT::v16i8, 10 }, // pblendvb sequence. 961 { ISD::SHL, MVT::v8i16, 11 }, // pblendvb sequence. 962 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 963 964 { ISD::SRL, MVT::v16i8, 11 }, // pblendvb sequence. 965 { ISD::SRL, MVT::v8i16, 13 }, // pblendvb sequence. 966 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 967 968 { ISD::SRA, MVT::v16i8, 21 }, // pblendvb sequence. 969 { ISD::SRA, MVT::v8i16, 13 }, // pblendvb sequence. 970 971 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 972 }; 973 974 if (ST->hasSSE41()) 975 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 976 return LT.first * Entry->Cost; 977 978 static const CostTblEntry SSE2CostTable[] = { 979 // We don't correctly identify costs of casts because they are marked as 980 // custom. 981 { ISD::SHL, MVT::v16i8, 13 }, // cmpgtb sequence. 982 { ISD::SHL, MVT::v8i16, 25 }, // cmpgtw sequence. 983 { ISD::SHL, MVT::v4i32, 16 }, // pslld/paddd/cvttps2dq/pmuludq. 984 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 985 986 { ISD::SRL, MVT::v16i8, 14 }, // cmpgtb sequence. 987 { ISD::SRL, MVT::v8i16, 16 }, // cmpgtw sequence. 988 { ISD::SRL, MVT::v4i32, 12 }, // Shift each lane + blend. 989 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 990 991 { ISD::SRA, MVT::v16i8, 27 }, // unpacked cmpgtb sequence. 992 { ISD::SRA, MVT::v8i16, 16 }, // cmpgtw sequence. 993 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 994 { ISD::SRA, MVT::v2i64, 8 }, // srl/xor/sub splat+shuffle sequence. 995 996 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 997 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 998 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 999 1000 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 1001 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 1002 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 1003 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 1004 1005 { ISD::FNEG, MVT::f32, 1 }, // Pentium IV from http://www.agner.org/ 1006 { ISD::FNEG, MVT::f64, 1 }, // Pentium IV from http://www.agner.org/ 1007 { ISD::FNEG, MVT::v4f32, 1 }, // Pentium IV from http://www.agner.org/ 1008 { ISD::FNEG, MVT::v2f64, 1 }, // Pentium IV from http://www.agner.org/ 1009 1010 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 1011 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 1012 1013 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 1014 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 1015 }; 1016 1017 if (ST->hasSSE2()) 1018 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 1019 return LT.first * Entry->Cost; 1020 1021 static const CostTblEntry SSE1CostTable[] = { 1022 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 1023 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 1024 1025 { ISD::FNEG, MVT::f32, 2 }, // Pentium III from http://www.agner.org/ 1026 { ISD::FNEG, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1027 1028 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1029 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1030 1031 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1032 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1033 }; 1034 1035 if (ST->hasSSE1()) 1036 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 1037 return LT.first * Entry->Cost; 1038 1039 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 1040 { ISD::ADD, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1041 { ISD::SUB, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1042 { ISD::MUL, MVT::i64, 2 }, // Nehalem from http://www.agner.org/ 1043 }; 1044 1045 if (ST->is64Bit()) 1046 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, LT.second)) 1047 return LT.first * Entry->Cost; 1048 1049 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 1050 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1051 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1052 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1053 1054 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1055 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1056 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1057 }; 1058 1059 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, LT.second)) 1060 return LT.first * Entry->Cost; 1061 1062 // It is not a good idea to vectorize division. We have to scalarize it and 1063 // in the process we will often end up having to spilling regular 1064 // registers. The overhead of division is going to dominate most kernels 1065 // anyways so try hard to prevent vectorization of division - it is 1066 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 1067 // to hide "20 cycles" for each lane. 1068 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 1069 ISD == ISD::UDIV || ISD == ISD::UREM)) { 1070 InstructionCost ScalarCost = getArithmeticInstrCost( 1071 Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info, 1072 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 1073 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 1074 } 1075 1076 // Fallback to the default implementation. 1077 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info); 1078 } 1079 1080 InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, 1081 VectorType *BaseTp, 1082 ArrayRef<int> Mask, int Index, 1083 VectorType *SubTp) { 1084 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 1085 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 1086 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 1087 1088 Kind = improveShuffleKindFromMask(Kind, Mask); 1089 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 1090 if (Kind == TTI::SK_Transpose) 1091 Kind = TTI::SK_PermuteTwoSrc; 1092 1093 // For Broadcasts we are splatting the first element from the first input 1094 // register, so only need to reference that input and all the output 1095 // registers are the same. 1096 if (Kind == TTI::SK_Broadcast) 1097 LT.first = 1; 1098 1099 // Subvector extractions are free if they start at the beginning of a 1100 // vector and cheap if the subvectors are aligned. 1101 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 1102 int NumElts = LT.second.getVectorNumElements(); 1103 if ((Index % NumElts) == 0) 1104 return 0; 1105 std::pair<InstructionCost, MVT> SubLT = 1106 TLI->getTypeLegalizationCost(DL, SubTp); 1107 if (SubLT.second.isVector()) { 1108 int NumSubElts = SubLT.second.getVectorNumElements(); 1109 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1110 return SubLT.first; 1111 // Handle some cases for widening legalization. For now we only handle 1112 // cases where the original subvector was naturally aligned and evenly 1113 // fit in its legalized subvector type. 1114 // FIXME: Remove some of the alignment restrictions. 1115 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 1116 // vectors. 1117 int OrigSubElts = cast<FixedVectorType>(SubTp)->getNumElements(); 1118 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 1119 (NumSubElts % OrigSubElts) == 0 && 1120 LT.second.getVectorElementType() == 1121 SubLT.second.getVectorElementType() && 1122 LT.second.getVectorElementType().getSizeInBits() == 1123 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 1124 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 1125 "Unexpected number of elements!"); 1126 auto *VecTy = FixedVectorType::get(BaseTp->getElementType(), 1127 LT.second.getVectorNumElements()); 1128 auto *SubTy = FixedVectorType::get(BaseTp->getElementType(), 1129 SubLT.second.getVectorNumElements()); 1130 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 1131 InstructionCost ExtractCost = getShuffleCost( 1132 TTI::SK_ExtractSubvector, VecTy, None, ExtractIndex, SubTy); 1133 1134 // If the original size is 32-bits or more, we can use pshufd. Otherwise 1135 // if we have SSSE3 we can use pshufb. 1136 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 1137 return ExtractCost + 1; // pshufd or pshufb 1138 1139 assert(SubTp->getPrimitiveSizeInBits() == 16 && 1140 "Unexpected vector size"); 1141 1142 return ExtractCost + 2; // worst case pshufhw + pshufd 1143 } 1144 } 1145 } 1146 1147 // Subvector insertions are cheap if the subvectors are aligned. 1148 // Note that in general, the insertion starting at the beginning of a vector 1149 // isn't free, because we need to preserve the rest of the wide vector. 1150 if (Kind == TTI::SK_InsertSubvector && LT.second.isVector()) { 1151 int NumElts = LT.second.getVectorNumElements(); 1152 std::pair<InstructionCost, MVT> SubLT = 1153 TLI->getTypeLegalizationCost(DL, SubTp); 1154 if (SubLT.second.isVector()) { 1155 int NumSubElts = SubLT.second.getVectorNumElements(); 1156 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1157 return SubLT.first; 1158 } 1159 1160 // If the insertion isn't aligned, treat it like a 2-op shuffle. 1161 Kind = TTI::SK_PermuteTwoSrc; 1162 } 1163 1164 // Handle some common (illegal) sub-vector types as they are often very cheap 1165 // to shuffle even on targets without PSHUFB. 1166 EVT VT = TLI->getValueType(DL, BaseTp); 1167 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 1168 !ST->hasSSSE3()) { 1169 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 1170 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 1171 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1172 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1173 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1174 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1175 1176 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1177 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1178 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1179 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1180 1181 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1182 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1183 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1184 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1185 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1186 1187 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1188 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1189 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1190 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1191 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1192 }; 1193 1194 if (ST->hasSSE2()) 1195 if (const auto *Entry = 1196 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1197 return Entry->Cost; 1198 } 1199 1200 // We are going to permute multiple sources and the result will be in multiple 1201 // destinations. Providing an accurate cost only for splits where the element 1202 // type remains the same. 1203 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1204 MVT LegalVT = LT.second; 1205 if (LegalVT.isVector() && 1206 LegalVT.getVectorElementType().getSizeInBits() == 1207 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1208 LegalVT.getVectorNumElements() < 1209 cast<FixedVectorType>(BaseTp)->getNumElements()) { 1210 1211 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1212 unsigned LegalVTSize = LegalVT.getStoreSize(); 1213 // Number of source vectors after legalization: 1214 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1215 // Number of destination vectors after legalization: 1216 InstructionCost NumOfDests = LT.first; 1217 1218 auto *SingleOpTy = FixedVectorType::get(BaseTp->getElementType(), 1219 LegalVT.getVectorNumElements()); 1220 1221 InstructionCost NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1222 return NumOfShuffles * getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 1223 None, 0, nullptr); 1224 } 1225 1226 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1227 } 1228 1229 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1230 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1231 // We assume that source and destination have the same vector type. 1232 InstructionCost NumOfDests = LT.first; 1233 InstructionCost NumOfShufflesPerDest = LT.first * 2 - 1; 1234 LT.first = NumOfDests * NumOfShufflesPerDest; 1235 } 1236 1237 static const CostTblEntry AVX512FP16ShuffleTbl[] = { 1238 {TTI::SK_Broadcast, MVT::v32f16, 1}, // vpbroadcastw 1239 {TTI::SK_Broadcast, MVT::v16f16, 1}, // vpbroadcastw 1240 {TTI::SK_Broadcast, MVT::v8f16, 1}, // vpbroadcastw 1241 1242 {TTI::SK_Reverse, MVT::v32f16, 2}, // vpermw 1243 {TTI::SK_Reverse, MVT::v16f16, 2}, // vpermw 1244 {TTI::SK_Reverse, MVT::v8f16, 1}, // vpshufb 1245 1246 {TTI::SK_PermuteSingleSrc, MVT::v32f16, 2}, // vpermw 1247 {TTI::SK_PermuteSingleSrc, MVT::v16f16, 2}, // vpermw 1248 {TTI::SK_PermuteSingleSrc, MVT::v8f16, 1}, // vpshufb 1249 1250 {TTI::SK_PermuteTwoSrc, MVT::v32f16, 2}, // vpermt2w 1251 {TTI::SK_PermuteTwoSrc, MVT::v16f16, 2}, // vpermt2w 1252 {TTI::SK_PermuteTwoSrc, MVT::v8f16, 2} // vpermt2w 1253 }; 1254 1255 if (!ST->useSoftFloat() && ST->hasFP16()) 1256 if (const auto *Entry = 1257 CostTableLookup(AVX512FP16ShuffleTbl, Kind, LT.second)) 1258 return LT.first * Entry->Cost; 1259 1260 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1261 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1262 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1263 1264 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1265 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1266 1267 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b 1268 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b 1269 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2} // vpermt2b 1270 }; 1271 1272 if (ST->hasVBMI()) 1273 if (const auto *Entry = 1274 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1275 return LT.first * Entry->Cost; 1276 1277 static const CostTblEntry AVX512BWShuffleTbl[] = { 1278 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1279 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1280 1281 {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw 1282 {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw 1283 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1284 1285 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw 1286 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw 1287 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1288 1289 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w 1290 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w 1291 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2}, // vpermt2w 1292 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1293 1294 {TTI::SK_Select, MVT::v32i16, 1}, // vblendmw 1295 {TTI::SK_Select, MVT::v64i8, 1}, // vblendmb 1296 }; 1297 1298 if (ST->hasBWI()) 1299 if (const auto *Entry = 1300 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1301 return LT.first * Entry->Cost; 1302 1303 static const CostTblEntry AVX512ShuffleTbl[] = { 1304 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1305 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1306 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1307 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1308 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1309 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1310 1311 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1312 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1313 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1314 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1315 {TTI::SK_Reverse, MVT::v32i16, 7}, // per mca 1316 {TTI::SK_Reverse, MVT::v64i8, 7}, // per mca 1317 1318 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1319 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1320 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1321 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1322 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1323 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1324 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1325 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1326 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1327 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1328 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1329 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1330 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1331 1332 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1333 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1334 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1335 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1336 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1337 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1338 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1339 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1340 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1341 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1342 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1343 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1344 1345 // FIXME: This just applies the type legalization cost rules above 1346 // assuming these completely split. 1347 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1348 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1349 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1350 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1351 1352 {TTI::SK_Select, MVT::v32i16, 1}, // vpternlogq 1353 {TTI::SK_Select, MVT::v64i8, 1}, // vpternlogq 1354 {TTI::SK_Select, MVT::v8f64, 1}, // vblendmpd 1355 {TTI::SK_Select, MVT::v16f32, 1}, // vblendmps 1356 {TTI::SK_Select, MVT::v8i64, 1}, // vblendmq 1357 {TTI::SK_Select, MVT::v16i32, 1}, // vblendmd 1358 }; 1359 1360 if (ST->hasAVX512()) 1361 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1362 return LT.first * Entry->Cost; 1363 1364 static const CostTblEntry AVX2ShuffleTbl[] = { 1365 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1366 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1367 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1368 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1369 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1370 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1371 1372 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1373 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1374 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1375 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1376 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1377 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1378 1379 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1380 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1381 1382 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1383 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1384 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1385 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1386 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1387 // + vpblendvb 1388 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1389 // + vpblendvb 1390 1391 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1392 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1393 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1394 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1395 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1396 // + vpblendvb 1397 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1398 // + vpblendvb 1399 }; 1400 1401 if (ST->hasAVX2()) 1402 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1403 return LT.first * Entry->Cost; 1404 1405 static const CostTblEntry XOPShuffleTbl[] = { 1406 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1407 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1408 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1409 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1410 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1411 // + vinsertf128 1412 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1413 // + vinsertf128 1414 1415 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1416 // + vinsertf128 1417 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1418 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1419 // + vinsertf128 1420 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1421 }; 1422 1423 if (ST->hasXOP()) 1424 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1425 return LT.first * Entry->Cost; 1426 1427 static const CostTblEntry AVX1ShuffleTbl[] = { 1428 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1429 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1430 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1431 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1432 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1433 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1434 1435 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1436 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1437 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1438 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1439 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1440 // + vinsertf128 1441 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1442 // + vinsertf128 1443 1444 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1445 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1446 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1447 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1448 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1449 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1450 1451 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1452 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1453 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1454 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1455 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1456 // + 2*por + vinsertf128 1457 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1458 // + 2*por + vinsertf128 1459 1460 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1461 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1462 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1463 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1464 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1465 // + 4*por + vinsertf128 1466 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1467 // + 4*por + vinsertf128 1468 }; 1469 1470 if (ST->hasAVX()) 1471 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1472 return LT.first * Entry->Cost; 1473 1474 static const CostTblEntry SSE41ShuffleTbl[] = { 1475 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1476 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1477 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1478 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1479 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1480 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1481 }; 1482 1483 if (ST->hasSSE41()) 1484 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1485 return LT.first * Entry->Cost; 1486 1487 static const CostTblEntry SSSE3ShuffleTbl[] = { 1488 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1489 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1490 1491 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1492 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1493 1494 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1495 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1496 1497 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1498 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1499 1500 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1501 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1502 }; 1503 1504 if (ST->hasSSSE3()) 1505 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1506 return LT.first * Entry->Cost; 1507 1508 static const CostTblEntry SSE2ShuffleTbl[] = { 1509 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1510 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1511 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1512 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1513 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1514 1515 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1516 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1517 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1518 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1519 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1520 // + 2*pshufd + 2*unpck + packus 1521 1522 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1523 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1524 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1525 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1526 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1527 1528 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1529 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1530 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1531 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1532 // + pshufd/unpck 1533 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1534 // + 2*pshufd + 2*unpck + 2*packus 1535 1536 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1537 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1538 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1539 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1540 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1541 }; 1542 1543 if (ST->hasSSE2()) 1544 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1545 return LT.first * Entry->Cost; 1546 1547 static const CostTblEntry SSE1ShuffleTbl[] = { 1548 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1549 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1550 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1551 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1552 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1553 }; 1554 1555 if (ST->hasSSE1()) 1556 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1557 return LT.first * Entry->Cost; 1558 1559 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1560 } 1561 1562 InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, 1563 Type *Src, 1564 TTI::CastContextHint CCH, 1565 TTI::TargetCostKind CostKind, 1566 const Instruction *I) { 1567 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1568 assert(ISD && "Invalid opcode"); 1569 1570 // TODO: Allow non-throughput costs that aren't binary. 1571 auto AdjustCost = [&CostKind](InstructionCost Cost) -> InstructionCost { 1572 if (CostKind != TTI::TCK_RecipThroughput) 1573 return Cost == 0 ? 0 : 1; 1574 return Cost; 1575 }; 1576 1577 // The cost tables include both specific, custom (non-legal) src/dst type 1578 // conversions and generic, legalized types. We test for customs first, before 1579 // falling back to legalization. 1580 // FIXME: Need a better design of the cost table to handle non-simple types of 1581 // potential massive combinations (elem_num x src_type x dst_type). 1582 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1583 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1584 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1585 1586 // Mask sign extend has an instruction. 1587 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1588 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v2i1, 1 }, 1589 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1590 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v2i1, 1 }, 1591 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1592 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v4i1, 1 }, 1593 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1594 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v4i1, 1 }, 1595 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1596 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v8i1, 1 }, 1597 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1598 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1599 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1600 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1601 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1602 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1603 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v64i1, 1 }, 1604 1605 // Mask zero extend is a sext + shift. 1606 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1607 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v2i1, 2 }, 1608 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1609 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v2i1, 2 }, 1610 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1611 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v4i1, 2 }, 1612 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1613 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v4i1, 2 }, 1614 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1615 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v8i1, 2 }, 1616 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1617 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1618 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1619 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1620 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1621 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1622 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v64i1, 2 }, 1623 1624 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, 1625 { ISD::TRUNCATE, MVT::v2i1, MVT::v16i8, 2 }, 1626 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, 1627 { ISD::TRUNCATE, MVT::v2i1, MVT::v8i16, 2 }, 1628 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, 1629 { ISD::TRUNCATE, MVT::v4i1, MVT::v16i8, 2 }, 1630 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, 1631 { ISD::TRUNCATE, MVT::v4i1, MVT::v8i16, 2 }, 1632 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, 1633 { ISD::TRUNCATE, MVT::v8i1, MVT::v16i8, 2 }, 1634 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, 1635 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, 1636 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, 1637 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, 1638 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, 1639 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, 1640 { ISD::TRUNCATE, MVT::v64i1, MVT::v32i16, 2 }, 1641 1642 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, 1643 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm 1644 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // vpmovwb 1645 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // vpmovwb 1646 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // vpmovwb 1647 }; 1648 1649 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1650 // Mask sign extend has an instruction. 1651 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, 1652 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v2i1, 1 }, 1653 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, 1654 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, 1655 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, 1656 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v16i1, 1 }, 1657 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, 1658 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, 1659 1660 // Mask zero extend is a sext + shift. 1661 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, 1662 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v2i1, 2 }, 1663 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, 1664 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, 1665 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, 1666 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v16i1, 2 }, 1667 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, 1668 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1669 1670 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, 1671 { ISD::TRUNCATE, MVT::v2i1, MVT::v4i32, 2 }, 1672 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, 1673 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, 1674 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1675 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, 1676 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, 1677 { ISD::TRUNCATE, MVT::v16i1, MVT::v8i64, 2 }, 1678 1679 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1680 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1681 1682 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1683 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1684 1685 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1686 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1687 1688 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1689 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1690 }; 1691 1692 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1693 // 256-bit wide vectors. 1694 1695 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1696 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1697 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1698 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1699 1700 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1701 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1702 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1703 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd 1704 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1705 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1706 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1707 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd 1708 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd 1709 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd 1710 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd 1711 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd 1712 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq 1713 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq 1714 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq 1715 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 2 }, // vpmovdb 1716 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 2 }, // vpmovdb 1717 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, // vpmovdb 1718 { ISD::TRUNCATE, MVT::v32i8, MVT::v16i32, 2 }, // vpmovdb 1719 { ISD::TRUNCATE, MVT::v64i8, MVT::v16i32, 2 }, // vpmovdb 1720 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, // vpmovdw 1721 { ISD::TRUNCATE, MVT::v32i16, MVT::v16i32, 2 }, // vpmovdw 1722 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 2 }, // vpmovqb 1723 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 1 }, // vpshufb 1724 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, // vpmovqb 1725 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i64, 2 }, // vpmovqb 1726 { ISD::TRUNCATE, MVT::v32i8, MVT::v8i64, 2 }, // vpmovqb 1727 { ISD::TRUNCATE, MVT::v64i8, MVT::v8i64, 2 }, // vpmovqb 1728 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, // vpmovqw 1729 { ISD::TRUNCATE, MVT::v16i16, MVT::v8i64, 2 }, // vpmovqw 1730 { ISD::TRUNCATE, MVT::v32i16, MVT::v8i64, 2 }, // vpmovqw 1731 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, // vpmovqd 1732 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd 1733 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb 1734 1735 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32 1736 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, 1737 { ISD::TRUNCATE, MVT::v64i8, MVT::v32i16, 8 }, 1738 1739 // Sign extend is zmm vpternlogd+vptruncdb. 1740 // Zero extend is zmm broadcast load+vptruncdw. 1741 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 }, 1742 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 }, 1743 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, 1744 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, 1745 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, 1746 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, 1747 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 }, 1748 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 }, 1749 1750 // Sign extend is zmm vpternlogd+vptruncdw. 1751 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw. 1752 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 }, 1753 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1754 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 }, 1755 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1756 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 }, 1757 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1758 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 }, 1759 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1760 1761 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd 1762 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld 1763 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd 1764 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld 1765 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd 1766 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld 1767 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq 1768 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq 1769 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq 1770 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq 1771 1772 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd 1773 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld 1774 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq 1775 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq 1776 1777 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1778 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1779 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1780 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1781 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1782 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1783 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1784 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1785 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1786 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1787 1788 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1789 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1790 1791 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1792 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1793 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, 1794 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, 1795 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1796 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, 1797 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1798 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1799 1800 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1801 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1802 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, 1803 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, 1804 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1805 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, 1806 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1807 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1808 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1809 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1810 1811 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2 }, 1812 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f64, 7 }, 1813 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f64,15 }, 1814 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f32,11 }, 1815 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f64,31 }, 1816 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, 1817 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f64, 7 }, 1818 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f32, 5 }, 1819 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f64,15 }, 1820 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 1 }, 1821 { ISD::FP_TO_SINT, MVT::v16i32, MVT::v16f64, 3 }, 1822 1823 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1824 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, 1825 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, 1826 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1827 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, 1828 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, 1829 }; 1830 1831 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1832 // Mask sign extend has an instruction. 1833 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1834 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v2i1, 1 }, 1835 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1836 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v2i1, 1 }, 1837 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1838 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v4i1, 1 }, 1839 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1840 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v4i1, 1 }, 1841 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1842 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v8i1, 1 }, 1843 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1844 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1845 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1846 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1847 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v32i1, 1 }, 1848 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v64i1, 1 }, 1849 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v64i1, 1 }, 1850 1851 // Mask zero extend is a sext + shift. 1852 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1853 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v2i1, 2 }, 1854 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1855 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v2i1, 2 }, 1856 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1857 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v4i1, 2 }, 1858 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1859 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v4i1, 2 }, 1860 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1861 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v8i1, 2 }, 1862 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1863 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1864 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1865 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1866 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v32i1, 2 }, 1867 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v64i1, 2 }, 1868 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v64i1, 2 }, 1869 1870 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, 1871 { ISD::TRUNCATE, MVT::v2i1, MVT::v16i8, 2 }, 1872 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, 1873 { ISD::TRUNCATE, MVT::v2i1, MVT::v8i16, 2 }, 1874 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, 1875 { ISD::TRUNCATE, MVT::v4i1, MVT::v16i8, 2 }, 1876 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, 1877 { ISD::TRUNCATE, MVT::v4i1, MVT::v8i16, 2 }, 1878 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, 1879 { ISD::TRUNCATE, MVT::v8i1, MVT::v16i8, 2 }, 1880 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, 1881 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, 1882 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, 1883 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, 1884 { ISD::TRUNCATE, MVT::v32i1, MVT::v16i16, 2 }, 1885 { ISD::TRUNCATE, MVT::v64i1, MVT::v32i8, 2 }, 1886 { ISD::TRUNCATE, MVT::v64i1, MVT::v16i16, 2 }, 1887 1888 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, 1889 }; 1890 1891 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1892 // Mask sign extend has an instruction. 1893 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, 1894 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v2i1, 1 }, 1895 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, 1896 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i1, 1 }, 1897 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, 1898 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i1, 1 }, 1899 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i1, 1 }, 1900 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, 1901 1902 // Mask zero extend is a sext + shift. 1903 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, 1904 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v2i1, 2 }, 1905 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, 1906 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i1, 2 }, 1907 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, 1908 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i1, 2 }, 1909 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i1, 2 }, 1910 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, 1911 1912 { ISD::TRUNCATE, MVT::v16i1, MVT::v4i64, 2 }, 1913 { ISD::TRUNCATE, MVT::v16i1, MVT::v8i32, 2 }, 1914 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, 1915 { ISD::TRUNCATE, MVT::v2i1, MVT::v4i32, 2 }, 1916 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, 1917 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, 1918 { ISD::TRUNCATE, MVT::v8i1, MVT::v4i64, 2 }, 1919 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1920 1921 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1922 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1923 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1924 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1925 1926 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1927 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1928 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1929 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1930 1931 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v4f32, 1 }, 1932 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1933 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1934 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1935 1936 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v4f32, 1 }, 1937 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1938 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1939 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1940 }; 1941 1942 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 1943 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1944 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1945 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1946 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 8 }, // split+2*v8i8 1947 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1948 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1949 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1950 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16 1951 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // vpslld+vptestmd 1952 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd 1953 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // vpslld+vptestmd 1954 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // vpsllq+vptestmq 1955 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // vpsllq+vptestmq 1956 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // vpmovqd 1957 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, // vpmovqb 1958 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, // vpmovqw 1959 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, // vpmovwb 1960 1961 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb 1962 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb 1963 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 }, 1964 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 }, 1965 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 }, 1966 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 }, 1967 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 }, 1968 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 }, 1969 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 }, 1970 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 }, 1971 1972 // sign extend is vpcmpeq+maskedmove+vpmovdw 1973 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw 1974 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1975 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 }, 1976 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1977 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 }, 1978 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1979 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 }, 1980 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 }, 1981 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 }, 1982 1983 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd 1984 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld 1985 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd 1986 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld 1987 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd 1988 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld 1989 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq 1990 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq 1991 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq 1992 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq 1993 1994 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 1 }, 1995 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 1 }, 1996 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 1 }, 1997 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 1 }, 1998 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1999 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 2000 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 1 }, 2001 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 1 }, 2002 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 2003 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 2004 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 2005 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 2006 2007 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2008 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 1 }, 2009 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2010 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 1 }, 2011 2012 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 2013 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 2014 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2015 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 1 }, 2016 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2017 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 1 }, 2018 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 2019 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 2020 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 2021 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 2022 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 2023 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 2024 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 2025 2026 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v8f32, 2 }, 2027 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2 }, 2028 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f32, 5 }, 2029 2030 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 2031 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 2032 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 2033 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 1 }, 2034 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 2035 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 2036 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 2037 }; 2038 2039 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 2040 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 2041 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 2042 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 2043 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 2044 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 2045 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 2046 2047 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 2 }, 2048 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 2 }, 2049 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 2 }, 2050 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 2 }, 2051 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 2052 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 2053 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 2 }, 2054 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 2 }, 2055 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 2056 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 2057 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 2058 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 2059 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 2060 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 2061 2062 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 2063 2064 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 4 }, 2065 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 4 }, 2066 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i16, 1 }, 2067 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 1 }, 2068 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 1 }, 2069 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i32, 4 }, 2070 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i64, 4 }, 2071 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 1 }, 2072 { ISD::TRUNCATE, MVT::v8i16, MVT::v2i64, 1 }, 2073 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i64, 5 }, 2074 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, 2075 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 2076 2077 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 2078 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 2079 2080 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v8f32, 1 }, 2081 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 1 }, 2082 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 1 }, 2083 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 3 }, 2084 2085 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 3 }, 2086 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 3 }, 2087 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v8f32, 1 }, 2088 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 3 }, 2089 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 2090 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4 }, 2091 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 3 }, 2092 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v4f64, 4 }, 2093 2094 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 2 }, 2095 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 2 }, 2096 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 2 }, 2097 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 2098 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 2099 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 2100 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 3 }, 2101 2102 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 2 }, 2103 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 2 }, 2104 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 2 }, 2105 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 2106 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 2107 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 2108 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 2 }, 2109 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2110 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 2111 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 }, 2112 }; 2113 2114 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 2115 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 2116 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 2117 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 2118 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 2119 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 2120 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 2121 2122 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 3 }, 2123 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 3 }, 2124 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 3 }, 2125 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 3 }, 2126 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 2127 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 2128 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 3 }, 2129 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 3 }, 2130 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 2131 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 2132 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 2133 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 2134 2135 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 4 }, 2136 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 5 }, 2137 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 4 }, 2138 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 9 }, 2139 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, 11 }, 2140 2141 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 2142 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, 2143 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // and+extract+packuswb 2144 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i32, 5 }, 2145 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2146 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i64, 5 }, 2147 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i64, 3 }, // and+extract+2*packusdw 2148 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 2149 2150 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 2151 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 2152 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 2153 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 4 }, 2154 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v16i8, 2 }, 2155 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 2156 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v8i16, 2 }, 2157 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2158 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 2159 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 }, 2160 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 5 }, 2161 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 8 }, 2162 2163 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 2164 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 2165 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 2166 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 4 }, 2167 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v16i8, 2 }, 2168 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 2169 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v8i16, 2 }, 2170 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 4 }, 2171 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 4 }, 2172 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 2173 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 2174 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 2175 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 10 }, 2176 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 10 }, 2177 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 18 }, 2178 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 2179 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 10 }, 2180 2181 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v8f32, 2 }, 2182 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f64, 2 }, 2183 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v8f32, 2 }, 2184 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v4f64, 2 }, 2185 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 2 }, 2186 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f64, 2 }, 2187 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v8f32, 2 }, 2188 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v4f64, 2 }, 2189 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 2 }, 2190 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 2 }, 2191 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 5 }, 2192 2193 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v8f32, 2 }, 2194 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f64, 2 }, 2195 { ISD::FP_TO_UINT, MVT::v32i8, MVT::v8f32, 2 }, 2196 { ISD::FP_TO_UINT, MVT::v32i8, MVT::v4f64, 2 }, 2197 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 2 }, 2198 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f64, 2 }, 2199 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v8f32, 2 }, 2200 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v4f64, 2 }, 2201 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 3 }, 2202 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 2203 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 6 }, 2204 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 7 }, 2205 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v4f64, 7 }, 2206 2207 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 2208 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 2209 }; 2210 2211 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 2212 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8, 1 }, 2213 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8, 1 }, 2214 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8, 1 }, 2215 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8, 1 }, 2216 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2217 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2218 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16, 1 }, 2219 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16, 1 }, 2220 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2221 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2222 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2223 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2224 2225 // These truncates end up widening elements. 2226 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 1 }, // PMOVXZBQ 2227 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 1 }, // PMOVXZWQ 2228 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 1 }, // PMOVXZBD 2229 2230 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 2 }, 2231 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 2 }, 2232 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 2 }, 2233 2234 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 1 }, 2235 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 1 }, 2236 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 1 }, 2237 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 1 }, 2238 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 1 }, 2239 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2240 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 1 }, 2241 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2242 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 2243 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 1 }, 2244 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2245 2246 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 1 }, 2247 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 1 }, 2248 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 2249 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 2250 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 1 }, 2251 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2252 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 1 }, 2253 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2254 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 3 }, 2255 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 3 }, 2256 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 2 }, 2257 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 12 }, 2258 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 22 }, 2259 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 4 }, 2260 2261 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 1 }, 2262 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 1 }, 2263 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 1 }, 2264 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 1 }, 2265 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f32, 2 }, 2266 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v2f64, 2 }, 2267 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f32, 1 }, 2268 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v2f64, 1 }, 2269 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, 2270 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v2f64, 1 }, 2271 2272 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 1 }, 2273 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 2274 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 1 }, 2275 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 2276 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f32, 2 }, 2277 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v2f64, 2 }, 2278 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f32, 1 }, 2279 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v2f64, 1 }, 2280 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 4 }, 2281 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 2282 }; 2283 2284 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 2285 // These are somewhat magic numbers justified by comparing the 2286 // output of llvm-mca for our various supported scheduler models 2287 // and basing it off the worst case scenario. 2288 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 3 }, 2289 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 3 }, 2290 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 3 }, 2291 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 3 }, 2292 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 3 }, 2293 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 4 }, 2294 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 3 }, 2295 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 4 }, 2296 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 3 }, 2297 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4 }, 2298 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 8 }, 2299 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 8 }, 2300 2301 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 3 }, 2302 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 3 }, 2303 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 8 }, 2304 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 9 }, 2305 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 4 }, 2306 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 4 }, 2307 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 4 }, 2308 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 4 }, 2309 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 7 }, 2310 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 7 }, 2311 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 2312 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 15 }, 2313 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 18 }, 2314 2315 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 4 }, 2316 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 4 }, 2317 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 4 }, 2318 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 4 }, 2319 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f32, 6 }, 2320 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v2f64, 6 }, 2321 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f32, 5 }, 2322 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v2f64, 5 }, 2323 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 4 }, 2324 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v2f64, 4 }, 2325 2326 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 4 }, 2327 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 2328 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 4 }, 2329 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 15 }, 2330 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f32, 6 }, 2331 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v2f64, 6 }, 2332 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f32, 5 }, 2333 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v2f64, 5 }, 2334 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 8 }, 2335 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 8 }, 2336 2337 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8, 4 }, 2338 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8, 4 }, 2339 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8, 2 }, 2340 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8, 3 }, 2341 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2342 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8, 2 }, 2343 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16, 2 }, 2344 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16, 3 }, 2345 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2346 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16, 2 }, 2347 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2348 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32, 2 }, 2349 2350 // These truncates are really widening elements. 2351 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 1 }, // PSHUFD 2352 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // PUNPCKLWD+DQ 2353 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // PUNPCKLBW+WD+PSHUFD 2354 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 1 }, // PUNPCKLWD 2355 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // PUNPCKLBW+WD 2356 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 1 }, // PUNPCKLBW 2357 2358 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i16, 2 }, // PAND+PACKUSWB 2359 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 2360 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 3 }, // PAND+2*PACKUSWB 2361 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 2362 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 2363 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 3 }, 2364 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2365 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32,10 }, 2366 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 2367 { ISD::TRUNCATE, MVT::v8i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 2368 { ISD::TRUNCATE, MVT::v4i32, MVT::v2i64, 1 }, // PSHUFD 2369 }; 2370 2371 // Attempt to map directly to (simple) MVT types to let us match custom entries. 2372 EVT SrcTy = TLI->getValueType(DL, Src); 2373 EVT DstTy = TLI->getValueType(DL, Dst); 2374 2375 // The function getSimpleVT only handles simple value types. 2376 if (SrcTy.isSimple() && DstTy.isSimple()) { 2377 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 2378 MVT SimpleDstTy = DstTy.getSimpleVT(); 2379 2380 if (ST->useAVX512Regs()) { 2381 if (ST->hasBWI()) 2382 if (const auto *Entry = ConvertCostTableLookup( 2383 AVX512BWConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2384 return AdjustCost(Entry->Cost); 2385 2386 if (ST->hasDQI()) 2387 if (const auto *Entry = ConvertCostTableLookup( 2388 AVX512DQConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2389 return AdjustCost(Entry->Cost); 2390 2391 if (ST->hasAVX512()) 2392 if (const auto *Entry = ConvertCostTableLookup( 2393 AVX512FConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2394 return AdjustCost(Entry->Cost); 2395 } 2396 2397 if (ST->hasBWI()) 2398 if (const auto *Entry = ConvertCostTableLookup( 2399 AVX512BWVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2400 return AdjustCost(Entry->Cost); 2401 2402 if (ST->hasDQI()) 2403 if (const auto *Entry = ConvertCostTableLookup( 2404 AVX512DQVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2405 return AdjustCost(Entry->Cost); 2406 2407 if (ST->hasAVX512()) 2408 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2409 SimpleDstTy, SimpleSrcTy)) 2410 return AdjustCost(Entry->Cost); 2411 2412 if (ST->hasAVX2()) { 2413 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2414 SimpleDstTy, SimpleSrcTy)) 2415 return AdjustCost(Entry->Cost); 2416 } 2417 2418 if (ST->hasAVX()) { 2419 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2420 SimpleDstTy, SimpleSrcTy)) 2421 return AdjustCost(Entry->Cost); 2422 } 2423 2424 if (ST->hasSSE41()) { 2425 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2426 SimpleDstTy, SimpleSrcTy)) 2427 return AdjustCost(Entry->Cost); 2428 } 2429 2430 if (ST->hasSSE2()) { 2431 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2432 SimpleDstTy, SimpleSrcTy)) 2433 return AdjustCost(Entry->Cost); 2434 } 2435 } 2436 2437 // Fall back to legalized types. 2438 std::pair<InstructionCost, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 2439 std::pair<InstructionCost, MVT> LTDest = 2440 TLI->getTypeLegalizationCost(DL, Dst); 2441 2442 if (ST->useAVX512Regs()) { 2443 if (ST->hasBWI()) 2444 if (const auto *Entry = ConvertCostTableLookup( 2445 AVX512BWConversionTbl, ISD, LTDest.second, LTSrc.second)) 2446 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2447 2448 if (ST->hasDQI()) 2449 if (const auto *Entry = ConvertCostTableLookup( 2450 AVX512DQConversionTbl, ISD, LTDest.second, LTSrc.second)) 2451 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2452 2453 if (ST->hasAVX512()) 2454 if (const auto *Entry = ConvertCostTableLookup( 2455 AVX512FConversionTbl, ISD, LTDest.second, LTSrc.second)) 2456 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2457 } 2458 2459 if (ST->hasBWI()) 2460 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 2461 LTDest.second, LTSrc.second)) 2462 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2463 2464 if (ST->hasDQI()) 2465 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 2466 LTDest.second, LTSrc.second)) 2467 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2468 2469 if (ST->hasAVX512()) 2470 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2471 LTDest.second, LTSrc.second)) 2472 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2473 2474 if (ST->hasAVX2()) 2475 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2476 LTDest.second, LTSrc.second)) 2477 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2478 2479 if (ST->hasAVX()) 2480 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2481 LTDest.second, LTSrc.second)) 2482 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2483 2484 if (ST->hasSSE41()) 2485 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2486 LTDest.second, LTSrc.second)) 2487 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2488 2489 if (ST->hasSSE2()) 2490 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2491 LTDest.second, LTSrc.second)) 2492 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2493 2494 // Fallback, for i8/i16 sitofp/uitofp cases we need to extend to i32 for 2495 // sitofp. 2496 if ((ISD == ISD::SINT_TO_FP || ISD == ISD::UINT_TO_FP) && 2497 1 < Src->getScalarSizeInBits() && Src->getScalarSizeInBits() < 32) { 2498 Type *ExtSrc = Src->getWithNewBitWidth(32); 2499 unsigned ExtOpc = 2500 (ISD == ISD::SINT_TO_FP) ? Instruction::SExt : Instruction::ZExt; 2501 2502 // For scalar loads the extend would be free. 2503 InstructionCost ExtCost = 0; 2504 if (!(Src->isIntegerTy() && I && isa<LoadInst>(I->getOperand(0)))) 2505 ExtCost = getCastInstrCost(ExtOpc, ExtSrc, Src, CCH, CostKind); 2506 2507 return ExtCost + getCastInstrCost(Instruction::SIToFP, Dst, ExtSrc, 2508 TTI::CastContextHint::None, CostKind); 2509 } 2510 2511 // Fallback for fptosi/fptoui i8/i16 cases we need to truncate from fptosi 2512 // i32. 2513 if ((ISD == ISD::FP_TO_SINT || ISD == ISD::FP_TO_UINT) && 2514 1 < Dst->getScalarSizeInBits() && Dst->getScalarSizeInBits() < 32) { 2515 Type *TruncDst = Dst->getWithNewBitWidth(32); 2516 return getCastInstrCost(Instruction::FPToSI, TruncDst, Src, CCH, CostKind) + 2517 getCastInstrCost(Instruction::Trunc, Dst, TruncDst, 2518 TTI::CastContextHint::None, CostKind); 2519 } 2520 2521 return AdjustCost( 2522 BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I)); 2523 } 2524 2525 InstructionCost X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 2526 Type *CondTy, 2527 CmpInst::Predicate VecPred, 2528 TTI::TargetCostKind CostKind, 2529 const Instruction *I) { 2530 // TODO: Handle other cost kinds. 2531 if (CostKind != TTI::TCK_RecipThroughput) 2532 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, 2533 I); 2534 2535 // Legalize the type. 2536 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2537 2538 MVT MTy = LT.second; 2539 2540 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2541 assert(ISD && "Invalid opcode"); 2542 2543 unsigned ExtraCost = 0; 2544 if (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp) { 2545 // Some vector comparison predicates cost extra instructions. 2546 // TODO: Should we invert this and assume worst case cmp costs 2547 // and reduce for particular predicates? 2548 if (MTy.isVector() && 2549 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 2550 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 2551 ST->hasBWI())) { 2552 // Fallback to I if a specific predicate wasn't specified. 2553 CmpInst::Predicate Pred = VecPred; 2554 if (I && (Pred == CmpInst::BAD_ICMP_PREDICATE || 2555 Pred == CmpInst::BAD_FCMP_PREDICATE)) 2556 Pred = cast<CmpInst>(I)->getPredicate(); 2557 2558 switch (Pred) { 2559 case CmpInst::Predicate::ICMP_NE: 2560 // xor(cmpeq(x,y),-1) 2561 ExtraCost = 1; 2562 break; 2563 case CmpInst::Predicate::ICMP_SGE: 2564 case CmpInst::Predicate::ICMP_SLE: 2565 // xor(cmpgt(x,y),-1) 2566 ExtraCost = 1; 2567 break; 2568 case CmpInst::Predicate::ICMP_ULT: 2569 case CmpInst::Predicate::ICMP_UGT: 2570 // cmpgt(xor(x,signbit),xor(y,signbit)) 2571 // xor(cmpeq(pmaxu(x,y),x),-1) 2572 ExtraCost = 2; 2573 break; 2574 case CmpInst::Predicate::ICMP_ULE: 2575 case CmpInst::Predicate::ICMP_UGE: 2576 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 2577 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 2578 // cmpeq(psubus(x,y),0) 2579 // cmpeq(pminu(x,y),x) 2580 ExtraCost = 1; 2581 } else { 2582 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 2583 ExtraCost = 3; 2584 } 2585 break; 2586 case CmpInst::Predicate::BAD_ICMP_PREDICATE: 2587 case CmpInst::Predicate::BAD_FCMP_PREDICATE: 2588 // Assume worst case scenario and add the maximum extra cost. 2589 ExtraCost = 3; 2590 break; 2591 default: 2592 break; 2593 } 2594 } 2595 } 2596 2597 static const CostTblEntry SLMCostTbl[] = { 2598 // slm pcmpeq/pcmpgt throughput is 2 2599 { ISD::SETCC, MVT::v2i64, 2 }, 2600 }; 2601 2602 static const CostTblEntry AVX512BWCostTbl[] = { 2603 { ISD::SETCC, MVT::v32i16, 1 }, 2604 { ISD::SETCC, MVT::v64i8, 1 }, 2605 2606 { ISD::SELECT, MVT::v32i16, 1 }, 2607 { ISD::SELECT, MVT::v64i8, 1 }, 2608 }; 2609 2610 static const CostTblEntry AVX512CostTbl[] = { 2611 { ISD::SETCC, MVT::v8i64, 1 }, 2612 { ISD::SETCC, MVT::v16i32, 1 }, 2613 { ISD::SETCC, MVT::v8f64, 1 }, 2614 { ISD::SETCC, MVT::v16f32, 1 }, 2615 2616 { ISD::SELECT, MVT::v8i64, 1 }, 2617 { ISD::SELECT, MVT::v16i32, 1 }, 2618 { ISD::SELECT, MVT::v8f64, 1 }, 2619 { ISD::SELECT, MVT::v16f32, 1 }, 2620 2621 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 2622 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 2623 2624 { ISD::SELECT, MVT::v32i16, 2 }, // FIXME: should be 3 2625 { ISD::SELECT, MVT::v64i8, 2 }, // FIXME: should be 3 2626 }; 2627 2628 static const CostTblEntry AVX2CostTbl[] = { 2629 { ISD::SETCC, MVT::v4i64, 1 }, 2630 { ISD::SETCC, MVT::v8i32, 1 }, 2631 { ISD::SETCC, MVT::v16i16, 1 }, 2632 { ISD::SETCC, MVT::v32i8, 1 }, 2633 2634 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 2635 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 2636 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 2637 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 2638 }; 2639 2640 static const CostTblEntry AVX1CostTbl[] = { 2641 { ISD::SETCC, MVT::v4f64, 1 }, 2642 { ISD::SETCC, MVT::v8f32, 1 }, 2643 // AVX1 does not support 8-wide integer compare. 2644 { ISD::SETCC, MVT::v4i64, 4 }, 2645 { ISD::SETCC, MVT::v8i32, 4 }, 2646 { ISD::SETCC, MVT::v16i16, 4 }, 2647 { ISD::SETCC, MVT::v32i8, 4 }, 2648 2649 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 2650 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 2651 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 2652 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 2653 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 2654 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 2655 }; 2656 2657 static const CostTblEntry SSE42CostTbl[] = { 2658 { ISD::SETCC, MVT::v2f64, 1 }, 2659 { ISD::SETCC, MVT::v4f32, 1 }, 2660 { ISD::SETCC, MVT::v2i64, 1 }, 2661 }; 2662 2663 static const CostTblEntry SSE41CostTbl[] = { 2664 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 2665 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 2666 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 2667 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 2668 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 2669 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 2670 }; 2671 2672 static const CostTblEntry SSE2CostTbl[] = { 2673 { ISD::SETCC, MVT::v2f64, 2 }, 2674 { ISD::SETCC, MVT::f64, 1 }, 2675 { ISD::SETCC, MVT::v2i64, 8 }, 2676 { ISD::SETCC, MVT::v4i32, 1 }, 2677 { ISD::SETCC, MVT::v8i16, 1 }, 2678 { ISD::SETCC, MVT::v16i8, 1 }, 2679 2680 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 2681 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 2682 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 2683 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 2684 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 2685 }; 2686 2687 static const CostTblEntry SSE1CostTbl[] = { 2688 { ISD::SETCC, MVT::v4f32, 2 }, 2689 { ISD::SETCC, MVT::f32, 1 }, 2690 2691 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 2692 }; 2693 2694 if (ST->useSLMArithCosts()) 2695 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2696 return LT.first * (ExtraCost + Entry->Cost); 2697 2698 if (ST->hasBWI()) 2699 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2700 return LT.first * (ExtraCost + Entry->Cost); 2701 2702 if (ST->hasAVX512()) 2703 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2704 return LT.first * (ExtraCost + Entry->Cost); 2705 2706 if (ST->hasAVX2()) 2707 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2708 return LT.first * (ExtraCost + Entry->Cost); 2709 2710 if (ST->hasAVX()) 2711 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2712 return LT.first * (ExtraCost + Entry->Cost); 2713 2714 if (ST->hasSSE42()) 2715 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2716 return LT.first * (ExtraCost + Entry->Cost); 2717 2718 if (ST->hasSSE41()) 2719 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2720 return LT.first * (ExtraCost + Entry->Cost); 2721 2722 if (ST->hasSSE2()) 2723 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2724 return LT.first * (ExtraCost + Entry->Cost); 2725 2726 if (ST->hasSSE1()) 2727 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2728 return LT.first * (ExtraCost + Entry->Cost); 2729 2730 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I); 2731 } 2732 2733 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2734 2735 InstructionCost 2736 X86TTIImpl::getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 2737 TTI::TargetCostKind CostKind) { 2738 2739 // Costs should match the codegen from: 2740 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2741 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2742 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2743 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2744 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2745 2746 // TODO: Overflow intrinsics (*ADDO, *SUBO, *MULO) with vector types are not 2747 // specialized in these tables yet. 2748 static const CostTblEntry AVX512BITALGCostTbl[] = { 2749 { ISD::CTPOP, MVT::v32i16, 1 }, 2750 { ISD::CTPOP, MVT::v64i8, 1 }, 2751 { ISD::CTPOP, MVT::v16i16, 1 }, 2752 { ISD::CTPOP, MVT::v32i8, 1 }, 2753 { ISD::CTPOP, MVT::v8i16, 1 }, 2754 { ISD::CTPOP, MVT::v16i8, 1 }, 2755 }; 2756 static const CostTblEntry AVX512VPOPCNTDQCostTbl[] = { 2757 { ISD::CTPOP, MVT::v8i64, 1 }, 2758 { ISD::CTPOP, MVT::v16i32, 1 }, 2759 { ISD::CTPOP, MVT::v4i64, 1 }, 2760 { ISD::CTPOP, MVT::v8i32, 1 }, 2761 { ISD::CTPOP, MVT::v2i64, 1 }, 2762 { ISD::CTPOP, MVT::v4i32, 1 }, 2763 }; 2764 static const CostTblEntry AVX512CDCostTbl[] = { 2765 { ISD::CTLZ, MVT::v8i64, 1 }, 2766 { ISD::CTLZ, MVT::v16i32, 1 }, 2767 { ISD::CTLZ, MVT::v32i16, 8 }, 2768 { ISD::CTLZ, MVT::v64i8, 20 }, 2769 { ISD::CTLZ, MVT::v4i64, 1 }, 2770 { ISD::CTLZ, MVT::v8i32, 1 }, 2771 { ISD::CTLZ, MVT::v16i16, 4 }, 2772 { ISD::CTLZ, MVT::v32i8, 10 }, 2773 { ISD::CTLZ, MVT::v2i64, 1 }, 2774 { ISD::CTLZ, MVT::v4i32, 1 }, 2775 { ISD::CTLZ, MVT::v8i16, 4 }, 2776 { ISD::CTLZ, MVT::v16i8, 4 }, 2777 }; 2778 static const CostTblEntry AVX512BWCostTbl[] = { 2779 { ISD::ABS, MVT::v32i16, 1 }, 2780 { ISD::ABS, MVT::v64i8, 1 }, 2781 { ISD::BITREVERSE, MVT::v8i64, 3 }, 2782 { ISD::BITREVERSE, MVT::v16i32, 3 }, 2783 { ISD::BITREVERSE, MVT::v32i16, 3 }, 2784 { ISD::BITREVERSE, MVT::v64i8, 2 }, 2785 { ISD::BSWAP, MVT::v8i64, 1 }, 2786 { ISD::BSWAP, MVT::v16i32, 1 }, 2787 { ISD::BSWAP, MVT::v32i16, 1 }, 2788 { ISD::CTLZ, MVT::v8i64, 23 }, 2789 { ISD::CTLZ, MVT::v16i32, 22 }, 2790 { ISD::CTLZ, MVT::v32i16, 18 }, 2791 { ISD::CTLZ, MVT::v64i8, 17 }, 2792 { ISD::CTPOP, MVT::v8i64, 7 }, 2793 { ISD::CTPOP, MVT::v16i32, 11 }, 2794 { ISD::CTPOP, MVT::v32i16, 9 }, 2795 { ISD::CTPOP, MVT::v64i8, 6 }, 2796 { ISD::CTTZ, MVT::v8i64, 10 }, 2797 { ISD::CTTZ, MVT::v16i32, 14 }, 2798 { ISD::CTTZ, MVT::v32i16, 12 }, 2799 { ISD::CTTZ, MVT::v64i8, 9 }, 2800 { ISD::SADDSAT, MVT::v32i16, 1 }, 2801 { ISD::SADDSAT, MVT::v64i8, 1 }, 2802 { ISD::SMAX, MVT::v32i16, 1 }, 2803 { ISD::SMAX, MVT::v64i8, 1 }, 2804 { ISD::SMIN, MVT::v32i16, 1 }, 2805 { ISD::SMIN, MVT::v64i8, 1 }, 2806 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2807 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2808 { ISD::UADDSAT, MVT::v32i16, 1 }, 2809 { ISD::UADDSAT, MVT::v64i8, 1 }, 2810 { ISD::UMAX, MVT::v32i16, 1 }, 2811 { ISD::UMAX, MVT::v64i8, 1 }, 2812 { ISD::UMIN, MVT::v32i16, 1 }, 2813 { ISD::UMIN, MVT::v64i8, 1 }, 2814 { ISD::USUBSAT, MVT::v32i16, 1 }, 2815 { ISD::USUBSAT, MVT::v64i8, 1 }, 2816 }; 2817 static const CostTblEntry AVX512CostTbl[] = { 2818 { ISD::ABS, MVT::v8i64, 1 }, 2819 { ISD::ABS, MVT::v16i32, 1 }, 2820 { ISD::ABS, MVT::v32i16, 2 }, 2821 { ISD::ABS, MVT::v64i8, 2 }, 2822 { ISD::ABS, MVT::v4i64, 1 }, 2823 { ISD::ABS, MVT::v2i64, 1 }, 2824 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2825 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2826 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2827 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2828 { ISD::BSWAP, MVT::v8i64, 4 }, 2829 { ISD::BSWAP, MVT::v16i32, 4 }, 2830 { ISD::BSWAP, MVT::v32i16, 4 }, 2831 { ISD::CTLZ, MVT::v8i64, 29 }, 2832 { ISD::CTLZ, MVT::v16i32, 35 }, 2833 { ISD::CTLZ, MVT::v32i16, 28 }, 2834 { ISD::CTLZ, MVT::v64i8, 18 }, 2835 { ISD::CTPOP, MVT::v8i64, 16 }, 2836 { ISD::CTPOP, MVT::v16i32, 24 }, 2837 { ISD::CTPOP, MVT::v32i16, 18 }, 2838 { ISD::CTPOP, MVT::v64i8, 12 }, 2839 { ISD::CTTZ, MVT::v8i64, 20 }, 2840 { ISD::CTTZ, MVT::v16i32, 28 }, 2841 { ISD::CTTZ, MVT::v32i16, 24 }, 2842 { ISD::CTTZ, MVT::v64i8, 18 }, 2843 { ISD::SMAX, MVT::v8i64, 1 }, 2844 { ISD::SMAX, MVT::v16i32, 1 }, 2845 { ISD::SMAX, MVT::v32i16, 2 }, 2846 { ISD::SMAX, MVT::v64i8, 2 }, 2847 { ISD::SMAX, MVT::v4i64, 1 }, 2848 { ISD::SMAX, MVT::v2i64, 1 }, 2849 { ISD::SMIN, MVT::v8i64, 1 }, 2850 { ISD::SMIN, MVT::v16i32, 1 }, 2851 { ISD::SMIN, MVT::v32i16, 2 }, 2852 { ISD::SMIN, MVT::v64i8, 2 }, 2853 { ISD::SMIN, MVT::v4i64, 1 }, 2854 { ISD::SMIN, MVT::v2i64, 1 }, 2855 { ISD::UMAX, MVT::v8i64, 1 }, 2856 { ISD::UMAX, MVT::v16i32, 1 }, 2857 { ISD::UMAX, MVT::v32i16, 2 }, 2858 { ISD::UMAX, MVT::v64i8, 2 }, 2859 { ISD::UMAX, MVT::v4i64, 1 }, 2860 { ISD::UMAX, MVT::v2i64, 1 }, 2861 { ISD::UMIN, MVT::v8i64, 1 }, 2862 { ISD::UMIN, MVT::v16i32, 1 }, 2863 { ISD::UMIN, MVT::v32i16, 2 }, 2864 { ISD::UMIN, MVT::v64i8, 2 }, 2865 { ISD::UMIN, MVT::v4i64, 1 }, 2866 { ISD::UMIN, MVT::v2i64, 1 }, 2867 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2868 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2869 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2870 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2871 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2872 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2873 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2874 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2875 { ISD::SADDSAT, MVT::v32i16, 2 }, 2876 { ISD::SADDSAT, MVT::v64i8, 2 }, 2877 { ISD::SSUBSAT, MVT::v32i16, 2 }, 2878 { ISD::SSUBSAT, MVT::v64i8, 2 }, 2879 { ISD::UADDSAT, MVT::v32i16, 2 }, 2880 { ISD::UADDSAT, MVT::v64i8, 2 }, 2881 { ISD::USUBSAT, MVT::v32i16, 2 }, 2882 { ISD::USUBSAT, MVT::v64i8, 2 }, 2883 { ISD::FMAXNUM, MVT::f32, 2 }, 2884 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2885 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2886 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2887 { ISD::FMAXNUM, MVT::f64, 2 }, 2888 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2889 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2890 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2891 }; 2892 static const CostTblEntry XOPCostTbl[] = { 2893 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2894 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2895 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2896 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2897 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2898 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2899 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2900 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2901 { ISD::BITREVERSE, MVT::i64, 3 }, 2902 { ISD::BITREVERSE, MVT::i32, 3 }, 2903 { ISD::BITREVERSE, MVT::i16, 3 }, 2904 { ISD::BITREVERSE, MVT::i8, 3 } 2905 }; 2906 static const CostTblEntry AVX2CostTbl[] = { 2907 { ISD::ABS, MVT::v4i64, 2 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2908 { ISD::ABS, MVT::v8i32, 1 }, 2909 { ISD::ABS, MVT::v16i16, 1 }, 2910 { ISD::ABS, MVT::v32i8, 1 }, 2911 { ISD::BITREVERSE, MVT::v2i64, 3 }, 2912 { ISD::BITREVERSE, MVT::v4i64, 3 }, 2913 { ISD::BITREVERSE, MVT::v4i32, 3 }, 2914 { ISD::BITREVERSE, MVT::v8i32, 3 }, 2915 { ISD::BITREVERSE, MVT::v8i16, 3 }, 2916 { ISD::BITREVERSE, MVT::v16i16, 3 }, 2917 { ISD::BITREVERSE, MVT::v16i8, 3 }, 2918 { ISD::BITREVERSE, MVT::v32i8, 3 }, 2919 { ISD::BSWAP, MVT::v4i64, 1 }, 2920 { ISD::BSWAP, MVT::v8i32, 1 }, 2921 { ISD::BSWAP, MVT::v16i16, 1 }, 2922 { ISD::CTLZ, MVT::v2i64, 7 }, 2923 { ISD::CTLZ, MVT::v4i64, 7 }, 2924 { ISD::CTLZ, MVT::v4i32, 5 }, 2925 { ISD::CTLZ, MVT::v8i32, 5 }, 2926 { ISD::CTLZ, MVT::v8i16, 4 }, 2927 { ISD::CTLZ, MVT::v16i16, 4 }, 2928 { ISD::CTLZ, MVT::v16i8, 3 }, 2929 { ISD::CTLZ, MVT::v32i8, 3 }, 2930 { ISD::CTPOP, MVT::v2i64, 3 }, 2931 { ISD::CTPOP, MVT::v4i64, 3 }, 2932 { ISD::CTPOP, MVT::v4i32, 7 }, 2933 { ISD::CTPOP, MVT::v8i32, 7 }, 2934 { ISD::CTPOP, MVT::v8i16, 3 }, 2935 { ISD::CTPOP, MVT::v16i16, 3 }, 2936 { ISD::CTPOP, MVT::v16i8, 2 }, 2937 { ISD::CTPOP, MVT::v32i8, 2 }, 2938 { ISD::CTTZ, MVT::v2i64, 4 }, 2939 { ISD::CTTZ, MVT::v4i64, 4 }, 2940 { ISD::CTTZ, MVT::v4i32, 7 }, 2941 { ISD::CTTZ, MVT::v8i32, 7 }, 2942 { ISD::CTTZ, MVT::v8i16, 4 }, 2943 { ISD::CTTZ, MVT::v16i16, 4 }, 2944 { ISD::CTTZ, MVT::v16i8, 3 }, 2945 { ISD::CTTZ, MVT::v32i8, 3 }, 2946 { ISD::SADDSAT, MVT::v16i16, 1 }, 2947 { ISD::SADDSAT, MVT::v32i8, 1 }, 2948 { ISD::SMAX, MVT::v8i32, 1 }, 2949 { ISD::SMAX, MVT::v16i16, 1 }, 2950 { ISD::SMAX, MVT::v32i8, 1 }, 2951 { ISD::SMIN, MVT::v8i32, 1 }, 2952 { ISD::SMIN, MVT::v16i16, 1 }, 2953 { ISD::SMIN, MVT::v32i8, 1 }, 2954 { ISD::SSUBSAT, MVT::v16i16, 1 }, 2955 { ISD::SSUBSAT, MVT::v32i8, 1 }, 2956 { ISD::UADDSAT, MVT::v16i16, 1 }, 2957 { ISD::UADDSAT, MVT::v32i8, 1 }, 2958 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 2959 { ISD::UMAX, MVT::v8i32, 1 }, 2960 { ISD::UMAX, MVT::v16i16, 1 }, 2961 { ISD::UMAX, MVT::v32i8, 1 }, 2962 { ISD::UMIN, MVT::v8i32, 1 }, 2963 { ISD::UMIN, MVT::v16i16, 1 }, 2964 { ISD::UMIN, MVT::v32i8, 1 }, 2965 { ISD::USUBSAT, MVT::v16i16, 1 }, 2966 { ISD::USUBSAT, MVT::v32i8, 1 }, 2967 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2968 { ISD::FMAXNUM, MVT::v8f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2969 { ISD::FMAXNUM, MVT::v4f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2970 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2971 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2972 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2973 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2974 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2975 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2976 }; 2977 static const CostTblEntry AVX1CostTbl[] = { 2978 { ISD::ABS, MVT::v4i64, 5 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2979 { ISD::ABS, MVT::v8i32, 3 }, 2980 { ISD::ABS, MVT::v16i16, 3 }, 2981 { ISD::ABS, MVT::v32i8, 3 }, 2982 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 2983 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 2984 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 2985 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 2986 { ISD::BSWAP, MVT::v4i64, 4 }, 2987 { ISD::BSWAP, MVT::v8i32, 4 }, 2988 { ISD::BSWAP, MVT::v16i16, 4 }, 2989 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 2990 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 2991 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 2992 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2993 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 2994 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 2995 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 2996 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 2997 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 2998 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 2999 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 3000 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 3001 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3002 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3003 { ISD::SMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3004 { ISD::SMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3005 { ISD::SMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3006 { ISD::SMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3007 { ISD::SMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3008 { ISD::SMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3009 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3010 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3011 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3012 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3013 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 3014 { ISD::UMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3015 { ISD::UMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3016 { ISD::UMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3017 { ISD::UMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3018 { ISD::UMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3019 { ISD::UMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3020 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3021 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3022 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 3023 { ISD::FMAXNUM, MVT::f32, 3 }, // MAXSS + CMPUNORDSS + BLENDVPS 3024 { ISD::FMAXNUM, MVT::v4f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 3025 { ISD::FMAXNUM, MVT::v8f32, 5 }, // MAXPS + CMPUNORDPS + BLENDVPS + ? 3026 { ISD::FMAXNUM, MVT::f64, 3 }, // MAXSD + CMPUNORDSD + BLENDVPD 3027 { ISD::FMAXNUM, MVT::v2f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 3028 { ISD::FMAXNUM, MVT::v4f64, 5 }, // MAXPD + CMPUNORDPD + BLENDVPD + ? 3029 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 3030 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 3031 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 3032 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 3033 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 3034 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 3035 }; 3036 static const CostTblEntry GLMCostTbl[] = { 3037 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 3038 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 3039 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 3040 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 3041 }; 3042 static const CostTblEntry SLMCostTbl[] = { 3043 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 3044 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 3045 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 3046 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 3047 }; 3048 static const CostTblEntry SSE42CostTbl[] = { 3049 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 3050 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 3051 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 3052 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 3053 }; 3054 static const CostTblEntry SSE41CostTbl[] = { 3055 { ISD::ABS, MVT::v2i64, 2 }, // BLENDVPD(X,PSUBQ(0,X),X) 3056 { ISD::SMAX, MVT::v4i32, 1 }, 3057 { ISD::SMAX, MVT::v16i8, 1 }, 3058 { ISD::SMIN, MVT::v4i32, 1 }, 3059 { ISD::SMIN, MVT::v16i8, 1 }, 3060 { ISD::UMAX, MVT::v4i32, 1 }, 3061 { ISD::UMAX, MVT::v8i16, 1 }, 3062 { ISD::UMIN, MVT::v4i32, 1 }, 3063 { ISD::UMIN, MVT::v8i16, 1 }, 3064 }; 3065 static const CostTblEntry SSSE3CostTbl[] = { 3066 { ISD::ABS, MVT::v4i32, 1 }, 3067 { ISD::ABS, MVT::v8i16, 1 }, 3068 { ISD::ABS, MVT::v16i8, 1 }, 3069 { ISD::BITREVERSE, MVT::v2i64, 5 }, 3070 { ISD::BITREVERSE, MVT::v4i32, 5 }, 3071 { ISD::BITREVERSE, MVT::v8i16, 5 }, 3072 { ISD::BITREVERSE, MVT::v16i8, 5 }, 3073 { ISD::BSWAP, MVT::v2i64, 1 }, 3074 { ISD::BSWAP, MVT::v4i32, 1 }, 3075 { ISD::BSWAP, MVT::v8i16, 1 }, 3076 { ISD::CTLZ, MVT::v2i64, 23 }, 3077 { ISD::CTLZ, MVT::v4i32, 18 }, 3078 { ISD::CTLZ, MVT::v8i16, 14 }, 3079 { ISD::CTLZ, MVT::v16i8, 9 }, 3080 { ISD::CTPOP, MVT::v2i64, 7 }, 3081 { ISD::CTPOP, MVT::v4i32, 11 }, 3082 { ISD::CTPOP, MVT::v8i16, 9 }, 3083 { ISD::CTPOP, MVT::v16i8, 6 }, 3084 { ISD::CTTZ, MVT::v2i64, 10 }, 3085 { ISD::CTTZ, MVT::v4i32, 14 }, 3086 { ISD::CTTZ, MVT::v8i16, 12 }, 3087 { ISD::CTTZ, MVT::v16i8, 9 } 3088 }; 3089 static const CostTblEntry SSE2CostTbl[] = { 3090 { ISD::ABS, MVT::v2i64, 4 }, 3091 { ISD::ABS, MVT::v4i32, 3 }, 3092 { ISD::ABS, MVT::v8i16, 2 }, 3093 { ISD::ABS, MVT::v16i8, 2 }, 3094 { ISD::BITREVERSE, MVT::v2i64, 29 }, 3095 { ISD::BITREVERSE, MVT::v4i32, 27 }, 3096 { ISD::BITREVERSE, MVT::v8i16, 27 }, 3097 { ISD::BITREVERSE, MVT::v16i8, 20 }, 3098 { ISD::BSWAP, MVT::v2i64, 7 }, 3099 { ISD::BSWAP, MVT::v4i32, 7 }, 3100 { ISD::BSWAP, MVT::v8i16, 7 }, 3101 { ISD::CTLZ, MVT::v2i64, 25 }, 3102 { ISD::CTLZ, MVT::v4i32, 26 }, 3103 { ISD::CTLZ, MVT::v8i16, 20 }, 3104 { ISD::CTLZ, MVT::v16i8, 17 }, 3105 { ISD::CTPOP, MVT::v2i64, 12 }, 3106 { ISD::CTPOP, MVT::v4i32, 15 }, 3107 { ISD::CTPOP, MVT::v8i16, 13 }, 3108 { ISD::CTPOP, MVT::v16i8, 10 }, 3109 { ISD::CTTZ, MVT::v2i64, 14 }, 3110 { ISD::CTTZ, MVT::v4i32, 18 }, 3111 { ISD::CTTZ, MVT::v8i16, 16 }, 3112 { ISD::CTTZ, MVT::v16i8, 13 }, 3113 { ISD::SADDSAT, MVT::v8i16, 1 }, 3114 { ISD::SADDSAT, MVT::v16i8, 1 }, 3115 { ISD::SMAX, MVT::v8i16, 1 }, 3116 { ISD::SMIN, MVT::v8i16, 1 }, 3117 { ISD::SSUBSAT, MVT::v8i16, 1 }, 3118 { ISD::SSUBSAT, MVT::v16i8, 1 }, 3119 { ISD::UADDSAT, MVT::v8i16, 1 }, 3120 { ISD::UADDSAT, MVT::v16i8, 1 }, 3121 { ISD::UMAX, MVT::v8i16, 2 }, 3122 { ISD::UMAX, MVT::v16i8, 1 }, 3123 { ISD::UMIN, MVT::v8i16, 2 }, 3124 { ISD::UMIN, MVT::v16i8, 1 }, 3125 { ISD::USUBSAT, MVT::v8i16, 1 }, 3126 { ISD::USUBSAT, MVT::v16i8, 1 }, 3127 { ISD::FMAXNUM, MVT::f64, 4 }, 3128 { ISD::FMAXNUM, MVT::v2f64, 4 }, 3129 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 3130 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 3131 }; 3132 static const CostTblEntry SSE1CostTbl[] = { 3133 { ISD::FMAXNUM, MVT::f32, 4 }, 3134 { ISD::FMAXNUM, MVT::v4f32, 4 }, 3135 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 3136 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 3137 }; 3138 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 3139 { ISD::CTTZ, MVT::i64, 1 }, 3140 }; 3141 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 3142 { ISD::CTTZ, MVT::i32, 1 }, 3143 { ISD::CTTZ, MVT::i16, 1 }, 3144 { ISD::CTTZ, MVT::i8, 1 }, 3145 }; 3146 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 3147 { ISD::CTLZ, MVT::i64, 1 }, 3148 }; 3149 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 3150 { ISD::CTLZ, MVT::i32, 1 }, 3151 { ISD::CTLZ, MVT::i16, 1 }, 3152 { ISD::CTLZ, MVT::i8, 1 }, 3153 }; 3154 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 3155 { ISD::CTPOP, MVT::i64, 1 }, 3156 }; 3157 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 3158 { ISD::CTPOP, MVT::i32, 1 }, 3159 { ISD::CTPOP, MVT::i16, 1 }, 3160 { ISD::CTPOP, MVT::i8, 1 }, 3161 }; 3162 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 3163 { ISD::ABS, MVT::i64, 2 }, // SUB+CMOV 3164 { ISD::BITREVERSE, MVT::i64, 14 }, 3165 { ISD::BSWAP, MVT::i64, 1 }, 3166 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 3167 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 3168 { ISD::CTPOP, MVT::i64, 10 }, 3169 { ISD::SADDO, MVT::i64, 1 }, 3170 { ISD::UADDO, MVT::i64, 1 }, 3171 { ISD::UMULO, MVT::i64, 2 }, // mulq + seto 3172 }; 3173 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 3174 { ISD::ABS, MVT::i32, 2 }, // SUB+CMOV 3175 { ISD::ABS, MVT::i16, 2 }, // SUB+CMOV 3176 { ISD::BITREVERSE, MVT::i32, 14 }, 3177 { ISD::BITREVERSE, MVT::i16, 14 }, 3178 { ISD::BITREVERSE, MVT::i8, 11 }, 3179 { ISD::BSWAP, MVT::i32, 1 }, 3180 { ISD::BSWAP, MVT::i16, 1 }, // ROL 3181 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 3182 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 3183 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 3184 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 3185 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 3186 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 3187 { ISD::CTPOP, MVT::i32, 8 }, 3188 { ISD::CTPOP, MVT::i16, 9 }, 3189 { ISD::CTPOP, MVT::i8, 7 }, 3190 { ISD::SADDO, MVT::i32, 1 }, 3191 { ISD::SADDO, MVT::i16, 1 }, 3192 { ISD::SADDO, MVT::i8, 1 }, 3193 { ISD::UADDO, MVT::i32, 1 }, 3194 { ISD::UADDO, MVT::i16, 1 }, 3195 { ISD::UADDO, MVT::i8, 1 }, 3196 { ISD::UMULO, MVT::i32, 2 }, // mul + seto 3197 { ISD::UMULO, MVT::i16, 2 }, 3198 { ISD::UMULO, MVT::i8, 2 }, 3199 }; 3200 3201 Type *RetTy = ICA.getReturnType(); 3202 Type *OpTy = RetTy; 3203 Intrinsic::ID IID = ICA.getID(); 3204 unsigned ISD = ISD::DELETED_NODE; 3205 switch (IID) { 3206 default: 3207 break; 3208 case Intrinsic::abs: 3209 ISD = ISD::ABS; 3210 break; 3211 case Intrinsic::bitreverse: 3212 ISD = ISD::BITREVERSE; 3213 break; 3214 case Intrinsic::bswap: 3215 ISD = ISD::BSWAP; 3216 break; 3217 case Intrinsic::ctlz: 3218 ISD = ISD::CTLZ; 3219 break; 3220 case Intrinsic::ctpop: 3221 ISD = ISD::CTPOP; 3222 break; 3223 case Intrinsic::cttz: 3224 ISD = ISD::CTTZ; 3225 break; 3226 case Intrinsic::maxnum: 3227 case Intrinsic::minnum: 3228 // FMINNUM has same costs so don't duplicate. 3229 ISD = ISD::FMAXNUM; 3230 break; 3231 case Intrinsic::sadd_sat: 3232 ISD = ISD::SADDSAT; 3233 break; 3234 case Intrinsic::smax: 3235 ISD = ISD::SMAX; 3236 break; 3237 case Intrinsic::smin: 3238 ISD = ISD::SMIN; 3239 break; 3240 case Intrinsic::ssub_sat: 3241 ISD = ISD::SSUBSAT; 3242 break; 3243 case Intrinsic::uadd_sat: 3244 ISD = ISD::UADDSAT; 3245 break; 3246 case Intrinsic::umax: 3247 ISD = ISD::UMAX; 3248 break; 3249 case Intrinsic::umin: 3250 ISD = ISD::UMIN; 3251 break; 3252 case Intrinsic::usub_sat: 3253 ISD = ISD::USUBSAT; 3254 break; 3255 case Intrinsic::sqrt: 3256 ISD = ISD::FSQRT; 3257 break; 3258 case Intrinsic::sadd_with_overflow: 3259 case Intrinsic::ssub_with_overflow: 3260 // SSUBO has same costs so don't duplicate. 3261 ISD = ISD::SADDO; 3262 OpTy = RetTy->getContainedType(0); 3263 break; 3264 case Intrinsic::uadd_with_overflow: 3265 case Intrinsic::usub_with_overflow: 3266 // USUBO has same costs so don't duplicate. 3267 ISD = ISD::UADDO; 3268 OpTy = RetTy->getContainedType(0); 3269 break; 3270 case Intrinsic::umul_with_overflow: 3271 case Intrinsic::smul_with_overflow: 3272 // SMULO has same costs so don't duplicate. 3273 ISD = ISD::UMULO; 3274 OpTy = RetTy->getContainedType(0); 3275 break; 3276 } 3277 3278 if (ISD != ISD::DELETED_NODE) { 3279 // Legalize the type. 3280 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 3281 MVT MTy = LT.second; 3282 3283 // Attempt to lookup cost. 3284 if (ISD == ISD::BITREVERSE && ST->hasGFNI() && ST->hasSSSE3() && 3285 MTy.isVector()) { 3286 // With PSHUFB the code is very similar for all types. If we have integer 3287 // byte operations, we just need a GF2P8AFFINEQB for vXi8. For other types 3288 // we also need a PSHUFB. 3289 unsigned Cost = MTy.getVectorElementType() == MVT::i8 ? 1 : 2; 3290 3291 // Without byte operations, we need twice as many GF2P8AFFINEQB and PSHUFB 3292 // instructions. We also need an extract and an insert. 3293 if (!(MTy.is128BitVector() || (ST->hasAVX2() && MTy.is256BitVector()) || 3294 (ST->hasBWI() && MTy.is512BitVector()))) 3295 Cost = Cost * 2 + 2; 3296 3297 return LT.first * Cost; 3298 } 3299 3300 auto adjustTableCost = [](const CostTblEntry &Entry, 3301 InstructionCost LegalizationCost, 3302 FastMathFlags FMF) { 3303 // If there are no NANs to deal with, then these are reduced to a 3304 // single MIN** or MAX** instruction instead of the MIN/CMP/SELECT that we 3305 // assume is used in the non-fast case. 3306 if (Entry.ISD == ISD::FMAXNUM || Entry.ISD == ISD::FMINNUM) { 3307 if (FMF.noNaNs()) 3308 return LegalizationCost * 1; 3309 } 3310 return LegalizationCost * (int)Entry.Cost; 3311 }; 3312 3313 if (ST->useGLMDivSqrtCosts()) 3314 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 3315 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3316 3317 if (ST->useSLMArithCosts()) 3318 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 3319 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3320 3321 if (ST->hasBITALG()) 3322 if (const auto *Entry = CostTableLookup(AVX512BITALGCostTbl, ISD, MTy)) 3323 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3324 3325 if (ST->hasVPOPCNTDQ()) 3326 if (const auto *Entry = CostTableLookup(AVX512VPOPCNTDQCostTbl, ISD, MTy)) 3327 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3328 3329 if (ST->hasCDI()) 3330 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 3331 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3332 3333 if (ST->hasBWI()) 3334 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3335 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3336 3337 if (ST->hasAVX512()) 3338 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3339 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3340 3341 if (ST->hasXOP()) 3342 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3343 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3344 3345 if (ST->hasAVX2()) 3346 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3347 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3348 3349 if (ST->hasAVX()) 3350 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3351 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3352 3353 if (ST->hasSSE42()) 3354 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3355 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3356 3357 if (ST->hasSSE41()) 3358 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3359 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3360 3361 if (ST->hasSSSE3()) 3362 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 3363 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3364 3365 if (ST->hasSSE2()) 3366 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3367 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3368 3369 if (ST->hasSSE1()) 3370 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3371 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3372 3373 if (ST->hasBMI()) { 3374 if (ST->is64Bit()) 3375 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 3376 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3377 3378 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 3379 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3380 } 3381 3382 if (ST->hasLZCNT()) { 3383 if (ST->is64Bit()) 3384 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 3385 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3386 3387 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 3388 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3389 } 3390 3391 if (ST->hasPOPCNT()) { 3392 if (ST->is64Bit()) 3393 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 3394 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3395 3396 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 3397 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3398 } 3399 3400 if (ISD == ISD::BSWAP && ST->hasMOVBE() && ST->hasFastMOVBE()) { 3401 if (const Instruction *II = ICA.getInst()) { 3402 if (II->hasOneUse() && isa<StoreInst>(II->user_back())) 3403 return TTI::TCC_Free; 3404 if (auto *LI = dyn_cast<LoadInst>(II->getOperand(0))) { 3405 if (LI->hasOneUse()) 3406 return TTI::TCC_Free; 3407 } 3408 } 3409 } 3410 3411 if (ST->is64Bit()) 3412 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3413 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3414 3415 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3416 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3417 } 3418 3419 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3420 } 3421 3422 InstructionCost 3423 X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 3424 TTI::TargetCostKind CostKind) { 3425 if (ICA.isTypeBasedOnly()) 3426 return getTypeBasedIntrinsicInstrCost(ICA, CostKind); 3427 3428 static const CostTblEntry AVX512CostTbl[] = { 3429 { ISD::ROTL, MVT::v8i64, 1 }, 3430 { ISD::ROTL, MVT::v4i64, 1 }, 3431 { ISD::ROTL, MVT::v2i64, 1 }, 3432 { ISD::ROTL, MVT::v16i32, 1 }, 3433 { ISD::ROTL, MVT::v8i32, 1 }, 3434 { ISD::ROTL, MVT::v4i32, 1 }, 3435 { ISD::ROTR, MVT::v8i64, 1 }, 3436 { ISD::ROTR, MVT::v4i64, 1 }, 3437 { ISD::ROTR, MVT::v2i64, 1 }, 3438 { ISD::ROTR, MVT::v16i32, 1 }, 3439 { ISD::ROTR, MVT::v8i32, 1 }, 3440 { ISD::ROTR, MVT::v4i32, 1 } 3441 }; 3442 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 3443 static const CostTblEntry XOPCostTbl[] = { 3444 { ISD::ROTL, MVT::v4i64, 4 }, 3445 { ISD::ROTL, MVT::v8i32, 4 }, 3446 { ISD::ROTL, MVT::v16i16, 4 }, 3447 { ISD::ROTL, MVT::v32i8, 4 }, 3448 { ISD::ROTL, MVT::v2i64, 1 }, 3449 { ISD::ROTL, MVT::v4i32, 1 }, 3450 { ISD::ROTL, MVT::v8i16, 1 }, 3451 { ISD::ROTL, MVT::v16i8, 1 }, 3452 { ISD::ROTR, MVT::v4i64, 6 }, 3453 { ISD::ROTR, MVT::v8i32, 6 }, 3454 { ISD::ROTR, MVT::v16i16, 6 }, 3455 { ISD::ROTR, MVT::v32i8, 6 }, 3456 { ISD::ROTR, MVT::v2i64, 2 }, 3457 { ISD::ROTR, MVT::v4i32, 2 }, 3458 { ISD::ROTR, MVT::v8i16, 2 }, 3459 { ISD::ROTR, MVT::v16i8, 2 } 3460 }; 3461 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 3462 { ISD::ROTL, MVT::i64, 1 }, 3463 { ISD::ROTR, MVT::i64, 1 }, 3464 { ISD::FSHL, MVT::i64, 4 } 3465 }; 3466 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 3467 { ISD::ROTL, MVT::i32, 1 }, 3468 { ISD::ROTL, MVT::i16, 1 }, 3469 { ISD::ROTL, MVT::i8, 1 }, 3470 { ISD::ROTR, MVT::i32, 1 }, 3471 { ISD::ROTR, MVT::i16, 1 }, 3472 { ISD::ROTR, MVT::i8, 1 }, 3473 { ISD::FSHL, MVT::i32, 4 }, 3474 { ISD::FSHL, MVT::i16, 4 }, 3475 { ISD::FSHL, MVT::i8, 4 } 3476 }; 3477 3478 Intrinsic::ID IID = ICA.getID(); 3479 Type *RetTy = ICA.getReturnType(); 3480 const SmallVectorImpl<const Value *> &Args = ICA.getArgs(); 3481 unsigned ISD = ISD::DELETED_NODE; 3482 switch (IID) { 3483 default: 3484 break; 3485 case Intrinsic::fshl: 3486 ISD = ISD::FSHL; 3487 if (Args[0] == Args[1]) 3488 ISD = ISD::ROTL; 3489 break; 3490 case Intrinsic::fshr: 3491 // FSHR has same costs so don't duplicate. 3492 ISD = ISD::FSHL; 3493 if (Args[0] == Args[1]) 3494 ISD = ISD::ROTR; 3495 break; 3496 } 3497 3498 if (ISD != ISD::DELETED_NODE) { 3499 // Legalize the type. 3500 std::pair<InstructionCost, MVT> LT = 3501 TLI->getTypeLegalizationCost(DL, RetTy); 3502 MVT MTy = LT.second; 3503 3504 // Attempt to lookup cost. 3505 if (ST->hasAVX512()) 3506 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3507 return LT.first * Entry->Cost; 3508 3509 if (ST->hasXOP()) 3510 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3511 return LT.first * Entry->Cost; 3512 3513 if (ST->is64Bit()) 3514 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3515 return LT.first * Entry->Cost; 3516 3517 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3518 return LT.first * Entry->Cost; 3519 } 3520 3521 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3522 } 3523 3524 InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, 3525 unsigned Index) { 3526 static const CostTblEntry SLMCostTbl[] = { 3527 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 3528 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 3529 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 3530 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 3531 }; 3532 3533 assert(Val->isVectorTy() && "This must be a vector type"); 3534 Type *ScalarType = Val->getScalarType(); 3535 int RegisterFileMoveCost = 0; 3536 3537 // Non-immediate extraction/insertion can be handled as a sequence of 3538 // aliased loads+stores via the stack. 3539 if (Index == -1U && (Opcode == Instruction::ExtractElement || 3540 Opcode == Instruction::InsertElement)) { 3541 // TODO: On some SSE41+ targets, we expand to cmp+splat+select patterns: 3542 // inselt N0, N1, N2 --> select (SplatN2 == {0,1,2...}) ? SplatN1 : N0. 3543 3544 // TODO: Move this to BasicTTIImpl.h? We'd need better gep + index handling. 3545 assert(isa<FixedVectorType>(Val) && "Fixed vector type expected"); 3546 Align VecAlign = DL.getPrefTypeAlign(Val); 3547 Align SclAlign = DL.getPrefTypeAlign(ScalarType); 3548 3549 // Extract - store vector to stack, load scalar. 3550 if (Opcode == Instruction::ExtractElement) { 3551 return getMemoryOpCost(Instruction::Store, Val, VecAlign, 0, 3552 TTI::TargetCostKind::TCK_RecipThroughput) + 3553 getMemoryOpCost(Instruction::Load, ScalarType, SclAlign, 0, 3554 TTI::TargetCostKind::TCK_RecipThroughput); 3555 } 3556 // Insert - store vector to stack, store scalar, load vector. 3557 if (Opcode == Instruction::InsertElement) { 3558 return getMemoryOpCost(Instruction::Store, Val, VecAlign, 0, 3559 TTI::TargetCostKind::TCK_RecipThroughput) + 3560 getMemoryOpCost(Instruction::Store, ScalarType, SclAlign, 0, 3561 TTI::TargetCostKind::TCK_RecipThroughput) + 3562 getMemoryOpCost(Instruction::Load, Val, VecAlign, 0, 3563 TTI::TargetCostKind::TCK_RecipThroughput); 3564 } 3565 } 3566 3567 if (Index != -1U && (Opcode == Instruction::ExtractElement || 3568 Opcode == Instruction::InsertElement)) { 3569 // Legalize the type. 3570 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 3571 3572 // This type is legalized to a scalar type. 3573 if (!LT.second.isVector()) 3574 return 0; 3575 3576 // The type may be split. Normalize the index to the new type. 3577 unsigned NumElts = LT.second.getVectorNumElements(); 3578 unsigned SubNumElts = NumElts; 3579 Index = Index % NumElts; 3580 3581 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 3582 // For inserts, we also need to insert the subvector back. 3583 if (LT.second.getSizeInBits() > 128) { 3584 assert((LT.second.getSizeInBits() % 128) == 0 && "Illegal vector"); 3585 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 3586 SubNumElts = NumElts / NumSubVecs; 3587 if (SubNumElts <= Index) { 3588 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 3589 Index %= SubNumElts; 3590 } 3591 } 3592 3593 if (Index == 0) { 3594 // Floating point scalars are already located in index #0. 3595 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 3596 // true for all. 3597 if (ScalarType->isFloatingPointTy()) 3598 return RegisterFileMoveCost; 3599 3600 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 3601 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 3602 return 1 + RegisterFileMoveCost; 3603 } 3604 3605 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3606 assert(ISD && "Unexpected vector opcode"); 3607 MVT MScalarTy = LT.second.getScalarType(); 3608 if (ST->useSLMArithCosts()) 3609 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 3610 return Entry->Cost + RegisterFileMoveCost; 3611 3612 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 3613 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3614 (MScalarTy.isInteger() && ST->hasSSE41())) 3615 return 1 + RegisterFileMoveCost; 3616 3617 // Assume insertps is relatively cheap on all targets. 3618 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 3619 Opcode == Instruction::InsertElement) 3620 return 1 + RegisterFileMoveCost; 3621 3622 // For extractions we just need to shuffle the element to index 0, which 3623 // should be very cheap (assume cost = 1). For insertions we need to shuffle 3624 // the elements to its destination. In both cases we must handle the 3625 // subvector move(s). 3626 // If the vector type is already less than 128-bits then don't reduce it. 3627 // TODO: Under what circumstances should we shuffle using the full width? 3628 InstructionCost ShuffleCost = 1; 3629 if (Opcode == Instruction::InsertElement) { 3630 auto *SubTy = cast<VectorType>(Val); 3631 EVT VT = TLI->getValueType(DL, Val); 3632 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 3633 SubTy = FixedVectorType::get(ScalarType, SubNumElts); 3634 ShuffleCost = 3635 getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, None, 0, SubTy); 3636 } 3637 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 3638 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 3639 } 3640 3641 // Add to the base cost if we know that the extracted element of a vector is 3642 // destined to be moved to and used in the integer register file. 3643 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 3644 RegisterFileMoveCost += 1; 3645 3646 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 3647 } 3648 3649 InstructionCost X86TTIImpl::getScalarizationOverhead(VectorType *Ty, 3650 const APInt &DemandedElts, 3651 bool Insert, 3652 bool Extract) { 3653 InstructionCost Cost = 0; 3654 3655 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much 3656 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT. 3657 if (Insert) { 3658 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3659 MVT MScalarTy = LT.second.getScalarType(); 3660 3661 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3662 (MScalarTy.isInteger() && ST->hasSSE41()) || 3663 (MScalarTy == MVT::f32 && ST->hasSSE41())) { 3664 // For types we can insert directly, insertion into 128-bit sub vectors is 3665 // cheap, followed by a cheap chain of concatenations. 3666 if (LT.second.getSizeInBits() <= 128) { 3667 Cost += 3668 BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, false); 3669 } else { 3670 // In each 128-lane, if at least one index is demanded but not all 3671 // indices are demanded and this 128-lane is not the first 128-lane of 3672 // the legalized-vector, then this 128-lane needs a extracti128; If in 3673 // each 128-lane, there is at least one demanded index, this 128-lane 3674 // needs a inserti128. 3675 3676 // The following cases will help you build a better understanding: 3677 // Assume we insert several elements into a v8i32 vector in avx2, 3678 // Case#1: inserting into 1th index needs vpinsrd + inserti128. 3679 // Case#2: inserting into 5th index needs extracti128 + vpinsrd + 3680 // inserti128. 3681 // Case#3: inserting into 4,5,6,7 index needs 4*vpinsrd + inserti128. 3682 const int CostValue = *LT.first.getValue(); 3683 assert(CostValue >= 0 && "Negative cost!"); 3684 unsigned Num128Lanes = LT.second.getSizeInBits() / 128 * CostValue; 3685 unsigned NumElts = LT.second.getVectorNumElements() * CostValue; 3686 APInt WidenedDemandedElts = DemandedElts.zextOrSelf(NumElts); 3687 unsigned Scale = NumElts / Num128Lanes; 3688 // We iterate each 128-lane, and check if we need a 3689 // extracti128/inserti128 for this 128-lane. 3690 for (unsigned I = 0; I < NumElts; I += Scale) { 3691 APInt Mask = WidenedDemandedElts.getBitsSet(NumElts, I, I + Scale); 3692 APInt MaskedDE = Mask & WidenedDemandedElts; 3693 unsigned Population = MaskedDE.countPopulation(); 3694 Cost += (Population > 0 && Population != Scale && 3695 I % LT.second.getVectorNumElements() != 0); 3696 Cost += Population > 0; 3697 } 3698 Cost += DemandedElts.countPopulation(); 3699 3700 // For vXf32 cases, insertion into the 0'th index in each v4f32 3701 // 128-bit vector is free. 3702 // NOTE: This assumes legalization widens vXf32 vectors. 3703 if (MScalarTy == MVT::f32) 3704 for (unsigned i = 0, e = cast<FixedVectorType>(Ty)->getNumElements(); 3705 i < e; i += 4) 3706 if (DemandedElts[i]) 3707 Cost--; 3708 } 3709 } else if (LT.second.isVector()) { 3710 // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded 3711 // integer element as a SCALAR_TO_VECTOR, then we build the vector as a 3712 // series of UNPCK followed by CONCAT_VECTORS - all of these can be 3713 // considered cheap. 3714 if (Ty->isIntOrIntVectorTy()) 3715 Cost += DemandedElts.countPopulation(); 3716 3717 // Get the smaller of the legalized or original pow2-extended number of 3718 // vector elements, which represents the number of unpacks we'll end up 3719 // performing. 3720 unsigned NumElts = LT.second.getVectorNumElements(); 3721 unsigned Pow2Elts = 3722 PowerOf2Ceil(cast<FixedVectorType>(Ty)->getNumElements()); 3723 Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first; 3724 } 3725 } 3726 3727 // TODO: Use default extraction for now, but we should investigate extending this 3728 // to handle repeated subvector extraction. 3729 if (Extract) 3730 Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, false, Extract); 3731 3732 return Cost; 3733 } 3734 3735 InstructionCost 3736 X86TTIImpl::getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, 3737 int VF, const APInt &DemandedDstElts, 3738 TTI::TargetCostKind CostKind) { 3739 const unsigned EltTyBits = DL.getTypeSizeInBits(EltTy); 3740 // We don't differentiate element types here, only element bit width. 3741 EltTy = IntegerType::getIntNTy(EltTy->getContext(), EltTyBits); 3742 3743 auto bailout = [&]() { 3744 return BaseT::getReplicationShuffleCost(EltTy, ReplicationFactor, VF, 3745 DemandedDstElts, CostKind); 3746 }; 3747 3748 // For now, only deal with AVX512 cases. 3749 if (!ST->hasAVX512()) 3750 return bailout(); 3751 3752 // Do we have a native shuffle for this element type, or should we promote? 3753 unsigned PromEltTyBits = EltTyBits; 3754 switch (EltTyBits) { 3755 case 32: 3756 case 64: 3757 break; // AVX512F. 3758 case 16: 3759 if (!ST->hasBWI()) 3760 PromEltTyBits = 32; // promote to i32, AVX512F. 3761 break; // AVX512BW 3762 case 8: 3763 if (!ST->hasVBMI()) 3764 PromEltTyBits = 32; // promote to i32, AVX512F. 3765 break; // AVX512VBMI 3766 case 1: 3767 // There is no support for shuffling i1 elements. We *must* promote. 3768 if (ST->hasBWI()) { 3769 if (ST->hasVBMI()) 3770 PromEltTyBits = 8; // promote to i8, AVX512VBMI. 3771 else 3772 PromEltTyBits = 16; // promote to i16, AVX512BW. 3773 break; 3774 } 3775 return bailout(); 3776 default: 3777 return bailout(); 3778 } 3779 auto *PromEltTy = IntegerType::getIntNTy(EltTy->getContext(), PromEltTyBits); 3780 3781 auto *SrcVecTy = FixedVectorType::get(EltTy, VF); 3782 auto *PromSrcVecTy = FixedVectorType::get(PromEltTy, VF); 3783 3784 int NumDstElements = VF * ReplicationFactor; 3785 auto *PromDstVecTy = FixedVectorType::get(PromEltTy, NumDstElements); 3786 auto *DstVecTy = FixedVectorType::get(EltTy, NumDstElements); 3787 3788 // Legalize the types. 3789 MVT LegalSrcVecTy = TLI->getTypeLegalizationCost(DL, SrcVecTy).second; 3790 MVT LegalPromSrcVecTy = TLI->getTypeLegalizationCost(DL, PromSrcVecTy).second; 3791 MVT LegalPromDstVecTy = TLI->getTypeLegalizationCost(DL, PromDstVecTy).second; 3792 MVT LegalDstVecTy = TLI->getTypeLegalizationCost(DL, DstVecTy).second; 3793 // They should have legalized into vector types. 3794 if (!LegalSrcVecTy.isVector() || !LegalPromSrcVecTy.isVector() || 3795 !LegalPromDstVecTy.isVector() || !LegalDstVecTy.isVector()) 3796 return bailout(); 3797 3798 if (PromEltTyBits != EltTyBits) { 3799 // If we have to perform the shuffle with wider elt type than our data type, 3800 // then we will first need to anyext (we don't care about the new bits) 3801 // the source elements, and then truncate Dst elements. 3802 InstructionCost PromotionCost; 3803 PromotionCost += getCastInstrCost( 3804 Instruction::SExt, /*Dst=*/PromSrcVecTy, /*Src=*/SrcVecTy, 3805 TargetTransformInfo::CastContextHint::None, CostKind); 3806 PromotionCost += 3807 getCastInstrCost(Instruction::Trunc, /*Dst=*/DstVecTy, 3808 /*Src=*/PromDstVecTy, 3809 TargetTransformInfo::CastContextHint::None, CostKind); 3810 return PromotionCost + getReplicationShuffleCost(PromEltTy, 3811 ReplicationFactor, VF, 3812 DemandedDstElts, CostKind); 3813 } 3814 3815 assert(LegalSrcVecTy.getScalarSizeInBits() == EltTyBits && 3816 LegalSrcVecTy.getScalarType() == LegalDstVecTy.getScalarType() && 3817 "We expect that the legalization doesn't affect the element width, " 3818 "doesn't coalesce/split elements."); 3819 3820 unsigned NumEltsPerDstVec = LegalDstVecTy.getVectorNumElements(); 3821 unsigned NumDstVectors = 3822 divideCeil(DstVecTy->getNumElements(), NumEltsPerDstVec); 3823 3824 auto *SingleDstVecTy = FixedVectorType::get(EltTy, NumEltsPerDstVec); 3825 3826 // Not all the produced Dst elements may be demanded. In our case, 3827 // given that a single Dst vector is formed by a single shuffle, 3828 // if all elements that will form a single Dst vector aren't demanded, 3829 // then we won't need to do that shuffle, so adjust the cost accordingly. 3830 APInt DemandedDstVectors = APIntOps::ScaleBitMask( 3831 DemandedDstElts.zextOrSelf(NumDstVectors * NumEltsPerDstVec), 3832 NumDstVectors); 3833 unsigned NumDstVectorsDemanded = DemandedDstVectors.countPopulation(); 3834 3835 InstructionCost SingleShuffleCost = 3836 getShuffleCost(TTI::SK_PermuteSingleSrc, SingleDstVecTy, 3837 /*Mask=*/None, /*Index=*/0, /*SubTp=*/nullptr); 3838 return NumDstVectorsDemanded * SingleShuffleCost; 3839 } 3840 3841 InstructionCost X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 3842 MaybeAlign Alignment, 3843 unsigned AddressSpace, 3844 TTI::TargetCostKind CostKind, 3845 const Instruction *I) { 3846 // TODO: Handle other cost kinds. 3847 if (CostKind != TTI::TCK_RecipThroughput) { 3848 if (auto *SI = dyn_cast_or_null<StoreInst>(I)) { 3849 // Store instruction with index and scale costs 2 Uops. 3850 // Check the preceding GEP to identify non-const indices. 3851 if (auto *GEP = dyn_cast<GetElementPtrInst>(SI->getPointerOperand())) { 3852 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3853 return TTI::TCC_Basic * 2; 3854 } 3855 } 3856 return TTI::TCC_Basic; 3857 } 3858 3859 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 3860 "Invalid Opcode"); 3861 // Type legalization can't handle structs 3862 if (TLI->getValueType(DL, Src, true) == MVT::Other) 3863 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3864 CostKind); 3865 3866 // Legalize the type. 3867 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 3868 3869 auto *VTy = dyn_cast<FixedVectorType>(Src); 3870 3871 // Handle the simple case of non-vectors. 3872 // NOTE: this assumes that legalization never creates vector from scalars! 3873 if (!VTy || !LT.second.isVector()) 3874 // Each load/store unit costs 1. 3875 return LT.first * 1; 3876 3877 bool IsLoad = Opcode == Instruction::Load; 3878 3879 Type *EltTy = VTy->getElementType(); 3880 3881 const int EltTyBits = DL.getTypeSizeInBits(EltTy); 3882 3883 InstructionCost Cost = 0; 3884 3885 // Source of truth: how many elements were there in the original IR vector? 3886 const unsigned SrcNumElt = VTy->getNumElements(); 3887 3888 // How far have we gotten? 3889 int NumEltRemaining = SrcNumElt; 3890 // Note that we intentionally capture by-reference, NumEltRemaining changes. 3891 auto NumEltDone = [&]() { return SrcNumElt - NumEltRemaining; }; 3892 3893 const int MaxLegalOpSizeBytes = divideCeil(LT.second.getSizeInBits(), 8); 3894 3895 // Note that even if we can store 64 bits of an XMM, we still operate on XMM. 3896 const unsigned XMMBits = 128; 3897 if (XMMBits % EltTyBits != 0) 3898 // Vector size must be a multiple of the element size. I.e. no padding. 3899 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3900 CostKind); 3901 const int NumEltPerXMM = XMMBits / EltTyBits; 3902 3903 auto *XMMVecTy = FixedVectorType::get(EltTy, NumEltPerXMM); 3904 3905 for (int CurrOpSizeBytes = MaxLegalOpSizeBytes, SubVecEltsLeft = 0; 3906 NumEltRemaining > 0; CurrOpSizeBytes /= 2) { 3907 // How many elements would a single op deal with at once? 3908 if ((8 * CurrOpSizeBytes) % EltTyBits != 0) 3909 // Vector size must be a multiple of the element size. I.e. no padding. 3910 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3911 CostKind); 3912 int CurrNumEltPerOp = (8 * CurrOpSizeBytes) / EltTyBits; 3913 3914 assert(CurrOpSizeBytes > 0 && CurrNumEltPerOp > 0 && "How'd we get here?"); 3915 assert((((NumEltRemaining * EltTyBits) < (2 * 8 * CurrOpSizeBytes)) || 3916 (CurrOpSizeBytes == MaxLegalOpSizeBytes)) && 3917 "Unless we haven't halved the op size yet, " 3918 "we have less than two op's sized units of work left."); 3919 3920 auto *CurrVecTy = CurrNumEltPerOp > NumEltPerXMM 3921 ? FixedVectorType::get(EltTy, CurrNumEltPerOp) 3922 : XMMVecTy; 3923 3924 assert(CurrVecTy->getNumElements() % CurrNumEltPerOp == 0 && 3925 "After halving sizes, the vector elt count is no longer a multiple " 3926 "of number of elements per operation?"); 3927 auto *CoalescedVecTy = 3928 CurrNumEltPerOp == 1 3929 ? CurrVecTy 3930 : FixedVectorType::get( 3931 IntegerType::get(Src->getContext(), 3932 EltTyBits * CurrNumEltPerOp), 3933 CurrVecTy->getNumElements() / CurrNumEltPerOp); 3934 assert(DL.getTypeSizeInBits(CoalescedVecTy) == 3935 DL.getTypeSizeInBits(CurrVecTy) && 3936 "coalesciing elements doesn't change vector width."); 3937 3938 while (NumEltRemaining > 0) { 3939 assert(SubVecEltsLeft >= 0 && "Subreg element count overconsumtion?"); 3940 3941 // Can we use this vector size, as per the remaining element count? 3942 // Iff the vector is naturally aligned, we can do a wide load regardless. 3943 if (NumEltRemaining < CurrNumEltPerOp && 3944 (!IsLoad || Alignment.valueOrOne() < CurrOpSizeBytes) && 3945 CurrOpSizeBytes != 1) 3946 break; // Try smalled vector size. 3947 3948 bool Is0thSubVec = (NumEltDone() % LT.second.getVectorNumElements()) == 0; 3949 3950 // If we have fully processed the previous reg, we need to replenish it. 3951 if (SubVecEltsLeft == 0) { 3952 SubVecEltsLeft += CurrVecTy->getNumElements(); 3953 // And that's free only for the 0'th subvector of a legalized vector. 3954 if (!Is0thSubVec) 3955 Cost += getShuffleCost(IsLoad ? TTI::ShuffleKind::SK_InsertSubvector 3956 : TTI::ShuffleKind::SK_ExtractSubvector, 3957 VTy, None, NumEltDone(), CurrVecTy); 3958 } 3959 3960 // While we can directly load/store ZMM, YMM, and 64-bit halves of XMM, 3961 // for smaller widths (32/16/8) we have to insert/extract them separately. 3962 // Again, it's free for the 0'th subreg (if op is 32/64 bit wide, 3963 // but let's pretend that it is also true for 16/8 bit wide ops...) 3964 if (CurrOpSizeBytes <= 32 / 8 && !Is0thSubVec) { 3965 int NumEltDoneInCurrXMM = NumEltDone() % NumEltPerXMM; 3966 assert(NumEltDoneInCurrXMM % CurrNumEltPerOp == 0 && ""); 3967 int CoalescedVecEltIdx = NumEltDoneInCurrXMM / CurrNumEltPerOp; 3968 APInt DemandedElts = 3969 APInt::getBitsSet(CoalescedVecTy->getNumElements(), 3970 CoalescedVecEltIdx, CoalescedVecEltIdx + 1); 3971 assert(DemandedElts.countPopulation() == 1 && "Inserting single value"); 3972 Cost += getScalarizationOverhead(CoalescedVecTy, DemandedElts, IsLoad, 3973 !IsLoad); 3974 } 3975 3976 // This isn't exactly right. We're using slow unaligned 32-byte accesses 3977 // as a proxy for a double-pumped AVX memory interface such as on 3978 // Sandybridge. 3979 if (CurrOpSizeBytes == 32 && ST->isUnalignedMem32Slow()) 3980 Cost += 2; 3981 else 3982 Cost += 1; 3983 3984 SubVecEltsLeft -= CurrNumEltPerOp; 3985 NumEltRemaining -= CurrNumEltPerOp; 3986 Alignment = commonAlignment(Alignment.valueOrOne(), CurrOpSizeBytes); 3987 } 3988 } 3989 3990 assert(NumEltRemaining <= 0 && "Should have processed all the elements."); 3991 3992 return Cost; 3993 } 3994 3995 InstructionCost 3996 X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, Align Alignment, 3997 unsigned AddressSpace, 3998 TTI::TargetCostKind CostKind) { 3999 bool IsLoad = (Instruction::Load == Opcode); 4000 bool IsStore = (Instruction::Store == Opcode); 4001 4002 auto *SrcVTy = dyn_cast<FixedVectorType>(SrcTy); 4003 if (!SrcVTy) 4004 // To calculate scalar take the regular cost, without mask 4005 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace, CostKind); 4006 4007 unsigned NumElem = SrcVTy->getNumElements(); 4008 auto *MaskTy = 4009 FixedVectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 4010 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, Alignment)) || 4011 (IsStore && !isLegalMaskedStore(SrcVTy, Alignment))) { 4012 // Scalarization 4013 APInt DemandedElts = APInt::getAllOnes(NumElem); 4014 InstructionCost MaskSplitCost = 4015 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 4016 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 4017 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr, 4018 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4019 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 4020 InstructionCost MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 4021 InstructionCost ValueSplitCost = 4022 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore); 4023 InstructionCost MemopCost = 4024 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4025 Alignment, AddressSpace, CostKind); 4026 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 4027 } 4028 4029 // Legalize the type. 4030 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 4031 auto VT = TLI->getValueType(DL, SrcVTy); 4032 InstructionCost Cost = 0; 4033 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 4034 LT.second.getVectorNumElements() == NumElem) 4035 // Promotion requires extend/truncate for data and a shuffle for mask. 4036 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, None, 0, nullptr) + 4037 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, None, 0, nullptr); 4038 4039 else if (LT.first * LT.second.getVectorNumElements() > NumElem) { 4040 auto *NewMaskTy = FixedVectorType::get(MaskTy->getElementType(), 4041 LT.second.getVectorNumElements()); 4042 // Expanding requires fill mask with zeroes 4043 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, None, 0, MaskTy); 4044 } 4045 4046 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 4047 if (!ST->hasAVX512()) 4048 return Cost + LT.first * (IsLoad ? 2 : 8); 4049 4050 // AVX-512 masked load/store is cheapper 4051 return Cost + LT.first; 4052 } 4053 4054 InstructionCost X86TTIImpl::getAddressComputationCost(Type *Ty, 4055 ScalarEvolution *SE, 4056 const SCEV *Ptr) { 4057 // Address computations in vectorized code with non-consecutive addresses will 4058 // likely result in more instructions compared to scalar code where the 4059 // computation can more often be merged into the index mode. The resulting 4060 // extra micro-ops can significantly decrease throughput. 4061 const unsigned NumVectorInstToHideOverhead = 10; 4062 4063 // Cost modeling of Strided Access Computation is hidden by the indexing 4064 // modes of X86 regardless of the stride value. We dont believe that there 4065 // is a difference between constant strided access in gerenal and constant 4066 // strided value which is less than or equal to 64. 4067 // Even in the case of (loop invariant) stride whose value is not known at 4068 // compile time, the address computation will not incur more than one extra 4069 // ADD instruction. 4070 if (Ty->isVectorTy() && SE) { 4071 if (!BaseT::isStridedAccess(Ptr)) 4072 return NumVectorInstToHideOverhead; 4073 if (!BaseT::getConstantStrideStep(SE, Ptr)) 4074 return 1; 4075 } 4076 4077 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 4078 } 4079 4080 InstructionCost 4081 X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 4082 Optional<FastMathFlags> FMF, 4083 TTI::TargetCostKind CostKind) { 4084 if (TTI::requiresOrderedReduction(FMF)) 4085 return BaseT::getArithmeticReductionCost(Opcode, ValTy, FMF, CostKind); 4086 4087 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 4088 // and make it as the cost. 4089 4090 static const CostTblEntry SLMCostTblNoPairWise[] = { 4091 { ISD::FADD, MVT::v2f64, 3 }, 4092 { ISD::ADD, MVT::v2i64, 5 }, 4093 }; 4094 4095 static const CostTblEntry SSE2CostTblNoPairWise[] = { 4096 { ISD::FADD, MVT::v2f64, 2 }, 4097 { ISD::FADD, MVT::v2f32, 2 }, 4098 { ISD::FADD, MVT::v4f32, 4 }, 4099 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 4100 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 4101 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 4102 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 4103 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 4104 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 4105 { ISD::ADD, MVT::v2i8, 2 }, 4106 { ISD::ADD, MVT::v4i8, 2 }, 4107 { ISD::ADD, MVT::v8i8, 2 }, 4108 { ISD::ADD, MVT::v16i8, 3 }, 4109 }; 4110 4111 static const CostTblEntry AVX1CostTblNoPairWise[] = { 4112 { ISD::FADD, MVT::v4f64, 3 }, 4113 { ISD::FADD, MVT::v4f32, 3 }, 4114 { ISD::FADD, MVT::v8f32, 4 }, 4115 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 4116 { ISD::ADD, MVT::v4i64, 3 }, 4117 { ISD::ADD, MVT::v8i32, 5 }, 4118 { ISD::ADD, MVT::v16i16, 5 }, 4119 { ISD::ADD, MVT::v32i8, 4 }, 4120 }; 4121 4122 int ISD = TLI->InstructionOpcodeToISD(Opcode); 4123 assert(ISD && "Invalid opcode"); 4124 4125 // Before legalizing the type, give a chance to look up illegal narrow types 4126 // in the table. 4127 // FIXME: Is there a better way to do this? 4128 EVT VT = TLI->getValueType(DL, ValTy); 4129 if (VT.isSimple()) { 4130 MVT MTy = VT.getSimpleVT(); 4131 if (ST->useSLMArithCosts()) 4132 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 4133 return Entry->Cost; 4134 4135 if (ST->hasAVX()) 4136 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4137 return Entry->Cost; 4138 4139 if (ST->hasSSE2()) 4140 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4141 return Entry->Cost; 4142 } 4143 4144 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 4145 4146 MVT MTy = LT.second; 4147 4148 auto *ValVTy = cast<FixedVectorType>(ValTy); 4149 4150 // Special case: vXi8 mul reductions are performed as vXi16. 4151 if (ISD == ISD::MUL && MTy.getScalarType() == MVT::i8) { 4152 auto *WideSclTy = IntegerType::get(ValVTy->getContext(), 16); 4153 auto *WideVecTy = FixedVectorType::get(WideSclTy, ValVTy->getNumElements()); 4154 return getCastInstrCost(Instruction::ZExt, WideVecTy, ValTy, 4155 TargetTransformInfo::CastContextHint::None, 4156 CostKind) + 4157 getArithmeticReductionCost(Opcode, WideVecTy, FMF, CostKind); 4158 } 4159 4160 InstructionCost ArithmeticCost = 0; 4161 if (LT.first != 1 && MTy.isVector() && 4162 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4163 // Type needs to be split. We need LT.first - 1 arithmetic ops. 4164 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 4165 MTy.getVectorNumElements()); 4166 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 4167 ArithmeticCost *= LT.first - 1; 4168 } 4169 4170 if (ST->useSLMArithCosts()) 4171 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 4172 return ArithmeticCost + Entry->Cost; 4173 4174 if (ST->hasAVX()) 4175 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4176 return ArithmeticCost + Entry->Cost; 4177 4178 if (ST->hasSSE2()) 4179 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4180 return ArithmeticCost + Entry->Cost; 4181 4182 // FIXME: These assume a naive kshift+binop lowering, which is probably 4183 // conservative in most cases. 4184 static const CostTblEntry AVX512BoolReduction[] = { 4185 { ISD::AND, MVT::v2i1, 3 }, 4186 { ISD::AND, MVT::v4i1, 5 }, 4187 { ISD::AND, MVT::v8i1, 7 }, 4188 { ISD::AND, MVT::v16i1, 9 }, 4189 { ISD::AND, MVT::v32i1, 11 }, 4190 { ISD::AND, MVT::v64i1, 13 }, 4191 { ISD::OR, MVT::v2i1, 3 }, 4192 { ISD::OR, MVT::v4i1, 5 }, 4193 { ISD::OR, MVT::v8i1, 7 }, 4194 { ISD::OR, MVT::v16i1, 9 }, 4195 { ISD::OR, MVT::v32i1, 11 }, 4196 { ISD::OR, MVT::v64i1, 13 }, 4197 }; 4198 4199 static const CostTblEntry AVX2BoolReduction[] = { 4200 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 4201 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 4202 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 4203 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 4204 }; 4205 4206 static const CostTblEntry AVX1BoolReduction[] = { 4207 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 4208 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 4209 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 4210 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 4211 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 4212 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 4213 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 4214 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 4215 }; 4216 4217 static const CostTblEntry SSE2BoolReduction[] = { 4218 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 4219 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 4220 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 4221 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 4222 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 4223 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 4224 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 4225 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 4226 }; 4227 4228 // Handle bool allof/anyof patterns. 4229 if (ValVTy->getElementType()->isIntegerTy(1)) { 4230 InstructionCost ArithmeticCost = 0; 4231 if (LT.first != 1 && MTy.isVector() && 4232 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4233 // Type needs to be split. We need LT.first - 1 arithmetic ops. 4234 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 4235 MTy.getVectorNumElements()); 4236 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 4237 ArithmeticCost *= LT.first - 1; 4238 } 4239 4240 if (ST->hasAVX512()) 4241 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 4242 return ArithmeticCost + Entry->Cost; 4243 if (ST->hasAVX2()) 4244 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 4245 return ArithmeticCost + Entry->Cost; 4246 if (ST->hasAVX()) 4247 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 4248 return ArithmeticCost + Entry->Cost; 4249 if (ST->hasSSE2()) 4250 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 4251 return ArithmeticCost + Entry->Cost; 4252 4253 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, FMF, CostKind); 4254 } 4255 4256 unsigned NumVecElts = ValVTy->getNumElements(); 4257 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 4258 4259 // Special case power of 2 reductions where the scalar type isn't changed 4260 // by type legalization. 4261 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 4262 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, FMF, CostKind); 4263 4264 InstructionCost ReductionCost = 0; 4265 4266 auto *Ty = ValVTy; 4267 if (LT.first != 1 && MTy.isVector() && 4268 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4269 // Type needs to be split. We need LT.first - 1 arithmetic ops. 4270 Ty = FixedVectorType::get(ValVTy->getElementType(), 4271 MTy.getVectorNumElements()); 4272 ReductionCost = getArithmeticInstrCost(Opcode, Ty, CostKind); 4273 ReductionCost *= LT.first - 1; 4274 NumVecElts = MTy.getVectorNumElements(); 4275 } 4276 4277 // Now handle reduction with the legal type, taking into account size changes 4278 // at each level. 4279 while (NumVecElts > 1) { 4280 // Determine the size of the remaining vector we need to reduce. 4281 unsigned Size = NumVecElts * ScalarSize; 4282 NumVecElts /= 2; 4283 // If we're reducing from 256/512 bits, use an extract_subvector. 4284 if (Size > 128) { 4285 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 4286 ReductionCost += 4287 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 4288 Ty = SubTy; 4289 } else if (Size == 128) { 4290 // Reducing from 128 bits is a permute of v2f64/v2i64. 4291 FixedVectorType *ShufTy; 4292 if (ValVTy->isFloatingPointTy()) 4293 ShufTy = 4294 FixedVectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 4295 else 4296 ShufTy = 4297 FixedVectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 4298 ReductionCost += 4299 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4300 } else if (Size == 64) { 4301 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 4302 FixedVectorType *ShufTy; 4303 if (ValVTy->isFloatingPointTy()) 4304 ShufTy = 4305 FixedVectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 4306 else 4307 ShufTy = 4308 FixedVectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 4309 ReductionCost += 4310 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4311 } else { 4312 // Reducing from smaller size is a shift by immediate. 4313 auto *ShiftTy = FixedVectorType::get( 4314 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 4315 ReductionCost += getArithmeticInstrCost( 4316 Instruction::LShr, ShiftTy, CostKind, 4317 TargetTransformInfo::OK_AnyValue, 4318 TargetTransformInfo::OK_UniformConstantValue, 4319 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 4320 } 4321 4322 // Add the arithmetic op for this level. 4323 ReductionCost += getArithmeticInstrCost(Opcode, Ty, CostKind); 4324 } 4325 4326 // Add the final extract element to the cost. 4327 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 4328 } 4329 4330 InstructionCost X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, 4331 bool IsUnsigned) { 4332 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 4333 4334 MVT MTy = LT.second; 4335 4336 int ISD; 4337 if (Ty->isIntOrIntVectorTy()) { 4338 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 4339 } else { 4340 assert(Ty->isFPOrFPVectorTy() && 4341 "Expected float point or integer vector type."); 4342 ISD = ISD::FMINNUM; 4343 } 4344 4345 static const CostTblEntry SSE1CostTbl[] = { 4346 {ISD::FMINNUM, MVT::v4f32, 1}, 4347 }; 4348 4349 static const CostTblEntry SSE2CostTbl[] = { 4350 {ISD::FMINNUM, MVT::v2f64, 1}, 4351 {ISD::SMIN, MVT::v8i16, 1}, 4352 {ISD::UMIN, MVT::v16i8, 1}, 4353 }; 4354 4355 static const CostTblEntry SSE41CostTbl[] = { 4356 {ISD::SMIN, MVT::v4i32, 1}, 4357 {ISD::UMIN, MVT::v4i32, 1}, 4358 {ISD::UMIN, MVT::v8i16, 1}, 4359 {ISD::SMIN, MVT::v16i8, 1}, 4360 }; 4361 4362 static const CostTblEntry SSE42CostTbl[] = { 4363 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 4364 }; 4365 4366 static const CostTblEntry AVX1CostTbl[] = { 4367 {ISD::FMINNUM, MVT::v8f32, 1}, 4368 {ISD::FMINNUM, MVT::v4f64, 1}, 4369 {ISD::SMIN, MVT::v8i32, 3}, 4370 {ISD::UMIN, MVT::v8i32, 3}, 4371 {ISD::SMIN, MVT::v16i16, 3}, 4372 {ISD::UMIN, MVT::v16i16, 3}, 4373 {ISD::SMIN, MVT::v32i8, 3}, 4374 {ISD::UMIN, MVT::v32i8, 3}, 4375 }; 4376 4377 static const CostTblEntry AVX2CostTbl[] = { 4378 {ISD::SMIN, MVT::v8i32, 1}, 4379 {ISD::UMIN, MVT::v8i32, 1}, 4380 {ISD::SMIN, MVT::v16i16, 1}, 4381 {ISD::UMIN, MVT::v16i16, 1}, 4382 {ISD::SMIN, MVT::v32i8, 1}, 4383 {ISD::UMIN, MVT::v32i8, 1}, 4384 }; 4385 4386 static const CostTblEntry AVX512CostTbl[] = { 4387 {ISD::FMINNUM, MVT::v16f32, 1}, 4388 {ISD::FMINNUM, MVT::v8f64, 1}, 4389 {ISD::SMIN, MVT::v2i64, 1}, 4390 {ISD::UMIN, MVT::v2i64, 1}, 4391 {ISD::SMIN, MVT::v4i64, 1}, 4392 {ISD::UMIN, MVT::v4i64, 1}, 4393 {ISD::SMIN, MVT::v8i64, 1}, 4394 {ISD::UMIN, MVT::v8i64, 1}, 4395 {ISD::SMIN, MVT::v16i32, 1}, 4396 {ISD::UMIN, MVT::v16i32, 1}, 4397 }; 4398 4399 static const CostTblEntry AVX512BWCostTbl[] = { 4400 {ISD::SMIN, MVT::v32i16, 1}, 4401 {ISD::UMIN, MVT::v32i16, 1}, 4402 {ISD::SMIN, MVT::v64i8, 1}, 4403 {ISD::UMIN, MVT::v64i8, 1}, 4404 }; 4405 4406 // If we have a native MIN/MAX instruction for this type, use it. 4407 if (ST->hasBWI()) 4408 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 4409 return LT.first * Entry->Cost; 4410 4411 if (ST->hasAVX512()) 4412 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 4413 return LT.first * Entry->Cost; 4414 4415 if (ST->hasAVX2()) 4416 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 4417 return LT.first * Entry->Cost; 4418 4419 if (ST->hasAVX()) 4420 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 4421 return LT.first * Entry->Cost; 4422 4423 if (ST->hasSSE42()) 4424 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 4425 return LT.first * Entry->Cost; 4426 4427 if (ST->hasSSE41()) 4428 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 4429 return LT.first * Entry->Cost; 4430 4431 if (ST->hasSSE2()) 4432 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 4433 return LT.first * Entry->Cost; 4434 4435 if (ST->hasSSE1()) 4436 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 4437 return LT.first * Entry->Cost; 4438 4439 unsigned CmpOpcode; 4440 if (Ty->isFPOrFPVectorTy()) { 4441 CmpOpcode = Instruction::FCmp; 4442 } else { 4443 assert(Ty->isIntOrIntVectorTy() && 4444 "expecting floating point or integer type for min/max reduction"); 4445 CmpOpcode = Instruction::ICmp; 4446 } 4447 4448 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4449 // Otherwise fall back to cmp+select. 4450 InstructionCost Result = 4451 getCmpSelInstrCost(CmpOpcode, Ty, CondTy, CmpInst::BAD_ICMP_PREDICATE, 4452 CostKind) + 4453 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, 4454 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4455 return Result; 4456 } 4457 4458 InstructionCost 4459 X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 4460 bool IsUnsigned, 4461 TTI::TargetCostKind CostKind) { 4462 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 4463 4464 MVT MTy = LT.second; 4465 4466 int ISD; 4467 if (ValTy->isIntOrIntVectorTy()) { 4468 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 4469 } else { 4470 assert(ValTy->isFPOrFPVectorTy() && 4471 "Expected float point or integer vector type."); 4472 ISD = ISD::FMINNUM; 4473 } 4474 4475 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 4476 // and make it as the cost. 4477 4478 static const CostTblEntry SSE2CostTblNoPairWise[] = { 4479 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 4480 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 4481 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 4482 }; 4483 4484 static const CostTblEntry SSE41CostTblNoPairWise[] = { 4485 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 4486 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 4487 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 4488 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 4489 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 4490 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 4491 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 4492 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 4493 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 4494 {ISD::SMIN, MVT::v16i8, 6}, 4495 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 4496 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 4497 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 4498 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 4499 }; 4500 4501 static const CostTblEntry AVX1CostTblNoPairWise[] = { 4502 {ISD::SMIN, MVT::v16i16, 6}, 4503 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 4504 {ISD::SMIN, MVT::v32i8, 8}, 4505 {ISD::UMIN, MVT::v32i8, 8}, 4506 }; 4507 4508 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 4509 {ISD::SMIN, MVT::v32i16, 8}, 4510 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 4511 {ISD::SMIN, MVT::v64i8, 10}, 4512 {ISD::UMIN, MVT::v64i8, 10}, 4513 }; 4514 4515 // Before legalizing the type, give a chance to look up illegal narrow types 4516 // in the table. 4517 // FIXME: Is there a better way to do this? 4518 EVT VT = TLI->getValueType(DL, ValTy); 4519 if (VT.isSimple()) { 4520 MVT MTy = VT.getSimpleVT(); 4521 if (ST->hasBWI()) 4522 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4523 return Entry->Cost; 4524 4525 if (ST->hasAVX()) 4526 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4527 return Entry->Cost; 4528 4529 if (ST->hasSSE41()) 4530 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4531 return Entry->Cost; 4532 4533 if (ST->hasSSE2()) 4534 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4535 return Entry->Cost; 4536 } 4537 4538 auto *ValVTy = cast<FixedVectorType>(ValTy); 4539 unsigned NumVecElts = ValVTy->getNumElements(); 4540 4541 auto *Ty = ValVTy; 4542 InstructionCost MinMaxCost = 0; 4543 if (LT.first != 1 && MTy.isVector() && 4544 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4545 // Type needs to be split. We need LT.first - 1 operations ops. 4546 Ty = FixedVectorType::get(ValVTy->getElementType(), 4547 MTy.getVectorNumElements()); 4548 auto *SubCondTy = FixedVectorType::get(CondTy->getElementType(), 4549 MTy.getVectorNumElements()); 4550 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4551 MinMaxCost *= LT.first - 1; 4552 NumVecElts = MTy.getVectorNumElements(); 4553 } 4554 4555 if (ST->hasBWI()) 4556 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4557 return MinMaxCost + Entry->Cost; 4558 4559 if (ST->hasAVX()) 4560 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4561 return MinMaxCost + Entry->Cost; 4562 4563 if (ST->hasSSE41()) 4564 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4565 return MinMaxCost + Entry->Cost; 4566 4567 if (ST->hasSSE2()) 4568 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4569 return MinMaxCost + Entry->Cost; 4570 4571 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 4572 4573 // Special case power of 2 reductions where the scalar type isn't changed 4574 // by type legalization. 4575 if (!isPowerOf2_32(ValVTy->getNumElements()) || 4576 ScalarSize != MTy.getScalarSizeInBits()) 4577 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsUnsigned, CostKind); 4578 4579 // Now handle reduction with the legal type, taking into account size changes 4580 // at each level. 4581 while (NumVecElts > 1) { 4582 // Determine the size of the remaining vector we need to reduce. 4583 unsigned Size = NumVecElts * ScalarSize; 4584 NumVecElts /= 2; 4585 // If we're reducing from 256/512 bits, use an extract_subvector. 4586 if (Size > 128) { 4587 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 4588 MinMaxCost += 4589 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 4590 Ty = SubTy; 4591 } else if (Size == 128) { 4592 // Reducing from 128 bits is a permute of v2f64/v2i64. 4593 VectorType *ShufTy; 4594 if (ValTy->isFloatingPointTy()) 4595 ShufTy = 4596 FixedVectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 4597 else 4598 ShufTy = FixedVectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 4599 MinMaxCost += 4600 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4601 } else if (Size == 64) { 4602 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 4603 FixedVectorType *ShufTy; 4604 if (ValTy->isFloatingPointTy()) 4605 ShufTy = FixedVectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 4606 else 4607 ShufTy = FixedVectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 4608 MinMaxCost += 4609 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4610 } else { 4611 // Reducing from smaller size is a shift by immediate. 4612 auto *ShiftTy = FixedVectorType::get( 4613 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 4614 MinMaxCost += getArithmeticInstrCost( 4615 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, 4616 TargetTransformInfo::OK_AnyValue, 4617 TargetTransformInfo::OK_UniformConstantValue, 4618 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 4619 } 4620 4621 // Add the arithmetic op for this level. 4622 auto *SubCondTy = 4623 FixedVectorType::get(CondTy->getElementType(), Ty->getNumElements()); 4624 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4625 } 4626 4627 // Add the final extract element to the cost. 4628 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 4629 } 4630 4631 /// Calculate the cost of materializing a 64-bit value. This helper 4632 /// method might only calculate a fraction of a larger immediate. Therefore it 4633 /// is valid to return a cost of ZERO. 4634 InstructionCost X86TTIImpl::getIntImmCost(int64_t Val) { 4635 if (Val == 0) 4636 return TTI::TCC_Free; 4637 4638 if (isInt<32>(Val)) 4639 return TTI::TCC_Basic; 4640 4641 return 2 * TTI::TCC_Basic; 4642 } 4643 4644 InstructionCost X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 4645 TTI::TargetCostKind CostKind) { 4646 assert(Ty->isIntegerTy()); 4647 4648 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4649 if (BitSize == 0) 4650 return ~0U; 4651 4652 // Never hoist constants larger than 128bit, because this might lead to 4653 // incorrect code generation or assertions in codegen. 4654 // Fixme: Create a cost model for types larger than i128 once the codegen 4655 // issues have been fixed. 4656 if (BitSize > 128) 4657 return TTI::TCC_Free; 4658 4659 if (Imm == 0) 4660 return TTI::TCC_Free; 4661 4662 // Sign-extend all constants to a multiple of 64-bit. 4663 APInt ImmVal = Imm; 4664 if (BitSize % 64 != 0) 4665 ImmVal = Imm.sext(alignTo(BitSize, 64)); 4666 4667 // Split the constant into 64-bit chunks and calculate the cost for each 4668 // chunk. 4669 InstructionCost Cost = 0; 4670 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 4671 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 4672 int64_t Val = Tmp.getSExtValue(); 4673 Cost += getIntImmCost(Val); 4674 } 4675 // We need at least one instruction to materialize the constant. 4676 return std::max<InstructionCost>(1, Cost); 4677 } 4678 4679 InstructionCost X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, 4680 const APInt &Imm, Type *Ty, 4681 TTI::TargetCostKind CostKind, 4682 Instruction *Inst) { 4683 assert(Ty->isIntegerTy()); 4684 4685 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4686 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4687 // here, so that constant hoisting will ignore this constant. 4688 if (BitSize == 0) 4689 return TTI::TCC_Free; 4690 4691 unsigned ImmIdx = ~0U; 4692 switch (Opcode) { 4693 default: 4694 return TTI::TCC_Free; 4695 case Instruction::GetElementPtr: 4696 // Always hoist the base address of a GetElementPtr. This prevents the 4697 // creation of new constants for every base constant that gets constant 4698 // folded with the offset. 4699 if (Idx == 0) 4700 return 2 * TTI::TCC_Basic; 4701 return TTI::TCC_Free; 4702 case Instruction::Store: 4703 ImmIdx = 0; 4704 break; 4705 case Instruction::ICmp: 4706 // This is an imperfect hack to prevent constant hoisting of 4707 // compares that might be trying to check if a 64-bit value fits in 4708 // 32-bits. The backend can optimize these cases using a right shift by 32. 4709 // Ideally we would check the compare predicate here. There also other 4710 // similar immediates the backend can use shifts for. 4711 if (Idx == 1 && Imm.getBitWidth() == 64) { 4712 uint64_t ImmVal = Imm.getZExtValue(); 4713 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 4714 return TTI::TCC_Free; 4715 } 4716 ImmIdx = 1; 4717 break; 4718 case Instruction::And: 4719 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 4720 // by using a 32-bit operation with implicit zero extension. Detect such 4721 // immediates here as the normal path expects bit 31 to be sign extended. 4722 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 4723 return TTI::TCC_Free; 4724 ImmIdx = 1; 4725 break; 4726 case Instruction::Add: 4727 case Instruction::Sub: 4728 // For add/sub, we can use the opposite instruction for INT32_MIN. 4729 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 4730 return TTI::TCC_Free; 4731 ImmIdx = 1; 4732 break; 4733 case Instruction::UDiv: 4734 case Instruction::SDiv: 4735 case Instruction::URem: 4736 case Instruction::SRem: 4737 // Division by constant is typically expanded later into a different 4738 // instruction sequence. This completely changes the constants. 4739 // Report them as "free" to stop ConstantHoist from marking them as opaque. 4740 return TTI::TCC_Free; 4741 case Instruction::Mul: 4742 case Instruction::Or: 4743 case Instruction::Xor: 4744 ImmIdx = 1; 4745 break; 4746 // Always return TCC_Free for the shift value of a shift instruction. 4747 case Instruction::Shl: 4748 case Instruction::LShr: 4749 case Instruction::AShr: 4750 if (Idx == 1) 4751 return TTI::TCC_Free; 4752 break; 4753 case Instruction::Trunc: 4754 case Instruction::ZExt: 4755 case Instruction::SExt: 4756 case Instruction::IntToPtr: 4757 case Instruction::PtrToInt: 4758 case Instruction::BitCast: 4759 case Instruction::PHI: 4760 case Instruction::Call: 4761 case Instruction::Select: 4762 case Instruction::Ret: 4763 case Instruction::Load: 4764 break; 4765 } 4766 4767 if (Idx == ImmIdx) { 4768 int NumConstants = divideCeil(BitSize, 64); 4769 InstructionCost Cost = X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4770 return (Cost <= NumConstants * TTI::TCC_Basic) 4771 ? static_cast<int>(TTI::TCC_Free) 4772 : Cost; 4773 } 4774 4775 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4776 } 4777 4778 InstructionCost X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 4779 const APInt &Imm, Type *Ty, 4780 TTI::TargetCostKind CostKind) { 4781 assert(Ty->isIntegerTy()); 4782 4783 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4784 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4785 // here, so that constant hoisting will ignore this constant. 4786 if (BitSize == 0) 4787 return TTI::TCC_Free; 4788 4789 switch (IID) { 4790 default: 4791 return TTI::TCC_Free; 4792 case Intrinsic::sadd_with_overflow: 4793 case Intrinsic::uadd_with_overflow: 4794 case Intrinsic::ssub_with_overflow: 4795 case Intrinsic::usub_with_overflow: 4796 case Intrinsic::smul_with_overflow: 4797 case Intrinsic::umul_with_overflow: 4798 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 4799 return TTI::TCC_Free; 4800 break; 4801 case Intrinsic::experimental_stackmap: 4802 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4803 return TTI::TCC_Free; 4804 break; 4805 case Intrinsic::experimental_patchpoint_void: 4806 case Intrinsic::experimental_patchpoint_i64: 4807 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4808 return TTI::TCC_Free; 4809 break; 4810 } 4811 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4812 } 4813 4814 InstructionCost X86TTIImpl::getCFInstrCost(unsigned Opcode, 4815 TTI::TargetCostKind CostKind, 4816 const Instruction *I) { 4817 if (CostKind != TTI::TCK_RecipThroughput) 4818 return Opcode == Instruction::PHI ? 0 : 1; 4819 // Branches are assumed to be predicted. 4820 return 0; 4821 } 4822 4823 int X86TTIImpl::getGatherOverhead() const { 4824 // Some CPUs have more overhead for gather. The specified overhead is relative 4825 // to the Load operation. "2" is the number provided by Intel architects. This 4826 // parameter is used for cost estimation of Gather Op and comparison with 4827 // other alternatives. 4828 // TODO: Remove the explicit hasAVX512()?, That would mean we would only 4829 // enable gather with a -march. 4830 if (ST->hasAVX512() || (ST->hasAVX2() && ST->hasFastGather())) 4831 return 2; 4832 4833 return 1024; 4834 } 4835 4836 int X86TTIImpl::getScatterOverhead() const { 4837 if (ST->hasAVX512()) 4838 return 2; 4839 4840 return 1024; 4841 } 4842 4843 // Return an average cost of Gather / Scatter instruction, maybe improved later. 4844 // FIXME: Add TargetCostKind support. 4845 InstructionCost X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, 4846 const Value *Ptr, Align Alignment, 4847 unsigned AddressSpace) { 4848 4849 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 4850 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4851 4852 // Try to reduce index size from 64 bit (default for GEP) 4853 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 4854 // operation will use 16 x 64 indices which do not fit in a zmm and needs 4855 // to split. Also check that the base pointer is the same for all lanes, 4856 // and that there's at most one variable index. 4857 auto getIndexSizeInBits = [](const Value *Ptr, const DataLayout &DL) { 4858 unsigned IndexSize = DL.getPointerSizeInBits(); 4859 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 4860 if (IndexSize < 64 || !GEP) 4861 return IndexSize; 4862 4863 unsigned NumOfVarIndices = 0; 4864 const Value *Ptrs = GEP->getPointerOperand(); 4865 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 4866 return IndexSize; 4867 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 4868 if (isa<Constant>(GEP->getOperand(i))) 4869 continue; 4870 Type *IndxTy = GEP->getOperand(i)->getType(); 4871 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 4872 IndxTy = IndexVTy->getElementType(); 4873 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 4874 !isa<SExtInst>(GEP->getOperand(i))) || 4875 ++NumOfVarIndices > 1) 4876 return IndexSize; // 64 4877 } 4878 return (unsigned)32; 4879 }; 4880 4881 // Trying to reduce IndexSize to 32 bits for vector 16. 4882 // By default the IndexSize is equal to pointer size. 4883 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 4884 ? getIndexSizeInBits(Ptr, DL) 4885 : DL.getPointerSizeInBits(); 4886 4887 auto *IndexVTy = FixedVectorType::get( 4888 IntegerType::get(SrcVTy->getContext(), IndexSize), VF); 4889 std::pair<InstructionCost, MVT> IdxsLT = 4890 TLI->getTypeLegalizationCost(DL, IndexVTy); 4891 std::pair<InstructionCost, MVT> SrcLT = 4892 TLI->getTypeLegalizationCost(DL, SrcVTy); 4893 InstructionCost::CostType SplitFactor = 4894 *std::max(IdxsLT.first, SrcLT.first).getValue(); 4895 if (SplitFactor > 1) { 4896 // Handle splitting of vector of pointers 4897 auto *SplitSrcTy = 4898 FixedVectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 4899 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 4900 AddressSpace); 4901 } 4902 4903 // The gather / scatter cost is given by Intel architects. It is a rough 4904 // number since we are looking at one instruction in a time. 4905 const int GSOverhead = (Opcode == Instruction::Load) 4906 ? getGatherOverhead() 4907 : getScatterOverhead(); 4908 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4909 MaybeAlign(Alignment), AddressSpace, 4910 TTI::TCK_RecipThroughput); 4911 } 4912 4913 /// Return the cost of full scalarization of gather / scatter operation. 4914 /// 4915 /// Opcode - Load or Store instruction. 4916 /// SrcVTy - The type of the data vector that should be gathered or scattered. 4917 /// VariableMask - The mask is non-constant at compile time. 4918 /// Alignment - Alignment for one element. 4919 /// AddressSpace - pointer[s] address space. 4920 /// 4921 /// FIXME: Add TargetCostKind support. 4922 InstructionCost X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 4923 bool VariableMask, Align Alignment, 4924 unsigned AddressSpace) { 4925 Type *ScalarTy = SrcVTy->getScalarType(); 4926 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4927 APInt DemandedElts = APInt::getAllOnes(VF); 4928 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4929 4930 InstructionCost MaskUnpackCost = 0; 4931 if (VariableMask) { 4932 auto *MaskTy = 4933 FixedVectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 4934 MaskUnpackCost = getScalarizationOverhead( 4935 MaskTy, DemandedElts, /*Insert=*/false, /*Extract=*/true); 4936 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 4937 Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), nullptr, 4938 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4939 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 4940 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 4941 } 4942 4943 InstructionCost AddressUnpackCost = getScalarizationOverhead( 4944 FixedVectorType::get(ScalarTy->getPointerTo(), VF), DemandedElts, 4945 /*Insert=*/false, /*Extract=*/true); 4946 4947 // The cost of the scalar loads/stores. 4948 InstructionCost MemoryOpCost = 4949 VF * getMemoryOpCost(Opcode, ScalarTy, MaybeAlign(Alignment), 4950 AddressSpace, CostKind); 4951 4952 // The cost of forming the vector from loaded scalars/ 4953 // scalarizing the vector to perform scalar stores. 4954 InstructionCost InsertExtractCost = 4955 getScalarizationOverhead(cast<FixedVectorType>(SrcVTy), DemandedElts, 4956 /*Insert=*/Opcode == Instruction::Load, 4957 /*Extract=*/Opcode == Instruction::Store); 4958 4959 return AddressUnpackCost + MemoryOpCost + MaskUnpackCost + InsertExtractCost; 4960 } 4961 4962 /// Calculate the cost of Gather / Scatter operation 4963 InstructionCost X86TTIImpl::getGatherScatterOpCost( 4964 unsigned Opcode, Type *SrcVTy, const Value *Ptr, bool VariableMask, 4965 Align Alignment, TTI::TargetCostKind CostKind, 4966 const Instruction *I = nullptr) { 4967 if (CostKind != TTI::TCK_RecipThroughput) { 4968 if ((Opcode == Instruction::Load && 4969 isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4970 (Opcode == Instruction::Store && 4971 isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4972 return 1; 4973 return BaseT::getGatherScatterOpCost(Opcode, SrcVTy, Ptr, VariableMask, 4974 Alignment, CostKind, I); 4975 } 4976 4977 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 4978 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 4979 if (!PtrTy && Ptr->getType()->isVectorTy()) 4980 PtrTy = dyn_cast<PointerType>( 4981 cast<VectorType>(Ptr->getType())->getElementType()); 4982 assert(PtrTy && "Unexpected type for Ptr argument"); 4983 unsigned AddressSpace = PtrTy->getAddressSpace(); 4984 4985 if ((Opcode == Instruction::Load && 4986 !isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4987 (Opcode == Instruction::Store && 4988 !isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4989 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 4990 AddressSpace); 4991 4992 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 4993 } 4994 4995 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 4996 TargetTransformInfo::LSRCost &C2) { 4997 // X86 specific here are "instruction number 1st priority". 4998 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 4999 C1.NumIVMuls, C1.NumBaseAdds, 5000 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 5001 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 5002 C2.NumIVMuls, C2.NumBaseAdds, 5003 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 5004 } 5005 5006 bool X86TTIImpl::canMacroFuseCmp() { 5007 return ST->hasMacroFusion() || ST->hasBranchFusion(); 5008 } 5009 5010 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, Align Alignment) { 5011 if (!ST->hasAVX()) 5012 return false; 5013 5014 // The backend can't handle a single element vector. 5015 if (isa<VectorType>(DataTy) && 5016 cast<FixedVectorType>(DataTy)->getNumElements() == 1) 5017 return false; 5018 Type *ScalarTy = DataTy->getScalarType(); 5019 5020 if (ScalarTy->isPointerTy()) 5021 return true; 5022 5023 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 5024 return true; 5025 5026 if (ScalarTy->isHalfTy() && ST->hasBWI() && ST->hasFP16()) 5027 return true; 5028 5029 if (!ScalarTy->isIntegerTy()) 5030 return false; 5031 5032 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 5033 return IntWidth == 32 || IntWidth == 64 || 5034 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 5035 } 5036 5037 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, Align Alignment) { 5038 return isLegalMaskedLoad(DataType, Alignment); 5039 } 5040 5041 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 5042 unsigned DataSize = DL.getTypeStoreSize(DataType); 5043 // The only supported nontemporal loads are for aligned vectors of 16 or 32 5044 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 5045 // (the equivalent stores only require AVX). 5046 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 5047 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 5048 5049 return false; 5050 } 5051 5052 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 5053 unsigned DataSize = DL.getTypeStoreSize(DataType); 5054 5055 // SSE4A supports nontemporal stores of float and double at arbitrary 5056 // alignment. 5057 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 5058 return true; 5059 5060 // Besides the SSE4A subtarget exception above, only aligned stores are 5061 // available nontemporaly on any other subtarget. And only stores with a size 5062 // of 4..32 bytes (powers of 2, only) are permitted. 5063 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 5064 !isPowerOf2_32(DataSize)) 5065 return false; 5066 5067 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 5068 // loads require AVX2). 5069 if (DataSize == 32) 5070 return ST->hasAVX(); 5071 if (DataSize == 16) 5072 return ST->hasSSE1(); 5073 return true; 5074 } 5075 5076 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 5077 if (!isa<VectorType>(DataTy)) 5078 return false; 5079 5080 if (!ST->hasAVX512()) 5081 return false; 5082 5083 // The backend can't handle a single element vector. 5084 if (cast<FixedVectorType>(DataTy)->getNumElements() == 1) 5085 return false; 5086 5087 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 5088 5089 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 5090 return true; 5091 5092 if (!ScalarTy->isIntegerTy()) 5093 return false; 5094 5095 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 5096 return IntWidth == 32 || IntWidth == 64 || 5097 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 5098 } 5099 5100 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 5101 return isLegalMaskedExpandLoad(DataTy); 5102 } 5103 5104 bool X86TTIImpl::supportsGather() const { 5105 // Some CPUs have better gather performance than others. 5106 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 5107 // enable gather with a -march. 5108 return ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()); 5109 } 5110 5111 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, Align Alignment) { 5112 if (!supportsGather()) 5113 return false; 5114 5115 // This function is called now in two cases: from the Loop Vectorizer 5116 // and from the Scalarizer. 5117 // When the Loop Vectorizer asks about legality of the feature, 5118 // the vectorization factor is not calculated yet. The Loop Vectorizer 5119 // sends a scalar type and the decision is based on the width of the 5120 // scalar element. 5121 // Later on, the cost model will estimate usage this intrinsic based on 5122 // the vector type. 5123 // The Scalarizer asks again about legality. It sends a vector type. 5124 // In this case we can reject non-power-of-2 vectors. 5125 // We also reject single element vectors as the type legalizer can't 5126 // scalarize it. 5127 if (auto *DataVTy = dyn_cast<FixedVectorType>(DataTy)) { 5128 unsigned NumElts = DataVTy->getNumElements(); 5129 if (NumElts == 1) 5130 return false; 5131 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 5132 // Vector-4 of gather/scatter instruction does not exist on KNL. 5133 // We can extend it to 8 elements, but zeroing upper bits of 5134 // the mask vector will add more instructions. Right now we give the scalar 5135 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter 5136 // instruction is better in the VariableMask case. 5137 if (ST->hasAVX512() && (NumElts == 2 || (NumElts == 4 && !ST->hasVLX()))) 5138 return false; 5139 } 5140 Type *ScalarTy = DataTy->getScalarType(); 5141 if (ScalarTy->isPointerTy()) 5142 return true; 5143 5144 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 5145 return true; 5146 5147 if (!ScalarTy->isIntegerTy()) 5148 return false; 5149 5150 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 5151 return IntWidth == 32 || IntWidth == 64; 5152 } 5153 5154 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, Align Alignment) { 5155 // AVX2 doesn't support scatter 5156 if (!ST->hasAVX512()) 5157 return false; 5158 return isLegalMaskedGather(DataType, Alignment); 5159 } 5160 5161 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 5162 EVT VT = TLI->getValueType(DL, DataType); 5163 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 5164 } 5165 5166 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 5167 return false; 5168 } 5169 5170 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 5171 const Function *Callee) const { 5172 const TargetMachine &TM = getTLI()->getTargetMachine(); 5173 5174 // Work this as a subsetting of subtarget features. 5175 const FeatureBitset &CallerBits = 5176 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 5177 const FeatureBitset &CalleeBits = 5178 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 5179 5180 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 5181 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 5182 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 5183 } 5184 5185 bool X86TTIImpl::areFunctionArgsABICompatible( 5186 const Function *Caller, const Function *Callee, 5187 SmallPtrSetImpl<Argument *> &Args) const { 5188 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args)) 5189 return false; 5190 5191 // If we get here, we know the target features match. If one function 5192 // considers 512-bit vectors legal and the other does not, consider them 5193 // incompatible. 5194 const TargetMachine &TM = getTLI()->getTargetMachine(); 5195 5196 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 5197 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs()) 5198 return true; 5199 5200 // Consider the arguments compatible if they aren't vectors or aggregates. 5201 // FIXME: Look at the size of vectors. 5202 // FIXME: Look at the element types of aggregates to see if there are vectors. 5203 // FIXME: The API of this function seems intended to allow arguments 5204 // to be removed from the set, but the caller doesn't check if the set 5205 // becomes empty so that may not work in practice. 5206 return llvm::none_of(Args, [](Argument *A) { 5207 auto *EltTy = cast<PointerType>(A->getType())->getElementType(); 5208 return EltTy->isVectorTy() || EltTy->isAggregateType(); 5209 }); 5210 } 5211 5212 X86TTIImpl::TTI::MemCmpExpansionOptions 5213 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 5214 TTI::MemCmpExpansionOptions Options; 5215 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 5216 Options.NumLoadsPerBlock = 2; 5217 // All GPR and vector loads can be unaligned. 5218 Options.AllowOverlappingLoads = true; 5219 if (IsZeroCmp) { 5220 // Only enable vector loads for equality comparison. Right now the vector 5221 // version is not as fast for three way compare (see #33329). 5222 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 5223 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 5224 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 5225 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 5226 } 5227 if (ST->is64Bit()) { 5228 Options.LoadSizes.push_back(8); 5229 } 5230 Options.LoadSizes.push_back(4); 5231 Options.LoadSizes.push_back(2); 5232 Options.LoadSizes.push_back(1); 5233 return Options; 5234 } 5235 5236 bool X86TTIImpl::prefersVectorizedAddressing() const { 5237 return supportsGather(); 5238 } 5239 5240 bool X86TTIImpl::supportsEfficientVectorElementLoadStore() const { 5241 return false; 5242 } 5243 5244 bool X86TTIImpl::enableInterleavedAccessVectorization() { 5245 // TODO: We expect this to be beneficial regardless of arch, 5246 // but there are currently some unexplained performance artifacts on Atom. 5247 // As a temporary solution, disable on Atom. 5248 return !(ST->isAtom()); 5249 } 5250 5251 // Get estimation for interleaved load/store operations and strided load. 5252 // \p Indices contains indices for strided load. 5253 // \p Factor - the factor of interleaving. 5254 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 5255 InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX512( 5256 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 5257 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 5258 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 5259 // VecTy for interleave memop is <VF*Factor x Elt>. 5260 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 5261 // VecTy = <12 x i32>. 5262 5263 // Calculate the number of memory operations (NumOfMemOps), required 5264 // for load/store the VecTy. 5265 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 5266 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 5267 unsigned LegalVTSize = LegalVT.getStoreSize(); 5268 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 5269 5270 // Get the cost of one memory operation. 5271 auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(), 5272 LegalVT.getVectorNumElements()); 5273 InstructionCost MemOpCost; 5274 if (UseMaskForCond || UseMaskForGaps) 5275 MemOpCost = getMaskedMemoryOpCost(Opcode, SingleMemOpTy, Alignment, 5276 AddressSpace, CostKind); 5277 else 5278 MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, MaybeAlign(Alignment), 5279 AddressSpace, CostKind); 5280 5281 unsigned VF = VecTy->getNumElements() / Factor; 5282 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 5283 5284 // FIXME: this is the most conservative estimate for the mask cost. 5285 InstructionCost MaskCost; 5286 if (UseMaskForCond || UseMaskForGaps) { 5287 APInt DemandedLoadStoreElts = APInt::getZero(VecTy->getNumElements()); 5288 for (unsigned Index : Indices) { 5289 assert(Index < Factor && "Invalid index for interleaved memory op"); 5290 for (unsigned Elm = 0; Elm < VF; Elm++) 5291 DemandedLoadStoreElts.setBit(Index + Elm * Factor); 5292 } 5293 5294 Type *I8Type = Type::getInt8Ty(VecTy->getContext()); 5295 5296 MaskCost = getReplicationShuffleCost( 5297 I8Type, Factor, VF, 5298 UseMaskForGaps ? DemandedLoadStoreElts 5299 : APInt::getAllOnes(VecTy->getNumElements()), 5300 CostKind); 5301 5302 // The Gaps mask is invariant and created outside the loop, therefore the 5303 // cost of creating it is not accounted for here. However if we have both 5304 // a MaskForGaps and some other mask that guards the execution of the 5305 // memory access, we need to account for the cost of And-ing the two masks 5306 // inside the loop. 5307 if (UseMaskForGaps) { 5308 auto *MaskVT = FixedVectorType::get(I8Type, VecTy->getNumElements()); 5309 MaskCost += getArithmeticInstrCost(BinaryOperator::And, MaskVT, CostKind); 5310 } 5311 } 5312 5313 if (Opcode == Instruction::Load) { 5314 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 5315 // contain the cost of the optimized shuffle sequence that the 5316 // X86InterleavedAccess pass will generate. 5317 // The cost of loads and stores are computed separately from the table. 5318 5319 // X86InterleavedAccess support only the following interleaved-access group. 5320 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 5321 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 5322 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 5323 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 5324 }; 5325 5326 if (const auto *Entry = 5327 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 5328 return MaskCost + NumOfMemOps * MemOpCost + Entry->Cost; 5329 //If an entry does not exist, fallback to the default implementation. 5330 5331 // Kind of shuffle depends on number of loaded values. 5332 // If we load the entire data in one register, we can use a 1-src shuffle. 5333 // Otherwise, we'll merge 2 sources in each operation. 5334 TTI::ShuffleKind ShuffleKind = 5335 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 5336 5337 InstructionCost ShuffleCost = 5338 getShuffleCost(ShuffleKind, SingleMemOpTy, None, 0, nullptr); 5339 5340 unsigned NumOfLoadsInInterleaveGrp = 5341 Indices.size() ? Indices.size() : Factor; 5342 auto *ResultTy = FixedVectorType::get(VecTy->getElementType(), 5343 VecTy->getNumElements() / Factor); 5344 InstructionCost NumOfResults = 5345 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 5346 NumOfLoadsInInterleaveGrp; 5347 5348 // About a half of the loads may be folded in shuffles when we have only 5349 // one result. If we have more than one result, we do not fold loads at all. 5350 unsigned NumOfUnfoldedLoads = 5351 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 5352 5353 // Get a number of shuffle operations per result. 5354 unsigned NumOfShufflesPerResult = 5355 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 5356 5357 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 5358 // When we have more than one destination, we need additional instructions 5359 // to keep sources. 5360 InstructionCost NumOfMoves = 0; 5361 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 5362 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 5363 5364 InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 5365 MaskCost + NumOfUnfoldedLoads * MemOpCost + 5366 NumOfMoves; 5367 5368 return Cost; 5369 } 5370 5371 // Store. 5372 assert(Opcode == Instruction::Store && 5373 "Expected Store Instruction at this point"); 5374 // X86InterleavedAccess support only the following interleaved-access group. 5375 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 5376 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 5377 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 5378 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 5379 5380 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 5381 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 5382 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 5383 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 5384 }; 5385 5386 if (const auto *Entry = 5387 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 5388 return MaskCost + NumOfMemOps * MemOpCost + Entry->Cost; 5389 //If an entry does not exist, fallback to the default implementation. 5390 5391 // There is no strided stores meanwhile. And store can't be folded in 5392 // shuffle. 5393 unsigned NumOfSources = Factor; // The number of values to be merged. 5394 InstructionCost ShuffleCost = 5395 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, None, 0, nullptr); 5396 unsigned NumOfShufflesPerStore = NumOfSources - 1; 5397 5398 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 5399 // We need additional instructions to keep sources. 5400 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 5401 InstructionCost Cost = 5402 MaskCost + 5403 NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 5404 NumOfMoves; 5405 return Cost; 5406 } 5407 5408 InstructionCost X86TTIImpl::getInterleavedMemoryOpCost( 5409 unsigned Opcode, Type *BaseTy, unsigned Factor, ArrayRef<unsigned> Indices, 5410 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, 5411 bool UseMaskForCond, bool UseMaskForGaps) { 5412 auto *VecTy = cast<FixedVectorType>(BaseTy); 5413 5414 auto isSupportedOnAVX512 = [&](Type *VecTy, bool HasBW) { 5415 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 5416 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 5417 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 5418 return true; 5419 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8) || 5420 (!ST->useSoftFloat() && ST->hasFP16() && EltTy->isHalfTy())) 5421 return HasBW; 5422 return false; 5423 }; 5424 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 5425 return getInterleavedMemoryOpCostAVX512( 5426 Opcode, VecTy, Factor, Indices, Alignment, 5427 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 5428 5429 if (UseMaskForCond || UseMaskForGaps) 5430 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5431 Alignment, AddressSpace, CostKind, 5432 UseMaskForCond, UseMaskForGaps); 5433 5434 // Get estimation for interleaved load/store operations for SSE-AVX2. 5435 // As opposed to AVX-512, SSE-AVX2 do not have generic shuffles that allow 5436 // computing the cost using a generic formula as a function of generic 5437 // shuffles. We therefore use a lookup table instead, filled according to 5438 // the instruction sequences that codegen currently generates. 5439 5440 // VecTy for interleave memop is <VF*Factor x Elt>. 5441 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 5442 // VecTy = <12 x i32>. 5443 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 5444 5445 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 5446 // the VF=2, while v2i128 is an unsupported MVT vector type 5447 // (see MachineValueType.h::getVectorVT()). 5448 if (!LegalVT.isVector()) 5449 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5450 Alignment, AddressSpace, CostKind); 5451 5452 unsigned VF = VecTy->getNumElements() / Factor; 5453 Type *ScalarTy = VecTy->getElementType(); 5454 // Deduplicate entries, model floats/pointers as appropriately-sized integers. 5455 if (!ScalarTy->isIntegerTy()) 5456 ScalarTy = 5457 Type::getIntNTy(ScalarTy->getContext(), DL.getTypeSizeInBits(ScalarTy)); 5458 5459 // Get the cost of all the memory operations. 5460 // FIXME: discount dead loads. 5461 InstructionCost MemOpCosts = getMemoryOpCost( 5462 Opcode, VecTy, MaybeAlign(Alignment), AddressSpace, CostKind); 5463 5464 auto *VT = FixedVectorType::get(ScalarTy, VF); 5465 EVT ETy = TLI->getValueType(DL, VT); 5466 if (!ETy.isSimple()) 5467 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5468 Alignment, AddressSpace, CostKind); 5469 5470 // TODO: Complete for other data-types and strides. 5471 // Each combination of Stride, element bit width and VF results in a different 5472 // sequence; The cost tables are therefore accessed with: 5473 // Factor (stride) and VectorType=VFxiN. 5474 // The Cost accounts only for the shuffle sequence; 5475 // The cost of the loads/stores is accounted for separately. 5476 // 5477 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 5478 {2, MVT::v2i8, 2}, // (load 4i8 and) deinterleave into 2 x 2i8 5479 {2, MVT::v4i8, 2}, // (load 8i8 and) deinterleave into 2 x 4i8 5480 {2, MVT::v8i8, 2}, // (load 16i8 and) deinterleave into 2 x 8i8 5481 {2, MVT::v16i8, 4}, // (load 32i8 and) deinterleave into 2 x 16i8 5482 {2, MVT::v32i8, 6}, // (load 64i8 and) deinterleave into 2 x 32i8 5483 5484 {2, MVT::v8i16, 6}, // (load 16i16 and) deinterleave into 2 x 8i16 5485 {2, MVT::v16i16, 9}, // (load 32i16 and) deinterleave into 2 x 16i16 5486 {2, MVT::v32i16, 18}, // (load 64i16 and) deinterleave into 2 x 32i16 5487 5488 {2, MVT::v8i32, 4}, // (load 16i32 and) deinterleave into 2 x 8i32 5489 {2, MVT::v16i32, 8}, // (load 32i32 and) deinterleave into 2 x 16i32 5490 {2, MVT::v32i32, 16}, // (load 64i32 and) deinterleave into 2 x 32i32 5491 5492 {2, MVT::v4i64, 4}, // (load 8i64 and) deinterleave into 2 x 4i64 5493 {2, MVT::v8i64, 8}, // (load 16i64 and) deinterleave into 2 x 8i64 5494 {2, MVT::v16i64, 16}, // (load 32i64 and) deinterleave into 2 x 16i64 5495 {2, MVT::v32i64, 32}, // (load 64i64 and) deinterleave into 2 x 32i64 5496 5497 {3, MVT::v2i8, 3}, // (load 6i8 and) deinterleave into 3 x 2i8 5498 {3, MVT::v4i8, 3}, // (load 12i8 and) deinterleave into 3 x 4i8 5499 {3, MVT::v8i8, 6}, // (load 24i8 and) deinterleave into 3 x 8i8 5500 {3, MVT::v16i8, 11}, // (load 48i8 and) deinterleave into 3 x 16i8 5501 {3, MVT::v32i8, 14}, // (load 96i8 and) deinterleave into 3 x 32i8 5502 5503 {3, MVT::v2i16, 5}, // (load 6i16 and) deinterleave into 3 x 2i16 5504 {3, MVT::v4i16, 7}, // (load 12i16 and) deinterleave into 3 x 4i16 5505 {3, MVT::v8i16, 9}, // (load 24i16 and) deinterleave into 3 x 8i16 5506 {3, MVT::v16i16, 28}, // (load 48i16 and) deinterleave into 3 x 16i16 5507 {3, MVT::v32i16, 56}, // (load 96i16 and) deinterleave into 3 x 32i16 5508 5509 {3, MVT::v2i32, 3}, // (load 6i32 and) deinterleave into 3 x 2i32 5510 {3, MVT::v4i32, 3}, // (load 12i32 and) deinterleave into 3 x 4i32 5511 {3, MVT::v8i32, 7}, // (load 24i32 and) deinterleave into 3 x 8i32 5512 {3, MVT::v16i32, 14}, // (load 48i32 and) deinterleave into 3 x 16i32 5513 {3, MVT::v32i32, 32}, // (load 96i32 and) deinterleave into 3 x 32i32 5514 5515 {3, MVT::v2i64, 1}, // (load 6i64 and) deinterleave into 3 x 2i64 5516 {3, MVT::v4i64, 5}, // (load 12i64 and) deinterleave into 3 x 4i64 5517 {3, MVT::v8i64, 10}, // (load 24i64 and) deinterleave into 3 x 8i64 5518 {3, MVT::v16i64, 20}, // (load 48i64 and) deinterleave into 3 x 16i64 5519 5520 {4, MVT::v2i8, 4}, // (load 8i8 and) deinterleave into 4 x 2i8 5521 {4, MVT::v4i8, 4}, // (load 16i8 and) deinterleave into 4 x 4i8 5522 {4, MVT::v8i8, 12}, // (load 32i8 and) deinterleave into 4 x 8i8 5523 {4, MVT::v16i8, 24}, // (load 64i8 and) deinterleave into 4 x 16i8 5524 {4, MVT::v32i8, 56}, // (load 128i8 and) deinterleave into 4 x 32i8 5525 5526 {4, MVT::v2i16, 6}, // (load 8i16 and) deinterleave into 4 x 2i16 5527 {4, MVT::v4i16, 17}, // (load 16i16 and) deinterleave into 4 x 4i16 5528 {4, MVT::v8i16, 33}, // (load 32i16 and) deinterleave into 4 x 8i16 5529 {4, MVT::v16i16, 75}, // (load 64i16 and) deinterleave into 4 x 16i16 5530 {4, MVT::v32i16, 150}, // (load 128i16 and) deinterleave into 4 x 32i16 5531 5532 {4, MVT::v2i32, 4}, // (load 8i32 and) deinterleave into 4 x 2i32 5533 {4, MVT::v4i32, 8}, // (load 16i32 and) deinterleave into 4 x 4i32 5534 {4, MVT::v8i32, 16}, // (load 32i32 and) deinterleave into 4 x 8i32 5535 {4, MVT::v16i32, 32}, // (load 64i32 and) deinterleave into 4 x 16i32 5536 {4, MVT::v32i32, 68}, // (load 128i32 and) deinterleave into 4 x 32i32 5537 5538 {4, MVT::v2i64, 6}, // (load 8i64 and) deinterleave into 4 x 2i64 5539 {4, MVT::v4i64, 8}, // (load 16i64 and) deinterleave into 4 x 4i64 5540 {4, MVT::v8i64, 20}, // (load 32i64 and) deinterleave into 4 x 8i64 5541 {4, MVT::v16i64, 40}, // (load 64i64 and) deinterleave into 4 x 16i64 5542 5543 {6, MVT::v2i8, 6}, // (load 12i8 and) deinterleave into 6 x 2i8 5544 {6, MVT::v4i8, 14}, // (load 24i8 and) deinterleave into 6 x 4i8 5545 {6, MVT::v8i8, 18}, // (load 48i8 and) deinterleave into 6 x 8i8 5546 {6, MVT::v16i8, 43}, // (load 96i8 and) deinterleave into 6 x 16i8 5547 {6, MVT::v32i8, 82}, // (load 192i8 and) deinterleave into 6 x 32i8 5548 5549 {6, MVT::v2i16, 13}, // (load 12i16 and) deinterleave into 6 x 2i16 5550 {6, MVT::v4i16, 9}, // (load 24i16 and) deinterleave into 6 x 4i16 5551 {6, MVT::v8i16, 39}, // (load 48i16 and) deinterleave into 6 x 8i16 5552 {6, MVT::v16i16, 106}, // (load 96i16 and) deinterleave into 6 x 16i16 5553 {6, MVT::v32i16, 212}, // (load 192i16 and) deinterleave into 6 x 32i16 5554 5555 {6, MVT::v2i32, 6}, // (load 12i32 and) deinterleave into 6 x 2i32 5556 {6, MVT::v4i32, 15}, // (load 24i32 and) deinterleave into 6 x 4i32 5557 {6, MVT::v8i32, 31}, // (load 48i32 and) deinterleave into 6 x 8i32 5558 {6, MVT::v16i32, 64}, // (load 96i32 and) deinterleave into 6 x 16i32 5559 5560 {6, MVT::v2i64, 6}, // (load 12i64 and) deinterleave into 6 x 2i64 5561 {6, MVT::v4i64, 18}, // (load 24i64 and) deinterleave into 6 x 4i64 5562 {6, MVT::v8i64, 36}, // (load 48i64 and) deinterleave into 6 x 8i64 5563 5564 {8, MVT::v8i32, 40} // (load 64i32 and) deinterleave into 8 x 8i32 5565 }; 5566 5567 static const CostTblEntry SSSE3InterleavedLoadTbl[] = { 5568 {2, MVT::v4i16, 2}, // (load 8i16 and) deinterleave into 2 x 4i16 5569 }; 5570 5571 static const CostTblEntry SSE2InterleavedLoadTbl[] = { 5572 {2, MVT::v2i16, 2}, // (load 4i16 and) deinterleave into 2 x 2i16 5573 {2, MVT::v4i16, 7}, // (load 8i16 and) deinterleave into 2 x 4i16 5574 5575 {2, MVT::v2i32, 2}, // (load 4i32 and) deinterleave into 2 x 2i32 5576 {2, MVT::v4i32, 2}, // (load 8i32 and) deinterleave into 2 x 4i32 5577 5578 {2, MVT::v2i64, 2}, // (load 4i64 and) deinterleave into 2 x 2i64 5579 }; 5580 5581 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 5582 {2, MVT::v16i8, 3}, // interleave 2 x 16i8 into 32i8 (and store) 5583 {2, MVT::v32i8, 4}, // interleave 2 x 32i8 into 64i8 (and store) 5584 5585 {2, MVT::v8i16, 3}, // interleave 2 x 8i16 into 16i16 (and store) 5586 {2, MVT::v16i16, 4}, // interleave 2 x 16i16 into 32i16 (and store) 5587 {2, MVT::v32i16, 8}, // interleave 2 x 32i16 into 64i16 (and store) 5588 5589 {2, MVT::v4i32, 2}, // interleave 2 x 4i32 into 8i32 (and store) 5590 {2, MVT::v8i32, 4}, // interleave 2 x 8i32 into 16i32 (and store) 5591 {2, MVT::v16i32, 8}, // interleave 2 x 16i32 into 32i32 (and store) 5592 {2, MVT::v32i32, 16}, // interleave 2 x 32i32 into 64i32 (and store) 5593 5594 {2, MVT::v2i64, 2}, // interleave 2 x 2i64 into 4i64 (and store) 5595 {2, MVT::v4i64, 4}, // interleave 2 x 4i64 into 8i64 (and store) 5596 {2, MVT::v8i64, 8}, // interleave 2 x 8i64 into 16i64 (and store) 5597 {2, MVT::v16i64, 16}, // interleave 2 x 16i64 into 32i64 (and store) 5598 {2, MVT::v32i64, 32}, // interleave 2 x 32i64 into 64i64 (and store) 5599 5600 {3, MVT::v2i8, 4}, // interleave 3 x 2i8 into 6i8 (and store) 5601 {3, MVT::v4i8, 4}, // interleave 3 x 4i8 into 12i8 (and store) 5602 {3, MVT::v8i8, 6}, // interleave 3 x 8i8 into 24i8 (and store) 5603 {3, MVT::v16i8, 11}, // interleave 3 x 16i8 into 48i8 (and store) 5604 {3, MVT::v32i8, 13}, // interleave 3 x 32i8 into 96i8 (and store) 5605 5606 {3, MVT::v2i16, 4}, // interleave 3 x 2i16 into 6i16 (and store) 5607 {3, MVT::v4i16, 6}, // interleave 3 x 4i16 into 12i16 (and store) 5608 {3, MVT::v8i16, 12}, // interleave 3 x 8i16 into 24i16 (and store) 5609 {3, MVT::v16i16, 27}, // interleave 3 x 16i16 into 48i16 (and store) 5610 {3, MVT::v32i16, 54}, // interleave 3 x 32i16 into 96i16 (and store) 5611 5612 {3, MVT::v2i32, 4}, // interleave 3 x 2i32 into 6i32 (and store) 5613 {3, MVT::v4i32, 5}, // interleave 3 x 4i32 into 12i32 (and store) 5614 {3, MVT::v8i32, 11}, // interleave 3 x 8i32 into 24i32 (and store) 5615 {3, MVT::v16i32, 22}, // interleave 3 x 16i32 into 48i32 (and store) 5616 {3, MVT::v32i32, 48}, // interleave 3 x 32i32 into 96i32 (and store) 5617 5618 {3, MVT::v2i64, 4}, // interleave 3 x 2i64 into 6i64 (and store) 5619 {3, MVT::v4i64, 6}, // interleave 3 x 4i64 into 12i64 (and store) 5620 {3, MVT::v8i64, 12}, // interleave 3 x 8i64 into 24i64 (and store) 5621 {3, MVT::v16i64, 24}, // interleave 3 x 16i64 into 48i64 (and store) 5622 5623 {4, MVT::v2i8, 4}, // interleave 4 x 2i8 into 8i8 (and store) 5624 {4, MVT::v4i8, 4}, // interleave 4 x 4i8 into 16i8 (and store) 5625 {4, MVT::v8i8, 4}, // interleave 4 x 8i8 into 32i8 (and store) 5626 {4, MVT::v16i8, 8}, // interleave 4 x 16i8 into 64i8 (and store) 5627 {4, MVT::v32i8, 12}, // interleave 4 x 32i8 into 128i8 (and store) 5628 5629 {4, MVT::v2i16, 2}, // interleave 4 x 2i16 into 8i16 (and store) 5630 {4, MVT::v4i16, 6}, // interleave 4 x 4i16 into 16i16 (and store) 5631 {4, MVT::v8i16, 10}, // interleave 4 x 8i16 into 32i16 (and store) 5632 {4, MVT::v16i16, 32}, // interleave 4 x 16i16 into 64i16 (and store) 5633 {4, MVT::v32i16, 64}, // interleave 4 x 32i16 into 128i16 (and store) 5634 5635 {4, MVT::v2i32, 5}, // interleave 4 x 2i32 into 8i32 (and store) 5636 {4, MVT::v4i32, 6}, // interleave 4 x 4i32 into 16i32 (and store) 5637 {4, MVT::v8i32, 16}, // interleave 4 x 8i32 into 32i32 (and store) 5638 {4, MVT::v16i32, 32}, // interleave 4 x 16i32 into 64i32 (and store) 5639 {4, MVT::v32i32, 64}, // interleave 4 x 32i32 into 128i32 (and store) 5640 5641 {4, MVT::v2i64, 6}, // interleave 4 x 2i64 into 8i64 (and store) 5642 {4, MVT::v4i64, 8}, // interleave 4 x 4i64 into 16i64 (and store) 5643 {4, MVT::v8i64, 20}, // interleave 4 x 8i64 into 32i64 (and store) 5644 {4, MVT::v16i64, 40}, // interleave 4 x 16i64 into 64i64 (and store) 5645 5646 {6, MVT::v2i8, 7}, // interleave 6 x 2i8 into 12i8 (and store) 5647 {6, MVT::v4i8, 9}, // interleave 6 x 4i8 into 24i8 (and store) 5648 {6, MVT::v8i8, 16}, // interleave 6 x 8i8 into 48i8 (and store) 5649 {6, MVT::v16i8, 27}, // interleave 6 x 16i8 into 96i8 (and store) 5650 {6, MVT::v32i8, 90}, // interleave 6 x 32i8 into 192i8 (and store) 5651 5652 {6, MVT::v2i16, 10}, // interleave 6 x 2i16 into 12i16 (and store) 5653 {6, MVT::v4i16, 15}, // interleave 6 x 4i16 into 24i16 (and store) 5654 {6, MVT::v8i16, 21}, // interleave 6 x 8i16 into 48i16 (and store) 5655 {6, MVT::v16i16, 58}, // interleave 6 x 16i16 into 96i16 (and store) 5656 {6, MVT::v32i16, 90}, // interleave 6 x 32i16 into 192i16 (and store) 5657 5658 {6, MVT::v2i32, 9}, // interleave 6 x 2i32 into 12i32 (and store) 5659 {6, MVT::v4i32, 12}, // interleave 6 x 4i32 into 24i32 (and store) 5660 {6, MVT::v8i32, 33}, // interleave 6 x 8i32 into 48i32 (and store) 5661 {6, MVT::v16i32, 66}, // interleave 6 x 16i32 into 96i32 (and store) 5662 5663 {6, MVT::v2i64, 8}, // interleave 6 x 2i64 into 12i64 (and store) 5664 {6, MVT::v4i64, 15}, // interleave 6 x 4i64 into 24i64 (and store) 5665 {6, MVT::v8i64, 30}, // interleave 6 x 8i64 into 48i64 (and store) 5666 }; 5667 5668 static const CostTblEntry SSE2InterleavedStoreTbl[] = { 5669 {2, MVT::v2i8, 1}, // interleave 2 x 2i8 into 4i8 (and store) 5670 {2, MVT::v4i8, 1}, // interleave 2 x 4i8 into 8i8 (and store) 5671 {2, MVT::v8i8, 1}, // interleave 2 x 8i8 into 16i8 (and store) 5672 5673 {2, MVT::v2i16, 1}, // interleave 2 x 2i16 into 4i16 (and store) 5674 {2, MVT::v4i16, 1}, // interleave 2 x 4i16 into 8i16 (and store) 5675 5676 {2, MVT::v2i32, 1}, // interleave 2 x 2i32 into 4i32 (and store) 5677 }; 5678 5679 if (Opcode == Instruction::Load) { 5680 auto GetDiscountedCost = [Factor, NumMembers = Indices.size(), 5681 MemOpCosts](const CostTblEntry *Entry) { 5682 // NOTE: this is just an approximation! 5683 // It can over/under -estimate the cost! 5684 return MemOpCosts + divideCeil(NumMembers * Entry->Cost, Factor); 5685 }; 5686 5687 if (ST->hasAVX2()) 5688 if (const auto *Entry = CostTableLookup(AVX2InterleavedLoadTbl, Factor, 5689 ETy.getSimpleVT())) 5690 return GetDiscountedCost(Entry); 5691 5692 if (ST->hasSSSE3()) 5693 if (const auto *Entry = CostTableLookup(SSSE3InterleavedLoadTbl, Factor, 5694 ETy.getSimpleVT())) 5695 return GetDiscountedCost(Entry); 5696 5697 if (ST->hasSSE2()) 5698 if (const auto *Entry = CostTableLookup(SSE2InterleavedLoadTbl, Factor, 5699 ETy.getSimpleVT())) 5700 return GetDiscountedCost(Entry); 5701 } else { 5702 assert(Opcode == Instruction::Store && 5703 "Expected Store Instruction at this point"); 5704 assert((!Indices.size() || Indices.size() == Factor) && 5705 "Interleaved store only supports fully-interleaved groups."); 5706 if (ST->hasAVX2()) 5707 if (const auto *Entry = CostTableLookup(AVX2InterleavedStoreTbl, Factor, 5708 ETy.getSimpleVT())) 5709 return MemOpCosts + Entry->Cost; 5710 5711 if (ST->hasSSE2()) 5712 if (const auto *Entry = CostTableLookup(SSE2InterleavedStoreTbl, Factor, 5713 ETy.getSimpleVT())) 5714 return MemOpCosts + Entry->Cost; 5715 } 5716 5717 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5718 Alignment, AddressSpace, CostKind, 5719 UseMaskForCond, UseMaskForGaps); 5720 } 5721