1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // X86 cost model. 56 // 57 //===----------------------------------------------------------------------===// 58 59 TargetTransformInfo::PopcntSupportKind 60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 61 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 62 // TODO: Currently the __builtin_popcount() implementation using SSE3 63 // instructions is inefficient. Once the problem is fixed, we should 64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 66 } 67 68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 69 TargetTransformInfo::CacheLevel Level) const { 70 switch (Level) { 71 case TargetTransformInfo::CacheLevel::L1D: 72 // - Penryn 73 // - Nehalem 74 // - Westmere 75 // - Sandy Bridge 76 // - Ivy Bridge 77 // - Haswell 78 // - Broadwell 79 // - Skylake 80 // - Kabylake 81 return 32 * 1024; // 32 KByte 82 case TargetTransformInfo::CacheLevel::L2D: 83 // - Penryn 84 // - Nehalem 85 // - Westmere 86 // - Sandy Bridge 87 // - Ivy Bridge 88 // - Haswell 89 // - Broadwell 90 // - Skylake 91 // - Kabylake 92 return 256 * 1024; // 256 KByte 93 } 94 95 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 96 } 97 98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 99 TargetTransformInfo::CacheLevel Level) const { 100 // - Penryn 101 // - Nehalem 102 // - Westmere 103 // - Sandy Bridge 104 // - Ivy Bridge 105 // - Haswell 106 // - Broadwell 107 // - Skylake 108 // - Kabylake 109 switch (Level) { 110 case TargetTransformInfo::CacheLevel::L1D: 111 LLVM_FALLTHROUGH; 112 case TargetTransformInfo::CacheLevel::L2D: 113 return 8; 114 } 115 116 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 117 } 118 119 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 120 bool Vector = (ClassID == 1); 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 TypeSize 133 X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { 134 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 135 switch (K) { 136 case TargetTransformInfo::RGK_Scalar: 137 return TypeSize::getFixed(ST->is64Bit() ? 64 : 32); 138 case TargetTransformInfo::RGK_FixedWidthVector: 139 if (ST->hasAVX512() && PreferVectorWidth >= 512) 140 return TypeSize::getFixed(512); 141 if (ST->hasAVX() && PreferVectorWidth >= 256) 142 return TypeSize::getFixed(256); 143 if (ST->hasSSE1() && PreferVectorWidth >= 128) 144 return TypeSize::getFixed(128); 145 return TypeSize::getFixed(0); 146 case TargetTransformInfo::RGK_ScalableVector: 147 return TypeSize::getScalable(0); 148 } 149 150 llvm_unreachable("Unsupported register kind"); 151 } 152 153 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 154 return getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector) 155 .getFixedSize(); 156 } 157 158 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 159 // If the loop will not be vectorized, don't interleave the loop. 160 // Let regular unroll to unroll the loop, which saves the overflow 161 // check and memory check cost. 162 if (VF == 1) 163 return 1; 164 165 if (ST->isAtom()) 166 return 1; 167 168 // Sandybridge and Haswell have multiple execution ports and pipelined 169 // vector units. 170 if (ST->hasAVX()) 171 return 4; 172 173 return 2; 174 } 175 176 InstructionCost X86TTIImpl::getArithmeticInstrCost( 177 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, 178 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 179 TTI::OperandValueProperties Opd1PropInfo, 180 TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, 181 const Instruction *CxtI) { 182 // TODO: Handle more cost kinds. 183 if (CostKind != TTI::TCK_RecipThroughput) 184 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, 185 Op2Info, Opd1PropInfo, 186 Opd2PropInfo, Args, CxtI); 187 // Legalize the type. 188 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 189 190 int ISD = TLI->InstructionOpcodeToISD(Opcode); 191 assert(ISD && "Invalid opcode"); 192 193 static const CostTblEntry GLMCostTable[] = { 194 { ISD::FDIV, MVT::f32, 18 }, // divss 195 { ISD::FDIV, MVT::v4f32, 35 }, // divps 196 { ISD::FDIV, MVT::f64, 33 }, // divsd 197 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 198 }; 199 200 if (ST->useGLMDivSqrtCosts()) 201 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 202 LT.second)) 203 return LT.first * Entry->Cost; 204 205 static const CostTblEntry SLMCostTable[] = { 206 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 207 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 208 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. 209 { ISD::FMUL, MVT::f64, 2 }, // mulsd 210 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 211 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 212 { ISD::FDIV, MVT::f32, 17 }, // divss 213 { ISD::FDIV, MVT::v4f32, 39 }, // divps 214 { ISD::FDIV, MVT::f64, 32 }, // divsd 215 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 216 { ISD::FADD, MVT::v2f64, 2 }, // addpd 217 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 218 // v2i64/v4i64 mul is custom lowered as a series of long: 219 // multiplies(3), shifts(3) and adds(2) 220 // slm muldq version throughput is 2 and addq throughput 4 221 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 222 // 3X4 (addq throughput) = 17 223 { ISD::MUL, MVT::v2i64, 17 }, 224 // slm addq\subq throughput is 4 225 { ISD::ADD, MVT::v2i64, 4 }, 226 { ISD::SUB, MVT::v2i64, 4 }, 227 }; 228 229 if (ST->isSLM()) { 230 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 231 // Check if the operands can be shrinked into a smaller datatype. 232 bool Op1Signed = false; 233 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 234 bool Op2Signed = false; 235 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 236 237 bool SignedMode = Op1Signed || Op2Signed; 238 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 239 240 if (OpMinSize <= 7) 241 return LT.first * 3; // pmullw/sext 242 if (!SignedMode && OpMinSize <= 8) 243 return LT.first * 3; // pmullw/zext 244 if (OpMinSize <= 15) 245 return LT.first * 5; // pmullw/pmulhw/pshuf 246 if (!SignedMode && OpMinSize <= 16) 247 return LT.first * 5; // pmullw/pmulhw/pshuf 248 } 249 250 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 251 LT.second)) { 252 return LT.first * Entry->Cost; 253 } 254 } 255 256 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 257 ISD == ISD::UREM) && 258 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 259 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 260 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 261 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 262 // On X86, vector signed division by constants power-of-two are 263 // normally expanded to the sequence SRA + SRL + ADD + SRA. 264 // The OperandValue properties may not be the same as that of the previous 265 // operation; conservatively assume OP_None. 266 InstructionCost Cost = 267 2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Op1Info, 268 Op2Info, TargetTransformInfo::OP_None, 269 TargetTransformInfo::OP_None); 270 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 271 Op2Info, 272 TargetTransformInfo::OP_None, 273 TargetTransformInfo::OP_None); 274 Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind, Op1Info, 275 Op2Info, 276 TargetTransformInfo::OP_None, 277 TargetTransformInfo::OP_None); 278 279 if (ISD == ISD::SREM) { 280 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 281 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info, 282 Op2Info); 283 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info, 284 Op2Info); 285 } 286 287 return Cost; 288 } 289 290 // Vector unsigned division/remainder will be simplified to shifts/masks. 291 if (ISD == ISD::UDIV) 292 return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, 293 Op1Info, Op2Info, 294 TargetTransformInfo::OP_None, 295 TargetTransformInfo::OP_None); 296 297 else // UREM 298 return getArithmeticInstrCost(Instruction::And, Ty, CostKind, 299 Op1Info, Op2Info, 300 TargetTransformInfo::OP_None, 301 TargetTransformInfo::OP_None); 302 } 303 304 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 305 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 306 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 307 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 308 }; 309 310 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 311 ST->hasBWI()) { 312 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 313 LT.second)) 314 return LT.first * Entry->Cost; 315 } 316 317 static const CostTblEntry AVX512UniformConstCostTable[] = { 318 { ISD::SRA, MVT::v2i64, 1 }, 319 { ISD::SRA, MVT::v4i64, 1 }, 320 { ISD::SRA, MVT::v8i64, 1 }, 321 322 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 323 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 324 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 325 326 { ISD::SDIV, MVT::v16i32, 6 }, // pmuludq sequence 327 { ISD::SREM, MVT::v16i32, 8 }, // pmuludq+mul+sub sequence 328 { ISD::UDIV, MVT::v16i32, 5 }, // pmuludq sequence 329 { ISD::UREM, MVT::v16i32, 7 }, // pmuludq+mul+sub sequence 330 }; 331 332 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 333 ST->hasAVX512()) { 334 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 335 LT.second)) 336 return LT.first * Entry->Cost; 337 } 338 339 static const CostTblEntry AVX2UniformConstCostTable[] = { 340 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 341 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 342 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 343 344 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 345 346 { ISD::SDIV, MVT::v8i32, 6 }, // pmuludq sequence 347 { ISD::SREM, MVT::v8i32, 8 }, // pmuludq+mul+sub sequence 348 { ISD::UDIV, MVT::v8i32, 5 }, // pmuludq sequence 349 { ISD::UREM, MVT::v8i32, 7 }, // pmuludq+mul+sub sequence 350 }; 351 352 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 353 ST->hasAVX2()) { 354 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 355 LT.second)) 356 return LT.first * Entry->Cost; 357 } 358 359 static const CostTblEntry SSE2UniformConstCostTable[] = { 360 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 361 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 362 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 363 364 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 365 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 366 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 367 368 { ISD::SDIV, MVT::v8i32, 12+2 }, // 2*pmuludq sequence + split. 369 { ISD::SREM, MVT::v8i32, 16+2 }, // 2*pmuludq+mul+sub sequence + split. 370 { ISD::SDIV, MVT::v4i32, 6 }, // pmuludq sequence 371 { ISD::SREM, MVT::v4i32, 8 }, // pmuludq+mul+sub sequence 372 { ISD::UDIV, MVT::v8i32, 10+2 }, // 2*pmuludq sequence + split. 373 { ISD::UREM, MVT::v8i32, 14+2 }, // 2*pmuludq+mul+sub sequence + split. 374 { ISD::UDIV, MVT::v4i32, 5 }, // pmuludq sequence 375 { ISD::UREM, MVT::v4i32, 7 }, // pmuludq+mul+sub sequence 376 }; 377 378 // XOP has faster vXi8 shifts. 379 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 380 ST->hasSSE2() && !ST->hasXOP()) { 381 if (const auto *Entry = 382 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 383 return LT.first * Entry->Cost; 384 } 385 386 static const CostTblEntry AVX512BWConstCostTable[] = { 387 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 388 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 389 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 390 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 391 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 392 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 393 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 394 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 395 }; 396 397 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 398 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 399 ST->hasBWI()) { 400 if (const auto *Entry = 401 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 402 return LT.first * Entry->Cost; 403 } 404 405 static const CostTblEntry AVX512ConstCostTable[] = { 406 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 407 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 408 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 409 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 410 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 411 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 412 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 413 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 414 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 415 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 416 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 417 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 418 }; 419 420 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 421 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 422 ST->hasAVX512()) { 423 if (const auto *Entry = 424 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 425 return LT.first * Entry->Cost; 426 } 427 428 static const CostTblEntry AVX2ConstCostTable[] = { 429 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 430 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 431 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 432 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 433 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 434 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 435 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 436 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 437 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 438 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 439 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 440 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 441 }; 442 443 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 444 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 445 ST->hasAVX2()) { 446 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 447 return LT.first * Entry->Cost; 448 } 449 450 static const CostTblEntry SSE2ConstCostTable[] = { 451 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 452 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 453 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 454 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 455 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 456 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 457 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 458 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 459 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 460 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 461 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 462 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 463 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 464 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 465 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 466 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 467 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 468 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 469 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 470 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 471 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 472 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 473 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 474 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 475 }; 476 477 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 478 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 479 ST->hasSSE2()) { 480 // pmuldq sequence. 481 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 482 return LT.first * 32; 483 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 484 return LT.first * 38; 485 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 486 return LT.first * 15; 487 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 488 return LT.first * 20; 489 490 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 491 return LT.first * Entry->Cost; 492 } 493 494 static const CostTblEntry AVX512BWShiftCostTable[] = { 495 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 496 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 497 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 498 499 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 500 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 501 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 502 503 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 504 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 505 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 506 }; 507 508 if (ST->hasBWI()) 509 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 510 return LT.first * Entry->Cost; 511 512 static const CostTblEntry AVX2UniformCostTable[] = { 513 // Uniform splats are cheaper for the following instructions. 514 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 515 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 516 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 517 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 518 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 519 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 520 521 { ISD::SHL, MVT::v8i32, 1 }, // pslld 522 { ISD::SRL, MVT::v8i32, 1 }, // psrld 523 { ISD::SRA, MVT::v8i32, 1 }, // psrad 524 { ISD::SHL, MVT::v4i64, 1 }, // psllq 525 { ISD::SRL, MVT::v4i64, 1 }, // psrlq 526 }; 527 528 if (ST->hasAVX2() && 529 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 530 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 531 if (const auto *Entry = 532 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 533 return LT.first * Entry->Cost; 534 } 535 536 static const CostTblEntry SSE2UniformCostTable[] = { 537 // Uniform splats are cheaper for the following instructions. 538 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 539 { ISD::SHL, MVT::v4i32, 1 }, // pslld 540 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 541 542 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 543 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 544 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 545 546 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 547 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 548 }; 549 550 if (ST->hasSSE2() && 551 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 552 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 553 if (const auto *Entry = 554 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 555 return LT.first * Entry->Cost; 556 } 557 558 static const CostTblEntry AVX512DQCostTable[] = { 559 { ISD::MUL, MVT::v2i64, 1 }, 560 { ISD::MUL, MVT::v4i64, 1 }, 561 { ISD::MUL, MVT::v8i64, 1 } 562 }; 563 564 // Look for AVX512DQ lowering tricks for custom cases. 565 if (ST->hasDQI()) 566 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 567 return LT.first * Entry->Cost; 568 569 static const CostTblEntry AVX512BWCostTable[] = { 570 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 571 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 572 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 573 574 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence. 575 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence. 576 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence. 577 }; 578 579 // Look for AVX512BW lowering tricks for custom cases. 580 if (ST->hasBWI()) 581 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 582 return LT.first * Entry->Cost; 583 584 static const CostTblEntry AVX512CostTable[] = { 585 { ISD::SHL, MVT::v8i32, 1 }, 586 { ISD::SRL, MVT::v8i32, 1 }, 587 { ISD::SRA, MVT::v8i32, 1 }, 588 { ISD::SHL, MVT::v16i32, 1 }, 589 { ISD::SRL, MVT::v16i32, 1 }, 590 { ISD::SRA, MVT::v16i32, 1 }, 591 592 { ISD::SHL, MVT::v4i64, 1 }, 593 { ISD::SRL, MVT::v4i64, 1 }, 594 { ISD::SHL, MVT::v8i64, 1 }, 595 { ISD::SRL, MVT::v8i64, 1 }, 596 597 { ISD::SRA, MVT::v2i64, 1 }, 598 { ISD::SRA, MVT::v4i64, 1 }, 599 { ISD::SRA, MVT::v8i64, 1 }, 600 601 { ISD::MUL, MVT::v64i8, 26 }, // extend/pmullw/trunc sequence. 602 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence. 603 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence. 604 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 605 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 606 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 607 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add 608 609 { ISD::FNEG, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 610 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 611 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 612 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 613 614 { ISD::FNEG, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 615 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 616 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 617 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 618 }; 619 620 if (ST->hasAVX512()) 621 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 622 return LT.first * Entry->Cost; 623 624 static const CostTblEntry AVX2ShiftCostTable[] = { 625 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 626 // customize them to detect the cases where shift amount is a scalar one. 627 { ISD::SHL, MVT::v4i32, 1 }, 628 { ISD::SRL, MVT::v4i32, 1 }, 629 { ISD::SRA, MVT::v4i32, 1 }, 630 { ISD::SHL, MVT::v8i32, 2 }, // vpsllvd (Haswell from agner.org) 631 { ISD::SRL, MVT::v8i32, 2 }, // vpsrlvd (Haswell from agner.org) 632 { ISD::SRA, MVT::v8i32, 2 }, // vpsravd (Haswell from agner.org) 633 { ISD::SHL, MVT::v2i64, 1 }, 634 { ISD::SRL, MVT::v2i64, 1 }, 635 { ISD::SHL, MVT::v4i64, 2 }, // vpsllvq (Haswell from agner.org) 636 { ISD::SRL, MVT::v4i64, 2 }, // vpsrlvq (Haswell from agner.org) 637 }; 638 639 if (ST->hasAVX512()) { 640 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 641 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 642 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 643 // On AVX512, a packed v32i16 shift left by a constant build_vector 644 // is lowered into a vector multiply (vpmullw). 645 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 646 Op1Info, Op2Info, 647 TargetTransformInfo::OP_None, 648 TargetTransformInfo::OP_None); 649 } 650 651 // Look for AVX2 lowering tricks. 652 if (ST->hasAVX2()) { 653 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 654 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 655 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 656 // On AVX2, a packed v16i16 shift left by a constant build_vector 657 // is lowered into a vector multiply (vpmullw). 658 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 659 Op1Info, Op2Info, 660 TargetTransformInfo::OP_None, 661 TargetTransformInfo::OP_None); 662 663 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 664 return LT.first * Entry->Cost; 665 } 666 667 static const CostTblEntry XOPShiftCostTable[] = { 668 // 128bit shifts take 1cy, but right shifts require negation beforehand. 669 { ISD::SHL, MVT::v16i8, 1 }, 670 { ISD::SRL, MVT::v16i8, 2 }, 671 { ISD::SRA, MVT::v16i8, 2 }, 672 { ISD::SHL, MVT::v8i16, 1 }, 673 { ISD::SRL, MVT::v8i16, 2 }, 674 { ISD::SRA, MVT::v8i16, 2 }, 675 { ISD::SHL, MVT::v4i32, 1 }, 676 { ISD::SRL, MVT::v4i32, 2 }, 677 { ISD::SRA, MVT::v4i32, 2 }, 678 { ISD::SHL, MVT::v2i64, 1 }, 679 { ISD::SRL, MVT::v2i64, 2 }, 680 { ISD::SRA, MVT::v2i64, 2 }, 681 // 256bit shifts require splitting if AVX2 didn't catch them above. 682 { ISD::SHL, MVT::v32i8, 2+2 }, 683 { ISD::SRL, MVT::v32i8, 4+2 }, 684 { ISD::SRA, MVT::v32i8, 4+2 }, 685 { ISD::SHL, MVT::v16i16, 2+2 }, 686 { ISD::SRL, MVT::v16i16, 4+2 }, 687 { ISD::SRA, MVT::v16i16, 4+2 }, 688 { ISD::SHL, MVT::v8i32, 2+2 }, 689 { ISD::SRL, MVT::v8i32, 4+2 }, 690 { ISD::SRA, MVT::v8i32, 4+2 }, 691 { ISD::SHL, MVT::v4i64, 2+2 }, 692 { ISD::SRL, MVT::v4i64, 4+2 }, 693 { ISD::SRA, MVT::v4i64, 4+2 }, 694 }; 695 696 // Look for XOP lowering tricks. 697 if (ST->hasXOP()) { 698 // If the right shift is constant then we'll fold the negation so 699 // it's as cheap as a left shift. 700 int ShiftISD = ISD; 701 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 702 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 703 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 704 ShiftISD = ISD::SHL; 705 if (const auto *Entry = 706 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 707 return LT.first * Entry->Cost; 708 } 709 710 static const CostTblEntry SSE2UniformShiftCostTable[] = { 711 // Uniform splats are cheaper for the following instructions. 712 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 713 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 714 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 715 716 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 717 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 718 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 719 720 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 721 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 722 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 723 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 724 }; 725 726 if (ST->hasSSE2() && 727 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 728 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 729 730 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 731 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 732 return LT.first * 4; // 2*psrad + shuffle. 733 734 if (const auto *Entry = 735 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 736 return LT.first * Entry->Cost; 737 } 738 739 if (ISD == ISD::SHL && 740 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 741 MVT VT = LT.second; 742 // Vector shift left by non uniform constant can be lowered 743 // into vector multiply. 744 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 745 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 746 ISD = ISD::MUL; 747 } 748 749 static const CostTblEntry AVX2CostTable[] = { 750 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. 751 { ISD::SHL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. 752 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 753 { ISD::SHL, MVT::v32i16, 20 }, // 2*extend/vpsrlvd/pack sequence. 754 755 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. 756 { ISD::SRL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. 757 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 758 { ISD::SRL, MVT::v32i16, 20 }, // 2*extend/vpsrlvd/pack sequence. 759 760 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. 761 { ISD::SRA, MVT::v64i8, 48 }, // 2*vpblendvb sequence. 762 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. 763 { ISD::SRA, MVT::v32i16, 20 }, // 2*extend/vpsravd/pack sequence. 764 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. 765 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 766 767 { ISD::SUB, MVT::v32i8, 1 }, // psubb 768 { ISD::ADD, MVT::v32i8, 1 }, // paddb 769 { ISD::SUB, MVT::v16i16, 1 }, // psubw 770 { ISD::ADD, MVT::v16i16, 1 }, // paddw 771 { ISD::SUB, MVT::v8i32, 1 }, // psubd 772 { ISD::ADD, MVT::v8i32, 1 }, // paddd 773 { ISD::SUB, MVT::v4i64, 1 }, // psubq 774 { ISD::ADD, MVT::v4i64, 1 }, // paddq 775 776 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence. 777 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence. 778 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 779 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 780 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add 781 782 { ISD::FNEG, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 783 { ISD::FNEG, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 784 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 785 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 786 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 787 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 788 { ISD::FMUL, MVT::f64, 1 }, // Haswell from http://www.agner.org/ 789 { ISD::FMUL, MVT::v2f64, 1 }, // Haswell from http://www.agner.org/ 790 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 791 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 792 793 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 794 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 795 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 796 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 797 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 798 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 799 }; 800 801 // Look for AVX2 lowering tricks for custom cases. 802 if (ST->hasAVX2()) 803 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 804 return LT.first * Entry->Cost; 805 806 static const CostTblEntry AVX1CostTable[] = { 807 // We don't have to scalarize unsupported ops. We can issue two half-sized 808 // operations and we only need to extract the upper YMM half. 809 // Two ops + 1 extract + 1 insert = 4. 810 { ISD::MUL, MVT::v16i16, 4 }, 811 { ISD::MUL, MVT::v8i32, 5 }, // BTVER2 from http://www.agner.org/ 812 { ISD::SUB, MVT::v32i8, 4 }, 813 { ISD::ADD, MVT::v32i8, 4 }, 814 { ISD::SUB, MVT::v16i16, 4 }, 815 { ISD::ADD, MVT::v16i16, 4 }, 816 { ISD::SUB, MVT::v8i32, 4 }, 817 { ISD::ADD, MVT::v8i32, 4 }, 818 { ISD::SUB, MVT::v4i64, 4 }, 819 { ISD::ADD, MVT::v4i64, 4 }, 820 821 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 822 // are lowered as a series of long multiplies(3), shifts(3) and adds(2) 823 // Because we believe v4i64 to be a legal type, we must also include the 824 // extract+insert in the cost table. Therefore, the cost here is 18 825 // instead of 8. 826 { ISD::MUL, MVT::v4i64, 18 }, 827 828 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence. 829 830 { ISD::FNEG, MVT::v4f64, 2 }, // BTVER2 from http://www.agner.org/ 831 { ISD::FNEG, MVT::v8f32, 2 }, // BTVER2 from http://www.agner.org/ 832 833 { ISD::FMUL, MVT::f64, 2 }, // BTVER2 from http://www.agner.org/ 834 { ISD::FMUL, MVT::v2f64, 2 }, // BTVER2 from http://www.agner.org/ 835 { ISD::FMUL, MVT::v4f64, 4 }, // BTVER2 from http://www.agner.org/ 836 837 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 838 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 839 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 840 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 841 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 842 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 843 }; 844 845 if (ST->hasAVX()) 846 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 847 return LT.first * Entry->Cost; 848 849 static const CostTblEntry SSE42CostTable[] = { 850 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 851 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 852 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 853 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 854 855 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 856 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 857 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 858 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 859 860 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 861 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 862 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 863 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 864 865 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 866 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 867 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 868 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 869 }; 870 871 if (ST->hasSSE42()) 872 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 873 return LT.first * Entry->Cost; 874 875 static const CostTblEntry SSE41CostTable[] = { 876 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 877 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split. 878 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 879 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 880 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 881 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split 882 883 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 884 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split. 885 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 886 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 887 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 888 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split. 889 890 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 891 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split. 892 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 893 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 894 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 895 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split. 896 897 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 898 }; 899 900 if (ST->hasSSE41()) 901 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 902 return LT.first * Entry->Cost; 903 904 static const CostTblEntry SSE2CostTable[] = { 905 // We don't correctly identify costs of casts because they are marked as 906 // custom. 907 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 908 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 909 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 910 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 911 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 912 913 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 914 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 915 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 916 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 917 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 918 919 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 920 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 921 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 922 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 923 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split. 924 925 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence. 926 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 927 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 928 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 929 930 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 931 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 932 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 933 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 934 935 { ISD::FNEG, MVT::f32, 1 }, // Pentium IV from http://www.agner.org/ 936 { ISD::FNEG, MVT::f64, 1 }, // Pentium IV from http://www.agner.org/ 937 { ISD::FNEG, MVT::v4f32, 1 }, // Pentium IV from http://www.agner.org/ 938 { ISD::FNEG, MVT::v2f64, 1 }, // Pentium IV from http://www.agner.org/ 939 940 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 941 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 942 943 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 944 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 945 }; 946 947 if (ST->hasSSE2()) 948 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 949 return LT.first * Entry->Cost; 950 951 static const CostTblEntry SSE1CostTable[] = { 952 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 953 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 954 955 { ISD::FNEG, MVT::f32, 2 }, // Pentium III from http://www.agner.org/ 956 { ISD::FNEG, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 957 958 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 959 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 960 961 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 962 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 963 964 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 965 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 966 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 967 968 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 969 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 970 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 971 }; 972 973 if (ST->hasSSE1()) 974 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 975 return LT.first * Entry->Cost; 976 977 // It is not a good idea to vectorize division. We have to scalarize it and 978 // in the process we will often end up having to spilling regular 979 // registers. The overhead of division is going to dominate most kernels 980 // anyways so try hard to prevent vectorization of division - it is 981 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 982 // to hide "20 cycles" for each lane. 983 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 984 ISD == ISD::UDIV || ISD == ISD::UREM)) { 985 InstructionCost ScalarCost = getArithmeticInstrCost( 986 Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info, 987 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 988 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 989 } 990 991 // Fallback to the default implementation. 992 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info); 993 } 994 995 InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, 996 VectorType *BaseTp, 997 ArrayRef<int> Mask, int Index, 998 VectorType *SubTp) { 999 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 1000 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 1001 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 1002 1003 Kind = improveShuffleKindFromMask(Kind, Mask); 1004 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 1005 if (Kind == TTI::SK_Transpose) 1006 Kind = TTI::SK_PermuteTwoSrc; 1007 1008 // For Broadcasts we are splatting the first element from the first input 1009 // register, so only need to reference that input and all the output 1010 // registers are the same. 1011 if (Kind == TTI::SK_Broadcast) 1012 LT.first = 1; 1013 1014 // Subvector extractions are free if they start at the beginning of a 1015 // vector and cheap if the subvectors are aligned. 1016 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 1017 int NumElts = LT.second.getVectorNumElements(); 1018 if ((Index % NumElts) == 0) 1019 return 0; 1020 std::pair<InstructionCost, MVT> SubLT = 1021 TLI->getTypeLegalizationCost(DL, SubTp); 1022 if (SubLT.second.isVector()) { 1023 int NumSubElts = SubLT.second.getVectorNumElements(); 1024 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1025 return SubLT.first; 1026 // Handle some cases for widening legalization. For now we only handle 1027 // cases where the original subvector was naturally aligned and evenly 1028 // fit in its legalized subvector type. 1029 // FIXME: Remove some of the alignment restrictions. 1030 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 1031 // vectors. 1032 int OrigSubElts = cast<FixedVectorType>(SubTp)->getNumElements(); 1033 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 1034 (NumSubElts % OrigSubElts) == 0 && 1035 LT.second.getVectorElementType() == 1036 SubLT.second.getVectorElementType() && 1037 LT.second.getVectorElementType().getSizeInBits() == 1038 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 1039 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 1040 "Unexpected number of elements!"); 1041 auto *VecTy = FixedVectorType::get(BaseTp->getElementType(), 1042 LT.second.getVectorNumElements()); 1043 auto *SubTy = FixedVectorType::get(BaseTp->getElementType(), 1044 SubLT.second.getVectorNumElements()); 1045 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 1046 InstructionCost ExtractCost = getShuffleCost( 1047 TTI::SK_ExtractSubvector, VecTy, None, ExtractIndex, SubTy); 1048 1049 // If the original size is 32-bits or more, we can use pshufd. Otherwise 1050 // if we have SSSE3 we can use pshufb. 1051 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 1052 return ExtractCost + 1; // pshufd or pshufb 1053 1054 assert(SubTp->getPrimitiveSizeInBits() == 16 && 1055 "Unexpected vector size"); 1056 1057 return ExtractCost + 2; // worst case pshufhw + pshufd 1058 } 1059 } 1060 } 1061 1062 // Subvector insertions are cheap if the subvectors are aligned. 1063 // Note that in general, the insertion starting at the beginning of a vector 1064 // isn't free, because we need to preserve the rest of the wide vector. 1065 if (Kind == TTI::SK_InsertSubvector && LT.second.isVector()) { 1066 int NumElts = LT.second.getVectorNumElements(); 1067 std::pair<InstructionCost, MVT> SubLT = 1068 TLI->getTypeLegalizationCost(DL, SubTp); 1069 if (SubLT.second.isVector()) { 1070 int NumSubElts = SubLT.second.getVectorNumElements(); 1071 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1072 return SubLT.first; 1073 } 1074 } 1075 1076 // Handle some common (illegal) sub-vector types as they are often very cheap 1077 // to shuffle even on targets without PSHUFB. 1078 EVT VT = TLI->getValueType(DL, BaseTp); 1079 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 1080 !ST->hasSSSE3()) { 1081 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 1082 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 1083 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1084 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1085 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1086 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1087 1088 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1089 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1090 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1091 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1092 1093 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1094 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1095 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1096 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1097 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1098 1099 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1100 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1101 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1102 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1103 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1104 }; 1105 1106 if (ST->hasSSE2()) 1107 if (const auto *Entry = 1108 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1109 return Entry->Cost; 1110 } 1111 1112 // We are going to permute multiple sources and the result will be in multiple 1113 // destinations. Providing an accurate cost only for splits where the element 1114 // type remains the same. 1115 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1116 MVT LegalVT = LT.second; 1117 if (LegalVT.isVector() && 1118 LegalVT.getVectorElementType().getSizeInBits() == 1119 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1120 LegalVT.getVectorNumElements() < 1121 cast<FixedVectorType>(BaseTp)->getNumElements()) { 1122 1123 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1124 unsigned LegalVTSize = LegalVT.getStoreSize(); 1125 // Number of source vectors after legalization: 1126 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1127 // Number of destination vectors after legalization: 1128 InstructionCost NumOfDests = LT.first; 1129 1130 auto *SingleOpTy = FixedVectorType::get(BaseTp->getElementType(), 1131 LegalVT.getVectorNumElements()); 1132 1133 InstructionCost NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1134 return NumOfShuffles * getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 1135 None, 0, nullptr); 1136 } 1137 1138 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1139 } 1140 1141 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1142 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1143 // We assume that source and destination have the same vector type. 1144 InstructionCost NumOfDests = LT.first; 1145 InstructionCost NumOfShufflesPerDest = LT.first * 2 - 1; 1146 LT.first = NumOfDests * NumOfShufflesPerDest; 1147 } 1148 1149 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1150 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1151 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1152 1153 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1154 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1155 1156 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b 1157 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b 1158 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2} // vpermt2b 1159 }; 1160 1161 if (ST->hasVBMI()) 1162 if (const auto *Entry = 1163 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1164 return LT.first * Entry->Cost; 1165 1166 static const CostTblEntry AVX512BWShuffleTbl[] = { 1167 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1168 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1169 1170 {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw 1171 {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw 1172 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1173 1174 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw 1175 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw 1176 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1177 1178 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w 1179 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w 1180 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2}, // vpermt2w 1181 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1182 1183 {TTI::SK_Select, MVT::v32i16, 1}, // vblendmw 1184 {TTI::SK_Select, MVT::v64i8, 1}, // vblendmb 1185 }; 1186 1187 if (ST->hasBWI()) 1188 if (const auto *Entry = 1189 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1190 return LT.first * Entry->Cost; 1191 1192 static const CostTblEntry AVX512ShuffleTbl[] = { 1193 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1194 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1195 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1196 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1197 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1198 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1199 1200 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1201 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1202 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1203 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1204 {TTI::SK_Reverse, MVT::v32i16, 7}, // per mca 1205 {TTI::SK_Reverse, MVT::v64i8, 7}, // per mca 1206 1207 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1208 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1209 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1210 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1211 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1212 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1213 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1214 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1215 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1216 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1217 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1218 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1219 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1220 1221 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1222 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1223 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1224 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1225 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1226 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1227 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1228 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1229 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1230 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1231 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1232 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1233 1234 // FIXME: This just applies the type legalization cost rules above 1235 // assuming these completely split. 1236 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1237 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1238 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1239 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1240 1241 {TTI::SK_Select, MVT::v32i16, 1}, // vpternlogq 1242 {TTI::SK_Select, MVT::v64i8, 1}, // vpternlogq 1243 {TTI::SK_Select, MVT::v8f64, 1}, // vblendmpd 1244 {TTI::SK_Select, MVT::v16f32, 1}, // vblendmps 1245 {TTI::SK_Select, MVT::v8i64, 1}, // vblendmq 1246 {TTI::SK_Select, MVT::v16i32, 1}, // vblendmd 1247 }; 1248 1249 if (ST->hasAVX512()) 1250 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1251 return LT.first * Entry->Cost; 1252 1253 static const CostTblEntry AVX2ShuffleTbl[] = { 1254 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1255 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1256 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1257 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1258 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1259 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1260 1261 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1262 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1263 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1264 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1265 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1266 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1267 1268 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1269 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1270 1271 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1272 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1273 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1274 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1275 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1276 // + vpblendvb 1277 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1278 // + vpblendvb 1279 1280 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1281 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1282 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1283 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1284 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1285 // + vpblendvb 1286 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1287 // + vpblendvb 1288 }; 1289 1290 if (ST->hasAVX2()) 1291 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1292 return LT.first * Entry->Cost; 1293 1294 static const CostTblEntry XOPShuffleTbl[] = { 1295 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1296 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1297 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1298 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1299 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1300 // + vinsertf128 1301 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1302 // + vinsertf128 1303 1304 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1305 // + vinsertf128 1306 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1307 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1308 // + vinsertf128 1309 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1310 }; 1311 1312 if (ST->hasXOP()) 1313 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1314 return LT.first * Entry->Cost; 1315 1316 static const CostTblEntry AVX1ShuffleTbl[] = { 1317 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1318 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1319 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1320 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1321 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1322 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1323 1324 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1325 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1326 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1327 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1328 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1329 // + vinsertf128 1330 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1331 // + vinsertf128 1332 1333 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1334 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1335 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1336 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1337 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1338 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1339 1340 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1341 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1342 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1343 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1344 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1345 // + 2*por + vinsertf128 1346 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1347 // + 2*por + vinsertf128 1348 1349 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1350 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1351 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1352 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1353 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1354 // + 4*por + vinsertf128 1355 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1356 // + 4*por + vinsertf128 1357 }; 1358 1359 if (ST->hasAVX()) 1360 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1361 return LT.first * Entry->Cost; 1362 1363 static const CostTblEntry SSE41ShuffleTbl[] = { 1364 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1365 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1366 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1367 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1368 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1369 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1370 }; 1371 1372 if (ST->hasSSE41()) 1373 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1374 return LT.first * Entry->Cost; 1375 1376 static const CostTblEntry SSSE3ShuffleTbl[] = { 1377 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1378 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1379 1380 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1381 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1382 1383 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1384 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1385 1386 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1387 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1388 1389 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1390 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1391 }; 1392 1393 if (ST->hasSSSE3()) 1394 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1395 return LT.first * Entry->Cost; 1396 1397 static const CostTblEntry SSE2ShuffleTbl[] = { 1398 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1399 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1400 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1401 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1402 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1403 1404 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1405 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1406 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1407 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1408 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1409 // + 2*pshufd + 2*unpck + packus 1410 1411 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1412 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1413 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1414 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1415 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1416 1417 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1418 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1419 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1420 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1421 // + pshufd/unpck 1422 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1423 // + 2*pshufd + 2*unpck + 2*packus 1424 1425 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1426 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1427 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1428 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1429 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1430 }; 1431 1432 if (ST->hasSSE2()) 1433 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1434 return LT.first * Entry->Cost; 1435 1436 static const CostTblEntry SSE1ShuffleTbl[] = { 1437 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1438 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1439 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1440 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1441 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1442 }; 1443 1444 if (ST->hasSSE1()) 1445 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1446 return LT.first * Entry->Cost; 1447 1448 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1449 } 1450 1451 InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, 1452 Type *Src, 1453 TTI::CastContextHint CCH, 1454 TTI::TargetCostKind CostKind, 1455 const Instruction *I) { 1456 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1457 assert(ISD && "Invalid opcode"); 1458 1459 // TODO: Allow non-throughput costs that aren't binary. 1460 auto AdjustCost = [&CostKind](InstructionCost Cost) -> InstructionCost { 1461 if (CostKind != TTI::TCK_RecipThroughput) 1462 return Cost == 0 ? 0 : 1; 1463 return Cost; 1464 }; 1465 1466 // FIXME: Need a better design of the cost table to handle non-simple types of 1467 // potential massive combinations (elem_num x src_type x dst_type). 1468 1469 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1470 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1471 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1472 1473 // Mask sign extend has an instruction. 1474 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1475 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1476 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1477 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1478 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1479 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1480 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1481 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1482 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1483 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1484 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1485 1486 // Mask zero extend is a sext + shift. 1487 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1488 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1489 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1490 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1491 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1492 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1493 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1494 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1495 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1496 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1497 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1498 1499 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, 1500 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm 1501 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // widen to zmm 1502 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // widen to zmm 1503 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // widen to zmm 1504 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // widen to zmm 1505 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // widen to zmm 1506 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // widen to zmm 1507 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // widen to zmm 1508 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // widen to zmm 1509 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // widen to zmm 1510 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, 1511 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, 1512 }; 1513 1514 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1515 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1516 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1517 1518 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1519 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1520 1521 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1522 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1523 1524 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1525 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1526 }; 1527 1528 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1529 // 256-bit wide vectors. 1530 1531 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1532 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1533 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1534 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1535 1536 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1537 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1538 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1539 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd 1540 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1541 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1542 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1543 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd 1544 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd 1545 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd 1546 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd 1547 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd 1548 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq 1549 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq 1550 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq 1551 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, 1552 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, 1553 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, 1554 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, 1555 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 1556 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd 1557 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb 1558 1559 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32 1560 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, 1561 1562 // Sign extend is zmm vpternlogd+vptruncdb. 1563 // Zero extend is zmm broadcast load+vptruncdw. 1564 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 }, 1565 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 }, 1566 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, 1567 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, 1568 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, 1569 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, 1570 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 }, 1571 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 }, 1572 1573 // Sign extend is zmm vpternlogd+vptruncdw. 1574 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw. 1575 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 }, 1576 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1577 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 }, 1578 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1579 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 }, 1580 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1581 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 }, 1582 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1583 1584 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd 1585 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld 1586 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd 1587 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld 1588 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd 1589 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld 1590 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq 1591 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq 1592 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq 1593 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq 1594 1595 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd 1596 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld 1597 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq 1598 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq 1599 1600 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1601 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1602 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1603 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1604 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1605 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1606 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1607 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1608 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1609 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1610 1611 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1612 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1613 1614 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1615 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1616 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1617 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1618 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1619 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1620 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1621 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1622 1623 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1624 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1625 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1626 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1627 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1628 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1629 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1630 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1631 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1632 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1633 1634 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f64, 3 }, 1635 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, 1636 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 3 }, 1637 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 3 }, 1638 1639 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1640 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, 1641 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, 1642 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1643 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, 1644 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, 1645 }; 1646 1647 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1648 // Mask sign extend has an instruction. 1649 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1650 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1651 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1652 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1653 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1654 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1655 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1656 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1657 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1658 1659 // Mask zero extend is a sext + shift. 1660 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1661 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1662 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1663 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1664 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1665 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1666 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1667 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1668 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1669 1670 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, 1671 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // vpsllw+vptestmb 1672 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // vpsllw+vptestmw 1673 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // vpsllw+vptestmb 1674 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // vpsllw+vptestmw 1675 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // vpsllw+vptestmb 1676 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // vpsllw+vptestmw 1677 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // vpsllw+vptestmb 1678 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // vpsllw+vptestmw 1679 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // vpsllw+vptestmb 1680 }; 1681 1682 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1683 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1684 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1685 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1686 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1687 1688 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1689 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1690 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1691 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1692 1693 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1694 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1695 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1696 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1697 1698 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1699 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1700 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1701 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1702 }; 1703 1704 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 1705 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1706 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1707 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1708 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 8 }, // split+2*v8i8 1709 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1710 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1711 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1712 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16 1713 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // vpslld+vptestmd 1714 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd 1715 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // vpslld+vptestmd 1716 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // vpsllq+vptestmq 1717 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // vpsllq+vptestmq 1718 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // vpmovqd 1719 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, // vpmovqb 1720 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, // vpmovqw 1721 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, // vpmovwb 1722 1723 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb 1724 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb 1725 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 }, 1726 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 }, 1727 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 }, 1728 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 }, 1729 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 }, 1730 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 }, 1731 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 }, 1732 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 }, 1733 1734 // sign extend is vpcmpeq+maskedmove+vpmovdw 1735 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw 1736 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1737 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 }, 1738 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1739 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 }, 1740 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1741 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 }, 1742 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 }, 1743 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 }, 1744 1745 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd 1746 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld 1747 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd 1748 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld 1749 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd 1750 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld 1751 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq 1752 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq 1753 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq 1754 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq 1755 1756 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1757 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1758 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1759 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1760 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1761 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1762 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1763 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1764 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1765 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1766 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1767 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1768 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1769 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1770 1771 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 1772 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1773 1774 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 3 }, 1775 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 3 }, 1776 1777 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 1778 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 1779 1780 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1781 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1782 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 1 }, 1783 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1784 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1785 }; 1786 1787 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1788 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1789 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1790 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1791 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1792 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1793 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1794 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1795 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1796 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1797 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1798 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1799 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1800 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1801 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1802 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1803 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1804 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1805 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1806 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1807 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1808 1809 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1810 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1811 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1812 1813 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1814 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1815 1816 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 5 }, 1817 }; 1818 1819 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1820 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1821 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1822 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1823 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1824 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1825 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1826 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1827 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1828 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1829 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1830 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1831 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1832 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 4 }, 1833 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1834 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1835 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1836 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1837 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1838 1839 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 4 }, 1840 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 5 }, 1841 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 4 }, 1842 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 9 }, 1843 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, 11 }, 1844 1845 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 1846 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1847 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1848 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1849 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 1850 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1851 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 11 }, 1852 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 9 }, 1853 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 }, 1854 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 11 }, 1855 1856 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1857 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1858 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1859 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1860 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1861 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1862 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1863 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1864 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1865 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1866 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1867 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1868 1869 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1870 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1871 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1872 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1873 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1874 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1875 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1876 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1877 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1878 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 }, 1879 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 1880 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1881 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1882 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1883 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1884 // The generic code to compute the scalar overhead is currently broken. 1885 // Workaround this limitation by estimating the scalarization overhead 1886 // here. We have roughly 10 instructions per scalar element. 1887 // Multiply that by the vector width. 1888 // FIXME: remove that when PR19268 is fixed. 1889 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1890 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1891 1892 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 4 }, 1893 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f64, 3 }, 1894 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f64, 2 }, 1895 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 3 }, 1896 1897 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f64, 3 }, 1898 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f64, 2 }, 1899 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 4 }, 1900 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 3 }, 1901 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 9 }, 1902 // This node is expanded into scalarized operations but BasicTTI is overly 1903 // optimistic estimating its cost. It computes 3 per element (one 1904 // vector-extract, one scalar conversion and one vector-insert). The 1905 // problem is that the inserts form a read-modify-write chain so latency 1906 // should be factored in too. Inflating the cost per element by 1. 1907 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 1908 1909 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 1910 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 1911 }; 1912 1913 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 1914 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1915 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1916 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1917 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1918 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1919 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1920 1921 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1922 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 }, 1923 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1924 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1925 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1926 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1927 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1928 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1929 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1930 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1931 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1932 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1933 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1934 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1935 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1936 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1937 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1938 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1939 1940 // These truncates end up widening elements. 1941 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 1 }, // PMOVXZBQ 1942 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 1 }, // PMOVXZWQ 1943 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 1 }, // PMOVXZBD 1944 1945 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 1 }, 1946 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 1 }, 1947 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 1948 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 1949 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 1950 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 1951 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 1952 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 1953 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 1 }, // PSHUFB 1954 1955 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 1956 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 1957 1958 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 3 }, 1959 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 3 }, 1960 1961 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 3 }, 1962 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 3 }, 1963 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, 1964 }; 1965 1966 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 1967 // These are somewhat magic numbers justified by looking at the output of 1968 // Intel's IACA, running some kernels and making sure when we take 1969 // legalization into account the throughput will be overestimated. 1970 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1971 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1972 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1973 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1974 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1975 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 2*10 }, 1976 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2*10 }, 1977 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1978 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 1979 1980 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1981 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1982 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1983 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1984 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1985 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1986 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 }, 1987 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1988 1989 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 4 }, 1990 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 2 }, 1991 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, 1992 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, 1993 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, 1994 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 4 }, 1995 1996 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 1 }, 1997 1998 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 6 }, 1999 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 }, 2000 2001 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 2002 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 2003 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 4 }, 2004 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 4 }, 2005 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 }, 2006 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 2 }, 2007 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 }, 2008 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 4 }, 2009 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 8 }, 2010 2011 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 2012 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 2013 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 2014 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 2015 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 2016 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 2017 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 2018 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 2019 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 2020 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 2021 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 2022 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 2023 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 2024 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 2025 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 2026 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 2027 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 2028 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 2029 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 2030 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 2031 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 2032 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 2033 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 2034 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 2035 2036 // These truncates are really widening elements. 2037 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 1 }, // PSHUFD 2038 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // PUNPCKLWD+DQ 2039 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // PUNPCKLBW+WD+PSHUFD 2040 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 1 }, // PUNPCKLWD 2041 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // PUNPCKLBW+WD 2042 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 1 }, // PUNPCKLBW 2043 2044 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // PAND+PACKUSWB 2045 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // PAND+PACKUSWB 2046 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // PAND+PACKUSWB 2047 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 2048 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 3 }, // PAND+2*PACKUSWB 2049 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 2050 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 2051 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 2052 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 2053 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 2054 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2055 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 2056 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 2057 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 2058 { ISD::TRUNCATE, MVT::v2i32, MVT::v2i64, 1 }, // PSHUFD 2059 }; 2060 2061 std::pair<InstructionCost, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 2062 std::pair<InstructionCost, MVT> LTDest = 2063 TLI->getTypeLegalizationCost(DL, Dst); 2064 2065 if (ST->hasSSE41() && !ST->hasAVX()) 2066 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2067 LTDest.second, LTSrc.second)) 2068 return AdjustCost(LTSrc.first * Entry->Cost); 2069 2070 if (ST->hasSSE2() && !ST->hasAVX()) 2071 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2072 LTDest.second, LTSrc.second)) 2073 return AdjustCost(LTSrc.first * Entry->Cost); 2074 2075 EVT SrcTy = TLI->getValueType(DL, Src); 2076 EVT DstTy = TLI->getValueType(DL, Dst); 2077 2078 // The function getSimpleVT only handles simple value types. 2079 if (!SrcTy.isSimple() || !DstTy.isSimple()) 2080 return AdjustCost(BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind)); 2081 2082 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 2083 MVT SimpleDstTy = DstTy.getSimpleVT(); 2084 2085 if (ST->useAVX512Regs()) { 2086 if (ST->hasBWI()) 2087 if (const auto *Entry = ConvertCostTableLookup(AVX512BWConversionTbl, ISD, 2088 SimpleDstTy, SimpleSrcTy)) 2089 return AdjustCost(Entry->Cost); 2090 2091 if (ST->hasDQI()) 2092 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 2093 SimpleDstTy, SimpleSrcTy)) 2094 return AdjustCost(Entry->Cost); 2095 2096 if (ST->hasAVX512()) 2097 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 2098 SimpleDstTy, SimpleSrcTy)) 2099 return AdjustCost(Entry->Cost); 2100 } 2101 2102 if (ST->hasBWI()) 2103 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 2104 SimpleDstTy, SimpleSrcTy)) 2105 return AdjustCost(Entry->Cost); 2106 2107 if (ST->hasDQI()) 2108 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 2109 SimpleDstTy, SimpleSrcTy)) 2110 return AdjustCost(Entry->Cost); 2111 2112 if (ST->hasAVX512()) 2113 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2114 SimpleDstTy, SimpleSrcTy)) 2115 return AdjustCost(Entry->Cost); 2116 2117 if (ST->hasAVX2()) { 2118 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2119 SimpleDstTy, SimpleSrcTy)) 2120 return AdjustCost(Entry->Cost); 2121 } 2122 2123 if (ST->hasAVX()) { 2124 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2125 SimpleDstTy, SimpleSrcTy)) 2126 return AdjustCost(Entry->Cost); 2127 } 2128 2129 if (ST->hasSSE41()) { 2130 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2131 SimpleDstTy, SimpleSrcTy)) 2132 return AdjustCost(Entry->Cost); 2133 } 2134 2135 if (ST->hasSSE2()) { 2136 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2137 SimpleDstTy, SimpleSrcTy)) 2138 return AdjustCost(Entry->Cost); 2139 } 2140 2141 return AdjustCost( 2142 BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I)); 2143 } 2144 2145 InstructionCost X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 2146 Type *CondTy, 2147 CmpInst::Predicate VecPred, 2148 TTI::TargetCostKind CostKind, 2149 const Instruction *I) { 2150 // TODO: Handle other cost kinds. 2151 if (CostKind != TTI::TCK_RecipThroughput) 2152 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, 2153 I); 2154 2155 // Legalize the type. 2156 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2157 2158 MVT MTy = LT.second; 2159 2160 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2161 assert(ISD && "Invalid opcode"); 2162 2163 unsigned ExtraCost = 0; 2164 if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) { 2165 // Some vector comparison predicates cost extra instructions. 2166 if (MTy.isVector() && 2167 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 2168 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 2169 ST->hasBWI())) { 2170 switch (cast<CmpInst>(I)->getPredicate()) { 2171 case CmpInst::Predicate::ICMP_NE: 2172 // xor(cmpeq(x,y),-1) 2173 ExtraCost = 1; 2174 break; 2175 case CmpInst::Predicate::ICMP_SGE: 2176 case CmpInst::Predicate::ICMP_SLE: 2177 // xor(cmpgt(x,y),-1) 2178 ExtraCost = 1; 2179 break; 2180 case CmpInst::Predicate::ICMP_ULT: 2181 case CmpInst::Predicate::ICMP_UGT: 2182 // cmpgt(xor(x,signbit),xor(y,signbit)) 2183 // xor(cmpeq(pmaxu(x,y),x),-1) 2184 ExtraCost = 2; 2185 break; 2186 case CmpInst::Predicate::ICMP_ULE: 2187 case CmpInst::Predicate::ICMP_UGE: 2188 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 2189 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 2190 // cmpeq(psubus(x,y),0) 2191 // cmpeq(pminu(x,y),x) 2192 ExtraCost = 1; 2193 } else { 2194 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 2195 ExtraCost = 3; 2196 } 2197 break; 2198 default: 2199 break; 2200 } 2201 } 2202 } 2203 2204 static const CostTblEntry SLMCostTbl[] = { 2205 // slm pcmpeq/pcmpgt throughput is 2 2206 { ISD::SETCC, MVT::v2i64, 2 }, 2207 }; 2208 2209 static const CostTblEntry AVX512BWCostTbl[] = { 2210 { ISD::SETCC, MVT::v32i16, 1 }, 2211 { ISD::SETCC, MVT::v64i8, 1 }, 2212 2213 { ISD::SELECT, MVT::v32i16, 1 }, 2214 { ISD::SELECT, MVT::v64i8, 1 }, 2215 }; 2216 2217 static const CostTblEntry AVX512CostTbl[] = { 2218 { ISD::SETCC, MVT::v8i64, 1 }, 2219 { ISD::SETCC, MVT::v16i32, 1 }, 2220 { ISD::SETCC, MVT::v8f64, 1 }, 2221 { ISD::SETCC, MVT::v16f32, 1 }, 2222 2223 { ISD::SELECT, MVT::v8i64, 1 }, 2224 { ISD::SELECT, MVT::v16i32, 1 }, 2225 { ISD::SELECT, MVT::v8f64, 1 }, 2226 { ISD::SELECT, MVT::v16f32, 1 }, 2227 2228 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 2229 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 2230 2231 { ISD::SELECT, MVT::v32i16, 2 }, // FIXME: should be 3 2232 { ISD::SELECT, MVT::v64i8, 2 }, // FIXME: should be 3 2233 }; 2234 2235 static const CostTblEntry AVX2CostTbl[] = { 2236 { ISD::SETCC, MVT::v4i64, 1 }, 2237 { ISD::SETCC, MVT::v8i32, 1 }, 2238 { ISD::SETCC, MVT::v16i16, 1 }, 2239 { ISD::SETCC, MVT::v32i8, 1 }, 2240 2241 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 2242 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 2243 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 2244 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 2245 }; 2246 2247 static const CostTblEntry AVX1CostTbl[] = { 2248 { ISD::SETCC, MVT::v4f64, 1 }, 2249 { ISD::SETCC, MVT::v8f32, 1 }, 2250 // AVX1 does not support 8-wide integer compare. 2251 { ISD::SETCC, MVT::v4i64, 4 }, 2252 { ISD::SETCC, MVT::v8i32, 4 }, 2253 { ISD::SETCC, MVT::v16i16, 4 }, 2254 { ISD::SETCC, MVT::v32i8, 4 }, 2255 2256 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 2257 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 2258 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 2259 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 2260 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 2261 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 2262 }; 2263 2264 static const CostTblEntry SSE42CostTbl[] = { 2265 { ISD::SETCC, MVT::v2f64, 1 }, 2266 { ISD::SETCC, MVT::v4f32, 1 }, 2267 { ISD::SETCC, MVT::v2i64, 1 }, 2268 }; 2269 2270 static const CostTblEntry SSE41CostTbl[] = { 2271 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 2272 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 2273 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 2274 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 2275 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 2276 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 2277 }; 2278 2279 static const CostTblEntry SSE2CostTbl[] = { 2280 { ISD::SETCC, MVT::v2f64, 2 }, 2281 { ISD::SETCC, MVT::f64, 1 }, 2282 { ISD::SETCC, MVT::v2i64, 8 }, 2283 { ISD::SETCC, MVT::v4i32, 1 }, 2284 { ISD::SETCC, MVT::v8i16, 1 }, 2285 { ISD::SETCC, MVT::v16i8, 1 }, 2286 2287 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 2288 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 2289 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 2290 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 2291 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 2292 }; 2293 2294 static const CostTblEntry SSE1CostTbl[] = { 2295 { ISD::SETCC, MVT::v4f32, 2 }, 2296 { ISD::SETCC, MVT::f32, 1 }, 2297 2298 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 2299 }; 2300 2301 if (ST->isSLM()) 2302 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2303 return LT.first * (ExtraCost + Entry->Cost); 2304 2305 if (ST->hasBWI()) 2306 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2307 return LT.first * (ExtraCost + Entry->Cost); 2308 2309 if (ST->hasAVX512()) 2310 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2311 return LT.first * (ExtraCost + Entry->Cost); 2312 2313 if (ST->hasAVX2()) 2314 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2315 return LT.first * (ExtraCost + Entry->Cost); 2316 2317 if (ST->hasAVX()) 2318 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2319 return LT.first * (ExtraCost + Entry->Cost); 2320 2321 if (ST->hasSSE42()) 2322 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2323 return LT.first * (ExtraCost + Entry->Cost); 2324 2325 if (ST->hasSSE41()) 2326 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2327 return LT.first * (ExtraCost + Entry->Cost); 2328 2329 if (ST->hasSSE2()) 2330 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2331 return LT.first * (ExtraCost + Entry->Cost); 2332 2333 if (ST->hasSSE1()) 2334 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2335 return LT.first * (ExtraCost + Entry->Cost); 2336 2337 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I); 2338 } 2339 2340 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2341 2342 InstructionCost 2343 X86TTIImpl::getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 2344 TTI::TargetCostKind CostKind) { 2345 2346 // Costs should match the codegen from: 2347 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2348 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2349 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2350 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2351 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2352 2353 // TODO: Overflow intrinsics (*ADDO, *SUBO, *MULO) with vector types are not 2354 // specialized in these tables yet. 2355 static const CostTblEntry AVX512CDCostTbl[] = { 2356 { ISD::CTLZ, MVT::v8i64, 1 }, 2357 { ISD::CTLZ, MVT::v16i32, 1 }, 2358 { ISD::CTLZ, MVT::v32i16, 8 }, 2359 { ISD::CTLZ, MVT::v64i8, 20 }, 2360 { ISD::CTLZ, MVT::v4i64, 1 }, 2361 { ISD::CTLZ, MVT::v8i32, 1 }, 2362 { ISD::CTLZ, MVT::v16i16, 4 }, 2363 { ISD::CTLZ, MVT::v32i8, 10 }, 2364 { ISD::CTLZ, MVT::v2i64, 1 }, 2365 { ISD::CTLZ, MVT::v4i32, 1 }, 2366 { ISD::CTLZ, MVT::v8i16, 4 }, 2367 { ISD::CTLZ, MVT::v16i8, 4 }, 2368 }; 2369 static const CostTblEntry AVX512BWCostTbl[] = { 2370 { ISD::ABS, MVT::v32i16, 1 }, 2371 { ISD::ABS, MVT::v64i8, 1 }, 2372 { ISD::BITREVERSE, MVT::v8i64, 5 }, 2373 { ISD::BITREVERSE, MVT::v16i32, 5 }, 2374 { ISD::BITREVERSE, MVT::v32i16, 5 }, 2375 { ISD::BITREVERSE, MVT::v64i8, 5 }, 2376 { ISD::CTLZ, MVT::v8i64, 23 }, 2377 { ISD::CTLZ, MVT::v16i32, 22 }, 2378 { ISD::CTLZ, MVT::v32i16, 18 }, 2379 { ISD::CTLZ, MVT::v64i8, 17 }, 2380 { ISD::CTPOP, MVT::v8i64, 7 }, 2381 { ISD::CTPOP, MVT::v16i32, 11 }, 2382 { ISD::CTPOP, MVT::v32i16, 9 }, 2383 { ISD::CTPOP, MVT::v64i8, 6 }, 2384 { ISD::CTTZ, MVT::v8i64, 10 }, 2385 { ISD::CTTZ, MVT::v16i32, 14 }, 2386 { ISD::CTTZ, MVT::v32i16, 12 }, 2387 { ISD::CTTZ, MVT::v64i8, 9 }, 2388 { ISD::SADDSAT, MVT::v32i16, 1 }, 2389 { ISD::SADDSAT, MVT::v64i8, 1 }, 2390 { ISD::SMAX, MVT::v32i16, 1 }, 2391 { ISD::SMAX, MVT::v64i8, 1 }, 2392 { ISD::SMIN, MVT::v32i16, 1 }, 2393 { ISD::SMIN, MVT::v64i8, 1 }, 2394 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2395 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2396 { ISD::UADDSAT, MVT::v32i16, 1 }, 2397 { ISD::UADDSAT, MVT::v64i8, 1 }, 2398 { ISD::UMAX, MVT::v32i16, 1 }, 2399 { ISD::UMAX, MVT::v64i8, 1 }, 2400 { ISD::UMIN, MVT::v32i16, 1 }, 2401 { ISD::UMIN, MVT::v64i8, 1 }, 2402 { ISD::USUBSAT, MVT::v32i16, 1 }, 2403 { ISD::USUBSAT, MVT::v64i8, 1 }, 2404 }; 2405 static const CostTblEntry AVX512CostTbl[] = { 2406 { ISD::ABS, MVT::v8i64, 1 }, 2407 { ISD::ABS, MVT::v16i32, 1 }, 2408 { ISD::ABS, MVT::v32i16, 2 }, // FIXME: include split 2409 { ISD::ABS, MVT::v64i8, 2 }, // FIXME: include split 2410 { ISD::ABS, MVT::v4i64, 1 }, 2411 { ISD::ABS, MVT::v2i64, 1 }, 2412 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2413 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2414 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2415 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2416 { ISD::CTLZ, MVT::v8i64, 29 }, 2417 { ISD::CTLZ, MVT::v16i32, 35 }, 2418 { ISD::CTLZ, MVT::v32i16, 28 }, 2419 { ISD::CTLZ, MVT::v64i8, 18 }, 2420 { ISD::CTPOP, MVT::v8i64, 16 }, 2421 { ISD::CTPOP, MVT::v16i32, 24 }, 2422 { ISD::CTPOP, MVT::v32i16, 18 }, 2423 { ISD::CTPOP, MVT::v64i8, 12 }, 2424 { ISD::CTTZ, MVT::v8i64, 20 }, 2425 { ISD::CTTZ, MVT::v16i32, 28 }, 2426 { ISD::CTTZ, MVT::v32i16, 24 }, 2427 { ISD::CTTZ, MVT::v64i8, 18 }, 2428 { ISD::SMAX, MVT::v8i64, 1 }, 2429 { ISD::SMAX, MVT::v16i32, 1 }, 2430 { ISD::SMAX, MVT::v32i16, 2 }, // FIXME: include split 2431 { ISD::SMAX, MVT::v64i8, 2 }, // FIXME: include split 2432 { ISD::SMAX, MVT::v4i64, 1 }, 2433 { ISD::SMAX, MVT::v2i64, 1 }, 2434 { ISD::SMIN, MVT::v8i64, 1 }, 2435 { ISD::SMIN, MVT::v16i32, 1 }, 2436 { ISD::SMIN, MVT::v32i16, 2 }, // FIXME: include split 2437 { ISD::SMIN, MVT::v64i8, 2 }, // FIXME: include split 2438 { ISD::SMIN, MVT::v4i64, 1 }, 2439 { ISD::SMIN, MVT::v2i64, 1 }, 2440 { ISD::UMAX, MVT::v8i64, 1 }, 2441 { ISD::UMAX, MVT::v16i32, 1 }, 2442 { ISD::UMAX, MVT::v32i16, 2 }, // FIXME: include split 2443 { ISD::UMAX, MVT::v64i8, 2 }, // FIXME: include split 2444 { ISD::UMAX, MVT::v4i64, 1 }, 2445 { ISD::UMAX, MVT::v2i64, 1 }, 2446 { ISD::UMIN, MVT::v8i64, 1 }, 2447 { ISD::UMIN, MVT::v16i32, 1 }, 2448 { ISD::UMIN, MVT::v32i16, 2 }, // FIXME: include split 2449 { ISD::UMIN, MVT::v64i8, 2 }, // FIXME: include split 2450 { ISD::UMIN, MVT::v4i64, 1 }, 2451 { ISD::UMIN, MVT::v2i64, 1 }, 2452 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2453 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2454 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2455 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2456 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2457 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2458 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2459 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2460 { ISD::SADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2461 { ISD::SADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2462 { ISD::SSUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2463 { ISD::SSUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2464 { ISD::UADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2465 { ISD::UADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2466 { ISD::USUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2467 { ISD::USUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2468 { ISD::FMAXNUM, MVT::f32, 2 }, 2469 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2470 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2471 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2472 { ISD::FMAXNUM, MVT::f64, 2 }, 2473 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2474 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2475 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2476 }; 2477 static const CostTblEntry XOPCostTbl[] = { 2478 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2479 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2480 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2481 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2482 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2483 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2484 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2485 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2486 { ISD::BITREVERSE, MVT::i64, 3 }, 2487 { ISD::BITREVERSE, MVT::i32, 3 }, 2488 { ISD::BITREVERSE, MVT::i16, 3 }, 2489 { ISD::BITREVERSE, MVT::i8, 3 } 2490 }; 2491 static const CostTblEntry AVX2CostTbl[] = { 2492 { ISD::ABS, MVT::v4i64, 2 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2493 { ISD::ABS, MVT::v8i32, 1 }, 2494 { ISD::ABS, MVT::v16i16, 1 }, 2495 { ISD::ABS, MVT::v32i8, 1 }, 2496 { ISD::BITREVERSE, MVT::v4i64, 5 }, 2497 { ISD::BITREVERSE, MVT::v8i32, 5 }, 2498 { ISD::BITREVERSE, MVT::v16i16, 5 }, 2499 { ISD::BITREVERSE, MVT::v32i8, 5 }, 2500 { ISD::BSWAP, MVT::v4i64, 1 }, 2501 { ISD::BSWAP, MVT::v8i32, 1 }, 2502 { ISD::BSWAP, MVT::v16i16, 1 }, 2503 { ISD::CTLZ, MVT::v4i64, 23 }, 2504 { ISD::CTLZ, MVT::v8i32, 18 }, 2505 { ISD::CTLZ, MVT::v16i16, 14 }, 2506 { ISD::CTLZ, MVT::v32i8, 9 }, 2507 { ISD::CTPOP, MVT::v4i64, 7 }, 2508 { ISD::CTPOP, MVT::v8i32, 11 }, 2509 { ISD::CTPOP, MVT::v16i16, 9 }, 2510 { ISD::CTPOP, MVT::v32i8, 6 }, 2511 { ISD::CTTZ, MVT::v4i64, 10 }, 2512 { ISD::CTTZ, MVT::v8i32, 14 }, 2513 { ISD::CTTZ, MVT::v16i16, 12 }, 2514 { ISD::CTTZ, MVT::v32i8, 9 }, 2515 { ISD::SADDSAT, MVT::v16i16, 1 }, 2516 { ISD::SADDSAT, MVT::v32i8, 1 }, 2517 { ISD::SMAX, MVT::v8i32, 1 }, 2518 { ISD::SMAX, MVT::v16i16, 1 }, 2519 { ISD::SMAX, MVT::v32i8, 1 }, 2520 { ISD::SMIN, MVT::v8i32, 1 }, 2521 { ISD::SMIN, MVT::v16i16, 1 }, 2522 { ISD::SMIN, MVT::v32i8, 1 }, 2523 { ISD::SSUBSAT, MVT::v16i16, 1 }, 2524 { ISD::SSUBSAT, MVT::v32i8, 1 }, 2525 { ISD::UADDSAT, MVT::v16i16, 1 }, 2526 { ISD::UADDSAT, MVT::v32i8, 1 }, 2527 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 2528 { ISD::UMAX, MVT::v8i32, 1 }, 2529 { ISD::UMAX, MVT::v16i16, 1 }, 2530 { ISD::UMAX, MVT::v32i8, 1 }, 2531 { ISD::UMIN, MVT::v8i32, 1 }, 2532 { ISD::UMIN, MVT::v16i16, 1 }, 2533 { ISD::UMIN, MVT::v32i8, 1 }, 2534 { ISD::USUBSAT, MVT::v16i16, 1 }, 2535 { ISD::USUBSAT, MVT::v32i8, 1 }, 2536 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2537 { ISD::FMAXNUM, MVT::v8f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2538 { ISD::FMAXNUM, MVT::v4f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2539 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2540 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2541 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2542 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2543 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2544 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2545 }; 2546 static const CostTblEntry AVX1CostTbl[] = { 2547 { ISD::ABS, MVT::v4i64, 5 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2548 { ISD::ABS, MVT::v8i32, 3 }, 2549 { ISD::ABS, MVT::v16i16, 3 }, 2550 { ISD::ABS, MVT::v32i8, 3 }, 2551 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 2552 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 2553 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 2554 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 2555 { ISD::BSWAP, MVT::v4i64, 4 }, 2556 { ISD::BSWAP, MVT::v8i32, 4 }, 2557 { ISD::BSWAP, MVT::v16i16, 4 }, 2558 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 2559 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 2560 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 2561 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2562 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 2563 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 2564 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 2565 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 2566 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 2567 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 2568 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 2569 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2570 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2571 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2572 { ISD::SMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2573 { ISD::SMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2574 { ISD::SMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2575 { ISD::SMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2576 { ISD::SMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2577 { ISD::SMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2578 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2579 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2580 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2581 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2582 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 2583 { ISD::UMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2584 { ISD::UMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2585 { ISD::UMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2586 { ISD::UMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2587 { ISD::UMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2588 { ISD::UMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2589 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2590 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2591 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 2592 { ISD::FMAXNUM, MVT::f32, 3 }, // MAXSS + CMPUNORDSS + BLENDVPS 2593 { ISD::FMAXNUM, MVT::v4f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2594 { ISD::FMAXNUM, MVT::v8f32, 5 }, // MAXPS + CMPUNORDPS + BLENDVPS + ? 2595 { ISD::FMAXNUM, MVT::f64, 3 }, // MAXSD + CMPUNORDSD + BLENDVPD 2596 { ISD::FMAXNUM, MVT::v2f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2597 { ISD::FMAXNUM, MVT::v4f64, 5 }, // MAXPD + CMPUNORDPD + BLENDVPD + ? 2598 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 2599 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 2600 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 2601 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 2602 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 2603 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 2604 }; 2605 static const CostTblEntry GLMCostTbl[] = { 2606 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 2607 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 2608 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 2609 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 2610 }; 2611 static const CostTblEntry SLMCostTbl[] = { 2612 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 2613 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 2614 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 2615 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 2616 }; 2617 static const CostTblEntry SSE42CostTbl[] = { 2618 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 2619 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 2620 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 2621 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 2622 }; 2623 static const CostTblEntry SSE41CostTbl[] = { 2624 { ISD::ABS, MVT::v2i64, 2 }, // BLENDVPD(X,PSUBQ(0,X),X) 2625 { ISD::SMAX, MVT::v4i32, 1 }, 2626 { ISD::SMAX, MVT::v16i8, 1 }, 2627 { ISD::SMIN, MVT::v4i32, 1 }, 2628 { ISD::SMIN, MVT::v16i8, 1 }, 2629 { ISD::UMAX, MVT::v4i32, 1 }, 2630 { ISD::UMAX, MVT::v8i16, 1 }, 2631 { ISD::UMIN, MVT::v4i32, 1 }, 2632 { ISD::UMIN, MVT::v8i16, 1 }, 2633 }; 2634 static const CostTblEntry SSSE3CostTbl[] = { 2635 { ISD::ABS, MVT::v4i32, 1 }, 2636 { ISD::ABS, MVT::v8i16, 1 }, 2637 { ISD::ABS, MVT::v16i8, 1 }, 2638 { ISD::BITREVERSE, MVT::v2i64, 5 }, 2639 { ISD::BITREVERSE, MVT::v4i32, 5 }, 2640 { ISD::BITREVERSE, MVT::v8i16, 5 }, 2641 { ISD::BITREVERSE, MVT::v16i8, 5 }, 2642 { ISD::BSWAP, MVT::v2i64, 1 }, 2643 { ISD::BSWAP, MVT::v4i32, 1 }, 2644 { ISD::BSWAP, MVT::v8i16, 1 }, 2645 { ISD::CTLZ, MVT::v2i64, 23 }, 2646 { ISD::CTLZ, MVT::v4i32, 18 }, 2647 { ISD::CTLZ, MVT::v8i16, 14 }, 2648 { ISD::CTLZ, MVT::v16i8, 9 }, 2649 { ISD::CTPOP, MVT::v2i64, 7 }, 2650 { ISD::CTPOP, MVT::v4i32, 11 }, 2651 { ISD::CTPOP, MVT::v8i16, 9 }, 2652 { ISD::CTPOP, MVT::v16i8, 6 }, 2653 { ISD::CTTZ, MVT::v2i64, 10 }, 2654 { ISD::CTTZ, MVT::v4i32, 14 }, 2655 { ISD::CTTZ, MVT::v8i16, 12 }, 2656 { ISD::CTTZ, MVT::v16i8, 9 } 2657 }; 2658 static const CostTblEntry SSE2CostTbl[] = { 2659 { ISD::ABS, MVT::v2i64, 4 }, 2660 { ISD::ABS, MVT::v4i32, 3 }, 2661 { ISD::ABS, MVT::v8i16, 2 }, 2662 { ISD::ABS, MVT::v16i8, 2 }, 2663 { ISD::BITREVERSE, MVT::v2i64, 29 }, 2664 { ISD::BITREVERSE, MVT::v4i32, 27 }, 2665 { ISD::BITREVERSE, MVT::v8i16, 27 }, 2666 { ISD::BITREVERSE, MVT::v16i8, 20 }, 2667 { ISD::BSWAP, MVT::v2i64, 7 }, 2668 { ISD::BSWAP, MVT::v4i32, 7 }, 2669 { ISD::BSWAP, MVT::v8i16, 7 }, 2670 { ISD::CTLZ, MVT::v2i64, 25 }, 2671 { ISD::CTLZ, MVT::v4i32, 26 }, 2672 { ISD::CTLZ, MVT::v8i16, 20 }, 2673 { ISD::CTLZ, MVT::v16i8, 17 }, 2674 { ISD::CTPOP, MVT::v2i64, 12 }, 2675 { ISD::CTPOP, MVT::v4i32, 15 }, 2676 { ISD::CTPOP, MVT::v8i16, 13 }, 2677 { ISD::CTPOP, MVT::v16i8, 10 }, 2678 { ISD::CTTZ, MVT::v2i64, 14 }, 2679 { ISD::CTTZ, MVT::v4i32, 18 }, 2680 { ISD::CTTZ, MVT::v8i16, 16 }, 2681 { ISD::CTTZ, MVT::v16i8, 13 }, 2682 { ISD::SADDSAT, MVT::v8i16, 1 }, 2683 { ISD::SADDSAT, MVT::v16i8, 1 }, 2684 { ISD::SMAX, MVT::v8i16, 1 }, 2685 { ISD::SMIN, MVT::v8i16, 1 }, 2686 { ISD::SSUBSAT, MVT::v8i16, 1 }, 2687 { ISD::SSUBSAT, MVT::v16i8, 1 }, 2688 { ISD::UADDSAT, MVT::v8i16, 1 }, 2689 { ISD::UADDSAT, MVT::v16i8, 1 }, 2690 { ISD::UMAX, MVT::v8i16, 2 }, 2691 { ISD::UMAX, MVT::v16i8, 1 }, 2692 { ISD::UMIN, MVT::v8i16, 2 }, 2693 { ISD::UMIN, MVT::v16i8, 1 }, 2694 { ISD::USUBSAT, MVT::v8i16, 1 }, 2695 { ISD::USUBSAT, MVT::v16i8, 1 }, 2696 { ISD::FMAXNUM, MVT::f64, 4 }, 2697 { ISD::FMAXNUM, MVT::v2f64, 4 }, 2698 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 2699 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 2700 }; 2701 static const CostTblEntry SSE1CostTbl[] = { 2702 { ISD::FMAXNUM, MVT::f32, 4 }, 2703 { ISD::FMAXNUM, MVT::v4f32, 4 }, 2704 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 2705 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 2706 }; 2707 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 2708 { ISD::CTTZ, MVT::i64, 1 }, 2709 }; 2710 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 2711 { ISD::CTTZ, MVT::i32, 1 }, 2712 { ISD::CTTZ, MVT::i16, 1 }, 2713 { ISD::CTTZ, MVT::i8, 1 }, 2714 }; 2715 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 2716 { ISD::CTLZ, MVT::i64, 1 }, 2717 }; 2718 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 2719 { ISD::CTLZ, MVT::i32, 1 }, 2720 { ISD::CTLZ, MVT::i16, 1 }, 2721 { ISD::CTLZ, MVT::i8, 1 }, 2722 }; 2723 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 2724 { ISD::CTPOP, MVT::i64, 1 }, 2725 }; 2726 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 2727 { ISD::CTPOP, MVT::i32, 1 }, 2728 { ISD::CTPOP, MVT::i16, 1 }, 2729 { ISD::CTPOP, MVT::i8, 1 }, 2730 }; 2731 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2732 { ISD::ABS, MVT::i64, 2 }, // SUB+CMOV 2733 { ISD::BITREVERSE, MVT::i64, 14 }, 2734 { ISD::BSWAP, MVT::i64, 1 }, 2735 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 2736 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 2737 { ISD::CTPOP, MVT::i64, 10 }, 2738 { ISD::SADDO, MVT::i64, 1 }, 2739 { ISD::UADDO, MVT::i64, 1 }, 2740 { ISD::UMULO, MVT::i64, 2 }, // mulq + seto 2741 }; 2742 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2743 { ISD::ABS, MVT::i32, 2 }, // SUB+CMOV 2744 { ISD::ABS, MVT::i16, 2 }, // SUB+CMOV 2745 { ISD::BITREVERSE, MVT::i32, 14 }, 2746 { ISD::BITREVERSE, MVT::i16, 14 }, 2747 { ISD::BITREVERSE, MVT::i8, 11 }, 2748 { ISD::BSWAP, MVT::i32, 1 }, 2749 { ISD::BSWAP, MVT::i16, 1 }, // ROL 2750 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 2751 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 2752 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 2753 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 2754 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 2755 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 2756 { ISD::CTPOP, MVT::i32, 8 }, 2757 { ISD::CTPOP, MVT::i16, 9 }, 2758 { ISD::CTPOP, MVT::i8, 7 }, 2759 { ISD::SADDO, MVT::i32, 1 }, 2760 { ISD::SADDO, MVT::i16, 1 }, 2761 { ISD::SADDO, MVT::i8, 1 }, 2762 { ISD::UADDO, MVT::i32, 1 }, 2763 { ISD::UADDO, MVT::i16, 1 }, 2764 { ISD::UADDO, MVT::i8, 1 }, 2765 { ISD::UMULO, MVT::i32, 2 }, // mul + seto 2766 { ISD::UMULO, MVT::i16, 2 }, 2767 { ISD::UMULO, MVT::i8, 2 }, 2768 }; 2769 2770 Type *RetTy = ICA.getReturnType(); 2771 Type *OpTy = RetTy; 2772 Intrinsic::ID IID = ICA.getID(); 2773 unsigned ISD = ISD::DELETED_NODE; 2774 switch (IID) { 2775 default: 2776 break; 2777 case Intrinsic::abs: 2778 ISD = ISD::ABS; 2779 break; 2780 case Intrinsic::bitreverse: 2781 ISD = ISD::BITREVERSE; 2782 break; 2783 case Intrinsic::bswap: 2784 ISD = ISD::BSWAP; 2785 break; 2786 case Intrinsic::ctlz: 2787 ISD = ISD::CTLZ; 2788 break; 2789 case Intrinsic::ctpop: 2790 ISD = ISD::CTPOP; 2791 break; 2792 case Intrinsic::cttz: 2793 ISD = ISD::CTTZ; 2794 break; 2795 case Intrinsic::maxnum: 2796 case Intrinsic::minnum: 2797 // FMINNUM has same costs so don't duplicate. 2798 ISD = ISD::FMAXNUM; 2799 break; 2800 case Intrinsic::sadd_sat: 2801 ISD = ISD::SADDSAT; 2802 break; 2803 case Intrinsic::smax: 2804 ISD = ISD::SMAX; 2805 break; 2806 case Intrinsic::smin: 2807 ISD = ISD::SMIN; 2808 break; 2809 case Intrinsic::ssub_sat: 2810 ISD = ISD::SSUBSAT; 2811 break; 2812 case Intrinsic::uadd_sat: 2813 ISD = ISD::UADDSAT; 2814 break; 2815 case Intrinsic::umax: 2816 ISD = ISD::UMAX; 2817 break; 2818 case Intrinsic::umin: 2819 ISD = ISD::UMIN; 2820 break; 2821 case Intrinsic::usub_sat: 2822 ISD = ISD::USUBSAT; 2823 break; 2824 case Intrinsic::sqrt: 2825 ISD = ISD::FSQRT; 2826 break; 2827 case Intrinsic::sadd_with_overflow: 2828 case Intrinsic::ssub_with_overflow: 2829 // SSUBO has same costs so don't duplicate. 2830 ISD = ISD::SADDO; 2831 OpTy = RetTy->getContainedType(0); 2832 break; 2833 case Intrinsic::uadd_with_overflow: 2834 case Intrinsic::usub_with_overflow: 2835 // USUBO has same costs so don't duplicate. 2836 ISD = ISD::UADDO; 2837 OpTy = RetTy->getContainedType(0); 2838 break; 2839 case Intrinsic::umul_with_overflow: 2840 case Intrinsic::smul_with_overflow: 2841 // SMULO has same costs so don't duplicate. 2842 ISD = ISD::UMULO; 2843 OpTy = RetTy->getContainedType(0); 2844 break; 2845 } 2846 2847 if (ISD != ISD::DELETED_NODE) { 2848 // Legalize the type. 2849 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 2850 MVT MTy = LT.second; 2851 2852 // Attempt to lookup cost. 2853 if (ISD == ISD::BITREVERSE && ST->hasGFNI() && ST->hasSSSE3() && 2854 MTy.isVector()) { 2855 // With PSHUFB the code is very similar for all types. If we have integer 2856 // byte operations, we just need a GF2P8AFFINEQB for vXi8. For other types 2857 // we also need a PSHUFB. 2858 unsigned Cost = MTy.getVectorElementType() == MVT::i8 ? 1 : 2; 2859 2860 // Without byte operations, we need twice as many GF2P8AFFINEQB and PSHUFB 2861 // instructions. We also need an extract and an insert. 2862 if (!(MTy.is128BitVector() || (ST->hasAVX2() && MTy.is256BitVector()) || 2863 (ST->hasBWI() && MTy.is512BitVector()))) 2864 Cost = Cost * 2 + 2; 2865 2866 return LT.first * Cost; 2867 } 2868 2869 auto adjustTableCost = [](const CostTblEntry &Entry, 2870 InstructionCost LegalizationCost, 2871 FastMathFlags FMF) { 2872 // If there are no NANs to deal with, then these are reduced to a 2873 // single MIN** or MAX** instruction instead of the MIN/CMP/SELECT that we 2874 // assume is used in the non-fast case. 2875 if (Entry.ISD == ISD::FMAXNUM || Entry.ISD == ISD::FMINNUM) { 2876 if (FMF.noNaNs()) 2877 return LegalizationCost * 1; 2878 } 2879 return LegalizationCost * (int)Entry.Cost; 2880 }; 2881 2882 if (ST->useGLMDivSqrtCosts()) 2883 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 2884 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2885 2886 if (ST->isSLM()) 2887 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2888 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2889 2890 if (ST->hasCDI()) 2891 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 2892 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2893 2894 if (ST->hasBWI()) 2895 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2896 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2897 2898 if (ST->hasAVX512()) 2899 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2900 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2901 2902 if (ST->hasXOP()) 2903 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2904 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2905 2906 if (ST->hasAVX2()) 2907 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2908 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2909 2910 if (ST->hasAVX()) 2911 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2912 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2913 2914 if (ST->hasSSE42()) 2915 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2916 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2917 2918 if (ST->hasSSE41()) 2919 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2920 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2921 2922 if (ST->hasSSSE3()) 2923 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 2924 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2925 2926 if (ST->hasSSE2()) 2927 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2928 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2929 2930 if (ST->hasSSE1()) 2931 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2932 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2933 2934 if (ST->hasBMI()) { 2935 if (ST->is64Bit()) 2936 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 2937 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2938 2939 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 2940 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2941 } 2942 2943 if (ST->hasLZCNT()) { 2944 if (ST->is64Bit()) 2945 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 2946 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2947 2948 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 2949 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2950 } 2951 2952 if (ST->hasPOPCNT()) { 2953 if (ST->is64Bit()) 2954 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 2955 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2956 2957 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 2958 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2959 } 2960 2961 if (ISD == ISD::BSWAP && ST->hasMOVBE() && ST->hasFastMOVBE()) { 2962 if (const Instruction *II = ICA.getInst()) { 2963 if (II->hasOneUse() && isa<StoreInst>(II->user_back())) 2964 return TTI::TCC_Free; 2965 if (auto *LI = dyn_cast<LoadInst>(II->getOperand(0))) { 2966 if (LI->hasOneUse()) 2967 return TTI::TCC_Free; 2968 } 2969 } 2970 } 2971 2972 // TODO - add BMI (TZCNT) scalar handling 2973 2974 if (ST->is64Bit()) 2975 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2976 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2977 2978 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2979 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2980 } 2981 2982 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 2983 } 2984 2985 InstructionCost 2986 X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 2987 TTI::TargetCostKind CostKind) { 2988 if (ICA.isTypeBasedOnly()) 2989 return getTypeBasedIntrinsicInstrCost(ICA, CostKind); 2990 2991 static const CostTblEntry AVX512CostTbl[] = { 2992 { ISD::ROTL, MVT::v8i64, 1 }, 2993 { ISD::ROTL, MVT::v4i64, 1 }, 2994 { ISD::ROTL, MVT::v2i64, 1 }, 2995 { ISD::ROTL, MVT::v16i32, 1 }, 2996 { ISD::ROTL, MVT::v8i32, 1 }, 2997 { ISD::ROTL, MVT::v4i32, 1 }, 2998 { ISD::ROTR, MVT::v8i64, 1 }, 2999 { ISD::ROTR, MVT::v4i64, 1 }, 3000 { ISD::ROTR, MVT::v2i64, 1 }, 3001 { ISD::ROTR, MVT::v16i32, 1 }, 3002 { ISD::ROTR, MVT::v8i32, 1 }, 3003 { ISD::ROTR, MVT::v4i32, 1 } 3004 }; 3005 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 3006 static const CostTblEntry XOPCostTbl[] = { 3007 { ISD::ROTL, MVT::v4i64, 4 }, 3008 { ISD::ROTL, MVT::v8i32, 4 }, 3009 { ISD::ROTL, MVT::v16i16, 4 }, 3010 { ISD::ROTL, MVT::v32i8, 4 }, 3011 { ISD::ROTL, MVT::v2i64, 1 }, 3012 { ISD::ROTL, MVT::v4i32, 1 }, 3013 { ISD::ROTL, MVT::v8i16, 1 }, 3014 { ISD::ROTL, MVT::v16i8, 1 }, 3015 { ISD::ROTR, MVT::v4i64, 6 }, 3016 { ISD::ROTR, MVT::v8i32, 6 }, 3017 { ISD::ROTR, MVT::v16i16, 6 }, 3018 { ISD::ROTR, MVT::v32i8, 6 }, 3019 { ISD::ROTR, MVT::v2i64, 2 }, 3020 { ISD::ROTR, MVT::v4i32, 2 }, 3021 { ISD::ROTR, MVT::v8i16, 2 }, 3022 { ISD::ROTR, MVT::v16i8, 2 } 3023 }; 3024 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 3025 { ISD::ROTL, MVT::i64, 1 }, 3026 { ISD::ROTR, MVT::i64, 1 }, 3027 { ISD::FSHL, MVT::i64, 4 } 3028 }; 3029 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 3030 { ISD::ROTL, MVT::i32, 1 }, 3031 { ISD::ROTL, MVT::i16, 1 }, 3032 { ISD::ROTL, MVT::i8, 1 }, 3033 { ISD::ROTR, MVT::i32, 1 }, 3034 { ISD::ROTR, MVT::i16, 1 }, 3035 { ISD::ROTR, MVT::i8, 1 }, 3036 { ISD::FSHL, MVT::i32, 4 }, 3037 { ISD::FSHL, MVT::i16, 4 }, 3038 { ISD::FSHL, MVT::i8, 4 } 3039 }; 3040 3041 Intrinsic::ID IID = ICA.getID(); 3042 Type *RetTy = ICA.getReturnType(); 3043 const SmallVectorImpl<const Value *> &Args = ICA.getArgs(); 3044 unsigned ISD = ISD::DELETED_NODE; 3045 switch (IID) { 3046 default: 3047 break; 3048 case Intrinsic::fshl: 3049 ISD = ISD::FSHL; 3050 if (Args[0] == Args[1]) 3051 ISD = ISD::ROTL; 3052 break; 3053 case Intrinsic::fshr: 3054 // FSHR has same costs so don't duplicate. 3055 ISD = ISD::FSHL; 3056 if (Args[0] == Args[1]) 3057 ISD = ISD::ROTR; 3058 break; 3059 } 3060 3061 if (ISD != ISD::DELETED_NODE) { 3062 // Legalize the type. 3063 std::pair<InstructionCost, MVT> LT = 3064 TLI->getTypeLegalizationCost(DL, RetTy); 3065 MVT MTy = LT.second; 3066 3067 // Attempt to lookup cost. 3068 if (ST->hasAVX512()) 3069 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3070 return LT.first * Entry->Cost; 3071 3072 if (ST->hasXOP()) 3073 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3074 return LT.first * Entry->Cost; 3075 3076 if (ST->is64Bit()) 3077 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3078 return LT.first * Entry->Cost; 3079 3080 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3081 return LT.first * Entry->Cost; 3082 } 3083 3084 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3085 } 3086 3087 InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, 3088 unsigned Index) { 3089 static const CostTblEntry SLMCostTbl[] = { 3090 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 3091 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 3092 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 3093 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 3094 }; 3095 3096 assert(Val->isVectorTy() && "This must be a vector type"); 3097 Type *ScalarType = Val->getScalarType(); 3098 int RegisterFileMoveCost = 0; 3099 3100 if (Index != -1U && (Opcode == Instruction::ExtractElement || 3101 Opcode == Instruction::InsertElement)) { 3102 // Legalize the type. 3103 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 3104 3105 // This type is legalized to a scalar type. 3106 if (!LT.second.isVector()) 3107 return 0; 3108 3109 // The type may be split. Normalize the index to the new type. 3110 unsigned NumElts = LT.second.getVectorNumElements(); 3111 unsigned SubNumElts = NumElts; 3112 Index = Index % NumElts; 3113 3114 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 3115 // For inserts, we also need to insert the subvector back. 3116 if (LT.second.getSizeInBits() > 128) { 3117 assert((LT.second.getSizeInBits() % 128) == 0 && "Illegal vector"); 3118 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 3119 SubNumElts = NumElts / NumSubVecs; 3120 if (SubNumElts <= Index) { 3121 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 3122 Index %= SubNumElts; 3123 } 3124 } 3125 3126 if (Index == 0) { 3127 // Floating point scalars are already located in index #0. 3128 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 3129 // true for all. 3130 if (ScalarType->isFloatingPointTy()) 3131 return RegisterFileMoveCost; 3132 3133 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 3134 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 3135 return 1 + RegisterFileMoveCost; 3136 } 3137 3138 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3139 assert(ISD && "Unexpected vector opcode"); 3140 MVT MScalarTy = LT.second.getScalarType(); 3141 if (ST->isSLM()) 3142 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 3143 return Entry->Cost + RegisterFileMoveCost; 3144 3145 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 3146 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3147 (MScalarTy.isInteger() && ST->hasSSE41())) 3148 return 1 + RegisterFileMoveCost; 3149 3150 // Assume insertps is relatively cheap on all targets. 3151 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 3152 Opcode == Instruction::InsertElement) 3153 return 1 + RegisterFileMoveCost; 3154 3155 // For extractions we just need to shuffle the element to index 0, which 3156 // should be very cheap (assume cost = 1). For insertions we need to shuffle 3157 // the elements to its destination. In both cases we must handle the 3158 // subvector move(s). 3159 // If the vector type is already less than 128-bits then don't reduce it. 3160 // TODO: Under what circumstances should we shuffle using the full width? 3161 InstructionCost ShuffleCost = 1; 3162 if (Opcode == Instruction::InsertElement) { 3163 auto *SubTy = cast<VectorType>(Val); 3164 EVT VT = TLI->getValueType(DL, Val); 3165 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 3166 SubTy = FixedVectorType::get(ScalarType, SubNumElts); 3167 ShuffleCost = 3168 getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, None, 0, SubTy); 3169 } 3170 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 3171 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 3172 } 3173 3174 // Add to the base cost if we know that the extracted element of a vector is 3175 // destined to be moved to and used in the integer register file. 3176 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 3177 RegisterFileMoveCost += 1; 3178 3179 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 3180 } 3181 3182 InstructionCost X86TTIImpl::getScalarizationOverhead(VectorType *Ty, 3183 const APInt &DemandedElts, 3184 bool Insert, 3185 bool Extract) { 3186 InstructionCost Cost = 0; 3187 3188 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much 3189 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT. 3190 if (Insert) { 3191 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3192 MVT MScalarTy = LT.second.getScalarType(); 3193 3194 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3195 (MScalarTy.isInteger() && ST->hasSSE41()) || 3196 (MScalarTy == MVT::f32 && ST->hasSSE41())) { 3197 // For types we can insert directly, insertion into 128-bit sub vectors is 3198 // cheap, followed by a cheap chain of concatenations. 3199 if (LT.second.getSizeInBits() <= 128) { 3200 Cost += 3201 BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, false); 3202 } else { 3203 // In each 128-lane, if at least one index is demanded but not all 3204 // indices are demanded and this 128-lane is not the first 128-lane of 3205 // the legalized-vector, then this 128-lane needs a extracti128; If in 3206 // each 128-lane, there is at least one demanded index, this 128-lane 3207 // needs a inserti128. 3208 3209 // The following cases will help you build a better understanding: 3210 // Assume we insert several elements into a v8i32 vector in avx2, 3211 // Case#1: inserting into 1th index needs vpinsrd + inserti128. 3212 // Case#2: inserting into 5th index needs extracti128 + vpinsrd + 3213 // inserti128. 3214 // Case#3: inserting into 4,5,6,7 index needs 4*vpinsrd + inserti128. 3215 const int CostValue = *LT.first.getValue(); 3216 assert(CostValue >= 0 && "Negative cost!"); 3217 unsigned Num128Lanes = LT.second.getSizeInBits() / 128 * CostValue; 3218 unsigned NumElts = LT.second.getVectorNumElements() * CostValue; 3219 APInt WidenedDemandedElts = DemandedElts.zextOrSelf(NumElts); 3220 unsigned Scale = NumElts / Num128Lanes; 3221 // We iterate each 128-lane, and check if we need a 3222 // extracti128/inserti128 for this 128-lane. 3223 for (unsigned I = 0; I < NumElts; I += Scale) { 3224 APInt Mask = WidenedDemandedElts.getBitsSet(NumElts, I, I + Scale); 3225 APInt MaskedDE = Mask & WidenedDemandedElts; 3226 unsigned Population = MaskedDE.countPopulation(); 3227 Cost += (Population > 0 && Population != Scale && 3228 I % LT.second.getVectorNumElements() != 0); 3229 Cost += Population > 0; 3230 } 3231 Cost += DemandedElts.countPopulation(); 3232 3233 // For vXf32 cases, insertion into the 0'th index in each v4f32 3234 // 128-bit vector is free. 3235 // NOTE: This assumes legalization widens vXf32 vectors. 3236 if (MScalarTy == MVT::f32) 3237 for (unsigned i = 0, e = cast<FixedVectorType>(Ty)->getNumElements(); 3238 i < e; i += 4) 3239 if (DemandedElts[i]) 3240 Cost--; 3241 } 3242 } else if (LT.second.isVector()) { 3243 // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded 3244 // integer element as a SCALAR_TO_VECTOR, then we build the vector as a 3245 // series of UNPCK followed by CONCAT_VECTORS - all of these can be 3246 // considered cheap. 3247 if (Ty->isIntOrIntVectorTy()) 3248 Cost += DemandedElts.countPopulation(); 3249 3250 // Get the smaller of the legalized or original pow2-extended number of 3251 // vector elements, which represents the number of unpacks we'll end up 3252 // performing. 3253 unsigned NumElts = LT.second.getVectorNumElements(); 3254 unsigned Pow2Elts = 3255 PowerOf2Ceil(cast<FixedVectorType>(Ty)->getNumElements()); 3256 Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first; 3257 } 3258 } 3259 3260 // TODO: Use default extraction for now, but we should investigate extending this 3261 // to handle repeated subvector extraction. 3262 if (Extract) 3263 Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, false, Extract); 3264 3265 return Cost; 3266 } 3267 3268 InstructionCost X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 3269 MaybeAlign Alignment, 3270 unsigned AddressSpace, 3271 TTI::TargetCostKind CostKind, 3272 const Instruction *I) { 3273 // TODO: Handle other cost kinds. 3274 if (CostKind != TTI::TCK_RecipThroughput) { 3275 if (auto *SI = dyn_cast_or_null<StoreInst>(I)) { 3276 // Store instruction with index and scale costs 2 Uops. 3277 // Check the preceding GEP to identify non-const indices. 3278 if (auto *GEP = dyn_cast<GetElementPtrInst>(SI->getPointerOperand())) { 3279 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3280 return TTI::TCC_Basic * 2; 3281 } 3282 } 3283 return TTI::TCC_Basic; 3284 } 3285 3286 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 3287 "Invalid Opcode"); 3288 // Type legalization can't handle structs 3289 if (TLI->getValueType(DL, Src, true) == MVT::Other) 3290 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3291 CostKind); 3292 3293 // Legalize the type. 3294 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 3295 3296 auto *VTy = dyn_cast<FixedVectorType>(Src); 3297 3298 // Handle the simple case of non-vectors. 3299 // NOTE: this assumes that legalization never creates vector from scalars! 3300 if (!VTy || !LT.second.isVector()) 3301 // Each load/store unit costs 1. 3302 return LT.first * 1; 3303 3304 bool IsLoad = Opcode == Instruction::Load; 3305 3306 Type *EltTy = VTy->getElementType(); 3307 3308 const int EltTyBits = DL.getTypeSizeInBits(EltTy); 3309 3310 InstructionCost Cost = 0; 3311 3312 // Source of truth: how many elements were there in the original IR vector? 3313 const unsigned SrcNumElt = VTy->getNumElements(); 3314 3315 // How far have we gotten? 3316 int NumEltRemaining = SrcNumElt; 3317 // Note that we intentionally capture by-reference, NumEltRemaining changes. 3318 auto NumEltDone = [&]() { return SrcNumElt - NumEltRemaining; }; 3319 3320 const int MaxLegalOpSizeBytes = divideCeil(LT.second.getSizeInBits(), 8); 3321 3322 // Note that even if we can store 64 bits of an XMM, we still operate on XMM. 3323 const unsigned XMMBits = 128; 3324 if (XMMBits % EltTyBits != 0) 3325 // Vector size must be a multiple of the element size. I.e. no padding. 3326 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3327 CostKind); 3328 const int NumEltPerXMM = XMMBits / EltTyBits; 3329 3330 auto *XMMVecTy = FixedVectorType::get(EltTy, NumEltPerXMM); 3331 3332 for (int CurrOpSizeBytes = MaxLegalOpSizeBytes, SubVecEltsLeft = 0; 3333 NumEltRemaining > 0; CurrOpSizeBytes /= 2) { 3334 // How many elements would a single op deal with at once? 3335 if ((8 * CurrOpSizeBytes) % EltTyBits != 0) 3336 // Vector size must be a multiple of the element size. I.e. no padding. 3337 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3338 CostKind); 3339 int CurrNumEltPerOp = (8 * CurrOpSizeBytes) / EltTyBits; 3340 3341 assert(CurrOpSizeBytes > 0 && CurrNumEltPerOp > 0 && "How'd we get here?"); 3342 assert((((NumEltRemaining * EltTyBits) < (2 * 8 * CurrOpSizeBytes)) || 3343 (CurrOpSizeBytes == MaxLegalOpSizeBytes)) && 3344 "Unless we haven't halved the op size yet, " 3345 "we have less than two op's sized units of work left."); 3346 3347 auto *CurrVecTy = CurrNumEltPerOp > NumEltPerXMM 3348 ? FixedVectorType::get(EltTy, CurrNumEltPerOp) 3349 : XMMVecTy; 3350 3351 assert(CurrVecTy->getNumElements() % CurrNumEltPerOp == 0 && 3352 "After halving sizes, the vector elt count is no longer a multiple " 3353 "of number of elements per operation?"); 3354 auto *CoalescedVecTy = 3355 CurrNumEltPerOp == 1 3356 ? CurrVecTy 3357 : FixedVectorType::get( 3358 IntegerType::get(Src->getContext(), 3359 EltTyBits * CurrNumEltPerOp), 3360 CurrVecTy->getNumElements() / CurrNumEltPerOp); 3361 assert(DL.getTypeSizeInBits(CoalescedVecTy) == 3362 DL.getTypeSizeInBits(CurrVecTy) && 3363 "coalesciing elements doesn't change vector width."); 3364 3365 while (NumEltRemaining > 0) { 3366 assert(SubVecEltsLeft >= 0 && "Subreg element count overconsumtion?"); 3367 3368 // Can we use this vector size, as per the remaining element count? 3369 // Iff the vector is naturally aligned, we can do a wide load regardless. 3370 if (NumEltRemaining < CurrNumEltPerOp && 3371 (!IsLoad || Alignment.valueOrOne() < CurrOpSizeBytes) && 3372 CurrOpSizeBytes != 1) 3373 break; // Try smalled vector size. 3374 3375 bool Is0thSubVec = (NumEltDone() % LT.second.getVectorNumElements()) == 0; 3376 3377 // If we have fully processed the previous reg, we need to replenish it. 3378 if (SubVecEltsLeft == 0) { 3379 SubVecEltsLeft += CurrVecTy->getNumElements(); 3380 // And that's free only for the 0'th subvector of a legalized vector. 3381 if (!Is0thSubVec) 3382 Cost += getShuffleCost(IsLoad ? TTI::ShuffleKind::SK_InsertSubvector 3383 : TTI::ShuffleKind::SK_ExtractSubvector, 3384 VTy, None, NumEltDone(), CurrVecTy); 3385 } 3386 3387 // While we can directly load/store ZMM, YMM, and 64-bit halves of XMM, 3388 // for smaller widths (32/16/8) we have to insert/extract them separately. 3389 // Again, it's free for the 0'th subreg (if op is 32/64 bit wide, 3390 // but let's pretend that it is also true for 16/8 bit wide ops...) 3391 if (CurrOpSizeBytes <= 32 / 8 && !Is0thSubVec) { 3392 int NumEltDoneInCurrXMM = NumEltDone() % NumEltPerXMM; 3393 assert(NumEltDoneInCurrXMM % CurrNumEltPerOp == 0 && ""); 3394 int CoalescedVecEltIdx = NumEltDoneInCurrXMM / CurrNumEltPerOp; 3395 APInt DemandedElts = 3396 APInt::getBitsSet(CoalescedVecTy->getNumElements(), 3397 CoalescedVecEltIdx, CoalescedVecEltIdx + 1); 3398 assert(DemandedElts.countPopulation() == 1 && "Inserting single value"); 3399 Cost += getScalarizationOverhead(CoalescedVecTy, DemandedElts, IsLoad, 3400 !IsLoad); 3401 } 3402 3403 // This isn't exactly right. We're using slow unaligned 32-byte accesses 3404 // as a proxy for a double-pumped AVX memory interface such as on 3405 // Sandybridge. 3406 if (CurrOpSizeBytes == 32 && ST->isUnalignedMem32Slow()) 3407 Cost += 2; 3408 else 3409 Cost += 1; 3410 3411 SubVecEltsLeft -= CurrNumEltPerOp; 3412 NumEltRemaining -= CurrNumEltPerOp; 3413 Alignment = commonAlignment(Alignment.valueOrOne(), CurrOpSizeBytes); 3414 } 3415 } 3416 3417 assert(NumEltRemaining <= 0 && "Should have processed all the elements."); 3418 3419 return Cost; 3420 } 3421 3422 InstructionCost 3423 X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, Align Alignment, 3424 unsigned AddressSpace, 3425 TTI::TargetCostKind CostKind) { 3426 bool IsLoad = (Instruction::Load == Opcode); 3427 bool IsStore = (Instruction::Store == Opcode); 3428 3429 auto *SrcVTy = dyn_cast<FixedVectorType>(SrcTy); 3430 if (!SrcVTy) 3431 // To calculate scalar take the regular cost, without mask 3432 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace, CostKind); 3433 3434 unsigned NumElem = SrcVTy->getNumElements(); 3435 auto *MaskTy = 3436 FixedVectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 3437 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, Alignment)) || 3438 (IsStore && !isLegalMaskedStore(SrcVTy, Alignment)) || 3439 !isPowerOf2_32(NumElem)) { 3440 // Scalarization 3441 APInt DemandedElts = APInt::getAllOnesValue(NumElem); 3442 InstructionCost MaskSplitCost = 3443 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 3444 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 3445 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr, 3446 CmpInst::BAD_ICMP_PREDICATE, CostKind); 3447 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 3448 InstructionCost MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 3449 InstructionCost ValueSplitCost = 3450 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore); 3451 InstructionCost MemopCost = 3452 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3453 Alignment, AddressSpace, CostKind); 3454 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 3455 } 3456 3457 // Legalize the type. 3458 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3459 auto VT = TLI->getValueType(DL, SrcVTy); 3460 InstructionCost Cost = 0; 3461 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 3462 LT.second.getVectorNumElements() == NumElem) 3463 // Promotion requires expand/truncate for data and a shuffle for mask. 3464 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, None, 0, nullptr) + 3465 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, None, 0, nullptr); 3466 3467 else if (LT.second.getVectorNumElements() > NumElem) { 3468 auto *NewMaskTy = FixedVectorType::get(MaskTy->getElementType(), 3469 LT.second.getVectorNumElements()); 3470 // Expanding requires fill mask with zeroes 3471 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, None, 0, MaskTy); 3472 } 3473 3474 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 3475 if (!ST->hasAVX512()) 3476 return Cost + LT.first * (IsLoad ? 2 : 8); 3477 3478 // AVX-512 masked load/store is cheapper 3479 return Cost + LT.first; 3480 } 3481 3482 InstructionCost X86TTIImpl::getAddressComputationCost(Type *Ty, 3483 ScalarEvolution *SE, 3484 const SCEV *Ptr) { 3485 // Address computations in vectorized code with non-consecutive addresses will 3486 // likely result in more instructions compared to scalar code where the 3487 // computation can more often be merged into the index mode. The resulting 3488 // extra micro-ops can significantly decrease throughput. 3489 const unsigned NumVectorInstToHideOverhead = 10; 3490 3491 // Cost modeling of Strided Access Computation is hidden by the indexing 3492 // modes of X86 regardless of the stride value. We dont believe that there 3493 // is a difference between constant strided access in gerenal and constant 3494 // strided value which is less than or equal to 64. 3495 // Even in the case of (loop invariant) stride whose value is not known at 3496 // compile time, the address computation will not incur more than one extra 3497 // ADD instruction. 3498 if (Ty->isVectorTy() && SE) { 3499 if (!BaseT::isStridedAccess(Ptr)) 3500 return NumVectorInstToHideOverhead; 3501 if (!BaseT::getConstantStrideStep(SE, Ptr)) 3502 return 1; 3503 } 3504 3505 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 3506 } 3507 3508 InstructionCost 3509 X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 3510 bool IsPairwise, 3511 TTI::TargetCostKind CostKind) { 3512 // Just use the default implementation for pair reductions. 3513 if (IsPairwise) 3514 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise, CostKind); 3515 3516 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3517 // and make it as the cost. 3518 3519 static const CostTblEntry SLMCostTblNoPairWise[] = { 3520 { ISD::FADD, MVT::v2f64, 3 }, 3521 { ISD::ADD, MVT::v2i64, 5 }, 3522 }; 3523 3524 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3525 { ISD::FADD, MVT::v2f64, 2 }, 3526 { ISD::FADD, MVT::v2f32, 2 }, 3527 { ISD::FADD, MVT::v4f32, 4 }, 3528 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 3529 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 3530 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 3531 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 3532 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 3533 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 3534 { ISD::ADD, MVT::v2i8, 2 }, 3535 { ISD::ADD, MVT::v4i8, 2 }, 3536 { ISD::ADD, MVT::v8i8, 2 }, 3537 { ISD::ADD, MVT::v16i8, 3 }, 3538 }; 3539 3540 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3541 { ISD::FADD, MVT::v4f64, 3 }, 3542 { ISD::FADD, MVT::v4f32, 3 }, 3543 { ISD::FADD, MVT::v8f32, 4 }, 3544 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 3545 { ISD::ADD, MVT::v4i64, 3 }, 3546 { ISD::ADD, MVT::v8i32, 5 }, 3547 { ISD::ADD, MVT::v16i16, 5 }, 3548 { ISD::ADD, MVT::v32i8, 4 }, 3549 }; 3550 3551 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3552 assert(ISD && "Invalid opcode"); 3553 3554 // Before legalizing the type, give a chance to look up illegal narrow types 3555 // in the table. 3556 // FIXME: Is there a better way to do this? 3557 EVT VT = TLI->getValueType(DL, ValTy); 3558 if (VT.isSimple()) { 3559 MVT MTy = VT.getSimpleVT(); 3560 if (ST->isSLM()) 3561 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3562 return Entry->Cost; 3563 3564 if (ST->hasAVX()) 3565 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3566 return Entry->Cost; 3567 3568 if (ST->hasSSE2()) 3569 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3570 return Entry->Cost; 3571 } 3572 3573 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3574 3575 MVT MTy = LT.second; 3576 3577 auto *ValVTy = cast<FixedVectorType>(ValTy); 3578 3579 // Special case: vXi8 mul reductions are performed as vXi16. 3580 if (ISD == ISD::MUL && MTy.getScalarType() == MVT::i8) { 3581 auto *WideSclTy = IntegerType::get(ValVTy->getContext(), 16); 3582 auto *WideVecTy = FixedVectorType::get(WideSclTy, ValVTy->getNumElements()); 3583 return getCastInstrCost(Instruction::ZExt, WideVecTy, ValTy, 3584 TargetTransformInfo::CastContextHint::None, 3585 CostKind) + 3586 getArithmeticReductionCost(Opcode, WideVecTy, IsPairwise, CostKind); 3587 } 3588 3589 InstructionCost ArithmeticCost = 0; 3590 if (LT.first != 1 && MTy.isVector() && 3591 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3592 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3593 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3594 MTy.getVectorNumElements()); 3595 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3596 ArithmeticCost *= LT.first - 1; 3597 } 3598 3599 if (ST->isSLM()) 3600 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3601 return ArithmeticCost + Entry->Cost; 3602 3603 if (ST->hasAVX()) 3604 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3605 return ArithmeticCost + Entry->Cost; 3606 3607 if (ST->hasSSE2()) 3608 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3609 return ArithmeticCost + Entry->Cost; 3610 3611 // FIXME: These assume a naive kshift+binop lowering, which is probably 3612 // conservative in most cases. 3613 static const CostTblEntry AVX512BoolReduction[] = { 3614 { ISD::AND, MVT::v2i1, 3 }, 3615 { ISD::AND, MVT::v4i1, 5 }, 3616 { ISD::AND, MVT::v8i1, 7 }, 3617 { ISD::AND, MVT::v16i1, 9 }, 3618 { ISD::AND, MVT::v32i1, 11 }, 3619 { ISD::AND, MVT::v64i1, 13 }, 3620 { ISD::OR, MVT::v2i1, 3 }, 3621 { ISD::OR, MVT::v4i1, 5 }, 3622 { ISD::OR, MVT::v8i1, 7 }, 3623 { ISD::OR, MVT::v16i1, 9 }, 3624 { ISD::OR, MVT::v32i1, 11 }, 3625 { ISD::OR, MVT::v64i1, 13 }, 3626 }; 3627 3628 static const CostTblEntry AVX2BoolReduction[] = { 3629 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 3630 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 3631 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 3632 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 3633 }; 3634 3635 static const CostTblEntry AVX1BoolReduction[] = { 3636 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 3637 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 3638 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3639 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3640 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 3641 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 3642 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3643 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3644 }; 3645 3646 static const CostTblEntry SSE2BoolReduction[] = { 3647 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 3648 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 3649 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 3650 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 3651 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 3652 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 3653 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 3654 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 3655 }; 3656 3657 // Handle bool allof/anyof patterns. 3658 if (ValVTy->getElementType()->isIntegerTy(1)) { 3659 InstructionCost ArithmeticCost = 0; 3660 if (LT.first != 1 && MTy.isVector() && 3661 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3662 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3663 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3664 MTy.getVectorNumElements()); 3665 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3666 ArithmeticCost *= LT.first - 1; 3667 } 3668 3669 if (ST->hasAVX512()) 3670 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 3671 return ArithmeticCost + Entry->Cost; 3672 if (ST->hasAVX2()) 3673 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 3674 return ArithmeticCost + Entry->Cost; 3675 if (ST->hasAVX()) 3676 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 3677 return ArithmeticCost + Entry->Cost; 3678 if (ST->hasSSE2()) 3679 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 3680 return ArithmeticCost + Entry->Cost; 3681 3682 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise, 3683 CostKind); 3684 } 3685 3686 unsigned NumVecElts = ValVTy->getNumElements(); 3687 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 3688 3689 // Special case power of 2 reductions where the scalar type isn't changed 3690 // by type legalization. 3691 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 3692 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise, 3693 CostKind); 3694 3695 InstructionCost ReductionCost = 0; 3696 3697 auto *Ty = ValVTy; 3698 if (LT.first != 1 && MTy.isVector() && 3699 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3700 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3701 Ty = FixedVectorType::get(ValVTy->getElementType(), 3702 MTy.getVectorNumElements()); 3703 ReductionCost = getArithmeticInstrCost(Opcode, Ty, CostKind); 3704 ReductionCost *= LT.first - 1; 3705 NumVecElts = MTy.getVectorNumElements(); 3706 } 3707 3708 // Now handle reduction with the legal type, taking into account size changes 3709 // at each level. 3710 while (NumVecElts > 1) { 3711 // Determine the size of the remaining vector we need to reduce. 3712 unsigned Size = NumVecElts * ScalarSize; 3713 NumVecElts /= 2; 3714 // If we're reducing from 256/512 bits, use an extract_subvector. 3715 if (Size > 128) { 3716 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 3717 ReductionCost += 3718 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 3719 Ty = SubTy; 3720 } else if (Size == 128) { 3721 // Reducing from 128 bits is a permute of v2f64/v2i64. 3722 FixedVectorType *ShufTy; 3723 if (ValVTy->isFloatingPointTy()) 3724 ShufTy = 3725 FixedVectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 3726 else 3727 ShufTy = 3728 FixedVectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 3729 ReductionCost += 3730 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3731 } else if (Size == 64) { 3732 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3733 FixedVectorType *ShufTy; 3734 if (ValVTy->isFloatingPointTy()) 3735 ShufTy = 3736 FixedVectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 3737 else 3738 ShufTy = 3739 FixedVectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 3740 ReductionCost += 3741 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3742 } else { 3743 // Reducing from smaller size is a shift by immediate. 3744 auto *ShiftTy = FixedVectorType::get( 3745 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 3746 ReductionCost += getArithmeticInstrCost( 3747 Instruction::LShr, ShiftTy, CostKind, 3748 TargetTransformInfo::OK_AnyValue, 3749 TargetTransformInfo::OK_UniformConstantValue, 3750 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3751 } 3752 3753 // Add the arithmetic op for this level. 3754 ReductionCost += getArithmeticInstrCost(Opcode, Ty, CostKind); 3755 } 3756 3757 // Add the final extract element to the cost. 3758 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3759 } 3760 3761 InstructionCost X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, 3762 bool IsUnsigned) { 3763 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3764 3765 MVT MTy = LT.second; 3766 3767 int ISD; 3768 if (Ty->isIntOrIntVectorTy()) { 3769 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3770 } else { 3771 assert(Ty->isFPOrFPVectorTy() && 3772 "Expected float point or integer vector type."); 3773 ISD = ISD::FMINNUM; 3774 } 3775 3776 static const CostTblEntry SSE1CostTbl[] = { 3777 {ISD::FMINNUM, MVT::v4f32, 1}, 3778 }; 3779 3780 static const CostTblEntry SSE2CostTbl[] = { 3781 {ISD::FMINNUM, MVT::v2f64, 1}, 3782 {ISD::SMIN, MVT::v8i16, 1}, 3783 {ISD::UMIN, MVT::v16i8, 1}, 3784 }; 3785 3786 static const CostTblEntry SSE41CostTbl[] = { 3787 {ISD::SMIN, MVT::v4i32, 1}, 3788 {ISD::UMIN, MVT::v4i32, 1}, 3789 {ISD::UMIN, MVT::v8i16, 1}, 3790 {ISD::SMIN, MVT::v16i8, 1}, 3791 }; 3792 3793 static const CostTblEntry SSE42CostTbl[] = { 3794 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 3795 }; 3796 3797 static const CostTblEntry AVX1CostTbl[] = { 3798 {ISD::FMINNUM, MVT::v8f32, 1}, 3799 {ISD::FMINNUM, MVT::v4f64, 1}, 3800 {ISD::SMIN, MVT::v8i32, 3}, 3801 {ISD::UMIN, MVT::v8i32, 3}, 3802 {ISD::SMIN, MVT::v16i16, 3}, 3803 {ISD::UMIN, MVT::v16i16, 3}, 3804 {ISD::SMIN, MVT::v32i8, 3}, 3805 {ISD::UMIN, MVT::v32i8, 3}, 3806 }; 3807 3808 static const CostTblEntry AVX2CostTbl[] = { 3809 {ISD::SMIN, MVT::v8i32, 1}, 3810 {ISD::UMIN, MVT::v8i32, 1}, 3811 {ISD::SMIN, MVT::v16i16, 1}, 3812 {ISD::UMIN, MVT::v16i16, 1}, 3813 {ISD::SMIN, MVT::v32i8, 1}, 3814 {ISD::UMIN, MVT::v32i8, 1}, 3815 }; 3816 3817 static const CostTblEntry AVX512CostTbl[] = { 3818 {ISD::FMINNUM, MVT::v16f32, 1}, 3819 {ISD::FMINNUM, MVT::v8f64, 1}, 3820 {ISD::SMIN, MVT::v2i64, 1}, 3821 {ISD::UMIN, MVT::v2i64, 1}, 3822 {ISD::SMIN, MVT::v4i64, 1}, 3823 {ISD::UMIN, MVT::v4i64, 1}, 3824 {ISD::SMIN, MVT::v8i64, 1}, 3825 {ISD::UMIN, MVT::v8i64, 1}, 3826 {ISD::SMIN, MVT::v16i32, 1}, 3827 {ISD::UMIN, MVT::v16i32, 1}, 3828 }; 3829 3830 static const CostTblEntry AVX512BWCostTbl[] = { 3831 {ISD::SMIN, MVT::v32i16, 1}, 3832 {ISD::UMIN, MVT::v32i16, 1}, 3833 {ISD::SMIN, MVT::v64i8, 1}, 3834 {ISD::UMIN, MVT::v64i8, 1}, 3835 }; 3836 3837 // If we have a native MIN/MAX instruction for this type, use it. 3838 if (ST->hasBWI()) 3839 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3840 return LT.first * Entry->Cost; 3841 3842 if (ST->hasAVX512()) 3843 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3844 return LT.first * Entry->Cost; 3845 3846 if (ST->hasAVX2()) 3847 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3848 return LT.first * Entry->Cost; 3849 3850 if (ST->hasAVX()) 3851 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3852 return LT.first * Entry->Cost; 3853 3854 if (ST->hasSSE42()) 3855 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3856 return LT.first * Entry->Cost; 3857 3858 if (ST->hasSSE41()) 3859 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3860 return LT.first * Entry->Cost; 3861 3862 if (ST->hasSSE2()) 3863 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3864 return LT.first * Entry->Cost; 3865 3866 if (ST->hasSSE1()) 3867 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3868 return LT.first * Entry->Cost; 3869 3870 unsigned CmpOpcode; 3871 if (Ty->isFPOrFPVectorTy()) { 3872 CmpOpcode = Instruction::FCmp; 3873 } else { 3874 assert(Ty->isIntOrIntVectorTy() && 3875 "expecting floating point or integer type for min/max reduction"); 3876 CmpOpcode = Instruction::ICmp; 3877 } 3878 3879 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 3880 // Otherwise fall back to cmp+select. 3881 InstructionCost Result = 3882 getCmpSelInstrCost(CmpOpcode, Ty, CondTy, CmpInst::BAD_ICMP_PREDICATE, 3883 CostKind) + 3884 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, 3885 CmpInst::BAD_ICMP_PREDICATE, CostKind); 3886 return Result; 3887 } 3888 3889 InstructionCost 3890 X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 3891 bool IsPairwise, bool IsUnsigned, 3892 TTI::TargetCostKind CostKind) { 3893 // Just use the default implementation for pair reductions. 3894 if (IsPairwise) 3895 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned, 3896 CostKind); 3897 3898 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3899 3900 MVT MTy = LT.second; 3901 3902 int ISD; 3903 if (ValTy->isIntOrIntVectorTy()) { 3904 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3905 } else { 3906 assert(ValTy->isFPOrFPVectorTy() && 3907 "Expected float point or integer vector type."); 3908 ISD = ISD::FMINNUM; 3909 } 3910 3911 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3912 // and make it as the cost. 3913 3914 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3915 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 3916 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 3917 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 3918 }; 3919 3920 static const CostTblEntry SSE41CostTblNoPairWise[] = { 3921 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 3922 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 3923 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 3924 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 3925 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 3926 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 3927 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 3928 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 3929 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 3930 {ISD::SMIN, MVT::v16i8, 6}, 3931 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 3932 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 3933 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 3934 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 3935 }; 3936 3937 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3938 {ISD::SMIN, MVT::v16i16, 6}, 3939 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 3940 {ISD::SMIN, MVT::v32i8, 8}, 3941 {ISD::UMIN, MVT::v32i8, 8}, 3942 }; 3943 3944 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 3945 {ISD::SMIN, MVT::v32i16, 8}, 3946 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 3947 {ISD::SMIN, MVT::v64i8, 10}, 3948 {ISD::UMIN, MVT::v64i8, 10}, 3949 }; 3950 3951 // Before legalizing the type, give a chance to look up illegal narrow types 3952 // in the table. 3953 // FIXME: Is there a better way to do this? 3954 EVT VT = TLI->getValueType(DL, ValTy); 3955 if (VT.isSimple()) { 3956 MVT MTy = VT.getSimpleVT(); 3957 if (ST->hasBWI()) 3958 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3959 return Entry->Cost; 3960 3961 if (ST->hasAVX()) 3962 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3963 return Entry->Cost; 3964 3965 if (ST->hasSSE41()) 3966 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3967 return Entry->Cost; 3968 3969 if (ST->hasSSE2()) 3970 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3971 return Entry->Cost; 3972 } 3973 3974 auto *ValVTy = cast<FixedVectorType>(ValTy); 3975 unsigned NumVecElts = ValVTy->getNumElements(); 3976 3977 auto *Ty = ValVTy; 3978 InstructionCost MinMaxCost = 0; 3979 if (LT.first != 1 && MTy.isVector() && 3980 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3981 // Type needs to be split. We need LT.first - 1 operations ops. 3982 Ty = FixedVectorType::get(ValVTy->getElementType(), 3983 MTy.getVectorNumElements()); 3984 auto *SubCondTy = FixedVectorType::get(CondTy->getElementType(), 3985 MTy.getVectorNumElements()); 3986 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3987 MinMaxCost *= LT.first - 1; 3988 NumVecElts = MTy.getVectorNumElements(); 3989 } 3990 3991 if (ST->hasBWI()) 3992 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3993 return MinMaxCost + Entry->Cost; 3994 3995 if (ST->hasAVX()) 3996 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3997 return MinMaxCost + Entry->Cost; 3998 3999 if (ST->hasSSE41()) 4000 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4001 return MinMaxCost + Entry->Cost; 4002 4003 if (ST->hasSSE2()) 4004 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4005 return MinMaxCost + Entry->Cost; 4006 4007 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 4008 4009 // Special case power of 2 reductions where the scalar type isn't changed 4010 // by type legalization. 4011 if (!isPowerOf2_32(ValVTy->getNumElements()) || 4012 ScalarSize != MTy.getScalarSizeInBits()) 4013 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned, 4014 CostKind); 4015 4016 // Now handle reduction with the legal type, taking into account size changes 4017 // at each level. 4018 while (NumVecElts > 1) { 4019 // Determine the size of the remaining vector we need to reduce. 4020 unsigned Size = NumVecElts * ScalarSize; 4021 NumVecElts /= 2; 4022 // If we're reducing from 256/512 bits, use an extract_subvector. 4023 if (Size > 128) { 4024 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 4025 MinMaxCost += 4026 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 4027 Ty = SubTy; 4028 } else if (Size == 128) { 4029 // Reducing from 128 bits is a permute of v2f64/v2i64. 4030 VectorType *ShufTy; 4031 if (ValTy->isFloatingPointTy()) 4032 ShufTy = 4033 FixedVectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 4034 else 4035 ShufTy = FixedVectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 4036 MinMaxCost += 4037 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4038 } else if (Size == 64) { 4039 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 4040 FixedVectorType *ShufTy; 4041 if (ValTy->isFloatingPointTy()) 4042 ShufTy = FixedVectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 4043 else 4044 ShufTy = FixedVectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 4045 MinMaxCost += 4046 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4047 } else { 4048 // Reducing from smaller size is a shift by immediate. 4049 auto *ShiftTy = FixedVectorType::get( 4050 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 4051 MinMaxCost += getArithmeticInstrCost( 4052 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, 4053 TargetTransformInfo::OK_AnyValue, 4054 TargetTransformInfo::OK_UniformConstantValue, 4055 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 4056 } 4057 4058 // Add the arithmetic op for this level. 4059 auto *SubCondTy = 4060 FixedVectorType::get(CondTy->getElementType(), Ty->getNumElements()); 4061 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4062 } 4063 4064 // Add the final extract element to the cost. 4065 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 4066 } 4067 4068 /// Calculate the cost of materializing a 64-bit value. This helper 4069 /// method might only calculate a fraction of a larger immediate. Therefore it 4070 /// is valid to return a cost of ZERO. 4071 InstructionCost X86TTIImpl::getIntImmCost(int64_t Val) { 4072 if (Val == 0) 4073 return TTI::TCC_Free; 4074 4075 if (isInt<32>(Val)) 4076 return TTI::TCC_Basic; 4077 4078 return 2 * TTI::TCC_Basic; 4079 } 4080 4081 InstructionCost X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 4082 TTI::TargetCostKind CostKind) { 4083 assert(Ty->isIntegerTy()); 4084 4085 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4086 if (BitSize == 0) 4087 return ~0U; 4088 4089 // Never hoist constants larger than 128bit, because this might lead to 4090 // incorrect code generation or assertions in codegen. 4091 // Fixme: Create a cost model for types larger than i128 once the codegen 4092 // issues have been fixed. 4093 if (BitSize > 128) 4094 return TTI::TCC_Free; 4095 4096 if (Imm == 0) 4097 return TTI::TCC_Free; 4098 4099 // Sign-extend all constants to a multiple of 64-bit. 4100 APInt ImmVal = Imm; 4101 if (BitSize % 64 != 0) 4102 ImmVal = Imm.sext(alignTo(BitSize, 64)); 4103 4104 // Split the constant into 64-bit chunks and calculate the cost for each 4105 // chunk. 4106 InstructionCost Cost = 0; 4107 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 4108 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 4109 int64_t Val = Tmp.getSExtValue(); 4110 Cost += getIntImmCost(Val); 4111 } 4112 // We need at least one instruction to materialize the constant. 4113 return std::max<InstructionCost>(1, Cost); 4114 } 4115 4116 InstructionCost X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, 4117 const APInt &Imm, Type *Ty, 4118 TTI::TargetCostKind CostKind, 4119 Instruction *Inst) { 4120 assert(Ty->isIntegerTy()); 4121 4122 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4123 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4124 // here, so that constant hoisting will ignore this constant. 4125 if (BitSize == 0) 4126 return TTI::TCC_Free; 4127 4128 unsigned ImmIdx = ~0U; 4129 switch (Opcode) { 4130 default: 4131 return TTI::TCC_Free; 4132 case Instruction::GetElementPtr: 4133 // Always hoist the base address of a GetElementPtr. This prevents the 4134 // creation of new constants for every base constant that gets constant 4135 // folded with the offset. 4136 if (Idx == 0) 4137 return 2 * TTI::TCC_Basic; 4138 return TTI::TCC_Free; 4139 case Instruction::Store: 4140 ImmIdx = 0; 4141 break; 4142 case Instruction::ICmp: 4143 // This is an imperfect hack to prevent constant hoisting of 4144 // compares that might be trying to check if a 64-bit value fits in 4145 // 32-bits. The backend can optimize these cases using a right shift by 32. 4146 // Ideally we would check the compare predicate here. There also other 4147 // similar immediates the backend can use shifts for. 4148 if (Idx == 1 && Imm.getBitWidth() == 64) { 4149 uint64_t ImmVal = Imm.getZExtValue(); 4150 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 4151 return TTI::TCC_Free; 4152 } 4153 ImmIdx = 1; 4154 break; 4155 case Instruction::And: 4156 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 4157 // by using a 32-bit operation with implicit zero extension. Detect such 4158 // immediates here as the normal path expects bit 31 to be sign extended. 4159 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 4160 return TTI::TCC_Free; 4161 ImmIdx = 1; 4162 break; 4163 case Instruction::Add: 4164 case Instruction::Sub: 4165 // For add/sub, we can use the opposite instruction for INT32_MIN. 4166 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 4167 return TTI::TCC_Free; 4168 ImmIdx = 1; 4169 break; 4170 case Instruction::UDiv: 4171 case Instruction::SDiv: 4172 case Instruction::URem: 4173 case Instruction::SRem: 4174 // Division by constant is typically expanded later into a different 4175 // instruction sequence. This completely changes the constants. 4176 // Report them as "free" to stop ConstantHoist from marking them as opaque. 4177 return TTI::TCC_Free; 4178 case Instruction::Mul: 4179 case Instruction::Or: 4180 case Instruction::Xor: 4181 ImmIdx = 1; 4182 break; 4183 // Always return TCC_Free for the shift value of a shift instruction. 4184 case Instruction::Shl: 4185 case Instruction::LShr: 4186 case Instruction::AShr: 4187 if (Idx == 1) 4188 return TTI::TCC_Free; 4189 break; 4190 case Instruction::Trunc: 4191 case Instruction::ZExt: 4192 case Instruction::SExt: 4193 case Instruction::IntToPtr: 4194 case Instruction::PtrToInt: 4195 case Instruction::BitCast: 4196 case Instruction::PHI: 4197 case Instruction::Call: 4198 case Instruction::Select: 4199 case Instruction::Ret: 4200 case Instruction::Load: 4201 break; 4202 } 4203 4204 if (Idx == ImmIdx) { 4205 int NumConstants = divideCeil(BitSize, 64); 4206 InstructionCost Cost = X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4207 return (Cost <= NumConstants * TTI::TCC_Basic) 4208 ? static_cast<int>(TTI::TCC_Free) 4209 : Cost; 4210 } 4211 4212 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4213 } 4214 4215 InstructionCost X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 4216 const APInt &Imm, Type *Ty, 4217 TTI::TargetCostKind CostKind) { 4218 assert(Ty->isIntegerTy()); 4219 4220 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4221 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4222 // here, so that constant hoisting will ignore this constant. 4223 if (BitSize == 0) 4224 return TTI::TCC_Free; 4225 4226 switch (IID) { 4227 default: 4228 return TTI::TCC_Free; 4229 case Intrinsic::sadd_with_overflow: 4230 case Intrinsic::uadd_with_overflow: 4231 case Intrinsic::ssub_with_overflow: 4232 case Intrinsic::usub_with_overflow: 4233 case Intrinsic::smul_with_overflow: 4234 case Intrinsic::umul_with_overflow: 4235 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 4236 return TTI::TCC_Free; 4237 break; 4238 case Intrinsic::experimental_stackmap: 4239 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4240 return TTI::TCC_Free; 4241 break; 4242 case Intrinsic::experimental_patchpoint_void: 4243 case Intrinsic::experimental_patchpoint_i64: 4244 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4245 return TTI::TCC_Free; 4246 break; 4247 } 4248 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4249 } 4250 4251 InstructionCost X86TTIImpl::getCFInstrCost(unsigned Opcode, 4252 TTI::TargetCostKind CostKind, 4253 const Instruction *I) { 4254 if (CostKind != TTI::TCK_RecipThroughput) 4255 return Opcode == Instruction::PHI ? 0 : 1; 4256 // Branches are assumed to be predicted. 4257 return 0; 4258 } 4259 4260 int X86TTIImpl::getGatherOverhead() const { 4261 // Some CPUs have more overhead for gather. The specified overhead is relative 4262 // to the Load operation. "2" is the number provided by Intel architects. This 4263 // parameter is used for cost estimation of Gather Op and comparison with 4264 // other alternatives. 4265 // TODO: Remove the explicit hasAVX512()?, That would mean we would only 4266 // enable gather with a -march. 4267 if (ST->hasAVX512() || (ST->hasAVX2() && ST->hasFastGather())) 4268 return 2; 4269 4270 return 1024; 4271 } 4272 4273 int X86TTIImpl::getScatterOverhead() const { 4274 if (ST->hasAVX512()) 4275 return 2; 4276 4277 return 1024; 4278 } 4279 4280 // Return an average cost of Gather / Scatter instruction, maybe improved later. 4281 // FIXME: Add TargetCostKind support. 4282 InstructionCost X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, 4283 const Value *Ptr, Align Alignment, 4284 unsigned AddressSpace) { 4285 4286 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 4287 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4288 4289 // Try to reduce index size from 64 bit (default for GEP) 4290 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 4291 // operation will use 16 x 64 indices which do not fit in a zmm and needs 4292 // to split. Also check that the base pointer is the same for all lanes, 4293 // and that there's at most one variable index. 4294 auto getIndexSizeInBits = [](const Value *Ptr, const DataLayout &DL) { 4295 unsigned IndexSize = DL.getPointerSizeInBits(); 4296 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 4297 if (IndexSize < 64 || !GEP) 4298 return IndexSize; 4299 4300 unsigned NumOfVarIndices = 0; 4301 const Value *Ptrs = GEP->getPointerOperand(); 4302 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 4303 return IndexSize; 4304 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 4305 if (isa<Constant>(GEP->getOperand(i))) 4306 continue; 4307 Type *IndxTy = GEP->getOperand(i)->getType(); 4308 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 4309 IndxTy = IndexVTy->getElementType(); 4310 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 4311 !isa<SExtInst>(GEP->getOperand(i))) || 4312 ++NumOfVarIndices > 1) 4313 return IndexSize; // 64 4314 } 4315 return (unsigned)32; 4316 }; 4317 4318 // Trying to reduce IndexSize to 32 bits for vector 16. 4319 // By default the IndexSize is equal to pointer size. 4320 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 4321 ? getIndexSizeInBits(Ptr, DL) 4322 : DL.getPointerSizeInBits(); 4323 4324 auto *IndexVTy = FixedVectorType::get( 4325 IntegerType::get(SrcVTy->getContext(), IndexSize), VF); 4326 std::pair<InstructionCost, MVT> IdxsLT = 4327 TLI->getTypeLegalizationCost(DL, IndexVTy); 4328 std::pair<InstructionCost, MVT> SrcLT = 4329 TLI->getTypeLegalizationCost(DL, SrcVTy); 4330 InstructionCost::CostType SplitFactor = 4331 *std::max(IdxsLT.first, SrcLT.first).getValue(); 4332 if (SplitFactor > 1) { 4333 // Handle splitting of vector of pointers 4334 auto *SplitSrcTy = 4335 FixedVectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 4336 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 4337 AddressSpace); 4338 } 4339 4340 // The gather / scatter cost is given by Intel architects. It is a rough 4341 // number since we are looking at one instruction in a time. 4342 const int GSOverhead = (Opcode == Instruction::Load) 4343 ? getGatherOverhead() 4344 : getScatterOverhead(); 4345 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4346 MaybeAlign(Alignment), AddressSpace, 4347 TTI::TCK_RecipThroughput); 4348 } 4349 4350 /// Return the cost of full scalarization of gather / scatter operation. 4351 /// 4352 /// Opcode - Load or Store instruction. 4353 /// SrcVTy - The type of the data vector that should be gathered or scattered. 4354 /// VariableMask - The mask is non-constant at compile time. 4355 /// Alignment - Alignment for one element. 4356 /// AddressSpace - pointer[s] address space. 4357 /// 4358 /// FIXME: Add TargetCostKind support. 4359 InstructionCost X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 4360 bool VariableMask, Align Alignment, 4361 unsigned AddressSpace) { 4362 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4363 APInt DemandedElts = APInt::getAllOnesValue(VF); 4364 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4365 4366 InstructionCost MaskUnpackCost = 0; 4367 if (VariableMask) { 4368 auto *MaskTy = 4369 FixedVectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 4370 MaskUnpackCost = 4371 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 4372 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 4373 Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), nullptr, 4374 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4375 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 4376 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 4377 } 4378 4379 // The cost of the scalar loads/stores. 4380 InstructionCost MemoryOpCost = 4381 VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4382 MaybeAlign(Alignment), AddressSpace, CostKind); 4383 4384 InstructionCost InsertExtractCost = 0; 4385 if (Opcode == Instruction::Load) 4386 for (unsigned i = 0; i < VF; ++i) 4387 // Add the cost of inserting each scalar load into the vector 4388 InsertExtractCost += 4389 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 4390 else 4391 for (unsigned i = 0; i < VF; ++i) 4392 // Add the cost of extracting each element out of the data vector 4393 InsertExtractCost += 4394 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 4395 4396 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 4397 } 4398 4399 /// Calculate the cost of Gather / Scatter operation 4400 InstructionCost X86TTIImpl::getGatherScatterOpCost( 4401 unsigned Opcode, Type *SrcVTy, const Value *Ptr, bool VariableMask, 4402 Align Alignment, TTI::TargetCostKind CostKind, 4403 const Instruction *I = nullptr) { 4404 if (CostKind != TTI::TCK_RecipThroughput) { 4405 if ((Opcode == Instruction::Load && 4406 isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4407 (Opcode == Instruction::Store && 4408 isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4409 return 1; 4410 return BaseT::getGatherScatterOpCost(Opcode, SrcVTy, Ptr, VariableMask, 4411 Alignment, CostKind, I); 4412 } 4413 4414 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 4415 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4416 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 4417 if (!PtrTy && Ptr->getType()->isVectorTy()) 4418 PtrTy = dyn_cast<PointerType>( 4419 cast<VectorType>(Ptr->getType())->getElementType()); 4420 assert(PtrTy && "Unexpected type for Ptr argument"); 4421 unsigned AddressSpace = PtrTy->getAddressSpace(); 4422 4423 bool Scalarize = false; 4424 if ((Opcode == Instruction::Load && 4425 !isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4426 (Opcode == Instruction::Store && 4427 !isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4428 Scalarize = true; 4429 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 4430 // Vector-4 of gather/scatter instruction does not exist on KNL. 4431 // We can extend it to 8 elements, but zeroing upper bits of 4432 // the mask vector will add more instructions. Right now we give the scalar 4433 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 4434 // is better in the VariableMask case. 4435 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 4436 Scalarize = true; 4437 4438 if (Scalarize) 4439 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 4440 AddressSpace); 4441 4442 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 4443 } 4444 4445 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 4446 TargetTransformInfo::LSRCost &C2) { 4447 // X86 specific here are "instruction number 1st priority". 4448 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 4449 C1.NumIVMuls, C1.NumBaseAdds, 4450 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 4451 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 4452 C2.NumIVMuls, C2.NumBaseAdds, 4453 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 4454 } 4455 4456 bool X86TTIImpl::canMacroFuseCmp() { 4457 return ST->hasMacroFusion() || ST->hasBranchFusion(); 4458 } 4459 4460 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, Align Alignment) { 4461 if (!ST->hasAVX()) 4462 return false; 4463 4464 // The backend can't handle a single element vector. 4465 if (isa<VectorType>(DataTy) && 4466 cast<FixedVectorType>(DataTy)->getNumElements() == 1) 4467 return false; 4468 Type *ScalarTy = DataTy->getScalarType(); 4469 4470 if (ScalarTy->isPointerTy()) 4471 return true; 4472 4473 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4474 return true; 4475 4476 if (!ScalarTy->isIntegerTy()) 4477 return false; 4478 4479 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4480 return IntWidth == 32 || IntWidth == 64 || 4481 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 4482 } 4483 4484 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, Align Alignment) { 4485 return isLegalMaskedLoad(DataType, Alignment); 4486 } 4487 4488 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 4489 unsigned DataSize = DL.getTypeStoreSize(DataType); 4490 // The only supported nontemporal loads are for aligned vectors of 16 or 32 4491 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 4492 // (the equivalent stores only require AVX). 4493 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 4494 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 4495 4496 return false; 4497 } 4498 4499 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 4500 unsigned DataSize = DL.getTypeStoreSize(DataType); 4501 4502 // SSE4A supports nontemporal stores of float and double at arbitrary 4503 // alignment. 4504 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 4505 return true; 4506 4507 // Besides the SSE4A subtarget exception above, only aligned stores are 4508 // available nontemporaly on any other subtarget. And only stores with a size 4509 // of 4..32 bytes (powers of 2, only) are permitted. 4510 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 4511 !isPowerOf2_32(DataSize)) 4512 return false; 4513 4514 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 4515 // loads require AVX2). 4516 if (DataSize == 32) 4517 return ST->hasAVX(); 4518 else if (DataSize == 16) 4519 return ST->hasSSE1(); 4520 return true; 4521 } 4522 4523 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 4524 if (!isa<VectorType>(DataTy)) 4525 return false; 4526 4527 if (!ST->hasAVX512()) 4528 return false; 4529 4530 // The backend can't handle a single element vector. 4531 if (cast<FixedVectorType>(DataTy)->getNumElements() == 1) 4532 return false; 4533 4534 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 4535 4536 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4537 return true; 4538 4539 if (!ScalarTy->isIntegerTy()) 4540 return false; 4541 4542 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4543 return IntWidth == 32 || IntWidth == 64 || 4544 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 4545 } 4546 4547 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 4548 return isLegalMaskedExpandLoad(DataTy); 4549 } 4550 4551 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, Align Alignment) { 4552 // Some CPUs have better gather performance than others. 4553 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 4554 // enable gather with a -march. 4555 if (!(ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()))) 4556 return false; 4557 4558 // This function is called now in two cases: from the Loop Vectorizer 4559 // and from the Scalarizer. 4560 // When the Loop Vectorizer asks about legality of the feature, 4561 // the vectorization factor is not calculated yet. The Loop Vectorizer 4562 // sends a scalar type and the decision is based on the width of the 4563 // scalar element. 4564 // Later on, the cost model will estimate usage this intrinsic based on 4565 // the vector type. 4566 // The Scalarizer asks again about legality. It sends a vector type. 4567 // In this case we can reject non-power-of-2 vectors. 4568 // We also reject single element vectors as the type legalizer can't 4569 // scalarize it. 4570 if (auto *DataVTy = dyn_cast<FixedVectorType>(DataTy)) { 4571 unsigned NumElts = DataVTy->getNumElements(); 4572 if (NumElts == 1) 4573 return false; 4574 } 4575 Type *ScalarTy = DataTy->getScalarType(); 4576 if (ScalarTy->isPointerTy()) 4577 return true; 4578 4579 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4580 return true; 4581 4582 if (!ScalarTy->isIntegerTy()) 4583 return false; 4584 4585 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4586 return IntWidth == 32 || IntWidth == 64; 4587 } 4588 4589 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, Align Alignment) { 4590 // AVX2 doesn't support scatter 4591 if (!ST->hasAVX512()) 4592 return false; 4593 return isLegalMaskedGather(DataType, Alignment); 4594 } 4595 4596 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 4597 EVT VT = TLI->getValueType(DL, DataType); 4598 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 4599 } 4600 4601 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 4602 return false; 4603 } 4604 4605 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 4606 const Function *Callee) const { 4607 const TargetMachine &TM = getTLI()->getTargetMachine(); 4608 4609 // Work this as a subsetting of subtarget features. 4610 const FeatureBitset &CallerBits = 4611 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 4612 const FeatureBitset &CalleeBits = 4613 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 4614 4615 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 4616 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 4617 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 4618 } 4619 4620 bool X86TTIImpl::areFunctionArgsABICompatible( 4621 const Function *Caller, const Function *Callee, 4622 SmallPtrSetImpl<Argument *> &Args) const { 4623 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args)) 4624 return false; 4625 4626 // If we get here, we know the target features match. If one function 4627 // considers 512-bit vectors legal and the other does not, consider them 4628 // incompatible. 4629 const TargetMachine &TM = getTLI()->getTargetMachine(); 4630 4631 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 4632 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs()) 4633 return true; 4634 4635 // Consider the arguments compatible if they aren't vectors or aggregates. 4636 // FIXME: Look at the size of vectors. 4637 // FIXME: Look at the element types of aggregates to see if there are vectors. 4638 // FIXME: The API of this function seems intended to allow arguments 4639 // to be removed from the set, but the caller doesn't check if the set 4640 // becomes empty so that may not work in practice. 4641 return llvm::none_of(Args, [](Argument *A) { 4642 auto *EltTy = cast<PointerType>(A->getType())->getElementType(); 4643 return EltTy->isVectorTy() || EltTy->isAggregateType(); 4644 }); 4645 } 4646 4647 X86TTIImpl::TTI::MemCmpExpansionOptions 4648 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 4649 TTI::MemCmpExpansionOptions Options; 4650 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 4651 Options.NumLoadsPerBlock = 2; 4652 // All GPR and vector loads can be unaligned. 4653 Options.AllowOverlappingLoads = true; 4654 if (IsZeroCmp) { 4655 // Only enable vector loads for equality comparison. Right now the vector 4656 // version is not as fast for three way compare (see #33329). 4657 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 4658 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 4659 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 4660 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 4661 } 4662 if (ST->is64Bit()) { 4663 Options.LoadSizes.push_back(8); 4664 } 4665 Options.LoadSizes.push_back(4); 4666 Options.LoadSizes.push_back(2); 4667 Options.LoadSizes.push_back(1); 4668 return Options; 4669 } 4670 4671 bool X86TTIImpl::enableInterleavedAccessVectorization() { 4672 // TODO: We expect this to be beneficial regardless of arch, 4673 // but there are currently some unexplained performance artifacts on Atom. 4674 // As a temporary solution, disable on Atom. 4675 return !(ST->isAtom()); 4676 } 4677 4678 // Get estimation for interleaved load/store operations for AVX2. 4679 // \p Factor is the interleaved-access factor (stride) - number of 4680 // (interleaved) elements in the group. 4681 // \p Indices contains the indices for a strided load: when the 4682 // interleaved load has gaps they indicate which elements are used. 4683 // If Indices is empty (or if the number of indices is equal to the size 4684 // of the interleaved-access as given in \p Factor) the access has no gaps. 4685 // 4686 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 4687 // computing the cost using a generic formula as a function of generic 4688 // shuffles. We therefore use a lookup table instead, filled according to 4689 // the instruction sequences that codegen currently generates. 4690 InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2( 4691 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 4692 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 4693 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 4694 4695 if (UseMaskForCond || UseMaskForGaps) 4696 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4697 Alignment, AddressSpace, CostKind, 4698 UseMaskForCond, UseMaskForGaps); 4699 4700 // We currently Support only fully-interleaved groups, with no gaps. 4701 // TODO: Support also strided loads (interleaved-groups with gaps). 4702 if (Indices.size() && Indices.size() != Factor) 4703 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4704 Alignment, AddressSpace, 4705 CostKind); 4706 4707 // VecTy for interleave memop is <VF*Factor x Elt>. 4708 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4709 // VecTy = <12 x i32>. 4710 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4711 4712 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 4713 // the VF=2, while v2i128 is an unsupported MVT vector type 4714 // (see MachineValueType.h::getVectorVT()). 4715 if (!LegalVT.isVector()) 4716 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4717 Alignment, AddressSpace, 4718 CostKind); 4719 4720 unsigned VF = VecTy->getNumElements() / Factor; 4721 Type *ScalarTy = VecTy->getElementType(); 4722 // Deduplicate entries, model floats/pointers as appropriately-sized integers. 4723 if (!ScalarTy->isIntegerTy()) 4724 ScalarTy = 4725 Type::getIntNTy(ScalarTy->getContext(), DL.getTypeSizeInBits(ScalarTy)); 4726 4727 // Get the cost of all the memory operations. 4728 InstructionCost MemOpCosts = getMemoryOpCost( 4729 Opcode, VecTy, MaybeAlign(Alignment), AddressSpace, CostKind); 4730 4731 auto *VT = FixedVectorType::get(ScalarTy, VF); 4732 EVT ETy = TLI->getValueType(DL, VT); 4733 if (!ETy.isSimple()) 4734 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4735 Alignment, AddressSpace, 4736 CostKind); 4737 4738 // TODO: Complete for other data-types and strides. 4739 // Each combination of Stride, element bit width and VF results in a different 4740 // sequence; The cost tables are therefore accessed with: 4741 // Factor (stride) and VectorType=VFxiN. 4742 // The Cost accounts only for the shuffle sequence; 4743 // The cost of the loads/stores is accounted for separately. 4744 // 4745 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 4746 { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64 4747 4748 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8 4749 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8 4750 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8 4751 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8 4752 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8 4753 4754 { 3, MVT::v8i32, 17 }, //(load 24i32 and)deinterleave into 3 x 8i32 4755 4756 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8 4757 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8 4758 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8 4759 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8 4760 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8 4761 4762 { 8, MVT::v8i32, 40 } //(load 64i32 and)deinterleave into 8 x 8i32 4763 }; 4764 4765 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 4766 { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store) 4767 4768 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store) 4769 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store) 4770 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store) 4771 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store) 4772 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store) 4773 4774 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store) 4775 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store) 4776 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store) 4777 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store) 4778 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store) 4779 }; 4780 4781 if (Opcode == Instruction::Load) { 4782 if (const auto *Entry = 4783 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 4784 return MemOpCosts + Entry->Cost; 4785 } else { 4786 assert(Opcode == Instruction::Store && 4787 "Expected Store Instruction at this point"); 4788 if (const auto *Entry = 4789 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 4790 return MemOpCosts + Entry->Cost; 4791 } 4792 4793 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4794 Alignment, AddressSpace, CostKind); 4795 } 4796 4797 // Get estimation for interleaved load/store operations and strided load. 4798 // \p Indices contains indices for strided load. 4799 // \p Factor - the factor of interleaving. 4800 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 4801 InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX512( 4802 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 4803 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 4804 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 4805 4806 if (UseMaskForCond || UseMaskForGaps) 4807 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4808 Alignment, AddressSpace, CostKind, 4809 UseMaskForCond, UseMaskForGaps); 4810 4811 // VecTy for interleave memop is <VF*Factor x Elt>. 4812 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4813 // VecTy = <12 x i32>. 4814 4815 // Calculate the number of memory operations (NumOfMemOps), required 4816 // for load/store the VecTy. 4817 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4818 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4819 unsigned LegalVTSize = LegalVT.getStoreSize(); 4820 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4821 4822 // Get the cost of one memory operation. 4823 auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(), 4824 LegalVT.getVectorNumElements()); 4825 InstructionCost MemOpCost = getMemoryOpCost( 4826 Opcode, SingleMemOpTy, MaybeAlign(Alignment), AddressSpace, CostKind); 4827 4828 unsigned VF = VecTy->getNumElements() / Factor; 4829 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 4830 4831 if (Opcode == Instruction::Load) { 4832 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 4833 // contain the cost of the optimized shuffle sequence that the 4834 // X86InterleavedAccess pass will generate. 4835 // The cost of loads and stores are computed separately from the table. 4836 4837 // X86InterleavedAccess support only the following interleaved-access group. 4838 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 4839 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 4840 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 4841 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 4842 }; 4843 4844 if (const auto *Entry = 4845 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 4846 return NumOfMemOps * MemOpCost + Entry->Cost; 4847 //If an entry does not exist, fallback to the default implementation. 4848 4849 // Kind of shuffle depends on number of loaded values. 4850 // If we load the entire data in one register, we can use a 1-src shuffle. 4851 // Otherwise, we'll merge 2 sources in each operation. 4852 TTI::ShuffleKind ShuffleKind = 4853 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 4854 4855 InstructionCost ShuffleCost = 4856 getShuffleCost(ShuffleKind, SingleMemOpTy, None, 0, nullptr); 4857 4858 unsigned NumOfLoadsInInterleaveGrp = 4859 Indices.size() ? Indices.size() : Factor; 4860 auto *ResultTy = FixedVectorType::get(VecTy->getElementType(), 4861 VecTy->getNumElements() / Factor); 4862 InstructionCost NumOfResults = 4863 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 4864 NumOfLoadsInInterleaveGrp; 4865 4866 // About a half of the loads may be folded in shuffles when we have only 4867 // one result. If we have more than one result, we do not fold loads at all. 4868 unsigned NumOfUnfoldedLoads = 4869 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 4870 4871 // Get a number of shuffle operations per result. 4872 unsigned NumOfShufflesPerResult = 4873 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 4874 4875 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4876 // When we have more than one destination, we need additional instructions 4877 // to keep sources. 4878 InstructionCost NumOfMoves = 0; 4879 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 4880 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 4881 4882 InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 4883 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 4884 4885 return Cost; 4886 } 4887 4888 // Store. 4889 assert(Opcode == Instruction::Store && 4890 "Expected Store Instruction at this point"); 4891 // X86InterleavedAccess support only the following interleaved-access group. 4892 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 4893 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 4894 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 4895 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 4896 4897 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 4898 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 4899 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 4900 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 4901 }; 4902 4903 if (const auto *Entry = 4904 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 4905 return NumOfMemOps * MemOpCost + Entry->Cost; 4906 //If an entry does not exist, fallback to the default implementation. 4907 4908 // There is no strided stores meanwhile. And store can't be folded in 4909 // shuffle. 4910 unsigned NumOfSources = Factor; // The number of values to be merged. 4911 InstructionCost ShuffleCost = 4912 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, None, 0, nullptr); 4913 unsigned NumOfShufflesPerStore = NumOfSources - 1; 4914 4915 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4916 // We need additional instructions to keep sources. 4917 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 4918 InstructionCost Cost = 4919 NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 4920 NumOfMoves; 4921 return Cost; 4922 } 4923 4924 InstructionCost X86TTIImpl::getInterleavedMemoryOpCost( 4925 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, 4926 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, 4927 bool UseMaskForCond, bool UseMaskForGaps) { 4928 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 4929 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 4930 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 4931 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 4932 return true; 4933 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 4934 return HasBW; 4935 return false; 4936 }; 4937 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 4938 return getInterleavedMemoryOpCostAVX512( 4939 Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment, 4940 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 4941 if (ST->hasAVX2()) 4942 return getInterleavedMemoryOpCostAVX2( 4943 Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment, 4944 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 4945 4946 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4947 Alignment, AddressSpace, CostKind, 4948 UseMaskForCond, UseMaskForGaps); 4949 } 4950