1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/InstIterator.h" 47 #include "llvm/IR/IntrinsicInst.h" 48 #include "llvm/Support/Debug.h" 49 50 using namespace llvm; 51 52 #define DEBUG_TYPE "x86tti" 53 54 //===----------------------------------------------------------------------===// 55 // 56 // X86 cost model. 57 // 58 //===----------------------------------------------------------------------===// 59 60 TargetTransformInfo::PopcntSupportKind 61 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 62 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 63 // TODO: Currently the __builtin_popcount() implementation using SSE3 64 // instructions is inefficient. Once the problem is fixed, we should 65 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 66 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 67 } 68 69 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 70 TargetTransformInfo::CacheLevel Level) const { 71 switch (Level) { 72 case TargetTransformInfo::CacheLevel::L1D: 73 // - Penryn 74 // - Nehalem 75 // - Westmere 76 // - Sandy Bridge 77 // - Ivy Bridge 78 // - Haswell 79 // - Broadwell 80 // - Skylake 81 // - Kabylake 82 return 32 * 1024; // 32 KByte 83 case TargetTransformInfo::CacheLevel::L2D: 84 // - Penryn 85 // - Nehalem 86 // - Westmere 87 // - Sandy Bridge 88 // - Ivy Bridge 89 // - Haswell 90 // - Broadwell 91 // - Skylake 92 // - Kabylake 93 return 256 * 1024; // 256 KByte 94 } 95 96 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 97 } 98 99 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 100 TargetTransformInfo::CacheLevel Level) const { 101 // - Penryn 102 // - Nehalem 103 // - Westmere 104 // - Sandy Bridge 105 // - Ivy Bridge 106 // - Haswell 107 // - Broadwell 108 // - Skylake 109 // - Kabylake 110 switch (Level) { 111 case TargetTransformInfo::CacheLevel::L1D: 112 LLVM_FALLTHROUGH; 113 case TargetTransformInfo::CacheLevel::L2D: 114 return 8; 115 } 116 117 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 118 } 119 120 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 121 bool Vector = (ClassID == 1); 122 if (Vector && !ST->hasSSE1()) 123 return 0; 124 125 if (ST->is64Bit()) { 126 if (Vector && ST->hasAVX512()) 127 return 32; 128 return 16; 129 } 130 return 8; 131 } 132 133 TypeSize 134 X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { 135 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 136 switch (K) { 137 case TargetTransformInfo::RGK_Scalar: 138 return TypeSize::getFixed(ST->is64Bit() ? 64 : 32); 139 case TargetTransformInfo::RGK_FixedWidthVector: 140 if (ST->hasAVX512() && PreferVectorWidth >= 512) 141 return TypeSize::getFixed(512); 142 if (ST->hasAVX() && PreferVectorWidth >= 256) 143 return TypeSize::getFixed(256); 144 if (ST->hasSSE1() && PreferVectorWidth >= 128) 145 return TypeSize::getFixed(128); 146 return TypeSize::getFixed(0); 147 case TargetTransformInfo::RGK_ScalableVector: 148 return TypeSize::getScalable(0); 149 } 150 151 llvm_unreachable("Unsupported register kind"); 152 } 153 154 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 155 return getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector) 156 .getFixedSize(); 157 } 158 159 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 160 // If the loop will not be vectorized, don't interleave the loop. 161 // Let regular unroll to unroll the loop, which saves the overflow 162 // check and memory check cost. 163 if (VF == 1) 164 return 1; 165 166 if (ST->isAtom()) 167 return 1; 168 169 // Sandybridge and Haswell have multiple execution ports and pipelined 170 // vector units. 171 if (ST->hasAVX()) 172 return 4; 173 174 return 2; 175 } 176 177 InstructionCost X86TTIImpl::getArithmeticInstrCost( 178 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, 179 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 180 TTI::OperandValueProperties Opd1PropInfo, 181 TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, 182 const Instruction *CxtI) { 183 // TODO: Handle more cost kinds. 184 if (CostKind != TTI::TCK_RecipThroughput) 185 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, 186 Op2Info, Opd1PropInfo, 187 Opd2PropInfo, Args, CxtI); 188 189 // vXi8 multiplications are always promoted to vXi16. 190 if (Opcode == Instruction::Mul && Ty->isVectorTy() && 191 Ty->getScalarSizeInBits() == 8) { 192 Type *WideVecTy = 193 VectorType::getExtendedElementVectorType(cast<VectorType>(Ty)); 194 return getCastInstrCost(Instruction::ZExt, WideVecTy, Ty, 195 TargetTransformInfo::CastContextHint::None, 196 CostKind) + 197 getCastInstrCost(Instruction::Trunc, Ty, WideVecTy, 198 TargetTransformInfo::CastContextHint::None, 199 CostKind) + 200 getArithmeticInstrCost(Opcode, WideVecTy, CostKind, Op1Info, Op2Info, 201 Opd1PropInfo, Opd2PropInfo); 202 } 203 204 // Legalize the type. 205 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 206 207 int ISD = TLI->InstructionOpcodeToISD(Opcode); 208 assert(ISD && "Invalid opcode"); 209 210 if (ISD == ISD::MUL && Args.size() == 2 && LT.second.isVector() && 211 LT.second.getScalarType() == MVT::i32) { 212 // Check if the operands can be represented as a smaller datatype. 213 bool Op1Signed = false, Op2Signed = false; 214 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 215 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 216 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 217 218 // If both are representable as i15 and at least one is constant, 219 // zero-extended, or sign-extended from vXi16 (or less pre-SSE41) then we 220 // can treat this as PMADDWD which has the same costs as a vXi16 multiply. 221 if (OpMinSize <= 15 && !ST->isPMADDWDSlow()) { 222 bool Op1Constant = 223 isa<ConstantDataVector>(Args[0]) || isa<ConstantVector>(Args[0]); 224 bool Op2Constant = 225 isa<ConstantDataVector>(Args[1]) || isa<ConstantVector>(Args[1]); 226 bool Op1Sext = isa<SExtInst>(Args[0]) && 227 (Op1MinSize == 15 || (Op1MinSize < 15 && !ST->hasSSE41())); 228 bool Op2Sext = isa<SExtInst>(Args[1]) && 229 (Op2MinSize == 15 || (Op2MinSize < 15 && !ST->hasSSE41())); 230 231 bool IsZeroExtended = !Op1Signed || !Op2Signed; 232 bool IsConstant = Op1Constant || Op2Constant; 233 bool IsSext = Op1Sext || Op2Sext; 234 if (IsConstant || IsZeroExtended || IsSext) 235 LT.second = 236 MVT::getVectorVT(MVT::i16, 2 * LT.second.getVectorNumElements()); 237 } 238 } 239 240 // Vector multiply by pow2 will be simplified to shifts. 241 if (ISD == ISD::MUL && 242 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 243 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 244 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) 245 return getArithmeticInstrCost(Instruction::Shl, Ty, CostKind, Op1Info, 246 Op2Info, TargetTransformInfo::OP_None, 247 TargetTransformInfo::OP_None); 248 249 // On X86, vector signed division by constants power-of-two are 250 // normally expanded to the sequence SRA + SRL + ADD + SRA. 251 // The OperandValue properties may not be the same as that of the previous 252 // operation; conservatively assume OP_None. 253 if ((ISD == ISD::SDIV || ISD == ISD::SREM) && 254 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 255 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 256 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 257 InstructionCost Cost = 258 2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Op1Info, 259 Op2Info, TargetTransformInfo::OP_None, 260 TargetTransformInfo::OP_None); 261 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 262 Op2Info, TargetTransformInfo::OP_None, 263 TargetTransformInfo::OP_None); 264 Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind, Op1Info, 265 Op2Info, TargetTransformInfo::OP_None, 266 TargetTransformInfo::OP_None); 267 268 if (ISD == ISD::SREM) { 269 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 270 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info, 271 Op2Info); 272 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info, 273 Op2Info); 274 } 275 276 return Cost; 277 } 278 279 // Vector unsigned division/remainder will be simplified to shifts/masks. 280 if ((ISD == ISD::UDIV || ISD == ISD::UREM) && 281 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 282 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 283 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 284 if (ISD == ISD::UDIV) 285 return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 286 Op2Info, TargetTransformInfo::OP_None, 287 TargetTransformInfo::OP_None); 288 // UREM 289 return getArithmeticInstrCost(Instruction::And, Ty, CostKind, Op1Info, 290 Op2Info, TargetTransformInfo::OP_None, 291 TargetTransformInfo::OP_None); 292 } 293 294 static const CostTblEntry GLMCostTable[] = { 295 { ISD::FDIV, MVT::f32, 18 }, // divss 296 { ISD::FDIV, MVT::v4f32, 35 }, // divps 297 { ISD::FDIV, MVT::f64, 33 }, // divsd 298 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 299 }; 300 301 if (ST->useGLMDivSqrtCosts()) 302 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 303 LT.second)) 304 return LT.first * Entry->Cost; 305 306 static const CostTblEntry SLMCostTable[] = { 307 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 308 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 309 { ISD::FMUL, MVT::f64, 2 }, // mulsd 310 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 311 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 312 { ISD::FDIV, MVT::f32, 17 }, // divss 313 { ISD::FDIV, MVT::v4f32, 39 }, // divps 314 { ISD::FDIV, MVT::f64, 32 }, // divsd 315 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 316 { ISD::FADD, MVT::v2f64, 2 }, // addpd 317 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 318 // v2i64/v4i64 mul is custom lowered as a series of long: 319 // multiplies(3), shifts(3) and adds(2) 320 // slm muldq version throughput is 2 and addq throughput 4 321 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 322 // 3X4 (addq throughput) = 17 323 { ISD::MUL, MVT::v2i64, 17 }, 324 // slm addq\subq throughput is 4 325 { ISD::ADD, MVT::v2i64, 4 }, 326 { ISD::SUB, MVT::v2i64, 4 }, 327 }; 328 329 if (ST->useSLMArithCosts()) { 330 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 331 // Check if the operands can be shrinked into a smaller datatype. 332 // TODO: Merge this into generiic vXi32 MUL patterns above. 333 bool Op1Signed = false; 334 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 335 bool Op2Signed = false; 336 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 337 338 bool SignedMode = Op1Signed || Op2Signed; 339 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 340 341 if (OpMinSize <= 7) 342 return LT.first * 3; // pmullw/sext 343 if (!SignedMode && OpMinSize <= 8) 344 return LT.first * 3; // pmullw/zext 345 if (OpMinSize <= 15) 346 return LT.first * 5; // pmullw/pmulhw/pshuf 347 if (!SignedMode && OpMinSize <= 16) 348 return LT.first * 5; // pmullw/pmulhw/pshuf 349 } 350 351 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 352 LT.second)) { 353 return LT.first * Entry->Cost; 354 } 355 } 356 357 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 358 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 359 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 360 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 361 }; 362 363 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 364 ST->hasBWI()) { 365 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 366 LT.second)) 367 return LT.first * Entry->Cost; 368 } 369 370 static const CostTblEntry AVX512UniformConstCostTable[] = { 371 { ISD::SRA, MVT::v2i64, 1 }, 372 { ISD::SRA, MVT::v4i64, 1 }, 373 { ISD::SRA, MVT::v8i64, 1 }, 374 375 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 376 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 377 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 378 379 { ISD::SDIV, MVT::v16i32, 6 }, // pmuludq sequence 380 { ISD::SREM, MVT::v16i32, 8 }, // pmuludq+mul+sub sequence 381 { ISD::UDIV, MVT::v16i32, 5 }, // pmuludq sequence 382 { ISD::UREM, MVT::v16i32, 7 }, // pmuludq+mul+sub sequence 383 }; 384 385 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 386 ST->hasAVX512()) { 387 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 388 LT.second)) 389 return LT.first * Entry->Cost; 390 } 391 392 static const CostTblEntry AVX2UniformConstCostTable[] = { 393 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 394 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 395 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 396 397 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 398 399 { ISD::SDIV, MVT::v8i32, 6 }, // pmuludq sequence 400 { ISD::SREM, MVT::v8i32, 8 }, // pmuludq+mul+sub sequence 401 { ISD::UDIV, MVT::v8i32, 5 }, // pmuludq sequence 402 { ISD::UREM, MVT::v8i32, 7 }, // pmuludq+mul+sub sequence 403 }; 404 405 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 406 ST->hasAVX2()) { 407 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 408 LT.second)) 409 return LT.first * Entry->Cost; 410 } 411 412 static const CostTblEntry SSE2UniformConstCostTable[] = { 413 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 414 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 415 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 416 417 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 418 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 419 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 420 421 { ISD::SDIV, MVT::v8i32, 12+2 }, // 2*pmuludq sequence + split. 422 { ISD::SREM, MVT::v8i32, 16+2 }, // 2*pmuludq+mul+sub sequence + split. 423 { ISD::SDIV, MVT::v4i32, 6 }, // pmuludq sequence 424 { ISD::SREM, MVT::v4i32, 8 }, // pmuludq+mul+sub sequence 425 { ISD::UDIV, MVT::v8i32, 10+2 }, // 2*pmuludq sequence + split. 426 { ISD::UREM, MVT::v8i32, 14+2 }, // 2*pmuludq+mul+sub sequence + split. 427 { ISD::UDIV, MVT::v4i32, 5 }, // pmuludq sequence 428 { ISD::UREM, MVT::v4i32, 7 }, // pmuludq+mul+sub sequence 429 }; 430 431 // XOP has faster vXi8 shifts. 432 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 433 ST->hasSSE2() && !ST->hasXOP()) { 434 if (const auto *Entry = 435 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 436 return LT.first * Entry->Cost; 437 } 438 439 static const CostTblEntry AVX512BWConstCostTable[] = { 440 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 441 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 442 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 443 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 444 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 445 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 446 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 447 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 448 }; 449 450 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 451 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 452 ST->hasBWI()) { 453 if (const auto *Entry = 454 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 455 return LT.first * Entry->Cost; 456 } 457 458 static const CostTblEntry AVX512ConstCostTable[] = { 459 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 460 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 461 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 462 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 463 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 464 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 465 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 466 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 467 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 468 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 469 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 470 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 471 }; 472 473 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 474 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 475 ST->hasAVX512()) { 476 if (const auto *Entry = 477 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 478 return LT.first * Entry->Cost; 479 } 480 481 static const CostTblEntry AVX2ConstCostTable[] = { 482 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 483 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 484 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 485 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 486 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 487 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 488 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 489 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 490 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 491 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 492 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 493 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 494 }; 495 496 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 497 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 498 ST->hasAVX2()) { 499 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 500 return LT.first * Entry->Cost; 501 } 502 503 static const CostTblEntry SSE2ConstCostTable[] = { 504 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 505 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 506 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 507 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 508 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 509 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 510 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 511 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 512 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 513 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 514 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 515 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 516 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 517 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 518 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 519 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 520 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 521 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 522 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 523 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 524 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 525 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 526 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 527 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 528 }; 529 530 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 531 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 532 ST->hasSSE2()) { 533 // pmuldq sequence. 534 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 535 return LT.first * 32; 536 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 537 return LT.first * 38; 538 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 539 return LT.first * 15; 540 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 541 return LT.first * 20; 542 543 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 544 return LT.first * Entry->Cost; 545 } 546 547 static const CostTblEntry AVX512BWShiftCostTable[] = { 548 { ISD::SHL, MVT::v16i8, 4 }, // extend/vpsllvw/pack sequence. 549 { ISD::SRL, MVT::v16i8, 4 }, // extend/vpsrlvw/pack sequence. 550 { ISD::SRA, MVT::v16i8, 4 }, // extend/vpsravw/pack sequence. 551 { ISD::SHL, MVT::v32i8, 4 }, // extend/vpsllvw/pack sequence. 552 { ISD::SRL, MVT::v32i8, 4 }, // extend/vpsrlvw/pack sequence. 553 { ISD::SRA, MVT::v32i8, 6 }, // extend/vpsravw/pack sequence. 554 { ISD::SHL, MVT::v64i8, 6 }, // extend/vpsllvw/pack sequence. 555 { ISD::SRL, MVT::v64i8, 7 }, // extend/vpsrlvw/pack sequence. 556 { ISD::SRA, MVT::v64i8, 15 }, // extend/vpsravw/pack sequence. 557 558 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 559 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 560 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 561 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 562 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 563 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 564 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 565 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 566 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 567 }; 568 569 if (ST->hasBWI()) 570 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 571 return LT.first * Entry->Cost; 572 573 static const CostTblEntry AVX2UniformCostTable[] = { 574 // Uniform splats are cheaper for the following instructions. 575 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 576 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 577 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 578 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 579 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 580 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 581 582 { ISD::SHL, MVT::v8i32, 1 }, // pslld 583 { ISD::SRL, MVT::v8i32, 1 }, // psrld 584 { ISD::SRA, MVT::v8i32, 1 }, // psrad 585 { ISD::SHL, MVT::v4i64, 1 }, // psllq 586 { ISD::SRL, MVT::v4i64, 1 }, // psrlq 587 }; 588 589 if (ST->hasAVX2() && 590 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 591 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 592 if (const auto *Entry = 593 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 594 return LT.first * Entry->Cost; 595 } 596 597 static const CostTblEntry SSE2UniformCostTable[] = { 598 // Uniform splats are cheaper for the following instructions. 599 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 600 { ISD::SHL, MVT::v4i32, 1 }, // pslld 601 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 602 603 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 604 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 605 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 606 607 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 608 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 609 }; 610 611 if (ST->hasSSE2() && 612 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 613 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 614 if (const auto *Entry = 615 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 616 return LT.first * Entry->Cost; 617 } 618 619 static const CostTblEntry AVX512DQCostTable[] = { 620 { ISD::MUL, MVT::v2i64, 2 }, // pmullq 621 { ISD::MUL, MVT::v4i64, 2 }, // pmullq 622 { ISD::MUL, MVT::v8i64, 2 } // pmullq 623 }; 624 625 // Look for AVX512DQ lowering tricks for custom cases. 626 if (ST->hasDQI()) 627 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 628 return LT.first * Entry->Cost; 629 630 static const CostTblEntry AVX512BWCostTable[] = { 631 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 632 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 633 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 634 }; 635 636 // Look for AVX512BW lowering tricks for custom cases. 637 if (ST->hasBWI()) 638 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 639 return LT.first * Entry->Cost; 640 641 static const CostTblEntry AVX512CostTable[] = { 642 { ISD::SHL, MVT::v4i32, 1 }, 643 { ISD::SRL, MVT::v4i32, 1 }, 644 { ISD::SRA, MVT::v4i32, 1 }, 645 { ISD::SHL, MVT::v8i32, 1 }, 646 { ISD::SRL, MVT::v8i32, 1 }, 647 { ISD::SRA, MVT::v8i32, 1 }, 648 { ISD::SHL, MVT::v16i32, 1 }, 649 { ISD::SRL, MVT::v16i32, 1 }, 650 { ISD::SRA, MVT::v16i32, 1 }, 651 652 { ISD::SHL, MVT::v2i64, 1 }, 653 { ISD::SRL, MVT::v2i64, 1 }, 654 { ISD::SHL, MVT::v4i64, 1 }, 655 { ISD::SRL, MVT::v4i64, 1 }, 656 { ISD::SHL, MVT::v8i64, 1 }, 657 { ISD::SRL, MVT::v8i64, 1 }, 658 659 { ISD::SRA, MVT::v2i64, 1 }, 660 { ISD::SRA, MVT::v4i64, 1 }, 661 { ISD::SRA, MVT::v8i64, 1 }, 662 663 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 664 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 665 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 666 { ISD::MUL, MVT::v8i64, 6 }, // 3*pmuludq/3*shift/2*add 667 { ISD::MUL, MVT::i64, 1 }, // Skylake from http://www.agner.org/ 668 669 { ISD::FNEG, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 670 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 671 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 672 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 673 { ISD::FDIV, MVT::f64, 4 }, // Skylake from http://www.agner.org/ 674 { ISD::FDIV, MVT::v2f64, 4 }, // Skylake from http://www.agner.org/ 675 { ISD::FDIV, MVT::v4f64, 8 }, // Skylake from http://www.agner.org/ 676 { ISD::FDIV, MVT::v8f64, 16 }, // Skylake from http://www.agner.org/ 677 678 { ISD::FNEG, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 679 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 680 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 681 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 682 { ISD::FDIV, MVT::f32, 3 }, // Skylake from http://www.agner.org/ 683 { ISD::FDIV, MVT::v4f32, 3 }, // Skylake from http://www.agner.org/ 684 { ISD::FDIV, MVT::v8f32, 5 }, // Skylake from http://www.agner.org/ 685 { ISD::FDIV, MVT::v16f32, 10 }, // Skylake from http://www.agner.org/ 686 }; 687 688 if (ST->hasAVX512()) 689 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 690 return LT.first * Entry->Cost; 691 692 static const CostTblEntry AVX2ShiftCostTable[] = { 693 // Shifts on vXi64/vXi32 on AVX2 is legal even though we declare to 694 // customize them to detect the cases where shift amount is a scalar one. 695 { ISD::SHL, MVT::v4i32, 2 }, // vpsllvd (Haswell from agner.org) 696 { ISD::SRL, MVT::v4i32, 2 }, // vpsrlvd (Haswell from agner.org) 697 { ISD::SRA, MVT::v4i32, 2 }, // vpsravd (Haswell from agner.org) 698 { ISD::SHL, MVT::v8i32, 2 }, // vpsllvd (Haswell from agner.org) 699 { ISD::SRL, MVT::v8i32, 2 }, // vpsrlvd (Haswell from agner.org) 700 { ISD::SRA, MVT::v8i32, 2 }, // vpsravd (Haswell from agner.org) 701 { ISD::SHL, MVT::v2i64, 1 }, // vpsllvq (Haswell from agner.org) 702 { ISD::SRL, MVT::v2i64, 1 }, // vpsrlvq (Haswell from agner.org) 703 { ISD::SHL, MVT::v4i64, 1 }, // vpsllvq (Haswell from agner.org) 704 { ISD::SRL, MVT::v4i64, 1 }, // vpsrlvq (Haswell from agner.org) 705 }; 706 707 if (ST->hasAVX512()) { 708 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 709 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 710 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 711 // On AVX512, a packed v32i16 shift left by a constant build_vector 712 // is lowered into a vector multiply (vpmullw). 713 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 714 Op1Info, Op2Info, 715 TargetTransformInfo::OP_None, 716 TargetTransformInfo::OP_None); 717 } 718 719 // Look for AVX2 lowering tricks (XOP is always better at v4i32 shifts). 720 if (ST->hasAVX2() && !(ST->hasXOP() && LT.second == MVT::v4i32)) { 721 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 722 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 723 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 724 // On AVX2, a packed v16i16 shift left by a constant build_vector 725 // is lowered into a vector multiply (vpmullw). 726 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 727 Op1Info, Op2Info, 728 TargetTransformInfo::OP_None, 729 TargetTransformInfo::OP_None); 730 731 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 732 return LT.first * Entry->Cost; 733 } 734 735 static const CostTblEntry XOPShiftCostTable[] = { 736 // 128bit shifts take 1cy, but right shifts require negation beforehand. 737 { ISD::SHL, MVT::v16i8, 1 }, 738 { ISD::SRL, MVT::v16i8, 2 }, 739 { ISD::SRA, MVT::v16i8, 2 }, 740 { ISD::SHL, MVT::v8i16, 1 }, 741 { ISD::SRL, MVT::v8i16, 2 }, 742 { ISD::SRA, MVT::v8i16, 2 }, 743 { ISD::SHL, MVT::v4i32, 1 }, 744 { ISD::SRL, MVT::v4i32, 2 }, 745 { ISD::SRA, MVT::v4i32, 2 }, 746 { ISD::SHL, MVT::v2i64, 1 }, 747 { ISD::SRL, MVT::v2i64, 2 }, 748 { ISD::SRA, MVT::v2i64, 2 }, 749 // 256bit shifts require splitting if AVX2 didn't catch them above. 750 { ISD::SHL, MVT::v32i8, 2+2 }, 751 { ISD::SRL, MVT::v32i8, 4+2 }, 752 { ISD::SRA, MVT::v32i8, 4+2 }, 753 { ISD::SHL, MVT::v16i16, 2+2 }, 754 { ISD::SRL, MVT::v16i16, 4+2 }, 755 { ISD::SRA, MVT::v16i16, 4+2 }, 756 { ISD::SHL, MVT::v8i32, 2+2 }, 757 { ISD::SRL, MVT::v8i32, 4+2 }, 758 { ISD::SRA, MVT::v8i32, 4+2 }, 759 { ISD::SHL, MVT::v4i64, 2+2 }, 760 { ISD::SRL, MVT::v4i64, 4+2 }, 761 { ISD::SRA, MVT::v4i64, 4+2 }, 762 }; 763 764 // Look for XOP lowering tricks. 765 if (ST->hasXOP()) { 766 // If the right shift is constant then we'll fold the negation so 767 // it's as cheap as a left shift. 768 int ShiftISD = ISD; 769 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 770 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 771 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 772 ShiftISD = ISD::SHL; 773 if (const auto *Entry = 774 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 775 return LT.first * Entry->Cost; 776 } 777 778 static const CostTblEntry SSE2UniformShiftCostTable[] = { 779 // Uniform splats are cheaper for the following instructions. 780 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 781 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 782 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 783 784 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 785 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 786 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 787 788 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 789 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 790 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 791 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 792 }; 793 794 if (ST->hasSSE2() && 795 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 796 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 797 798 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 799 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 800 return LT.first * 4; // 2*psrad + shuffle. 801 802 if (const auto *Entry = 803 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 804 return LT.first * Entry->Cost; 805 } 806 807 if (ISD == ISD::SHL && 808 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 809 MVT VT = LT.second; 810 // Vector shift left by non uniform constant can be lowered 811 // into vector multiply. 812 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 813 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 814 ISD = ISD::MUL; 815 } 816 817 static const CostTblEntry AVX2CostTable[] = { 818 { ISD::SHL, MVT::v16i8, 6 }, // vpblendvb sequence. 819 { ISD::SHL, MVT::v32i8, 6 }, // vpblendvb sequence. 820 { ISD::SHL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 821 { ISD::SHL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 822 { ISD::SHL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 823 { ISD::SHL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 824 825 { ISD::SRL, MVT::v16i8, 6 }, // vpblendvb sequence. 826 { ISD::SRL, MVT::v32i8, 6 }, // vpblendvb sequence. 827 { ISD::SRL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 828 { ISD::SRL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 829 { ISD::SRL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 830 { ISD::SRL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 831 832 { ISD::SRA, MVT::v16i8, 17 }, // vpblendvb sequence. 833 { ISD::SRA, MVT::v32i8, 17 }, // vpblendvb sequence. 834 { ISD::SRA, MVT::v64i8, 34 }, // 2*vpblendvb sequence. 835 { ISD::SRA, MVT::v8i16, 5 }, // extend/vpsravd/pack sequence. 836 { ISD::SRA, MVT::v16i16, 7 }, // extend/vpsravd/pack sequence. 837 { ISD::SRA, MVT::v32i16, 14 }, // 2*extend/vpsravd/pack sequence. 838 { ISD::SRA, MVT::v2i64, 2 }, // srl/xor/sub sequence. 839 { ISD::SRA, MVT::v4i64, 2 }, // srl/xor/sub sequence. 840 841 { ISD::SUB, MVT::v32i8, 1 }, // psubb 842 { ISD::ADD, MVT::v32i8, 1 }, // paddb 843 { ISD::SUB, MVT::v16i16, 1 }, // psubw 844 { ISD::ADD, MVT::v16i16, 1 }, // paddw 845 { ISD::SUB, MVT::v8i32, 1 }, // psubd 846 { ISD::ADD, MVT::v8i32, 1 }, // paddd 847 { ISD::SUB, MVT::v4i64, 1 }, // psubq 848 { ISD::ADD, MVT::v4i64, 1 }, // paddq 849 850 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 851 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 852 { ISD::MUL, MVT::v4i64, 6 }, // 3*pmuludq/3*shift/2*add 853 854 { ISD::FNEG, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 855 { ISD::FNEG, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 856 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 857 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 858 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 859 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 860 { ISD::FMUL, MVT::f64, 1 }, // Haswell from http://www.agner.org/ 861 { ISD::FMUL, MVT::v2f64, 1 }, // Haswell from http://www.agner.org/ 862 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 863 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 864 865 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 866 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 867 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 868 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 869 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 870 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 871 }; 872 873 // Look for AVX2 lowering tricks for custom cases. 874 if (ST->hasAVX2()) 875 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 876 return LT.first * Entry->Cost; 877 878 static const CostTblEntry AVX1CostTable[] = { 879 // We don't have to scalarize unsupported ops. We can issue two half-sized 880 // operations and we only need to extract the upper YMM half. 881 // Two ops + 1 extract + 1 insert = 4. 882 { ISD::MUL, MVT::v16i16, 4 }, 883 { ISD::MUL, MVT::v8i32, 5 }, // BTVER2 from http://www.agner.org/ 884 { ISD::MUL, MVT::v4i64, 12 }, 885 886 { ISD::SUB, MVT::v32i8, 4 }, 887 { ISD::ADD, MVT::v32i8, 4 }, 888 { ISD::SUB, MVT::v16i16, 4 }, 889 { ISD::ADD, MVT::v16i16, 4 }, 890 { ISD::SUB, MVT::v8i32, 4 }, 891 { ISD::ADD, MVT::v8i32, 4 }, 892 { ISD::SUB, MVT::v4i64, 4 }, 893 { ISD::ADD, MVT::v4i64, 4 }, 894 895 { ISD::SHL, MVT::v32i8, 22 }, // pblendvb sequence + split. 896 { ISD::SHL, MVT::v8i16, 6 }, // pblendvb sequence. 897 { ISD::SHL, MVT::v16i16, 13 }, // pblendvb sequence + split. 898 { ISD::SHL, MVT::v4i32, 3 }, // pslld/paddd/cvttps2dq/pmulld 899 { ISD::SHL, MVT::v8i32, 9 }, // pslld/paddd/cvttps2dq/pmulld + split 900 { ISD::SHL, MVT::v2i64, 2 }, // Shift each lane + blend. 901 { ISD::SHL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 902 903 { ISD::SRL, MVT::v32i8, 23 }, // pblendvb sequence + split. 904 { ISD::SRL, MVT::v16i16, 28 }, // pblendvb sequence + split. 905 { ISD::SRL, MVT::v4i32, 6 }, // Shift each lane + blend. 906 { ISD::SRL, MVT::v8i32, 14 }, // Shift each lane + blend + split. 907 { ISD::SRL, MVT::v2i64, 2 }, // Shift each lane + blend. 908 { ISD::SRL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 909 910 { ISD::SRA, MVT::v32i8, 44 }, // pblendvb sequence + split. 911 { ISD::SRA, MVT::v16i16, 28 }, // pblendvb sequence + split. 912 { ISD::SRA, MVT::v4i32, 6 }, // Shift each lane + blend. 913 { ISD::SRA, MVT::v8i32, 14 }, // Shift each lane + blend + split. 914 { ISD::SRA, MVT::v2i64, 5 }, // Shift each lane + blend. 915 { ISD::SRA, MVT::v4i64, 12 }, // Shift each lane + blend + split. 916 917 { ISD::FNEG, MVT::v4f64, 2 }, // BTVER2 from http://www.agner.org/ 918 { ISD::FNEG, MVT::v8f32, 2 }, // BTVER2 from http://www.agner.org/ 919 920 { ISD::FMUL, MVT::f64, 2 }, // BTVER2 from http://www.agner.org/ 921 { ISD::FMUL, MVT::v2f64, 2 }, // BTVER2 from http://www.agner.org/ 922 { ISD::FMUL, MVT::v4f64, 4 }, // BTVER2 from http://www.agner.org/ 923 924 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 925 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 926 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 927 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 928 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 929 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 930 }; 931 932 if (ST->hasAVX()) 933 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 934 return LT.first * Entry->Cost; 935 936 static const CostTblEntry SSE42CostTable[] = { 937 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 938 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 939 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 940 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 941 942 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 943 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 944 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 945 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 946 947 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 948 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 949 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 950 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 951 952 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 953 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 954 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 955 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 956 957 { ISD::MUL, MVT::v2i64, 6 } // 3*pmuludq/3*shift/2*add 958 }; 959 960 if (ST->hasSSE42()) 961 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 962 return LT.first * Entry->Cost; 963 964 static const CostTblEntry SSE41CostTable[] = { 965 { ISD::SHL, MVT::v16i8, 10 }, // pblendvb sequence. 966 { ISD::SHL, MVT::v8i16, 11 }, // pblendvb sequence. 967 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 968 969 { ISD::SRL, MVT::v16i8, 11 }, // pblendvb sequence. 970 { ISD::SRL, MVT::v8i16, 13 }, // pblendvb sequence. 971 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 972 973 { ISD::SRA, MVT::v16i8, 21 }, // pblendvb sequence. 974 { ISD::SRA, MVT::v8i16, 13 }, // pblendvb sequence. 975 976 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 977 }; 978 979 if (ST->hasSSE41()) 980 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 981 return LT.first * Entry->Cost; 982 983 static const CostTblEntry SSE2CostTable[] = { 984 // We don't correctly identify costs of casts because they are marked as 985 // custom. 986 { ISD::SHL, MVT::v16i8, 13 }, // cmpgtb sequence. 987 { ISD::SHL, MVT::v8i16, 25 }, // cmpgtw sequence. 988 { ISD::SHL, MVT::v4i32, 16 }, // pslld/paddd/cvttps2dq/pmuludq. 989 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 990 991 { ISD::SRL, MVT::v16i8, 14 }, // cmpgtb sequence. 992 { ISD::SRL, MVT::v8i16, 16 }, // cmpgtw sequence. 993 { ISD::SRL, MVT::v4i32, 12 }, // Shift each lane + blend. 994 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 995 996 { ISD::SRA, MVT::v16i8, 27 }, // unpacked cmpgtb sequence. 997 { ISD::SRA, MVT::v8i16, 16 }, // cmpgtw sequence. 998 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 999 { ISD::SRA, MVT::v2i64, 8 }, // srl/xor/sub splat+shuffle sequence. 1000 1001 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 1002 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 1003 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 1004 1005 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 1006 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 1007 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 1008 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 1009 1010 { ISD::FNEG, MVT::f32, 1 }, // Pentium IV from http://www.agner.org/ 1011 { ISD::FNEG, MVT::f64, 1 }, // Pentium IV from http://www.agner.org/ 1012 { ISD::FNEG, MVT::v4f32, 1 }, // Pentium IV from http://www.agner.org/ 1013 { ISD::FNEG, MVT::v2f64, 1 }, // Pentium IV from http://www.agner.org/ 1014 1015 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 1016 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 1017 1018 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 1019 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 1020 }; 1021 1022 if (ST->hasSSE2()) 1023 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 1024 return LT.first * Entry->Cost; 1025 1026 static const CostTblEntry SSE1CostTable[] = { 1027 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 1028 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 1029 1030 { ISD::FNEG, MVT::f32, 2 }, // Pentium III from http://www.agner.org/ 1031 { ISD::FNEG, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1032 1033 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1034 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1035 1036 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1037 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1038 }; 1039 1040 if (ST->hasSSE1()) 1041 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 1042 return LT.first * Entry->Cost; 1043 1044 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 1045 { ISD::ADD, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1046 { ISD::SUB, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1047 { ISD::MUL, MVT::i64, 2 }, // Nehalem from http://www.agner.org/ 1048 }; 1049 1050 if (ST->is64Bit()) 1051 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, LT.second)) 1052 return LT.first * Entry->Cost; 1053 1054 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 1055 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1056 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1057 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1058 1059 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1060 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1061 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1062 }; 1063 1064 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, LT.second)) 1065 return LT.first * Entry->Cost; 1066 1067 // It is not a good idea to vectorize division. We have to scalarize it and 1068 // in the process we will often end up having to spilling regular 1069 // registers. The overhead of division is going to dominate most kernels 1070 // anyways so try hard to prevent vectorization of division - it is 1071 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 1072 // to hide "20 cycles" for each lane. 1073 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 1074 ISD == ISD::UDIV || ISD == ISD::UREM)) { 1075 InstructionCost ScalarCost = getArithmeticInstrCost( 1076 Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info, 1077 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 1078 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 1079 } 1080 1081 // Fallback to the default implementation. 1082 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info); 1083 } 1084 1085 InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, 1086 VectorType *BaseTp, 1087 ArrayRef<int> Mask, int Index, 1088 VectorType *SubTp, 1089 ArrayRef<Value *> Args) { 1090 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 1091 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 1092 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 1093 1094 Kind = improveShuffleKindFromMask(Kind, Mask); 1095 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 1096 if (Kind == TTI::SK_Transpose) 1097 Kind = TTI::SK_PermuteTwoSrc; 1098 1099 // For Broadcasts we are splatting the first element from the first input 1100 // register, so only need to reference that input and all the output 1101 // registers are the same. 1102 if (Kind == TTI::SK_Broadcast) 1103 LT.first = 1; 1104 1105 // Subvector extractions are free if they start at the beginning of a 1106 // vector and cheap if the subvectors are aligned. 1107 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 1108 int NumElts = LT.second.getVectorNumElements(); 1109 if ((Index % NumElts) == 0) 1110 return 0; 1111 std::pair<InstructionCost, MVT> SubLT = 1112 TLI->getTypeLegalizationCost(DL, SubTp); 1113 if (SubLT.second.isVector()) { 1114 int NumSubElts = SubLT.second.getVectorNumElements(); 1115 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1116 return SubLT.first; 1117 // Handle some cases for widening legalization. For now we only handle 1118 // cases where the original subvector was naturally aligned and evenly 1119 // fit in its legalized subvector type. 1120 // FIXME: Remove some of the alignment restrictions. 1121 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 1122 // vectors. 1123 int OrigSubElts = cast<FixedVectorType>(SubTp)->getNumElements(); 1124 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 1125 (NumSubElts % OrigSubElts) == 0 && 1126 LT.second.getVectorElementType() == 1127 SubLT.second.getVectorElementType() && 1128 LT.second.getVectorElementType().getSizeInBits() == 1129 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 1130 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 1131 "Unexpected number of elements!"); 1132 auto *VecTy = FixedVectorType::get(BaseTp->getElementType(), 1133 LT.second.getVectorNumElements()); 1134 auto *SubTy = FixedVectorType::get(BaseTp->getElementType(), 1135 SubLT.second.getVectorNumElements()); 1136 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 1137 InstructionCost ExtractCost = getShuffleCost( 1138 TTI::SK_ExtractSubvector, VecTy, None, ExtractIndex, SubTy); 1139 1140 // If the original size is 32-bits or more, we can use pshufd. Otherwise 1141 // if we have SSSE3 we can use pshufb. 1142 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 1143 return ExtractCost + 1; // pshufd or pshufb 1144 1145 assert(SubTp->getPrimitiveSizeInBits() == 16 && 1146 "Unexpected vector size"); 1147 1148 return ExtractCost + 2; // worst case pshufhw + pshufd 1149 } 1150 } 1151 } 1152 1153 // Subvector insertions are cheap if the subvectors are aligned. 1154 // Note that in general, the insertion starting at the beginning of a vector 1155 // isn't free, because we need to preserve the rest of the wide vector. 1156 if (Kind == TTI::SK_InsertSubvector && LT.second.isVector()) { 1157 int NumElts = LT.second.getVectorNumElements(); 1158 std::pair<InstructionCost, MVT> SubLT = 1159 TLI->getTypeLegalizationCost(DL, SubTp); 1160 if (SubLT.second.isVector()) { 1161 int NumSubElts = SubLT.second.getVectorNumElements(); 1162 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1163 return SubLT.first; 1164 } 1165 1166 // If the insertion isn't aligned, treat it like a 2-op shuffle. 1167 Kind = TTI::SK_PermuteTwoSrc; 1168 } 1169 1170 // Handle some common (illegal) sub-vector types as they are often very cheap 1171 // to shuffle even on targets without PSHUFB. 1172 EVT VT = TLI->getValueType(DL, BaseTp); 1173 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 1174 !ST->hasSSSE3()) { 1175 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 1176 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 1177 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1178 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1179 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1180 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1181 1182 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1183 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1184 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1185 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1186 1187 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1188 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1189 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1190 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1191 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1192 1193 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1194 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1195 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1196 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1197 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1198 }; 1199 1200 if (ST->hasSSE2()) 1201 if (const auto *Entry = 1202 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1203 return Entry->Cost; 1204 } 1205 1206 // We are going to permute multiple sources and the result will be in multiple 1207 // destinations. Providing an accurate cost only for splits where the element 1208 // type remains the same. 1209 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1210 MVT LegalVT = LT.second; 1211 if (LegalVT.isVector() && 1212 LegalVT.getVectorElementType().getSizeInBits() == 1213 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1214 LegalVT.getVectorNumElements() < 1215 cast<FixedVectorType>(BaseTp)->getNumElements()) { 1216 1217 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1218 unsigned LegalVTSize = LegalVT.getStoreSize(); 1219 // Number of source vectors after legalization: 1220 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1221 // Number of destination vectors after legalization: 1222 InstructionCost NumOfDests = LT.first; 1223 1224 auto *SingleOpTy = FixedVectorType::get(BaseTp->getElementType(), 1225 LegalVT.getVectorNumElements()); 1226 1227 InstructionCost NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1228 return NumOfShuffles * getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 1229 None, 0, nullptr); 1230 } 1231 1232 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1233 } 1234 1235 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1236 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1237 // We assume that source and destination have the same vector type. 1238 InstructionCost NumOfDests = LT.first; 1239 InstructionCost NumOfShufflesPerDest = LT.first * 2 - 1; 1240 LT.first = NumOfDests * NumOfShufflesPerDest; 1241 } 1242 1243 static const CostTblEntry AVX512FP16ShuffleTbl[] = { 1244 {TTI::SK_Broadcast, MVT::v32f16, 1}, // vpbroadcastw 1245 {TTI::SK_Broadcast, MVT::v16f16, 1}, // vpbroadcastw 1246 {TTI::SK_Broadcast, MVT::v8f16, 1}, // vpbroadcastw 1247 1248 {TTI::SK_Reverse, MVT::v32f16, 2}, // vpermw 1249 {TTI::SK_Reverse, MVT::v16f16, 2}, // vpermw 1250 {TTI::SK_Reverse, MVT::v8f16, 1}, // vpshufb 1251 1252 {TTI::SK_PermuteSingleSrc, MVT::v32f16, 2}, // vpermw 1253 {TTI::SK_PermuteSingleSrc, MVT::v16f16, 2}, // vpermw 1254 {TTI::SK_PermuteSingleSrc, MVT::v8f16, 1}, // vpshufb 1255 1256 {TTI::SK_PermuteTwoSrc, MVT::v32f16, 2}, // vpermt2w 1257 {TTI::SK_PermuteTwoSrc, MVT::v16f16, 2}, // vpermt2w 1258 {TTI::SK_PermuteTwoSrc, MVT::v8f16, 2} // vpermt2w 1259 }; 1260 1261 if (!ST->useSoftFloat() && ST->hasFP16()) 1262 if (const auto *Entry = 1263 CostTableLookup(AVX512FP16ShuffleTbl, Kind, LT.second)) 1264 return LT.first * Entry->Cost; 1265 1266 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1267 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1268 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1269 1270 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1271 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1272 1273 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b 1274 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b 1275 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2} // vpermt2b 1276 }; 1277 1278 if (ST->hasVBMI()) 1279 if (const auto *Entry = 1280 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1281 return LT.first * Entry->Cost; 1282 1283 static const CostTblEntry AVX512BWShuffleTbl[] = { 1284 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1285 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1286 1287 {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw 1288 {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw 1289 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1290 1291 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw 1292 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw 1293 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1294 1295 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w 1296 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w 1297 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2}, // vpermt2w 1298 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1299 1300 {TTI::SK_Select, MVT::v32i16, 1}, // vblendmw 1301 {TTI::SK_Select, MVT::v64i8, 1}, // vblendmb 1302 }; 1303 1304 if (ST->hasBWI()) 1305 if (const auto *Entry = 1306 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1307 return LT.first * Entry->Cost; 1308 1309 static const CostTblEntry AVX512ShuffleTbl[] = { 1310 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1311 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1312 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1313 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1314 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1315 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1316 1317 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1318 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1319 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1320 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1321 {TTI::SK_Reverse, MVT::v32i16, 7}, // per mca 1322 {TTI::SK_Reverse, MVT::v64i8, 7}, // per mca 1323 1324 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1325 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1326 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1327 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1328 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1329 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1330 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1331 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1332 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1333 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1334 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1335 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1336 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1337 1338 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1339 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1340 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1341 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1342 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1343 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1344 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1345 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1346 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1347 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1348 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1349 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1350 1351 // FIXME: This just applies the type legalization cost rules above 1352 // assuming these completely split. 1353 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1354 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1355 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1356 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1357 1358 {TTI::SK_Select, MVT::v32i16, 1}, // vpternlogq 1359 {TTI::SK_Select, MVT::v64i8, 1}, // vpternlogq 1360 {TTI::SK_Select, MVT::v8f64, 1}, // vblendmpd 1361 {TTI::SK_Select, MVT::v16f32, 1}, // vblendmps 1362 {TTI::SK_Select, MVT::v8i64, 1}, // vblendmq 1363 {TTI::SK_Select, MVT::v16i32, 1}, // vblendmd 1364 }; 1365 1366 if (ST->hasAVX512()) 1367 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1368 return LT.first * Entry->Cost; 1369 1370 static const CostTblEntry AVX2ShuffleTbl[] = { 1371 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1372 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1373 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1374 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1375 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1376 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1377 1378 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1379 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1380 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1381 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1382 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1383 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1384 1385 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1386 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1387 1388 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1389 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1390 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1391 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1392 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1393 // + vpblendvb 1394 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1395 // + vpblendvb 1396 1397 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1398 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1399 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1400 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1401 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1402 // + vpblendvb 1403 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1404 // + vpblendvb 1405 }; 1406 1407 if (ST->hasAVX2()) 1408 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1409 return LT.first * Entry->Cost; 1410 1411 static const CostTblEntry XOPShuffleTbl[] = { 1412 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1413 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1414 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1415 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1416 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1417 // + vinsertf128 1418 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1419 // + vinsertf128 1420 1421 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1422 // + vinsertf128 1423 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1424 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1425 // + vinsertf128 1426 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1427 }; 1428 1429 if (ST->hasXOP()) 1430 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1431 return LT.first * Entry->Cost; 1432 1433 static const CostTblEntry AVX1ShuffleTbl[] = { 1434 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1435 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1436 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1437 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1438 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1439 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1440 1441 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1442 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1443 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1444 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1445 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1446 // + vinsertf128 1447 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1448 // + vinsertf128 1449 1450 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1451 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1452 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1453 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1454 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1455 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1456 1457 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1458 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1459 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1460 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1461 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1462 // + 2*por + vinsertf128 1463 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1464 // + 2*por + vinsertf128 1465 1466 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1467 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1468 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1469 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1470 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1471 // + 4*por + vinsertf128 1472 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1473 // + 4*por + vinsertf128 1474 }; 1475 1476 if (ST->hasAVX()) 1477 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1478 return LT.first * Entry->Cost; 1479 1480 static const CostTblEntry SSE41ShuffleTbl[] = { 1481 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1482 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1483 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1484 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1485 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1486 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1487 }; 1488 1489 if (ST->hasSSE41()) 1490 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1491 return LT.first * Entry->Cost; 1492 1493 static const CostTblEntry SSSE3ShuffleTbl[] = { 1494 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1495 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1496 1497 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1498 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1499 1500 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1501 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1502 1503 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1504 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1505 1506 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1507 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1508 }; 1509 1510 if (ST->hasSSSE3()) 1511 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1512 return LT.first * Entry->Cost; 1513 1514 static const CostTblEntry SSE2ShuffleTbl[] = { 1515 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1516 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1517 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1518 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1519 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1520 1521 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1522 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1523 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1524 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1525 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1526 // + 2*pshufd + 2*unpck + packus 1527 1528 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1529 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1530 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1531 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1532 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1533 1534 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1535 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1536 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1537 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1538 // + pshufd/unpck 1539 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1540 // + 2*pshufd + 2*unpck + 2*packus 1541 1542 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1543 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1544 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1545 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1546 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1547 }; 1548 1549 static const CostTblEntry SSE3BroadcastLoadTbl[] = { 1550 {TTI::SK_Broadcast, MVT::v2f64, 0}, // broadcast handled by movddup 1551 }; 1552 1553 if (ST->hasSSE2()) { 1554 bool IsLoad = !Args.empty() && llvm::all_of(Args, [](const Value *V) { 1555 return isa<LoadInst>(V); 1556 }); 1557 if (ST->hasSSE3() && IsLoad) 1558 if (const auto *Entry = 1559 CostTableLookup(SSE3BroadcastLoadTbl, Kind, LT.second)) { 1560 assert(isLegalBroadcastLoad(BaseTp->getElementType(), 1561 LT.second.getVectorNumElements()) && 1562 "Table entry missing from isLegalBroadcastLoad()"); 1563 return LT.first * Entry->Cost; 1564 } 1565 1566 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1567 return LT.first * Entry->Cost; 1568 } 1569 1570 static const CostTblEntry SSE1ShuffleTbl[] = { 1571 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1572 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1573 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1574 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1575 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1576 }; 1577 1578 if (ST->hasSSE1()) 1579 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1580 return LT.first * Entry->Cost; 1581 1582 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1583 } 1584 1585 InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, 1586 Type *Src, 1587 TTI::CastContextHint CCH, 1588 TTI::TargetCostKind CostKind, 1589 const Instruction *I) { 1590 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1591 assert(ISD && "Invalid opcode"); 1592 1593 // TODO: Allow non-throughput costs that aren't binary. 1594 auto AdjustCost = [&CostKind](InstructionCost Cost) -> InstructionCost { 1595 if (CostKind != TTI::TCK_RecipThroughput) 1596 return Cost == 0 ? 0 : 1; 1597 return Cost; 1598 }; 1599 1600 // The cost tables include both specific, custom (non-legal) src/dst type 1601 // conversions and generic, legalized types. We test for customs first, before 1602 // falling back to legalization. 1603 // FIXME: Need a better design of the cost table to handle non-simple types of 1604 // potential massive combinations (elem_num x src_type x dst_type). 1605 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1606 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1607 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1608 1609 // Mask sign extend has an instruction. 1610 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1611 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v2i1, 1 }, 1612 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1613 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v2i1, 1 }, 1614 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1615 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v4i1, 1 }, 1616 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1617 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v4i1, 1 }, 1618 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1619 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v8i1, 1 }, 1620 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1621 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1622 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1623 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1624 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1625 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1626 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v64i1, 1 }, 1627 1628 // Mask zero extend is a sext + shift. 1629 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1630 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v2i1, 2 }, 1631 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1632 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v2i1, 2 }, 1633 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1634 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v4i1, 2 }, 1635 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1636 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v4i1, 2 }, 1637 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1638 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v8i1, 2 }, 1639 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1640 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1641 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1642 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1643 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1644 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1645 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v64i1, 2 }, 1646 1647 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, 1648 { ISD::TRUNCATE, MVT::v2i1, MVT::v16i8, 2 }, 1649 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, 1650 { ISD::TRUNCATE, MVT::v2i1, MVT::v8i16, 2 }, 1651 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, 1652 { ISD::TRUNCATE, MVT::v4i1, MVT::v16i8, 2 }, 1653 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, 1654 { ISD::TRUNCATE, MVT::v4i1, MVT::v8i16, 2 }, 1655 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, 1656 { ISD::TRUNCATE, MVT::v8i1, MVT::v16i8, 2 }, 1657 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, 1658 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, 1659 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, 1660 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, 1661 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, 1662 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, 1663 { ISD::TRUNCATE, MVT::v64i1, MVT::v32i16, 2 }, 1664 1665 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, 1666 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm 1667 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // vpmovwb 1668 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // vpmovwb 1669 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // vpmovwb 1670 }; 1671 1672 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1673 // Mask sign extend has an instruction. 1674 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, 1675 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v2i1, 1 }, 1676 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, 1677 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, 1678 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, 1679 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v16i1, 1 }, 1680 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, 1681 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, 1682 1683 // Mask zero extend is a sext + shift. 1684 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, 1685 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v2i1, 2 }, 1686 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, 1687 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, 1688 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, 1689 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v16i1, 2 }, 1690 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, 1691 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1692 1693 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, 1694 { ISD::TRUNCATE, MVT::v2i1, MVT::v4i32, 2 }, 1695 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, 1696 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, 1697 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1698 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, 1699 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, 1700 { ISD::TRUNCATE, MVT::v16i1, MVT::v8i64, 2 }, 1701 1702 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1703 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1704 1705 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1706 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1707 1708 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1709 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1710 1711 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1712 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1713 }; 1714 1715 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1716 // 256-bit wide vectors. 1717 1718 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1719 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1720 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1721 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1722 1723 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1724 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1725 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1726 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd 1727 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1728 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1729 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1730 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd 1731 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd 1732 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd 1733 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd 1734 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd 1735 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq 1736 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq 1737 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq 1738 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 2 }, // vpmovdb 1739 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 2 }, // vpmovdb 1740 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, // vpmovdb 1741 { ISD::TRUNCATE, MVT::v32i8, MVT::v16i32, 2 }, // vpmovdb 1742 { ISD::TRUNCATE, MVT::v64i8, MVT::v16i32, 2 }, // vpmovdb 1743 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, // vpmovdw 1744 { ISD::TRUNCATE, MVT::v32i16, MVT::v16i32, 2 }, // vpmovdw 1745 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 2 }, // vpmovqb 1746 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 1 }, // vpshufb 1747 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, // vpmovqb 1748 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i64, 2 }, // vpmovqb 1749 { ISD::TRUNCATE, MVT::v32i8, MVT::v8i64, 2 }, // vpmovqb 1750 { ISD::TRUNCATE, MVT::v64i8, MVT::v8i64, 2 }, // vpmovqb 1751 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, // vpmovqw 1752 { ISD::TRUNCATE, MVT::v16i16, MVT::v8i64, 2 }, // vpmovqw 1753 { ISD::TRUNCATE, MVT::v32i16, MVT::v8i64, 2 }, // vpmovqw 1754 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, // vpmovqd 1755 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd 1756 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb 1757 1758 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32 1759 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, 1760 { ISD::TRUNCATE, MVT::v64i8, MVT::v32i16, 8 }, 1761 1762 // Sign extend is zmm vpternlogd+vptruncdb. 1763 // Zero extend is zmm broadcast load+vptruncdw. 1764 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 }, 1765 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 }, 1766 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, 1767 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, 1768 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, 1769 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, 1770 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 }, 1771 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 }, 1772 1773 // Sign extend is zmm vpternlogd+vptruncdw. 1774 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw. 1775 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 }, 1776 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1777 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 }, 1778 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1779 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 }, 1780 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1781 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 }, 1782 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1783 1784 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd 1785 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld 1786 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd 1787 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld 1788 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd 1789 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld 1790 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq 1791 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq 1792 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq 1793 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq 1794 1795 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd 1796 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld 1797 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq 1798 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq 1799 1800 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1801 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1802 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1803 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1804 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1805 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1806 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1807 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1808 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1809 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1810 1811 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1812 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1813 1814 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1815 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1816 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, 1817 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, 1818 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1819 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, 1820 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1821 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1822 1823 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1824 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1825 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, 1826 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, 1827 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1828 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, 1829 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1830 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1831 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1832 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1833 1834 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2 }, 1835 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f64, 7 }, 1836 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f64,15 }, 1837 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f32,11 }, 1838 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f64,31 }, 1839 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, 1840 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f64, 7 }, 1841 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f32, 5 }, 1842 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f64,15 }, 1843 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 1 }, 1844 { ISD::FP_TO_SINT, MVT::v16i32, MVT::v16f64, 3 }, 1845 1846 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1847 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, 1848 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, 1849 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1850 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, 1851 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, 1852 }; 1853 1854 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1855 // Mask sign extend has an instruction. 1856 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1857 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v2i1, 1 }, 1858 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1859 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v2i1, 1 }, 1860 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1861 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v4i1, 1 }, 1862 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1863 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v4i1, 1 }, 1864 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1865 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v8i1, 1 }, 1866 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1867 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1868 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1869 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1870 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v32i1, 1 }, 1871 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v64i1, 1 }, 1872 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v64i1, 1 }, 1873 1874 // Mask zero extend is a sext + shift. 1875 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1876 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v2i1, 2 }, 1877 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1878 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v2i1, 2 }, 1879 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1880 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v4i1, 2 }, 1881 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1882 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v4i1, 2 }, 1883 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1884 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v8i1, 2 }, 1885 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1886 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1887 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1888 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1889 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v32i1, 2 }, 1890 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v64i1, 2 }, 1891 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v64i1, 2 }, 1892 1893 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, 1894 { ISD::TRUNCATE, MVT::v2i1, MVT::v16i8, 2 }, 1895 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, 1896 { ISD::TRUNCATE, MVT::v2i1, MVT::v8i16, 2 }, 1897 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, 1898 { ISD::TRUNCATE, MVT::v4i1, MVT::v16i8, 2 }, 1899 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, 1900 { ISD::TRUNCATE, MVT::v4i1, MVT::v8i16, 2 }, 1901 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, 1902 { ISD::TRUNCATE, MVT::v8i1, MVT::v16i8, 2 }, 1903 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, 1904 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, 1905 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, 1906 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, 1907 { ISD::TRUNCATE, MVT::v32i1, MVT::v16i16, 2 }, 1908 { ISD::TRUNCATE, MVT::v64i1, MVT::v32i8, 2 }, 1909 { ISD::TRUNCATE, MVT::v64i1, MVT::v16i16, 2 }, 1910 1911 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, 1912 }; 1913 1914 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1915 // Mask sign extend has an instruction. 1916 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, 1917 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v2i1, 1 }, 1918 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, 1919 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i1, 1 }, 1920 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, 1921 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i1, 1 }, 1922 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i1, 1 }, 1923 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, 1924 1925 // Mask zero extend is a sext + shift. 1926 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, 1927 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v2i1, 2 }, 1928 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, 1929 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i1, 2 }, 1930 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, 1931 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i1, 2 }, 1932 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i1, 2 }, 1933 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, 1934 1935 { ISD::TRUNCATE, MVT::v16i1, MVT::v4i64, 2 }, 1936 { ISD::TRUNCATE, MVT::v16i1, MVT::v8i32, 2 }, 1937 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, 1938 { ISD::TRUNCATE, MVT::v2i1, MVT::v4i32, 2 }, 1939 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, 1940 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, 1941 { ISD::TRUNCATE, MVT::v8i1, MVT::v4i64, 2 }, 1942 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1943 1944 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1945 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1946 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1947 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1948 1949 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1950 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1951 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1952 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1953 1954 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v4f32, 1 }, 1955 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1956 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1957 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1958 1959 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v4f32, 1 }, 1960 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1961 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1962 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1963 }; 1964 1965 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 1966 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1967 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1968 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1969 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 8 }, // split+2*v8i8 1970 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1971 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1972 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1973 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16 1974 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // vpslld+vptestmd 1975 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd 1976 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // vpslld+vptestmd 1977 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // vpsllq+vptestmq 1978 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // vpsllq+vptestmq 1979 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // vpmovqd 1980 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, // vpmovqb 1981 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, // vpmovqw 1982 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, // vpmovwb 1983 1984 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb 1985 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb 1986 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 }, 1987 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 }, 1988 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 }, 1989 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 }, 1990 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 }, 1991 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 }, 1992 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 }, 1993 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 }, 1994 1995 // sign extend is vpcmpeq+maskedmove+vpmovdw 1996 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw 1997 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1998 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 }, 1999 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 2000 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 }, 2001 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 2002 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 }, 2003 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 }, 2004 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 }, 2005 2006 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd 2007 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld 2008 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd 2009 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld 2010 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd 2011 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld 2012 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq 2013 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq 2014 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq 2015 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq 2016 2017 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 1 }, 2018 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 1 }, 2019 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 1 }, 2020 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 1 }, 2021 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 2022 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 2023 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 1 }, 2024 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 1 }, 2025 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 2026 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 2027 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 2028 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 2029 2030 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2031 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 1 }, 2032 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2033 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 1 }, 2034 2035 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 2036 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 2037 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2038 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 1 }, 2039 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2040 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 1 }, 2041 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 2042 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 2043 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 2044 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 2045 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 2046 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 2047 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 2048 2049 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v8f32, 2 }, 2050 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2 }, 2051 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f32, 5 }, 2052 2053 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 2054 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 2055 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 2056 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 1 }, 2057 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 2058 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 2059 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 2060 }; 2061 2062 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 2063 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 2064 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 2065 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 2066 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 2067 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 2068 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 2069 2070 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 2 }, 2071 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 2 }, 2072 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 2 }, 2073 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 2 }, 2074 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 2075 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 2076 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 2 }, 2077 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 2 }, 2078 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 2079 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 2080 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 2081 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 2082 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 2083 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 2084 2085 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 2086 2087 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 4 }, 2088 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 4 }, 2089 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i16, 1 }, 2090 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 1 }, 2091 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 1 }, 2092 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i32, 4 }, 2093 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i64, 4 }, 2094 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 1 }, 2095 { ISD::TRUNCATE, MVT::v8i16, MVT::v2i64, 1 }, 2096 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i64, 5 }, 2097 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, 2098 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 2099 2100 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 2101 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 2102 2103 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v8f32, 1 }, 2104 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 1 }, 2105 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 1 }, 2106 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 3 }, 2107 2108 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 3 }, 2109 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 3 }, 2110 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v8f32, 1 }, 2111 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 3 }, 2112 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 2113 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4 }, 2114 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 3 }, 2115 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v4f64, 4 }, 2116 2117 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 2 }, 2118 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 2 }, 2119 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 2 }, 2120 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 2121 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 2122 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 2123 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 3 }, 2124 2125 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 2 }, 2126 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 2 }, 2127 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 2 }, 2128 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 2129 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 2130 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 2131 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 2 }, 2132 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2133 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 2134 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 }, 2135 }; 2136 2137 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 2138 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 2139 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 2140 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 2141 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 2142 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 2143 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 2144 2145 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 3 }, 2146 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 3 }, 2147 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 3 }, 2148 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 3 }, 2149 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 2150 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 2151 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 3 }, 2152 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 3 }, 2153 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 2154 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 2155 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 2156 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 2157 2158 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 4 }, 2159 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 5 }, 2160 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 4 }, 2161 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 9 }, 2162 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, 11 }, 2163 2164 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 2165 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, 2166 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // and+extract+packuswb 2167 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i32, 5 }, 2168 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2169 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i64, 5 }, 2170 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i64, 3 }, // and+extract+2*packusdw 2171 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 2172 2173 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 2174 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 2175 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 2176 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 4 }, 2177 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v16i8, 2 }, 2178 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 2179 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v8i16, 2 }, 2180 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2181 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 2182 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 }, 2183 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 5 }, 2184 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 8 }, 2185 2186 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 2187 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 2188 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 2189 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 4 }, 2190 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v16i8, 2 }, 2191 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 2192 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v8i16, 2 }, 2193 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 4 }, 2194 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 4 }, 2195 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 2196 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 2197 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 2198 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 10 }, 2199 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 10 }, 2200 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 18 }, 2201 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 2202 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 10 }, 2203 2204 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v8f32, 2 }, 2205 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f64, 2 }, 2206 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v8f32, 2 }, 2207 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v4f64, 2 }, 2208 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 2 }, 2209 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f64, 2 }, 2210 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v8f32, 2 }, 2211 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v4f64, 2 }, 2212 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 2 }, 2213 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 2 }, 2214 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 5 }, 2215 2216 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v8f32, 2 }, 2217 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f64, 2 }, 2218 { ISD::FP_TO_UINT, MVT::v32i8, MVT::v8f32, 2 }, 2219 { ISD::FP_TO_UINT, MVT::v32i8, MVT::v4f64, 2 }, 2220 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 2 }, 2221 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f64, 2 }, 2222 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v8f32, 2 }, 2223 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v4f64, 2 }, 2224 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 3 }, 2225 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 2226 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 6 }, 2227 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 7 }, 2228 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v4f64, 7 }, 2229 2230 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 2231 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 2232 }; 2233 2234 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 2235 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8, 1 }, 2236 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8, 1 }, 2237 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8, 1 }, 2238 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8, 1 }, 2239 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2240 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2241 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16, 1 }, 2242 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16, 1 }, 2243 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2244 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2245 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2246 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2247 2248 // These truncates end up widening elements. 2249 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 1 }, // PMOVXZBQ 2250 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 1 }, // PMOVXZWQ 2251 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 1 }, // PMOVXZBD 2252 2253 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 2 }, 2254 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 2 }, 2255 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 2 }, 2256 2257 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 1 }, 2258 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 1 }, 2259 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 1 }, 2260 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 1 }, 2261 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 1 }, 2262 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2263 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 1 }, 2264 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2265 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 2266 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 1 }, 2267 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2268 2269 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 1 }, 2270 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 1 }, 2271 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 2272 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 2273 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 1 }, 2274 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2275 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 1 }, 2276 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2277 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 3 }, 2278 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 3 }, 2279 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 2 }, 2280 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 12 }, 2281 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 22 }, 2282 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 4 }, 2283 2284 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 1 }, 2285 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 1 }, 2286 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 1 }, 2287 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 1 }, 2288 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f32, 2 }, 2289 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v2f64, 2 }, 2290 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f32, 1 }, 2291 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v2f64, 1 }, 2292 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, 2293 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v2f64, 1 }, 2294 2295 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 1 }, 2296 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 2297 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 1 }, 2298 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 2299 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f32, 2 }, 2300 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v2f64, 2 }, 2301 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f32, 1 }, 2302 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v2f64, 1 }, 2303 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 4 }, 2304 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 2305 }; 2306 2307 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 2308 // These are somewhat magic numbers justified by comparing the 2309 // output of llvm-mca for our various supported scheduler models 2310 // and basing it off the worst case scenario. 2311 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 3 }, 2312 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 3 }, 2313 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 3 }, 2314 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 3 }, 2315 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 3 }, 2316 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 4 }, 2317 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 3 }, 2318 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 4 }, 2319 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 3 }, 2320 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4 }, 2321 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 8 }, 2322 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 8 }, 2323 2324 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 3 }, 2325 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 3 }, 2326 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 8 }, 2327 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 9 }, 2328 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 4 }, 2329 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 4 }, 2330 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 4 }, 2331 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 4 }, 2332 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 7 }, 2333 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 7 }, 2334 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 2335 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 15 }, 2336 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 18 }, 2337 2338 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 4 }, 2339 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 4 }, 2340 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 4 }, 2341 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 4 }, 2342 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f32, 6 }, 2343 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v2f64, 6 }, 2344 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f32, 5 }, 2345 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v2f64, 5 }, 2346 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 4 }, 2347 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v2f64, 4 }, 2348 2349 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 4 }, 2350 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 2351 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 4 }, 2352 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 15 }, 2353 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f32, 6 }, 2354 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v2f64, 6 }, 2355 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f32, 5 }, 2356 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v2f64, 5 }, 2357 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 8 }, 2358 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 8 }, 2359 2360 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8, 4 }, 2361 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8, 4 }, 2362 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8, 2 }, 2363 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8, 3 }, 2364 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2365 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8, 2 }, 2366 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16, 2 }, 2367 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16, 3 }, 2368 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2369 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16, 2 }, 2370 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2371 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32, 2 }, 2372 2373 // These truncates are really widening elements. 2374 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 1 }, // PSHUFD 2375 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // PUNPCKLWD+DQ 2376 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // PUNPCKLBW+WD+PSHUFD 2377 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 1 }, // PUNPCKLWD 2378 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // PUNPCKLBW+WD 2379 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 1 }, // PUNPCKLBW 2380 2381 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i16, 2 }, // PAND+PACKUSWB 2382 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 2383 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 3 }, // PAND+2*PACKUSWB 2384 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 2385 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 2386 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 3 }, 2387 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2388 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32,10 }, 2389 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 2390 { ISD::TRUNCATE, MVT::v8i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 2391 { ISD::TRUNCATE, MVT::v4i32, MVT::v2i64, 1 }, // PSHUFD 2392 }; 2393 2394 // Attempt to map directly to (simple) MVT types to let us match custom entries. 2395 EVT SrcTy = TLI->getValueType(DL, Src); 2396 EVT DstTy = TLI->getValueType(DL, Dst); 2397 2398 // The function getSimpleVT only handles simple value types. 2399 if (SrcTy.isSimple() && DstTy.isSimple()) { 2400 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 2401 MVT SimpleDstTy = DstTy.getSimpleVT(); 2402 2403 if (ST->useAVX512Regs()) { 2404 if (ST->hasBWI()) 2405 if (const auto *Entry = ConvertCostTableLookup( 2406 AVX512BWConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2407 return AdjustCost(Entry->Cost); 2408 2409 if (ST->hasDQI()) 2410 if (const auto *Entry = ConvertCostTableLookup( 2411 AVX512DQConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2412 return AdjustCost(Entry->Cost); 2413 2414 if (ST->hasAVX512()) 2415 if (const auto *Entry = ConvertCostTableLookup( 2416 AVX512FConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2417 return AdjustCost(Entry->Cost); 2418 } 2419 2420 if (ST->hasBWI()) 2421 if (const auto *Entry = ConvertCostTableLookup( 2422 AVX512BWVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2423 return AdjustCost(Entry->Cost); 2424 2425 if (ST->hasDQI()) 2426 if (const auto *Entry = ConvertCostTableLookup( 2427 AVX512DQVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2428 return AdjustCost(Entry->Cost); 2429 2430 if (ST->hasAVX512()) 2431 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2432 SimpleDstTy, SimpleSrcTy)) 2433 return AdjustCost(Entry->Cost); 2434 2435 if (ST->hasAVX2()) { 2436 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2437 SimpleDstTy, SimpleSrcTy)) 2438 return AdjustCost(Entry->Cost); 2439 } 2440 2441 if (ST->hasAVX()) { 2442 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2443 SimpleDstTy, SimpleSrcTy)) 2444 return AdjustCost(Entry->Cost); 2445 } 2446 2447 if (ST->hasSSE41()) { 2448 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2449 SimpleDstTy, SimpleSrcTy)) 2450 return AdjustCost(Entry->Cost); 2451 } 2452 2453 if (ST->hasSSE2()) { 2454 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2455 SimpleDstTy, SimpleSrcTy)) 2456 return AdjustCost(Entry->Cost); 2457 } 2458 } 2459 2460 // Fall back to legalized types. 2461 std::pair<InstructionCost, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 2462 std::pair<InstructionCost, MVT> LTDest = 2463 TLI->getTypeLegalizationCost(DL, Dst); 2464 2465 if (ST->useAVX512Regs()) { 2466 if (ST->hasBWI()) 2467 if (const auto *Entry = ConvertCostTableLookup( 2468 AVX512BWConversionTbl, ISD, LTDest.second, LTSrc.second)) 2469 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2470 2471 if (ST->hasDQI()) 2472 if (const auto *Entry = ConvertCostTableLookup( 2473 AVX512DQConversionTbl, ISD, LTDest.second, LTSrc.second)) 2474 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2475 2476 if (ST->hasAVX512()) 2477 if (const auto *Entry = ConvertCostTableLookup( 2478 AVX512FConversionTbl, ISD, LTDest.second, LTSrc.second)) 2479 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2480 } 2481 2482 if (ST->hasBWI()) 2483 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 2484 LTDest.second, LTSrc.second)) 2485 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2486 2487 if (ST->hasDQI()) 2488 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 2489 LTDest.second, LTSrc.second)) 2490 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2491 2492 if (ST->hasAVX512()) 2493 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2494 LTDest.second, LTSrc.second)) 2495 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2496 2497 if (ST->hasAVX2()) 2498 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2499 LTDest.second, LTSrc.second)) 2500 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2501 2502 if (ST->hasAVX()) 2503 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2504 LTDest.second, LTSrc.second)) 2505 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2506 2507 if (ST->hasSSE41()) 2508 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2509 LTDest.second, LTSrc.second)) 2510 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2511 2512 if (ST->hasSSE2()) 2513 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2514 LTDest.second, LTSrc.second)) 2515 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2516 2517 // Fallback, for i8/i16 sitofp/uitofp cases we need to extend to i32 for 2518 // sitofp. 2519 if ((ISD == ISD::SINT_TO_FP || ISD == ISD::UINT_TO_FP) && 2520 1 < Src->getScalarSizeInBits() && Src->getScalarSizeInBits() < 32) { 2521 Type *ExtSrc = Src->getWithNewBitWidth(32); 2522 unsigned ExtOpc = 2523 (ISD == ISD::SINT_TO_FP) ? Instruction::SExt : Instruction::ZExt; 2524 2525 // For scalar loads the extend would be free. 2526 InstructionCost ExtCost = 0; 2527 if (!(Src->isIntegerTy() && I && isa<LoadInst>(I->getOperand(0)))) 2528 ExtCost = getCastInstrCost(ExtOpc, ExtSrc, Src, CCH, CostKind); 2529 2530 return ExtCost + getCastInstrCost(Instruction::SIToFP, Dst, ExtSrc, 2531 TTI::CastContextHint::None, CostKind); 2532 } 2533 2534 // Fallback for fptosi/fptoui i8/i16 cases we need to truncate from fptosi 2535 // i32. 2536 if ((ISD == ISD::FP_TO_SINT || ISD == ISD::FP_TO_UINT) && 2537 1 < Dst->getScalarSizeInBits() && Dst->getScalarSizeInBits() < 32) { 2538 Type *TruncDst = Dst->getWithNewBitWidth(32); 2539 return getCastInstrCost(Instruction::FPToSI, TruncDst, Src, CCH, CostKind) + 2540 getCastInstrCost(Instruction::Trunc, Dst, TruncDst, 2541 TTI::CastContextHint::None, CostKind); 2542 } 2543 2544 return AdjustCost( 2545 BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I)); 2546 } 2547 2548 InstructionCost X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 2549 Type *CondTy, 2550 CmpInst::Predicate VecPred, 2551 TTI::TargetCostKind CostKind, 2552 const Instruction *I) { 2553 // TODO: Handle other cost kinds. 2554 if (CostKind != TTI::TCK_RecipThroughput) 2555 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, 2556 I); 2557 2558 // Legalize the type. 2559 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2560 2561 MVT MTy = LT.second; 2562 2563 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2564 assert(ISD && "Invalid opcode"); 2565 2566 unsigned ExtraCost = 0; 2567 if (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp) { 2568 // Some vector comparison predicates cost extra instructions. 2569 // TODO: Should we invert this and assume worst case cmp costs 2570 // and reduce for particular predicates? 2571 if (MTy.isVector() && 2572 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 2573 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 2574 ST->hasBWI())) { 2575 // Fallback to I if a specific predicate wasn't specified. 2576 CmpInst::Predicate Pred = VecPred; 2577 if (I && (Pred == CmpInst::BAD_ICMP_PREDICATE || 2578 Pred == CmpInst::BAD_FCMP_PREDICATE)) 2579 Pred = cast<CmpInst>(I)->getPredicate(); 2580 2581 switch (Pred) { 2582 case CmpInst::Predicate::ICMP_NE: 2583 // xor(cmpeq(x,y),-1) 2584 ExtraCost = 1; 2585 break; 2586 case CmpInst::Predicate::ICMP_SGE: 2587 case CmpInst::Predicate::ICMP_SLE: 2588 // xor(cmpgt(x,y),-1) 2589 ExtraCost = 1; 2590 break; 2591 case CmpInst::Predicate::ICMP_ULT: 2592 case CmpInst::Predicate::ICMP_UGT: 2593 // cmpgt(xor(x,signbit),xor(y,signbit)) 2594 // xor(cmpeq(pmaxu(x,y),x),-1) 2595 ExtraCost = 2; 2596 break; 2597 case CmpInst::Predicate::ICMP_ULE: 2598 case CmpInst::Predicate::ICMP_UGE: 2599 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 2600 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 2601 // cmpeq(psubus(x,y),0) 2602 // cmpeq(pminu(x,y),x) 2603 ExtraCost = 1; 2604 } else { 2605 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 2606 ExtraCost = 3; 2607 } 2608 break; 2609 case CmpInst::Predicate::BAD_ICMP_PREDICATE: 2610 case CmpInst::Predicate::BAD_FCMP_PREDICATE: 2611 // Assume worst case scenario and add the maximum extra cost. 2612 ExtraCost = 3; 2613 break; 2614 default: 2615 break; 2616 } 2617 } 2618 } 2619 2620 static const CostTblEntry SLMCostTbl[] = { 2621 // slm pcmpeq/pcmpgt throughput is 2 2622 { ISD::SETCC, MVT::v2i64, 2 }, 2623 }; 2624 2625 static const CostTblEntry AVX512BWCostTbl[] = { 2626 { ISD::SETCC, MVT::v32i16, 1 }, 2627 { ISD::SETCC, MVT::v64i8, 1 }, 2628 2629 { ISD::SELECT, MVT::v32i16, 1 }, 2630 { ISD::SELECT, MVT::v64i8, 1 }, 2631 }; 2632 2633 static const CostTblEntry AVX512CostTbl[] = { 2634 { ISD::SETCC, MVT::v8i64, 1 }, 2635 { ISD::SETCC, MVT::v16i32, 1 }, 2636 { ISD::SETCC, MVT::v8f64, 1 }, 2637 { ISD::SETCC, MVT::v16f32, 1 }, 2638 2639 { ISD::SELECT, MVT::v8i64, 1 }, 2640 { ISD::SELECT, MVT::v16i32, 1 }, 2641 { ISD::SELECT, MVT::v8f64, 1 }, 2642 { ISD::SELECT, MVT::v16f32, 1 }, 2643 2644 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 2645 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 2646 2647 { ISD::SELECT, MVT::v32i16, 2 }, // FIXME: should be 3 2648 { ISD::SELECT, MVT::v64i8, 2 }, // FIXME: should be 3 2649 }; 2650 2651 static const CostTblEntry AVX2CostTbl[] = { 2652 { ISD::SETCC, MVT::v4i64, 1 }, 2653 { ISD::SETCC, MVT::v8i32, 1 }, 2654 { ISD::SETCC, MVT::v16i16, 1 }, 2655 { ISD::SETCC, MVT::v32i8, 1 }, 2656 2657 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 2658 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 2659 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 2660 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 2661 }; 2662 2663 static const CostTblEntry AVX1CostTbl[] = { 2664 { ISD::SETCC, MVT::v4f64, 1 }, 2665 { ISD::SETCC, MVT::v8f32, 1 }, 2666 // AVX1 does not support 8-wide integer compare. 2667 { ISD::SETCC, MVT::v4i64, 4 }, 2668 { ISD::SETCC, MVT::v8i32, 4 }, 2669 { ISD::SETCC, MVT::v16i16, 4 }, 2670 { ISD::SETCC, MVT::v32i8, 4 }, 2671 2672 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 2673 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 2674 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 2675 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 2676 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 2677 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 2678 }; 2679 2680 static const CostTblEntry SSE42CostTbl[] = { 2681 { ISD::SETCC, MVT::v2f64, 1 }, 2682 { ISD::SETCC, MVT::v4f32, 1 }, 2683 { ISD::SETCC, MVT::v2i64, 1 }, 2684 }; 2685 2686 static const CostTblEntry SSE41CostTbl[] = { 2687 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 2688 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 2689 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 2690 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 2691 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 2692 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 2693 }; 2694 2695 static const CostTblEntry SSE2CostTbl[] = { 2696 { ISD::SETCC, MVT::v2f64, 2 }, 2697 { ISD::SETCC, MVT::f64, 1 }, 2698 { ISD::SETCC, MVT::v2i64, 5 }, // pcmpeqd/pcmpgtd expansion 2699 { ISD::SETCC, MVT::v4i32, 1 }, 2700 { ISD::SETCC, MVT::v8i16, 1 }, 2701 { ISD::SETCC, MVT::v16i8, 1 }, 2702 2703 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 2704 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 2705 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 2706 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 2707 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 2708 }; 2709 2710 static const CostTblEntry SSE1CostTbl[] = { 2711 { ISD::SETCC, MVT::v4f32, 2 }, 2712 { ISD::SETCC, MVT::f32, 1 }, 2713 2714 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 2715 }; 2716 2717 if (ST->useSLMArithCosts()) 2718 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2719 return LT.first * (ExtraCost + Entry->Cost); 2720 2721 if (ST->hasBWI()) 2722 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2723 return LT.first * (ExtraCost + Entry->Cost); 2724 2725 if (ST->hasAVX512()) 2726 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2727 return LT.first * (ExtraCost + Entry->Cost); 2728 2729 if (ST->hasAVX2()) 2730 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2731 return LT.first * (ExtraCost + Entry->Cost); 2732 2733 if (ST->hasAVX()) 2734 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2735 return LT.first * (ExtraCost + Entry->Cost); 2736 2737 if (ST->hasSSE42()) 2738 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2739 return LT.first * (ExtraCost + Entry->Cost); 2740 2741 if (ST->hasSSE41()) 2742 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2743 return LT.first * (ExtraCost + Entry->Cost); 2744 2745 if (ST->hasSSE2()) 2746 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2747 return LT.first * (ExtraCost + Entry->Cost); 2748 2749 if (ST->hasSSE1()) 2750 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2751 return LT.first * (ExtraCost + Entry->Cost); 2752 2753 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I); 2754 } 2755 2756 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2757 2758 InstructionCost 2759 X86TTIImpl::getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 2760 TTI::TargetCostKind CostKind) { 2761 2762 // Costs should match the codegen from: 2763 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2764 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2765 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2766 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2767 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2768 2769 // TODO: Overflow intrinsics (*ADDO, *SUBO, *MULO) with vector types are not 2770 // specialized in these tables yet. 2771 static const CostTblEntry AVX512BITALGCostTbl[] = { 2772 { ISD::CTPOP, MVT::v32i16, 1 }, 2773 { ISD::CTPOP, MVT::v64i8, 1 }, 2774 { ISD::CTPOP, MVT::v16i16, 1 }, 2775 { ISD::CTPOP, MVT::v32i8, 1 }, 2776 { ISD::CTPOP, MVT::v8i16, 1 }, 2777 { ISD::CTPOP, MVT::v16i8, 1 }, 2778 }; 2779 static const CostTblEntry AVX512VPOPCNTDQCostTbl[] = { 2780 { ISD::CTPOP, MVT::v8i64, 1 }, 2781 { ISD::CTPOP, MVT::v16i32, 1 }, 2782 { ISD::CTPOP, MVT::v4i64, 1 }, 2783 { ISD::CTPOP, MVT::v8i32, 1 }, 2784 { ISD::CTPOP, MVT::v2i64, 1 }, 2785 { ISD::CTPOP, MVT::v4i32, 1 }, 2786 }; 2787 static const CostTblEntry AVX512CDCostTbl[] = { 2788 { ISD::CTLZ, MVT::v8i64, 1 }, 2789 { ISD::CTLZ, MVT::v16i32, 1 }, 2790 { ISD::CTLZ, MVT::v32i16, 8 }, 2791 { ISD::CTLZ, MVT::v64i8, 20 }, 2792 { ISD::CTLZ, MVT::v4i64, 1 }, 2793 { ISD::CTLZ, MVT::v8i32, 1 }, 2794 { ISD::CTLZ, MVT::v16i16, 4 }, 2795 { ISD::CTLZ, MVT::v32i8, 10 }, 2796 { ISD::CTLZ, MVT::v2i64, 1 }, 2797 { ISD::CTLZ, MVT::v4i32, 1 }, 2798 { ISD::CTLZ, MVT::v8i16, 4 }, 2799 { ISD::CTLZ, MVT::v16i8, 4 }, 2800 }; 2801 static const CostTblEntry AVX512BWCostTbl[] = { 2802 { ISD::ABS, MVT::v32i16, 1 }, 2803 { ISD::ABS, MVT::v64i8, 1 }, 2804 { ISD::BITREVERSE, MVT::v8i64, 3 }, 2805 { ISD::BITREVERSE, MVT::v16i32, 3 }, 2806 { ISD::BITREVERSE, MVT::v32i16, 3 }, 2807 { ISD::BITREVERSE, MVT::v64i8, 2 }, 2808 { ISD::BSWAP, MVT::v8i64, 1 }, 2809 { ISD::BSWAP, MVT::v16i32, 1 }, 2810 { ISD::BSWAP, MVT::v32i16, 1 }, 2811 { ISD::CTLZ, MVT::v8i64, 23 }, 2812 { ISD::CTLZ, MVT::v16i32, 22 }, 2813 { ISD::CTLZ, MVT::v32i16, 18 }, 2814 { ISD::CTLZ, MVT::v64i8, 17 }, 2815 { ISD::CTPOP, MVT::v8i64, 7 }, 2816 { ISD::CTPOP, MVT::v16i32, 11 }, 2817 { ISD::CTPOP, MVT::v32i16, 9 }, 2818 { ISD::CTPOP, MVT::v64i8, 6 }, 2819 { ISD::CTTZ, MVT::v8i64, 10 }, 2820 { ISD::CTTZ, MVT::v16i32, 14 }, 2821 { ISD::CTTZ, MVT::v32i16, 12 }, 2822 { ISD::CTTZ, MVT::v64i8, 9 }, 2823 { ISD::SADDSAT, MVT::v32i16, 1 }, 2824 { ISD::SADDSAT, MVT::v64i8, 1 }, 2825 { ISD::SMAX, MVT::v32i16, 1 }, 2826 { ISD::SMAX, MVT::v64i8, 1 }, 2827 { ISD::SMIN, MVT::v32i16, 1 }, 2828 { ISD::SMIN, MVT::v64i8, 1 }, 2829 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2830 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2831 { ISD::UADDSAT, MVT::v32i16, 1 }, 2832 { ISD::UADDSAT, MVT::v64i8, 1 }, 2833 { ISD::UMAX, MVT::v32i16, 1 }, 2834 { ISD::UMAX, MVT::v64i8, 1 }, 2835 { ISD::UMIN, MVT::v32i16, 1 }, 2836 { ISD::UMIN, MVT::v64i8, 1 }, 2837 { ISD::USUBSAT, MVT::v32i16, 1 }, 2838 { ISD::USUBSAT, MVT::v64i8, 1 }, 2839 }; 2840 static const CostTblEntry AVX512CostTbl[] = { 2841 { ISD::ABS, MVT::v8i64, 1 }, 2842 { ISD::ABS, MVT::v16i32, 1 }, 2843 { ISD::ABS, MVT::v32i16, 2 }, 2844 { ISD::ABS, MVT::v64i8, 2 }, 2845 { ISD::ABS, MVT::v4i64, 1 }, 2846 { ISD::ABS, MVT::v2i64, 1 }, 2847 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2848 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2849 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2850 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2851 { ISD::BSWAP, MVT::v8i64, 4 }, 2852 { ISD::BSWAP, MVT::v16i32, 4 }, 2853 { ISD::BSWAP, MVT::v32i16, 4 }, 2854 { ISD::CTLZ, MVT::v8i64, 29 }, 2855 { ISD::CTLZ, MVT::v16i32, 35 }, 2856 { ISD::CTLZ, MVT::v32i16, 28 }, 2857 { ISD::CTLZ, MVT::v64i8, 18 }, 2858 { ISD::CTPOP, MVT::v8i64, 16 }, 2859 { ISD::CTPOP, MVT::v16i32, 24 }, 2860 { ISD::CTPOP, MVT::v32i16, 18 }, 2861 { ISD::CTPOP, MVT::v64i8, 12 }, 2862 { ISD::CTTZ, MVT::v8i64, 20 }, 2863 { ISD::CTTZ, MVT::v16i32, 28 }, 2864 { ISD::CTTZ, MVT::v32i16, 24 }, 2865 { ISD::CTTZ, MVT::v64i8, 18 }, 2866 { ISD::SMAX, MVT::v8i64, 1 }, 2867 { ISD::SMAX, MVT::v16i32, 1 }, 2868 { ISD::SMAX, MVT::v32i16, 2 }, 2869 { ISD::SMAX, MVT::v64i8, 2 }, 2870 { ISD::SMAX, MVT::v4i64, 1 }, 2871 { ISD::SMAX, MVT::v2i64, 1 }, 2872 { ISD::SMIN, MVT::v8i64, 1 }, 2873 { ISD::SMIN, MVT::v16i32, 1 }, 2874 { ISD::SMIN, MVT::v32i16, 2 }, 2875 { ISD::SMIN, MVT::v64i8, 2 }, 2876 { ISD::SMIN, MVT::v4i64, 1 }, 2877 { ISD::SMIN, MVT::v2i64, 1 }, 2878 { ISD::UMAX, MVT::v8i64, 1 }, 2879 { ISD::UMAX, MVT::v16i32, 1 }, 2880 { ISD::UMAX, MVT::v32i16, 2 }, 2881 { ISD::UMAX, MVT::v64i8, 2 }, 2882 { ISD::UMAX, MVT::v4i64, 1 }, 2883 { ISD::UMAX, MVT::v2i64, 1 }, 2884 { ISD::UMIN, MVT::v8i64, 1 }, 2885 { ISD::UMIN, MVT::v16i32, 1 }, 2886 { ISD::UMIN, MVT::v32i16, 2 }, 2887 { ISD::UMIN, MVT::v64i8, 2 }, 2888 { ISD::UMIN, MVT::v4i64, 1 }, 2889 { ISD::UMIN, MVT::v2i64, 1 }, 2890 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2891 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2892 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2893 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2894 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2895 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2896 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2897 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2898 { ISD::SADDSAT, MVT::v32i16, 2 }, 2899 { ISD::SADDSAT, MVT::v64i8, 2 }, 2900 { ISD::SSUBSAT, MVT::v32i16, 2 }, 2901 { ISD::SSUBSAT, MVT::v64i8, 2 }, 2902 { ISD::UADDSAT, MVT::v32i16, 2 }, 2903 { ISD::UADDSAT, MVT::v64i8, 2 }, 2904 { ISD::USUBSAT, MVT::v32i16, 2 }, 2905 { ISD::USUBSAT, MVT::v64i8, 2 }, 2906 { ISD::FMAXNUM, MVT::f32, 2 }, 2907 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2908 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2909 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2910 { ISD::FMAXNUM, MVT::f64, 2 }, 2911 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2912 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2913 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2914 }; 2915 static const CostTblEntry XOPCostTbl[] = { 2916 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2917 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2918 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2919 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2920 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2921 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2922 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2923 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2924 { ISD::BITREVERSE, MVT::i64, 3 }, 2925 { ISD::BITREVERSE, MVT::i32, 3 }, 2926 { ISD::BITREVERSE, MVT::i16, 3 }, 2927 { ISD::BITREVERSE, MVT::i8, 3 } 2928 }; 2929 static const CostTblEntry AVX2CostTbl[] = { 2930 { ISD::ABS, MVT::v4i64, 2 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2931 { ISD::ABS, MVT::v8i32, 1 }, 2932 { ISD::ABS, MVT::v16i16, 1 }, 2933 { ISD::ABS, MVT::v32i8, 1 }, 2934 { ISD::BITREVERSE, MVT::v2i64, 3 }, 2935 { ISD::BITREVERSE, MVT::v4i64, 3 }, 2936 { ISD::BITREVERSE, MVT::v4i32, 3 }, 2937 { ISD::BITREVERSE, MVT::v8i32, 3 }, 2938 { ISD::BITREVERSE, MVT::v8i16, 3 }, 2939 { ISD::BITREVERSE, MVT::v16i16, 3 }, 2940 { ISD::BITREVERSE, MVT::v16i8, 3 }, 2941 { ISD::BITREVERSE, MVT::v32i8, 3 }, 2942 { ISD::BSWAP, MVT::v4i64, 1 }, 2943 { ISD::BSWAP, MVT::v8i32, 1 }, 2944 { ISD::BSWAP, MVT::v16i16, 1 }, 2945 { ISD::CTLZ, MVT::v2i64, 7 }, 2946 { ISD::CTLZ, MVT::v4i64, 7 }, 2947 { ISD::CTLZ, MVT::v4i32, 5 }, 2948 { ISD::CTLZ, MVT::v8i32, 5 }, 2949 { ISD::CTLZ, MVT::v8i16, 4 }, 2950 { ISD::CTLZ, MVT::v16i16, 4 }, 2951 { ISD::CTLZ, MVT::v16i8, 3 }, 2952 { ISD::CTLZ, MVT::v32i8, 3 }, 2953 { ISD::CTPOP, MVT::v2i64, 3 }, 2954 { ISD::CTPOP, MVT::v4i64, 3 }, 2955 { ISD::CTPOP, MVT::v4i32, 7 }, 2956 { ISD::CTPOP, MVT::v8i32, 7 }, 2957 { ISD::CTPOP, MVT::v8i16, 3 }, 2958 { ISD::CTPOP, MVT::v16i16, 3 }, 2959 { ISD::CTPOP, MVT::v16i8, 2 }, 2960 { ISD::CTPOP, MVT::v32i8, 2 }, 2961 { ISD::CTTZ, MVT::v2i64, 4 }, 2962 { ISD::CTTZ, MVT::v4i64, 4 }, 2963 { ISD::CTTZ, MVT::v4i32, 7 }, 2964 { ISD::CTTZ, MVT::v8i32, 7 }, 2965 { ISD::CTTZ, MVT::v8i16, 4 }, 2966 { ISD::CTTZ, MVT::v16i16, 4 }, 2967 { ISD::CTTZ, MVT::v16i8, 3 }, 2968 { ISD::CTTZ, MVT::v32i8, 3 }, 2969 { ISD::SADDSAT, MVT::v16i16, 1 }, 2970 { ISD::SADDSAT, MVT::v32i8, 1 }, 2971 { ISD::SMAX, MVT::v8i32, 1 }, 2972 { ISD::SMAX, MVT::v16i16, 1 }, 2973 { ISD::SMAX, MVT::v32i8, 1 }, 2974 { ISD::SMIN, MVT::v8i32, 1 }, 2975 { ISD::SMIN, MVT::v16i16, 1 }, 2976 { ISD::SMIN, MVT::v32i8, 1 }, 2977 { ISD::SSUBSAT, MVT::v16i16, 1 }, 2978 { ISD::SSUBSAT, MVT::v32i8, 1 }, 2979 { ISD::UADDSAT, MVT::v16i16, 1 }, 2980 { ISD::UADDSAT, MVT::v32i8, 1 }, 2981 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 2982 { ISD::UMAX, MVT::v8i32, 1 }, 2983 { ISD::UMAX, MVT::v16i16, 1 }, 2984 { ISD::UMAX, MVT::v32i8, 1 }, 2985 { ISD::UMIN, MVT::v8i32, 1 }, 2986 { ISD::UMIN, MVT::v16i16, 1 }, 2987 { ISD::UMIN, MVT::v32i8, 1 }, 2988 { ISD::USUBSAT, MVT::v16i16, 1 }, 2989 { ISD::USUBSAT, MVT::v32i8, 1 }, 2990 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2991 { ISD::FMAXNUM, MVT::v8f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2992 { ISD::FMAXNUM, MVT::v4f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2993 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2994 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2995 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2996 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2997 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2998 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2999 }; 3000 static const CostTblEntry AVX1CostTbl[] = { 3001 { ISD::ABS, MVT::v4i64, 5 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 3002 { ISD::ABS, MVT::v8i32, 3 }, 3003 { ISD::ABS, MVT::v16i16, 3 }, 3004 { ISD::ABS, MVT::v32i8, 3 }, 3005 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 3006 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 3007 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 3008 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 3009 { ISD::BSWAP, MVT::v4i64, 4 }, 3010 { ISD::BSWAP, MVT::v8i32, 4 }, 3011 { ISD::BSWAP, MVT::v16i16, 4 }, 3012 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 3013 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 3014 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 3015 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 3016 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 3017 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 3018 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 3019 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 3020 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 3021 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 3022 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 3023 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 3024 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3025 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3026 { ISD::SMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3027 { ISD::SMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3028 { ISD::SMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3029 { ISD::SMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3030 { ISD::SMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3031 { ISD::SMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3032 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3033 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3034 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3035 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3036 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 3037 { ISD::UMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3038 { ISD::UMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3039 { ISD::UMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3040 { ISD::UMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3041 { ISD::UMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3042 { ISD::UMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3043 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3044 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3045 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 3046 { ISD::FMAXNUM, MVT::f32, 3 }, // MAXSS + CMPUNORDSS + BLENDVPS 3047 { ISD::FMAXNUM, MVT::v4f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 3048 { ISD::FMAXNUM, MVT::v8f32, 5 }, // MAXPS + CMPUNORDPS + BLENDVPS + ? 3049 { ISD::FMAXNUM, MVT::f64, 3 }, // MAXSD + CMPUNORDSD + BLENDVPD 3050 { ISD::FMAXNUM, MVT::v2f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 3051 { ISD::FMAXNUM, MVT::v4f64, 5 }, // MAXPD + CMPUNORDPD + BLENDVPD + ? 3052 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 3053 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 3054 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 3055 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 3056 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 3057 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 3058 }; 3059 static const CostTblEntry GLMCostTbl[] = { 3060 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 3061 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 3062 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 3063 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 3064 }; 3065 static const CostTblEntry SLMCostTbl[] = { 3066 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 3067 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 3068 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 3069 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 3070 }; 3071 static const CostTblEntry SSE42CostTbl[] = { 3072 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 3073 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 3074 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 3075 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 3076 }; 3077 static const CostTblEntry SSE41CostTbl[] = { 3078 { ISD::ABS, MVT::v2i64, 2 }, // BLENDVPD(X,PSUBQ(0,X),X) 3079 { ISD::SMAX, MVT::v4i32, 1 }, 3080 { ISD::SMAX, MVT::v16i8, 1 }, 3081 { ISD::SMIN, MVT::v4i32, 1 }, 3082 { ISD::SMIN, MVT::v16i8, 1 }, 3083 { ISD::UMAX, MVT::v4i32, 1 }, 3084 { ISD::UMAX, MVT::v8i16, 1 }, 3085 { ISD::UMIN, MVT::v4i32, 1 }, 3086 { ISD::UMIN, MVT::v8i16, 1 }, 3087 }; 3088 static const CostTblEntry SSSE3CostTbl[] = { 3089 { ISD::ABS, MVT::v4i32, 1 }, 3090 { ISD::ABS, MVT::v8i16, 1 }, 3091 { ISD::ABS, MVT::v16i8, 1 }, 3092 { ISD::BITREVERSE, MVT::v2i64, 5 }, 3093 { ISD::BITREVERSE, MVT::v4i32, 5 }, 3094 { ISD::BITREVERSE, MVT::v8i16, 5 }, 3095 { ISD::BITREVERSE, MVT::v16i8, 5 }, 3096 { ISD::BSWAP, MVT::v2i64, 1 }, 3097 { ISD::BSWAP, MVT::v4i32, 1 }, 3098 { ISD::BSWAP, MVT::v8i16, 1 }, 3099 { ISD::CTLZ, MVT::v2i64, 23 }, 3100 { ISD::CTLZ, MVT::v4i32, 18 }, 3101 { ISD::CTLZ, MVT::v8i16, 14 }, 3102 { ISD::CTLZ, MVT::v16i8, 9 }, 3103 { ISD::CTPOP, MVT::v2i64, 7 }, 3104 { ISD::CTPOP, MVT::v4i32, 11 }, 3105 { ISD::CTPOP, MVT::v8i16, 9 }, 3106 { ISD::CTPOP, MVT::v16i8, 6 }, 3107 { ISD::CTTZ, MVT::v2i64, 10 }, 3108 { ISD::CTTZ, MVT::v4i32, 14 }, 3109 { ISD::CTTZ, MVT::v8i16, 12 }, 3110 { ISD::CTTZ, MVT::v16i8, 9 } 3111 }; 3112 static const CostTblEntry SSE2CostTbl[] = { 3113 { ISD::ABS, MVT::v2i64, 4 }, 3114 { ISD::ABS, MVT::v4i32, 3 }, 3115 { ISD::ABS, MVT::v8i16, 2 }, 3116 { ISD::ABS, MVT::v16i8, 2 }, 3117 { ISD::BITREVERSE, MVT::v2i64, 29 }, 3118 { ISD::BITREVERSE, MVT::v4i32, 27 }, 3119 { ISD::BITREVERSE, MVT::v8i16, 27 }, 3120 { ISD::BITREVERSE, MVT::v16i8, 20 }, 3121 { ISD::BSWAP, MVT::v2i64, 7 }, 3122 { ISD::BSWAP, MVT::v4i32, 7 }, 3123 { ISD::BSWAP, MVT::v8i16, 7 }, 3124 { ISD::CTLZ, MVT::v2i64, 25 }, 3125 { ISD::CTLZ, MVT::v4i32, 26 }, 3126 { ISD::CTLZ, MVT::v8i16, 20 }, 3127 { ISD::CTLZ, MVT::v16i8, 17 }, 3128 { ISD::CTPOP, MVT::v2i64, 12 }, 3129 { ISD::CTPOP, MVT::v4i32, 15 }, 3130 { ISD::CTPOP, MVT::v8i16, 13 }, 3131 { ISD::CTPOP, MVT::v16i8, 10 }, 3132 { ISD::CTTZ, MVT::v2i64, 14 }, 3133 { ISD::CTTZ, MVT::v4i32, 18 }, 3134 { ISD::CTTZ, MVT::v8i16, 16 }, 3135 { ISD::CTTZ, MVT::v16i8, 13 }, 3136 { ISD::SADDSAT, MVT::v8i16, 1 }, 3137 { ISD::SADDSAT, MVT::v16i8, 1 }, 3138 { ISD::SMAX, MVT::v8i16, 1 }, 3139 { ISD::SMIN, MVT::v8i16, 1 }, 3140 { ISD::SSUBSAT, MVT::v8i16, 1 }, 3141 { ISD::SSUBSAT, MVT::v16i8, 1 }, 3142 { ISD::UADDSAT, MVT::v8i16, 1 }, 3143 { ISD::UADDSAT, MVT::v16i8, 1 }, 3144 { ISD::UMAX, MVT::v8i16, 2 }, 3145 { ISD::UMAX, MVT::v16i8, 1 }, 3146 { ISD::UMIN, MVT::v8i16, 2 }, 3147 { ISD::UMIN, MVT::v16i8, 1 }, 3148 { ISD::USUBSAT, MVT::v8i16, 1 }, 3149 { ISD::USUBSAT, MVT::v16i8, 1 }, 3150 { ISD::FMAXNUM, MVT::f64, 4 }, 3151 { ISD::FMAXNUM, MVT::v2f64, 4 }, 3152 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 3153 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 3154 }; 3155 static const CostTblEntry SSE1CostTbl[] = { 3156 { ISD::FMAXNUM, MVT::f32, 4 }, 3157 { ISD::FMAXNUM, MVT::v4f32, 4 }, 3158 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 3159 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 3160 }; 3161 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 3162 { ISD::CTTZ, MVT::i64, 1 }, 3163 }; 3164 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 3165 { ISD::CTTZ, MVT::i32, 1 }, 3166 { ISD::CTTZ, MVT::i16, 1 }, 3167 { ISD::CTTZ, MVT::i8, 1 }, 3168 }; 3169 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 3170 { ISD::CTLZ, MVT::i64, 1 }, 3171 }; 3172 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 3173 { ISD::CTLZ, MVT::i32, 1 }, 3174 { ISD::CTLZ, MVT::i16, 1 }, 3175 { ISD::CTLZ, MVT::i8, 1 }, 3176 }; 3177 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 3178 { ISD::CTPOP, MVT::i64, 1 }, 3179 }; 3180 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 3181 { ISD::CTPOP, MVT::i32, 1 }, 3182 { ISD::CTPOP, MVT::i16, 1 }, 3183 { ISD::CTPOP, MVT::i8, 1 }, 3184 }; 3185 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 3186 { ISD::ABS, MVT::i64, 2 }, // SUB+CMOV 3187 { ISD::BITREVERSE, MVT::i64, 14 }, 3188 { ISD::BSWAP, MVT::i64, 1 }, 3189 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 3190 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 3191 { ISD::CTPOP, MVT::i64, 10 }, 3192 { ISD::SADDO, MVT::i64, 1 }, 3193 { ISD::UADDO, MVT::i64, 1 }, 3194 { ISD::UMULO, MVT::i64, 2 }, // mulq + seto 3195 }; 3196 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 3197 { ISD::ABS, MVT::i32, 2 }, // SUB+CMOV 3198 { ISD::ABS, MVT::i16, 2 }, // SUB+CMOV 3199 { ISD::BITREVERSE, MVT::i32, 14 }, 3200 { ISD::BITREVERSE, MVT::i16, 14 }, 3201 { ISD::BITREVERSE, MVT::i8, 11 }, 3202 { ISD::BSWAP, MVT::i32, 1 }, 3203 { ISD::BSWAP, MVT::i16, 1 }, // ROL 3204 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 3205 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 3206 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 3207 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 3208 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 3209 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 3210 { ISD::CTPOP, MVT::i32, 8 }, 3211 { ISD::CTPOP, MVT::i16, 9 }, 3212 { ISD::CTPOP, MVT::i8, 7 }, 3213 { ISD::SADDO, MVT::i32, 1 }, 3214 { ISD::SADDO, MVT::i16, 1 }, 3215 { ISD::SADDO, MVT::i8, 1 }, 3216 { ISD::UADDO, MVT::i32, 1 }, 3217 { ISD::UADDO, MVT::i16, 1 }, 3218 { ISD::UADDO, MVT::i8, 1 }, 3219 { ISD::UMULO, MVT::i32, 2 }, // mul + seto 3220 { ISD::UMULO, MVT::i16, 2 }, 3221 { ISD::UMULO, MVT::i8, 2 }, 3222 }; 3223 3224 Type *RetTy = ICA.getReturnType(); 3225 Type *OpTy = RetTy; 3226 Intrinsic::ID IID = ICA.getID(); 3227 unsigned ISD = ISD::DELETED_NODE; 3228 switch (IID) { 3229 default: 3230 break; 3231 case Intrinsic::abs: 3232 ISD = ISD::ABS; 3233 break; 3234 case Intrinsic::bitreverse: 3235 ISD = ISD::BITREVERSE; 3236 break; 3237 case Intrinsic::bswap: 3238 ISD = ISD::BSWAP; 3239 break; 3240 case Intrinsic::ctlz: 3241 ISD = ISD::CTLZ; 3242 break; 3243 case Intrinsic::ctpop: 3244 ISD = ISD::CTPOP; 3245 break; 3246 case Intrinsic::cttz: 3247 ISD = ISD::CTTZ; 3248 break; 3249 case Intrinsic::maxnum: 3250 case Intrinsic::minnum: 3251 // FMINNUM has same costs so don't duplicate. 3252 ISD = ISD::FMAXNUM; 3253 break; 3254 case Intrinsic::sadd_sat: 3255 ISD = ISD::SADDSAT; 3256 break; 3257 case Intrinsic::smax: 3258 ISD = ISD::SMAX; 3259 break; 3260 case Intrinsic::smin: 3261 ISD = ISD::SMIN; 3262 break; 3263 case Intrinsic::ssub_sat: 3264 ISD = ISD::SSUBSAT; 3265 break; 3266 case Intrinsic::uadd_sat: 3267 ISD = ISD::UADDSAT; 3268 break; 3269 case Intrinsic::umax: 3270 ISD = ISD::UMAX; 3271 break; 3272 case Intrinsic::umin: 3273 ISD = ISD::UMIN; 3274 break; 3275 case Intrinsic::usub_sat: 3276 ISD = ISD::USUBSAT; 3277 break; 3278 case Intrinsic::sqrt: 3279 ISD = ISD::FSQRT; 3280 break; 3281 case Intrinsic::sadd_with_overflow: 3282 case Intrinsic::ssub_with_overflow: 3283 // SSUBO has same costs so don't duplicate. 3284 ISD = ISD::SADDO; 3285 OpTy = RetTy->getContainedType(0); 3286 break; 3287 case Intrinsic::uadd_with_overflow: 3288 case Intrinsic::usub_with_overflow: 3289 // USUBO has same costs so don't duplicate. 3290 ISD = ISD::UADDO; 3291 OpTy = RetTy->getContainedType(0); 3292 break; 3293 case Intrinsic::umul_with_overflow: 3294 case Intrinsic::smul_with_overflow: 3295 // SMULO has same costs so don't duplicate. 3296 ISD = ISD::UMULO; 3297 OpTy = RetTy->getContainedType(0); 3298 break; 3299 } 3300 3301 if (ISD != ISD::DELETED_NODE) { 3302 // Legalize the type. 3303 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 3304 MVT MTy = LT.second; 3305 3306 // Attempt to lookup cost. 3307 if (ISD == ISD::BITREVERSE && ST->hasGFNI() && ST->hasSSSE3() && 3308 MTy.isVector()) { 3309 // With PSHUFB the code is very similar for all types. If we have integer 3310 // byte operations, we just need a GF2P8AFFINEQB for vXi8. For other types 3311 // we also need a PSHUFB. 3312 unsigned Cost = MTy.getVectorElementType() == MVT::i8 ? 1 : 2; 3313 3314 // Without byte operations, we need twice as many GF2P8AFFINEQB and PSHUFB 3315 // instructions. We also need an extract and an insert. 3316 if (!(MTy.is128BitVector() || (ST->hasAVX2() && MTy.is256BitVector()) || 3317 (ST->hasBWI() && MTy.is512BitVector()))) 3318 Cost = Cost * 2 + 2; 3319 3320 return LT.first * Cost; 3321 } 3322 3323 auto adjustTableCost = [](const CostTblEntry &Entry, 3324 InstructionCost LegalizationCost, 3325 FastMathFlags FMF) { 3326 // If there are no NANs to deal with, then these are reduced to a 3327 // single MIN** or MAX** instruction instead of the MIN/CMP/SELECT that we 3328 // assume is used in the non-fast case. 3329 if (Entry.ISD == ISD::FMAXNUM || Entry.ISD == ISD::FMINNUM) { 3330 if (FMF.noNaNs()) 3331 return LegalizationCost * 1; 3332 } 3333 return LegalizationCost * (int)Entry.Cost; 3334 }; 3335 3336 if (ST->useGLMDivSqrtCosts()) 3337 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 3338 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3339 3340 if (ST->useSLMArithCosts()) 3341 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 3342 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3343 3344 if (ST->hasBITALG()) 3345 if (const auto *Entry = CostTableLookup(AVX512BITALGCostTbl, ISD, MTy)) 3346 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3347 3348 if (ST->hasVPOPCNTDQ()) 3349 if (const auto *Entry = CostTableLookup(AVX512VPOPCNTDQCostTbl, ISD, MTy)) 3350 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3351 3352 if (ST->hasCDI()) 3353 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 3354 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3355 3356 if (ST->hasBWI()) 3357 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3358 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3359 3360 if (ST->hasAVX512()) 3361 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3362 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3363 3364 if (ST->hasXOP()) 3365 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3366 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3367 3368 if (ST->hasAVX2()) 3369 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3370 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3371 3372 if (ST->hasAVX()) 3373 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3374 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3375 3376 if (ST->hasSSE42()) 3377 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3378 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3379 3380 if (ST->hasSSE41()) 3381 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3382 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3383 3384 if (ST->hasSSSE3()) 3385 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 3386 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3387 3388 if (ST->hasSSE2()) 3389 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3390 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3391 3392 if (ST->hasSSE1()) 3393 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3394 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3395 3396 if (ST->hasBMI()) { 3397 if (ST->is64Bit()) 3398 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 3399 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3400 3401 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 3402 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3403 } 3404 3405 if (ST->hasLZCNT()) { 3406 if (ST->is64Bit()) 3407 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 3408 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3409 3410 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 3411 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3412 } 3413 3414 if (ST->hasPOPCNT()) { 3415 if (ST->is64Bit()) 3416 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 3417 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3418 3419 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 3420 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3421 } 3422 3423 if (ISD == ISD::BSWAP && ST->hasMOVBE() && ST->hasFastMOVBE()) { 3424 if (const Instruction *II = ICA.getInst()) { 3425 if (II->hasOneUse() && isa<StoreInst>(II->user_back())) 3426 return TTI::TCC_Free; 3427 if (auto *LI = dyn_cast<LoadInst>(II->getOperand(0))) { 3428 if (LI->hasOneUse()) 3429 return TTI::TCC_Free; 3430 } 3431 } 3432 } 3433 3434 if (ST->is64Bit()) 3435 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3436 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3437 3438 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3439 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3440 } 3441 3442 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3443 } 3444 3445 InstructionCost 3446 X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 3447 TTI::TargetCostKind CostKind) { 3448 if (ICA.isTypeBasedOnly()) 3449 return getTypeBasedIntrinsicInstrCost(ICA, CostKind); 3450 3451 static const CostTblEntry AVX512BWCostTbl[] = { 3452 { ISD::ROTL, MVT::v32i16, 2 }, 3453 { ISD::ROTL, MVT::v16i16, 2 }, 3454 { ISD::ROTL, MVT::v8i16, 2 }, 3455 { ISD::ROTL, MVT::v64i8, 5 }, 3456 { ISD::ROTL, MVT::v32i8, 5 }, 3457 { ISD::ROTL, MVT::v16i8, 5 }, 3458 { ISD::ROTR, MVT::v32i16, 2 }, 3459 { ISD::ROTR, MVT::v16i16, 2 }, 3460 { ISD::ROTR, MVT::v8i16, 2 }, 3461 { ISD::ROTR, MVT::v64i8, 5 }, 3462 { ISD::ROTR, MVT::v32i8, 5 }, 3463 { ISD::ROTR, MVT::v16i8, 5 } 3464 }; 3465 static const CostTblEntry AVX512CostTbl[] = { 3466 { ISD::ROTL, MVT::v8i64, 1 }, 3467 { ISD::ROTL, MVT::v4i64, 1 }, 3468 { ISD::ROTL, MVT::v2i64, 1 }, 3469 { ISD::ROTL, MVT::v16i32, 1 }, 3470 { ISD::ROTL, MVT::v8i32, 1 }, 3471 { ISD::ROTL, MVT::v4i32, 1 }, 3472 { ISD::ROTR, MVT::v8i64, 1 }, 3473 { ISD::ROTR, MVT::v4i64, 1 }, 3474 { ISD::ROTR, MVT::v2i64, 1 }, 3475 { ISD::ROTR, MVT::v16i32, 1 }, 3476 { ISD::ROTR, MVT::v8i32, 1 }, 3477 { ISD::ROTR, MVT::v4i32, 1 } 3478 }; 3479 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 3480 static const CostTblEntry XOPCostTbl[] = { 3481 { ISD::ROTL, MVT::v4i64, 4 }, 3482 { ISD::ROTL, MVT::v8i32, 4 }, 3483 { ISD::ROTL, MVT::v16i16, 4 }, 3484 { ISD::ROTL, MVT::v32i8, 4 }, 3485 { ISD::ROTL, MVT::v2i64, 1 }, 3486 { ISD::ROTL, MVT::v4i32, 1 }, 3487 { ISD::ROTL, MVT::v8i16, 1 }, 3488 { ISD::ROTL, MVT::v16i8, 1 }, 3489 { ISD::ROTR, MVT::v4i64, 6 }, 3490 { ISD::ROTR, MVT::v8i32, 6 }, 3491 { ISD::ROTR, MVT::v16i16, 6 }, 3492 { ISD::ROTR, MVT::v32i8, 6 }, 3493 { ISD::ROTR, MVT::v2i64, 2 }, 3494 { ISD::ROTR, MVT::v4i32, 2 }, 3495 { ISD::ROTR, MVT::v8i16, 2 }, 3496 { ISD::ROTR, MVT::v16i8, 2 } 3497 }; 3498 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 3499 { ISD::ROTL, MVT::i64, 1 }, 3500 { ISD::ROTR, MVT::i64, 1 }, 3501 { ISD::FSHL, MVT::i64, 4 } 3502 }; 3503 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 3504 { ISD::ROTL, MVT::i32, 1 }, 3505 { ISD::ROTL, MVT::i16, 1 }, 3506 { ISD::ROTL, MVT::i8, 1 }, 3507 { ISD::ROTR, MVT::i32, 1 }, 3508 { ISD::ROTR, MVT::i16, 1 }, 3509 { ISD::ROTR, MVT::i8, 1 }, 3510 { ISD::FSHL, MVT::i32, 4 }, 3511 { ISD::FSHL, MVT::i16, 4 }, 3512 { ISD::FSHL, MVT::i8, 4 } 3513 }; 3514 3515 Intrinsic::ID IID = ICA.getID(); 3516 Type *RetTy = ICA.getReturnType(); 3517 const SmallVectorImpl<const Value *> &Args = ICA.getArgs(); 3518 unsigned ISD = ISD::DELETED_NODE; 3519 switch (IID) { 3520 default: 3521 break; 3522 case Intrinsic::fshl: 3523 ISD = ISD::FSHL; 3524 if (Args[0] == Args[1]) 3525 ISD = ISD::ROTL; 3526 break; 3527 case Intrinsic::fshr: 3528 // FSHR has same costs so don't duplicate. 3529 ISD = ISD::FSHL; 3530 if (Args[0] == Args[1]) 3531 ISD = ISD::ROTR; 3532 break; 3533 } 3534 3535 if (ISD != ISD::DELETED_NODE) { 3536 // Legalize the type. 3537 std::pair<InstructionCost, MVT> LT = 3538 TLI->getTypeLegalizationCost(DL, RetTy); 3539 MVT MTy = LT.second; 3540 3541 // Attempt to lookup cost. 3542 if (ST->hasBWI()) 3543 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3544 return LT.first * Entry->Cost; 3545 3546 if (ST->hasAVX512()) 3547 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3548 return LT.first * Entry->Cost; 3549 3550 if (ST->hasXOP()) 3551 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3552 return LT.first * Entry->Cost; 3553 3554 if (ST->is64Bit()) 3555 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3556 return LT.first * Entry->Cost; 3557 3558 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3559 return LT.first * Entry->Cost; 3560 } 3561 3562 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3563 } 3564 3565 InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, 3566 unsigned Index) { 3567 static const CostTblEntry SLMCostTbl[] = { 3568 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 3569 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 3570 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 3571 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 3572 }; 3573 3574 assert(Val->isVectorTy() && "This must be a vector type"); 3575 Type *ScalarType = Val->getScalarType(); 3576 int RegisterFileMoveCost = 0; 3577 3578 // Non-immediate extraction/insertion can be handled as a sequence of 3579 // aliased loads+stores via the stack. 3580 if (Index == -1U && (Opcode == Instruction::ExtractElement || 3581 Opcode == Instruction::InsertElement)) { 3582 // TODO: On some SSE41+ targets, we expand to cmp+splat+select patterns: 3583 // inselt N0, N1, N2 --> select (SplatN2 == {0,1,2...}) ? SplatN1 : N0. 3584 3585 // TODO: Move this to BasicTTIImpl.h? We'd need better gep + index handling. 3586 assert(isa<FixedVectorType>(Val) && "Fixed vector type expected"); 3587 Align VecAlign = DL.getPrefTypeAlign(Val); 3588 Align SclAlign = DL.getPrefTypeAlign(ScalarType); 3589 3590 // Extract - store vector to stack, load scalar. 3591 if (Opcode == Instruction::ExtractElement) { 3592 return getMemoryOpCost(Instruction::Store, Val, VecAlign, 0, 3593 TTI::TargetCostKind::TCK_RecipThroughput) + 3594 getMemoryOpCost(Instruction::Load, ScalarType, SclAlign, 0, 3595 TTI::TargetCostKind::TCK_RecipThroughput); 3596 } 3597 // Insert - store vector to stack, store scalar, load vector. 3598 if (Opcode == Instruction::InsertElement) { 3599 return getMemoryOpCost(Instruction::Store, Val, VecAlign, 0, 3600 TTI::TargetCostKind::TCK_RecipThroughput) + 3601 getMemoryOpCost(Instruction::Store, ScalarType, SclAlign, 0, 3602 TTI::TargetCostKind::TCK_RecipThroughput) + 3603 getMemoryOpCost(Instruction::Load, Val, VecAlign, 0, 3604 TTI::TargetCostKind::TCK_RecipThroughput); 3605 } 3606 } 3607 3608 if (Index != -1U && (Opcode == Instruction::ExtractElement || 3609 Opcode == Instruction::InsertElement)) { 3610 // Extraction of vXi1 elements are now efficiently handled by MOVMSK. 3611 if (Opcode == Instruction::ExtractElement && 3612 ScalarType->getScalarSizeInBits() == 1 && 3613 cast<FixedVectorType>(Val)->getNumElements() > 1) 3614 return 1; 3615 3616 // Legalize the type. 3617 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 3618 3619 // This type is legalized to a scalar type. 3620 if (!LT.second.isVector()) 3621 return 0; 3622 3623 // The type may be split. Normalize the index to the new type. 3624 unsigned SizeInBits = LT.second.getSizeInBits(); 3625 unsigned NumElts = LT.second.getVectorNumElements(); 3626 unsigned SubNumElts = NumElts; 3627 Index = Index % NumElts; 3628 3629 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 3630 // For inserts, we also need to insert the subvector back. 3631 if (SizeInBits > 128) { 3632 assert((SizeInBits % 128) == 0 && "Illegal vector"); 3633 unsigned NumSubVecs = SizeInBits / 128; 3634 SubNumElts = NumElts / NumSubVecs; 3635 if (SubNumElts <= Index) { 3636 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 3637 Index %= SubNumElts; 3638 } 3639 } 3640 3641 if (Index == 0) { 3642 // Floating point scalars are already located in index #0. 3643 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 3644 // true for all. 3645 if (ScalarType->isFloatingPointTy()) 3646 return RegisterFileMoveCost; 3647 3648 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 3649 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 3650 return 1 + RegisterFileMoveCost; 3651 } 3652 3653 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3654 assert(ISD && "Unexpected vector opcode"); 3655 MVT MScalarTy = LT.second.getScalarType(); 3656 if (ST->useSLMArithCosts()) 3657 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 3658 return Entry->Cost + RegisterFileMoveCost; 3659 3660 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 3661 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3662 (MScalarTy.isInteger() && ST->hasSSE41())) 3663 return 1 + RegisterFileMoveCost; 3664 3665 // Assume insertps is relatively cheap on all targets. 3666 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 3667 Opcode == Instruction::InsertElement) 3668 return 1 + RegisterFileMoveCost; 3669 3670 // For extractions we just need to shuffle the element to index 0, which 3671 // should be very cheap (assume cost = 1). For insertions we need to shuffle 3672 // the elements to its destination. In both cases we must handle the 3673 // subvector move(s). 3674 // If the vector type is already less than 128-bits then don't reduce it. 3675 // TODO: Under what circumstances should we shuffle using the full width? 3676 InstructionCost ShuffleCost = 1; 3677 if (Opcode == Instruction::InsertElement) { 3678 auto *SubTy = cast<VectorType>(Val); 3679 EVT VT = TLI->getValueType(DL, Val); 3680 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 3681 SubTy = FixedVectorType::get(ScalarType, SubNumElts); 3682 ShuffleCost = 3683 getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, None, 0, SubTy); 3684 } 3685 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 3686 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 3687 } 3688 3689 // Add to the base cost if we know that the extracted element of a vector is 3690 // destined to be moved to and used in the integer register file. 3691 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 3692 RegisterFileMoveCost += 1; 3693 3694 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 3695 } 3696 3697 InstructionCost X86TTIImpl::getScalarizationOverhead(VectorType *Ty, 3698 const APInt &DemandedElts, 3699 bool Insert, 3700 bool Extract) { 3701 InstructionCost Cost = 0; 3702 3703 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much 3704 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT. 3705 if (Insert) { 3706 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3707 MVT MScalarTy = LT.second.getScalarType(); 3708 unsigned SizeInBits = LT.second.getSizeInBits(); 3709 3710 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3711 (MScalarTy.isInteger() && ST->hasSSE41()) || 3712 (MScalarTy == MVT::f32 && ST->hasSSE41())) { 3713 // For types we can insert directly, insertion into 128-bit sub vectors is 3714 // cheap, followed by a cheap chain of concatenations. 3715 if (SizeInBits <= 128) { 3716 Cost += 3717 BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, false); 3718 } else { 3719 // In each 128-lane, if at least one index is demanded but not all 3720 // indices are demanded and this 128-lane is not the first 128-lane of 3721 // the legalized-vector, then this 128-lane needs a extracti128; If in 3722 // each 128-lane, there is at least one demanded index, this 128-lane 3723 // needs a inserti128. 3724 3725 // The following cases will help you build a better understanding: 3726 // Assume we insert several elements into a v8i32 vector in avx2, 3727 // Case#1: inserting into 1th index needs vpinsrd + inserti128. 3728 // Case#2: inserting into 5th index needs extracti128 + vpinsrd + 3729 // inserti128. 3730 // Case#3: inserting into 4,5,6,7 index needs 4*vpinsrd + inserti128. 3731 const int CostValue = *LT.first.getValue(); 3732 assert(CostValue >= 0 && "Negative cost!"); 3733 unsigned Num128Lanes = SizeInBits / 128 * CostValue; 3734 unsigned NumElts = LT.second.getVectorNumElements() * CostValue; 3735 APInt WidenedDemandedElts = DemandedElts.zextOrSelf(NumElts); 3736 unsigned Scale = NumElts / Num128Lanes; 3737 // We iterate each 128-lane, and check if we need a 3738 // extracti128/inserti128 for this 128-lane. 3739 for (unsigned I = 0; I < NumElts; I += Scale) { 3740 APInt Mask = WidenedDemandedElts.getBitsSet(NumElts, I, I + Scale); 3741 APInt MaskedDE = Mask & WidenedDemandedElts; 3742 unsigned Population = MaskedDE.countPopulation(); 3743 Cost += (Population > 0 && Population != Scale && 3744 I % LT.second.getVectorNumElements() != 0); 3745 Cost += Population > 0; 3746 } 3747 Cost += DemandedElts.countPopulation(); 3748 3749 // For vXf32 cases, insertion into the 0'th index in each v4f32 3750 // 128-bit vector is free. 3751 // NOTE: This assumes legalization widens vXf32 vectors. 3752 if (MScalarTy == MVT::f32) 3753 for (unsigned i = 0, e = cast<FixedVectorType>(Ty)->getNumElements(); 3754 i < e; i += 4) 3755 if (DemandedElts[i]) 3756 Cost--; 3757 } 3758 } else if (LT.second.isVector()) { 3759 // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded 3760 // integer element as a SCALAR_TO_VECTOR, then we build the vector as a 3761 // series of UNPCK followed by CONCAT_VECTORS - all of these can be 3762 // considered cheap. 3763 if (Ty->isIntOrIntVectorTy()) 3764 Cost += DemandedElts.countPopulation(); 3765 3766 // Get the smaller of the legalized or original pow2-extended number of 3767 // vector elements, which represents the number of unpacks we'll end up 3768 // performing. 3769 unsigned NumElts = LT.second.getVectorNumElements(); 3770 unsigned Pow2Elts = 3771 PowerOf2Ceil(cast<FixedVectorType>(Ty)->getNumElements()); 3772 Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first; 3773 } 3774 } 3775 3776 // TODO: Use default extraction for now, but we should investigate extending this 3777 // to handle repeated subvector extraction. 3778 if (Extract) 3779 Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, false, Extract); 3780 3781 return Cost; 3782 } 3783 3784 InstructionCost 3785 X86TTIImpl::getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, 3786 int VF, const APInt &DemandedDstElts, 3787 TTI::TargetCostKind CostKind) { 3788 const unsigned EltTyBits = DL.getTypeSizeInBits(EltTy); 3789 // We don't differentiate element types here, only element bit width. 3790 EltTy = IntegerType::getIntNTy(EltTy->getContext(), EltTyBits); 3791 3792 auto bailout = [&]() { 3793 return BaseT::getReplicationShuffleCost(EltTy, ReplicationFactor, VF, 3794 DemandedDstElts, CostKind); 3795 }; 3796 3797 // For now, only deal with AVX512 cases. 3798 if (!ST->hasAVX512()) 3799 return bailout(); 3800 3801 // Do we have a native shuffle for this element type, or should we promote? 3802 unsigned PromEltTyBits = EltTyBits; 3803 switch (EltTyBits) { 3804 case 32: 3805 case 64: 3806 break; // AVX512F. 3807 case 16: 3808 if (!ST->hasBWI()) 3809 PromEltTyBits = 32; // promote to i32, AVX512F. 3810 break; // AVX512BW 3811 case 8: 3812 if (!ST->hasVBMI()) 3813 PromEltTyBits = 32; // promote to i32, AVX512F. 3814 break; // AVX512VBMI 3815 case 1: 3816 // There is no support for shuffling i1 elements. We *must* promote. 3817 if (ST->hasBWI()) { 3818 if (ST->hasVBMI()) 3819 PromEltTyBits = 8; // promote to i8, AVX512VBMI. 3820 else 3821 PromEltTyBits = 16; // promote to i16, AVX512BW. 3822 break; 3823 } 3824 if (ST->hasDQI()) { 3825 PromEltTyBits = 32; // promote to i32, AVX512F. 3826 break; 3827 } 3828 return bailout(); 3829 default: 3830 return bailout(); 3831 } 3832 auto *PromEltTy = IntegerType::getIntNTy(EltTy->getContext(), PromEltTyBits); 3833 3834 auto *SrcVecTy = FixedVectorType::get(EltTy, VF); 3835 auto *PromSrcVecTy = FixedVectorType::get(PromEltTy, VF); 3836 3837 int NumDstElements = VF * ReplicationFactor; 3838 auto *PromDstVecTy = FixedVectorType::get(PromEltTy, NumDstElements); 3839 auto *DstVecTy = FixedVectorType::get(EltTy, NumDstElements); 3840 3841 // Legalize the types. 3842 MVT LegalSrcVecTy = TLI->getTypeLegalizationCost(DL, SrcVecTy).second; 3843 MVT LegalPromSrcVecTy = TLI->getTypeLegalizationCost(DL, PromSrcVecTy).second; 3844 MVT LegalPromDstVecTy = TLI->getTypeLegalizationCost(DL, PromDstVecTy).second; 3845 MVT LegalDstVecTy = TLI->getTypeLegalizationCost(DL, DstVecTy).second; 3846 // They should have legalized into vector types. 3847 if (!LegalSrcVecTy.isVector() || !LegalPromSrcVecTy.isVector() || 3848 !LegalPromDstVecTy.isVector() || !LegalDstVecTy.isVector()) 3849 return bailout(); 3850 3851 if (PromEltTyBits != EltTyBits) { 3852 // If we have to perform the shuffle with wider elt type than our data type, 3853 // then we will first need to anyext (we don't care about the new bits) 3854 // the source elements, and then truncate Dst elements. 3855 InstructionCost PromotionCost; 3856 PromotionCost += getCastInstrCost( 3857 Instruction::SExt, /*Dst=*/PromSrcVecTy, /*Src=*/SrcVecTy, 3858 TargetTransformInfo::CastContextHint::None, CostKind); 3859 PromotionCost += 3860 getCastInstrCost(Instruction::Trunc, /*Dst=*/DstVecTy, 3861 /*Src=*/PromDstVecTy, 3862 TargetTransformInfo::CastContextHint::None, CostKind); 3863 return PromotionCost + getReplicationShuffleCost(PromEltTy, 3864 ReplicationFactor, VF, 3865 DemandedDstElts, CostKind); 3866 } 3867 3868 assert(LegalSrcVecTy.getScalarSizeInBits() == EltTyBits && 3869 LegalSrcVecTy.getScalarType() == LegalDstVecTy.getScalarType() && 3870 "We expect that the legalization doesn't affect the element width, " 3871 "doesn't coalesce/split elements."); 3872 3873 unsigned NumEltsPerDstVec = LegalDstVecTy.getVectorNumElements(); 3874 unsigned NumDstVectors = 3875 divideCeil(DstVecTy->getNumElements(), NumEltsPerDstVec); 3876 3877 auto *SingleDstVecTy = FixedVectorType::get(EltTy, NumEltsPerDstVec); 3878 3879 // Not all the produced Dst elements may be demanded. In our case, 3880 // given that a single Dst vector is formed by a single shuffle, 3881 // if all elements that will form a single Dst vector aren't demanded, 3882 // then we won't need to do that shuffle, so adjust the cost accordingly. 3883 APInt DemandedDstVectors = APIntOps::ScaleBitMask( 3884 DemandedDstElts.zextOrSelf(NumDstVectors * NumEltsPerDstVec), 3885 NumDstVectors); 3886 unsigned NumDstVectorsDemanded = DemandedDstVectors.countPopulation(); 3887 3888 InstructionCost SingleShuffleCost = 3889 getShuffleCost(TTI::SK_PermuteSingleSrc, SingleDstVecTy, 3890 /*Mask=*/None, /*Index=*/0, /*SubTp=*/nullptr); 3891 return NumDstVectorsDemanded * SingleShuffleCost; 3892 } 3893 3894 InstructionCost X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 3895 MaybeAlign Alignment, 3896 unsigned AddressSpace, 3897 TTI::TargetCostKind CostKind, 3898 const Instruction *I) { 3899 // TODO: Handle other cost kinds. 3900 if (CostKind != TTI::TCK_RecipThroughput) { 3901 if (auto *SI = dyn_cast_or_null<StoreInst>(I)) { 3902 // Store instruction with index and scale costs 2 Uops. 3903 // Check the preceding GEP to identify non-const indices. 3904 if (auto *GEP = dyn_cast<GetElementPtrInst>(SI->getPointerOperand())) { 3905 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3906 return TTI::TCC_Basic * 2; 3907 } 3908 } 3909 return TTI::TCC_Basic; 3910 } 3911 3912 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 3913 "Invalid Opcode"); 3914 // Type legalization can't handle structs 3915 if (TLI->getValueType(DL, Src, true) == MVT::Other) 3916 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3917 CostKind); 3918 3919 // Legalize the type. 3920 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 3921 3922 auto *VTy = dyn_cast<FixedVectorType>(Src); 3923 3924 // Handle the simple case of non-vectors. 3925 // NOTE: this assumes that legalization never creates vector from scalars! 3926 if (!VTy || !LT.second.isVector()) 3927 // Each load/store unit costs 1. 3928 return LT.first * 1; 3929 3930 bool IsLoad = Opcode == Instruction::Load; 3931 3932 Type *EltTy = VTy->getElementType(); 3933 3934 const int EltTyBits = DL.getTypeSizeInBits(EltTy); 3935 3936 InstructionCost Cost = 0; 3937 3938 // Source of truth: how many elements were there in the original IR vector? 3939 const unsigned SrcNumElt = VTy->getNumElements(); 3940 3941 // How far have we gotten? 3942 int NumEltRemaining = SrcNumElt; 3943 // Note that we intentionally capture by-reference, NumEltRemaining changes. 3944 auto NumEltDone = [&]() { return SrcNumElt - NumEltRemaining; }; 3945 3946 const int MaxLegalOpSizeBytes = divideCeil(LT.second.getSizeInBits(), 8); 3947 3948 // Note that even if we can store 64 bits of an XMM, we still operate on XMM. 3949 const unsigned XMMBits = 128; 3950 if (XMMBits % EltTyBits != 0) 3951 // Vector size must be a multiple of the element size. I.e. no padding. 3952 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3953 CostKind); 3954 const int NumEltPerXMM = XMMBits / EltTyBits; 3955 3956 auto *XMMVecTy = FixedVectorType::get(EltTy, NumEltPerXMM); 3957 3958 for (int CurrOpSizeBytes = MaxLegalOpSizeBytes, SubVecEltsLeft = 0; 3959 NumEltRemaining > 0; CurrOpSizeBytes /= 2) { 3960 // How many elements would a single op deal with at once? 3961 if ((8 * CurrOpSizeBytes) % EltTyBits != 0) 3962 // Vector size must be a multiple of the element size. I.e. no padding. 3963 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3964 CostKind); 3965 int CurrNumEltPerOp = (8 * CurrOpSizeBytes) / EltTyBits; 3966 3967 assert(CurrOpSizeBytes > 0 && CurrNumEltPerOp > 0 && "How'd we get here?"); 3968 assert((((NumEltRemaining * EltTyBits) < (2 * 8 * CurrOpSizeBytes)) || 3969 (CurrOpSizeBytes == MaxLegalOpSizeBytes)) && 3970 "Unless we haven't halved the op size yet, " 3971 "we have less than two op's sized units of work left."); 3972 3973 auto *CurrVecTy = CurrNumEltPerOp > NumEltPerXMM 3974 ? FixedVectorType::get(EltTy, CurrNumEltPerOp) 3975 : XMMVecTy; 3976 3977 assert(CurrVecTy->getNumElements() % CurrNumEltPerOp == 0 && 3978 "After halving sizes, the vector elt count is no longer a multiple " 3979 "of number of elements per operation?"); 3980 auto *CoalescedVecTy = 3981 CurrNumEltPerOp == 1 3982 ? CurrVecTy 3983 : FixedVectorType::get( 3984 IntegerType::get(Src->getContext(), 3985 EltTyBits * CurrNumEltPerOp), 3986 CurrVecTy->getNumElements() / CurrNumEltPerOp); 3987 assert(DL.getTypeSizeInBits(CoalescedVecTy) == 3988 DL.getTypeSizeInBits(CurrVecTy) && 3989 "coalesciing elements doesn't change vector width."); 3990 3991 while (NumEltRemaining > 0) { 3992 assert(SubVecEltsLeft >= 0 && "Subreg element count overconsumtion?"); 3993 3994 // Can we use this vector size, as per the remaining element count? 3995 // Iff the vector is naturally aligned, we can do a wide load regardless. 3996 if (NumEltRemaining < CurrNumEltPerOp && 3997 (!IsLoad || Alignment.valueOrOne() < CurrOpSizeBytes) && 3998 CurrOpSizeBytes != 1) 3999 break; // Try smalled vector size. 4000 4001 bool Is0thSubVec = (NumEltDone() % LT.second.getVectorNumElements()) == 0; 4002 4003 // If we have fully processed the previous reg, we need to replenish it. 4004 if (SubVecEltsLeft == 0) { 4005 SubVecEltsLeft += CurrVecTy->getNumElements(); 4006 // And that's free only for the 0'th subvector of a legalized vector. 4007 if (!Is0thSubVec) 4008 Cost += getShuffleCost(IsLoad ? TTI::ShuffleKind::SK_InsertSubvector 4009 : TTI::ShuffleKind::SK_ExtractSubvector, 4010 VTy, None, NumEltDone(), CurrVecTy); 4011 } 4012 4013 // While we can directly load/store ZMM, YMM, and 64-bit halves of XMM, 4014 // for smaller widths (32/16/8) we have to insert/extract them separately. 4015 // Again, it's free for the 0'th subreg (if op is 32/64 bit wide, 4016 // but let's pretend that it is also true for 16/8 bit wide ops...) 4017 if (CurrOpSizeBytes <= 32 / 8 && !Is0thSubVec) { 4018 int NumEltDoneInCurrXMM = NumEltDone() % NumEltPerXMM; 4019 assert(NumEltDoneInCurrXMM % CurrNumEltPerOp == 0 && ""); 4020 int CoalescedVecEltIdx = NumEltDoneInCurrXMM / CurrNumEltPerOp; 4021 APInt DemandedElts = 4022 APInt::getBitsSet(CoalescedVecTy->getNumElements(), 4023 CoalescedVecEltIdx, CoalescedVecEltIdx + 1); 4024 assert(DemandedElts.countPopulation() == 1 && "Inserting single value"); 4025 Cost += getScalarizationOverhead(CoalescedVecTy, DemandedElts, IsLoad, 4026 !IsLoad); 4027 } 4028 4029 // This isn't exactly right. We're using slow unaligned 32-byte accesses 4030 // as a proxy for a double-pumped AVX memory interface such as on 4031 // Sandybridge. 4032 if (CurrOpSizeBytes == 32 && ST->isUnalignedMem32Slow()) 4033 Cost += 2; 4034 else 4035 Cost += 1; 4036 4037 SubVecEltsLeft -= CurrNumEltPerOp; 4038 NumEltRemaining -= CurrNumEltPerOp; 4039 Alignment = commonAlignment(Alignment.valueOrOne(), CurrOpSizeBytes); 4040 } 4041 } 4042 4043 assert(NumEltRemaining <= 0 && "Should have processed all the elements."); 4044 4045 return Cost; 4046 } 4047 4048 InstructionCost 4049 X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, Align Alignment, 4050 unsigned AddressSpace, 4051 TTI::TargetCostKind CostKind) { 4052 bool IsLoad = (Instruction::Load == Opcode); 4053 bool IsStore = (Instruction::Store == Opcode); 4054 4055 auto *SrcVTy = dyn_cast<FixedVectorType>(SrcTy); 4056 if (!SrcVTy) 4057 // To calculate scalar take the regular cost, without mask 4058 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace, CostKind); 4059 4060 unsigned NumElem = SrcVTy->getNumElements(); 4061 auto *MaskTy = 4062 FixedVectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 4063 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, Alignment)) || 4064 (IsStore && !isLegalMaskedStore(SrcVTy, Alignment))) { 4065 // Scalarization 4066 APInt DemandedElts = APInt::getAllOnes(NumElem); 4067 InstructionCost MaskSplitCost = 4068 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 4069 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 4070 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr, 4071 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4072 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 4073 InstructionCost MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 4074 InstructionCost ValueSplitCost = 4075 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore); 4076 InstructionCost MemopCost = 4077 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4078 Alignment, AddressSpace, CostKind); 4079 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 4080 } 4081 4082 // Legalize the type. 4083 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 4084 auto VT = TLI->getValueType(DL, SrcVTy); 4085 InstructionCost Cost = 0; 4086 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 4087 LT.second.getVectorNumElements() == NumElem) 4088 // Promotion requires extend/truncate for data and a shuffle for mask. 4089 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, None, 0, nullptr) + 4090 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, None, 0, nullptr); 4091 4092 else if (LT.first * LT.second.getVectorNumElements() > NumElem) { 4093 auto *NewMaskTy = FixedVectorType::get(MaskTy->getElementType(), 4094 LT.second.getVectorNumElements()); 4095 // Expanding requires fill mask with zeroes 4096 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, None, 0, MaskTy); 4097 } 4098 4099 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 4100 if (!ST->hasAVX512()) 4101 return Cost + LT.first * (IsLoad ? 2 : 8); 4102 4103 // AVX-512 masked load/store is cheapper 4104 return Cost + LT.first; 4105 } 4106 4107 InstructionCost X86TTIImpl::getAddressComputationCost(Type *Ty, 4108 ScalarEvolution *SE, 4109 const SCEV *Ptr) { 4110 // Address computations in vectorized code with non-consecutive addresses will 4111 // likely result in more instructions compared to scalar code where the 4112 // computation can more often be merged into the index mode. The resulting 4113 // extra micro-ops can significantly decrease throughput. 4114 const unsigned NumVectorInstToHideOverhead = 10; 4115 4116 // Cost modeling of Strided Access Computation is hidden by the indexing 4117 // modes of X86 regardless of the stride value. We dont believe that there 4118 // is a difference between constant strided access in gerenal and constant 4119 // strided value which is less than or equal to 64. 4120 // Even in the case of (loop invariant) stride whose value is not known at 4121 // compile time, the address computation will not incur more than one extra 4122 // ADD instruction. 4123 if (Ty->isVectorTy() && SE && !ST->hasAVX2()) { 4124 // TODO: AVX2 is the current cut-off because we don't have correct 4125 // interleaving costs for prior ISA's. 4126 if (!BaseT::isStridedAccess(Ptr)) 4127 return NumVectorInstToHideOverhead; 4128 if (!BaseT::getConstantStrideStep(SE, Ptr)) 4129 return 1; 4130 } 4131 4132 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 4133 } 4134 4135 InstructionCost 4136 X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 4137 Optional<FastMathFlags> FMF, 4138 TTI::TargetCostKind CostKind) { 4139 if (TTI::requiresOrderedReduction(FMF)) 4140 return BaseT::getArithmeticReductionCost(Opcode, ValTy, FMF, CostKind); 4141 4142 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 4143 // and make it as the cost. 4144 4145 static const CostTblEntry SLMCostTblNoPairWise[] = { 4146 { ISD::FADD, MVT::v2f64, 3 }, 4147 { ISD::ADD, MVT::v2i64, 5 }, 4148 }; 4149 4150 static const CostTblEntry SSE2CostTblNoPairWise[] = { 4151 { ISD::FADD, MVT::v2f64, 2 }, 4152 { ISD::FADD, MVT::v2f32, 2 }, 4153 { ISD::FADD, MVT::v4f32, 4 }, 4154 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 4155 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 4156 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 4157 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 4158 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 4159 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 4160 { ISD::ADD, MVT::v2i8, 2 }, 4161 { ISD::ADD, MVT::v4i8, 2 }, 4162 { ISD::ADD, MVT::v8i8, 2 }, 4163 { ISD::ADD, MVT::v16i8, 3 }, 4164 }; 4165 4166 static const CostTblEntry AVX1CostTblNoPairWise[] = { 4167 { ISD::FADD, MVT::v4f64, 3 }, 4168 { ISD::FADD, MVT::v4f32, 3 }, 4169 { ISD::FADD, MVT::v8f32, 4 }, 4170 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 4171 { ISD::ADD, MVT::v4i64, 3 }, 4172 { ISD::ADD, MVT::v8i32, 5 }, 4173 { ISD::ADD, MVT::v16i16, 5 }, 4174 { ISD::ADD, MVT::v32i8, 4 }, 4175 }; 4176 4177 int ISD = TLI->InstructionOpcodeToISD(Opcode); 4178 assert(ISD && "Invalid opcode"); 4179 4180 // Before legalizing the type, give a chance to look up illegal narrow types 4181 // in the table. 4182 // FIXME: Is there a better way to do this? 4183 EVT VT = TLI->getValueType(DL, ValTy); 4184 if (VT.isSimple()) { 4185 MVT MTy = VT.getSimpleVT(); 4186 if (ST->useSLMArithCosts()) 4187 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 4188 return Entry->Cost; 4189 4190 if (ST->hasAVX()) 4191 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4192 return Entry->Cost; 4193 4194 if (ST->hasSSE2()) 4195 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4196 return Entry->Cost; 4197 } 4198 4199 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 4200 4201 MVT MTy = LT.second; 4202 4203 auto *ValVTy = cast<FixedVectorType>(ValTy); 4204 4205 // Special case: vXi8 mul reductions are performed as vXi16. 4206 if (ISD == ISD::MUL && MTy.getScalarType() == MVT::i8) { 4207 auto *WideSclTy = IntegerType::get(ValVTy->getContext(), 16); 4208 auto *WideVecTy = FixedVectorType::get(WideSclTy, ValVTy->getNumElements()); 4209 return getCastInstrCost(Instruction::ZExt, WideVecTy, ValTy, 4210 TargetTransformInfo::CastContextHint::None, 4211 CostKind) + 4212 getArithmeticReductionCost(Opcode, WideVecTy, FMF, CostKind); 4213 } 4214 4215 InstructionCost ArithmeticCost = 0; 4216 if (LT.first != 1 && MTy.isVector() && 4217 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4218 // Type needs to be split. We need LT.first - 1 arithmetic ops. 4219 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 4220 MTy.getVectorNumElements()); 4221 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 4222 ArithmeticCost *= LT.first - 1; 4223 } 4224 4225 if (ST->useSLMArithCosts()) 4226 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 4227 return ArithmeticCost + Entry->Cost; 4228 4229 if (ST->hasAVX()) 4230 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4231 return ArithmeticCost + Entry->Cost; 4232 4233 if (ST->hasSSE2()) 4234 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4235 return ArithmeticCost + Entry->Cost; 4236 4237 // FIXME: These assume a naive kshift+binop lowering, which is probably 4238 // conservative in most cases. 4239 static const CostTblEntry AVX512BoolReduction[] = { 4240 { ISD::AND, MVT::v2i1, 3 }, 4241 { ISD::AND, MVT::v4i1, 5 }, 4242 { ISD::AND, MVT::v8i1, 7 }, 4243 { ISD::AND, MVT::v16i1, 9 }, 4244 { ISD::AND, MVT::v32i1, 11 }, 4245 { ISD::AND, MVT::v64i1, 13 }, 4246 { ISD::OR, MVT::v2i1, 3 }, 4247 { ISD::OR, MVT::v4i1, 5 }, 4248 { ISD::OR, MVT::v8i1, 7 }, 4249 { ISD::OR, MVT::v16i1, 9 }, 4250 { ISD::OR, MVT::v32i1, 11 }, 4251 { ISD::OR, MVT::v64i1, 13 }, 4252 }; 4253 4254 static const CostTblEntry AVX2BoolReduction[] = { 4255 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 4256 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 4257 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 4258 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 4259 }; 4260 4261 static const CostTblEntry AVX1BoolReduction[] = { 4262 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 4263 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 4264 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 4265 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 4266 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 4267 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 4268 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 4269 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 4270 }; 4271 4272 static const CostTblEntry SSE2BoolReduction[] = { 4273 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 4274 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 4275 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 4276 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 4277 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 4278 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 4279 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 4280 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 4281 }; 4282 4283 // Handle bool allof/anyof patterns. 4284 if (ValVTy->getElementType()->isIntegerTy(1)) { 4285 InstructionCost ArithmeticCost = 0; 4286 if (LT.first != 1 && MTy.isVector() && 4287 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4288 // Type needs to be split. We need LT.first - 1 arithmetic ops. 4289 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 4290 MTy.getVectorNumElements()); 4291 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 4292 ArithmeticCost *= LT.first - 1; 4293 } 4294 4295 if (ST->hasAVX512()) 4296 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 4297 return ArithmeticCost + Entry->Cost; 4298 if (ST->hasAVX2()) 4299 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 4300 return ArithmeticCost + Entry->Cost; 4301 if (ST->hasAVX()) 4302 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 4303 return ArithmeticCost + Entry->Cost; 4304 if (ST->hasSSE2()) 4305 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 4306 return ArithmeticCost + Entry->Cost; 4307 4308 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, FMF, CostKind); 4309 } 4310 4311 unsigned NumVecElts = ValVTy->getNumElements(); 4312 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 4313 4314 // Special case power of 2 reductions where the scalar type isn't changed 4315 // by type legalization. 4316 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 4317 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, FMF, CostKind); 4318 4319 InstructionCost ReductionCost = 0; 4320 4321 auto *Ty = ValVTy; 4322 if (LT.first != 1 && MTy.isVector() && 4323 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4324 // Type needs to be split. We need LT.first - 1 arithmetic ops. 4325 Ty = FixedVectorType::get(ValVTy->getElementType(), 4326 MTy.getVectorNumElements()); 4327 ReductionCost = getArithmeticInstrCost(Opcode, Ty, CostKind); 4328 ReductionCost *= LT.first - 1; 4329 NumVecElts = MTy.getVectorNumElements(); 4330 } 4331 4332 // Now handle reduction with the legal type, taking into account size changes 4333 // at each level. 4334 while (NumVecElts > 1) { 4335 // Determine the size of the remaining vector we need to reduce. 4336 unsigned Size = NumVecElts * ScalarSize; 4337 NumVecElts /= 2; 4338 // If we're reducing from 256/512 bits, use an extract_subvector. 4339 if (Size > 128) { 4340 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 4341 ReductionCost += 4342 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 4343 Ty = SubTy; 4344 } else if (Size == 128) { 4345 // Reducing from 128 bits is a permute of v2f64/v2i64. 4346 FixedVectorType *ShufTy; 4347 if (ValVTy->isFloatingPointTy()) 4348 ShufTy = 4349 FixedVectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 4350 else 4351 ShufTy = 4352 FixedVectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 4353 ReductionCost += 4354 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4355 } else if (Size == 64) { 4356 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 4357 FixedVectorType *ShufTy; 4358 if (ValVTy->isFloatingPointTy()) 4359 ShufTy = 4360 FixedVectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 4361 else 4362 ShufTy = 4363 FixedVectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 4364 ReductionCost += 4365 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4366 } else { 4367 // Reducing from smaller size is a shift by immediate. 4368 auto *ShiftTy = FixedVectorType::get( 4369 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 4370 ReductionCost += getArithmeticInstrCost( 4371 Instruction::LShr, ShiftTy, CostKind, 4372 TargetTransformInfo::OK_AnyValue, 4373 TargetTransformInfo::OK_UniformConstantValue, 4374 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 4375 } 4376 4377 // Add the arithmetic op for this level. 4378 ReductionCost += getArithmeticInstrCost(Opcode, Ty, CostKind); 4379 } 4380 4381 // Add the final extract element to the cost. 4382 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 4383 } 4384 4385 InstructionCost X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, 4386 bool IsUnsigned) { 4387 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 4388 4389 MVT MTy = LT.second; 4390 4391 int ISD; 4392 if (Ty->isIntOrIntVectorTy()) { 4393 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 4394 } else { 4395 assert(Ty->isFPOrFPVectorTy() && 4396 "Expected float point or integer vector type."); 4397 ISD = ISD::FMINNUM; 4398 } 4399 4400 static const CostTblEntry SSE1CostTbl[] = { 4401 {ISD::FMINNUM, MVT::v4f32, 1}, 4402 }; 4403 4404 static const CostTblEntry SSE2CostTbl[] = { 4405 {ISD::FMINNUM, MVT::v2f64, 1}, 4406 {ISD::SMIN, MVT::v8i16, 1}, 4407 {ISD::UMIN, MVT::v16i8, 1}, 4408 }; 4409 4410 static const CostTblEntry SSE41CostTbl[] = { 4411 {ISD::SMIN, MVT::v4i32, 1}, 4412 {ISD::UMIN, MVT::v4i32, 1}, 4413 {ISD::UMIN, MVT::v8i16, 1}, 4414 {ISD::SMIN, MVT::v16i8, 1}, 4415 }; 4416 4417 static const CostTblEntry SSE42CostTbl[] = { 4418 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 4419 }; 4420 4421 static const CostTblEntry AVX1CostTbl[] = { 4422 {ISD::FMINNUM, MVT::v8f32, 1}, 4423 {ISD::FMINNUM, MVT::v4f64, 1}, 4424 {ISD::SMIN, MVT::v8i32, 3}, 4425 {ISD::UMIN, MVT::v8i32, 3}, 4426 {ISD::SMIN, MVT::v16i16, 3}, 4427 {ISD::UMIN, MVT::v16i16, 3}, 4428 {ISD::SMIN, MVT::v32i8, 3}, 4429 {ISD::UMIN, MVT::v32i8, 3}, 4430 }; 4431 4432 static const CostTblEntry AVX2CostTbl[] = { 4433 {ISD::SMIN, MVT::v8i32, 1}, 4434 {ISD::UMIN, MVT::v8i32, 1}, 4435 {ISD::SMIN, MVT::v16i16, 1}, 4436 {ISD::UMIN, MVT::v16i16, 1}, 4437 {ISD::SMIN, MVT::v32i8, 1}, 4438 {ISD::UMIN, MVT::v32i8, 1}, 4439 }; 4440 4441 static const CostTblEntry AVX512CostTbl[] = { 4442 {ISD::FMINNUM, MVT::v16f32, 1}, 4443 {ISD::FMINNUM, MVT::v8f64, 1}, 4444 {ISD::SMIN, MVT::v2i64, 1}, 4445 {ISD::UMIN, MVT::v2i64, 1}, 4446 {ISD::SMIN, MVT::v4i64, 1}, 4447 {ISD::UMIN, MVT::v4i64, 1}, 4448 {ISD::SMIN, MVT::v8i64, 1}, 4449 {ISD::UMIN, MVT::v8i64, 1}, 4450 {ISD::SMIN, MVT::v16i32, 1}, 4451 {ISD::UMIN, MVT::v16i32, 1}, 4452 }; 4453 4454 static const CostTblEntry AVX512BWCostTbl[] = { 4455 {ISD::SMIN, MVT::v32i16, 1}, 4456 {ISD::UMIN, MVT::v32i16, 1}, 4457 {ISD::SMIN, MVT::v64i8, 1}, 4458 {ISD::UMIN, MVT::v64i8, 1}, 4459 }; 4460 4461 // If we have a native MIN/MAX instruction for this type, use it. 4462 if (ST->hasBWI()) 4463 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 4464 return LT.first * Entry->Cost; 4465 4466 if (ST->hasAVX512()) 4467 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 4468 return LT.first * Entry->Cost; 4469 4470 if (ST->hasAVX2()) 4471 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 4472 return LT.first * Entry->Cost; 4473 4474 if (ST->hasAVX()) 4475 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 4476 return LT.first * Entry->Cost; 4477 4478 if (ST->hasSSE42()) 4479 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 4480 return LT.first * Entry->Cost; 4481 4482 if (ST->hasSSE41()) 4483 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 4484 return LT.first * Entry->Cost; 4485 4486 if (ST->hasSSE2()) 4487 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 4488 return LT.first * Entry->Cost; 4489 4490 if (ST->hasSSE1()) 4491 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 4492 return LT.first * Entry->Cost; 4493 4494 unsigned CmpOpcode; 4495 if (Ty->isFPOrFPVectorTy()) { 4496 CmpOpcode = Instruction::FCmp; 4497 } else { 4498 assert(Ty->isIntOrIntVectorTy() && 4499 "expecting floating point or integer type for min/max reduction"); 4500 CmpOpcode = Instruction::ICmp; 4501 } 4502 4503 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4504 // Otherwise fall back to cmp+select. 4505 InstructionCost Result = 4506 getCmpSelInstrCost(CmpOpcode, Ty, CondTy, CmpInst::BAD_ICMP_PREDICATE, 4507 CostKind) + 4508 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, 4509 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4510 return Result; 4511 } 4512 4513 InstructionCost 4514 X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 4515 bool IsUnsigned, 4516 TTI::TargetCostKind CostKind) { 4517 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 4518 4519 MVT MTy = LT.second; 4520 4521 int ISD; 4522 if (ValTy->isIntOrIntVectorTy()) { 4523 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 4524 } else { 4525 assert(ValTy->isFPOrFPVectorTy() && 4526 "Expected float point or integer vector type."); 4527 ISD = ISD::FMINNUM; 4528 } 4529 4530 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 4531 // and make it as the cost. 4532 4533 static const CostTblEntry SSE2CostTblNoPairWise[] = { 4534 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 4535 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 4536 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 4537 }; 4538 4539 static const CostTblEntry SSE41CostTblNoPairWise[] = { 4540 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 4541 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 4542 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 4543 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 4544 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 4545 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 4546 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 4547 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 4548 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 4549 {ISD::SMIN, MVT::v16i8, 6}, 4550 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 4551 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 4552 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 4553 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 4554 }; 4555 4556 static const CostTblEntry AVX1CostTblNoPairWise[] = { 4557 {ISD::SMIN, MVT::v16i16, 6}, 4558 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 4559 {ISD::SMIN, MVT::v32i8, 8}, 4560 {ISD::UMIN, MVT::v32i8, 8}, 4561 }; 4562 4563 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 4564 {ISD::SMIN, MVT::v32i16, 8}, 4565 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 4566 {ISD::SMIN, MVT::v64i8, 10}, 4567 {ISD::UMIN, MVT::v64i8, 10}, 4568 }; 4569 4570 // Before legalizing the type, give a chance to look up illegal narrow types 4571 // in the table. 4572 // FIXME: Is there a better way to do this? 4573 EVT VT = TLI->getValueType(DL, ValTy); 4574 if (VT.isSimple()) { 4575 MVT MTy = VT.getSimpleVT(); 4576 if (ST->hasBWI()) 4577 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4578 return Entry->Cost; 4579 4580 if (ST->hasAVX()) 4581 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4582 return Entry->Cost; 4583 4584 if (ST->hasSSE41()) 4585 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4586 return Entry->Cost; 4587 4588 if (ST->hasSSE2()) 4589 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4590 return Entry->Cost; 4591 } 4592 4593 auto *ValVTy = cast<FixedVectorType>(ValTy); 4594 unsigned NumVecElts = ValVTy->getNumElements(); 4595 4596 auto *Ty = ValVTy; 4597 InstructionCost MinMaxCost = 0; 4598 if (LT.first != 1 && MTy.isVector() && 4599 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4600 // Type needs to be split. We need LT.first - 1 operations ops. 4601 Ty = FixedVectorType::get(ValVTy->getElementType(), 4602 MTy.getVectorNumElements()); 4603 auto *SubCondTy = FixedVectorType::get(CondTy->getElementType(), 4604 MTy.getVectorNumElements()); 4605 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4606 MinMaxCost *= LT.first - 1; 4607 NumVecElts = MTy.getVectorNumElements(); 4608 } 4609 4610 if (ST->hasBWI()) 4611 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4612 return MinMaxCost + Entry->Cost; 4613 4614 if (ST->hasAVX()) 4615 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4616 return MinMaxCost + Entry->Cost; 4617 4618 if (ST->hasSSE41()) 4619 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4620 return MinMaxCost + Entry->Cost; 4621 4622 if (ST->hasSSE2()) 4623 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4624 return MinMaxCost + Entry->Cost; 4625 4626 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 4627 4628 // Special case power of 2 reductions where the scalar type isn't changed 4629 // by type legalization. 4630 if (!isPowerOf2_32(ValVTy->getNumElements()) || 4631 ScalarSize != MTy.getScalarSizeInBits()) 4632 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsUnsigned, CostKind); 4633 4634 // Now handle reduction with the legal type, taking into account size changes 4635 // at each level. 4636 while (NumVecElts > 1) { 4637 // Determine the size of the remaining vector we need to reduce. 4638 unsigned Size = NumVecElts * ScalarSize; 4639 NumVecElts /= 2; 4640 // If we're reducing from 256/512 bits, use an extract_subvector. 4641 if (Size > 128) { 4642 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 4643 MinMaxCost += 4644 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 4645 Ty = SubTy; 4646 } else if (Size == 128) { 4647 // Reducing from 128 bits is a permute of v2f64/v2i64. 4648 VectorType *ShufTy; 4649 if (ValTy->isFloatingPointTy()) 4650 ShufTy = 4651 FixedVectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 4652 else 4653 ShufTy = FixedVectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 4654 MinMaxCost += 4655 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4656 } else if (Size == 64) { 4657 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 4658 FixedVectorType *ShufTy; 4659 if (ValTy->isFloatingPointTy()) 4660 ShufTy = FixedVectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 4661 else 4662 ShufTy = FixedVectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 4663 MinMaxCost += 4664 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4665 } else { 4666 // Reducing from smaller size is a shift by immediate. 4667 auto *ShiftTy = FixedVectorType::get( 4668 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 4669 MinMaxCost += getArithmeticInstrCost( 4670 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, 4671 TargetTransformInfo::OK_AnyValue, 4672 TargetTransformInfo::OK_UniformConstantValue, 4673 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 4674 } 4675 4676 // Add the arithmetic op for this level. 4677 auto *SubCondTy = 4678 FixedVectorType::get(CondTy->getElementType(), Ty->getNumElements()); 4679 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4680 } 4681 4682 // Add the final extract element to the cost. 4683 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 4684 } 4685 4686 /// Calculate the cost of materializing a 64-bit value. This helper 4687 /// method might only calculate a fraction of a larger immediate. Therefore it 4688 /// is valid to return a cost of ZERO. 4689 InstructionCost X86TTIImpl::getIntImmCost(int64_t Val) { 4690 if (Val == 0) 4691 return TTI::TCC_Free; 4692 4693 if (isInt<32>(Val)) 4694 return TTI::TCC_Basic; 4695 4696 return 2 * TTI::TCC_Basic; 4697 } 4698 4699 InstructionCost X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 4700 TTI::TargetCostKind CostKind) { 4701 assert(Ty->isIntegerTy()); 4702 4703 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4704 if (BitSize == 0) 4705 return ~0U; 4706 4707 // Never hoist constants larger than 128bit, because this might lead to 4708 // incorrect code generation or assertions in codegen. 4709 // Fixme: Create a cost model for types larger than i128 once the codegen 4710 // issues have been fixed. 4711 if (BitSize > 128) 4712 return TTI::TCC_Free; 4713 4714 if (Imm == 0) 4715 return TTI::TCC_Free; 4716 4717 // Sign-extend all constants to a multiple of 64-bit. 4718 APInt ImmVal = Imm; 4719 if (BitSize % 64 != 0) 4720 ImmVal = Imm.sext(alignTo(BitSize, 64)); 4721 4722 // Split the constant into 64-bit chunks and calculate the cost for each 4723 // chunk. 4724 InstructionCost Cost = 0; 4725 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 4726 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 4727 int64_t Val = Tmp.getSExtValue(); 4728 Cost += getIntImmCost(Val); 4729 } 4730 // We need at least one instruction to materialize the constant. 4731 return std::max<InstructionCost>(1, Cost); 4732 } 4733 4734 InstructionCost X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, 4735 const APInt &Imm, Type *Ty, 4736 TTI::TargetCostKind CostKind, 4737 Instruction *Inst) { 4738 assert(Ty->isIntegerTy()); 4739 4740 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4741 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4742 // here, so that constant hoisting will ignore this constant. 4743 if (BitSize == 0) 4744 return TTI::TCC_Free; 4745 4746 unsigned ImmIdx = ~0U; 4747 switch (Opcode) { 4748 default: 4749 return TTI::TCC_Free; 4750 case Instruction::GetElementPtr: 4751 // Always hoist the base address of a GetElementPtr. This prevents the 4752 // creation of new constants for every base constant that gets constant 4753 // folded with the offset. 4754 if (Idx == 0) 4755 return 2 * TTI::TCC_Basic; 4756 return TTI::TCC_Free; 4757 case Instruction::Store: 4758 ImmIdx = 0; 4759 break; 4760 case Instruction::ICmp: 4761 // This is an imperfect hack to prevent constant hoisting of 4762 // compares that might be trying to check if a 64-bit value fits in 4763 // 32-bits. The backend can optimize these cases using a right shift by 32. 4764 // Ideally we would check the compare predicate here. There also other 4765 // similar immediates the backend can use shifts for. 4766 if (Idx == 1 && Imm.getBitWidth() == 64) { 4767 uint64_t ImmVal = Imm.getZExtValue(); 4768 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 4769 return TTI::TCC_Free; 4770 } 4771 ImmIdx = 1; 4772 break; 4773 case Instruction::And: 4774 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 4775 // by using a 32-bit operation with implicit zero extension. Detect such 4776 // immediates here as the normal path expects bit 31 to be sign extended. 4777 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 4778 return TTI::TCC_Free; 4779 ImmIdx = 1; 4780 break; 4781 case Instruction::Add: 4782 case Instruction::Sub: 4783 // For add/sub, we can use the opposite instruction for INT32_MIN. 4784 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 4785 return TTI::TCC_Free; 4786 ImmIdx = 1; 4787 break; 4788 case Instruction::UDiv: 4789 case Instruction::SDiv: 4790 case Instruction::URem: 4791 case Instruction::SRem: 4792 // Division by constant is typically expanded later into a different 4793 // instruction sequence. This completely changes the constants. 4794 // Report them as "free" to stop ConstantHoist from marking them as opaque. 4795 return TTI::TCC_Free; 4796 case Instruction::Mul: 4797 case Instruction::Or: 4798 case Instruction::Xor: 4799 ImmIdx = 1; 4800 break; 4801 // Always return TCC_Free for the shift value of a shift instruction. 4802 case Instruction::Shl: 4803 case Instruction::LShr: 4804 case Instruction::AShr: 4805 if (Idx == 1) 4806 return TTI::TCC_Free; 4807 break; 4808 case Instruction::Trunc: 4809 case Instruction::ZExt: 4810 case Instruction::SExt: 4811 case Instruction::IntToPtr: 4812 case Instruction::PtrToInt: 4813 case Instruction::BitCast: 4814 case Instruction::PHI: 4815 case Instruction::Call: 4816 case Instruction::Select: 4817 case Instruction::Ret: 4818 case Instruction::Load: 4819 break; 4820 } 4821 4822 if (Idx == ImmIdx) { 4823 int NumConstants = divideCeil(BitSize, 64); 4824 InstructionCost Cost = X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4825 return (Cost <= NumConstants * TTI::TCC_Basic) 4826 ? static_cast<int>(TTI::TCC_Free) 4827 : Cost; 4828 } 4829 4830 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4831 } 4832 4833 InstructionCost X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 4834 const APInt &Imm, Type *Ty, 4835 TTI::TargetCostKind CostKind) { 4836 assert(Ty->isIntegerTy()); 4837 4838 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4839 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4840 // here, so that constant hoisting will ignore this constant. 4841 if (BitSize == 0) 4842 return TTI::TCC_Free; 4843 4844 switch (IID) { 4845 default: 4846 return TTI::TCC_Free; 4847 case Intrinsic::sadd_with_overflow: 4848 case Intrinsic::uadd_with_overflow: 4849 case Intrinsic::ssub_with_overflow: 4850 case Intrinsic::usub_with_overflow: 4851 case Intrinsic::smul_with_overflow: 4852 case Intrinsic::umul_with_overflow: 4853 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 4854 return TTI::TCC_Free; 4855 break; 4856 case Intrinsic::experimental_stackmap: 4857 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4858 return TTI::TCC_Free; 4859 break; 4860 case Intrinsic::experimental_patchpoint_void: 4861 case Intrinsic::experimental_patchpoint_i64: 4862 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4863 return TTI::TCC_Free; 4864 break; 4865 } 4866 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4867 } 4868 4869 InstructionCost X86TTIImpl::getCFInstrCost(unsigned Opcode, 4870 TTI::TargetCostKind CostKind, 4871 const Instruction *I) { 4872 if (CostKind != TTI::TCK_RecipThroughput) 4873 return Opcode == Instruction::PHI ? 0 : 1; 4874 // Branches are assumed to be predicted. 4875 return 0; 4876 } 4877 4878 int X86TTIImpl::getGatherOverhead() const { 4879 // Some CPUs have more overhead for gather. The specified overhead is relative 4880 // to the Load operation. "2" is the number provided by Intel architects. This 4881 // parameter is used for cost estimation of Gather Op and comparison with 4882 // other alternatives. 4883 // TODO: Remove the explicit hasAVX512()?, That would mean we would only 4884 // enable gather with a -march. 4885 if (ST->hasAVX512() || (ST->hasAVX2() && ST->hasFastGather())) 4886 return 2; 4887 4888 return 1024; 4889 } 4890 4891 int X86TTIImpl::getScatterOverhead() const { 4892 if (ST->hasAVX512()) 4893 return 2; 4894 4895 return 1024; 4896 } 4897 4898 // Return an average cost of Gather / Scatter instruction, maybe improved later. 4899 // FIXME: Add TargetCostKind support. 4900 InstructionCost X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, 4901 const Value *Ptr, Align Alignment, 4902 unsigned AddressSpace) { 4903 4904 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 4905 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4906 4907 // Try to reduce index size from 64 bit (default for GEP) 4908 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 4909 // operation will use 16 x 64 indices which do not fit in a zmm and needs 4910 // to split. Also check that the base pointer is the same for all lanes, 4911 // and that there's at most one variable index. 4912 auto getIndexSizeInBits = [](const Value *Ptr, const DataLayout &DL) { 4913 unsigned IndexSize = DL.getPointerSizeInBits(); 4914 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 4915 if (IndexSize < 64 || !GEP) 4916 return IndexSize; 4917 4918 unsigned NumOfVarIndices = 0; 4919 const Value *Ptrs = GEP->getPointerOperand(); 4920 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 4921 return IndexSize; 4922 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 4923 if (isa<Constant>(GEP->getOperand(i))) 4924 continue; 4925 Type *IndxTy = GEP->getOperand(i)->getType(); 4926 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 4927 IndxTy = IndexVTy->getElementType(); 4928 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 4929 !isa<SExtInst>(GEP->getOperand(i))) || 4930 ++NumOfVarIndices > 1) 4931 return IndexSize; // 64 4932 } 4933 return (unsigned)32; 4934 }; 4935 4936 // Trying to reduce IndexSize to 32 bits for vector 16. 4937 // By default the IndexSize is equal to pointer size. 4938 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 4939 ? getIndexSizeInBits(Ptr, DL) 4940 : DL.getPointerSizeInBits(); 4941 4942 auto *IndexVTy = FixedVectorType::get( 4943 IntegerType::get(SrcVTy->getContext(), IndexSize), VF); 4944 std::pair<InstructionCost, MVT> IdxsLT = 4945 TLI->getTypeLegalizationCost(DL, IndexVTy); 4946 std::pair<InstructionCost, MVT> SrcLT = 4947 TLI->getTypeLegalizationCost(DL, SrcVTy); 4948 InstructionCost::CostType SplitFactor = 4949 *std::max(IdxsLT.first, SrcLT.first).getValue(); 4950 if (SplitFactor > 1) { 4951 // Handle splitting of vector of pointers 4952 auto *SplitSrcTy = 4953 FixedVectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 4954 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 4955 AddressSpace); 4956 } 4957 4958 // The gather / scatter cost is given by Intel architects. It is a rough 4959 // number since we are looking at one instruction in a time. 4960 const int GSOverhead = (Opcode == Instruction::Load) 4961 ? getGatherOverhead() 4962 : getScatterOverhead(); 4963 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4964 MaybeAlign(Alignment), AddressSpace, 4965 TTI::TCK_RecipThroughput); 4966 } 4967 4968 /// Return the cost of full scalarization of gather / scatter operation. 4969 /// 4970 /// Opcode - Load or Store instruction. 4971 /// SrcVTy - The type of the data vector that should be gathered or scattered. 4972 /// VariableMask - The mask is non-constant at compile time. 4973 /// Alignment - Alignment for one element. 4974 /// AddressSpace - pointer[s] address space. 4975 /// 4976 /// FIXME: Add TargetCostKind support. 4977 InstructionCost X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 4978 bool VariableMask, Align Alignment, 4979 unsigned AddressSpace) { 4980 Type *ScalarTy = SrcVTy->getScalarType(); 4981 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4982 APInt DemandedElts = APInt::getAllOnes(VF); 4983 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4984 4985 InstructionCost MaskUnpackCost = 0; 4986 if (VariableMask) { 4987 auto *MaskTy = 4988 FixedVectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 4989 MaskUnpackCost = getScalarizationOverhead( 4990 MaskTy, DemandedElts, /*Insert=*/false, /*Extract=*/true); 4991 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 4992 Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), nullptr, 4993 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4994 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 4995 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 4996 } 4997 4998 InstructionCost AddressUnpackCost = getScalarizationOverhead( 4999 FixedVectorType::get(ScalarTy->getPointerTo(), VF), DemandedElts, 5000 /*Insert=*/false, /*Extract=*/true); 5001 5002 // The cost of the scalar loads/stores. 5003 InstructionCost MemoryOpCost = 5004 VF * getMemoryOpCost(Opcode, ScalarTy, MaybeAlign(Alignment), 5005 AddressSpace, CostKind); 5006 5007 // The cost of forming the vector from loaded scalars/ 5008 // scalarizing the vector to perform scalar stores. 5009 InstructionCost InsertExtractCost = 5010 getScalarizationOverhead(cast<FixedVectorType>(SrcVTy), DemandedElts, 5011 /*Insert=*/Opcode == Instruction::Load, 5012 /*Extract=*/Opcode == Instruction::Store); 5013 5014 return AddressUnpackCost + MemoryOpCost + MaskUnpackCost + InsertExtractCost; 5015 } 5016 5017 /// Calculate the cost of Gather / Scatter operation 5018 InstructionCost X86TTIImpl::getGatherScatterOpCost( 5019 unsigned Opcode, Type *SrcVTy, const Value *Ptr, bool VariableMask, 5020 Align Alignment, TTI::TargetCostKind CostKind, 5021 const Instruction *I = nullptr) { 5022 if (CostKind != TTI::TCK_RecipThroughput) { 5023 if ((Opcode == Instruction::Load && 5024 isLegalMaskedGather(SrcVTy, Align(Alignment)) && 5025 !forceScalarizeMaskedGather(cast<VectorType>(SrcVTy), 5026 Align(Alignment))) || 5027 (Opcode == Instruction::Store && 5028 isLegalMaskedScatter(SrcVTy, Align(Alignment)) && 5029 !forceScalarizeMaskedScatter(cast<VectorType>(SrcVTy), 5030 Align(Alignment)))) 5031 return 1; 5032 return BaseT::getGatherScatterOpCost(Opcode, SrcVTy, Ptr, VariableMask, 5033 Alignment, CostKind, I); 5034 } 5035 5036 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 5037 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 5038 if (!PtrTy && Ptr->getType()->isVectorTy()) 5039 PtrTy = dyn_cast<PointerType>( 5040 cast<VectorType>(Ptr->getType())->getElementType()); 5041 assert(PtrTy && "Unexpected type for Ptr argument"); 5042 unsigned AddressSpace = PtrTy->getAddressSpace(); 5043 5044 if ((Opcode == Instruction::Load && 5045 (!isLegalMaskedGather(SrcVTy, Align(Alignment)) || 5046 forceScalarizeMaskedGather(cast<VectorType>(SrcVTy), 5047 Align(Alignment)))) || 5048 (Opcode == Instruction::Store && 5049 (!isLegalMaskedScatter(SrcVTy, Align(Alignment)) || 5050 forceScalarizeMaskedScatter(cast<VectorType>(SrcVTy), 5051 Align(Alignment))))) 5052 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 5053 AddressSpace); 5054 5055 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 5056 } 5057 5058 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 5059 TargetTransformInfo::LSRCost &C2) { 5060 // X86 specific here are "instruction number 1st priority". 5061 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 5062 C1.NumIVMuls, C1.NumBaseAdds, 5063 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 5064 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 5065 C2.NumIVMuls, C2.NumBaseAdds, 5066 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 5067 } 5068 5069 bool X86TTIImpl::canMacroFuseCmp() { 5070 return ST->hasMacroFusion() || ST->hasBranchFusion(); 5071 } 5072 5073 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, Align Alignment) { 5074 if (!ST->hasAVX()) 5075 return false; 5076 5077 // The backend can't handle a single element vector. 5078 if (isa<VectorType>(DataTy) && 5079 cast<FixedVectorType>(DataTy)->getNumElements() == 1) 5080 return false; 5081 Type *ScalarTy = DataTy->getScalarType(); 5082 5083 if (ScalarTy->isPointerTy()) 5084 return true; 5085 5086 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 5087 return true; 5088 5089 if (ScalarTy->isHalfTy() && ST->hasBWI() && ST->hasFP16()) 5090 return true; 5091 5092 if (!ScalarTy->isIntegerTy()) 5093 return false; 5094 5095 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 5096 return IntWidth == 32 || IntWidth == 64 || 5097 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 5098 } 5099 5100 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, Align Alignment) { 5101 return isLegalMaskedLoad(DataType, Alignment); 5102 } 5103 5104 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 5105 unsigned DataSize = DL.getTypeStoreSize(DataType); 5106 // The only supported nontemporal loads are for aligned vectors of 16 or 32 5107 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 5108 // (the equivalent stores only require AVX). 5109 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 5110 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 5111 5112 return false; 5113 } 5114 5115 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 5116 unsigned DataSize = DL.getTypeStoreSize(DataType); 5117 5118 // SSE4A supports nontemporal stores of float and double at arbitrary 5119 // alignment. 5120 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 5121 return true; 5122 5123 // Besides the SSE4A subtarget exception above, only aligned stores are 5124 // available nontemporaly on any other subtarget. And only stores with a size 5125 // of 4..32 bytes (powers of 2, only) are permitted. 5126 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 5127 !isPowerOf2_32(DataSize)) 5128 return false; 5129 5130 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 5131 // loads require AVX2). 5132 if (DataSize == 32) 5133 return ST->hasAVX(); 5134 if (DataSize == 16) 5135 return ST->hasSSE1(); 5136 return true; 5137 } 5138 5139 bool X86TTIImpl::isLegalBroadcastLoad(Type *ElementTy, 5140 unsigned NumElements) const { 5141 // movddup 5142 return ST->hasSSE3() && NumElements == 2 && 5143 ElementTy == Type::getDoubleTy(ElementTy->getContext()); 5144 } 5145 5146 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 5147 if (!isa<VectorType>(DataTy)) 5148 return false; 5149 5150 if (!ST->hasAVX512()) 5151 return false; 5152 5153 // The backend can't handle a single element vector. 5154 if (cast<FixedVectorType>(DataTy)->getNumElements() == 1) 5155 return false; 5156 5157 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 5158 5159 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 5160 return true; 5161 5162 if (!ScalarTy->isIntegerTy()) 5163 return false; 5164 5165 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 5166 return IntWidth == 32 || IntWidth == 64 || 5167 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 5168 } 5169 5170 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 5171 return isLegalMaskedExpandLoad(DataTy); 5172 } 5173 5174 bool X86TTIImpl::supportsGather() const { 5175 // Some CPUs have better gather performance than others. 5176 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 5177 // enable gather with a -march. 5178 return ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()); 5179 } 5180 5181 bool X86TTIImpl::forceScalarizeMaskedGather(VectorType *VTy, Align Alignment) { 5182 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 5183 // Vector-4 of gather/scatter instruction does not exist on KNL. We can extend 5184 // it to 8 elements, but zeroing upper bits of the mask vector will add more 5185 // instructions. Right now we give the scalar cost of vector-4 for KNL. TODO: 5186 // Check, maybe the gather/scatter instruction is better in the VariableMask 5187 // case. 5188 unsigned NumElts = cast<FixedVectorType>(VTy)->getNumElements(); 5189 return NumElts == 1 || 5190 (ST->hasAVX512() && (NumElts == 2 || (NumElts == 4 && !ST->hasVLX()))); 5191 } 5192 5193 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, Align Alignment) { 5194 if (!supportsGather()) 5195 return false; 5196 Type *ScalarTy = DataTy->getScalarType(); 5197 if (ScalarTy->isPointerTy()) 5198 return true; 5199 5200 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 5201 return true; 5202 5203 if (!ScalarTy->isIntegerTy()) 5204 return false; 5205 5206 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 5207 return IntWidth == 32 || IntWidth == 64; 5208 } 5209 5210 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, Align Alignment) { 5211 // AVX2 doesn't support scatter 5212 if (!ST->hasAVX512()) 5213 return false; 5214 return isLegalMaskedGather(DataType, Alignment); 5215 } 5216 5217 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 5218 EVT VT = TLI->getValueType(DL, DataType); 5219 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 5220 } 5221 5222 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 5223 return false; 5224 } 5225 5226 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 5227 const Function *Callee) const { 5228 const TargetMachine &TM = getTLI()->getTargetMachine(); 5229 5230 // Work this as a subsetting of subtarget features. 5231 const FeatureBitset &CallerBits = 5232 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 5233 const FeatureBitset &CalleeBits = 5234 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 5235 5236 // Check whether features are the same (apart from the ignore list). 5237 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 5238 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 5239 if (RealCallerBits == RealCalleeBits) 5240 return true; 5241 5242 // If the features are a subset, we need to additionally check for calls 5243 // that may become ABI-incompatible as a result of inlining. 5244 if ((RealCallerBits & RealCalleeBits) != RealCalleeBits) 5245 return false; 5246 5247 for (const Instruction &I : instructions(Callee)) { 5248 if (const auto *CB = dyn_cast<CallBase>(&I)) { 5249 SmallVector<Type *, 8> Types; 5250 for (Value *Arg : CB->args()) 5251 Types.push_back(Arg->getType()); 5252 if (!CB->getType()->isVoidTy()) 5253 Types.push_back(CB->getType()); 5254 5255 // Simple types are always ABI compatible. 5256 auto IsSimpleTy = [](Type *Ty) { 5257 return !Ty->isVectorTy() && !Ty->isAggregateType(); 5258 }; 5259 if (all_of(Types, IsSimpleTy)) 5260 continue; 5261 5262 if (Function *NestedCallee = CB->getCalledFunction()) { 5263 // Assume that intrinsics are always ABI compatible. 5264 if (NestedCallee->isIntrinsic()) 5265 continue; 5266 5267 // Do a precise compatibility check. 5268 if (!areTypesABICompatible(Caller, NestedCallee, Types)) 5269 return false; 5270 } else { 5271 // We don't know the target features of the callee, 5272 // assume it is incompatible. 5273 return false; 5274 } 5275 } 5276 } 5277 return true; 5278 } 5279 5280 bool X86TTIImpl::areTypesABICompatible(const Function *Caller, 5281 const Function *Callee, 5282 const ArrayRef<Type *> &Types) const { 5283 if (!BaseT::areTypesABICompatible(Caller, Callee, Types)) 5284 return false; 5285 5286 // If we get here, we know the target features match. If one function 5287 // considers 512-bit vectors legal and the other does not, consider them 5288 // incompatible. 5289 const TargetMachine &TM = getTLI()->getTargetMachine(); 5290 5291 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 5292 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs()) 5293 return true; 5294 5295 // Consider the arguments compatible if they aren't vectors or aggregates. 5296 // FIXME: Look at the size of vectors. 5297 // FIXME: Look at the element types of aggregates to see if there are vectors. 5298 return llvm::none_of(Types, 5299 [](Type *T) { return T->isVectorTy() || T->isAggregateType(); }); 5300 } 5301 5302 X86TTIImpl::TTI::MemCmpExpansionOptions 5303 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 5304 TTI::MemCmpExpansionOptions Options; 5305 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 5306 Options.NumLoadsPerBlock = 2; 5307 // All GPR and vector loads can be unaligned. 5308 Options.AllowOverlappingLoads = true; 5309 if (IsZeroCmp) { 5310 // Only enable vector loads for equality comparison. Right now the vector 5311 // version is not as fast for three way compare (see #33329). 5312 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 5313 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 5314 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 5315 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 5316 } 5317 if (ST->is64Bit()) { 5318 Options.LoadSizes.push_back(8); 5319 } 5320 Options.LoadSizes.push_back(4); 5321 Options.LoadSizes.push_back(2); 5322 Options.LoadSizes.push_back(1); 5323 return Options; 5324 } 5325 5326 bool X86TTIImpl::prefersVectorizedAddressing() const { 5327 return supportsGather(); 5328 } 5329 5330 bool X86TTIImpl::supportsEfficientVectorElementLoadStore() const { 5331 return false; 5332 } 5333 5334 bool X86TTIImpl::enableInterleavedAccessVectorization() { 5335 // TODO: We expect this to be beneficial regardless of arch, 5336 // but there are currently some unexplained performance artifacts on Atom. 5337 // As a temporary solution, disable on Atom. 5338 return !(ST->isAtom()); 5339 } 5340 5341 // Get estimation for interleaved load/store operations and strided load. 5342 // \p Indices contains indices for strided load. 5343 // \p Factor - the factor of interleaving. 5344 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 5345 InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX512( 5346 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 5347 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 5348 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 5349 // VecTy for interleave memop is <VF*Factor x Elt>. 5350 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 5351 // VecTy = <12 x i32>. 5352 5353 // Calculate the number of memory operations (NumOfMemOps), required 5354 // for load/store the VecTy. 5355 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 5356 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 5357 unsigned LegalVTSize = LegalVT.getStoreSize(); 5358 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 5359 5360 // Get the cost of one memory operation. 5361 auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(), 5362 LegalVT.getVectorNumElements()); 5363 InstructionCost MemOpCost; 5364 bool UseMaskedMemOp = UseMaskForCond || UseMaskForGaps; 5365 if (UseMaskedMemOp) 5366 MemOpCost = getMaskedMemoryOpCost(Opcode, SingleMemOpTy, Alignment, 5367 AddressSpace, CostKind); 5368 else 5369 MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, MaybeAlign(Alignment), 5370 AddressSpace, CostKind); 5371 5372 unsigned VF = VecTy->getNumElements() / Factor; 5373 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 5374 5375 InstructionCost MaskCost; 5376 if (UseMaskedMemOp) { 5377 APInt DemandedLoadStoreElts = APInt::getZero(VecTy->getNumElements()); 5378 for (unsigned Index : Indices) { 5379 assert(Index < Factor && "Invalid index for interleaved memory op"); 5380 for (unsigned Elm = 0; Elm < VF; Elm++) 5381 DemandedLoadStoreElts.setBit(Index + Elm * Factor); 5382 } 5383 5384 Type *I1Type = Type::getInt1Ty(VecTy->getContext()); 5385 5386 MaskCost = getReplicationShuffleCost( 5387 I1Type, Factor, VF, 5388 UseMaskForGaps ? DemandedLoadStoreElts 5389 : APInt::getAllOnes(VecTy->getNumElements()), 5390 CostKind); 5391 5392 // The Gaps mask is invariant and created outside the loop, therefore the 5393 // cost of creating it is not accounted for here. However if we have both 5394 // a MaskForGaps and some other mask that guards the execution of the 5395 // memory access, we need to account for the cost of And-ing the two masks 5396 // inside the loop. 5397 if (UseMaskForGaps) { 5398 auto *MaskVT = FixedVectorType::get(I1Type, VecTy->getNumElements()); 5399 MaskCost += getArithmeticInstrCost(BinaryOperator::And, MaskVT, CostKind); 5400 } 5401 } 5402 5403 if (Opcode == Instruction::Load) { 5404 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 5405 // contain the cost of the optimized shuffle sequence that the 5406 // X86InterleavedAccess pass will generate. 5407 // The cost of loads and stores are computed separately from the table. 5408 5409 // X86InterleavedAccess support only the following interleaved-access group. 5410 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 5411 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 5412 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 5413 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 5414 }; 5415 5416 if (const auto *Entry = 5417 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 5418 return MaskCost + NumOfMemOps * MemOpCost + Entry->Cost; 5419 //If an entry does not exist, fallback to the default implementation. 5420 5421 // Kind of shuffle depends on number of loaded values. 5422 // If we load the entire data in one register, we can use a 1-src shuffle. 5423 // Otherwise, we'll merge 2 sources in each operation. 5424 TTI::ShuffleKind ShuffleKind = 5425 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 5426 5427 InstructionCost ShuffleCost = 5428 getShuffleCost(ShuffleKind, SingleMemOpTy, None, 0, nullptr); 5429 5430 unsigned NumOfLoadsInInterleaveGrp = 5431 Indices.size() ? Indices.size() : Factor; 5432 auto *ResultTy = FixedVectorType::get(VecTy->getElementType(), 5433 VecTy->getNumElements() / Factor); 5434 InstructionCost NumOfResults = 5435 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 5436 NumOfLoadsInInterleaveGrp; 5437 5438 // About a half of the loads may be folded in shuffles when we have only 5439 // one result. If we have more than one result, or the loads are masked, 5440 // we do not fold loads at all. 5441 unsigned NumOfUnfoldedLoads = 5442 UseMaskedMemOp || NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 5443 5444 // Get a number of shuffle operations per result. 5445 unsigned NumOfShufflesPerResult = 5446 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 5447 5448 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 5449 // When we have more than one destination, we need additional instructions 5450 // to keep sources. 5451 InstructionCost NumOfMoves = 0; 5452 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 5453 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 5454 5455 InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 5456 MaskCost + NumOfUnfoldedLoads * MemOpCost + 5457 NumOfMoves; 5458 5459 return Cost; 5460 } 5461 5462 // Store. 5463 assert(Opcode == Instruction::Store && 5464 "Expected Store Instruction at this point"); 5465 // X86InterleavedAccess support only the following interleaved-access group. 5466 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 5467 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 5468 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 5469 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 5470 5471 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 5472 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 5473 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 5474 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 5475 }; 5476 5477 if (const auto *Entry = 5478 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 5479 return MaskCost + NumOfMemOps * MemOpCost + Entry->Cost; 5480 //If an entry does not exist, fallback to the default implementation. 5481 5482 // There is no strided stores meanwhile. And store can't be folded in 5483 // shuffle. 5484 unsigned NumOfSources = Factor; // The number of values to be merged. 5485 InstructionCost ShuffleCost = 5486 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, None, 0, nullptr); 5487 unsigned NumOfShufflesPerStore = NumOfSources - 1; 5488 5489 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 5490 // We need additional instructions to keep sources. 5491 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 5492 InstructionCost Cost = 5493 MaskCost + 5494 NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 5495 NumOfMoves; 5496 return Cost; 5497 } 5498 5499 InstructionCost X86TTIImpl::getInterleavedMemoryOpCost( 5500 unsigned Opcode, Type *BaseTy, unsigned Factor, ArrayRef<unsigned> Indices, 5501 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, 5502 bool UseMaskForCond, bool UseMaskForGaps) { 5503 auto *VecTy = cast<FixedVectorType>(BaseTy); 5504 5505 auto isSupportedOnAVX512 = [&](Type *VecTy, bool HasBW) { 5506 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 5507 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 5508 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 5509 return true; 5510 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8) || 5511 (!ST->useSoftFloat() && ST->hasFP16() && EltTy->isHalfTy())) 5512 return HasBW; 5513 return false; 5514 }; 5515 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 5516 return getInterleavedMemoryOpCostAVX512( 5517 Opcode, VecTy, Factor, Indices, Alignment, 5518 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 5519 5520 if (UseMaskForCond || UseMaskForGaps) 5521 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5522 Alignment, AddressSpace, CostKind, 5523 UseMaskForCond, UseMaskForGaps); 5524 5525 // Get estimation for interleaved load/store operations for SSE-AVX2. 5526 // As opposed to AVX-512, SSE-AVX2 do not have generic shuffles that allow 5527 // computing the cost using a generic formula as a function of generic 5528 // shuffles. We therefore use a lookup table instead, filled according to 5529 // the instruction sequences that codegen currently generates. 5530 5531 // VecTy for interleave memop is <VF*Factor x Elt>. 5532 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 5533 // VecTy = <12 x i32>. 5534 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 5535 5536 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 5537 // the VF=2, while v2i128 is an unsupported MVT vector type 5538 // (see MachineValueType.h::getVectorVT()). 5539 if (!LegalVT.isVector()) 5540 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5541 Alignment, AddressSpace, CostKind); 5542 5543 unsigned VF = VecTy->getNumElements() / Factor; 5544 Type *ScalarTy = VecTy->getElementType(); 5545 // Deduplicate entries, model floats/pointers as appropriately-sized integers. 5546 if (!ScalarTy->isIntegerTy()) 5547 ScalarTy = 5548 Type::getIntNTy(ScalarTy->getContext(), DL.getTypeSizeInBits(ScalarTy)); 5549 5550 // Get the cost of all the memory operations. 5551 // FIXME: discount dead loads. 5552 InstructionCost MemOpCosts = getMemoryOpCost( 5553 Opcode, VecTy, MaybeAlign(Alignment), AddressSpace, CostKind); 5554 5555 auto *VT = FixedVectorType::get(ScalarTy, VF); 5556 EVT ETy = TLI->getValueType(DL, VT); 5557 if (!ETy.isSimple()) 5558 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5559 Alignment, AddressSpace, CostKind); 5560 5561 // TODO: Complete for other data-types and strides. 5562 // Each combination of Stride, element bit width and VF results in a different 5563 // sequence; The cost tables are therefore accessed with: 5564 // Factor (stride) and VectorType=VFxiN. 5565 // The Cost accounts only for the shuffle sequence; 5566 // The cost of the loads/stores is accounted for separately. 5567 // 5568 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 5569 {2, MVT::v2i8, 2}, // (load 4i8 and) deinterleave into 2 x 2i8 5570 {2, MVT::v4i8, 2}, // (load 8i8 and) deinterleave into 2 x 4i8 5571 {2, MVT::v8i8, 2}, // (load 16i8 and) deinterleave into 2 x 8i8 5572 {2, MVT::v16i8, 4}, // (load 32i8 and) deinterleave into 2 x 16i8 5573 {2, MVT::v32i8, 6}, // (load 64i8 and) deinterleave into 2 x 32i8 5574 5575 {2, MVT::v8i16, 6}, // (load 16i16 and) deinterleave into 2 x 8i16 5576 {2, MVT::v16i16, 9}, // (load 32i16 and) deinterleave into 2 x 16i16 5577 {2, MVT::v32i16, 18}, // (load 64i16 and) deinterleave into 2 x 32i16 5578 5579 {2, MVT::v8i32, 4}, // (load 16i32 and) deinterleave into 2 x 8i32 5580 {2, MVT::v16i32, 8}, // (load 32i32 and) deinterleave into 2 x 16i32 5581 {2, MVT::v32i32, 16}, // (load 64i32 and) deinterleave into 2 x 32i32 5582 5583 {2, MVT::v4i64, 4}, // (load 8i64 and) deinterleave into 2 x 4i64 5584 {2, MVT::v8i64, 8}, // (load 16i64 and) deinterleave into 2 x 8i64 5585 {2, MVT::v16i64, 16}, // (load 32i64 and) deinterleave into 2 x 16i64 5586 {2, MVT::v32i64, 32}, // (load 64i64 and) deinterleave into 2 x 32i64 5587 5588 {3, MVT::v2i8, 3}, // (load 6i8 and) deinterleave into 3 x 2i8 5589 {3, MVT::v4i8, 3}, // (load 12i8 and) deinterleave into 3 x 4i8 5590 {3, MVT::v8i8, 6}, // (load 24i8 and) deinterleave into 3 x 8i8 5591 {3, MVT::v16i8, 11}, // (load 48i8 and) deinterleave into 3 x 16i8 5592 {3, MVT::v32i8, 14}, // (load 96i8 and) deinterleave into 3 x 32i8 5593 5594 {3, MVT::v2i16, 5}, // (load 6i16 and) deinterleave into 3 x 2i16 5595 {3, MVT::v4i16, 7}, // (load 12i16 and) deinterleave into 3 x 4i16 5596 {3, MVT::v8i16, 9}, // (load 24i16 and) deinterleave into 3 x 8i16 5597 {3, MVT::v16i16, 28}, // (load 48i16 and) deinterleave into 3 x 16i16 5598 {3, MVT::v32i16, 56}, // (load 96i16 and) deinterleave into 3 x 32i16 5599 5600 {3, MVT::v2i32, 3}, // (load 6i32 and) deinterleave into 3 x 2i32 5601 {3, MVT::v4i32, 3}, // (load 12i32 and) deinterleave into 3 x 4i32 5602 {3, MVT::v8i32, 7}, // (load 24i32 and) deinterleave into 3 x 8i32 5603 {3, MVT::v16i32, 14}, // (load 48i32 and) deinterleave into 3 x 16i32 5604 {3, MVT::v32i32, 32}, // (load 96i32 and) deinterleave into 3 x 32i32 5605 5606 {3, MVT::v2i64, 1}, // (load 6i64 and) deinterleave into 3 x 2i64 5607 {3, MVT::v4i64, 5}, // (load 12i64 and) deinterleave into 3 x 4i64 5608 {3, MVT::v8i64, 10}, // (load 24i64 and) deinterleave into 3 x 8i64 5609 {3, MVT::v16i64, 20}, // (load 48i64 and) deinterleave into 3 x 16i64 5610 5611 {4, MVT::v2i8, 4}, // (load 8i8 and) deinterleave into 4 x 2i8 5612 {4, MVT::v4i8, 4}, // (load 16i8 and) deinterleave into 4 x 4i8 5613 {4, MVT::v8i8, 12}, // (load 32i8 and) deinterleave into 4 x 8i8 5614 {4, MVT::v16i8, 24}, // (load 64i8 and) deinterleave into 4 x 16i8 5615 {4, MVT::v32i8, 56}, // (load 128i8 and) deinterleave into 4 x 32i8 5616 5617 {4, MVT::v2i16, 6}, // (load 8i16 and) deinterleave into 4 x 2i16 5618 {4, MVT::v4i16, 17}, // (load 16i16 and) deinterleave into 4 x 4i16 5619 {4, MVT::v8i16, 33}, // (load 32i16 and) deinterleave into 4 x 8i16 5620 {4, MVT::v16i16, 75}, // (load 64i16 and) deinterleave into 4 x 16i16 5621 {4, MVT::v32i16, 150}, // (load 128i16 and) deinterleave into 4 x 32i16 5622 5623 {4, MVT::v2i32, 4}, // (load 8i32 and) deinterleave into 4 x 2i32 5624 {4, MVT::v4i32, 8}, // (load 16i32 and) deinterleave into 4 x 4i32 5625 {4, MVT::v8i32, 16}, // (load 32i32 and) deinterleave into 4 x 8i32 5626 {4, MVT::v16i32, 32}, // (load 64i32 and) deinterleave into 4 x 16i32 5627 {4, MVT::v32i32, 68}, // (load 128i32 and) deinterleave into 4 x 32i32 5628 5629 {4, MVT::v2i64, 6}, // (load 8i64 and) deinterleave into 4 x 2i64 5630 {4, MVT::v4i64, 8}, // (load 16i64 and) deinterleave into 4 x 4i64 5631 {4, MVT::v8i64, 20}, // (load 32i64 and) deinterleave into 4 x 8i64 5632 {4, MVT::v16i64, 40}, // (load 64i64 and) deinterleave into 4 x 16i64 5633 5634 {6, MVT::v2i8, 6}, // (load 12i8 and) deinterleave into 6 x 2i8 5635 {6, MVT::v4i8, 14}, // (load 24i8 and) deinterleave into 6 x 4i8 5636 {6, MVT::v8i8, 18}, // (load 48i8 and) deinterleave into 6 x 8i8 5637 {6, MVT::v16i8, 43}, // (load 96i8 and) deinterleave into 6 x 16i8 5638 {6, MVT::v32i8, 82}, // (load 192i8 and) deinterleave into 6 x 32i8 5639 5640 {6, MVT::v2i16, 13}, // (load 12i16 and) deinterleave into 6 x 2i16 5641 {6, MVT::v4i16, 9}, // (load 24i16 and) deinterleave into 6 x 4i16 5642 {6, MVT::v8i16, 39}, // (load 48i16 and) deinterleave into 6 x 8i16 5643 {6, MVT::v16i16, 106}, // (load 96i16 and) deinterleave into 6 x 16i16 5644 {6, MVT::v32i16, 212}, // (load 192i16 and) deinterleave into 6 x 32i16 5645 5646 {6, MVT::v2i32, 6}, // (load 12i32 and) deinterleave into 6 x 2i32 5647 {6, MVT::v4i32, 15}, // (load 24i32 and) deinterleave into 6 x 4i32 5648 {6, MVT::v8i32, 31}, // (load 48i32 and) deinterleave into 6 x 8i32 5649 {6, MVT::v16i32, 64}, // (load 96i32 and) deinterleave into 6 x 16i32 5650 5651 {6, MVT::v2i64, 6}, // (load 12i64 and) deinterleave into 6 x 2i64 5652 {6, MVT::v4i64, 18}, // (load 24i64 and) deinterleave into 6 x 4i64 5653 {6, MVT::v8i64, 36}, // (load 48i64 and) deinterleave into 6 x 8i64 5654 5655 {8, MVT::v8i32, 40} // (load 64i32 and) deinterleave into 8 x 8i32 5656 }; 5657 5658 static const CostTblEntry SSSE3InterleavedLoadTbl[] = { 5659 {2, MVT::v4i16, 2}, // (load 8i16 and) deinterleave into 2 x 4i16 5660 }; 5661 5662 static const CostTblEntry SSE2InterleavedLoadTbl[] = { 5663 {2, MVT::v2i16, 2}, // (load 4i16 and) deinterleave into 2 x 2i16 5664 {2, MVT::v4i16, 7}, // (load 8i16 and) deinterleave into 2 x 4i16 5665 5666 {2, MVT::v2i32, 2}, // (load 4i32 and) deinterleave into 2 x 2i32 5667 {2, MVT::v4i32, 2}, // (load 8i32 and) deinterleave into 2 x 4i32 5668 5669 {2, MVT::v2i64, 2}, // (load 4i64 and) deinterleave into 2 x 2i64 5670 }; 5671 5672 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 5673 {2, MVT::v16i8, 3}, // interleave 2 x 16i8 into 32i8 (and store) 5674 {2, MVT::v32i8, 4}, // interleave 2 x 32i8 into 64i8 (and store) 5675 5676 {2, MVT::v8i16, 3}, // interleave 2 x 8i16 into 16i16 (and store) 5677 {2, MVT::v16i16, 4}, // interleave 2 x 16i16 into 32i16 (and store) 5678 {2, MVT::v32i16, 8}, // interleave 2 x 32i16 into 64i16 (and store) 5679 5680 {2, MVT::v4i32, 2}, // interleave 2 x 4i32 into 8i32 (and store) 5681 {2, MVT::v8i32, 4}, // interleave 2 x 8i32 into 16i32 (and store) 5682 {2, MVT::v16i32, 8}, // interleave 2 x 16i32 into 32i32 (and store) 5683 {2, MVT::v32i32, 16}, // interleave 2 x 32i32 into 64i32 (and store) 5684 5685 {2, MVT::v2i64, 2}, // interleave 2 x 2i64 into 4i64 (and store) 5686 {2, MVT::v4i64, 4}, // interleave 2 x 4i64 into 8i64 (and store) 5687 {2, MVT::v8i64, 8}, // interleave 2 x 8i64 into 16i64 (and store) 5688 {2, MVT::v16i64, 16}, // interleave 2 x 16i64 into 32i64 (and store) 5689 {2, MVT::v32i64, 32}, // interleave 2 x 32i64 into 64i64 (and store) 5690 5691 {3, MVT::v2i8, 4}, // interleave 3 x 2i8 into 6i8 (and store) 5692 {3, MVT::v4i8, 4}, // interleave 3 x 4i8 into 12i8 (and store) 5693 {3, MVT::v8i8, 6}, // interleave 3 x 8i8 into 24i8 (and store) 5694 {3, MVT::v16i8, 11}, // interleave 3 x 16i8 into 48i8 (and store) 5695 {3, MVT::v32i8, 13}, // interleave 3 x 32i8 into 96i8 (and store) 5696 5697 {3, MVT::v2i16, 4}, // interleave 3 x 2i16 into 6i16 (and store) 5698 {3, MVT::v4i16, 6}, // interleave 3 x 4i16 into 12i16 (and store) 5699 {3, MVT::v8i16, 12}, // interleave 3 x 8i16 into 24i16 (and store) 5700 {3, MVT::v16i16, 27}, // interleave 3 x 16i16 into 48i16 (and store) 5701 {3, MVT::v32i16, 54}, // interleave 3 x 32i16 into 96i16 (and store) 5702 5703 {3, MVT::v2i32, 4}, // interleave 3 x 2i32 into 6i32 (and store) 5704 {3, MVT::v4i32, 5}, // interleave 3 x 4i32 into 12i32 (and store) 5705 {3, MVT::v8i32, 11}, // interleave 3 x 8i32 into 24i32 (and store) 5706 {3, MVT::v16i32, 22}, // interleave 3 x 16i32 into 48i32 (and store) 5707 {3, MVT::v32i32, 48}, // interleave 3 x 32i32 into 96i32 (and store) 5708 5709 {3, MVT::v2i64, 4}, // interleave 3 x 2i64 into 6i64 (and store) 5710 {3, MVT::v4i64, 6}, // interleave 3 x 4i64 into 12i64 (and store) 5711 {3, MVT::v8i64, 12}, // interleave 3 x 8i64 into 24i64 (and store) 5712 {3, MVT::v16i64, 24}, // interleave 3 x 16i64 into 48i64 (and store) 5713 5714 {4, MVT::v2i8, 4}, // interleave 4 x 2i8 into 8i8 (and store) 5715 {4, MVT::v4i8, 4}, // interleave 4 x 4i8 into 16i8 (and store) 5716 {4, MVT::v8i8, 4}, // interleave 4 x 8i8 into 32i8 (and store) 5717 {4, MVT::v16i8, 8}, // interleave 4 x 16i8 into 64i8 (and store) 5718 {4, MVT::v32i8, 12}, // interleave 4 x 32i8 into 128i8 (and store) 5719 5720 {4, MVT::v2i16, 2}, // interleave 4 x 2i16 into 8i16 (and store) 5721 {4, MVT::v4i16, 6}, // interleave 4 x 4i16 into 16i16 (and store) 5722 {4, MVT::v8i16, 10}, // interleave 4 x 8i16 into 32i16 (and store) 5723 {4, MVT::v16i16, 32}, // interleave 4 x 16i16 into 64i16 (and store) 5724 {4, MVT::v32i16, 64}, // interleave 4 x 32i16 into 128i16 (and store) 5725 5726 {4, MVT::v2i32, 5}, // interleave 4 x 2i32 into 8i32 (and store) 5727 {4, MVT::v4i32, 6}, // interleave 4 x 4i32 into 16i32 (and store) 5728 {4, MVT::v8i32, 16}, // interleave 4 x 8i32 into 32i32 (and store) 5729 {4, MVT::v16i32, 32}, // interleave 4 x 16i32 into 64i32 (and store) 5730 {4, MVT::v32i32, 64}, // interleave 4 x 32i32 into 128i32 (and store) 5731 5732 {4, MVT::v2i64, 6}, // interleave 4 x 2i64 into 8i64 (and store) 5733 {4, MVT::v4i64, 8}, // interleave 4 x 4i64 into 16i64 (and store) 5734 {4, MVT::v8i64, 20}, // interleave 4 x 8i64 into 32i64 (and store) 5735 {4, MVT::v16i64, 40}, // interleave 4 x 16i64 into 64i64 (and store) 5736 5737 {6, MVT::v2i8, 7}, // interleave 6 x 2i8 into 12i8 (and store) 5738 {6, MVT::v4i8, 9}, // interleave 6 x 4i8 into 24i8 (and store) 5739 {6, MVT::v8i8, 16}, // interleave 6 x 8i8 into 48i8 (and store) 5740 {6, MVT::v16i8, 27}, // interleave 6 x 16i8 into 96i8 (and store) 5741 {6, MVT::v32i8, 90}, // interleave 6 x 32i8 into 192i8 (and store) 5742 5743 {6, MVT::v2i16, 10}, // interleave 6 x 2i16 into 12i16 (and store) 5744 {6, MVT::v4i16, 15}, // interleave 6 x 4i16 into 24i16 (and store) 5745 {6, MVT::v8i16, 21}, // interleave 6 x 8i16 into 48i16 (and store) 5746 {6, MVT::v16i16, 58}, // interleave 6 x 16i16 into 96i16 (and store) 5747 {6, MVT::v32i16, 90}, // interleave 6 x 32i16 into 192i16 (and store) 5748 5749 {6, MVT::v2i32, 9}, // interleave 6 x 2i32 into 12i32 (and store) 5750 {6, MVT::v4i32, 12}, // interleave 6 x 4i32 into 24i32 (and store) 5751 {6, MVT::v8i32, 33}, // interleave 6 x 8i32 into 48i32 (and store) 5752 {6, MVT::v16i32, 66}, // interleave 6 x 16i32 into 96i32 (and store) 5753 5754 {6, MVT::v2i64, 8}, // interleave 6 x 2i64 into 12i64 (and store) 5755 {6, MVT::v4i64, 15}, // interleave 6 x 4i64 into 24i64 (and store) 5756 {6, MVT::v8i64, 30}, // interleave 6 x 8i64 into 48i64 (and store) 5757 }; 5758 5759 static const CostTblEntry SSE2InterleavedStoreTbl[] = { 5760 {2, MVT::v2i8, 1}, // interleave 2 x 2i8 into 4i8 (and store) 5761 {2, MVT::v4i8, 1}, // interleave 2 x 4i8 into 8i8 (and store) 5762 {2, MVT::v8i8, 1}, // interleave 2 x 8i8 into 16i8 (and store) 5763 5764 {2, MVT::v2i16, 1}, // interleave 2 x 2i16 into 4i16 (and store) 5765 {2, MVT::v4i16, 1}, // interleave 2 x 4i16 into 8i16 (and store) 5766 5767 {2, MVT::v2i32, 1}, // interleave 2 x 2i32 into 4i32 (and store) 5768 }; 5769 5770 if (Opcode == Instruction::Load) { 5771 auto GetDiscountedCost = [Factor, NumMembers = Indices.size(), 5772 MemOpCosts](const CostTblEntry *Entry) { 5773 // NOTE: this is just an approximation! 5774 // It can over/under -estimate the cost! 5775 return MemOpCosts + divideCeil(NumMembers * Entry->Cost, Factor); 5776 }; 5777 5778 if (ST->hasAVX2()) 5779 if (const auto *Entry = CostTableLookup(AVX2InterleavedLoadTbl, Factor, 5780 ETy.getSimpleVT())) 5781 return GetDiscountedCost(Entry); 5782 5783 if (ST->hasSSSE3()) 5784 if (const auto *Entry = CostTableLookup(SSSE3InterleavedLoadTbl, Factor, 5785 ETy.getSimpleVT())) 5786 return GetDiscountedCost(Entry); 5787 5788 if (ST->hasSSE2()) 5789 if (const auto *Entry = CostTableLookup(SSE2InterleavedLoadTbl, Factor, 5790 ETy.getSimpleVT())) 5791 return GetDiscountedCost(Entry); 5792 } else { 5793 assert(Opcode == Instruction::Store && 5794 "Expected Store Instruction at this point"); 5795 assert((!Indices.size() || Indices.size() == Factor) && 5796 "Interleaved store only supports fully-interleaved groups."); 5797 if (ST->hasAVX2()) 5798 if (const auto *Entry = CostTableLookup(AVX2InterleavedStoreTbl, Factor, 5799 ETy.getSimpleVT())) 5800 return MemOpCosts + Entry->Cost; 5801 5802 if (ST->hasSSE2()) 5803 if (const auto *Entry = CostTableLookup(SSE2InterleavedStoreTbl, Factor, 5804 ETy.getSimpleVT())) 5805 return MemOpCosts + Entry->Cost; 5806 } 5807 5808 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5809 Alignment, AddressSpace, CostKind, 5810 UseMaskForCond, UseMaskForGaps); 5811 } 5812