1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // X86 cost model. 56 // 57 //===----------------------------------------------------------------------===// 58 59 TargetTransformInfo::PopcntSupportKind 60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 61 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 62 // TODO: Currently the __builtin_popcount() implementation using SSE3 63 // instructions is inefficient. Once the problem is fixed, we should 64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 66 } 67 68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 69 TargetTransformInfo::CacheLevel Level) const { 70 switch (Level) { 71 case TargetTransformInfo::CacheLevel::L1D: 72 // - Penryn 73 // - Nehalem 74 // - Westmere 75 // - Sandy Bridge 76 // - Ivy Bridge 77 // - Haswell 78 // - Broadwell 79 // - Skylake 80 // - Kabylake 81 return 32 * 1024; // 32 KByte 82 case TargetTransformInfo::CacheLevel::L2D: 83 // - Penryn 84 // - Nehalem 85 // - Westmere 86 // - Sandy Bridge 87 // - Ivy Bridge 88 // - Haswell 89 // - Broadwell 90 // - Skylake 91 // - Kabylake 92 return 256 * 1024; // 256 KByte 93 } 94 95 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 96 } 97 98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 99 TargetTransformInfo::CacheLevel Level) const { 100 // - Penryn 101 // - Nehalem 102 // - Westmere 103 // - Sandy Bridge 104 // - Ivy Bridge 105 // - Haswell 106 // - Broadwell 107 // - Skylake 108 // - Kabylake 109 switch (Level) { 110 case TargetTransformInfo::CacheLevel::L1D: 111 LLVM_FALLTHROUGH; 112 case TargetTransformInfo::CacheLevel::L2D: 113 return 8; 114 } 115 116 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 117 } 118 119 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 120 bool Vector = (ClassID == 1); 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const { 133 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 134 if (Vector) { 135 if (ST->hasAVX512() && PreferVectorWidth >= 512) 136 return 512; 137 if (ST->hasAVX() && PreferVectorWidth >= 256) 138 return 256; 139 if (ST->hasSSE1() && PreferVectorWidth >= 128) 140 return 128; 141 return 0; 142 } 143 144 if (ST->is64Bit()) 145 return 64; 146 147 return 32; 148 } 149 150 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 151 return getRegisterBitWidth(true); 152 } 153 154 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 155 // If the loop will not be vectorized, don't interleave the loop. 156 // Let regular unroll to unroll the loop, which saves the overflow 157 // check and memory check cost. 158 if (VF == 1) 159 return 1; 160 161 if (ST->isAtom()) 162 return 1; 163 164 // Sandybridge and Haswell have multiple execution ports and pipelined 165 // vector units. 166 if (ST->hasAVX()) 167 return 4; 168 169 return 2; 170 } 171 172 int X86TTIImpl::getArithmeticInstrCost(unsigned Opcode, Type *Ty, 173 TTI::TargetCostKind CostKind, 174 TTI::OperandValueKind Op1Info, 175 TTI::OperandValueKind Op2Info, 176 TTI::OperandValueProperties Opd1PropInfo, 177 TTI::OperandValueProperties Opd2PropInfo, 178 ArrayRef<const Value *> Args, 179 const Instruction *CxtI) { 180 // TODO: Handle more cost kinds. 181 if (CostKind != TTI::TCK_RecipThroughput) 182 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, 183 Op2Info, Opd1PropInfo, 184 Opd2PropInfo, Args, CxtI); 185 // Legalize the type. 186 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 187 188 int ISD = TLI->InstructionOpcodeToISD(Opcode); 189 assert(ISD && "Invalid opcode"); 190 191 static const CostTblEntry GLMCostTable[] = { 192 { ISD::FDIV, MVT::f32, 18 }, // divss 193 { ISD::FDIV, MVT::v4f32, 35 }, // divps 194 { ISD::FDIV, MVT::f64, 33 }, // divsd 195 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 196 }; 197 198 if (ST->useGLMDivSqrtCosts()) 199 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 200 LT.second)) 201 return LT.first * Entry->Cost; 202 203 static const CostTblEntry SLMCostTable[] = { 204 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 205 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 206 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. 207 { ISD::FMUL, MVT::f64, 2 }, // mulsd 208 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 209 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 210 { ISD::FDIV, MVT::f32, 17 }, // divss 211 { ISD::FDIV, MVT::v4f32, 39 }, // divps 212 { ISD::FDIV, MVT::f64, 32 }, // divsd 213 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 214 { ISD::FADD, MVT::v2f64, 2 }, // addpd 215 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 216 // v2i64/v4i64 mul is custom lowered as a series of long: 217 // multiplies(3), shifts(3) and adds(2) 218 // slm muldq version throughput is 2 and addq throughput 4 219 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 220 // 3X4 (addq throughput) = 17 221 { ISD::MUL, MVT::v2i64, 17 }, 222 // slm addq\subq throughput is 4 223 { ISD::ADD, MVT::v2i64, 4 }, 224 { ISD::SUB, MVT::v2i64, 4 }, 225 }; 226 227 if (ST->isSLM()) { 228 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 229 // Check if the operands can be shrinked into a smaller datatype. 230 bool Op1Signed = false; 231 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 232 bool Op2Signed = false; 233 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 234 235 bool SignedMode = Op1Signed || Op2Signed; 236 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 237 238 if (OpMinSize <= 7) 239 return LT.first * 3; // pmullw/sext 240 if (!SignedMode && OpMinSize <= 8) 241 return LT.first * 3; // pmullw/zext 242 if (OpMinSize <= 15) 243 return LT.first * 5; // pmullw/pmulhw/pshuf 244 if (!SignedMode && OpMinSize <= 16) 245 return LT.first * 5; // pmullw/pmulhw/pshuf 246 } 247 248 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 249 LT.second)) { 250 return LT.first * Entry->Cost; 251 } 252 } 253 254 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 255 ISD == ISD::UREM) && 256 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 257 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 258 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 259 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 260 // On X86, vector signed division by constants power-of-two are 261 // normally expanded to the sequence SRA + SRL + ADD + SRA. 262 // The OperandValue properties may not be the same as that of the previous 263 // operation; conservatively assume OP_None. 264 int Cost = 265 2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Op1Info, 266 Op2Info, 267 TargetTransformInfo::OP_None, 268 TargetTransformInfo::OP_None); 269 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 270 Op2Info, 271 TargetTransformInfo::OP_None, 272 TargetTransformInfo::OP_None); 273 Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind, Op1Info, 274 Op2Info, 275 TargetTransformInfo::OP_None, 276 TargetTransformInfo::OP_None); 277 278 if (ISD == ISD::SREM) { 279 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 280 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info, 281 Op2Info); 282 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info, 283 Op2Info); 284 } 285 286 return Cost; 287 } 288 289 // Vector unsigned division/remainder will be simplified to shifts/masks. 290 if (ISD == ISD::UDIV) 291 return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, 292 Op1Info, Op2Info, 293 TargetTransformInfo::OP_None, 294 TargetTransformInfo::OP_None); 295 296 else // UREM 297 return getArithmeticInstrCost(Instruction::And, Ty, CostKind, 298 Op1Info, Op2Info, 299 TargetTransformInfo::OP_None, 300 TargetTransformInfo::OP_None); 301 } 302 303 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 304 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 305 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 306 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 307 }; 308 309 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 310 ST->hasBWI()) { 311 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 312 LT.second)) 313 return LT.first * Entry->Cost; 314 } 315 316 static const CostTblEntry AVX512UniformConstCostTable[] = { 317 { ISD::SRA, MVT::v2i64, 1 }, 318 { ISD::SRA, MVT::v4i64, 1 }, 319 { ISD::SRA, MVT::v8i64, 1 }, 320 321 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 322 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 323 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 324 325 { ISD::SDIV, MVT::v16i32, 6 }, // pmuludq sequence 326 { ISD::SREM, MVT::v16i32, 8 }, // pmuludq+mul+sub sequence 327 { ISD::UDIV, MVT::v16i32, 5 }, // pmuludq sequence 328 { ISD::UREM, MVT::v16i32, 7 }, // pmuludq+mul+sub sequence 329 }; 330 331 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 332 ST->hasAVX512()) { 333 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 334 LT.second)) 335 return LT.first * Entry->Cost; 336 } 337 338 static const CostTblEntry AVX2UniformConstCostTable[] = { 339 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 340 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 341 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 342 343 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 344 345 { ISD::SDIV, MVT::v8i32, 6 }, // pmuludq sequence 346 { ISD::SREM, MVT::v8i32, 8 }, // pmuludq+mul+sub sequence 347 { ISD::UDIV, MVT::v8i32, 5 }, // pmuludq sequence 348 { ISD::UREM, MVT::v8i32, 7 }, // pmuludq+mul+sub sequence 349 }; 350 351 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 352 ST->hasAVX2()) { 353 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 354 LT.second)) 355 return LT.first * Entry->Cost; 356 } 357 358 static const CostTblEntry SSE2UniformConstCostTable[] = { 359 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 360 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 361 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 362 363 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 364 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 365 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 366 367 { ISD::SDIV, MVT::v8i32, 12+2 }, // 2*pmuludq sequence + split. 368 { ISD::SREM, MVT::v8i32, 16+2 }, // 2*pmuludq+mul+sub sequence + split. 369 { ISD::SDIV, MVT::v4i32, 6 }, // pmuludq sequence 370 { ISD::SREM, MVT::v4i32, 8 }, // pmuludq+mul+sub sequence 371 { ISD::UDIV, MVT::v8i32, 10+2 }, // 2*pmuludq sequence + split. 372 { ISD::UREM, MVT::v8i32, 14+2 }, // 2*pmuludq+mul+sub sequence + split. 373 { ISD::UDIV, MVT::v4i32, 5 }, // pmuludq sequence 374 { ISD::UREM, MVT::v4i32, 7 }, // pmuludq+mul+sub sequence 375 }; 376 377 // XOP has faster vXi8 shifts. 378 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 379 ST->hasSSE2() && !ST->hasXOP()) { 380 if (const auto *Entry = 381 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 382 return LT.first * Entry->Cost; 383 } 384 385 static const CostTblEntry AVX512BWConstCostTable[] = { 386 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 387 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 388 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 389 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 390 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 391 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 392 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 393 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 394 }; 395 396 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 397 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 398 ST->hasBWI()) { 399 if (const auto *Entry = 400 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 401 return LT.first * Entry->Cost; 402 } 403 404 static const CostTblEntry AVX512ConstCostTable[] = { 405 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 406 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 407 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 408 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 409 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 410 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 411 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 412 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 413 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 414 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 415 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 416 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 417 }; 418 419 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 420 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 421 ST->hasAVX512()) { 422 if (const auto *Entry = 423 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 424 return LT.first * Entry->Cost; 425 } 426 427 static const CostTblEntry AVX2ConstCostTable[] = { 428 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 429 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 430 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 431 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 432 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 433 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 434 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 435 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 436 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 437 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 438 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 439 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 440 }; 441 442 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 443 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 444 ST->hasAVX2()) { 445 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 446 return LT.first * Entry->Cost; 447 } 448 449 static const CostTblEntry SSE2ConstCostTable[] = { 450 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 451 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 452 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 453 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 454 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 455 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 456 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 457 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 458 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 459 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 460 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 461 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 462 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 463 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 464 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 465 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 466 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 467 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 468 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 469 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 470 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 471 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 472 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 473 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 474 }; 475 476 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 477 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 478 ST->hasSSE2()) { 479 // pmuldq sequence. 480 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 481 return LT.first * 32; 482 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 483 return LT.first * 38; 484 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 485 return LT.first * 15; 486 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 487 return LT.first * 20; 488 489 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 490 return LT.first * Entry->Cost; 491 } 492 493 static const CostTblEntry AVX512BWShiftCostTable[] = { 494 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 495 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 496 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 497 498 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 499 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 500 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 501 502 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 503 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 504 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 505 }; 506 507 if (ST->hasBWI()) 508 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 509 return LT.first * Entry->Cost; 510 511 static const CostTblEntry AVX2UniformCostTable[] = { 512 // Uniform splats are cheaper for the following instructions. 513 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 514 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 515 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 516 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 517 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 518 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 519 }; 520 521 if (ST->hasAVX2() && 522 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 523 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 524 if (const auto *Entry = 525 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 526 return LT.first * Entry->Cost; 527 } 528 529 static const CostTblEntry SSE2UniformCostTable[] = { 530 // Uniform splats are cheaper for the following instructions. 531 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 532 { ISD::SHL, MVT::v4i32, 1 }, // pslld 533 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 534 535 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 536 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 537 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 538 539 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 540 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 541 }; 542 543 if (ST->hasSSE2() && 544 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 545 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 546 if (const auto *Entry = 547 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 548 return LT.first * Entry->Cost; 549 } 550 551 static const CostTblEntry AVX512DQCostTable[] = { 552 { ISD::MUL, MVT::v2i64, 1 }, 553 { ISD::MUL, MVT::v4i64, 1 }, 554 { ISD::MUL, MVT::v8i64, 1 } 555 }; 556 557 // Look for AVX512DQ lowering tricks for custom cases. 558 if (ST->hasDQI()) 559 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 560 return LT.first * Entry->Cost; 561 562 static const CostTblEntry AVX512BWCostTable[] = { 563 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 564 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 565 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 566 567 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence. 568 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence. 569 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence. 570 }; 571 572 // Look for AVX512BW lowering tricks for custom cases. 573 if (ST->hasBWI()) 574 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 575 return LT.first * Entry->Cost; 576 577 static const CostTblEntry AVX512CostTable[] = { 578 { ISD::SHL, MVT::v16i32, 1 }, 579 { ISD::SRL, MVT::v16i32, 1 }, 580 { ISD::SRA, MVT::v16i32, 1 }, 581 582 { ISD::SHL, MVT::v8i64, 1 }, 583 { ISD::SRL, MVT::v8i64, 1 }, 584 585 { ISD::SRA, MVT::v2i64, 1 }, 586 { ISD::SRA, MVT::v4i64, 1 }, 587 { ISD::SRA, MVT::v8i64, 1 }, 588 589 { ISD::MUL, MVT::v64i8, 26 }, // extend/pmullw/trunc sequence. 590 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence. 591 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence. 592 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 593 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 594 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 595 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add 596 597 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 598 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 599 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 600 601 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 602 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 603 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 604 }; 605 606 if (ST->hasAVX512()) 607 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 608 return LT.first * Entry->Cost; 609 610 static const CostTblEntry AVX2ShiftCostTable[] = { 611 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 612 // customize them to detect the cases where shift amount is a scalar one. 613 { ISD::SHL, MVT::v4i32, 1 }, 614 { ISD::SRL, MVT::v4i32, 1 }, 615 { ISD::SRA, MVT::v4i32, 1 }, 616 { ISD::SHL, MVT::v8i32, 1 }, 617 { ISD::SRL, MVT::v8i32, 1 }, 618 { ISD::SRA, MVT::v8i32, 1 }, 619 { ISD::SHL, MVT::v2i64, 1 }, 620 { ISD::SRL, MVT::v2i64, 1 }, 621 { ISD::SHL, MVT::v4i64, 1 }, 622 { ISD::SRL, MVT::v4i64, 1 }, 623 }; 624 625 if (ST->hasAVX512()) { 626 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 627 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 628 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 629 // On AVX512, a packed v32i16 shift left by a constant build_vector 630 // is lowered into a vector multiply (vpmullw). 631 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 632 Op1Info, Op2Info, 633 TargetTransformInfo::OP_None, 634 TargetTransformInfo::OP_None); 635 } 636 637 // Look for AVX2 lowering tricks. 638 if (ST->hasAVX2()) { 639 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 640 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 641 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 642 // On AVX2, a packed v16i16 shift left by a constant build_vector 643 // is lowered into a vector multiply (vpmullw). 644 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 645 Op1Info, Op2Info, 646 TargetTransformInfo::OP_None, 647 TargetTransformInfo::OP_None); 648 649 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 650 return LT.first * Entry->Cost; 651 } 652 653 static const CostTblEntry XOPShiftCostTable[] = { 654 // 128bit shifts take 1cy, but right shifts require negation beforehand. 655 { ISD::SHL, MVT::v16i8, 1 }, 656 { ISD::SRL, MVT::v16i8, 2 }, 657 { ISD::SRA, MVT::v16i8, 2 }, 658 { ISD::SHL, MVT::v8i16, 1 }, 659 { ISD::SRL, MVT::v8i16, 2 }, 660 { ISD::SRA, MVT::v8i16, 2 }, 661 { ISD::SHL, MVT::v4i32, 1 }, 662 { ISD::SRL, MVT::v4i32, 2 }, 663 { ISD::SRA, MVT::v4i32, 2 }, 664 { ISD::SHL, MVT::v2i64, 1 }, 665 { ISD::SRL, MVT::v2i64, 2 }, 666 { ISD::SRA, MVT::v2i64, 2 }, 667 // 256bit shifts require splitting if AVX2 didn't catch them above. 668 { ISD::SHL, MVT::v32i8, 2+2 }, 669 { ISD::SRL, MVT::v32i8, 4+2 }, 670 { ISD::SRA, MVT::v32i8, 4+2 }, 671 { ISD::SHL, MVT::v16i16, 2+2 }, 672 { ISD::SRL, MVT::v16i16, 4+2 }, 673 { ISD::SRA, MVT::v16i16, 4+2 }, 674 { ISD::SHL, MVT::v8i32, 2+2 }, 675 { ISD::SRL, MVT::v8i32, 4+2 }, 676 { ISD::SRA, MVT::v8i32, 4+2 }, 677 { ISD::SHL, MVT::v4i64, 2+2 }, 678 { ISD::SRL, MVT::v4i64, 4+2 }, 679 { ISD::SRA, MVT::v4i64, 4+2 }, 680 }; 681 682 // Look for XOP lowering tricks. 683 if (ST->hasXOP()) { 684 // If the right shift is constant then we'll fold the negation so 685 // it's as cheap as a left shift. 686 int ShiftISD = ISD; 687 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 688 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 689 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 690 ShiftISD = ISD::SHL; 691 if (const auto *Entry = 692 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 693 return LT.first * Entry->Cost; 694 } 695 696 static const CostTblEntry SSE2UniformShiftCostTable[] = { 697 // Uniform splats are cheaper for the following instructions. 698 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 699 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 700 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 701 702 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 703 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 704 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 705 706 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 707 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 708 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 709 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 710 }; 711 712 if (ST->hasSSE2() && 713 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 714 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 715 716 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 717 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 718 return LT.first * 4; // 2*psrad + shuffle. 719 720 if (const auto *Entry = 721 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 722 return LT.first * Entry->Cost; 723 } 724 725 if (ISD == ISD::SHL && 726 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 727 MVT VT = LT.second; 728 // Vector shift left by non uniform constant can be lowered 729 // into vector multiply. 730 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 731 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 732 ISD = ISD::MUL; 733 } 734 735 static const CostTblEntry AVX2CostTable[] = { 736 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. 737 { ISD::SHL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. 738 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 739 { ISD::SHL, MVT::v32i16, 20 }, // 2*extend/vpsrlvd/pack sequence. 740 741 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. 742 { ISD::SRL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. 743 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 744 { ISD::SRL, MVT::v32i16, 20 }, // 2*extend/vpsrlvd/pack sequence. 745 746 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. 747 { ISD::SRA, MVT::v64i8, 48 }, // 2*vpblendvb sequence. 748 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. 749 { ISD::SRA, MVT::v32i16, 20 }, // 2*extend/vpsravd/pack sequence. 750 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. 751 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 752 753 { ISD::SUB, MVT::v32i8, 1 }, // psubb 754 { ISD::ADD, MVT::v32i8, 1 }, // paddb 755 { ISD::SUB, MVT::v16i16, 1 }, // psubw 756 { ISD::ADD, MVT::v16i16, 1 }, // paddw 757 { ISD::SUB, MVT::v8i32, 1 }, // psubd 758 { ISD::ADD, MVT::v8i32, 1 }, // paddd 759 { ISD::SUB, MVT::v4i64, 1 }, // psubq 760 { ISD::ADD, MVT::v4i64, 1 }, // paddq 761 762 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence. 763 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence. 764 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 765 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 766 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add 767 768 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 769 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 770 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 771 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 772 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 773 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 774 775 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 776 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 777 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 778 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 779 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 780 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 781 }; 782 783 // Look for AVX2 lowering tricks for custom cases. 784 if (ST->hasAVX2()) 785 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 786 return LT.first * Entry->Cost; 787 788 static const CostTblEntry AVX1CostTable[] = { 789 // We don't have to scalarize unsupported ops. We can issue two half-sized 790 // operations and we only need to extract the upper YMM half. 791 // Two ops + 1 extract + 1 insert = 4. 792 { ISD::MUL, MVT::v16i16, 4 }, 793 { ISD::MUL, MVT::v8i32, 4 }, 794 { ISD::SUB, MVT::v32i8, 4 }, 795 { ISD::ADD, MVT::v32i8, 4 }, 796 { ISD::SUB, MVT::v16i16, 4 }, 797 { ISD::ADD, MVT::v16i16, 4 }, 798 { ISD::SUB, MVT::v8i32, 4 }, 799 { ISD::ADD, MVT::v8i32, 4 }, 800 { ISD::SUB, MVT::v4i64, 4 }, 801 { ISD::ADD, MVT::v4i64, 4 }, 802 803 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 804 // are lowered as a series of long multiplies(3), shifts(3) and adds(2) 805 // Because we believe v4i64 to be a legal type, we must also include the 806 // extract+insert in the cost table. Therefore, the cost here is 18 807 // instead of 8. 808 { ISD::MUL, MVT::v4i64, 18 }, 809 810 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence. 811 812 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 813 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 814 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 815 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 816 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 817 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 818 }; 819 820 if (ST->hasAVX()) 821 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 822 return LT.first * Entry->Cost; 823 824 static const CostTblEntry SSE42CostTable[] = { 825 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 826 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 827 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 828 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 829 830 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 831 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 832 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 833 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 834 835 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 836 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 837 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 838 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 839 840 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 841 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 842 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 843 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 844 }; 845 846 if (ST->hasSSE42()) 847 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 848 return LT.first * Entry->Cost; 849 850 static const CostTblEntry SSE41CostTable[] = { 851 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 852 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split. 853 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 854 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 855 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 856 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split 857 858 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 859 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split. 860 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 861 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 862 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 863 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split. 864 865 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 866 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split. 867 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 868 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 869 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 870 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split. 871 872 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 873 }; 874 875 if (ST->hasSSE41()) 876 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 877 return LT.first * Entry->Cost; 878 879 static const CostTblEntry SSE2CostTable[] = { 880 // We don't correctly identify costs of casts because they are marked as 881 // custom. 882 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 883 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 884 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 885 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 886 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 887 888 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 889 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 890 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 891 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 892 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 893 894 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 895 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 896 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 897 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 898 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split. 899 900 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence. 901 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 902 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 903 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 904 905 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 906 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 907 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 908 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 909 910 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 911 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 912 913 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 914 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 915 }; 916 917 if (ST->hasSSE2()) 918 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 919 return LT.first * Entry->Cost; 920 921 static const CostTblEntry SSE1CostTable[] = { 922 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 923 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 924 925 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 926 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 927 928 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 929 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 930 931 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 932 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 933 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 934 935 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 936 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 937 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 938 }; 939 940 if (ST->hasSSE1()) 941 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 942 return LT.first * Entry->Cost; 943 944 // It is not a good idea to vectorize division. We have to scalarize it and 945 // in the process we will often end up having to spilling regular 946 // registers. The overhead of division is going to dominate most kernels 947 // anyways so try hard to prevent vectorization of division - it is 948 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 949 // to hide "20 cycles" for each lane. 950 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 951 ISD == ISD::UDIV || ISD == ISD::UREM)) { 952 int ScalarCost = getArithmeticInstrCost( 953 Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info, 954 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 955 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 956 } 957 958 // Fallback to the default implementation. 959 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info); 960 } 961 962 int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, VectorType *BaseTp, 963 ArrayRef<int> Mask, int Index, 964 VectorType *SubTp) { 965 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 966 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 967 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 968 969 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 970 if (Kind == TTI::SK_Transpose) 971 Kind = TTI::SK_PermuteTwoSrc; 972 973 // For Broadcasts we are splatting the first element from the first input 974 // register, so only need to reference that input and all the output 975 // registers are the same. 976 if (Kind == TTI::SK_Broadcast) 977 LT.first = 1; 978 979 // Subvector extractions are free if they start at the beginning of a 980 // vector and cheap if the subvectors are aligned. 981 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 982 int NumElts = LT.second.getVectorNumElements(); 983 if ((Index % NumElts) == 0) 984 return 0; 985 std::pair<int, MVT> SubLT = TLI->getTypeLegalizationCost(DL, SubTp); 986 if (SubLT.second.isVector()) { 987 int NumSubElts = SubLT.second.getVectorNumElements(); 988 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 989 return SubLT.first; 990 // Handle some cases for widening legalization. For now we only handle 991 // cases where the original subvector was naturally aligned and evenly 992 // fit in its legalized subvector type. 993 // FIXME: Remove some of the alignment restrictions. 994 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 995 // vectors. 996 int OrigSubElts = cast<FixedVectorType>(SubTp)->getNumElements(); 997 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 998 (NumSubElts % OrigSubElts) == 0 && 999 LT.second.getVectorElementType() == 1000 SubLT.second.getVectorElementType() && 1001 LT.second.getVectorElementType().getSizeInBits() == 1002 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 1003 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 1004 "Unexpected number of elements!"); 1005 auto *VecTy = FixedVectorType::get(BaseTp->getElementType(), 1006 LT.second.getVectorNumElements()); 1007 auto *SubTy = FixedVectorType::get(BaseTp->getElementType(), 1008 SubLT.second.getVectorNumElements()); 1009 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 1010 int ExtractCost = getShuffleCost(TTI::SK_ExtractSubvector, VecTy, None, 1011 ExtractIndex, SubTy); 1012 1013 // If the original size is 32-bits or more, we can use pshufd. Otherwise 1014 // if we have SSSE3 we can use pshufb. 1015 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 1016 return ExtractCost + 1; // pshufd or pshufb 1017 1018 assert(SubTp->getPrimitiveSizeInBits() == 16 && 1019 "Unexpected vector size"); 1020 1021 return ExtractCost + 2; // worst case pshufhw + pshufd 1022 } 1023 } 1024 } 1025 1026 // Handle some common (illegal) sub-vector types as they are often very cheap 1027 // to shuffle even on targets without PSHUFB. 1028 EVT VT = TLI->getValueType(DL, BaseTp); 1029 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 1030 !ST->hasSSSE3()) { 1031 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 1032 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 1033 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1034 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1035 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1036 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1037 1038 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1039 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1040 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1041 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1042 1043 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1044 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1045 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1046 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1047 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1048 1049 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1050 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1051 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1052 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1053 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1054 }; 1055 1056 if (ST->hasSSE2()) 1057 if (const auto *Entry = 1058 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1059 return Entry->Cost; 1060 } 1061 1062 // We are going to permute multiple sources and the result will be in multiple 1063 // destinations. Providing an accurate cost only for splits where the element 1064 // type remains the same. 1065 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1066 MVT LegalVT = LT.second; 1067 if (LegalVT.isVector() && 1068 LegalVT.getVectorElementType().getSizeInBits() == 1069 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1070 LegalVT.getVectorNumElements() < 1071 cast<FixedVectorType>(BaseTp)->getNumElements()) { 1072 1073 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1074 unsigned LegalVTSize = LegalVT.getStoreSize(); 1075 // Number of source vectors after legalization: 1076 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1077 // Number of destination vectors after legalization: 1078 unsigned NumOfDests = LT.first; 1079 1080 auto *SingleOpTy = FixedVectorType::get(BaseTp->getElementType(), 1081 LegalVT.getVectorNumElements()); 1082 1083 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1084 return NumOfShuffles * getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 1085 None, 0, nullptr); 1086 } 1087 1088 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1089 } 1090 1091 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1092 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1093 // We assume that source and destination have the same vector type. 1094 int NumOfDests = LT.first; 1095 int NumOfShufflesPerDest = LT.first * 2 - 1; 1096 LT.first = NumOfDests * NumOfShufflesPerDest; 1097 } 1098 1099 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1100 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1101 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1102 1103 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1104 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1105 1106 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b 1107 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b 1108 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2} // vpermt2b 1109 }; 1110 1111 if (ST->hasVBMI()) 1112 if (const auto *Entry = 1113 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1114 return LT.first * Entry->Cost; 1115 1116 static const CostTblEntry AVX512BWShuffleTbl[] = { 1117 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1118 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1119 1120 {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw 1121 {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw 1122 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1123 1124 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw 1125 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw 1126 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1127 1128 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w 1129 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w 1130 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2}, // vpermt2w 1131 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1132 1133 {TTI::SK_Select, MVT::v32i16, 1}, // vblendmw 1134 {TTI::SK_Select, MVT::v64i8, 1}, // vblendmb 1135 }; 1136 1137 if (ST->hasBWI()) 1138 if (const auto *Entry = 1139 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1140 return LT.first * Entry->Cost; 1141 1142 static const CostTblEntry AVX512ShuffleTbl[] = { 1143 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1144 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1145 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1146 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1147 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1148 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1149 1150 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1151 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1152 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1153 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1154 1155 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1156 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1157 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1158 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1159 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1160 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1161 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1162 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1163 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1164 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1165 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1166 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1167 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1168 1169 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1170 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1171 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1172 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1173 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1174 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1175 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1176 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1177 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1178 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1179 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1180 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1181 1182 // FIXME: This just applies the type legalization cost rules above 1183 // assuming these completely split. 1184 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1185 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1186 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1187 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1188 1189 {TTI::SK_Select, MVT::v32i16, 1}, // vpternlogq 1190 {TTI::SK_Select, MVT::v64i8, 1}, // vpternlogq 1191 {TTI::SK_Select, MVT::v8f64, 1}, // vblendmpd 1192 {TTI::SK_Select, MVT::v16f32, 1}, // vblendmps 1193 {TTI::SK_Select, MVT::v8i64, 1}, // vblendmq 1194 {TTI::SK_Select, MVT::v16i32, 1}, // vblendmd 1195 }; 1196 1197 if (ST->hasAVX512()) 1198 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1199 return LT.first * Entry->Cost; 1200 1201 static const CostTblEntry AVX2ShuffleTbl[] = { 1202 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1203 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1204 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1205 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1206 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1207 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1208 1209 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1210 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1211 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1212 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1213 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1214 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1215 1216 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1217 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1218 1219 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1220 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1221 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1222 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1223 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1224 // + vpblendvb 1225 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1226 // + vpblendvb 1227 1228 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1229 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1230 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1231 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1232 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1233 // + vpblendvb 1234 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1235 // + vpblendvb 1236 }; 1237 1238 if (ST->hasAVX2()) 1239 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1240 return LT.first * Entry->Cost; 1241 1242 static const CostTblEntry XOPShuffleTbl[] = { 1243 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1244 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1245 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1246 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1247 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1248 // + vinsertf128 1249 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1250 // + vinsertf128 1251 1252 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1253 // + vinsertf128 1254 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1255 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1256 // + vinsertf128 1257 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1258 }; 1259 1260 if (ST->hasXOP()) 1261 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1262 return LT.first * Entry->Cost; 1263 1264 static const CostTblEntry AVX1ShuffleTbl[] = { 1265 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1266 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1267 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1268 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1269 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1270 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1271 1272 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1273 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1274 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1275 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1276 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1277 // + vinsertf128 1278 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1279 // + vinsertf128 1280 1281 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1282 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1283 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1284 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1285 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1286 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1287 1288 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1289 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1290 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1291 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1292 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1293 // + 2*por + vinsertf128 1294 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1295 // + 2*por + vinsertf128 1296 1297 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1298 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1299 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1300 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1301 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1302 // + 4*por + vinsertf128 1303 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1304 // + 4*por + vinsertf128 1305 }; 1306 1307 if (ST->hasAVX()) 1308 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1309 return LT.first * Entry->Cost; 1310 1311 static const CostTblEntry SSE41ShuffleTbl[] = { 1312 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1313 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1314 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1315 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1316 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1317 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1318 }; 1319 1320 if (ST->hasSSE41()) 1321 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1322 return LT.first * Entry->Cost; 1323 1324 static const CostTblEntry SSSE3ShuffleTbl[] = { 1325 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1326 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1327 1328 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1329 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1330 1331 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1332 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1333 1334 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1335 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1336 1337 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1338 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1339 }; 1340 1341 if (ST->hasSSSE3()) 1342 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1343 return LT.first * Entry->Cost; 1344 1345 static const CostTblEntry SSE2ShuffleTbl[] = { 1346 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1347 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1348 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1349 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1350 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1351 1352 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1353 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1354 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1355 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1356 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1357 // + 2*pshufd + 2*unpck + packus 1358 1359 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1360 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1361 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1362 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1363 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1364 1365 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1366 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1367 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1368 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1369 // + pshufd/unpck 1370 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1371 // + 2*pshufd + 2*unpck + 2*packus 1372 1373 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1374 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1375 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1376 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1377 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1378 }; 1379 1380 if (ST->hasSSE2()) 1381 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1382 return LT.first * Entry->Cost; 1383 1384 static const CostTblEntry SSE1ShuffleTbl[] = { 1385 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1386 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1387 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1388 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1389 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1390 }; 1391 1392 if (ST->hasSSE1()) 1393 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1394 return LT.first * Entry->Cost; 1395 1396 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1397 } 1398 1399 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 1400 TTI::CastContextHint CCH, 1401 TTI::TargetCostKind CostKind, 1402 const Instruction *I) { 1403 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1404 assert(ISD && "Invalid opcode"); 1405 1406 // TODO: Allow non-throughput costs that aren't binary. 1407 auto AdjustCost = [&CostKind](int Cost) { 1408 if (CostKind != TTI::TCK_RecipThroughput) 1409 return Cost == 0 ? 0 : 1; 1410 return Cost; 1411 }; 1412 1413 // FIXME: Need a better design of the cost table to handle non-simple types of 1414 // potential massive combinations (elem_num x src_type x dst_type). 1415 1416 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1417 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1418 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1419 1420 // Mask sign extend has an instruction. 1421 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1422 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1423 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1424 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1425 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1426 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1427 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1428 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1429 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1430 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1431 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1432 1433 // Mask zero extend is a sext + shift. 1434 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1435 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1436 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1437 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1438 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1439 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1440 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1441 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1442 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1443 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1444 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1445 1446 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, 1447 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm 1448 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // widen to zmm 1449 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // widen to zmm 1450 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // widen to zmm 1451 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // widen to zmm 1452 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // widen to zmm 1453 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // widen to zmm 1454 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // widen to zmm 1455 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // widen to zmm 1456 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // widen to zmm 1457 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, 1458 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, 1459 }; 1460 1461 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1462 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1463 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1464 1465 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1466 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1467 1468 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1469 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1470 1471 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1472 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1473 }; 1474 1475 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1476 // 256-bit wide vectors. 1477 1478 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1479 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1480 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1481 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1482 1483 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1484 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1485 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1486 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd 1487 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1488 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1489 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1490 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd 1491 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd 1492 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd 1493 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd 1494 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd 1495 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq 1496 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq 1497 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq 1498 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, 1499 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, 1500 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, 1501 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, 1502 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 1503 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd 1504 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb 1505 1506 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32 1507 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, 1508 1509 // Sign extend is zmm vpternlogd+vptruncdb. 1510 // Zero extend is zmm broadcast load+vptruncdw. 1511 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 }, 1512 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 }, 1513 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, 1514 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, 1515 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, 1516 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, 1517 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 }, 1518 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 }, 1519 1520 // Sign extend is zmm vpternlogd+vptruncdw. 1521 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw. 1522 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 }, 1523 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1524 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 }, 1525 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1526 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 }, 1527 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1528 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 }, 1529 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1530 1531 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd 1532 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld 1533 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd 1534 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld 1535 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd 1536 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld 1537 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq 1538 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq 1539 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq 1540 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq 1541 1542 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd 1543 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld 1544 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq 1545 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq 1546 1547 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1548 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1549 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1550 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1551 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1552 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1553 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1554 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1555 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1556 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1557 1558 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1559 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1560 1561 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1562 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1563 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1564 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1565 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1566 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1567 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1568 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1569 1570 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1571 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1572 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1573 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1574 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1575 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1576 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1577 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1578 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1579 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1580 1581 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f64, 3 }, 1582 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, 1583 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 3 }, 1584 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 3 }, 1585 1586 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1587 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, 1588 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, 1589 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1590 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, 1591 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, 1592 }; 1593 1594 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1595 // Mask sign extend has an instruction. 1596 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1597 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1598 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1599 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1600 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1601 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1602 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1603 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1604 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1605 1606 // Mask zero extend is a sext + shift. 1607 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1608 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1609 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1610 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1611 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1612 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1613 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1614 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1615 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1616 1617 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, 1618 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // vpsllw+vptestmb 1619 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // vpsllw+vptestmw 1620 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // vpsllw+vptestmb 1621 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // vpsllw+vptestmw 1622 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // vpsllw+vptestmb 1623 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // vpsllw+vptestmw 1624 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // vpsllw+vptestmb 1625 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // vpsllw+vptestmw 1626 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // vpsllw+vptestmb 1627 }; 1628 1629 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1630 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1631 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1632 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1633 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1634 1635 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1636 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1637 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1638 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1639 1640 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1641 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1642 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1643 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1644 1645 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1646 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1647 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1648 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1649 }; 1650 1651 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 1652 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1653 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1654 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1655 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 8 }, // split+2*v8i8 1656 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1657 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1658 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1659 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16 1660 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // vpslld+vptestmd 1661 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd 1662 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // vpslld+vptestmd 1663 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // vpsllq+vptestmq 1664 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // vpsllq+vptestmq 1665 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // vpmovqd 1666 1667 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb 1668 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb 1669 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 }, 1670 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 }, 1671 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 }, 1672 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 }, 1673 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 }, 1674 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 }, 1675 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 }, 1676 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 }, 1677 1678 // sign extend is vpcmpeq+maskedmove+vpmovdw 1679 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw 1680 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1681 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 }, 1682 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1683 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 }, 1684 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1685 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 }, 1686 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 }, 1687 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 }, 1688 1689 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd 1690 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld 1691 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd 1692 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld 1693 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd 1694 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld 1695 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq 1696 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq 1697 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq 1698 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq 1699 1700 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1701 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1702 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1703 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1704 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1705 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1706 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1707 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1708 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1709 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1710 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1711 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1712 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1713 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1714 1715 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 1716 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1717 1718 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 3 }, 1719 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 3 }, 1720 1721 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 1722 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 1723 1724 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1725 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1726 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 1 }, 1727 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1728 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1729 }; 1730 1731 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1732 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1733 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1734 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1735 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1736 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1737 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1738 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1739 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1740 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1741 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1742 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1743 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1744 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1745 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1746 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1747 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1748 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1749 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1750 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1751 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1752 1753 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1754 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1755 1756 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 1757 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 1758 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 1759 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1760 1761 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1762 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1763 1764 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1765 }; 1766 1767 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1768 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1769 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1770 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1771 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1772 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1773 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1774 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1775 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1776 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1777 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1778 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1779 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1780 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 4 }, 1781 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1782 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1783 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1784 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1785 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1786 1787 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 4 }, 1788 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 5 }, 1789 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 4 }, 1790 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 9 }, 1791 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, 11 }, 1792 1793 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 1794 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1795 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1796 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1797 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 1798 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1799 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 11 }, 1800 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 9 }, 1801 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 }, 1802 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 11 }, 1803 1804 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1805 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1806 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1807 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1808 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1809 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1810 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1811 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1812 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1813 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1814 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1815 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1816 1817 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1818 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1819 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1820 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1821 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1822 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1823 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1824 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1825 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1826 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 }, 1827 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 1828 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1829 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 1830 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1831 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1832 // The generic code to compute the scalar overhead is currently broken. 1833 // Workaround this limitation by estimating the scalarization overhead 1834 // here. We have roughly 10 instructions per scalar element. 1835 // Multiply that by the vector width. 1836 // FIXME: remove that when PR19268 is fixed. 1837 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1838 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1839 1840 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 4 }, 1841 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f64, 3 }, 1842 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f64, 2 }, 1843 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 3 }, 1844 1845 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f64, 3 }, 1846 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f64, 2 }, 1847 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 4 }, 1848 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 3 }, 1849 // This node is expanded into scalarized operations but BasicTTI is overly 1850 // optimistic estimating its cost. It computes 3 per element (one 1851 // vector-extract, one scalar conversion and one vector-insert). The 1852 // problem is that the inserts form a read-modify-write chain so latency 1853 // should be factored in too. Inflating the cost per element by 1. 1854 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, 1855 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 1856 1857 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 1858 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 1859 }; 1860 1861 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 1862 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1863 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1864 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1865 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1866 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1867 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1868 1869 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1870 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 }, 1871 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1872 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1873 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1874 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1875 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1876 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1877 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1878 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1879 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1880 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1881 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1882 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1883 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1884 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1885 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1886 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1887 1888 // These truncates end up widening elements. 1889 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 1 }, // PMOVXZBQ 1890 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 1 }, // PMOVXZWQ 1891 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 1 }, // PMOVXZBD 1892 1893 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 1 }, 1894 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 1 }, 1895 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 1896 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 1897 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 1898 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 1899 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 1900 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 1901 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 1 }, // PSHUFB 1902 1903 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 1904 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 1905 1906 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 3 }, 1907 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 3 }, 1908 1909 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 3 }, 1910 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 3 }, 1911 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, 1912 }; 1913 1914 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 1915 // These are somewhat magic numbers justified by looking at the output of 1916 // Intel's IACA, running some kernels and making sure when we take 1917 // legalization into account the throughput will be overestimated. 1918 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1919 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1920 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1921 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1922 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1923 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 2*10 }, 1924 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2*10 }, 1925 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1926 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 1927 1928 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1929 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1930 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1931 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1932 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1933 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, 1934 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 }, 1935 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1936 1937 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 4 }, 1938 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 2 }, 1939 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, 1940 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, 1941 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, 1942 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 4 }, 1943 1944 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 1 }, 1945 1946 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 6 }, 1947 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 }, 1948 1949 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 1950 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 1951 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 4 }, 1952 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 4 }, 1953 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 }, 1954 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 2 }, 1955 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 }, 1956 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 4 }, 1957 1958 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1959 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 1960 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 1961 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 1962 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1963 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 1964 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1965 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 1966 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1967 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1968 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1969 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1970 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 1971 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 1972 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1973 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 1974 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1975 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 1976 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1977 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1978 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 1979 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 1980 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1981 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 1982 1983 // These truncates are really widening elements. 1984 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 1 }, // PSHUFD 1985 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // PUNPCKLWD+DQ 1986 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // PUNPCKLBW+WD+PSHUFD 1987 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 1 }, // PUNPCKLWD 1988 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // PUNPCKLBW+WD 1989 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 1 }, // PUNPCKLBW 1990 1991 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // PAND+PACKUSWB 1992 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // PAND+PACKUSWB 1993 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // PAND+PACKUSWB 1994 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 1995 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 3 }, // PAND+2*PACKUSWB 1996 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 1997 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 1998 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 1999 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 2000 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 2001 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2002 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 2003 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 2004 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 2005 { ISD::TRUNCATE, MVT::v2i32, MVT::v2i64, 1 }, // PSHUFD 2006 }; 2007 2008 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 2009 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst); 2010 2011 if (ST->hasSSE2() && !ST->hasAVX()) { 2012 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2013 LTDest.second, LTSrc.second)) 2014 return AdjustCost(LTSrc.first * Entry->Cost); 2015 } 2016 2017 EVT SrcTy = TLI->getValueType(DL, Src); 2018 EVT DstTy = TLI->getValueType(DL, Dst); 2019 2020 // The function getSimpleVT only handles simple value types. 2021 if (!SrcTy.isSimple() || !DstTy.isSimple()) 2022 return AdjustCost(BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind)); 2023 2024 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 2025 MVT SimpleDstTy = DstTy.getSimpleVT(); 2026 2027 if (ST->useAVX512Regs()) { 2028 if (ST->hasBWI()) 2029 if (const auto *Entry = ConvertCostTableLookup(AVX512BWConversionTbl, ISD, 2030 SimpleDstTy, SimpleSrcTy)) 2031 return AdjustCost(Entry->Cost); 2032 2033 if (ST->hasDQI()) 2034 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 2035 SimpleDstTy, SimpleSrcTy)) 2036 return AdjustCost(Entry->Cost); 2037 2038 if (ST->hasAVX512()) 2039 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 2040 SimpleDstTy, SimpleSrcTy)) 2041 return AdjustCost(Entry->Cost); 2042 } 2043 2044 if (ST->hasBWI()) 2045 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 2046 SimpleDstTy, SimpleSrcTy)) 2047 return AdjustCost(Entry->Cost); 2048 2049 if (ST->hasDQI()) 2050 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 2051 SimpleDstTy, SimpleSrcTy)) 2052 return AdjustCost(Entry->Cost); 2053 2054 if (ST->hasAVX512()) 2055 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2056 SimpleDstTy, SimpleSrcTy)) 2057 return AdjustCost(Entry->Cost); 2058 2059 if (ST->hasAVX2()) { 2060 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2061 SimpleDstTy, SimpleSrcTy)) 2062 return AdjustCost(Entry->Cost); 2063 } 2064 2065 if (ST->hasAVX()) { 2066 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2067 SimpleDstTy, SimpleSrcTy)) 2068 return AdjustCost(Entry->Cost); 2069 } 2070 2071 if (ST->hasSSE41()) { 2072 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2073 SimpleDstTy, SimpleSrcTy)) 2074 return AdjustCost(Entry->Cost); 2075 } 2076 2077 if (ST->hasSSE2()) { 2078 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2079 SimpleDstTy, SimpleSrcTy)) 2080 return AdjustCost(Entry->Cost); 2081 } 2082 2083 return AdjustCost( 2084 BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I)); 2085 } 2086 2087 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 2088 CmpInst::Predicate VecPred, 2089 TTI::TargetCostKind CostKind, 2090 const Instruction *I) { 2091 // TODO: Handle other cost kinds. 2092 if (CostKind != TTI::TCK_RecipThroughput) 2093 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, 2094 I); 2095 2096 // Legalize the type. 2097 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2098 2099 MVT MTy = LT.second; 2100 2101 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2102 assert(ISD && "Invalid opcode"); 2103 2104 unsigned ExtraCost = 0; 2105 if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) { 2106 // Some vector comparison predicates cost extra instructions. 2107 if (MTy.isVector() && 2108 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 2109 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 2110 ST->hasBWI())) { 2111 switch (cast<CmpInst>(I)->getPredicate()) { 2112 case CmpInst::Predicate::ICMP_NE: 2113 // xor(cmpeq(x,y),-1) 2114 ExtraCost = 1; 2115 break; 2116 case CmpInst::Predicate::ICMP_SGE: 2117 case CmpInst::Predicate::ICMP_SLE: 2118 // xor(cmpgt(x,y),-1) 2119 ExtraCost = 1; 2120 break; 2121 case CmpInst::Predicate::ICMP_ULT: 2122 case CmpInst::Predicate::ICMP_UGT: 2123 // cmpgt(xor(x,signbit),xor(y,signbit)) 2124 // xor(cmpeq(pmaxu(x,y),x),-1) 2125 ExtraCost = 2; 2126 break; 2127 case CmpInst::Predicate::ICMP_ULE: 2128 case CmpInst::Predicate::ICMP_UGE: 2129 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 2130 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 2131 // cmpeq(psubus(x,y),0) 2132 // cmpeq(pminu(x,y),x) 2133 ExtraCost = 1; 2134 } else { 2135 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 2136 ExtraCost = 3; 2137 } 2138 break; 2139 default: 2140 break; 2141 } 2142 } 2143 } 2144 2145 static const CostTblEntry SLMCostTbl[] = { 2146 // slm pcmpeq/pcmpgt throughput is 2 2147 { ISD::SETCC, MVT::v2i64, 2 }, 2148 }; 2149 2150 static const CostTblEntry AVX512BWCostTbl[] = { 2151 { ISD::SETCC, MVT::v32i16, 1 }, 2152 { ISD::SETCC, MVT::v64i8, 1 }, 2153 2154 { ISD::SELECT, MVT::v32i16, 1 }, 2155 { ISD::SELECT, MVT::v64i8, 1 }, 2156 }; 2157 2158 static const CostTblEntry AVX512CostTbl[] = { 2159 { ISD::SETCC, MVT::v8i64, 1 }, 2160 { ISD::SETCC, MVT::v16i32, 1 }, 2161 { ISD::SETCC, MVT::v8f64, 1 }, 2162 { ISD::SETCC, MVT::v16f32, 1 }, 2163 2164 { ISD::SELECT, MVT::v8i64, 1 }, 2165 { ISD::SELECT, MVT::v16i32, 1 }, 2166 { ISD::SELECT, MVT::v8f64, 1 }, 2167 { ISD::SELECT, MVT::v16f32, 1 }, 2168 2169 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 2170 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 2171 2172 { ISD::SELECT, MVT::v32i16, 2 }, // FIXME: should be 3 2173 { ISD::SELECT, MVT::v64i8, 2 }, // FIXME: should be 3 2174 }; 2175 2176 static const CostTblEntry AVX2CostTbl[] = { 2177 { ISD::SETCC, MVT::v4i64, 1 }, 2178 { ISD::SETCC, MVT::v8i32, 1 }, 2179 { ISD::SETCC, MVT::v16i16, 1 }, 2180 { ISD::SETCC, MVT::v32i8, 1 }, 2181 2182 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 2183 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 2184 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 2185 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 2186 }; 2187 2188 static const CostTblEntry AVX1CostTbl[] = { 2189 { ISD::SETCC, MVT::v4f64, 1 }, 2190 { ISD::SETCC, MVT::v8f32, 1 }, 2191 // AVX1 does not support 8-wide integer compare. 2192 { ISD::SETCC, MVT::v4i64, 4 }, 2193 { ISD::SETCC, MVT::v8i32, 4 }, 2194 { ISD::SETCC, MVT::v16i16, 4 }, 2195 { ISD::SETCC, MVT::v32i8, 4 }, 2196 2197 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 2198 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 2199 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 2200 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 2201 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 2202 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 2203 }; 2204 2205 static const CostTblEntry SSE42CostTbl[] = { 2206 { ISD::SETCC, MVT::v2f64, 1 }, 2207 { ISD::SETCC, MVT::v4f32, 1 }, 2208 { ISD::SETCC, MVT::v2i64, 1 }, 2209 }; 2210 2211 static const CostTblEntry SSE41CostTbl[] = { 2212 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 2213 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 2214 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 2215 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 2216 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 2217 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 2218 }; 2219 2220 static const CostTblEntry SSE2CostTbl[] = { 2221 { ISD::SETCC, MVT::v2f64, 2 }, 2222 { ISD::SETCC, MVT::f64, 1 }, 2223 { ISD::SETCC, MVT::v2i64, 8 }, 2224 { ISD::SETCC, MVT::v4i32, 1 }, 2225 { ISD::SETCC, MVT::v8i16, 1 }, 2226 { ISD::SETCC, MVT::v16i8, 1 }, 2227 2228 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 2229 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 2230 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 2231 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 2232 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 2233 }; 2234 2235 static const CostTblEntry SSE1CostTbl[] = { 2236 { ISD::SETCC, MVT::v4f32, 2 }, 2237 { ISD::SETCC, MVT::f32, 1 }, 2238 2239 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 2240 }; 2241 2242 if (ST->isSLM()) 2243 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2244 return LT.first * (ExtraCost + Entry->Cost); 2245 2246 if (ST->hasBWI()) 2247 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2248 return LT.first * (ExtraCost + Entry->Cost); 2249 2250 if (ST->hasAVX512()) 2251 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2252 return LT.first * (ExtraCost + Entry->Cost); 2253 2254 if (ST->hasAVX2()) 2255 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2256 return LT.first * (ExtraCost + Entry->Cost); 2257 2258 if (ST->hasAVX()) 2259 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2260 return LT.first * (ExtraCost + Entry->Cost); 2261 2262 if (ST->hasSSE42()) 2263 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2264 return LT.first * (ExtraCost + Entry->Cost); 2265 2266 if (ST->hasSSE41()) 2267 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2268 return LT.first * (ExtraCost + Entry->Cost); 2269 2270 if (ST->hasSSE2()) 2271 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2272 return LT.first * (ExtraCost + Entry->Cost); 2273 2274 if (ST->hasSSE1()) 2275 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2276 return LT.first * (ExtraCost + Entry->Cost); 2277 2278 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I); 2279 } 2280 2281 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2282 2283 int X86TTIImpl::getTypeBasedIntrinsicInstrCost( 2284 const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) { 2285 2286 // Costs should match the codegen from: 2287 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2288 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2289 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2290 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2291 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2292 2293 // TODO: Overflow intrinsics (*ADDO, *SUBO, *MULO) with vector types are not 2294 // specialized in these tables yet. 2295 static const CostTblEntry AVX512CDCostTbl[] = { 2296 { ISD::CTLZ, MVT::v8i64, 1 }, 2297 { ISD::CTLZ, MVT::v16i32, 1 }, 2298 { ISD::CTLZ, MVT::v32i16, 8 }, 2299 { ISD::CTLZ, MVT::v64i8, 20 }, 2300 { ISD::CTLZ, MVT::v4i64, 1 }, 2301 { ISD::CTLZ, MVT::v8i32, 1 }, 2302 { ISD::CTLZ, MVT::v16i16, 4 }, 2303 { ISD::CTLZ, MVT::v32i8, 10 }, 2304 { ISD::CTLZ, MVT::v2i64, 1 }, 2305 { ISD::CTLZ, MVT::v4i32, 1 }, 2306 { ISD::CTLZ, MVT::v8i16, 4 }, 2307 { ISD::CTLZ, MVT::v16i8, 4 }, 2308 }; 2309 static const CostTblEntry AVX512BWCostTbl[] = { 2310 { ISD::ABS, MVT::v32i16, 1 }, 2311 { ISD::ABS, MVT::v64i8, 1 }, 2312 { ISD::BITREVERSE, MVT::v8i64, 5 }, 2313 { ISD::BITREVERSE, MVT::v16i32, 5 }, 2314 { ISD::BITREVERSE, MVT::v32i16, 5 }, 2315 { ISD::BITREVERSE, MVT::v64i8, 5 }, 2316 { ISD::CTLZ, MVT::v8i64, 23 }, 2317 { ISD::CTLZ, MVT::v16i32, 22 }, 2318 { ISD::CTLZ, MVT::v32i16, 18 }, 2319 { ISD::CTLZ, MVT::v64i8, 17 }, 2320 { ISD::CTPOP, MVT::v8i64, 7 }, 2321 { ISD::CTPOP, MVT::v16i32, 11 }, 2322 { ISD::CTPOP, MVT::v32i16, 9 }, 2323 { ISD::CTPOP, MVT::v64i8, 6 }, 2324 { ISD::CTTZ, MVT::v8i64, 10 }, 2325 { ISD::CTTZ, MVT::v16i32, 14 }, 2326 { ISD::CTTZ, MVT::v32i16, 12 }, 2327 { ISD::CTTZ, MVT::v64i8, 9 }, 2328 { ISD::SADDSAT, MVT::v32i16, 1 }, 2329 { ISD::SADDSAT, MVT::v64i8, 1 }, 2330 { ISD::SMAX, MVT::v32i16, 1 }, 2331 { ISD::SMAX, MVT::v64i8, 1 }, 2332 { ISD::SMIN, MVT::v32i16, 1 }, 2333 { ISD::SMIN, MVT::v64i8, 1 }, 2334 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2335 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2336 { ISD::UADDSAT, MVT::v32i16, 1 }, 2337 { ISD::UADDSAT, MVT::v64i8, 1 }, 2338 { ISD::UMAX, MVT::v32i16, 1 }, 2339 { ISD::UMAX, MVT::v64i8, 1 }, 2340 { ISD::UMIN, MVT::v32i16, 1 }, 2341 { ISD::UMIN, MVT::v64i8, 1 }, 2342 { ISD::USUBSAT, MVT::v32i16, 1 }, 2343 { ISD::USUBSAT, MVT::v64i8, 1 }, 2344 }; 2345 static const CostTblEntry AVX512CostTbl[] = { 2346 { ISD::ABS, MVT::v8i64, 1 }, 2347 { ISD::ABS, MVT::v16i32, 1 }, 2348 { ISD::ABS, MVT::v32i16, 2 }, // FIXME: include split 2349 { ISD::ABS, MVT::v64i8, 2 }, // FIXME: include split 2350 { ISD::ABS, MVT::v4i64, 1 }, 2351 { ISD::ABS, MVT::v2i64, 1 }, 2352 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2353 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2354 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2355 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2356 { ISD::CTLZ, MVT::v8i64, 29 }, 2357 { ISD::CTLZ, MVT::v16i32, 35 }, 2358 { ISD::CTLZ, MVT::v32i16, 28 }, 2359 { ISD::CTLZ, MVT::v64i8, 18 }, 2360 { ISD::CTPOP, MVT::v8i64, 16 }, 2361 { ISD::CTPOP, MVT::v16i32, 24 }, 2362 { ISD::CTPOP, MVT::v32i16, 18 }, 2363 { ISD::CTPOP, MVT::v64i8, 12 }, 2364 { ISD::CTTZ, MVT::v8i64, 20 }, 2365 { ISD::CTTZ, MVT::v16i32, 28 }, 2366 { ISD::CTTZ, MVT::v32i16, 24 }, 2367 { ISD::CTTZ, MVT::v64i8, 18 }, 2368 { ISD::SMAX, MVT::v8i64, 1 }, 2369 { ISD::SMAX, MVT::v16i32, 1 }, 2370 { ISD::SMAX, MVT::v32i16, 2 }, // FIXME: include split 2371 { ISD::SMAX, MVT::v64i8, 2 }, // FIXME: include split 2372 { ISD::SMAX, MVT::v4i64, 1 }, 2373 { ISD::SMAX, MVT::v2i64, 1 }, 2374 { ISD::SMIN, MVT::v8i64, 1 }, 2375 { ISD::SMIN, MVT::v16i32, 1 }, 2376 { ISD::SMIN, MVT::v32i16, 2 }, // FIXME: include split 2377 { ISD::SMIN, MVT::v64i8, 2 }, // FIXME: include split 2378 { ISD::SMIN, MVT::v4i64, 1 }, 2379 { ISD::SMIN, MVT::v2i64, 1 }, 2380 { ISD::UMAX, MVT::v8i64, 1 }, 2381 { ISD::UMAX, MVT::v16i32, 1 }, 2382 { ISD::UMAX, MVT::v32i16, 2 }, // FIXME: include split 2383 { ISD::UMAX, MVT::v64i8, 2 }, // FIXME: include split 2384 { ISD::UMAX, MVT::v4i64, 1 }, 2385 { ISD::UMAX, MVT::v2i64, 1 }, 2386 { ISD::UMIN, MVT::v8i64, 1 }, 2387 { ISD::UMIN, MVT::v16i32, 1 }, 2388 { ISD::UMIN, MVT::v32i16, 2 }, // FIXME: include split 2389 { ISD::UMIN, MVT::v64i8, 2 }, // FIXME: include split 2390 { ISD::UMIN, MVT::v4i64, 1 }, 2391 { ISD::UMIN, MVT::v2i64, 1 }, 2392 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2393 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2394 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2395 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2396 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2397 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2398 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2399 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2400 { ISD::SADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2401 { ISD::SADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2402 { ISD::SSUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2403 { ISD::SSUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2404 { ISD::UADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2405 { ISD::UADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2406 { ISD::USUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2407 { ISD::USUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2408 { ISD::FMAXNUM, MVT::f32, 2 }, 2409 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2410 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2411 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2412 { ISD::FMAXNUM, MVT::f64, 2 }, 2413 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2414 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2415 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2416 }; 2417 static const CostTblEntry XOPCostTbl[] = { 2418 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2419 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2420 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2421 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2422 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2423 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2424 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2425 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2426 { ISD::BITREVERSE, MVT::i64, 3 }, 2427 { ISD::BITREVERSE, MVT::i32, 3 }, 2428 { ISD::BITREVERSE, MVT::i16, 3 }, 2429 { ISD::BITREVERSE, MVT::i8, 3 } 2430 }; 2431 static const CostTblEntry AVX2CostTbl[] = { 2432 { ISD::ABS, MVT::v4i64, 2 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2433 { ISD::ABS, MVT::v8i32, 1 }, 2434 { ISD::ABS, MVT::v16i16, 1 }, 2435 { ISD::ABS, MVT::v32i8, 1 }, 2436 { ISD::BITREVERSE, MVT::v4i64, 5 }, 2437 { ISD::BITREVERSE, MVT::v8i32, 5 }, 2438 { ISD::BITREVERSE, MVT::v16i16, 5 }, 2439 { ISD::BITREVERSE, MVT::v32i8, 5 }, 2440 { ISD::BSWAP, MVT::v4i64, 1 }, 2441 { ISD::BSWAP, MVT::v8i32, 1 }, 2442 { ISD::BSWAP, MVT::v16i16, 1 }, 2443 { ISD::CTLZ, MVT::v4i64, 23 }, 2444 { ISD::CTLZ, MVT::v8i32, 18 }, 2445 { ISD::CTLZ, MVT::v16i16, 14 }, 2446 { ISD::CTLZ, MVT::v32i8, 9 }, 2447 { ISD::CTPOP, MVT::v4i64, 7 }, 2448 { ISD::CTPOP, MVT::v8i32, 11 }, 2449 { ISD::CTPOP, MVT::v16i16, 9 }, 2450 { ISD::CTPOP, MVT::v32i8, 6 }, 2451 { ISD::CTTZ, MVT::v4i64, 10 }, 2452 { ISD::CTTZ, MVT::v8i32, 14 }, 2453 { ISD::CTTZ, MVT::v16i16, 12 }, 2454 { ISD::CTTZ, MVT::v32i8, 9 }, 2455 { ISD::SADDSAT, MVT::v16i16, 1 }, 2456 { ISD::SADDSAT, MVT::v32i8, 1 }, 2457 { ISD::SMAX, MVT::v8i32, 1 }, 2458 { ISD::SMAX, MVT::v16i16, 1 }, 2459 { ISD::SMAX, MVT::v32i8, 1 }, 2460 { ISD::SMIN, MVT::v8i32, 1 }, 2461 { ISD::SMIN, MVT::v16i16, 1 }, 2462 { ISD::SMIN, MVT::v32i8, 1 }, 2463 { ISD::SSUBSAT, MVT::v16i16, 1 }, 2464 { ISD::SSUBSAT, MVT::v32i8, 1 }, 2465 { ISD::UADDSAT, MVT::v16i16, 1 }, 2466 { ISD::UADDSAT, MVT::v32i8, 1 }, 2467 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 2468 { ISD::UMAX, MVT::v8i32, 1 }, 2469 { ISD::UMAX, MVT::v16i16, 1 }, 2470 { ISD::UMAX, MVT::v32i8, 1 }, 2471 { ISD::UMIN, MVT::v8i32, 1 }, 2472 { ISD::UMIN, MVT::v16i16, 1 }, 2473 { ISD::UMIN, MVT::v32i8, 1 }, 2474 { ISD::USUBSAT, MVT::v16i16, 1 }, 2475 { ISD::USUBSAT, MVT::v32i8, 1 }, 2476 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2477 { ISD::FMAXNUM, MVT::v8f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2478 { ISD::FMAXNUM, MVT::v4f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2479 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2480 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2481 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2482 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2483 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2484 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2485 }; 2486 static const CostTblEntry AVX1CostTbl[] = { 2487 { ISD::ABS, MVT::v4i64, 5 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2488 { ISD::ABS, MVT::v8i32, 3 }, 2489 { ISD::ABS, MVT::v16i16, 3 }, 2490 { ISD::ABS, MVT::v32i8, 3 }, 2491 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 2492 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 2493 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 2494 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 2495 { ISD::BSWAP, MVT::v4i64, 4 }, 2496 { ISD::BSWAP, MVT::v8i32, 4 }, 2497 { ISD::BSWAP, MVT::v16i16, 4 }, 2498 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 2499 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 2500 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 2501 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2502 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 2503 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 2504 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 2505 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 2506 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 2507 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 2508 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 2509 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2510 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2511 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2512 { ISD::SMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2513 { ISD::SMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2514 { ISD::SMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2515 { ISD::SMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2516 { ISD::SMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2517 { ISD::SMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2518 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2519 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2520 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2521 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2522 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 2523 { ISD::UMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2524 { ISD::UMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2525 { ISD::UMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2526 { ISD::UMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2527 { ISD::UMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2528 { ISD::UMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2529 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2530 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2531 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 2532 { ISD::FMAXNUM, MVT::f32, 3 }, // MAXSS + CMPUNORDSS + BLENDVPS 2533 { ISD::FMAXNUM, MVT::v4f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2534 { ISD::FMAXNUM, MVT::v8f32, 5 }, // MAXPS + CMPUNORDPS + BLENDVPS + ? 2535 { ISD::FMAXNUM, MVT::f64, 3 }, // MAXSD + CMPUNORDSD + BLENDVPD 2536 { ISD::FMAXNUM, MVT::v2f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2537 { ISD::FMAXNUM, MVT::v4f64, 5 }, // MAXPD + CMPUNORDPD + BLENDVPD + ? 2538 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 2539 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 2540 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 2541 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 2542 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 2543 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 2544 }; 2545 static const CostTblEntry GLMCostTbl[] = { 2546 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 2547 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 2548 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 2549 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 2550 }; 2551 static const CostTblEntry SLMCostTbl[] = { 2552 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 2553 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 2554 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 2555 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 2556 }; 2557 static const CostTblEntry SSE42CostTbl[] = { 2558 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 2559 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 2560 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 2561 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 2562 }; 2563 static const CostTblEntry SSE41CostTbl[] = { 2564 { ISD::ABS, MVT::v2i64, 2 }, // BLENDVPD(X,PSUBQ(0,X),X) 2565 { ISD::SMAX, MVT::v4i32, 1 }, 2566 { ISD::SMAX, MVT::v16i8, 1 }, 2567 { ISD::SMIN, MVT::v4i32, 1 }, 2568 { ISD::SMIN, MVT::v16i8, 1 }, 2569 { ISD::UMAX, MVT::v4i32, 1 }, 2570 { ISD::UMAX, MVT::v8i16, 1 }, 2571 { ISD::UMIN, MVT::v4i32, 1 }, 2572 { ISD::UMIN, MVT::v8i16, 1 }, 2573 }; 2574 static const CostTblEntry SSSE3CostTbl[] = { 2575 { ISD::ABS, MVT::v4i32, 1 }, 2576 { ISD::ABS, MVT::v8i16, 1 }, 2577 { ISD::ABS, MVT::v16i8, 1 }, 2578 { ISD::BITREVERSE, MVT::v2i64, 5 }, 2579 { ISD::BITREVERSE, MVT::v4i32, 5 }, 2580 { ISD::BITREVERSE, MVT::v8i16, 5 }, 2581 { ISD::BITREVERSE, MVT::v16i8, 5 }, 2582 { ISD::BSWAP, MVT::v2i64, 1 }, 2583 { ISD::BSWAP, MVT::v4i32, 1 }, 2584 { ISD::BSWAP, MVT::v8i16, 1 }, 2585 { ISD::CTLZ, MVT::v2i64, 23 }, 2586 { ISD::CTLZ, MVT::v4i32, 18 }, 2587 { ISD::CTLZ, MVT::v8i16, 14 }, 2588 { ISD::CTLZ, MVT::v16i8, 9 }, 2589 { ISD::CTPOP, MVT::v2i64, 7 }, 2590 { ISD::CTPOP, MVT::v4i32, 11 }, 2591 { ISD::CTPOP, MVT::v8i16, 9 }, 2592 { ISD::CTPOP, MVT::v16i8, 6 }, 2593 { ISD::CTTZ, MVT::v2i64, 10 }, 2594 { ISD::CTTZ, MVT::v4i32, 14 }, 2595 { ISD::CTTZ, MVT::v8i16, 12 }, 2596 { ISD::CTTZ, MVT::v16i8, 9 } 2597 }; 2598 static const CostTblEntry SSE2CostTbl[] = { 2599 { ISD::ABS, MVT::v2i64, 4 }, 2600 { ISD::ABS, MVT::v4i32, 3 }, 2601 { ISD::ABS, MVT::v8i16, 2 }, 2602 { ISD::ABS, MVT::v16i8, 2 }, 2603 { ISD::BITREVERSE, MVT::v2i64, 29 }, 2604 { ISD::BITREVERSE, MVT::v4i32, 27 }, 2605 { ISD::BITREVERSE, MVT::v8i16, 27 }, 2606 { ISD::BITREVERSE, MVT::v16i8, 20 }, 2607 { ISD::BSWAP, MVT::v2i64, 7 }, 2608 { ISD::BSWAP, MVT::v4i32, 7 }, 2609 { ISD::BSWAP, MVT::v8i16, 7 }, 2610 { ISD::CTLZ, MVT::v2i64, 25 }, 2611 { ISD::CTLZ, MVT::v4i32, 26 }, 2612 { ISD::CTLZ, MVT::v8i16, 20 }, 2613 { ISD::CTLZ, MVT::v16i8, 17 }, 2614 { ISD::CTPOP, MVT::v2i64, 12 }, 2615 { ISD::CTPOP, MVT::v4i32, 15 }, 2616 { ISD::CTPOP, MVT::v8i16, 13 }, 2617 { ISD::CTPOP, MVT::v16i8, 10 }, 2618 { ISD::CTTZ, MVT::v2i64, 14 }, 2619 { ISD::CTTZ, MVT::v4i32, 18 }, 2620 { ISD::CTTZ, MVT::v8i16, 16 }, 2621 { ISD::CTTZ, MVT::v16i8, 13 }, 2622 { ISD::SADDSAT, MVT::v8i16, 1 }, 2623 { ISD::SADDSAT, MVT::v16i8, 1 }, 2624 { ISD::SMAX, MVT::v8i16, 1 }, 2625 { ISD::SMIN, MVT::v8i16, 1 }, 2626 { ISD::SSUBSAT, MVT::v8i16, 1 }, 2627 { ISD::SSUBSAT, MVT::v16i8, 1 }, 2628 { ISD::UADDSAT, MVT::v8i16, 1 }, 2629 { ISD::UADDSAT, MVT::v16i8, 1 }, 2630 { ISD::UMAX, MVT::v8i16, 2 }, 2631 { ISD::UMAX, MVT::v16i8, 1 }, 2632 { ISD::UMIN, MVT::v8i16, 2 }, 2633 { ISD::UMIN, MVT::v16i8, 1 }, 2634 { ISD::USUBSAT, MVT::v8i16, 1 }, 2635 { ISD::USUBSAT, MVT::v16i8, 1 }, 2636 { ISD::FMAXNUM, MVT::f64, 4 }, 2637 { ISD::FMAXNUM, MVT::v2f64, 4 }, 2638 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 2639 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 2640 }; 2641 static const CostTblEntry SSE1CostTbl[] = { 2642 { ISD::FMAXNUM, MVT::f32, 4 }, 2643 { ISD::FMAXNUM, MVT::v4f32, 4 }, 2644 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 2645 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 2646 }; 2647 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 2648 { ISD::CTTZ, MVT::i64, 1 }, 2649 }; 2650 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 2651 { ISD::CTTZ, MVT::i32, 1 }, 2652 { ISD::CTTZ, MVT::i16, 1 }, 2653 { ISD::CTTZ, MVT::i8, 1 }, 2654 }; 2655 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 2656 { ISD::CTLZ, MVT::i64, 1 }, 2657 }; 2658 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 2659 { ISD::CTLZ, MVT::i32, 1 }, 2660 { ISD::CTLZ, MVT::i16, 1 }, 2661 { ISD::CTLZ, MVT::i8, 1 }, 2662 }; 2663 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 2664 { ISD::CTPOP, MVT::i64, 1 }, 2665 }; 2666 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 2667 { ISD::CTPOP, MVT::i32, 1 }, 2668 { ISD::CTPOP, MVT::i16, 1 }, 2669 { ISD::CTPOP, MVT::i8, 1 }, 2670 }; 2671 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2672 { ISD::ABS, MVT::i64, 2 }, // SUB+CMOV 2673 { ISD::BITREVERSE, MVT::i64, 14 }, 2674 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 2675 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 2676 { ISD::CTPOP, MVT::i64, 10 }, 2677 { ISD::SADDO, MVT::i64, 1 }, 2678 { ISD::UADDO, MVT::i64, 1 }, 2679 { ISD::UMULO, MVT::i64, 2 }, // mulq + seto 2680 }; 2681 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2682 { ISD::ABS, MVT::i32, 2 }, // SUB+CMOV 2683 { ISD::ABS, MVT::i16, 2 }, // SUB+CMOV 2684 { ISD::BITREVERSE, MVT::i32, 14 }, 2685 { ISD::BITREVERSE, MVT::i16, 14 }, 2686 { ISD::BITREVERSE, MVT::i8, 11 }, 2687 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 2688 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 2689 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 2690 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 2691 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 2692 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 2693 { ISD::CTPOP, MVT::i32, 8 }, 2694 { ISD::CTPOP, MVT::i16, 9 }, 2695 { ISD::CTPOP, MVT::i8, 7 }, 2696 { ISD::SADDO, MVT::i32, 1 }, 2697 { ISD::SADDO, MVT::i16, 1 }, 2698 { ISD::SADDO, MVT::i8, 1 }, 2699 { ISD::UADDO, MVT::i32, 1 }, 2700 { ISD::UADDO, MVT::i16, 1 }, 2701 { ISD::UADDO, MVT::i8, 1 }, 2702 { ISD::UMULO, MVT::i32, 2 }, // mul + seto 2703 { ISD::UMULO, MVT::i16, 2 }, 2704 { ISD::UMULO, MVT::i8, 2 }, 2705 }; 2706 2707 Type *RetTy = ICA.getReturnType(); 2708 Type *OpTy = RetTy; 2709 Intrinsic::ID IID = ICA.getID(); 2710 unsigned ISD = ISD::DELETED_NODE; 2711 switch (IID) { 2712 default: 2713 break; 2714 case Intrinsic::abs: 2715 ISD = ISD::ABS; 2716 break; 2717 case Intrinsic::bitreverse: 2718 ISD = ISD::BITREVERSE; 2719 break; 2720 case Intrinsic::bswap: 2721 ISD = ISD::BSWAP; 2722 break; 2723 case Intrinsic::ctlz: 2724 ISD = ISD::CTLZ; 2725 break; 2726 case Intrinsic::ctpop: 2727 ISD = ISD::CTPOP; 2728 break; 2729 case Intrinsic::cttz: 2730 ISD = ISD::CTTZ; 2731 break; 2732 case Intrinsic::maxnum: 2733 case Intrinsic::minnum: 2734 // FMINNUM has same costs so don't duplicate. 2735 ISD = ISD::FMAXNUM; 2736 break; 2737 case Intrinsic::sadd_sat: 2738 ISD = ISD::SADDSAT; 2739 break; 2740 case Intrinsic::smax: 2741 ISD = ISD::SMAX; 2742 break; 2743 case Intrinsic::smin: 2744 ISD = ISD::SMIN; 2745 break; 2746 case Intrinsic::ssub_sat: 2747 ISD = ISD::SSUBSAT; 2748 break; 2749 case Intrinsic::uadd_sat: 2750 ISD = ISD::UADDSAT; 2751 break; 2752 case Intrinsic::umax: 2753 ISD = ISD::UMAX; 2754 break; 2755 case Intrinsic::umin: 2756 ISD = ISD::UMIN; 2757 break; 2758 case Intrinsic::usub_sat: 2759 ISD = ISD::USUBSAT; 2760 break; 2761 case Intrinsic::sqrt: 2762 ISD = ISD::FSQRT; 2763 break; 2764 case Intrinsic::sadd_with_overflow: 2765 case Intrinsic::ssub_with_overflow: 2766 // SSUBO has same costs so don't duplicate. 2767 ISD = ISD::SADDO; 2768 OpTy = RetTy->getContainedType(0); 2769 break; 2770 case Intrinsic::uadd_with_overflow: 2771 case Intrinsic::usub_with_overflow: 2772 // USUBO has same costs so don't duplicate. 2773 ISD = ISD::UADDO; 2774 OpTy = RetTy->getContainedType(0); 2775 break; 2776 case Intrinsic::umul_with_overflow: 2777 case Intrinsic::smul_with_overflow: 2778 // SMULO has same costs so don't duplicate. 2779 ISD = ISD::UMULO; 2780 OpTy = RetTy->getContainedType(0); 2781 break; 2782 } 2783 2784 if (ISD != ISD::DELETED_NODE) { 2785 // Legalize the type. 2786 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 2787 MVT MTy = LT.second; 2788 2789 // Attempt to lookup cost. 2790 if (ISD == ISD::BITREVERSE && ST->hasGFNI() && ST->hasSSSE3() && 2791 MTy.isVector()) { 2792 // With PSHUFB the code is very similar for all types. If we have integer 2793 // byte operations, we just need a GF2P8AFFINEQB for vXi8. For other types 2794 // we also need a PSHUFB. 2795 unsigned Cost = MTy.getVectorElementType() == MVT::i8 ? 1 : 2; 2796 2797 // Without byte operations, we need twice as many GF2P8AFFINEQB and PSHUFB 2798 // instructions. We also need an extract and an insert. 2799 if (!(MTy.is128BitVector() || (ST->hasAVX2() && MTy.is256BitVector()) || 2800 (ST->hasBWI() && MTy.is512BitVector()))) 2801 Cost = Cost * 2 + 2; 2802 2803 return LT.first * Cost; 2804 } 2805 2806 auto adjustTableCost = [](const CostTblEntry &Entry, int LegalizationCost, 2807 FastMathFlags FMF) { 2808 // If there are no NANs to deal with, then these are reduced to a 2809 // single MIN** or MAX** instruction instead of the MIN/CMP/SELECT that we 2810 // assume is used in the non-fast case. 2811 if (Entry.ISD == ISD::FMAXNUM || Entry.ISD == ISD::FMINNUM) { 2812 if (FMF.noNaNs()) 2813 return LegalizationCost * 1; 2814 } 2815 return LegalizationCost * (int)Entry.Cost; 2816 }; 2817 2818 if (ST->useGLMDivSqrtCosts()) 2819 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 2820 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2821 2822 if (ST->isSLM()) 2823 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2824 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2825 2826 if (ST->hasCDI()) 2827 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 2828 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2829 2830 if (ST->hasBWI()) 2831 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2832 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2833 2834 if (ST->hasAVX512()) 2835 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2836 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2837 2838 if (ST->hasXOP()) 2839 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2840 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2841 2842 if (ST->hasAVX2()) 2843 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2844 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2845 2846 if (ST->hasAVX()) 2847 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2848 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2849 2850 if (ST->hasSSE42()) 2851 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2852 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2853 2854 if (ST->hasSSE41()) 2855 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2856 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2857 2858 if (ST->hasSSSE3()) 2859 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 2860 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2861 2862 if (ST->hasSSE2()) 2863 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2864 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2865 2866 if (ST->hasSSE1()) 2867 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2868 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2869 2870 if (ST->hasBMI()) { 2871 if (ST->is64Bit()) 2872 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 2873 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2874 2875 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 2876 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2877 } 2878 2879 if (ST->hasLZCNT()) { 2880 if (ST->is64Bit()) 2881 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 2882 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2883 2884 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 2885 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2886 } 2887 2888 if (ST->hasPOPCNT()) { 2889 if (ST->is64Bit()) 2890 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 2891 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2892 2893 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 2894 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2895 } 2896 2897 // TODO - add BMI (TZCNT) scalar handling 2898 2899 if (ST->is64Bit()) 2900 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2901 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2902 2903 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2904 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2905 } 2906 2907 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 2908 } 2909 2910 int X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 2911 TTI::TargetCostKind CostKind) { 2912 if (ICA.isTypeBasedOnly()) 2913 return getTypeBasedIntrinsicInstrCost(ICA, CostKind); 2914 2915 static const CostTblEntry AVX512CostTbl[] = { 2916 { ISD::ROTL, MVT::v8i64, 1 }, 2917 { ISD::ROTL, MVT::v4i64, 1 }, 2918 { ISD::ROTL, MVT::v2i64, 1 }, 2919 { ISD::ROTL, MVT::v16i32, 1 }, 2920 { ISD::ROTL, MVT::v8i32, 1 }, 2921 { ISD::ROTL, MVT::v4i32, 1 }, 2922 { ISD::ROTR, MVT::v8i64, 1 }, 2923 { ISD::ROTR, MVT::v4i64, 1 }, 2924 { ISD::ROTR, MVT::v2i64, 1 }, 2925 { ISD::ROTR, MVT::v16i32, 1 }, 2926 { ISD::ROTR, MVT::v8i32, 1 }, 2927 { ISD::ROTR, MVT::v4i32, 1 } 2928 }; 2929 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 2930 static const CostTblEntry XOPCostTbl[] = { 2931 { ISD::ROTL, MVT::v4i64, 4 }, 2932 { ISD::ROTL, MVT::v8i32, 4 }, 2933 { ISD::ROTL, MVT::v16i16, 4 }, 2934 { ISD::ROTL, MVT::v32i8, 4 }, 2935 { ISD::ROTL, MVT::v2i64, 1 }, 2936 { ISD::ROTL, MVT::v4i32, 1 }, 2937 { ISD::ROTL, MVT::v8i16, 1 }, 2938 { ISD::ROTL, MVT::v16i8, 1 }, 2939 { ISD::ROTR, MVT::v4i64, 6 }, 2940 { ISD::ROTR, MVT::v8i32, 6 }, 2941 { ISD::ROTR, MVT::v16i16, 6 }, 2942 { ISD::ROTR, MVT::v32i8, 6 }, 2943 { ISD::ROTR, MVT::v2i64, 2 }, 2944 { ISD::ROTR, MVT::v4i32, 2 }, 2945 { ISD::ROTR, MVT::v8i16, 2 }, 2946 { ISD::ROTR, MVT::v16i8, 2 } 2947 }; 2948 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2949 { ISD::ROTL, MVT::i64, 1 }, 2950 { ISD::ROTR, MVT::i64, 1 }, 2951 { ISD::FSHL, MVT::i64, 4 } 2952 }; 2953 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2954 { ISD::ROTL, MVT::i32, 1 }, 2955 { ISD::ROTL, MVT::i16, 1 }, 2956 { ISD::ROTL, MVT::i8, 1 }, 2957 { ISD::ROTR, MVT::i32, 1 }, 2958 { ISD::ROTR, MVT::i16, 1 }, 2959 { ISD::ROTR, MVT::i8, 1 }, 2960 { ISD::FSHL, MVT::i32, 4 }, 2961 { ISD::FSHL, MVT::i16, 4 }, 2962 { ISD::FSHL, MVT::i8, 4 } 2963 }; 2964 2965 Intrinsic::ID IID = ICA.getID(); 2966 Type *RetTy = ICA.getReturnType(); 2967 const SmallVectorImpl<const Value *> &Args = ICA.getArgs(); 2968 unsigned ISD = ISD::DELETED_NODE; 2969 switch (IID) { 2970 default: 2971 break; 2972 case Intrinsic::fshl: 2973 ISD = ISD::FSHL; 2974 if (Args[0] == Args[1]) 2975 ISD = ISD::ROTL; 2976 break; 2977 case Intrinsic::fshr: 2978 // FSHR has same costs so don't duplicate. 2979 ISD = ISD::FSHL; 2980 if (Args[0] == Args[1]) 2981 ISD = ISD::ROTR; 2982 break; 2983 } 2984 2985 if (ISD != ISD::DELETED_NODE) { 2986 // Legalize the type. 2987 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 2988 MVT MTy = LT.second; 2989 2990 // Attempt to lookup cost. 2991 if (ST->hasAVX512()) 2992 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2993 return LT.first * Entry->Cost; 2994 2995 if (ST->hasXOP()) 2996 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2997 return LT.first * Entry->Cost; 2998 2999 if (ST->is64Bit()) 3000 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3001 return LT.first * Entry->Cost; 3002 3003 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3004 return LT.first * Entry->Cost; 3005 } 3006 3007 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3008 } 3009 3010 int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { 3011 static const CostTblEntry SLMCostTbl[] = { 3012 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 3013 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 3014 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 3015 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 3016 }; 3017 3018 assert(Val->isVectorTy() && "This must be a vector type"); 3019 Type *ScalarType = Val->getScalarType(); 3020 int RegisterFileMoveCost = 0; 3021 3022 if (Index != -1U && (Opcode == Instruction::ExtractElement || 3023 Opcode == Instruction::InsertElement)) { 3024 // Legalize the type. 3025 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 3026 3027 // This type is legalized to a scalar type. 3028 if (!LT.second.isVector()) 3029 return 0; 3030 3031 // The type may be split. Normalize the index to the new type. 3032 unsigned NumElts = LT.second.getVectorNumElements(); 3033 unsigned SubNumElts = NumElts; 3034 Index = Index % NumElts; 3035 3036 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 3037 // For inserts, we also need to insert the subvector back. 3038 if (LT.second.getSizeInBits() > 128) { 3039 assert((LT.second.getSizeInBits() % 128) == 0 && "Illegal vector"); 3040 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 3041 SubNumElts = NumElts / NumSubVecs; 3042 if (SubNumElts <= Index) { 3043 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 3044 Index %= SubNumElts; 3045 } 3046 } 3047 3048 if (Index == 0) { 3049 // Floating point scalars are already located in index #0. 3050 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 3051 // true for all. 3052 if (ScalarType->isFloatingPointTy()) 3053 return RegisterFileMoveCost; 3054 3055 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 3056 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 3057 return 1 + RegisterFileMoveCost; 3058 } 3059 3060 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3061 assert(ISD && "Unexpected vector opcode"); 3062 MVT MScalarTy = LT.second.getScalarType(); 3063 if (ST->isSLM()) 3064 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 3065 return Entry->Cost + RegisterFileMoveCost; 3066 3067 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 3068 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3069 (MScalarTy.isInteger() && ST->hasSSE41())) 3070 return 1 + RegisterFileMoveCost; 3071 3072 // Assume insertps is relatively cheap on all targets. 3073 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 3074 Opcode == Instruction::InsertElement) 3075 return 1 + RegisterFileMoveCost; 3076 3077 // For extractions we just need to shuffle the element to index 0, which 3078 // should be very cheap (assume cost = 1). For insertions we need to shuffle 3079 // the elements to its destination. In both cases we must handle the 3080 // subvector move(s). 3081 // If the vector type is already less than 128-bits then don't reduce it. 3082 // TODO: Under what circumstances should we shuffle using the full width? 3083 int ShuffleCost = 1; 3084 if (Opcode == Instruction::InsertElement) { 3085 auto *SubTy = cast<VectorType>(Val); 3086 EVT VT = TLI->getValueType(DL, Val); 3087 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 3088 SubTy = FixedVectorType::get(ScalarType, SubNumElts); 3089 ShuffleCost = 3090 getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, None, 0, SubTy); 3091 } 3092 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 3093 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 3094 } 3095 3096 // Add to the base cost if we know that the extracted element of a vector is 3097 // destined to be moved to and used in the integer register file. 3098 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 3099 RegisterFileMoveCost += 1; 3100 3101 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 3102 } 3103 3104 unsigned X86TTIImpl::getScalarizationOverhead(VectorType *Ty, 3105 const APInt &DemandedElts, 3106 bool Insert, bool Extract) { 3107 unsigned Cost = 0; 3108 3109 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much 3110 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT. 3111 if (Insert) { 3112 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3113 MVT MScalarTy = LT.second.getScalarType(); 3114 3115 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3116 (MScalarTy.isInteger() && ST->hasSSE41()) || 3117 (MScalarTy == MVT::f32 && ST->hasSSE41())) { 3118 // For types we can insert directly, insertion into 128-bit sub vectors is 3119 // cheap, followed by a cheap chain of concatenations. 3120 if (LT.second.getSizeInBits() <= 128) { 3121 Cost += 3122 BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, false); 3123 } else { 3124 // In each 128-lane, if at least one index is demanded but not all 3125 // indices are demanded and this 128-lane is not the first 128-lane of 3126 // the legalized-vector, then this 128-lane needs a extracti128; If in 3127 // each 128-lane, there is at least one demanded index, this 128-lane 3128 // needs a inserti128. 3129 3130 // The following cases will help you build a better understanding: 3131 // Assume we insert several elements into a v8i32 vector in avx2, 3132 // Case#1: inserting into 1th index needs vpinsrd + inserti128. 3133 // Case#2: inserting into 5th index needs extracti128 + vpinsrd + 3134 // inserti128. 3135 // Case#3: inserting into 4,5,6,7 index needs 4*vpinsrd + inserti128. 3136 unsigned Num128Lanes = LT.second.getSizeInBits() / 128 * LT.first; 3137 unsigned NumElts = LT.second.getVectorNumElements() * LT.first; 3138 APInt WidenedDemandedElts = DemandedElts.zextOrSelf(NumElts); 3139 unsigned Scale = NumElts / Num128Lanes; 3140 // We iterate each 128-lane, and check if we need a 3141 // extracti128/inserti128 for this 128-lane. 3142 for (unsigned I = 0; I < NumElts; I += Scale) { 3143 APInt Mask = WidenedDemandedElts.getBitsSet(NumElts, I, I + Scale); 3144 APInt MaskedDE = Mask & WidenedDemandedElts; 3145 unsigned Population = MaskedDE.countPopulation(); 3146 Cost += (Population > 0 && Population != Scale && 3147 I % LT.second.getVectorNumElements() != 0); 3148 Cost += Population > 0; 3149 } 3150 Cost += DemandedElts.countPopulation(); 3151 3152 // For vXf32 cases, insertion into the 0'th index in each v4f32 3153 // 128-bit vector is free. 3154 // NOTE: This assumes legalization widens vXf32 vectors. 3155 if (MScalarTy == MVT::f32) 3156 for (unsigned i = 0, e = cast<FixedVectorType>(Ty)->getNumElements(); 3157 i < e; i += 4) 3158 if (DemandedElts[i]) 3159 Cost--; 3160 } 3161 } else if (LT.second.isVector()) { 3162 // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded 3163 // integer element as a SCALAR_TO_VECTOR, then we build the vector as a 3164 // series of UNPCK followed by CONCAT_VECTORS - all of these can be 3165 // considered cheap. 3166 if (Ty->isIntOrIntVectorTy()) 3167 Cost += DemandedElts.countPopulation(); 3168 3169 // Get the smaller of the legalized or original pow2-extended number of 3170 // vector elements, which represents the number of unpacks we'll end up 3171 // performing. 3172 unsigned NumElts = LT.second.getVectorNumElements(); 3173 unsigned Pow2Elts = 3174 PowerOf2Ceil(cast<FixedVectorType>(Ty)->getNumElements()); 3175 Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first; 3176 } 3177 } 3178 3179 // TODO: Use default extraction for now, but we should investigate extending this 3180 // to handle repeated subvector extraction. 3181 if (Extract) 3182 Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, false, Extract); 3183 3184 return Cost; 3185 } 3186 3187 int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 3188 MaybeAlign Alignment, unsigned AddressSpace, 3189 TTI::TargetCostKind CostKind, 3190 const Instruction *I) { 3191 // TODO: Handle other cost kinds. 3192 if (CostKind != TTI::TCK_RecipThroughput) { 3193 if (auto *SI = dyn_cast_or_null<StoreInst>(I)) { 3194 // Store instruction with index and scale costs 2 Uops. 3195 // Check the preceding GEP to identify non-const indices. 3196 if (auto *GEP = dyn_cast<GetElementPtrInst>(SI->getPointerOperand())) { 3197 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3198 return TTI::TCC_Basic * 2; 3199 } 3200 } 3201 return TTI::TCC_Basic; 3202 } 3203 3204 // Handle non-power-of-two vectors such as <3 x float> 3205 if (auto *VTy = dyn_cast<FixedVectorType>(Src)) { 3206 unsigned NumElem = VTy->getNumElements(); 3207 3208 // Handle a few common cases: 3209 // <3 x float> 3210 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 3211 // Cost = 64 bit store + extract + 32 bit store. 3212 return 3; 3213 3214 // <3 x double> 3215 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 3216 // Cost = 128 bit store + unpack + 64 bit store. 3217 return 3; 3218 3219 // Assume that all other non-power-of-two numbers are scalarized. 3220 if (!isPowerOf2_32(NumElem)) { 3221 APInt DemandedElts = APInt::getAllOnesValue(NumElem); 3222 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment, 3223 AddressSpace, CostKind); 3224 int SplitCost = getScalarizationOverhead(VTy, DemandedElts, 3225 Opcode == Instruction::Load, 3226 Opcode == Instruction::Store); 3227 return NumElem * Cost + SplitCost; 3228 } 3229 } 3230 3231 // Type legalization can't handle structs 3232 if (TLI->getValueType(DL, Src, true) == MVT::Other) 3233 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3234 CostKind); 3235 3236 // Legalize the type. 3237 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 3238 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 3239 "Invalid Opcode"); 3240 3241 // Each load/store unit costs 1. 3242 int Cost = LT.first * 1; 3243 3244 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a 3245 // proxy for a double-pumped AVX memory interface such as on Sandybridge. 3246 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow()) 3247 Cost *= 2; 3248 3249 return Cost; 3250 } 3251 3252 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, 3253 Align Alignment, unsigned AddressSpace, 3254 TTI::TargetCostKind CostKind) { 3255 bool IsLoad = (Instruction::Load == Opcode); 3256 bool IsStore = (Instruction::Store == Opcode); 3257 3258 auto *SrcVTy = dyn_cast<FixedVectorType>(SrcTy); 3259 if (!SrcVTy) 3260 // To calculate scalar take the regular cost, without mask 3261 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace, CostKind); 3262 3263 unsigned NumElem = SrcVTy->getNumElements(); 3264 auto *MaskTy = 3265 FixedVectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 3266 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, Alignment)) || 3267 (IsStore && !isLegalMaskedStore(SrcVTy, Alignment)) || 3268 !isPowerOf2_32(NumElem)) { 3269 // Scalarization 3270 APInt DemandedElts = APInt::getAllOnesValue(NumElem); 3271 int MaskSplitCost = 3272 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 3273 int ScalarCompareCost = getCmpSelInstrCost( 3274 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr, 3275 CmpInst::BAD_ICMP_PREDICATE, CostKind); 3276 int BranchCost = getCFInstrCost(Instruction::Br, CostKind); 3277 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 3278 int ValueSplitCost = 3279 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore); 3280 int MemopCost = 3281 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3282 Alignment, AddressSpace, CostKind); 3283 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 3284 } 3285 3286 // Legalize the type. 3287 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3288 auto VT = TLI->getValueType(DL, SrcVTy); 3289 int Cost = 0; 3290 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 3291 LT.second.getVectorNumElements() == NumElem) 3292 // Promotion requires expand/truncate for data and a shuffle for mask. 3293 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, None, 0, nullptr) + 3294 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, None, 0, nullptr); 3295 3296 else if (LT.second.getVectorNumElements() > NumElem) { 3297 auto *NewMaskTy = FixedVectorType::get(MaskTy->getElementType(), 3298 LT.second.getVectorNumElements()); 3299 // Expanding requires fill mask with zeroes 3300 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, None, 0, MaskTy); 3301 } 3302 3303 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 3304 if (!ST->hasAVX512()) 3305 return Cost + LT.first * (IsLoad ? 2 : 8); 3306 3307 // AVX-512 masked load/store is cheapper 3308 return Cost + LT.first; 3309 } 3310 3311 int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE, 3312 const SCEV *Ptr) { 3313 // Address computations in vectorized code with non-consecutive addresses will 3314 // likely result in more instructions compared to scalar code where the 3315 // computation can more often be merged into the index mode. The resulting 3316 // extra micro-ops can significantly decrease throughput. 3317 const unsigned NumVectorInstToHideOverhead = 10; 3318 3319 // Cost modeling of Strided Access Computation is hidden by the indexing 3320 // modes of X86 regardless of the stride value. We dont believe that there 3321 // is a difference between constant strided access in gerenal and constant 3322 // strided value which is less than or equal to 64. 3323 // Even in the case of (loop invariant) stride whose value is not known at 3324 // compile time, the address computation will not incur more than one extra 3325 // ADD instruction. 3326 if (Ty->isVectorTy() && SE) { 3327 if (!BaseT::isStridedAccess(Ptr)) 3328 return NumVectorInstToHideOverhead; 3329 if (!BaseT::getConstantStrideStep(SE, Ptr)) 3330 return 1; 3331 } 3332 3333 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 3334 } 3335 3336 int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 3337 bool IsPairwise, 3338 TTI::TargetCostKind CostKind) { 3339 // Just use the default implementation for pair reductions. 3340 if (IsPairwise) 3341 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise, CostKind); 3342 3343 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3344 // and make it as the cost. 3345 3346 static const CostTblEntry SLMCostTblNoPairWise[] = { 3347 { ISD::FADD, MVT::v2f64, 3 }, 3348 { ISD::ADD, MVT::v2i64, 5 }, 3349 }; 3350 3351 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3352 { ISD::FADD, MVT::v2f64, 2 }, 3353 { ISD::FADD, MVT::v4f32, 4 }, 3354 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 3355 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 3356 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 3357 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 3358 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 3359 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 3360 { ISD::ADD, MVT::v2i8, 2 }, 3361 { ISD::ADD, MVT::v4i8, 2 }, 3362 { ISD::ADD, MVT::v8i8, 2 }, 3363 { ISD::ADD, MVT::v16i8, 3 }, 3364 }; 3365 3366 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3367 { ISD::FADD, MVT::v4f64, 3 }, 3368 { ISD::FADD, MVT::v4f32, 3 }, 3369 { ISD::FADD, MVT::v8f32, 4 }, 3370 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 3371 { ISD::ADD, MVT::v4i64, 3 }, 3372 { ISD::ADD, MVT::v8i32, 5 }, 3373 { ISD::ADD, MVT::v16i16, 5 }, 3374 { ISD::ADD, MVT::v32i8, 4 }, 3375 }; 3376 3377 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3378 assert(ISD && "Invalid opcode"); 3379 3380 // Before legalizing the type, give a chance to look up illegal narrow types 3381 // in the table. 3382 // FIXME: Is there a better way to do this? 3383 EVT VT = TLI->getValueType(DL, ValTy); 3384 if (VT.isSimple()) { 3385 MVT MTy = VT.getSimpleVT(); 3386 if (ST->isSLM()) 3387 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3388 return Entry->Cost; 3389 3390 if (ST->hasAVX()) 3391 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3392 return Entry->Cost; 3393 3394 if (ST->hasSSE2()) 3395 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3396 return Entry->Cost; 3397 } 3398 3399 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3400 3401 MVT MTy = LT.second; 3402 3403 auto *ValVTy = cast<FixedVectorType>(ValTy); 3404 3405 unsigned ArithmeticCost = 0; 3406 if (LT.first != 1 && MTy.isVector() && 3407 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3408 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3409 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3410 MTy.getVectorNumElements()); 3411 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3412 ArithmeticCost *= LT.first - 1; 3413 } 3414 3415 if (ST->isSLM()) 3416 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3417 return ArithmeticCost + Entry->Cost; 3418 3419 if (ST->hasAVX()) 3420 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3421 return ArithmeticCost + Entry->Cost; 3422 3423 if (ST->hasSSE2()) 3424 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3425 return ArithmeticCost + Entry->Cost; 3426 3427 // FIXME: These assume a naive kshift+binop lowering, which is probably 3428 // conservative in most cases. 3429 static const CostTblEntry AVX512BoolReduction[] = { 3430 { ISD::AND, MVT::v2i1, 3 }, 3431 { ISD::AND, MVT::v4i1, 5 }, 3432 { ISD::AND, MVT::v8i1, 7 }, 3433 { ISD::AND, MVT::v16i1, 9 }, 3434 { ISD::AND, MVT::v32i1, 11 }, 3435 { ISD::AND, MVT::v64i1, 13 }, 3436 { ISD::OR, MVT::v2i1, 3 }, 3437 { ISD::OR, MVT::v4i1, 5 }, 3438 { ISD::OR, MVT::v8i1, 7 }, 3439 { ISD::OR, MVT::v16i1, 9 }, 3440 { ISD::OR, MVT::v32i1, 11 }, 3441 { ISD::OR, MVT::v64i1, 13 }, 3442 }; 3443 3444 static const CostTblEntry AVX2BoolReduction[] = { 3445 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 3446 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 3447 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 3448 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 3449 }; 3450 3451 static const CostTblEntry AVX1BoolReduction[] = { 3452 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 3453 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 3454 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3455 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3456 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 3457 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 3458 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3459 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3460 }; 3461 3462 static const CostTblEntry SSE2BoolReduction[] = { 3463 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 3464 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 3465 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 3466 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 3467 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 3468 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 3469 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 3470 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 3471 }; 3472 3473 // Handle bool allof/anyof patterns. 3474 if (ValVTy->getElementType()->isIntegerTy(1)) { 3475 unsigned ArithmeticCost = 0; 3476 if (LT.first != 1 && MTy.isVector() && 3477 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3478 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3479 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3480 MTy.getVectorNumElements()); 3481 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3482 ArithmeticCost *= LT.first - 1; 3483 } 3484 3485 if (ST->hasAVX512()) 3486 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 3487 return ArithmeticCost + Entry->Cost; 3488 if (ST->hasAVX2()) 3489 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 3490 return ArithmeticCost + Entry->Cost; 3491 if (ST->hasAVX()) 3492 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 3493 return ArithmeticCost + Entry->Cost; 3494 if (ST->hasSSE2()) 3495 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 3496 return ArithmeticCost + Entry->Cost; 3497 3498 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise, 3499 CostKind); 3500 } 3501 3502 unsigned NumVecElts = ValVTy->getNumElements(); 3503 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 3504 3505 // Special case power of 2 reductions where the scalar type isn't changed 3506 // by type legalization. 3507 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 3508 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise, 3509 CostKind); 3510 3511 unsigned ReductionCost = 0; 3512 3513 auto *Ty = ValVTy; 3514 if (LT.first != 1 && MTy.isVector() && 3515 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3516 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3517 Ty = FixedVectorType::get(ValVTy->getElementType(), 3518 MTy.getVectorNumElements()); 3519 ReductionCost = getArithmeticInstrCost(Opcode, Ty, CostKind); 3520 ReductionCost *= LT.first - 1; 3521 NumVecElts = MTy.getVectorNumElements(); 3522 } 3523 3524 // Now handle reduction with the legal type, taking into account size changes 3525 // at each level. 3526 while (NumVecElts > 1) { 3527 // Determine the size of the remaining vector we need to reduce. 3528 unsigned Size = NumVecElts * ScalarSize; 3529 NumVecElts /= 2; 3530 // If we're reducing from 256/512 bits, use an extract_subvector. 3531 if (Size > 128) { 3532 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 3533 ReductionCost += 3534 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 3535 Ty = SubTy; 3536 } else if (Size == 128) { 3537 // Reducing from 128 bits is a permute of v2f64/v2i64. 3538 FixedVectorType *ShufTy; 3539 if (ValVTy->isFloatingPointTy()) 3540 ShufTy = 3541 FixedVectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 3542 else 3543 ShufTy = 3544 FixedVectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 3545 ReductionCost += 3546 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3547 } else if (Size == 64) { 3548 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3549 FixedVectorType *ShufTy; 3550 if (ValVTy->isFloatingPointTy()) 3551 ShufTy = 3552 FixedVectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 3553 else 3554 ShufTy = 3555 FixedVectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 3556 ReductionCost += 3557 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3558 } else { 3559 // Reducing from smaller size is a shift by immediate. 3560 auto *ShiftTy = FixedVectorType::get( 3561 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 3562 ReductionCost += getArithmeticInstrCost( 3563 Instruction::LShr, ShiftTy, CostKind, 3564 TargetTransformInfo::OK_AnyValue, 3565 TargetTransformInfo::OK_UniformConstantValue, 3566 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3567 } 3568 3569 // Add the arithmetic op for this level. 3570 ReductionCost += getArithmeticInstrCost(Opcode, Ty, CostKind); 3571 } 3572 3573 // Add the final extract element to the cost. 3574 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3575 } 3576 3577 int X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, bool IsUnsigned) { 3578 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3579 3580 MVT MTy = LT.second; 3581 3582 int ISD; 3583 if (Ty->isIntOrIntVectorTy()) { 3584 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3585 } else { 3586 assert(Ty->isFPOrFPVectorTy() && 3587 "Expected float point or integer vector type."); 3588 ISD = ISD::FMINNUM; 3589 } 3590 3591 static const CostTblEntry SSE1CostTbl[] = { 3592 {ISD::FMINNUM, MVT::v4f32, 1}, 3593 }; 3594 3595 static const CostTblEntry SSE2CostTbl[] = { 3596 {ISD::FMINNUM, MVT::v2f64, 1}, 3597 {ISD::SMIN, MVT::v8i16, 1}, 3598 {ISD::UMIN, MVT::v16i8, 1}, 3599 }; 3600 3601 static const CostTblEntry SSE41CostTbl[] = { 3602 {ISD::SMIN, MVT::v4i32, 1}, 3603 {ISD::UMIN, MVT::v4i32, 1}, 3604 {ISD::UMIN, MVT::v8i16, 1}, 3605 {ISD::SMIN, MVT::v16i8, 1}, 3606 }; 3607 3608 static const CostTblEntry SSE42CostTbl[] = { 3609 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 3610 }; 3611 3612 static const CostTblEntry AVX1CostTbl[] = { 3613 {ISD::FMINNUM, MVT::v8f32, 1}, 3614 {ISD::FMINNUM, MVT::v4f64, 1}, 3615 {ISD::SMIN, MVT::v8i32, 3}, 3616 {ISD::UMIN, MVT::v8i32, 3}, 3617 {ISD::SMIN, MVT::v16i16, 3}, 3618 {ISD::UMIN, MVT::v16i16, 3}, 3619 {ISD::SMIN, MVT::v32i8, 3}, 3620 {ISD::UMIN, MVT::v32i8, 3}, 3621 }; 3622 3623 static const CostTblEntry AVX2CostTbl[] = { 3624 {ISD::SMIN, MVT::v8i32, 1}, 3625 {ISD::UMIN, MVT::v8i32, 1}, 3626 {ISD::SMIN, MVT::v16i16, 1}, 3627 {ISD::UMIN, MVT::v16i16, 1}, 3628 {ISD::SMIN, MVT::v32i8, 1}, 3629 {ISD::UMIN, MVT::v32i8, 1}, 3630 }; 3631 3632 static const CostTblEntry AVX512CostTbl[] = { 3633 {ISD::FMINNUM, MVT::v16f32, 1}, 3634 {ISD::FMINNUM, MVT::v8f64, 1}, 3635 {ISD::SMIN, MVT::v2i64, 1}, 3636 {ISD::UMIN, MVT::v2i64, 1}, 3637 {ISD::SMIN, MVT::v4i64, 1}, 3638 {ISD::UMIN, MVT::v4i64, 1}, 3639 {ISD::SMIN, MVT::v8i64, 1}, 3640 {ISD::UMIN, MVT::v8i64, 1}, 3641 {ISD::SMIN, MVT::v16i32, 1}, 3642 {ISD::UMIN, MVT::v16i32, 1}, 3643 }; 3644 3645 static const CostTblEntry AVX512BWCostTbl[] = { 3646 {ISD::SMIN, MVT::v32i16, 1}, 3647 {ISD::UMIN, MVT::v32i16, 1}, 3648 {ISD::SMIN, MVT::v64i8, 1}, 3649 {ISD::UMIN, MVT::v64i8, 1}, 3650 }; 3651 3652 // If we have a native MIN/MAX instruction for this type, use it. 3653 if (ST->hasBWI()) 3654 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3655 return LT.first * Entry->Cost; 3656 3657 if (ST->hasAVX512()) 3658 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3659 return LT.first * Entry->Cost; 3660 3661 if (ST->hasAVX2()) 3662 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3663 return LT.first * Entry->Cost; 3664 3665 if (ST->hasAVX()) 3666 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3667 return LT.first * Entry->Cost; 3668 3669 if (ST->hasSSE42()) 3670 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3671 return LT.first * Entry->Cost; 3672 3673 if (ST->hasSSE41()) 3674 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3675 return LT.first * Entry->Cost; 3676 3677 if (ST->hasSSE2()) 3678 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3679 return LT.first * Entry->Cost; 3680 3681 if (ST->hasSSE1()) 3682 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3683 return LT.first * Entry->Cost; 3684 3685 unsigned CmpOpcode; 3686 if (Ty->isFPOrFPVectorTy()) { 3687 CmpOpcode = Instruction::FCmp; 3688 } else { 3689 assert(Ty->isIntOrIntVectorTy() && 3690 "expecting floating point or integer type for min/max reduction"); 3691 CmpOpcode = Instruction::ICmp; 3692 } 3693 3694 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 3695 // Otherwise fall back to cmp+select. 3696 return getCmpSelInstrCost(CmpOpcode, Ty, CondTy, CmpInst::BAD_ICMP_PREDICATE, 3697 CostKind) + 3698 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, 3699 CmpInst::BAD_ICMP_PREDICATE, CostKind); 3700 } 3701 3702 int X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 3703 bool IsPairwise, bool IsUnsigned, 3704 TTI::TargetCostKind CostKind) { 3705 // Just use the default implementation for pair reductions. 3706 if (IsPairwise) 3707 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned, 3708 CostKind); 3709 3710 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3711 3712 MVT MTy = LT.second; 3713 3714 int ISD; 3715 if (ValTy->isIntOrIntVectorTy()) { 3716 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3717 } else { 3718 assert(ValTy->isFPOrFPVectorTy() && 3719 "Expected float point or integer vector type."); 3720 ISD = ISD::FMINNUM; 3721 } 3722 3723 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3724 // and make it as the cost. 3725 3726 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3727 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 3728 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 3729 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 3730 }; 3731 3732 static const CostTblEntry SSE41CostTblNoPairWise[] = { 3733 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 3734 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 3735 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 3736 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 3737 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 3738 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 3739 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 3740 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 3741 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 3742 {ISD::SMIN, MVT::v16i8, 6}, 3743 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 3744 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 3745 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 3746 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 3747 }; 3748 3749 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3750 {ISD::SMIN, MVT::v16i16, 6}, 3751 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 3752 {ISD::SMIN, MVT::v32i8, 8}, 3753 {ISD::UMIN, MVT::v32i8, 8}, 3754 }; 3755 3756 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 3757 {ISD::SMIN, MVT::v32i16, 8}, 3758 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 3759 {ISD::SMIN, MVT::v64i8, 10}, 3760 {ISD::UMIN, MVT::v64i8, 10}, 3761 }; 3762 3763 // Before legalizing the type, give a chance to look up illegal narrow types 3764 // in the table. 3765 // FIXME: Is there a better way to do this? 3766 EVT VT = TLI->getValueType(DL, ValTy); 3767 if (VT.isSimple()) { 3768 MVT MTy = VT.getSimpleVT(); 3769 if (ST->hasBWI()) 3770 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3771 return Entry->Cost; 3772 3773 if (ST->hasAVX()) 3774 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3775 return Entry->Cost; 3776 3777 if (ST->hasSSE41()) 3778 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3779 return Entry->Cost; 3780 3781 if (ST->hasSSE2()) 3782 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3783 return Entry->Cost; 3784 } 3785 3786 auto *ValVTy = cast<FixedVectorType>(ValTy); 3787 unsigned NumVecElts = ValVTy->getNumElements(); 3788 3789 auto *Ty = ValVTy; 3790 unsigned MinMaxCost = 0; 3791 if (LT.first != 1 && MTy.isVector() && 3792 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3793 // Type needs to be split. We need LT.first - 1 operations ops. 3794 Ty = FixedVectorType::get(ValVTy->getElementType(), 3795 MTy.getVectorNumElements()); 3796 auto *SubCondTy = FixedVectorType::get(CondTy->getElementType(), 3797 MTy.getVectorNumElements()); 3798 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3799 MinMaxCost *= LT.first - 1; 3800 NumVecElts = MTy.getVectorNumElements(); 3801 } 3802 3803 if (ST->hasBWI()) 3804 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3805 return MinMaxCost + Entry->Cost; 3806 3807 if (ST->hasAVX()) 3808 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3809 return MinMaxCost + Entry->Cost; 3810 3811 if (ST->hasSSE41()) 3812 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3813 return MinMaxCost + Entry->Cost; 3814 3815 if (ST->hasSSE2()) 3816 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3817 return MinMaxCost + Entry->Cost; 3818 3819 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 3820 3821 // Special case power of 2 reductions where the scalar type isn't changed 3822 // by type legalization. 3823 if (!isPowerOf2_32(ValVTy->getNumElements()) || 3824 ScalarSize != MTy.getScalarSizeInBits()) 3825 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned, 3826 CostKind); 3827 3828 // Now handle reduction with the legal type, taking into account size changes 3829 // at each level. 3830 while (NumVecElts > 1) { 3831 // Determine the size of the remaining vector we need to reduce. 3832 unsigned Size = NumVecElts * ScalarSize; 3833 NumVecElts /= 2; 3834 // If we're reducing from 256/512 bits, use an extract_subvector. 3835 if (Size > 128) { 3836 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 3837 MinMaxCost += 3838 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 3839 Ty = SubTy; 3840 } else if (Size == 128) { 3841 // Reducing from 128 bits is a permute of v2f64/v2i64. 3842 VectorType *ShufTy; 3843 if (ValTy->isFloatingPointTy()) 3844 ShufTy = 3845 FixedVectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 3846 else 3847 ShufTy = FixedVectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 3848 MinMaxCost += 3849 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3850 } else if (Size == 64) { 3851 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3852 FixedVectorType *ShufTy; 3853 if (ValTy->isFloatingPointTy()) 3854 ShufTy = FixedVectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 3855 else 3856 ShufTy = FixedVectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 3857 MinMaxCost += 3858 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3859 } else { 3860 // Reducing from smaller size is a shift by immediate. 3861 auto *ShiftTy = FixedVectorType::get( 3862 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 3863 MinMaxCost += getArithmeticInstrCost( 3864 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, 3865 TargetTransformInfo::OK_AnyValue, 3866 TargetTransformInfo::OK_UniformConstantValue, 3867 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3868 } 3869 3870 // Add the arithmetic op for this level. 3871 auto *SubCondTy = 3872 FixedVectorType::get(CondTy->getElementType(), Ty->getNumElements()); 3873 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3874 } 3875 3876 // Add the final extract element to the cost. 3877 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3878 } 3879 3880 /// Calculate the cost of materializing a 64-bit value. This helper 3881 /// method might only calculate a fraction of a larger immediate. Therefore it 3882 /// is valid to return a cost of ZERO. 3883 int X86TTIImpl::getIntImmCost(int64_t Val) { 3884 if (Val == 0) 3885 return TTI::TCC_Free; 3886 3887 if (isInt<32>(Val)) 3888 return TTI::TCC_Basic; 3889 3890 return 2 * TTI::TCC_Basic; 3891 } 3892 3893 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 3894 TTI::TargetCostKind CostKind) { 3895 assert(Ty->isIntegerTy()); 3896 3897 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3898 if (BitSize == 0) 3899 return ~0U; 3900 3901 // Never hoist constants larger than 128bit, because this might lead to 3902 // incorrect code generation or assertions in codegen. 3903 // Fixme: Create a cost model for types larger than i128 once the codegen 3904 // issues have been fixed. 3905 if (BitSize > 128) 3906 return TTI::TCC_Free; 3907 3908 if (Imm == 0) 3909 return TTI::TCC_Free; 3910 3911 // Sign-extend all constants to a multiple of 64-bit. 3912 APInt ImmVal = Imm; 3913 if (BitSize % 64 != 0) 3914 ImmVal = Imm.sext(alignTo(BitSize, 64)); 3915 3916 // Split the constant into 64-bit chunks and calculate the cost for each 3917 // chunk. 3918 int Cost = 0; 3919 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 3920 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 3921 int64_t Val = Tmp.getSExtValue(); 3922 Cost += getIntImmCost(Val); 3923 } 3924 // We need at least one instruction to materialize the constant. 3925 return std::max(1, Cost); 3926 } 3927 3928 int X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, 3929 const APInt &Imm, Type *Ty, 3930 TTI::TargetCostKind CostKind, 3931 Instruction *Inst) { 3932 assert(Ty->isIntegerTy()); 3933 3934 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3935 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3936 // here, so that constant hoisting will ignore this constant. 3937 if (BitSize == 0) 3938 return TTI::TCC_Free; 3939 3940 unsigned ImmIdx = ~0U; 3941 switch (Opcode) { 3942 default: 3943 return TTI::TCC_Free; 3944 case Instruction::GetElementPtr: 3945 // Always hoist the base address of a GetElementPtr. This prevents the 3946 // creation of new constants for every base constant that gets constant 3947 // folded with the offset. 3948 if (Idx == 0) 3949 return 2 * TTI::TCC_Basic; 3950 return TTI::TCC_Free; 3951 case Instruction::Store: 3952 ImmIdx = 0; 3953 break; 3954 case Instruction::ICmp: 3955 // This is an imperfect hack to prevent constant hoisting of 3956 // compares that might be trying to check if a 64-bit value fits in 3957 // 32-bits. The backend can optimize these cases using a right shift by 32. 3958 // Ideally we would check the compare predicate here. There also other 3959 // similar immediates the backend can use shifts for. 3960 if (Idx == 1 && Imm.getBitWidth() == 64) { 3961 uint64_t ImmVal = Imm.getZExtValue(); 3962 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 3963 return TTI::TCC_Free; 3964 } 3965 ImmIdx = 1; 3966 break; 3967 case Instruction::And: 3968 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 3969 // by using a 32-bit operation with implicit zero extension. Detect such 3970 // immediates here as the normal path expects bit 31 to be sign extended. 3971 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 3972 return TTI::TCC_Free; 3973 ImmIdx = 1; 3974 break; 3975 case Instruction::Add: 3976 case Instruction::Sub: 3977 // For add/sub, we can use the opposite instruction for INT32_MIN. 3978 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 3979 return TTI::TCC_Free; 3980 ImmIdx = 1; 3981 break; 3982 case Instruction::UDiv: 3983 case Instruction::SDiv: 3984 case Instruction::URem: 3985 case Instruction::SRem: 3986 // Division by constant is typically expanded later into a different 3987 // instruction sequence. This completely changes the constants. 3988 // Report them as "free" to stop ConstantHoist from marking them as opaque. 3989 return TTI::TCC_Free; 3990 case Instruction::Mul: 3991 case Instruction::Or: 3992 case Instruction::Xor: 3993 ImmIdx = 1; 3994 break; 3995 // Always return TCC_Free for the shift value of a shift instruction. 3996 case Instruction::Shl: 3997 case Instruction::LShr: 3998 case Instruction::AShr: 3999 if (Idx == 1) 4000 return TTI::TCC_Free; 4001 break; 4002 case Instruction::Trunc: 4003 case Instruction::ZExt: 4004 case Instruction::SExt: 4005 case Instruction::IntToPtr: 4006 case Instruction::PtrToInt: 4007 case Instruction::BitCast: 4008 case Instruction::PHI: 4009 case Instruction::Call: 4010 case Instruction::Select: 4011 case Instruction::Ret: 4012 case Instruction::Load: 4013 break; 4014 } 4015 4016 if (Idx == ImmIdx) { 4017 int NumConstants = divideCeil(BitSize, 64); 4018 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4019 return (Cost <= NumConstants * TTI::TCC_Basic) 4020 ? static_cast<int>(TTI::TCC_Free) 4021 : Cost; 4022 } 4023 4024 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4025 } 4026 4027 int X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 4028 const APInt &Imm, Type *Ty, 4029 TTI::TargetCostKind CostKind) { 4030 assert(Ty->isIntegerTy()); 4031 4032 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4033 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4034 // here, so that constant hoisting will ignore this constant. 4035 if (BitSize == 0) 4036 return TTI::TCC_Free; 4037 4038 switch (IID) { 4039 default: 4040 return TTI::TCC_Free; 4041 case Intrinsic::sadd_with_overflow: 4042 case Intrinsic::uadd_with_overflow: 4043 case Intrinsic::ssub_with_overflow: 4044 case Intrinsic::usub_with_overflow: 4045 case Intrinsic::smul_with_overflow: 4046 case Intrinsic::umul_with_overflow: 4047 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 4048 return TTI::TCC_Free; 4049 break; 4050 case Intrinsic::experimental_stackmap: 4051 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4052 return TTI::TCC_Free; 4053 break; 4054 case Intrinsic::experimental_patchpoint_void: 4055 case Intrinsic::experimental_patchpoint_i64: 4056 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4057 return TTI::TCC_Free; 4058 break; 4059 } 4060 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4061 } 4062 4063 unsigned 4064 X86TTIImpl::getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind) { 4065 if (CostKind != TTI::TCK_RecipThroughput) 4066 return Opcode == Instruction::PHI ? 0 : 1; 4067 // Branches are assumed to be predicted. 4068 return CostKind == TTI::TCK_RecipThroughput ? 0 : 1; 4069 } 4070 4071 int X86TTIImpl::getGatherOverhead() const { 4072 // Some CPUs have more overhead for gather. The specified overhead is relative 4073 // to the Load operation. "2" is the number provided by Intel architects. This 4074 // parameter is used for cost estimation of Gather Op and comparison with 4075 // other alternatives. 4076 // TODO: Remove the explicit hasAVX512()?, That would mean we would only 4077 // enable gather with a -march. 4078 if (ST->hasAVX512() || (ST->hasAVX2() && ST->hasFastGather())) 4079 return 2; 4080 4081 return 1024; 4082 } 4083 4084 int X86TTIImpl::getScatterOverhead() const { 4085 if (ST->hasAVX512()) 4086 return 2; 4087 4088 return 1024; 4089 } 4090 4091 // Return an average cost of Gather / Scatter instruction, maybe improved later. 4092 // FIXME: Add TargetCostKind support. 4093 int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, const Value *Ptr, 4094 Align Alignment, unsigned AddressSpace) { 4095 4096 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 4097 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4098 4099 // Try to reduce index size from 64 bit (default for GEP) 4100 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 4101 // operation will use 16 x 64 indices which do not fit in a zmm and needs 4102 // to split. Also check that the base pointer is the same for all lanes, 4103 // and that there's at most one variable index. 4104 auto getIndexSizeInBits = [](const Value *Ptr, const DataLayout &DL) { 4105 unsigned IndexSize = DL.getPointerSizeInBits(); 4106 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 4107 if (IndexSize < 64 || !GEP) 4108 return IndexSize; 4109 4110 unsigned NumOfVarIndices = 0; 4111 const Value *Ptrs = GEP->getPointerOperand(); 4112 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 4113 return IndexSize; 4114 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 4115 if (isa<Constant>(GEP->getOperand(i))) 4116 continue; 4117 Type *IndxTy = GEP->getOperand(i)->getType(); 4118 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 4119 IndxTy = IndexVTy->getElementType(); 4120 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 4121 !isa<SExtInst>(GEP->getOperand(i))) || 4122 ++NumOfVarIndices > 1) 4123 return IndexSize; // 64 4124 } 4125 return (unsigned)32; 4126 }; 4127 4128 // Trying to reduce IndexSize to 32 bits for vector 16. 4129 // By default the IndexSize is equal to pointer size. 4130 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 4131 ? getIndexSizeInBits(Ptr, DL) 4132 : DL.getPointerSizeInBits(); 4133 4134 auto *IndexVTy = FixedVectorType::get( 4135 IntegerType::get(SrcVTy->getContext(), IndexSize), VF); 4136 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy); 4137 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy); 4138 int SplitFactor = std::max(IdxsLT.first, SrcLT.first); 4139 if (SplitFactor > 1) { 4140 // Handle splitting of vector of pointers 4141 auto *SplitSrcTy = 4142 FixedVectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 4143 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 4144 AddressSpace); 4145 } 4146 4147 // The gather / scatter cost is given by Intel architects. It is a rough 4148 // number since we are looking at one instruction in a time. 4149 const int GSOverhead = (Opcode == Instruction::Load) 4150 ? getGatherOverhead() 4151 : getScatterOverhead(); 4152 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4153 MaybeAlign(Alignment), AddressSpace, 4154 TTI::TCK_RecipThroughput); 4155 } 4156 4157 /// Return the cost of full scalarization of gather / scatter operation. 4158 /// 4159 /// Opcode - Load or Store instruction. 4160 /// SrcVTy - The type of the data vector that should be gathered or scattered. 4161 /// VariableMask - The mask is non-constant at compile time. 4162 /// Alignment - Alignment for one element. 4163 /// AddressSpace - pointer[s] address space. 4164 /// 4165 /// FIXME: Add TargetCostKind support. 4166 int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 4167 bool VariableMask, Align Alignment, 4168 unsigned AddressSpace) { 4169 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4170 APInt DemandedElts = APInt::getAllOnesValue(VF); 4171 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4172 4173 int MaskUnpackCost = 0; 4174 if (VariableMask) { 4175 auto *MaskTy = 4176 FixedVectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 4177 MaskUnpackCost = 4178 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 4179 int ScalarCompareCost = getCmpSelInstrCost( 4180 Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), nullptr, 4181 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4182 int BranchCost = getCFInstrCost(Instruction::Br, CostKind); 4183 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 4184 } 4185 4186 // The cost of the scalar loads/stores. 4187 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4188 MaybeAlign(Alignment), AddressSpace, 4189 CostKind); 4190 4191 int InsertExtractCost = 0; 4192 if (Opcode == Instruction::Load) 4193 for (unsigned i = 0; i < VF; ++i) 4194 // Add the cost of inserting each scalar load into the vector 4195 InsertExtractCost += 4196 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 4197 else 4198 for (unsigned i = 0; i < VF; ++i) 4199 // Add the cost of extracting each element out of the data vector 4200 InsertExtractCost += 4201 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 4202 4203 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 4204 } 4205 4206 /// Calculate the cost of Gather / Scatter operation 4207 int X86TTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *SrcVTy, 4208 const Value *Ptr, bool VariableMask, 4209 Align Alignment, 4210 TTI::TargetCostKind CostKind, 4211 const Instruction *I = nullptr) { 4212 if (CostKind != TTI::TCK_RecipThroughput) { 4213 if ((Opcode == Instruction::Load && 4214 isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4215 (Opcode == Instruction::Store && 4216 isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4217 return 1; 4218 return BaseT::getGatherScatterOpCost(Opcode, SrcVTy, Ptr, VariableMask, 4219 Alignment, CostKind, I); 4220 } 4221 4222 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 4223 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4224 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 4225 if (!PtrTy && Ptr->getType()->isVectorTy()) 4226 PtrTy = dyn_cast<PointerType>( 4227 cast<VectorType>(Ptr->getType())->getElementType()); 4228 assert(PtrTy && "Unexpected type for Ptr argument"); 4229 unsigned AddressSpace = PtrTy->getAddressSpace(); 4230 4231 bool Scalarize = false; 4232 if ((Opcode == Instruction::Load && 4233 !isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4234 (Opcode == Instruction::Store && 4235 !isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4236 Scalarize = true; 4237 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 4238 // Vector-4 of gather/scatter instruction does not exist on KNL. 4239 // We can extend it to 8 elements, but zeroing upper bits of 4240 // the mask vector will add more instructions. Right now we give the scalar 4241 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 4242 // is better in the VariableMask case. 4243 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 4244 Scalarize = true; 4245 4246 if (Scalarize) 4247 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 4248 AddressSpace); 4249 4250 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 4251 } 4252 4253 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 4254 TargetTransformInfo::LSRCost &C2) { 4255 // X86 specific here are "instruction number 1st priority". 4256 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 4257 C1.NumIVMuls, C1.NumBaseAdds, 4258 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 4259 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 4260 C2.NumIVMuls, C2.NumBaseAdds, 4261 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 4262 } 4263 4264 bool X86TTIImpl::canMacroFuseCmp() { 4265 return ST->hasMacroFusion() || ST->hasBranchFusion(); 4266 } 4267 4268 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, Align Alignment) { 4269 if (!ST->hasAVX()) 4270 return false; 4271 4272 // The backend can't handle a single element vector. 4273 if (isa<VectorType>(DataTy) && 4274 cast<FixedVectorType>(DataTy)->getNumElements() == 1) 4275 return false; 4276 Type *ScalarTy = DataTy->getScalarType(); 4277 4278 if (ScalarTy->isPointerTy()) 4279 return true; 4280 4281 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4282 return true; 4283 4284 if (!ScalarTy->isIntegerTy()) 4285 return false; 4286 4287 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4288 return IntWidth == 32 || IntWidth == 64 || 4289 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 4290 } 4291 4292 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, Align Alignment) { 4293 return isLegalMaskedLoad(DataType, Alignment); 4294 } 4295 4296 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 4297 unsigned DataSize = DL.getTypeStoreSize(DataType); 4298 // The only supported nontemporal loads are for aligned vectors of 16 or 32 4299 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 4300 // (the equivalent stores only require AVX). 4301 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 4302 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 4303 4304 return false; 4305 } 4306 4307 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 4308 unsigned DataSize = DL.getTypeStoreSize(DataType); 4309 4310 // SSE4A supports nontemporal stores of float and double at arbitrary 4311 // alignment. 4312 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 4313 return true; 4314 4315 // Besides the SSE4A subtarget exception above, only aligned stores are 4316 // available nontemporaly on any other subtarget. And only stores with a size 4317 // of 4..32 bytes (powers of 2, only) are permitted. 4318 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 4319 !isPowerOf2_32(DataSize)) 4320 return false; 4321 4322 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 4323 // loads require AVX2). 4324 if (DataSize == 32) 4325 return ST->hasAVX(); 4326 else if (DataSize == 16) 4327 return ST->hasSSE1(); 4328 return true; 4329 } 4330 4331 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 4332 if (!isa<VectorType>(DataTy)) 4333 return false; 4334 4335 if (!ST->hasAVX512()) 4336 return false; 4337 4338 // The backend can't handle a single element vector. 4339 if (cast<FixedVectorType>(DataTy)->getNumElements() == 1) 4340 return false; 4341 4342 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 4343 4344 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4345 return true; 4346 4347 if (!ScalarTy->isIntegerTy()) 4348 return false; 4349 4350 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4351 return IntWidth == 32 || IntWidth == 64 || 4352 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 4353 } 4354 4355 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 4356 return isLegalMaskedExpandLoad(DataTy); 4357 } 4358 4359 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, Align Alignment) { 4360 // Some CPUs have better gather performance than others. 4361 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 4362 // enable gather with a -march. 4363 if (!(ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()))) 4364 return false; 4365 4366 // This function is called now in two cases: from the Loop Vectorizer 4367 // and from the Scalarizer. 4368 // When the Loop Vectorizer asks about legality of the feature, 4369 // the vectorization factor is not calculated yet. The Loop Vectorizer 4370 // sends a scalar type and the decision is based on the width of the 4371 // scalar element. 4372 // Later on, the cost model will estimate usage this intrinsic based on 4373 // the vector type. 4374 // The Scalarizer asks again about legality. It sends a vector type. 4375 // In this case we can reject non-power-of-2 vectors. 4376 // We also reject single element vectors as the type legalizer can't 4377 // scalarize it. 4378 if (auto *DataVTy = dyn_cast<FixedVectorType>(DataTy)) { 4379 unsigned NumElts = DataVTy->getNumElements(); 4380 if (NumElts == 1) 4381 return false; 4382 } 4383 Type *ScalarTy = DataTy->getScalarType(); 4384 if (ScalarTy->isPointerTy()) 4385 return true; 4386 4387 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4388 return true; 4389 4390 if (!ScalarTy->isIntegerTy()) 4391 return false; 4392 4393 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4394 return IntWidth == 32 || IntWidth == 64; 4395 } 4396 4397 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, Align Alignment) { 4398 // AVX2 doesn't support scatter 4399 if (!ST->hasAVX512()) 4400 return false; 4401 return isLegalMaskedGather(DataType, Alignment); 4402 } 4403 4404 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 4405 EVT VT = TLI->getValueType(DL, DataType); 4406 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 4407 } 4408 4409 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 4410 return false; 4411 } 4412 4413 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 4414 const Function *Callee) const { 4415 const TargetMachine &TM = getTLI()->getTargetMachine(); 4416 4417 // Work this as a subsetting of subtarget features. 4418 const FeatureBitset &CallerBits = 4419 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 4420 const FeatureBitset &CalleeBits = 4421 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 4422 4423 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 4424 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 4425 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 4426 } 4427 4428 bool X86TTIImpl::areFunctionArgsABICompatible( 4429 const Function *Caller, const Function *Callee, 4430 SmallPtrSetImpl<Argument *> &Args) const { 4431 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args)) 4432 return false; 4433 4434 // If we get here, we know the target features match. If one function 4435 // considers 512-bit vectors legal and the other does not, consider them 4436 // incompatible. 4437 const TargetMachine &TM = getTLI()->getTargetMachine(); 4438 4439 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 4440 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs()) 4441 return true; 4442 4443 // Consider the arguments compatible if they aren't vectors or aggregates. 4444 // FIXME: Look at the size of vectors. 4445 // FIXME: Look at the element types of aggregates to see if there are vectors. 4446 // FIXME: The API of this function seems intended to allow arguments 4447 // to be removed from the set, but the caller doesn't check if the set 4448 // becomes empty so that may not work in practice. 4449 return llvm::none_of(Args, [](Argument *A) { 4450 auto *EltTy = cast<PointerType>(A->getType())->getElementType(); 4451 return EltTy->isVectorTy() || EltTy->isAggregateType(); 4452 }); 4453 } 4454 4455 X86TTIImpl::TTI::MemCmpExpansionOptions 4456 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 4457 TTI::MemCmpExpansionOptions Options; 4458 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 4459 Options.NumLoadsPerBlock = 2; 4460 // All GPR and vector loads can be unaligned. 4461 Options.AllowOverlappingLoads = true; 4462 if (IsZeroCmp) { 4463 // Only enable vector loads for equality comparison. Right now the vector 4464 // version is not as fast for three way compare (see #33329). 4465 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 4466 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 4467 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 4468 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 4469 } 4470 if (ST->is64Bit()) { 4471 Options.LoadSizes.push_back(8); 4472 } 4473 Options.LoadSizes.push_back(4); 4474 Options.LoadSizes.push_back(2); 4475 Options.LoadSizes.push_back(1); 4476 return Options; 4477 } 4478 4479 bool X86TTIImpl::enableInterleavedAccessVectorization() { 4480 // TODO: We expect this to be beneficial regardless of arch, 4481 // but there are currently some unexplained performance artifacts on Atom. 4482 // As a temporary solution, disable on Atom. 4483 return !(ST->isAtom()); 4484 } 4485 4486 // Get estimation for interleaved load/store operations for AVX2. 4487 // \p Factor is the interleaved-access factor (stride) - number of 4488 // (interleaved) elements in the group. 4489 // \p Indices contains the indices for a strided load: when the 4490 // interleaved load has gaps they indicate which elements are used. 4491 // If Indices is empty (or if the number of indices is equal to the size 4492 // of the interleaved-access as given in \p Factor) the access has no gaps. 4493 // 4494 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 4495 // computing the cost using a generic formula as a function of generic 4496 // shuffles. We therefore use a lookup table instead, filled according to 4497 // the instruction sequences that codegen currently generates. 4498 int X86TTIImpl::getInterleavedMemoryOpCostAVX2( 4499 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 4500 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 4501 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 4502 4503 if (UseMaskForCond || UseMaskForGaps) 4504 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4505 Alignment, AddressSpace, CostKind, 4506 UseMaskForCond, UseMaskForGaps); 4507 4508 // We currently Support only fully-interleaved groups, with no gaps. 4509 // TODO: Support also strided loads (interleaved-groups with gaps). 4510 if (Indices.size() && Indices.size() != Factor) 4511 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4512 Alignment, AddressSpace, 4513 CostKind); 4514 4515 // VecTy for interleave memop is <VF*Factor x Elt>. 4516 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4517 // VecTy = <12 x i32>. 4518 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4519 4520 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 4521 // the VF=2, while v2i128 is an unsupported MVT vector type 4522 // (see MachineValueType.h::getVectorVT()). 4523 if (!LegalVT.isVector()) 4524 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4525 Alignment, AddressSpace, 4526 CostKind); 4527 4528 unsigned VF = VecTy->getNumElements() / Factor; 4529 Type *ScalarTy = VecTy->getElementType(); 4530 4531 // Calculate the number of memory operations (NumOfMemOps), required 4532 // for load/store the VecTy. 4533 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4534 unsigned LegalVTSize = LegalVT.getStoreSize(); 4535 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4536 4537 // Get the cost of one memory operation. 4538 auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(), 4539 LegalVT.getVectorNumElements()); 4540 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 4541 MaybeAlign(Alignment), AddressSpace, 4542 CostKind); 4543 4544 auto *VT = FixedVectorType::get(ScalarTy, VF); 4545 EVT ETy = TLI->getValueType(DL, VT); 4546 if (!ETy.isSimple()) 4547 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4548 Alignment, AddressSpace, 4549 CostKind); 4550 4551 // TODO: Complete for other data-types and strides. 4552 // Each combination of Stride, ElementTy and VF results in a different 4553 // sequence; The cost tables are therefore accessed with: 4554 // Factor (stride) and VectorType=VFxElemType. 4555 // The Cost accounts only for the shuffle sequence; 4556 // The cost of the loads/stores is accounted for separately. 4557 // 4558 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 4559 { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64 4560 { 2, MVT::v4f64, 6 }, //(load 8f64 and) deinterleave into 2 x 4f64 4561 4562 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8 4563 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8 4564 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8 4565 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8 4566 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8 4567 { 3, MVT::v8f32, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32 4568 4569 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8 4570 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8 4571 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8 4572 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8 4573 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8 4574 4575 { 8, MVT::v8f32, 40 } //(load 64f32 and)deinterleave into 8 x 8f32 4576 }; 4577 4578 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 4579 { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store) 4580 { 2, MVT::v4f64, 6 }, //interleave into 2 x 4f64 into 8f64 (and store) 4581 4582 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store) 4583 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store) 4584 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store) 4585 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store) 4586 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store) 4587 4588 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store) 4589 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store) 4590 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store) 4591 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store) 4592 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store) 4593 }; 4594 4595 if (Opcode == Instruction::Load) { 4596 if (const auto *Entry = 4597 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 4598 return NumOfMemOps * MemOpCost + Entry->Cost; 4599 } else { 4600 assert(Opcode == Instruction::Store && 4601 "Expected Store Instruction at this point"); 4602 if (const auto *Entry = 4603 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 4604 return NumOfMemOps * MemOpCost + Entry->Cost; 4605 } 4606 4607 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4608 Alignment, AddressSpace, CostKind); 4609 } 4610 4611 // Get estimation for interleaved load/store operations and strided load. 4612 // \p Indices contains indices for strided load. 4613 // \p Factor - the factor of interleaving. 4614 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 4615 int X86TTIImpl::getInterleavedMemoryOpCostAVX512( 4616 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 4617 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 4618 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 4619 4620 if (UseMaskForCond || UseMaskForGaps) 4621 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4622 Alignment, AddressSpace, CostKind, 4623 UseMaskForCond, UseMaskForGaps); 4624 4625 // VecTy for interleave memop is <VF*Factor x Elt>. 4626 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4627 // VecTy = <12 x i32>. 4628 4629 // Calculate the number of memory operations (NumOfMemOps), required 4630 // for load/store the VecTy. 4631 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4632 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4633 unsigned LegalVTSize = LegalVT.getStoreSize(); 4634 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4635 4636 // Get the cost of one memory operation. 4637 auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(), 4638 LegalVT.getVectorNumElements()); 4639 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 4640 MaybeAlign(Alignment), AddressSpace, 4641 CostKind); 4642 4643 unsigned VF = VecTy->getNumElements() / Factor; 4644 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 4645 4646 if (Opcode == Instruction::Load) { 4647 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 4648 // contain the cost of the optimized shuffle sequence that the 4649 // X86InterleavedAccess pass will generate. 4650 // The cost of loads and stores are computed separately from the table. 4651 4652 // X86InterleavedAccess support only the following interleaved-access group. 4653 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 4654 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 4655 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 4656 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 4657 }; 4658 4659 if (const auto *Entry = 4660 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 4661 return NumOfMemOps * MemOpCost + Entry->Cost; 4662 //If an entry does not exist, fallback to the default implementation. 4663 4664 // Kind of shuffle depends on number of loaded values. 4665 // If we load the entire data in one register, we can use a 1-src shuffle. 4666 // Otherwise, we'll merge 2 sources in each operation. 4667 TTI::ShuffleKind ShuffleKind = 4668 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 4669 4670 unsigned ShuffleCost = 4671 getShuffleCost(ShuffleKind, SingleMemOpTy, None, 0, nullptr); 4672 4673 unsigned NumOfLoadsInInterleaveGrp = 4674 Indices.size() ? Indices.size() : Factor; 4675 auto *ResultTy = FixedVectorType::get(VecTy->getElementType(), 4676 VecTy->getNumElements() / Factor); 4677 unsigned NumOfResults = 4678 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 4679 NumOfLoadsInInterleaveGrp; 4680 4681 // About a half of the loads may be folded in shuffles when we have only 4682 // one result. If we have more than one result, we do not fold loads at all. 4683 unsigned NumOfUnfoldedLoads = 4684 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 4685 4686 // Get a number of shuffle operations per result. 4687 unsigned NumOfShufflesPerResult = 4688 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 4689 4690 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4691 // When we have more than one destination, we need additional instructions 4692 // to keep sources. 4693 unsigned NumOfMoves = 0; 4694 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 4695 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 4696 4697 int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 4698 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 4699 4700 return Cost; 4701 } 4702 4703 // Store. 4704 assert(Opcode == Instruction::Store && 4705 "Expected Store Instruction at this point"); 4706 // X86InterleavedAccess support only the following interleaved-access group. 4707 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 4708 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 4709 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 4710 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 4711 4712 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 4713 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 4714 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 4715 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 4716 }; 4717 4718 if (const auto *Entry = 4719 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 4720 return NumOfMemOps * MemOpCost + Entry->Cost; 4721 //If an entry does not exist, fallback to the default implementation. 4722 4723 // There is no strided stores meanwhile. And store can't be folded in 4724 // shuffle. 4725 unsigned NumOfSources = Factor; // The number of values to be merged. 4726 unsigned ShuffleCost = 4727 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, None, 0, nullptr); 4728 unsigned NumOfShufflesPerStore = NumOfSources - 1; 4729 4730 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4731 // We need additional instructions to keep sources. 4732 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 4733 int Cost = NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 4734 NumOfMoves; 4735 return Cost; 4736 } 4737 4738 int X86TTIImpl::getInterleavedMemoryOpCost( 4739 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, 4740 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, 4741 bool UseMaskForCond, bool UseMaskForGaps) { 4742 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 4743 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 4744 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 4745 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 4746 return true; 4747 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 4748 return HasBW; 4749 return false; 4750 }; 4751 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 4752 return getInterleavedMemoryOpCostAVX512( 4753 Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment, 4754 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 4755 if (ST->hasAVX2()) 4756 return getInterleavedMemoryOpCostAVX2( 4757 Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment, 4758 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 4759 4760 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4761 Alignment, AddressSpace, CostKind, 4762 UseMaskForCond, UseMaskForGaps); 4763 } 4764