1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // X86 cost model. 56 // 57 //===----------------------------------------------------------------------===// 58 59 TargetTransformInfo::PopcntSupportKind 60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 61 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 62 // TODO: Currently the __builtin_popcount() implementation using SSE3 63 // instructions is inefficient. Once the problem is fixed, we should 64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 66 } 67 68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 69 TargetTransformInfo::CacheLevel Level) const { 70 switch (Level) { 71 case TargetTransformInfo::CacheLevel::L1D: 72 // - Penryn 73 // - Nehalem 74 // - Westmere 75 // - Sandy Bridge 76 // - Ivy Bridge 77 // - Haswell 78 // - Broadwell 79 // - Skylake 80 // - Kabylake 81 return 32 * 1024; // 32 KByte 82 case TargetTransformInfo::CacheLevel::L2D: 83 // - Penryn 84 // - Nehalem 85 // - Westmere 86 // - Sandy Bridge 87 // - Ivy Bridge 88 // - Haswell 89 // - Broadwell 90 // - Skylake 91 // - Kabylake 92 return 256 * 1024; // 256 KByte 93 } 94 95 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 96 } 97 98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 99 TargetTransformInfo::CacheLevel Level) const { 100 // - Penryn 101 // - Nehalem 102 // - Westmere 103 // - Sandy Bridge 104 // - Ivy Bridge 105 // - Haswell 106 // - Broadwell 107 // - Skylake 108 // - Kabylake 109 switch (Level) { 110 case TargetTransformInfo::CacheLevel::L1D: 111 LLVM_FALLTHROUGH; 112 case TargetTransformInfo::CacheLevel::L2D: 113 return 8; 114 } 115 116 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 117 } 118 119 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 120 bool Vector = (ClassID == 1); 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const { 133 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 134 if (Vector) { 135 if (ST->hasAVX512() && PreferVectorWidth >= 512) 136 return 512; 137 if (ST->hasAVX() && PreferVectorWidth >= 256) 138 return 256; 139 if (ST->hasSSE1() && PreferVectorWidth >= 128) 140 return 128; 141 return 0; 142 } 143 144 if (ST->is64Bit()) 145 return 64; 146 147 return 32; 148 } 149 150 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 151 return getRegisterBitWidth(true); 152 } 153 154 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 155 // If the loop will not be vectorized, don't interleave the loop. 156 // Let regular unroll to unroll the loop, which saves the overflow 157 // check and memory check cost. 158 if (VF == 1) 159 return 1; 160 161 if (ST->isAtom()) 162 return 1; 163 164 // Sandybridge and Haswell have multiple execution ports and pipelined 165 // vector units. 166 if (ST->hasAVX()) 167 return 4; 168 169 return 2; 170 } 171 172 int X86TTIImpl::getArithmeticInstrCost(unsigned Opcode, Type *Ty, 173 TTI::TargetCostKind CostKind, 174 TTI::OperandValueKind Op1Info, 175 TTI::OperandValueKind Op2Info, 176 TTI::OperandValueProperties Opd1PropInfo, 177 TTI::OperandValueProperties Opd2PropInfo, 178 ArrayRef<const Value *> Args, 179 const Instruction *CxtI) { 180 // TODO: Handle more cost kinds. 181 if (CostKind != TTI::TCK_RecipThroughput) 182 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, 183 Op2Info, Opd1PropInfo, 184 Opd2PropInfo, Args, CxtI); 185 // Legalize the type. 186 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 187 188 int ISD = TLI->InstructionOpcodeToISD(Opcode); 189 assert(ISD && "Invalid opcode"); 190 191 static const CostTblEntry GLMCostTable[] = { 192 { ISD::FDIV, MVT::f32, 18 }, // divss 193 { ISD::FDIV, MVT::v4f32, 35 }, // divps 194 { ISD::FDIV, MVT::f64, 33 }, // divsd 195 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 196 }; 197 198 if (ST->useGLMDivSqrtCosts()) 199 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 200 LT.second)) 201 return LT.first * Entry->Cost; 202 203 static const CostTblEntry SLMCostTable[] = { 204 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 205 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 206 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. 207 { ISD::FMUL, MVT::f64, 2 }, // mulsd 208 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 209 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 210 { ISD::FDIV, MVT::f32, 17 }, // divss 211 { ISD::FDIV, MVT::v4f32, 39 }, // divps 212 { ISD::FDIV, MVT::f64, 32 }, // divsd 213 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 214 { ISD::FADD, MVT::v2f64, 2 }, // addpd 215 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 216 // v2i64/v4i64 mul is custom lowered as a series of long: 217 // multiplies(3), shifts(3) and adds(2) 218 // slm muldq version throughput is 2 and addq throughput 4 219 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 220 // 3X4 (addq throughput) = 17 221 { ISD::MUL, MVT::v2i64, 17 }, 222 // slm addq\subq throughput is 4 223 { ISD::ADD, MVT::v2i64, 4 }, 224 { ISD::SUB, MVT::v2i64, 4 }, 225 }; 226 227 if (ST->isSLM()) { 228 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 229 // Check if the operands can be shrinked into a smaller datatype. 230 bool Op1Signed = false; 231 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 232 bool Op2Signed = false; 233 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 234 235 bool signedMode = Op1Signed | Op2Signed; 236 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 237 238 if (OpMinSize <= 7) 239 return LT.first * 3; // pmullw/sext 240 if (!signedMode && OpMinSize <= 8) 241 return LT.first * 3; // pmullw/zext 242 if (OpMinSize <= 15) 243 return LT.first * 5; // pmullw/pmulhw/pshuf 244 if (!signedMode && OpMinSize <= 16) 245 return LT.first * 5; // pmullw/pmulhw/pshuf 246 } 247 248 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 249 LT.second)) { 250 return LT.first * Entry->Cost; 251 } 252 } 253 254 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 255 ISD == ISD::UREM) && 256 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 257 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 258 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 259 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 260 // On X86, vector signed division by constants power-of-two are 261 // normally expanded to the sequence SRA + SRL + ADD + SRA. 262 // The OperandValue properties may not be the same as that of the previous 263 // operation; conservatively assume OP_None. 264 int Cost = 265 2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Op1Info, 266 Op2Info, 267 TargetTransformInfo::OP_None, 268 TargetTransformInfo::OP_None); 269 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 270 Op2Info, 271 TargetTransformInfo::OP_None, 272 TargetTransformInfo::OP_None); 273 Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind, Op1Info, 274 Op2Info, 275 TargetTransformInfo::OP_None, 276 TargetTransformInfo::OP_None); 277 278 if (ISD == ISD::SREM) { 279 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 280 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info, 281 Op2Info); 282 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info, 283 Op2Info); 284 } 285 286 return Cost; 287 } 288 289 // Vector unsigned division/remainder will be simplified to shifts/masks. 290 if (ISD == ISD::UDIV) 291 return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, 292 Op1Info, Op2Info, 293 TargetTransformInfo::OP_None, 294 TargetTransformInfo::OP_None); 295 296 else // UREM 297 return getArithmeticInstrCost(Instruction::And, Ty, CostKind, 298 Op1Info, Op2Info, 299 TargetTransformInfo::OP_None, 300 TargetTransformInfo::OP_None); 301 } 302 303 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 304 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 305 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 306 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 307 }; 308 309 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 310 ST->hasBWI()) { 311 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 312 LT.second)) 313 return LT.first * Entry->Cost; 314 } 315 316 static const CostTblEntry AVX512UniformConstCostTable[] = { 317 { ISD::SRA, MVT::v2i64, 1 }, 318 { ISD::SRA, MVT::v4i64, 1 }, 319 { ISD::SRA, MVT::v8i64, 1 }, 320 321 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 322 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 323 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 324 }; 325 326 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 327 ST->hasAVX512()) { 328 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 329 LT.second)) 330 return LT.first * Entry->Cost; 331 } 332 333 static const CostTblEntry AVX2UniformConstCostTable[] = { 334 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 335 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 336 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 337 338 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 339 }; 340 341 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 342 ST->hasAVX2()) { 343 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 344 LT.second)) 345 return LT.first * Entry->Cost; 346 } 347 348 static const CostTblEntry SSE2UniformConstCostTable[] = { 349 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 350 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 351 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 352 353 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 354 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 355 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 356 }; 357 358 // XOP has faster vXi8 shifts. 359 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 360 ST->hasSSE2() && !ST->hasXOP()) { 361 if (const auto *Entry = 362 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 363 return LT.first * Entry->Cost; 364 } 365 366 static const CostTblEntry AVX512BWConstCostTable[] = { 367 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 368 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 369 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 370 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 371 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 372 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 373 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 374 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 375 }; 376 377 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 378 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 379 ST->hasBWI()) { 380 if (const auto *Entry = 381 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 382 return LT.first * Entry->Cost; 383 } 384 385 static const CostTblEntry AVX512ConstCostTable[] = { 386 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 387 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 388 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 389 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 390 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 391 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 392 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 393 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 394 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 395 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 396 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 397 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 398 }; 399 400 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 401 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 402 ST->hasAVX512()) { 403 if (const auto *Entry = 404 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 405 return LT.first * Entry->Cost; 406 } 407 408 static const CostTblEntry AVX2ConstCostTable[] = { 409 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 410 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 411 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 412 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 413 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 414 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 415 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 416 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 417 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 418 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 419 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 420 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 421 }; 422 423 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 424 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 425 ST->hasAVX2()) { 426 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 427 return LT.first * Entry->Cost; 428 } 429 430 static const CostTblEntry SSE2ConstCostTable[] = { 431 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 432 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 433 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 434 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 435 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 436 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 437 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 438 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 439 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 440 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 441 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 442 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 443 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 444 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 445 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 446 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 447 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 448 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 449 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 450 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 451 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 452 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 453 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 454 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 455 }; 456 457 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 458 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 459 ST->hasSSE2()) { 460 // pmuldq sequence. 461 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 462 return LT.first * 32; 463 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 464 return LT.first * 38; 465 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 466 return LT.first * 15; 467 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 468 return LT.first * 20; 469 470 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 471 return LT.first * Entry->Cost; 472 } 473 474 static const CostTblEntry AVX512BWShiftCostTable[] = { 475 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 476 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 477 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 478 479 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 480 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 481 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 482 483 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 484 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 485 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 486 }; 487 488 if (ST->hasBWI()) 489 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 490 return LT.first * Entry->Cost; 491 492 static const CostTblEntry AVX2UniformCostTable[] = { 493 // Uniform splats are cheaper for the following instructions. 494 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 495 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 496 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 497 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 498 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 499 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 500 }; 501 502 if (ST->hasAVX2() && 503 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 504 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 505 if (const auto *Entry = 506 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 507 return LT.first * Entry->Cost; 508 } 509 510 static const CostTblEntry SSE2UniformCostTable[] = { 511 // Uniform splats are cheaper for the following instructions. 512 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 513 { ISD::SHL, MVT::v4i32, 1 }, // pslld 514 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 515 516 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 517 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 518 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 519 520 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 521 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 522 }; 523 524 if (ST->hasSSE2() && 525 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 526 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 527 if (const auto *Entry = 528 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 529 return LT.first * Entry->Cost; 530 } 531 532 static const CostTblEntry AVX512DQCostTable[] = { 533 { ISD::MUL, MVT::v2i64, 1 }, 534 { ISD::MUL, MVT::v4i64, 1 }, 535 { ISD::MUL, MVT::v8i64, 1 } 536 }; 537 538 // Look for AVX512DQ lowering tricks for custom cases. 539 if (ST->hasDQI()) 540 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 541 return LT.first * Entry->Cost; 542 543 static const CostTblEntry AVX512BWCostTable[] = { 544 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 545 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 546 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 547 548 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence. 549 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence. 550 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence. 551 }; 552 553 // Look for AVX512BW lowering tricks for custom cases. 554 if (ST->hasBWI()) 555 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 556 return LT.first * Entry->Cost; 557 558 static const CostTblEntry AVX512CostTable[] = { 559 { ISD::SHL, MVT::v16i32, 1 }, 560 { ISD::SRL, MVT::v16i32, 1 }, 561 { ISD::SRA, MVT::v16i32, 1 }, 562 563 { ISD::SHL, MVT::v8i64, 1 }, 564 { ISD::SRL, MVT::v8i64, 1 }, 565 566 { ISD::SRA, MVT::v2i64, 1 }, 567 { ISD::SRA, MVT::v4i64, 1 }, 568 { ISD::SRA, MVT::v8i64, 1 }, 569 570 { ISD::MUL, MVT::v64i8, 26 }, // extend/pmullw/trunc sequence. 571 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence. 572 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence. 573 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 574 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 575 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 576 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add 577 578 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 579 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 580 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 581 582 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 583 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 584 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 585 }; 586 587 if (ST->hasAVX512()) 588 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 589 return LT.first * Entry->Cost; 590 591 static const CostTblEntry AVX2ShiftCostTable[] = { 592 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 593 // customize them to detect the cases where shift amount is a scalar one. 594 { ISD::SHL, MVT::v4i32, 1 }, 595 { ISD::SRL, MVT::v4i32, 1 }, 596 { ISD::SRA, MVT::v4i32, 1 }, 597 { ISD::SHL, MVT::v8i32, 1 }, 598 { ISD::SRL, MVT::v8i32, 1 }, 599 { ISD::SRA, MVT::v8i32, 1 }, 600 { ISD::SHL, MVT::v2i64, 1 }, 601 { ISD::SRL, MVT::v2i64, 1 }, 602 { ISD::SHL, MVT::v4i64, 1 }, 603 { ISD::SRL, MVT::v4i64, 1 }, 604 }; 605 606 if (ST->hasAVX512()) { 607 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 608 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 609 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 610 // On AVX512, a packed v32i16 shift left by a constant build_vector 611 // is lowered into a vector multiply (vpmullw). 612 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 613 Op1Info, Op2Info, 614 TargetTransformInfo::OP_None, 615 TargetTransformInfo::OP_None); 616 } 617 618 // Look for AVX2 lowering tricks. 619 if (ST->hasAVX2()) { 620 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 621 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 622 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 623 // On AVX2, a packed v16i16 shift left by a constant build_vector 624 // is lowered into a vector multiply (vpmullw). 625 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 626 Op1Info, Op2Info, 627 TargetTransformInfo::OP_None, 628 TargetTransformInfo::OP_None); 629 630 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 631 return LT.first * Entry->Cost; 632 } 633 634 static const CostTblEntry XOPShiftCostTable[] = { 635 // 128bit shifts take 1cy, but right shifts require negation beforehand. 636 { ISD::SHL, MVT::v16i8, 1 }, 637 { ISD::SRL, MVT::v16i8, 2 }, 638 { ISD::SRA, MVT::v16i8, 2 }, 639 { ISD::SHL, MVT::v8i16, 1 }, 640 { ISD::SRL, MVT::v8i16, 2 }, 641 { ISD::SRA, MVT::v8i16, 2 }, 642 { ISD::SHL, MVT::v4i32, 1 }, 643 { ISD::SRL, MVT::v4i32, 2 }, 644 { ISD::SRA, MVT::v4i32, 2 }, 645 { ISD::SHL, MVT::v2i64, 1 }, 646 { ISD::SRL, MVT::v2i64, 2 }, 647 { ISD::SRA, MVT::v2i64, 2 }, 648 // 256bit shifts require splitting if AVX2 didn't catch them above. 649 { ISD::SHL, MVT::v32i8, 2+2 }, 650 { ISD::SRL, MVT::v32i8, 4+2 }, 651 { ISD::SRA, MVT::v32i8, 4+2 }, 652 { ISD::SHL, MVT::v16i16, 2+2 }, 653 { ISD::SRL, MVT::v16i16, 4+2 }, 654 { ISD::SRA, MVT::v16i16, 4+2 }, 655 { ISD::SHL, MVT::v8i32, 2+2 }, 656 { ISD::SRL, MVT::v8i32, 4+2 }, 657 { ISD::SRA, MVT::v8i32, 4+2 }, 658 { ISD::SHL, MVT::v4i64, 2+2 }, 659 { ISD::SRL, MVT::v4i64, 4+2 }, 660 { ISD::SRA, MVT::v4i64, 4+2 }, 661 }; 662 663 // Look for XOP lowering tricks. 664 if (ST->hasXOP()) { 665 // If the right shift is constant then we'll fold the negation so 666 // it's as cheap as a left shift. 667 int ShiftISD = ISD; 668 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 669 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 670 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 671 ShiftISD = ISD::SHL; 672 if (const auto *Entry = 673 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 674 return LT.first * Entry->Cost; 675 } 676 677 static const CostTblEntry SSE2UniformShiftCostTable[] = { 678 // Uniform splats are cheaper for the following instructions. 679 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 680 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 681 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 682 683 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 684 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 685 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 686 687 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 688 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 689 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 690 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 691 }; 692 693 if (ST->hasSSE2() && 694 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 695 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 696 697 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 698 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 699 return LT.first * 4; // 2*psrad + shuffle. 700 701 if (const auto *Entry = 702 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 703 return LT.first * Entry->Cost; 704 } 705 706 if (ISD == ISD::SHL && 707 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 708 MVT VT = LT.second; 709 // Vector shift left by non uniform constant can be lowered 710 // into vector multiply. 711 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 712 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 713 ISD = ISD::MUL; 714 } 715 716 static const CostTblEntry AVX2CostTable[] = { 717 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. 718 { ISD::SHL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. 719 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 720 { ISD::SHL, MVT::v32i16, 20 }, // 2*extend/vpsrlvd/pack sequence. 721 722 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. 723 { ISD::SRL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. 724 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 725 { ISD::SRL, MVT::v32i16, 20 }, // 2*extend/vpsrlvd/pack sequence. 726 727 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. 728 { ISD::SRA, MVT::v64i8, 48 }, // 2*vpblendvb sequence. 729 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. 730 { ISD::SRA, MVT::v32i16, 20 }, // 2*extend/vpsravd/pack sequence. 731 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. 732 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 733 734 { ISD::SUB, MVT::v32i8, 1 }, // psubb 735 { ISD::ADD, MVT::v32i8, 1 }, // paddb 736 { ISD::SUB, MVT::v16i16, 1 }, // psubw 737 { ISD::ADD, MVT::v16i16, 1 }, // paddw 738 { ISD::SUB, MVT::v8i32, 1 }, // psubd 739 { ISD::ADD, MVT::v8i32, 1 }, // paddd 740 { ISD::SUB, MVT::v4i64, 1 }, // psubq 741 { ISD::ADD, MVT::v4i64, 1 }, // paddq 742 743 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence. 744 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence. 745 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 746 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 747 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add 748 749 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 750 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 751 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 752 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 753 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 754 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 755 756 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 757 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 758 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 759 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 760 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 761 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 762 }; 763 764 // Look for AVX2 lowering tricks for custom cases. 765 if (ST->hasAVX2()) 766 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 767 return LT.first * Entry->Cost; 768 769 static const CostTblEntry AVX1CostTable[] = { 770 // We don't have to scalarize unsupported ops. We can issue two half-sized 771 // operations and we only need to extract the upper YMM half. 772 // Two ops + 1 extract + 1 insert = 4. 773 { ISD::MUL, MVT::v16i16, 4 }, 774 { ISD::MUL, MVT::v8i32, 4 }, 775 { ISD::SUB, MVT::v32i8, 4 }, 776 { ISD::ADD, MVT::v32i8, 4 }, 777 { ISD::SUB, MVT::v16i16, 4 }, 778 { ISD::ADD, MVT::v16i16, 4 }, 779 { ISD::SUB, MVT::v8i32, 4 }, 780 { ISD::ADD, MVT::v8i32, 4 }, 781 { ISD::SUB, MVT::v4i64, 4 }, 782 { ISD::ADD, MVT::v4i64, 4 }, 783 784 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 785 // are lowered as a series of long multiplies(3), shifts(3) and adds(2) 786 // Because we believe v4i64 to be a legal type, we must also include the 787 // extract+insert in the cost table. Therefore, the cost here is 18 788 // instead of 8. 789 { ISD::MUL, MVT::v4i64, 18 }, 790 791 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence. 792 793 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 794 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 795 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 796 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 797 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 798 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 799 }; 800 801 if (ST->hasAVX()) 802 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 803 return LT.first * Entry->Cost; 804 805 static const CostTblEntry SSE42CostTable[] = { 806 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 807 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 808 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 809 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 810 811 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 812 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 813 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 814 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 815 816 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 817 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 818 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 819 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 820 821 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 822 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 823 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 824 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 825 }; 826 827 if (ST->hasSSE42()) 828 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 829 return LT.first * Entry->Cost; 830 831 static const CostTblEntry SSE41CostTable[] = { 832 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 833 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split. 834 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 835 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 836 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 837 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split 838 839 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 840 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split. 841 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 842 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 843 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 844 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split. 845 846 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 847 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split. 848 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 849 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 850 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 851 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split. 852 853 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 854 }; 855 856 if (ST->hasSSE41()) 857 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 858 return LT.first * Entry->Cost; 859 860 static const CostTblEntry SSE2CostTable[] = { 861 // We don't correctly identify costs of casts because they are marked as 862 // custom. 863 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 864 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 865 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 866 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 867 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 868 869 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 870 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 871 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 872 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 873 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 874 875 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 876 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 877 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 878 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 879 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split. 880 881 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence. 882 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 883 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 884 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 885 886 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 887 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 888 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 889 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 890 891 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 892 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 893 894 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 895 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 896 }; 897 898 if (ST->hasSSE2()) 899 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 900 return LT.first * Entry->Cost; 901 902 static const CostTblEntry SSE1CostTable[] = { 903 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 904 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 905 906 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 907 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 908 909 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 910 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 911 912 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 913 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 914 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 915 916 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 917 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 918 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 919 }; 920 921 if (ST->hasSSE1()) 922 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 923 return LT.first * Entry->Cost; 924 925 // It is not a good idea to vectorize division. We have to scalarize it and 926 // in the process we will often end up having to spilling regular 927 // registers. The overhead of division is going to dominate most kernels 928 // anyways so try hard to prevent vectorization of division - it is 929 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 930 // to hide "20 cycles" for each lane. 931 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 932 ISD == ISD::UDIV || ISD == ISD::UREM)) { 933 int ScalarCost = getArithmeticInstrCost( 934 Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info, 935 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 936 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 937 } 938 939 // Fallback to the default implementation. 940 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info); 941 } 942 943 int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, VectorType *BaseTp, 944 int Index, VectorType *SubTp) { 945 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 946 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 947 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 948 949 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 950 if (Kind == TTI::SK_Transpose) 951 Kind = TTI::SK_PermuteTwoSrc; 952 953 // For Broadcasts we are splatting the first element from the first input 954 // register, so only need to reference that input and all the output 955 // registers are the same. 956 if (Kind == TTI::SK_Broadcast) 957 LT.first = 1; 958 959 // Subvector extractions are free if they start at the beginning of a 960 // vector and cheap if the subvectors are aligned. 961 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 962 int NumElts = LT.second.getVectorNumElements(); 963 if ((Index % NumElts) == 0) 964 return 0; 965 std::pair<int, MVT> SubLT = TLI->getTypeLegalizationCost(DL, SubTp); 966 if (SubLT.second.isVector()) { 967 int NumSubElts = SubLT.second.getVectorNumElements(); 968 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 969 return SubLT.first; 970 // Handle some cases for widening legalization. For now we only handle 971 // cases where the original subvector was naturally aligned and evenly 972 // fit in its legalized subvector type. 973 // FIXME: Remove some of the alignment restrictions. 974 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 975 // vectors. 976 int OrigSubElts = cast<FixedVectorType>(SubTp)->getNumElements(); 977 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 978 (NumSubElts % OrigSubElts) == 0 && 979 LT.second.getVectorElementType() == 980 SubLT.second.getVectorElementType() && 981 LT.second.getVectorElementType().getSizeInBits() == 982 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 983 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 984 "Unexpected number of elements!"); 985 auto *VecTy = FixedVectorType::get(BaseTp->getElementType(), 986 LT.second.getVectorNumElements()); 987 auto *SubTy = FixedVectorType::get(BaseTp->getElementType(), 988 SubLT.second.getVectorNumElements()); 989 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 990 int ExtractCost = getShuffleCost(TTI::SK_ExtractSubvector, VecTy, 991 ExtractIndex, SubTy); 992 993 // If the original size is 32-bits or more, we can use pshufd. Otherwise 994 // if we have SSSE3 we can use pshufb. 995 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 996 return ExtractCost + 1; // pshufd or pshufb 997 998 assert(SubTp->getPrimitiveSizeInBits() == 16 && 999 "Unexpected vector size"); 1000 1001 return ExtractCost + 2; // worst case pshufhw + pshufd 1002 } 1003 } 1004 } 1005 1006 // Handle some common (illegal) sub-vector types as they are often very cheap 1007 // to shuffle even on targets without PSHUFB. 1008 EVT VT = TLI->getValueType(DL, BaseTp); 1009 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 1010 !ST->hasSSSE3()) { 1011 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 1012 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 1013 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1014 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1015 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1016 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1017 1018 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1019 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1020 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1021 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1022 1023 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1024 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1025 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1026 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1027 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1028 1029 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1030 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1031 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1032 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1033 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1034 }; 1035 1036 if (ST->hasSSE2()) 1037 if (const auto *Entry = 1038 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1039 return Entry->Cost; 1040 } 1041 1042 // We are going to permute multiple sources and the result will be in multiple 1043 // destinations. Providing an accurate cost only for splits where the element 1044 // type remains the same. 1045 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1046 MVT LegalVT = LT.second; 1047 if (LegalVT.isVector() && 1048 LegalVT.getVectorElementType().getSizeInBits() == 1049 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1050 LegalVT.getVectorNumElements() < 1051 cast<FixedVectorType>(BaseTp)->getNumElements()) { 1052 1053 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1054 unsigned LegalVTSize = LegalVT.getStoreSize(); 1055 // Number of source vectors after legalization: 1056 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1057 // Number of destination vectors after legalization: 1058 unsigned NumOfDests = LT.first; 1059 1060 auto *SingleOpTy = FixedVectorType::get(BaseTp->getElementType(), 1061 LegalVT.getVectorNumElements()); 1062 1063 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1064 return NumOfShuffles * 1065 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 0, nullptr); 1066 } 1067 1068 return BaseT::getShuffleCost(Kind, BaseTp, Index, SubTp); 1069 } 1070 1071 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1072 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1073 // We assume that source and destination have the same vector type. 1074 int NumOfDests = LT.first; 1075 int NumOfShufflesPerDest = LT.first * 2 - 1; 1076 LT.first = NumOfDests * NumOfShufflesPerDest; 1077 } 1078 1079 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1080 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1081 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1082 1083 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1084 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1085 1086 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b 1087 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b 1088 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2} // vpermt2b 1089 }; 1090 1091 if (ST->hasVBMI()) 1092 if (const auto *Entry = 1093 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1094 return LT.first * Entry->Cost; 1095 1096 static const CostTblEntry AVX512BWShuffleTbl[] = { 1097 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1098 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1099 1100 {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw 1101 {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw 1102 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1103 1104 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw 1105 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw 1106 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1107 1108 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w 1109 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w 1110 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2}, // vpermt2w 1111 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1112 }; 1113 1114 if (ST->hasBWI()) 1115 if (const auto *Entry = 1116 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1117 return LT.first * Entry->Cost; 1118 1119 static const CostTblEntry AVX512ShuffleTbl[] = { 1120 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1121 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1122 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1123 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1124 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1125 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1126 1127 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1128 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1129 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1130 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1131 1132 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1133 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1134 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1135 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1136 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1137 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1138 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1139 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1140 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1141 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1142 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1143 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1144 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1145 1146 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1147 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1148 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1149 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1150 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1151 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1152 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1153 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1154 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1155 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1156 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1157 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1158 1159 // FIXME: This just applies the type legalization cost rules above 1160 // assuming these completely split. 1161 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1162 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1163 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1164 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1165 }; 1166 1167 if (ST->hasAVX512()) 1168 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1169 return LT.first * Entry->Cost; 1170 1171 static const CostTblEntry AVX2ShuffleTbl[] = { 1172 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1173 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1174 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1175 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1176 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1177 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1178 1179 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1180 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1181 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1182 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1183 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1184 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1185 1186 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1187 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1188 1189 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1190 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1191 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1192 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1193 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1194 // + vpblendvb 1195 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1196 // + vpblendvb 1197 1198 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1199 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1200 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1201 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1202 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1203 // + vpblendvb 1204 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1205 // + vpblendvb 1206 }; 1207 1208 if (ST->hasAVX2()) 1209 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1210 return LT.first * Entry->Cost; 1211 1212 static const CostTblEntry XOPShuffleTbl[] = { 1213 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1214 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1215 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1216 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1217 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1218 // + vinsertf128 1219 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1220 // + vinsertf128 1221 1222 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1223 // + vinsertf128 1224 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1225 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1226 // + vinsertf128 1227 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1228 }; 1229 1230 if (ST->hasXOP()) 1231 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1232 return LT.first * Entry->Cost; 1233 1234 static const CostTblEntry AVX1ShuffleTbl[] = { 1235 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1236 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1237 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1238 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1239 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1240 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1241 1242 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1243 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1244 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1245 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1246 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1247 // + vinsertf128 1248 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1249 // + vinsertf128 1250 1251 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1252 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1253 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1254 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1255 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1256 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1257 1258 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1259 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1260 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1261 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1262 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1263 // + 2*por + vinsertf128 1264 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1265 // + 2*por + vinsertf128 1266 1267 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1268 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1269 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1270 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1271 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1272 // + 4*por + vinsertf128 1273 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1274 // + 4*por + vinsertf128 1275 }; 1276 1277 if (ST->hasAVX()) 1278 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1279 return LT.first * Entry->Cost; 1280 1281 static const CostTblEntry SSE41ShuffleTbl[] = { 1282 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1283 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1284 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1285 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1286 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1287 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1288 }; 1289 1290 if (ST->hasSSE41()) 1291 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1292 return LT.first * Entry->Cost; 1293 1294 static const CostTblEntry SSSE3ShuffleTbl[] = { 1295 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1296 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1297 1298 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1299 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1300 1301 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1302 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1303 1304 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1305 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1306 1307 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1308 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1309 }; 1310 1311 if (ST->hasSSSE3()) 1312 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1313 return LT.first * Entry->Cost; 1314 1315 static const CostTblEntry SSE2ShuffleTbl[] = { 1316 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1317 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1318 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1319 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1320 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1321 1322 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1323 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1324 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1325 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1326 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1327 // + 2*pshufd + 2*unpck + packus 1328 1329 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1330 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1331 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1332 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1333 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1334 1335 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1336 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1337 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1338 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1339 // + pshufd/unpck 1340 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1341 // + 2*pshufd + 2*unpck + 2*packus 1342 1343 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1344 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1345 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1346 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1347 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1348 }; 1349 1350 if (ST->hasSSE2()) 1351 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1352 return LT.first * Entry->Cost; 1353 1354 static const CostTblEntry SSE1ShuffleTbl[] = { 1355 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1356 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1357 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1358 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1359 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1360 }; 1361 1362 if (ST->hasSSE1()) 1363 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1364 return LT.first * Entry->Cost; 1365 1366 return BaseT::getShuffleCost(Kind, BaseTp, Index, SubTp); 1367 } 1368 1369 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 1370 TTI::CastContextHint CCH, 1371 TTI::TargetCostKind CostKind, 1372 const Instruction *I) { 1373 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1374 assert(ISD && "Invalid opcode"); 1375 1376 // TODO: Allow non-throughput costs that aren't binary. 1377 auto AdjustCost = [&CostKind](int Cost) { 1378 if (CostKind != TTI::TCK_RecipThroughput) 1379 return Cost == 0 ? 0 : 1; 1380 return Cost; 1381 }; 1382 1383 // FIXME: Need a better design of the cost table to handle non-simple types of 1384 // potential massive combinations (elem_num x src_type x dst_type). 1385 1386 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1387 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1388 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1389 1390 // Mask sign extend has an instruction. 1391 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1392 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1393 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1394 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1395 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1396 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1397 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1398 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1399 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1400 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1401 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1402 1403 // Mask zero extend is a sext + shift. 1404 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1405 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1406 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1407 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1408 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1409 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1410 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1411 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1412 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1413 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1414 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1415 1416 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, 1417 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm 1418 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // widen to zmm 1419 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // widen to zmm 1420 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // widen to zmm 1421 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // widen to zmm 1422 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // widen to zmm 1423 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // widen to zmm 1424 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // widen to zmm 1425 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // widen to zmm 1426 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // widen to zmm 1427 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, 1428 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, 1429 }; 1430 1431 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1432 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1433 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1434 1435 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1436 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1437 1438 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1439 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1440 1441 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1442 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1443 }; 1444 1445 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1446 // 256-bit wide vectors. 1447 1448 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1449 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1450 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1451 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1452 1453 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1454 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1455 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1456 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd 1457 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1458 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1459 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1460 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd 1461 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd 1462 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd 1463 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd 1464 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd 1465 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq 1466 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq 1467 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq 1468 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, 1469 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, 1470 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, 1471 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, 1472 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 1473 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd 1474 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb 1475 1476 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32 1477 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, 1478 1479 // Sign extend is zmm vpternlogd+vptruncdb. 1480 // Zero extend is zmm broadcast load+vptruncdw. 1481 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 }, 1482 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 }, 1483 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, 1484 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, 1485 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, 1486 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, 1487 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 }, 1488 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 }, 1489 1490 // Sign extend is zmm vpternlogd+vptruncdw. 1491 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw. 1492 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 }, 1493 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1494 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 }, 1495 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1496 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 }, 1497 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1498 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 }, 1499 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1500 1501 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd 1502 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld 1503 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd 1504 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld 1505 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd 1506 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld 1507 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq 1508 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq 1509 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq 1510 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq 1511 1512 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd 1513 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld 1514 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq 1515 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq 1516 1517 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1518 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1519 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1520 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1521 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1522 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1523 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1524 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1525 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1526 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1527 1528 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1529 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1530 1531 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1532 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1533 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1534 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1535 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1536 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1537 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1538 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1539 1540 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1541 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1542 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1543 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1544 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1545 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1546 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1547 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1548 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1549 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1550 1551 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f64, 3 }, 1552 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, 1553 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 3 }, 1554 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 3 }, 1555 1556 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1557 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, 1558 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, 1559 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1560 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, 1561 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, 1562 }; 1563 1564 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1565 // Mask sign extend has an instruction. 1566 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1567 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1568 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1569 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1570 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1571 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1572 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1573 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1574 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1575 1576 // Mask zero extend is a sext + shift. 1577 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1578 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1579 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1580 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1581 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1582 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1583 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1584 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1585 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1586 1587 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, 1588 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // vpsllw+vptestmb 1589 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // vpsllw+vptestmw 1590 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // vpsllw+vptestmb 1591 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // vpsllw+vptestmw 1592 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // vpsllw+vptestmb 1593 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // vpsllw+vptestmw 1594 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // vpsllw+vptestmb 1595 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // vpsllw+vptestmw 1596 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // vpsllw+vptestmb 1597 }; 1598 1599 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1600 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1601 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1602 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1603 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1604 1605 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1606 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1607 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1608 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1609 1610 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1611 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1612 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1613 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1614 1615 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1616 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1617 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1618 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1619 }; 1620 1621 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 1622 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1623 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1624 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1625 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 8 }, // split+2*v8i8 1626 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1627 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1628 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1629 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16 1630 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // vpslld+vptestmd 1631 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd 1632 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // vpslld+vptestmd 1633 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // vpsllq+vptestmq 1634 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // vpsllq+vptestmq 1635 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // vpmovqd 1636 1637 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb 1638 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb 1639 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 }, 1640 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 }, 1641 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 }, 1642 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 }, 1643 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 }, 1644 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 }, 1645 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 }, 1646 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 }, 1647 1648 // sign extend is vpcmpeq+maskedmove+vpmovdw 1649 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw 1650 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1651 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 }, 1652 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1653 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 }, 1654 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1655 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 }, 1656 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 }, 1657 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 }, 1658 1659 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd 1660 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld 1661 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd 1662 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld 1663 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd 1664 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld 1665 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq 1666 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq 1667 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq 1668 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq 1669 1670 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1671 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1672 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1673 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1674 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1675 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1676 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1677 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1678 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1679 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1680 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1681 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1682 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1683 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1684 1685 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 1686 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1687 1688 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 3 }, 1689 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 3 }, 1690 1691 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 1692 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 1693 1694 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1695 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1696 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 1 }, 1697 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1698 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1699 }; 1700 1701 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1702 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1703 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1704 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1705 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1706 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1707 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1708 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1709 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1710 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1711 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1712 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1713 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1714 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1715 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1716 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1717 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1718 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1719 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1720 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1721 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1722 1723 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1724 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1725 1726 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 1727 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 1728 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 1729 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1730 1731 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1732 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1733 1734 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1735 }; 1736 1737 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1738 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1739 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1740 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1741 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1742 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1743 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1744 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1745 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1746 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1747 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1748 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1749 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1750 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 4 }, 1751 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1752 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1753 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1754 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1755 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1756 1757 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 4 }, 1758 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 5 }, 1759 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 4 }, 1760 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 9 }, 1761 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, 11 }, 1762 1763 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 1764 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1765 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1766 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1767 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 1768 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1769 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 11 }, 1770 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 9 }, 1771 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 }, 1772 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 11 }, 1773 1774 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1775 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1776 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1777 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1778 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1779 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1780 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1781 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1782 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1783 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1784 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1785 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1786 1787 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1788 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1789 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1790 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1791 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1792 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1793 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1794 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1795 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1796 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 }, 1797 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 1798 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1799 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 1800 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1801 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1802 // The generic code to compute the scalar overhead is currently broken. 1803 // Workaround this limitation by estimating the scalarization overhead 1804 // here. We have roughly 10 instructions per scalar element. 1805 // Multiply that by the vector width. 1806 // FIXME: remove that when PR19268 is fixed. 1807 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1808 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1809 1810 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 4 }, 1811 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f64, 3 }, 1812 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f64, 2 }, 1813 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 3 }, 1814 1815 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f64, 3 }, 1816 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f64, 2 }, 1817 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 4 }, 1818 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 3 }, 1819 // This node is expanded into scalarized operations but BasicTTI is overly 1820 // optimistic estimating its cost. It computes 3 per element (one 1821 // vector-extract, one scalar conversion and one vector-insert). The 1822 // problem is that the inserts form a read-modify-write chain so latency 1823 // should be factored in too. Inflating the cost per element by 1. 1824 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, 1825 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 1826 1827 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 1828 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 1829 }; 1830 1831 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 1832 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1833 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1834 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1835 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1836 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1837 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1838 1839 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1840 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 }, 1841 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1842 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1843 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1844 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1845 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1846 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1847 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1848 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1849 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1850 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1851 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1852 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1853 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1854 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1855 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1856 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1857 1858 // These truncates end up widening elements. 1859 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 1 }, // PMOVXZBQ 1860 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 1 }, // PMOVXZWQ 1861 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 1 }, // PMOVXZBD 1862 1863 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 1 }, 1864 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 1 }, 1865 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 1866 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 1867 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 1868 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 1869 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 1870 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 1871 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 1 }, // PSHUFB 1872 1873 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 1874 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 1875 1876 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 3 }, 1877 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 3 }, 1878 1879 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 3 }, 1880 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 3 }, 1881 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, 1882 }; 1883 1884 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 1885 // These are somewhat magic numbers justified by looking at the output of 1886 // Intel's IACA, running some kernels and making sure when we take 1887 // legalization into account the throughput will be overestimated. 1888 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1889 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1890 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1891 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1892 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1893 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 2*10 }, 1894 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2*10 }, 1895 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1896 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 1897 1898 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1899 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1900 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1901 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1902 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1903 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, 1904 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 }, 1905 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1906 1907 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 4 }, 1908 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 2 }, 1909 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, 1910 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, 1911 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, 1912 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 4 }, 1913 1914 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 1 }, 1915 1916 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 6 }, 1917 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 }, 1918 1919 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 1920 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 1921 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 4 }, 1922 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 4 }, 1923 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 }, 1924 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 2 }, 1925 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 }, 1926 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 4 }, 1927 1928 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1929 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 1930 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 1931 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 1932 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1933 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 1934 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1935 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 1936 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1937 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1938 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1939 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1940 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 1941 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 1942 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1943 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 1944 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1945 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 1946 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1947 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1948 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 1949 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 1950 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1951 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 1952 1953 // These truncates are really widening elements. 1954 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 1 }, // PSHUFD 1955 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // PUNPCKLWD+DQ 1956 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // PUNPCKLBW+WD+PSHUFD 1957 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 1 }, // PUNPCKLWD 1958 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // PUNPCKLBW+WD 1959 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 1 }, // PUNPCKLBW 1960 1961 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // PAND+PACKUSWB 1962 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // PAND+PACKUSWB 1963 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // PAND+PACKUSWB 1964 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 1965 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 3 }, // PAND+2*PACKUSWB 1966 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 1967 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 1968 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 1969 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1970 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 1971 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1972 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 1973 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 1974 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 1975 { ISD::TRUNCATE, MVT::v2i32, MVT::v2i64, 1 }, // PSHUFD 1976 }; 1977 1978 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 1979 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst); 1980 1981 if (ST->hasSSE2() && !ST->hasAVX()) { 1982 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1983 LTDest.second, LTSrc.second)) 1984 return AdjustCost(LTSrc.first * Entry->Cost); 1985 } 1986 1987 EVT SrcTy = TLI->getValueType(DL, Src); 1988 EVT DstTy = TLI->getValueType(DL, Dst); 1989 1990 // The function getSimpleVT only handles simple value types. 1991 if (!SrcTy.isSimple() || !DstTy.isSimple()) 1992 return AdjustCost(BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind)); 1993 1994 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 1995 MVT SimpleDstTy = DstTy.getSimpleVT(); 1996 1997 if (ST->useAVX512Regs()) { 1998 if (ST->hasBWI()) 1999 if (const auto *Entry = ConvertCostTableLookup(AVX512BWConversionTbl, ISD, 2000 SimpleDstTy, SimpleSrcTy)) 2001 return AdjustCost(Entry->Cost); 2002 2003 if (ST->hasDQI()) 2004 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 2005 SimpleDstTy, SimpleSrcTy)) 2006 return AdjustCost(Entry->Cost); 2007 2008 if (ST->hasAVX512()) 2009 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 2010 SimpleDstTy, SimpleSrcTy)) 2011 return AdjustCost(Entry->Cost); 2012 } 2013 2014 if (ST->hasBWI()) 2015 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 2016 SimpleDstTy, SimpleSrcTy)) 2017 return AdjustCost(Entry->Cost); 2018 2019 if (ST->hasDQI()) 2020 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 2021 SimpleDstTy, SimpleSrcTy)) 2022 return AdjustCost(Entry->Cost); 2023 2024 if (ST->hasAVX512()) 2025 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2026 SimpleDstTy, SimpleSrcTy)) 2027 return AdjustCost(Entry->Cost); 2028 2029 if (ST->hasAVX2()) { 2030 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2031 SimpleDstTy, SimpleSrcTy)) 2032 return AdjustCost(Entry->Cost); 2033 } 2034 2035 if (ST->hasAVX()) { 2036 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2037 SimpleDstTy, SimpleSrcTy)) 2038 return AdjustCost(Entry->Cost); 2039 } 2040 2041 if (ST->hasSSE41()) { 2042 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2043 SimpleDstTy, SimpleSrcTy)) 2044 return AdjustCost(Entry->Cost); 2045 } 2046 2047 if (ST->hasSSE2()) { 2048 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2049 SimpleDstTy, SimpleSrcTy)) 2050 return AdjustCost(Entry->Cost); 2051 } 2052 2053 return AdjustCost( 2054 BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I)); 2055 } 2056 2057 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 2058 TTI::TargetCostKind CostKind, 2059 const Instruction *I) { 2060 // TODO: Handle other cost kinds. 2061 if (CostKind != TTI::TCK_RecipThroughput) 2062 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, CostKind, I); 2063 2064 // Legalize the type. 2065 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2066 2067 MVT MTy = LT.second; 2068 2069 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2070 assert(ISD && "Invalid opcode"); 2071 2072 unsigned ExtraCost = 0; 2073 if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) { 2074 // Some vector comparison predicates cost extra instructions. 2075 if (MTy.isVector() && 2076 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 2077 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 2078 ST->hasBWI())) { 2079 switch (cast<CmpInst>(I)->getPredicate()) { 2080 case CmpInst::Predicate::ICMP_NE: 2081 // xor(cmpeq(x,y),-1) 2082 ExtraCost = 1; 2083 break; 2084 case CmpInst::Predicate::ICMP_SGE: 2085 case CmpInst::Predicate::ICMP_SLE: 2086 // xor(cmpgt(x,y),-1) 2087 ExtraCost = 1; 2088 break; 2089 case CmpInst::Predicate::ICMP_ULT: 2090 case CmpInst::Predicate::ICMP_UGT: 2091 // cmpgt(xor(x,signbit),xor(y,signbit)) 2092 // xor(cmpeq(pmaxu(x,y),x),-1) 2093 ExtraCost = 2; 2094 break; 2095 case CmpInst::Predicate::ICMP_ULE: 2096 case CmpInst::Predicate::ICMP_UGE: 2097 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 2098 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 2099 // cmpeq(psubus(x,y),0) 2100 // cmpeq(pminu(x,y),x) 2101 ExtraCost = 1; 2102 } else { 2103 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 2104 ExtraCost = 3; 2105 } 2106 break; 2107 default: 2108 break; 2109 } 2110 } 2111 } 2112 2113 static const CostTblEntry SLMCostTbl[] = { 2114 // slm pcmpeq/pcmpgt throughput is 2 2115 { ISD::SETCC, MVT::v2i64, 2 }, 2116 }; 2117 2118 static const CostTblEntry AVX512BWCostTbl[] = { 2119 { ISD::SETCC, MVT::v32i16, 1 }, 2120 { ISD::SETCC, MVT::v64i8, 1 }, 2121 2122 { ISD::SELECT, MVT::v32i16, 1 }, 2123 { ISD::SELECT, MVT::v64i8, 1 }, 2124 }; 2125 2126 static const CostTblEntry AVX512CostTbl[] = { 2127 { ISD::SETCC, MVT::v8i64, 1 }, 2128 { ISD::SETCC, MVT::v16i32, 1 }, 2129 { ISD::SETCC, MVT::v8f64, 1 }, 2130 { ISD::SETCC, MVT::v16f32, 1 }, 2131 2132 { ISD::SELECT, MVT::v8i64, 1 }, 2133 { ISD::SELECT, MVT::v16i32, 1 }, 2134 { ISD::SELECT, MVT::v8f64, 1 }, 2135 { ISD::SELECT, MVT::v16f32, 1 }, 2136 2137 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 2138 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 2139 2140 { ISD::SELECT, MVT::v32i16, 2 }, // FIXME: should be 3 2141 { ISD::SELECT, MVT::v64i8, 2 }, // FIXME: should be 3 2142 }; 2143 2144 static const CostTblEntry AVX2CostTbl[] = { 2145 { ISD::SETCC, MVT::v4i64, 1 }, 2146 { ISD::SETCC, MVT::v8i32, 1 }, 2147 { ISD::SETCC, MVT::v16i16, 1 }, 2148 { ISD::SETCC, MVT::v32i8, 1 }, 2149 2150 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 2151 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 2152 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 2153 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 2154 }; 2155 2156 static const CostTblEntry AVX1CostTbl[] = { 2157 { ISD::SETCC, MVT::v4f64, 1 }, 2158 { ISD::SETCC, MVT::v8f32, 1 }, 2159 // AVX1 does not support 8-wide integer compare. 2160 { ISD::SETCC, MVT::v4i64, 4 }, 2161 { ISD::SETCC, MVT::v8i32, 4 }, 2162 { ISD::SETCC, MVT::v16i16, 4 }, 2163 { ISD::SETCC, MVT::v32i8, 4 }, 2164 2165 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 2166 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 2167 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 2168 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 2169 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 2170 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 2171 }; 2172 2173 static const CostTblEntry SSE42CostTbl[] = { 2174 { ISD::SETCC, MVT::v2f64, 1 }, 2175 { ISD::SETCC, MVT::v4f32, 1 }, 2176 { ISD::SETCC, MVT::v2i64, 1 }, 2177 }; 2178 2179 static const CostTblEntry SSE41CostTbl[] = { 2180 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 2181 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 2182 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 2183 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 2184 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 2185 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 2186 }; 2187 2188 static const CostTblEntry SSE2CostTbl[] = { 2189 { ISD::SETCC, MVT::v2f64, 2 }, 2190 { ISD::SETCC, MVT::f64, 1 }, 2191 { ISD::SETCC, MVT::v2i64, 8 }, 2192 { ISD::SETCC, MVT::v4i32, 1 }, 2193 { ISD::SETCC, MVT::v8i16, 1 }, 2194 { ISD::SETCC, MVT::v16i8, 1 }, 2195 2196 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 2197 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 2198 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 2199 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 2200 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 2201 }; 2202 2203 static const CostTblEntry SSE1CostTbl[] = { 2204 { ISD::SETCC, MVT::v4f32, 2 }, 2205 { ISD::SETCC, MVT::f32, 1 }, 2206 2207 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 2208 }; 2209 2210 if (ST->isSLM()) 2211 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2212 return LT.first * (ExtraCost + Entry->Cost); 2213 2214 if (ST->hasBWI()) 2215 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2216 return LT.first * (ExtraCost + Entry->Cost); 2217 2218 if (ST->hasAVX512()) 2219 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2220 return LT.first * (ExtraCost + Entry->Cost); 2221 2222 if (ST->hasAVX2()) 2223 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2224 return LT.first * (ExtraCost + Entry->Cost); 2225 2226 if (ST->hasAVX()) 2227 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2228 return LT.first * (ExtraCost + Entry->Cost); 2229 2230 if (ST->hasSSE42()) 2231 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2232 return LT.first * (ExtraCost + Entry->Cost); 2233 2234 if (ST->hasSSE41()) 2235 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2236 return LT.first * (ExtraCost + Entry->Cost); 2237 2238 if (ST->hasSSE2()) 2239 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2240 return LT.first * (ExtraCost + Entry->Cost); 2241 2242 if (ST->hasSSE1()) 2243 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2244 return LT.first * (ExtraCost + Entry->Cost); 2245 2246 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, CostKind, I); 2247 } 2248 2249 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2250 2251 int X86TTIImpl::getTypeBasedIntrinsicInstrCost( 2252 const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) { 2253 2254 // Costs should match the codegen from: 2255 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2256 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2257 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2258 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2259 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2260 static const CostTblEntry AVX512CDCostTbl[] = { 2261 { ISD::CTLZ, MVT::v8i64, 1 }, 2262 { ISD::CTLZ, MVT::v16i32, 1 }, 2263 { ISD::CTLZ, MVT::v32i16, 8 }, 2264 { ISD::CTLZ, MVT::v64i8, 20 }, 2265 { ISD::CTLZ, MVT::v4i64, 1 }, 2266 { ISD::CTLZ, MVT::v8i32, 1 }, 2267 { ISD::CTLZ, MVT::v16i16, 4 }, 2268 { ISD::CTLZ, MVT::v32i8, 10 }, 2269 { ISD::CTLZ, MVT::v2i64, 1 }, 2270 { ISD::CTLZ, MVT::v4i32, 1 }, 2271 { ISD::CTLZ, MVT::v8i16, 4 }, 2272 { ISD::CTLZ, MVT::v16i8, 4 }, 2273 }; 2274 static const CostTblEntry AVX512BWCostTbl[] = { 2275 { ISD::ABS, MVT::v32i16, 1 }, 2276 { ISD::ABS, MVT::v64i8, 1 }, 2277 { ISD::BITREVERSE, MVT::v8i64, 5 }, 2278 { ISD::BITREVERSE, MVT::v16i32, 5 }, 2279 { ISD::BITREVERSE, MVT::v32i16, 5 }, 2280 { ISD::BITREVERSE, MVT::v64i8, 5 }, 2281 { ISD::CTLZ, MVT::v8i64, 23 }, 2282 { ISD::CTLZ, MVT::v16i32, 22 }, 2283 { ISD::CTLZ, MVT::v32i16, 18 }, 2284 { ISD::CTLZ, MVT::v64i8, 17 }, 2285 { ISD::CTPOP, MVT::v8i64, 7 }, 2286 { ISD::CTPOP, MVT::v16i32, 11 }, 2287 { ISD::CTPOP, MVT::v32i16, 9 }, 2288 { ISD::CTPOP, MVT::v64i8, 6 }, 2289 { ISD::CTTZ, MVT::v8i64, 10 }, 2290 { ISD::CTTZ, MVT::v16i32, 14 }, 2291 { ISD::CTTZ, MVT::v32i16, 12 }, 2292 { ISD::CTTZ, MVT::v64i8, 9 }, 2293 { ISD::SADDSAT, MVT::v32i16, 1 }, 2294 { ISD::SADDSAT, MVT::v64i8, 1 }, 2295 { ISD::SMAX, MVT::v32i16, 1 }, 2296 { ISD::SMAX, MVT::v64i8, 1 }, 2297 { ISD::SMIN, MVT::v32i16, 1 }, 2298 { ISD::SMIN, MVT::v64i8, 1 }, 2299 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2300 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2301 { ISD::UADDSAT, MVT::v32i16, 1 }, 2302 { ISD::UADDSAT, MVT::v64i8, 1 }, 2303 { ISD::UMAX, MVT::v32i16, 1 }, 2304 { ISD::UMAX, MVT::v64i8, 1 }, 2305 { ISD::UMIN, MVT::v32i16, 1 }, 2306 { ISD::UMIN, MVT::v64i8, 1 }, 2307 { ISD::USUBSAT, MVT::v32i16, 1 }, 2308 { ISD::USUBSAT, MVT::v64i8, 1 }, 2309 }; 2310 static const CostTblEntry AVX512CostTbl[] = { 2311 { ISD::ABS, MVT::v8i64, 1 }, 2312 { ISD::ABS, MVT::v16i32, 1 }, 2313 { ISD::ABS, MVT::v32i16, 2 }, // FIXME: include split 2314 { ISD::ABS, MVT::v64i8, 2 }, // FIXME: include split 2315 { ISD::ABS, MVT::v4i64, 1 }, 2316 { ISD::ABS, MVT::v2i64, 1 }, 2317 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2318 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2319 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2320 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2321 { ISD::CTLZ, MVT::v8i64, 29 }, 2322 { ISD::CTLZ, MVT::v16i32, 35 }, 2323 { ISD::CTLZ, MVT::v32i16, 28 }, 2324 { ISD::CTLZ, MVT::v64i8, 18 }, 2325 { ISD::CTPOP, MVT::v8i64, 16 }, 2326 { ISD::CTPOP, MVT::v16i32, 24 }, 2327 { ISD::CTPOP, MVT::v32i16, 18 }, 2328 { ISD::CTPOP, MVT::v64i8, 12 }, 2329 { ISD::CTTZ, MVT::v8i64, 20 }, 2330 { ISD::CTTZ, MVT::v16i32, 28 }, 2331 { ISD::CTTZ, MVT::v32i16, 24 }, 2332 { ISD::CTTZ, MVT::v64i8, 18 }, 2333 { ISD::SMAX, MVT::v8i64, 1 }, 2334 { ISD::SMAX, MVT::v16i32, 1 }, 2335 { ISD::SMAX, MVT::v32i16, 2 }, // FIXME: include split 2336 { ISD::SMAX, MVT::v64i8, 2 }, // FIXME: include split 2337 { ISD::SMAX, MVT::v4i64, 1 }, 2338 { ISD::SMAX, MVT::v2i64, 1 }, 2339 { ISD::SMIN, MVT::v8i64, 1 }, 2340 { ISD::SMIN, MVT::v16i32, 1 }, 2341 { ISD::SMIN, MVT::v32i16, 2 }, // FIXME: include split 2342 { ISD::SMIN, MVT::v64i8, 2 }, // FIXME: include split 2343 { ISD::SMIN, MVT::v4i64, 1 }, 2344 { ISD::SMIN, MVT::v2i64, 1 }, 2345 { ISD::UMAX, MVT::v8i64, 1 }, 2346 { ISD::UMAX, MVT::v16i32, 1 }, 2347 { ISD::UMAX, MVT::v32i16, 2 }, // FIXME: include split 2348 { ISD::UMAX, MVT::v64i8, 2 }, // FIXME: include split 2349 { ISD::UMAX, MVT::v4i64, 1 }, 2350 { ISD::UMAX, MVT::v2i64, 1 }, 2351 { ISD::UMIN, MVT::v8i64, 1 }, 2352 { ISD::UMIN, MVT::v16i32, 1 }, 2353 { ISD::UMIN, MVT::v32i16, 2 }, // FIXME: include split 2354 { ISD::UMIN, MVT::v64i8, 2 }, // FIXME: include split 2355 { ISD::UMIN, MVT::v4i64, 1 }, 2356 { ISD::UMIN, MVT::v2i64, 1 }, 2357 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2358 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2359 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2360 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2361 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2362 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2363 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2364 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2365 { ISD::SADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2366 { ISD::SADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2367 { ISD::SSUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2368 { ISD::SSUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2369 { ISD::UADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2370 { ISD::UADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2371 { ISD::USUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2372 { ISD::USUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2373 { ISD::FMAXNUM, MVT::f32, 2 }, 2374 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2375 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2376 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2377 { ISD::FMAXNUM, MVT::f64, 2 }, 2378 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2379 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2380 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2381 }; 2382 static const CostTblEntry XOPCostTbl[] = { 2383 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2384 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2385 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2386 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2387 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2388 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2389 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2390 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2391 { ISD::BITREVERSE, MVT::i64, 3 }, 2392 { ISD::BITREVERSE, MVT::i32, 3 }, 2393 { ISD::BITREVERSE, MVT::i16, 3 }, 2394 { ISD::BITREVERSE, MVT::i8, 3 } 2395 }; 2396 static const CostTblEntry AVX2CostTbl[] = { 2397 { ISD::ABS, MVT::v4i64, 2 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2398 { ISD::ABS, MVT::v8i32, 1 }, 2399 { ISD::ABS, MVT::v16i16, 1 }, 2400 { ISD::ABS, MVT::v32i8, 1 }, 2401 { ISD::BITREVERSE, MVT::v4i64, 5 }, 2402 { ISD::BITREVERSE, MVT::v8i32, 5 }, 2403 { ISD::BITREVERSE, MVT::v16i16, 5 }, 2404 { ISD::BITREVERSE, MVT::v32i8, 5 }, 2405 { ISD::BSWAP, MVT::v4i64, 1 }, 2406 { ISD::BSWAP, MVT::v8i32, 1 }, 2407 { ISD::BSWAP, MVT::v16i16, 1 }, 2408 { ISD::CTLZ, MVT::v4i64, 23 }, 2409 { ISD::CTLZ, MVT::v8i32, 18 }, 2410 { ISD::CTLZ, MVT::v16i16, 14 }, 2411 { ISD::CTLZ, MVT::v32i8, 9 }, 2412 { ISD::CTPOP, MVT::v4i64, 7 }, 2413 { ISD::CTPOP, MVT::v8i32, 11 }, 2414 { ISD::CTPOP, MVT::v16i16, 9 }, 2415 { ISD::CTPOP, MVT::v32i8, 6 }, 2416 { ISD::CTTZ, MVT::v4i64, 10 }, 2417 { ISD::CTTZ, MVT::v8i32, 14 }, 2418 { ISD::CTTZ, MVT::v16i16, 12 }, 2419 { ISD::CTTZ, MVT::v32i8, 9 }, 2420 { ISD::SADDSAT, MVT::v16i16, 1 }, 2421 { ISD::SADDSAT, MVT::v32i8, 1 }, 2422 { ISD::SMAX, MVT::v8i32, 1 }, 2423 { ISD::SMAX, MVT::v16i16, 1 }, 2424 { ISD::SMAX, MVT::v32i8, 1 }, 2425 { ISD::SMIN, MVT::v8i32, 1 }, 2426 { ISD::SMIN, MVT::v16i16, 1 }, 2427 { ISD::SMIN, MVT::v32i8, 1 }, 2428 { ISD::SSUBSAT, MVT::v16i16, 1 }, 2429 { ISD::SSUBSAT, MVT::v32i8, 1 }, 2430 { ISD::UADDSAT, MVT::v16i16, 1 }, 2431 { ISD::UADDSAT, MVT::v32i8, 1 }, 2432 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 2433 { ISD::UMAX, MVT::v8i32, 1 }, 2434 { ISD::UMAX, MVT::v16i16, 1 }, 2435 { ISD::UMAX, MVT::v32i8, 1 }, 2436 { ISD::UMIN, MVT::v8i32, 1 }, 2437 { ISD::UMIN, MVT::v16i16, 1 }, 2438 { ISD::UMIN, MVT::v32i8, 1 }, 2439 { ISD::USUBSAT, MVT::v16i16, 1 }, 2440 { ISD::USUBSAT, MVT::v32i8, 1 }, 2441 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2442 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2443 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2444 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2445 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2446 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2447 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2448 }; 2449 static const CostTblEntry AVX1CostTbl[] = { 2450 { ISD::ABS, MVT::v4i64, 6 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2451 { ISD::ABS, MVT::v8i32, 3 }, 2452 { ISD::ABS, MVT::v16i16, 3 }, 2453 { ISD::ABS, MVT::v32i8, 3 }, 2454 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 2455 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 2456 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 2457 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 2458 { ISD::BSWAP, MVT::v4i64, 4 }, 2459 { ISD::BSWAP, MVT::v8i32, 4 }, 2460 { ISD::BSWAP, MVT::v16i16, 4 }, 2461 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 2462 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 2463 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 2464 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2465 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 2466 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 2467 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 2468 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 2469 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 2470 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 2471 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 2472 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2473 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2474 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2475 { ISD::SMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2476 { ISD::SMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2477 { ISD::SMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2478 { ISD::SMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2479 { ISD::SMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2480 { ISD::SMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2481 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2482 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2483 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2484 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2485 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 2486 { ISD::UMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2487 { ISD::UMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2488 { ISD::UMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2489 { ISD::UMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2490 { ISD::UMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2491 { ISD::UMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2492 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2493 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2494 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 2495 { ISD::FMAXNUM, MVT::f32, 3 }, 2496 { ISD::FMAXNUM, MVT::v4f32, 3 }, 2497 { ISD::FMAXNUM, MVT::v8f32, 5 }, 2498 { ISD::FMAXNUM, MVT::f64, 3 }, 2499 { ISD::FMAXNUM, MVT::v2f64, 3 }, 2500 { ISD::FMAXNUM, MVT::v4f64, 5 }, 2501 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 2502 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 2503 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 2504 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 2505 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 2506 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 2507 }; 2508 static const CostTblEntry GLMCostTbl[] = { 2509 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 2510 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 2511 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 2512 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 2513 }; 2514 static const CostTblEntry SLMCostTbl[] = { 2515 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 2516 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 2517 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 2518 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 2519 }; 2520 static const CostTblEntry SSE42CostTbl[] = { 2521 { ISD::ABS, MVT::v2i64, 3 }, // BLENDVPD(X,PSUBQ(0,X),X) 2522 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 2523 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 2524 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 2525 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 2526 }; 2527 static const CostTblEntry SSE41CostTbl[] = { 2528 { ISD::SMAX, MVT::v4i32, 1 }, 2529 { ISD::SMAX, MVT::v16i8, 1 }, 2530 { ISD::SMIN, MVT::v4i32, 1 }, 2531 { ISD::SMIN, MVT::v16i8, 1 }, 2532 { ISD::UMAX, MVT::v4i32, 1 }, 2533 { ISD::UMAX, MVT::v8i16, 1 }, 2534 { ISD::UMIN, MVT::v4i32, 1 }, 2535 { ISD::UMIN, MVT::v8i16, 1 }, 2536 }; 2537 static const CostTblEntry SSSE3CostTbl[] = { 2538 { ISD::ABS, MVT::v4i32, 1 }, 2539 { ISD::ABS, MVT::v8i16, 1 }, 2540 { ISD::ABS, MVT::v16i8, 1 }, 2541 { ISD::BITREVERSE, MVT::v2i64, 5 }, 2542 { ISD::BITREVERSE, MVT::v4i32, 5 }, 2543 { ISD::BITREVERSE, MVT::v8i16, 5 }, 2544 { ISD::BITREVERSE, MVT::v16i8, 5 }, 2545 { ISD::BSWAP, MVT::v2i64, 1 }, 2546 { ISD::BSWAP, MVT::v4i32, 1 }, 2547 { ISD::BSWAP, MVT::v8i16, 1 }, 2548 { ISD::CTLZ, MVT::v2i64, 23 }, 2549 { ISD::CTLZ, MVT::v4i32, 18 }, 2550 { ISD::CTLZ, MVT::v8i16, 14 }, 2551 { ISD::CTLZ, MVT::v16i8, 9 }, 2552 { ISD::CTPOP, MVT::v2i64, 7 }, 2553 { ISD::CTPOP, MVT::v4i32, 11 }, 2554 { ISD::CTPOP, MVT::v8i16, 9 }, 2555 { ISD::CTPOP, MVT::v16i8, 6 }, 2556 { ISD::CTTZ, MVT::v2i64, 10 }, 2557 { ISD::CTTZ, MVT::v4i32, 14 }, 2558 { ISD::CTTZ, MVT::v8i16, 12 }, 2559 { ISD::CTTZ, MVT::v16i8, 9 } 2560 }; 2561 static const CostTblEntry SSE2CostTbl[] = { 2562 { ISD::ABS, MVT::v2i64, 4 }, 2563 { ISD::ABS, MVT::v4i32, 3 }, 2564 { ISD::ABS, MVT::v8i16, 3 }, 2565 { ISD::ABS, MVT::v16i8, 3 }, 2566 { ISD::BITREVERSE, MVT::v2i64, 29 }, 2567 { ISD::BITREVERSE, MVT::v4i32, 27 }, 2568 { ISD::BITREVERSE, MVT::v8i16, 27 }, 2569 { ISD::BITREVERSE, MVT::v16i8, 20 }, 2570 { ISD::BSWAP, MVT::v2i64, 7 }, 2571 { ISD::BSWAP, MVT::v4i32, 7 }, 2572 { ISD::BSWAP, MVT::v8i16, 7 }, 2573 { ISD::CTLZ, MVT::v2i64, 25 }, 2574 { ISD::CTLZ, MVT::v4i32, 26 }, 2575 { ISD::CTLZ, MVT::v8i16, 20 }, 2576 { ISD::CTLZ, MVT::v16i8, 17 }, 2577 { ISD::CTPOP, MVT::v2i64, 12 }, 2578 { ISD::CTPOP, MVT::v4i32, 15 }, 2579 { ISD::CTPOP, MVT::v8i16, 13 }, 2580 { ISD::CTPOP, MVT::v16i8, 10 }, 2581 { ISD::CTTZ, MVT::v2i64, 14 }, 2582 { ISD::CTTZ, MVT::v4i32, 18 }, 2583 { ISD::CTTZ, MVT::v8i16, 16 }, 2584 { ISD::CTTZ, MVT::v16i8, 13 }, 2585 { ISD::SADDSAT, MVT::v8i16, 1 }, 2586 { ISD::SADDSAT, MVT::v16i8, 1 }, 2587 { ISD::SMAX, MVT::v8i16, 1 }, 2588 { ISD::SMIN, MVT::v8i16, 1 }, 2589 { ISD::SSUBSAT, MVT::v8i16, 1 }, 2590 { ISD::SSUBSAT, MVT::v16i8, 1 }, 2591 { ISD::UADDSAT, MVT::v8i16, 1 }, 2592 { ISD::UADDSAT, MVT::v16i8, 1 }, 2593 { ISD::UMAX, MVT::v16i8, 1 }, 2594 { ISD::UMIN, MVT::v16i8, 1 }, 2595 { ISD::USUBSAT, MVT::v8i16, 1 }, 2596 { ISD::USUBSAT, MVT::v16i8, 1 }, 2597 { ISD::FMAXNUM, MVT::f64, 4 }, 2598 { ISD::FMAXNUM, MVT::v2f64, 4 }, 2599 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 2600 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 2601 }; 2602 static const CostTblEntry SSE1CostTbl[] = { 2603 { ISD::FMAXNUM, MVT::f32, 4 }, 2604 { ISD::FMAXNUM, MVT::v4f32, 4 }, 2605 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 2606 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 2607 }; 2608 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 2609 { ISD::CTTZ, MVT::i64, 1 }, 2610 }; 2611 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 2612 { ISD::CTTZ, MVT::i32, 1 }, 2613 { ISD::CTTZ, MVT::i16, 1 }, 2614 { ISD::CTTZ, MVT::i8, 1 }, 2615 }; 2616 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 2617 { ISD::CTLZ, MVT::i64, 1 }, 2618 }; 2619 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 2620 { ISD::CTLZ, MVT::i32, 1 }, 2621 { ISD::CTLZ, MVT::i16, 1 }, 2622 { ISD::CTLZ, MVT::i8, 1 }, 2623 }; 2624 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 2625 { ISD::CTPOP, MVT::i64, 1 }, 2626 }; 2627 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 2628 { ISD::CTPOP, MVT::i32, 1 }, 2629 { ISD::CTPOP, MVT::i16, 1 }, 2630 { ISD::CTPOP, MVT::i8, 1 }, 2631 }; 2632 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2633 { ISD::BITREVERSE, MVT::i64, 14 }, 2634 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 2635 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 2636 { ISD::CTPOP, MVT::i64, 10 }, 2637 { ISD::SADDO, MVT::i64, 1 }, 2638 { ISD::UADDO, MVT::i64, 1 }, 2639 }; 2640 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2641 { ISD::BITREVERSE, MVT::i32, 14 }, 2642 { ISD::BITREVERSE, MVT::i16, 14 }, 2643 { ISD::BITREVERSE, MVT::i8, 11 }, 2644 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 2645 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 2646 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 2647 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 2648 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 2649 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 2650 { ISD::CTPOP, MVT::i32, 8 }, 2651 { ISD::CTPOP, MVT::i16, 9 }, 2652 { ISD::CTPOP, MVT::i8, 7 }, 2653 { ISD::SADDO, MVT::i32, 1 }, 2654 { ISD::SADDO, MVT::i16, 1 }, 2655 { ISD::SADDO, MVT::i8, 1 }, 2656 { ISD::UADDO, MVT::i32, 1 }, 2657 { ISD::UADDO, MVT::i16, 1 }, 2658 { ISD::UADDO, MVT::i8, 1 }, 2659 }; 2660 2661 Type *RetTy = ICA.getReturnType(); 2662 Type *OpTy = RetTy; 2663 Intrinsic::ID IID = ICA.getID(); 2664 unsigned ISD = ISD::DELETED_NODE; 2665 switch (IID) { 2666 default: 2667 break; 2668 case Intrinsic::abs: 2669 ISD = ISD::ABS; 2670 break; 2671 case Intrinsic::bitreverse: 2672 ISD = ISD::BITREVERSE; 2673 break; 2674 case Intrinsic::bswap: 2675 ISD = ISD::BSWAP; 2676 break; 2677 case Intrinsic::ctlz: 2678 ISD = ISD::CTLZ; 2679 break; 2680 case Intrinsic::ctpop: 2681 ISD = ISD::CTPOP; 2682 break; 2683 case Intrinsic::cttz: 2684 ISD = ISD::CTTZ; 2685 break; 2686 case Intrinsic::maxnum: 2687 case Intrinsic::minnum: 2688 // FMINNUM has same costs so don't duplicate. 2689 ISD = ISD::FMAXNUM; 2690 break; 2691 case Intrinsic::sadd_sat: 2692 ISD = ISD::SADDSAT; 2693 break; 2694 case Intrinsic::smax: 2695 ISD = ISD::SMAX; 2696 break; 2697 case Intrinsic::smin: 2698 ISD = ISD::SMIN; 2699 break; 2700 case Intrinsic::ssub_sat: 2701 ISD = ISD::SSUBSAT; 2702 break; 2703 case Intrinsic::uadd_sat: 2704 ISD = ISD::UADDSAT; 2705 break; 2706 case Intrinsic::umax: 2707 ISD = ISD::UMAX; 2708 break; 2709 case Intrinsic::umin: 2710 ISD = ISD::UMIN; 2711 break; 2712 case Intrinsic::usub_sat: 2713 ISD = ISD::USUBSAT; 2714 break; 2715 case Intrinsic::sqrt: 2716 ISD = ISD::FSQRT; 2717 break; 2718 case Intrinsic::sadd_with_overflow: 2719 case Intrinsic::ssub_with_overflow: 2720 // SSUBO has same costs so don't duplicate. 2721 ISD = ISD::SADDO; 2722 OpTy = RetTy->getContainedType(0); 2723 break; 2724 case Intrinsic::uadd_with_overflow: 2725 case Intrinsic::usub_with_overflow: 2726 // USUBO has same costs so don't duplicate. 2727 ISD = ISD::UADDO; 2728 OpTy = RetTy->getContainedType(0); 2729 break; 2730 } 2731 2732 if (ISD != ISD::DELETED_NODE) { 2733 // Legalize the type. 2734 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 2735 MVT MTy = LT.second; 2736 2737 // Attempt to lookup cost. 2738 if (ST->useGLMDivSqrtCosts()) 2739 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 2740 return LT.first * Entry->Cost; 2741 2742 if (ST->isSLM()) 2743 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2744 return LT.first * Entry->Cost; 2745 2746 if (ST->hasCDI()) 2747 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 2748 return LT.first * Entry->Cost; 2749 2750 if (ST->hasBWI()) 2751 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2752 return LT.first * Entry->Cost; 2753 2754 if (ST->hasAVX512()) 2755 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2756 return LT.first * Entry->Cost; 2757 2758 if (ST->hasXOP()) 2759 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2760 return LT.first * Entry->Cost; 2761 2762 if (ST->hasAVX2()) 2763 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2764 return LT.first * Entry->Cost; 2765 2766 if (ST->hasAVX()) 2767 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2768 return LT.first * Entry->Cost; 2769 2770 if (ST->hasSSE42()) 2771 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2772 return LT.first * Entry->Cost; 2773 2774 if (ST->hasSSE41()) 2775 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2776 return LT.first * Entry->Cost; 2777 2778 if (ST->hasSSSE3()) 2779 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 2780 return LT.first * Entry->Cost; 2781 2782 if (ST->hasSSE2()) 2783 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2784 return LT.first * Entry->Cost; 2785 2786 if (ST->hasSSE1()) 2787 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2788 return LT.first * Entry->Cost; 2789 2790 if (ST->hasBMI()) { 2791 if (ST->is64Bit()) 2792 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 2793 return LT.first * Entry->Cost; 2794 2795 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 2796 return LT.first * Entry->Cost; 2797 } 2798 2799 if (ST->hasLZCNT()) { 2800 if (ST->is64Bit()) 2801 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 2802 return LT.first * Entry->Cost; 2803 2804 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 2805 return LT.first * Entry->Cost; 2806 } 2807 2808 if (ST->hasPOPCNT()) { 2809 if (ST->is64Bit()) 2810 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 2811 return LT.first * Entry->Cost; 2812 2813 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 2814 return LT.first * Entry->Cost; 2815 } 2816 2817 // TODO - add BMI (TZCNT) scalar handling 2818 2819 if (ST->is64Bit()) 2820 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2821 return LT.first * Entry->Cost; 2822 2823 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2824 return LT.first * Entry->Cost; 2825 } 2826 2827 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 2828 } 2829 2830 int X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 2831 TTI::TargetCostKind CostKind) { 2832 if (CostKind != TTI::TCK_RecipThroughput) 2833 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 2834 2835 if (ICA.isTypeBasedOnly()) 2836 return getTypeBasedIntrinsicInstrCost(ICA, CostKind); 2837 2838 static const CostTblEntry AVX512CostTbl[] = { 2839 { ISD::ROTL, MVT::v8i64, 1 }, 2840 { ISD::ROTL, MVT::v4i64, 1 }, 2841 { ISD::ROTL, MVT::v2i64, 1 }, 2842 { ISD::ROTL, MVT::v16i32, 1 }, 2843 { ISD::ROTL, MVT::v8i32, 1 }, 2844 { ISD::ROTL, MVT::v4i32, 1 }, 2845 { ISD::ROTR, MVT::v8i64, 1 }, 2846 { ISD::ROTR, MVT::v4i64, 1 }, 2847 { ISD::ROTR, MVT::v2i64, 1 }, 2848 { ISD::ROTR, MVT::v16i32, 1 }, 2849 { ISD::ROTR, MVT::v8i32, 1 }, 2850 { ISD::ROTR, MVT::v4i32, 1 } 2851 }; 2852 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 2853 static const CostTblEntry XOPCostTbl[] = { 2854 { ISD::ROTL, MVT::v4i64, 4 }, 2855 { ISD::ROTL, MVT::v8i32, 4 }, 2856 { ISD::ROTL, MVT::v16i16, 4 }, 2857 { ISD::ROTL, MVT::v32i8, 4 }, 2858 { ISD::ROTL, MVT::v2i64, 1 }, 2859 { ISD::ROTL, MVT::v4i32, 1 }, 2860 { ISD::ROTL, MVT::v8i16, 1 }, 2861 { ISD::ROTL, MVT::v16i8, 1 }, 2862 { ISD::ROTR, MVT::v4i64, 6 }, 2863 { ISD::ROTR, MVT::v8i32, 6 }, 2864 { ISD::ROTR, MVT::v16i16, 6 }, 2865 { ISD::ROTR, MVT::v32i8, 6 }, 2866 { ISD::ROTR, MVT::v2i64, 2 }, 2867 { ISD::ROTR, MVT::v4i32, 2 }, 2868 { ISD::ROTR, MVT::v8i16, 2 }, 2869 { ISD::ROTR, MVT::v16i8, 2 } 2870 }; 2871 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2872 { ISD::ROTL, MVT::i64, 1 }, 2873 { ISD::ROTR, MVT::i64, 1 }, 2874 { ISD::FSHL, MVT::i64, 4 } 2875 }; 2876 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2877 { ISD::ROTL, MVT::i32, 1 }, 2878 { ISD::ROTL, MVT::i16, 1 }, 2879 { ISD::ROTL, MVT::i8, 1 }, 2880 { ISD::ROTR, MVT::i32, 1 }, 2881 { ISD::ROTR, MVT::i16, 1 }, 2882 { ISD::ROTR, MVT::i8, 1 }, 2883 { ISD::FSHL, MVT::i32, 4 }, 2884 { ISD::FSHL, MVT::i16, 4 }, 2885 { ISD::FSHL, MVT::i8, 4 } 2886 }; 2887 2888 Intrinsic::ID IID = ICA.getID(); 2889 Type *RetTy = ICA.getReturnType(); 2890 const SmallVectorImpl<const Value *> &Args = ICA.getArgs(); 2891 unsigned ISD = ISD::DELETED_NODE; 2892 switch (IID) { 2893 default: 2894 break; 2895 case Intrinsic::fshl: 2896 ISD = ISD::FSHL; 2897 if (Args[0] == Args[1]) 2898 ISD = ISD::ROTL; 2899 break; 2900 case Intrinsic::fshr: 2901 // FSHR has same costs so don't duplicate. 2902 ISD = ISD::FSHL; 2903 if (Args[0] == Args[1]) 2904 ISD = ISD::ROTR; 2905 break; 2906 } 2907 2908 if (ISD != ISD::DELETED_NODE) { 2909 // Legalize the type. 2910 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 2911 MVT MTy = LT.second; 2912 2913 // Attempt to lookup cost. 2914 if (ST->hasAVX512()) 2915 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2916 return LT.first * Entry->Cost; 2917 2918 if (ST->hasXOP()) 2919 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2920 return LT.first * Entry->Cost; 2921 2922 if (ST->is64Bit()) 2923 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2924 return LT.first * Entry->Cost; 2925 2926 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2927 return LT.first * Entry->Cost; 2928 } 2929 2930 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 2931 } 2932 2933 int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { 2934 static const CostTblEntry SLMCostTbl[] = { 2935 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 2936 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 2937 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 2938 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 2939 }; 2940 2941 assert(Val->isVectorTy() && "This must be a vector type"); 2942 Type *ScalarType = Val->getScalarType(); 2943 int RegisterFileMoveCost = 0; 2944 2945 if (Index != -1U && (Opcode == Instruction::ExtractElement || 2946 Opcode == Instruction::InsertElement)) { 2947 // Legalize the type. 2948 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 2949 2950 // This type is legalized to a scalar type. 2951 if (!LT.second.isVector()) 2952 return 0; 2953 2954 // The type may be split. Normalize the index to the new type. 2955 unsigned NumElts = LT.second.getVectorNumElements(); 2956 unsigned SubNumElts = NumElts; 2957 Index = Index % NumElts; 2958 2959 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 2960 // For inserts, we also need to insert the subvector back. 2961 if (LT.second.getSizeInBits() > 128) { 2962 assert((LT.second.getSizeInBits() % 128) == 0 && "Illegal vector"); 2963 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 2964 SubNumElts = NumElts / NumSubVecs; 2965 if (SubNumElts <= Index) { 2966 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 2967 Index %= SubNumElts; 2968 } 2969 } 2970 2971 if (Index == 0) { 2972 // Floating point scalars are already located in index #0. 2973 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 2974 // true for all. 2975 if (ScalarType->isFloatingPointTy()) 2976 return RegisterFileMoveCost; 2977 2978 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 2979 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 2980 return 1 + RegisterFileMoveCost; 2981 } 2982 2983 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2984 assert(ISD && "Unexpected vector opcode"); 2985 MVT MScalarTy = LT.second.getScalarType(); 2986 if (ST->isSLM()) 2987 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 2988 return Entry->Cost + RegisterFileMoveCost; 2989 2990 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 2991 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 2992 (MScalarTy.isInteger() && ST->hasSSE41())) 2993 return 1 + RegisterFileMoveCost; 2994 2995 // Assume insertps is relatively cheap on all targets. 2996 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 2997 Opcode == Instruction::InsertElement) 2998 return 1 + RegisterFileMoveCost; 2999 3000 // For extractions we just need to shuffle the element to index 0, which 3001 // should be very cheap (assume cost = 1). For insertions we need to shuffle 3002 // the elements to its destination. In both cases we must handle the 3003 // subvector move(s). 3004 // If the vector type is already less than 128-bits then don't reduce it. 3005 // TODO: Under what circumstances should we shuffle using the full width? 3006 int ShuffleCost = 1; 3007 if (Opcode == Instruction::InsertElement) { 3008 auto *SubTy = cast<VectorType>(Val); 3009 EVT VT = TLI->getValueType(DL, Val); 3010 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 3011 SubTy = FixedVectorType::get(ScalarType, SubNumElts); 3012 ShuffleCost = getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, 0, SubTy); 3013 } 3014 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 3015 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 3016 } 3017 3018 // Add to the base cost if we know that the extracted element of a vector is 3019 // destined to be moved to and used in the integer register file. 3020 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 3021 RegisterFileMoveCost += 1; 3022 3023 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 3024 } 3025 3026 unsigned X86TTIImpl::getScalarizationOverhead(VectorType *Ty, 3027 const APInt &DemandedElts, 3028 bool Insert, bool Extract) { 3029 unsigned Cost = 0; 3030 3031 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much 3032 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT. 3033 if (Insert) { 3034 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3035 MVT MScalarTy = LT.second.getScalarType(); 3036 3037 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3038 (MScalarTy.isInteger() && ST->hasSSE41()) || 3039 (MScalarTy == MVT::f32 && ST->hasSSE41())) { 3040 // For types we can insert directly, insertion into 128-bit sub vectors is 3041 // cheap, followed by a cheap chain of concatenations. 3042 if (LT.second.getSizeInBits() <= 128) { 3043 Cost += 3044 BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, false); 3045 } else { 3046 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 3047 Cost += (PowerOf2Ceil(NumSubVecs) - 1) * LT.first; 3048 Cost += DemandedElts.countPopulation(); 3049 3050 // For vXf32 cases, insertion into the 0'th index in each v4f32 3051 // 128-bit vector is free. 3052 // NOTE: This assumes legalization widens vXf32 vectors. 3053 if (MScalarTy == MVT::f32) 3054 for (unsigned i = 0, e = cast<FixedVectorType>(Ty)->getNumElements(); 3055 i < e; i += 4) 3056 if (DemandedElts[i]) 3057 Cost--; 3058 } 3059 } else if (LT.second.isVector()) { 3060 // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded 3061 // integer element as a SCALAR_TO_VECTOR, then we build the vector as a 3062 // series of UNPCK followed by CONCAT_VECTORS - all of these can be 3063 // considered cheap. 3064 if (Ty->isIntOrIntVectorTy()) 3065 Cost += DemandedElts.countPopulation(); 3066 3067 // Get the smaller of the legalized or original pow2-extended number of 3068 // vector elements, which represents the number of unpacks we'll end up 3069 // performing. 3070 unsigned NumElts = LT.second.getVectorNumElements(); 3071 unsigned Pow2Elts = 3072 PowerOf2Ceil(cast<FixedVectorType>(Ty)->getNumElements()); 3073 Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first; 3074 } 3075 } 3076 3077 // TODO: Use default extraction for now, but we should investigate extending this 3078 // to handle repeated subvector extraction. 3079 if (Extract) 3080 Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, false, Extract); 3081 3082 return Cost; 3083 } 3084 3085 int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 3086 MaybeAlign Alignment, unsigned AddressSpace, 3087 TTI::TargetCostKind CostKind, 3088 const Instruction *I) { 3089 // TODO: Handle other cost kinds. 3090 if (CostKind != TTI::TCK_RecipThroughput) { 3091 if (isa_and_nonnull<StoreInst>(I)) { 3092 Value *Ptr = I->getOperand(1); 3093 // Store instruction with index and scale costs 2 Uops. 3094 // Check the preceding GEP to identify non-const indices. 3095 if (auto *GEP = dyn_cast<GetElementPtrInst>(Ptr)) { 3096 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3097 return TTI::TCC_Basic * 2; 3098 } 3099 } 3100 return TTI::TCC_Basic; 3101 } 3102 3103 // Handle non-power-of-two vectors such as <3 x float> 3104 if (auto *VTy = dyn_cast<FixedVectorType>(Src)) { 3105 unsigned NumElem = VTy->getNumElements(); 3106 3107 // Handle a few common cases: 3108 // <3 x float> 3109 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 3110 // Cost = 64 bit store + extract + 32 bit store. 3111 return 3; 3112 3113 // <3 x double> 3114 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 3115 // Cost = 128 bit store + unpack + 64 bit store. 3116 return 3; 3117 3118 // Assume that all other non-power-of-two numbers are scalarized. 3119 if (!isPowerOf2_32(NumElem)) { 3120 APInt DemandedElts = APInt::getAllOnesValue(NumElem); 3121 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment, 3122 AddressSpace, CostKind); 3123 int SplitCost = getScalarizationOverhead(VTy, DemandedElts, 3124 Opcode == Instruction::Load, 3125 Opcode == Instruction::Store); 3126 return NumElem * Cost + SplitCost; 3127 } 3128 } 3129 3130 // Type legalization can't handle structs 3131 if (TLI->getValueType(DL, Src, true) == MVT::Other) 3132 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3133 CostKind); 3134 3135 // Legalize the type. 3136 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 3137 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 3138 "Invalid Opcode"); 3139 3140 // Each load/store unit costs 1. 3141 int Cost = LT.first * 1; 3142 3143 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a 3144 // proxy for a double-pumped AVX memory interface such as on Sandybridge. 3145 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow()) 3146 Cost *= 2; 3147 3148 return Cost; 3149 } 3150 3151 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, 3152 Align Alignment, unsigned AddressSpace, 3153 TTI::TargetCostKind CostKind) { 3154 bool IsLoad = (Instruction::Load == Opcode); 3155 bool IsStore = (Instruction::Store == Opcode); 3156 3157 auto *SrcVTy = dyn_cast<FixedVectorType>(SrcTy); 3158 if (!SrcVTy) 3159 // To calculate scalar take the regular cost, without mask 3160 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace, CostKind); 3161 3162 unsigned NumElem = SrcVTy->getNumElements(); 3163 auto *MaskTy = 3164 FixedVectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 3165 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, Alignment)) || 3166 (IsStore && !isLegalMaskedStore(SrcVTy, Alignment)) || 3167 !isPowerOf2_32(NumElem)) { 3168 // Scalarization 3169 APInt DemandedElts = APInt::getAllOnesValue(NumElem); 3170 int MaskSplitCost = 3171 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 3172 int ScalarCompareCost = getCmpSelInstrCost( 3173 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr, 3174 CostKind); 3175 int BranchCost = getCFInstrCost(Instruction::Br, CostKind); 3176 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 3177 int ValueSplitCost = 3178 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore); 3179 int MemopCost = 3180 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3181 Alignment, AddressSpace, CostKind); 3182 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 3183 } 3184 3185 // Legalize the type. 3186 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3187 auto VT = TLI->getValueType(DL, SrcVTy); 3188 int Cost = 0; 3189 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 3190 LT.second.getVectorNumElements() == NumElem) 3191 // Promotion requires expand/truncate for data and a shuffle for mask. 3192 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, 0, nullptr) + 3193 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, 0, nullptr); 3194 3195 else if (LT.second.getVectorNumElements() > NumElem) { 3196 auto *NewMaskTy = FixedVectorType::get(MaskTy->getElementType(), 3197 LT.second.getVectorNumElements()); 3198 // Expanding requires fill mask with zeroes 3199 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, 0, MaskTy); 3200 } 3201 3202 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 3203 if (!ST->hasAVX512()) 3204 return Cost + LT.first * (IsLoad ? 2 : 8); 3205 3206 // AVX-512 masked load/store is cheapper 3207 return Cost + LT.first; 3208 } 3209 3210 int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE, 3211 const SCEV *Ptr) { 3212 // Address computations in vectorized code with non-consecutive addresses will 3213 // likely result in more instructions compared to scalar code where the 3214 // computation can more often be merged into the index mode. The resulting 3215 // extra micro-ops can significantly decrease throughput. 3216 const unsigned NumVectorInstToHideOverhead = 10; 3217 3218 // Cost modeling of Strided Access Computation is hidden by the indexing 3219 // modes of X86 regardless of the stride value. We dont believe that there 3220 // is a difference between constant strided access in gerenal and constant 3221 // strided value which is less than or equal to 64. 3222 // Even in the case of (loop invariant) stride whose value is not known at 3223 // compile time, the address computation will not incur more than one extra 3224 // ADD instruction. 3225 if (Ty->isVectorTy() && SE) { 3226 if (!BaseT::isStridedAccess(Ptr)) 3227 return NumVectorInstToHideOverhead; 3228 if (!BaseT::getConstantStrideStep(SE, Ptr)) 3229 return 1; 3230 } 3231 3232 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 3233 } 3234 3235 int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 3236 bool IsPairwise, 3237 TTI::TargetCostKind CostKind) { 3238 // Just use the default implementation for pair reductions. 3239 if (IsPairwise) 3240 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise, CostKind); 3241 3242 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3243 // and make it as the cost. 3244 3245 static const CostTblEntry SLMCostTblNoPairWise[] = { 3246 { ISD::FADD, MVT::v2f64, 3 }, 3247 { ISD::ADD, MVT::v2i64, 5 }, 3248 }; 3249 3250 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3251 { ISD::FADD, MVT::v2f64, 2 }, 3252 { ISD::FADD, MVT::v4f32, 4 }, 3253 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 3254 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 3255 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 3256 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 3257 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 3258 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 3259 { ISD::ADD, MVT::v2i8, 2 }, 3260 { ISD::ADD, MVT::v4i8, 2 }, 3261 { ISD::ADD, MVT::v8i8, 2 }, 3262 { ISD::ADD, MVT::v16i8, 3 }, 3263 }; 3264 3265 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3266 { ISD::FADD, MVT::v4f64, 3 }, 3267 { ISD::FADD, MVT::v4f32, 3 }, 3268 { ISD::FADD, MVT::v8f32, 4 }, 3269 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 3270 { ISD::ADD, MVT::v4i64, 3 }, 3271 { ISD::ADD, MVT::v8i32, 5 }, 3272 { ISD::ADD, MVT::v16i16, 5 }, 3273 { ISD::ADD, MVT::v32i8, 4 }, 3274 }; 3275 3276 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3277 assert(ISD && "Invalid opcode"); 3278 3279 // Before legalizing the type, give a chance to look up illegal narrow types 3280 // in the table. 3281 // FIXME: Is there a better way to do this? 3282 EVT VT = TLI->getValueType(DL, ValTy); 3283 if (VT.isSimple()) { 3284 MVT MTy = VT.getSimpleVT(); 3285 if (ST->isSLM()) 3286 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3287 return Entry->Cost; 3288 3289 if (ST->hasAVX()) 3290 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3291 return Entry->Cost; 3292 3293 if (ST->hasSSE2()) 3294 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3295 return Entry->Cost; 3296 } 3297 3298 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3299 3300 MVT MTy = LT.second; 3301 3302 auto *ValVTy = cast<FixedVectorType>(ValTy); 3303 3304 unsigned ArithmeticCost = 0; 3305 if (LT.first != 1 && MTy.isVector() && 3306 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3307 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3308 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3309 MTy.getVectorNumElements()); 3310 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3311 ArithmeticCost *= LT.first - 1; 3312 } 3313 3314 if (ST->isSLM()) 3315 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3316 return ArithmeticCost + Entry->Cost; 3317 3318 if (ST->hasAVX()) 3319 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3320 return ArithmeticCost + Entry->Cost; 3321 3322 if (ST->hasSSE2()) 3323 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3324 return ArithmeticCost + Entry->Cost; 3325 3326 // FIXME: These assume a naive kshift+binop lowering, which is probably 3327 // conservative in most cases. 3328 static const CostTblEntry AVX512BoolReduction[] = { 3329 { ISD::AND, MVT::v2i1, 3 }, 3330 { ISD::AND, MVT::v4i1, 5 }, 3331 { ISD::AND, MVT::v8i1, 7 }, 3332 { ISD::AND, MVT::v16i1, 9 }, 3333 { ISD::AND, MVT::v32i1, 11 }, 3334 { ISD::AND, MVT::v64i1, 13 }, 3335 { ISD::OR, MVT::v2i1, 3 }, 3336 { ISD::OR, MVT::v4i1, 5 }, 3337 { ISD::OR, MVT::v8i1, 7 }, 3338 { ISD::OR, MVT::v16i1, 9 }, 3339 { ISD::OR, MVT::v32i1, 11 }, 3340 { ISD::OR, MVT::v64i1, 13 }, 3341 }; 3342 3343 static const CostTblEntry AVX2BoolReduction[] = { 3344 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 3345 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 3346 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 3347 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 3348 }; 3349 3350 static const CostTblEntry AVX1BoolReduction[] = { 3351 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 3352 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 3353 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3354 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3355 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 3356 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 3357 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3358 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3359 }; 3360 3361 static const CostTblEntry SSE2BoolReduction[] = { 3362 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 3363 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 3364 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 3365 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 3366 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 3367 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 3368 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 3369 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 3370 }; 3371 3372 // Handle bool allof/anyof patterns. 3373 if (ValVTy->getElementType()->isIntegerTy(1)) { 3374 unsigned ArithmeticCost = 0; 3375 if (LT.first != 1 && MTy.isVector() && 3376 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3377 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3378 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3379 MTy.getVectorNumElements()); 3380 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3381 ArithmeticCost *= LT.first - 1; 3382 } 3383 3384 if (ST->hasAVX512()) 3385 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 3386 return ArithmeticCost + Entry->Cost; 3387 if (ST->hasAVX2()) 3388 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 3389 return ArithmeticCost + Entry->Cost; 3390 if (ST->hasAVX()) 3391 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 3392 return ArithmeticCost + Entry->Cost; 3393 if (ST->hasSSE2()) 3394 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 3395 return ArithmeticCost + Entry->Cost; 3396 3397 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise, 3398 CostKind); 3399 } 3400 3401 unsigned NumVecElts = ValVTy->getNumElements(); 3402 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 3403 3404 // Special case power of 2 reductions where the scalar type isn't changed 3405 // by type legalization. 3406 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 3407 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise, 3408 CostKind); 3409 3410 unsigned ReductionCost = 0; 3411 3412 auto *Ty = ValVTy; 3413 if (LT.first != 1 && MTy.isVector() && 3414 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3415 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3416 Ty = FixedVectorType::get(ValVTy->getElementType(), 3417 MTy.getVectorNumElements()); 3418 ReductionCost = getArithmeticInstrCost(Opcode, Ty, CostKind); 3419 ReductionCost *= LT.first - 1; 3420 NumVecElts = MTy.getVectorNumElements(); 3421 } 3422 3423 // Now handle reduction with the legal type, taking into account size changes 3424 // at each level. 3425 while (NumVecElts > 1) { 3426 // Determine the size of the remaining vector we need to reduce. 3427 unsigned Size = NumVecElts * ScalarSize; 3428 NumVecElts /= 2; 3429 // If we're reducing from 256/512 bits, use an extract_subvector. 3430 if (Size > 128) { 3431 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 3432 ReductionCost += 3433 getShuffleCost(TTI::SK_ExtractSubvector, Ty, NumVecElts, SubTy); 3434 Ty = SubTy; 3435 } else if (Size == 128) { 3436 // Reducing from 128 bits is a permute of v2f64/v2i64. 3437 FixedVectorType *ShufTy; 3438 if (ValVTy->isFloatingPointTy()) 3439 ShufTy = 3440 FixedVectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 3441 else 3442 ShufTy = 3443 FixedVectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 3444 ReductionCost += 3445 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3446 } else if (Size == 64) { 3447 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3448 FixedVectorType *ShufTy; 3449 if (ValVTy->isFloatingPointTy()) 3450 ShufTy = 3451 FixedVectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 3452 else 3453 ShufTy = 3454 FixedVectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 3455 ReductionCost += 3456 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3457 } else { 3458 // Reducing from smaller size is a shift by immediate. 3459 auto *ShiftTy = FixedVectorType::get( 3460 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 3461 ReductionCost += getArithmeticInstrCost( 3462 Instruction::LShr, ShiftTy, CostKind, 3463 TargetTransformInfo::OK_AnyValue, 3464 TargetTransformInfo::OK_UniformConstantValue, 3465 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3466 } 3467 3468 // Add the arithmetic op for this level. 3469 ReductionCost += getArithmeticInstrCost(Opcode, Ty, CostKind); 3470 } 3471 3472 // Add the final extract element to the cost. 3473 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3474 } 3475 3476 int X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, bool IsUnsigned) { 3477 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3478 3479 MVT MTy = LT.second; 3480 3481 int ISD; 3482 if (Ty->isIntOrIntVectorTy()) { 3483 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3484 } else { 3485 assert(Ty->isFPOrFPVectorTy() && 3486 "Expected float point or integer vector type."); 3487 ISD = ISD::FMINNUM; 3488 } 3489 3490 static const CostTblEntry SSE1CostTbl[] = { 3491 {ISD::FMINNUM, MVT::v4f32, 1}, 3492 }; 3493 3494 static const CostTblEntry SSE2CostTbl[] = { 3495 {ISD::FMINNUM, MVT::v2f64, 1}, 3496 {ISD::SMIN, MVT::v8i16, 1}, 3497 {ISD::UMIN, MVT::v16i8, 1}, 3498 }; 3499 3500 static const CostTblEntry SSE41CostTbl[] = { 3501 {ISD::SMIN, MVT::v4i32, 1}, 3502 {ISD::UMIN, MVT::v4i32, 1}, 3503 {ISD::UMIN, MVT::v8i16, 1}, 3504 {ISD::SMIN, MVT::v16i8, 1}, 3505 }; 3506 3507 static const CostTblEntry SSE42CostTbl[] = { 3508 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 3509 }; 3510 3511 static const CostTblEntry AVX1CostTbl[] = { 3512 {ISD::FMINNUM, MVT::v8f32, 1}, 3513 {ISD::FMINNUM, MVT::v4f64, 1}, 3514 {ISD::SMIN, MVT::v8i32, 3}, 3515 {ISD::UMIN, MVT::v8i32, 3}, 3516 {ISD::SMIN, MVT::v16i16, 3}, 3517 {ISD::UMIN, MVT::v16i16, 3}, 3518 {ISD::SMIN, MVT::v32i8, 3}, 3519 {ISD::UMIN, MVT::v32i8, 3}, 3520 }; 3521 3522 static const CostTblEntry AVX2CostTbl[] = { 3523 {ISD::SMIN, MVT::v8i32, 1}, 3524 {ISD::UMIN, MVT::v8i32, 1}, 3525 {ISD::SMIN, MVT::v16i16, 1}, 3526 {ISD::UMIN, MVT::v16i16, 1}, 3527 {ISD::SMIN, MVT::v32i8, 1}, 3528 {ISD::UMIN, MVT::v32i8, 1}, 3529 }; 3530 3531 static const CostTblEntry AVX512CostTbl[] = { 3532 {ISD::FMINNUM, MVT::v16f32, 1}, 3533 {ISD::FMINNUM, MVT::v8f64, 1}, 3534 {ISD::SMIN, MVT::v2i64, 1}, 3535 {ISD::UMIN, MVT::v2i64, 1}, 3536 {ISD::SMIN, MVT::v4i64, 1}, 3537 {ISD::UMIN, MVT::v4i64, 1}, 3538 {ISD::SMIN, MVT::v8i64, 1}, 3539 {ISD::UMIN, MVT::v8i64, 1}, 3540 {ISD::SMIN, MVT::v16i32, 1}, 3541 {ISD::UMIN, MVT::v16i32, 1}, 3542 }; 3543 3544 static const CostTblEntry AVX512BWCostTbl[] = { 3545 {ISD::SMIN, MVT::v32i16, 1}, 3546 {ISD::UMIN, MVT::v32i16, 1}, 3547 {ISD::SMIN, MVT::v64i8, 1}, 3548 {ISD::UMIN, MVT::v64i8, 1}, 3549 }; 3550 3551 // If we have a native MIN/MAX instruction for this type, use it. 3552 if (ST->hasBWI()) 3553 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3554 return LT.first * Entry->Cost; 3555 3556 if (ST->hasAVX512()) 3557 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3558 return LT.first * Entry->Cost; 3559 3560 if (ST->hasAVX2()) 3561 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3562 return LT.first * Entry->Cost; 3563 3564 if (ST->hasAVX()) 3565 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3566 return LT.first * Entry->Cost; 3567 3568 if (ST->hasSSE42()) 3569 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3570 return LT.first * Entry->Cost; 3571 3572 if (ST->hasSSE41()) 3573 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3574 return LT.first * Entry->Cost; 3575 3576 if (ST->hasSSE2()) 3577 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3578 return LT.first * Entry->Cost; 3579 3580 if (ST->hasSSE1()) 3581 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3582 return LT.first * Entry->Cost; 3583 3584 unsigned CmpOpcode; 3585 if (Ty->isFPOrFPVectorTy()) { 3586 CmpOpcode = Instruction::FCmp; 3587 } else { 3588 assert(Ty->isIntOrIntVectorTy() && 3589 "expecting floating point or integer type for min/max reduction"); 3590 CmpOpcode = Instruction::ICmp; 3591 } 3592 3593 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 3594 // Otherwise fall back to cmp+select. 3595 return getCmpSelInstrCost(CmpOpcode, Ty, CondTy, CostKind) + 3596 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, CostKind); 3597 } 3598 3599 int X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 3600 bool IsPairwise, bool IsUnsigned, 3601 TTI::TargetCostKind CostKind) { 3602 // Just use the default implementation for pair reductions. 3603 if (IsPairwise) 3604 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned, 3605 CostKind); 3606 3607 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3608 3609 MVT MTy = LT.second; 3610 3611 int ISD; 3612 if (ValTy->isIntOrIntVectorTy()) { 3613 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3614 } else { 3615 assert(ValTy->isFPOrFPVectorTy() && 3616 "Expected float point or integer vector type."); 3617 ISD = ISD::FMINNUM; 3618 } 3619 3620 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3621 // and make it as the cost. 3622 3623 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3624 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 3625 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 3626 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 3627 }; 3628 3629 static const CostTblEntry SSE41CostTblNoPairWise[] = { 3630 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 3631 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 3632 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 3633 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 3634 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 3635 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 3636 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 3637 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 3638 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 3639 {ISD::SMIN, MVT::v16i8, 6}, 3640 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 3641 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 3642 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 3643 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 3644 }; 3645 3646 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3647 {ISD::SMIN, MVT::v16i16, 6}, 3648 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 3649 {ISD::SMIN, MVT::v32i8, 8}, 3650 {ISD::UMIN, MVT::v32i8, 8}, 3651 }; 3652 3653 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 3654 {ISD::SMIN, MVT::v32i16, 8}, 3655 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 3656 {ISD::SMIN, MVT::v64i8, 10}, 3657 {ISD::UMIN, MVT::v64i8, 10}, 3658 }; 3659 3660 // Before legalizing the type, give a chance to look up illegal narrow types 3661 // in the table. 3662 // FIXME: Is there a better way to do this? 3663 EVT VT = TLI->getValueType(DL, ValTy); 3664 if (VT.isSimple()) { 3665 MVT MTy = VT.getSimpleVT(); 3666 if (ST->hasBWI()) 3667 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3668 return Entry->Cost; 3669 3670 if (ST->hasAVX()) 3671 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3672 return Entry->Cost; 3673 3674 if (ST->hasSSE41()) 3675 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3676 return Entry->Cost; 3677 3678 if (ST->hasSSE2()) 3679 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3680 return Entry->Cost; 3681 } 3682 3683 auto *ValVTy = cast<FixedVectorType>(ValTy); 3684 unsigned NumVecElts = ValVTy->getNumElements(); 3685 3686 auto *Ty = ValVTy; 3687 unsigned MinMaxCost = 0; 3688 if (LT.first != 1 && MTy.isVector() && 3689 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3690 // Type needs to be split. We need LT.first - 1 operations ops. 3691 Ty = FixedVectorType::get(ValVTy->getElementType(), 3692 MTy.getVectorNumElements()); 3693 auto *SubCondTy = FixedVectorType::get(CondTy->getElementType(), 3694 MTy.getVectorNumElements()); 3695 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3696 MinMaxCost *= LT.first - 1; 3697 NumVecElts = MTy.getVectorNumElements(); 3698 } 3699 3700 if (ST->hasBWI()) 3701 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3702 return MinMaxCost + Entry->Cost; 3703 3704 if (ST->hasAVX()) 3705 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3706 return MinMaxCost + Entry->Cost; 3707 3708 if (ST->hasSSE41()) 3709 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3710 return MinMaxCost + Entry->Cost; 3711 3712 if (ST->hasSSE2()) 3713 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3714 return MinMaxCost + Entry->Cost; 3715 3716 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 3717 3718 // Special case power of 2 reductions where the scalar type isn't changed 3719 // by type legalization. 3720 if (!isPowerOf2_32(ValVTy->getNumElements()) || 3721 ScalarSize != MTy.getScalarSizeInBits()) 3722 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned, 3723 CostKind); 3724 3725 // Now handle reduction with the legal type, taking into account size changes 3726 // at each level. 3727 while (NumVecElts > 1) { 3728 // Determine the size of the remaining vector we need to reduce. 3729 unsigned Size = NumVecElts * ScalarSize; 3730 NumVecElts /= 2; 3731 // If we're reducing from 256/512 bits, use an extract_subvector. 3732 if (Size > 128) { 3733 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 3734 MinMaxCost += 3735 getShuffleCost(TTI::SK_ExtractSubvector, Ty, NumVecElts, SubTy); 3736 Ty = SubTy; 3737 } else if (Size == 128) { 3738 // Reducing from 128 bits is a permute of v2f64/v2i64. 3739 VectorType *ShufTy; 3740 if (ValTy->isFloatingPointTy()) 3741 ShufTy = 3742 FixedVectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 3743 else 3744 ShufTy = FixedVectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 3745 MinMaxCost += 3746 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3747 } else if (Size == 64) { 3748 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3749 FixedVectorType *ShufTy; 3750 if (ValTy->isFloatingPointTy()) 3751 ShufTy = FixedVectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 3752 else 3753 ShufTy = FixedVectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 3754 MinMaxCost += 3755 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3756 } else { 3757 // Reducing from smaller size is a shift by immediate. 3758 auto *ShiftTy = FixedVectorType::get( 3759 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 3760 MinMaxCost += getArithmeticInstrCost( 3761 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, 3762 TargetTransformInfo::OK_AnyValue, 3763 TargetTransformInfo::OK_UniformConstantValue, 3764 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3765 } 3766 3767 // Add the arithmetic op for this level. 3768 auto *SubCondTy = 3769 FixedVectorType::get(CondTy->getElementType(), Ty->getNumElements()); 3770 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3771 } 3772 3773 // Add the final extract element to the cost. 3774 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3775 } 3776 3777 /// Calculate the cost of materializing a 64-bit value. This helper 3778 /// method might only calculate a fraction of a larger immediate. Therefore it 3779 /// is valid to return a cost of ZERO. 3780 int X86TTIImpl::getIntImmCost(int64_t Val) { 3781 if (Val == 0) 3782 return TTI::TCC_Free; 3783 3784 if (isInt<32>(Val)) 3785 return TTI::TCC_Basic; 3786 3787 return 2 * TTI::TCC_Basic; 3788 } 3789 3790 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 3791 TTI::TargetCostKind CostKind) { 3792 assert(Ty->isIntegerTy()); 3793 3794 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3795 if (BitSize == 0) 3796 return ~0U; 3797 3798 // Never hoist constants larger than 128bit, because this might lead to 3799 // incorrect code generation or assertions in codegen. 3800 // Fixme: Create a cost model for types larger than i128 once the codegen 3801 // issues have been fixed. 3802 if (BitSize > 128) 3803 return TTI::TCC_Free; 3804 3805 if (Imm == 0) 3806 return TTI::TCC_Free; 3807 3808 // Sign-extend all constants to a multiple of 64-bit. 3809 APInt ImmVal = Imm; 3810 if (BitSize % 64 != 0) 3811 ImmVal = Imm.sext(alignTo(BitSize, 64)); 3812 3813 // Split the constant into 64-bit chunks and calculate the cost for each 3814 // chunk. 3815 int Cost = 0; 3816 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 3817 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 3818 int64_t Val = Tmp.getSExtValue(); 3819 Cost += getIntImmCost(Val); 3820 } 3821 // We need at least one instruction to materialize the constant. 3822 return std::max(1, Cost); 3823 } 3824 3825 int X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, 3826 Type *Ty, TTI::TargetCostKind CostKind) { 3827 assert(Ty->isIntegerTy()); 3828 3829 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3830 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3831 // here, so that constant hoisting will ignore this constant. 3832 if (BitSize == 0) 3833 return TTI::TCC_Free; 3834 3835 unsigned ImmIdx = ~0U; 3836 switch (Opcode) { 3837 default: 3838 return TTI::TCC_Free; 3839 case Instruction::GetElementPtr: 3840 // Always hoist the base address of a GetElementPtr. This prevents the 3841 // creation of new constants for every base constant that gets constant 3842 // folded with the offset. 3843 if (Idx == 0) 3844 return 2 * TTI::TCC_Basic; 3845 return TTI::TCC_Free; 3846 case Instruction::Store: 3847 ImmIdx = 0; 3848 break; 3849 case Instruction::ICmp: 3850 // This is an imperfect hack to prevent constant hoisting of 3851 // compares that might be trying to check if a 64-bit value fits in 3852 // 32-bits. The backend can optimize these cases using a right shift by 32. 3853 // Ideally we would check the compare predicate here. There also other 3854 // similar immediates the backend can use shifts for. 3855 if (Idx == 1 && Imm.getBitWidth() == 64) { 3856 uint64_t ImmVal = Imm.getZExtValue(); 3857 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 3858 return TTI::TCC_Free; 3859 } 3860 ImmIdx = 1; 3861 break; 3862 case Instruction::And: 3863 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 3864 // by using a 32-bit operation with implicit zero extension. Detect such 3865 // immediates here as the normal path expects bit 31 to be sign extended. 3866 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 3867 return TTI::TCC_Free; 3868 ImmIdx = 1; 3869 break; 3870 case Instruction::Add: 3871 case Instruction::Sub: 3872 // For add/sub, we can use the opposite instruction for INT32_MIN. 3873 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 3874 return TTI::TCC_Free; 3875 ImmIdx = 1; 3876 break; 3877 case Instruction::UDiv: 3878 case Instruction::SDiv: 3879 case Instruction::URem: 3880 case Instruction::SRem: 3881 // Division by constant is typically expanded later into a different 3882 // instruction sequence. This completely changes the constants. 3883 // Report them as "free" to stop ConstantHoist from marking them as opaque. 3884 return TTI::TCC_Free; 3885 case Instruction::Mul: 3886 case Instruction::Or: 3887 case Instruction::Xor: 3888 ImmIdx = 1; 3889 break; 3890 // Always return TCC_Free for the shift value of a shift instruction. 3891 case Instruction::Shl: 3892 case Instruction::LShr: 3893 case Instruction::AShr: 3894 if (Idx == 1) 3895 return TTI::TCC_Free; 3896 break; 3897 case Instruction::Trunc: 3898 case Instruction::ZExt: 3899 case Instruction::SExt: 3900 case Instruction::IntToPtr: 3901 case Instruction::PtrToInt: 3902 case Instruction::BitCast: 3903 case Instruction::PHI: 3904 case Instruction::Call: 3905 case Instruction::Select: 3906 case Instruction::Ret: 3907 case Instruction::Load: 3908 break; 3909 } 3910 3911 if (Idx == ImmIdx) { 3912 int NumConstants = divideCeil(BitSize, 64); 3913 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 3914 return (Cost <= NumConstants * TTI::TCC_Basic) 3915 ? static_cast<int>(TTI::TCC_Free) 3916 : Cost; 3917 } 3918 3919 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 3920 } 3921 3922 int X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 3923 const APInt &Imm, Type *Ty, 3924 TTI::TargetCostKind CostKind) { 3925 assert(Ty->isIntegerTy()); 3926 3927 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3928 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3929 // here, so that constant hoisting will ignore this constant. 3930 if (BitSize == 0) 3931 return TTI::TCC_Free; 3932 3933 switch (IID) { 3934 default: 3935 return TTI::TCC_Free; 3936 case Intrinsic::sadd_with_overflow: 3937 case Intrinsic::uadd_with_overflow: 3938 case Intrinsic::ssub_with_overflow: 3939 case Intrinsic::usub_with_overflow: 3940 case Intrinsic::smul_with_overflow: 3941 case Intrinsic::umul_with_overflow: 3942 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 3943 return TTI::TCC_Free; 3944 break; 3945 case Intrinsic::experimental_stackmap: 3946 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 3947 return TTI::TCC_Free; 3948 break; 3949 case Intrinsic::experimental_patchpoint_void: 3950 case Intrinsic::experimental_patchpoint_i64: 3951 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 3952 return TTI::TCC_Free; 3953 break; 3954 } 3955 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 3956 } 3957 3958 unsigned 3959 X86TTIImpl::getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind) { 3960 if (CostKind != TTI::TCK_RecipThroughput) 3961 return Opcode == Instruction::PHI ? 0 : 1; 3962 // Branches are assumed to be predicted. 3963 return CostKind == TTI::TCK_RecipThroughput ? 0 : 1; 3964 } 3965 3966 int X86TTIImpl::getGatherOverhead() const { 3967 // Some CPUs have more overhead for gather. The specified overhead is relative 3968 // to the Load operation. "2" is the number provided by Intel architects. This 3969 // parameter is used for cost estimation of Gather Op and comparison with 3970 // other alternatives. 3971 // TODO: Remove the explicit hasAVX512()?, That would mean we would only 3972 // enable gather with a -march. 3973 if (ST->hasAVX512() || (ST->hasAVX2() && ST->hasFastGather())) 3974 return 2; 3975 3976 return 1024; 3977 } 3978 3979 int X86TTIImpl::getScatterOverhead() const { 3980 if (ST->hasAVX512()) 3981 return 2; 3982 3983 return 1024; 3984 } 3985 3986 // Return an average cost of Gather / Scatter instruction, maybe improved later 3987 int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, const Value *Ptr, 3988 Align Alignment, unsigned AddressSpace) { 3989 3990 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 3991 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 3992 3993 // Try to reduce index size from 64 bit (default for GEP) 3994 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 3995 // operation will use 16 x 64 indices which do not fit in a zmm and needs 3996 // to split. Also check that the base pointer is the same for all lanes, 3997 // and that there's at most one variable index. 3998 auto getIndexSizeInBits = [](const Value *Ptr, const DataLayout &DL) { 3999 unsigned IndexSize = DL.getPointerSizeInBits(); 4000 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 4001 if (IndexSize < 64 || !GEP) 4002 return IndexSize; 4003 4004 unsigned NumOfVarIndices = 0; 4005 const Value *Ptrs = GEP->getPointerOperand(); 4006 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 4007 return IndexSize; 4008 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 4009 if (isa<Constant>(GEP->getOperand(i))) 4010 continue; 4011 Type *IndxTy = GEP->getOperand(i)->getType(); 4012 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 4013 IndxTy = IndexVTy->getElementType(); 4014 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 4015 !isa<SExtInst>(GEP->getOperand(i))) || 4016 ++NumOfVarIndices > 1) 4017 return IndexSize; // 64 4018 } 4019 return (unsigned)32; 4020 }; 4021 4022 // Trying to reduce IndexSize to 32 bits for vector 16. 4023 // By default the IndexSize is equal to pointer size. 4024 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 4025 ? getIndexSizeInBits(Ptr, DL) 4026 : DL.getPointerSizeInBits(); 4027 4028 auto *IndexVTy = FixedVectorType::get( 4029 IntegerType::get(SrcVTy->getContext(), IndexSize), VF); 4030 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy); 4031 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy); 4032 int SplitFactor = std::max(IdxsLT.first, SrcLT.first); 4033 if (SplitFactor > 1) { 4034 // Handle splitting of vector of pointers 4035 auto *SplitSrcTy = 4036 FixedVectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 4037 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 4038 AddressSpace); 4039 } 4040 4041 // The gather / scatter cost is given by Intel architects. It is a rough 4042 // number since we are looking at one instruction in a time. 4043 const int GSOverhead = (Opcode == Instruction::Load) 4044 ? getGatherOverhead() 4045 : getScatterOverhead(); 4046 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4047 MaybeAlign(Alignment), AddressSpace, 4048 TTI::TCK_RecipThroughput); 4049 } 4050 4051 /// Return the cost of full scalarization of gather / scatter operation. 4052 /// 4053 /// Opcode - Load or Store instruction. 4054 /// SrcVTy - The type of the data vector that should be gathered or scattered. 4055 /// VariableMask - The mask is non-constant at compile time. 4056 /// Alignment - Alignment for one element. 4057 /// AddressSpace - pointer[s] address space. 4058 /// 4059 int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 4060 bool VariableMask, Align Alignment, 4061 unsigned AddressSpace) { 4062 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4063 APInt DemandedElts = APInt::getAllOnesValue(VF); 4064 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4065 4066 int MaskUnpackCost = 0; 4067 if (VariableMask) { 4068 auto *MaskTy = 4069 FixedVectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 4070 MaskUnpackCost = 4071 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 4072 int ScalarCompareCost = 4073 getCmpSelInstrCost(Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), 4074 nullptr, CostKind); 4075 int BranchCost = getCFInstrCost(Instruction::Br, CostKind); 4076 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 4077 } 4078 4079 // The cost of the scalar loads/stores. 4080 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4081 MaybeAlign(Alignment), AddressSpace, 4082 CostKind); 4083 4084 int InsertExtractCost = 0; 4085 if (Opcode == Instruction::Load) 4086 for (unsigned i = 0; i < VF; ++i) 4087 // Add the cost of inserting each scalar load into the vector 4088 InsertExtractCost += 4089 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 4090 else 4091 for (unsigned i = 0; i < VF; ++i) 4092 // Add the cost of extracting each element out of the data vector 4093 InsertExtractCost += 4094 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 4095 4096 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 4097 } 4098 4099 /// Calculate the cost of Gather / Scatter operation 4100 int X86TTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *SrcVTy, 4101 const Value *Ptr, bool VariableMask, 4102 Align Alignment, 4103 TTI::TargetCostKind CostKind, 4104 const Instruction *I = nullptr) { 4105 4106 if (CostKind != TTI::TCK_RecipThroughput) 4107 return 1; 4108 4109 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 4110 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4111 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 4112 if (!PtrTy && Ptr->getType()->isVectorTy()) 4113 PtrTy = dyn_cast<PointerType>( 4114 cast<VectorType>(Ptr->getType())->getElementType()); 4115 assert(PtrTy && "Unexpected type for Ptr argument"); 4116 unsigned AddressSpace = PtrTy->getAddressSpace(); 4117 4118 bool Scalarize = false; 4119 if ((Opcode == Instruction::Load && 4120 !isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4121 (Opcode == Instruction::Store && 4122 !isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4123 Scalarize = true; 4124 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 4125 // Vector-4 of gather/scatter instruction does not exist on KNL. 4126 // We can extend it to 8 elements, but zeroing upper bits of 4127 // the mask vector will add more instructions. Right now we give the scalar 4128 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 4129 // is better in the VariableMask case. 4130 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 4131 Scalarize = true; 4132 4133 if (Scalarize) 4134 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 4135 AddressSpace); 4136 4137 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 4138 } 4139 4140 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 4141 TargetTransformInfo::LSRCost &C2) { 4142 // X86 specific here are "instruction number 1st priority". 4143 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 4144 C1.NumIVMuls, C1.NumBaseAdds, 4145 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 4146 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 4147 C2.NumIVMuls, C2.NumBaseAdds, 4148 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 4149 } 4150 4151 bool X86TTIImpl::canMacroFuseCmp() { 4152 return ST->hasMacroFusion() || ST->hasBranchFusion(); 4153 } 4154 4155 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, Align Alignment) { 4156 if (!ST->hasAVX()) 4157 return false; 4158 4159 // The backend can't handle a single element vector. 4160 if (isa<VectorType>(DataTy) && 4161 cast<FixedVectorType>(DataTy)->getNumElements() == 1) 4162 return false; 4163 Type *ScalarTy = DataTy->getScalarType(); 4164 4165 if (ScalarTy->isPointerTy()) 4166 return true; 4167 4168 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4169 return true; 4170 4171 if (!ScalarTy->isIntegerTy()) 4172 return false; 4173 4174 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4175 return IntWidth == 32 || IntWidth == 64 || 4176 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 4177 } 4178 4179 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, Align Alignment) { 4180 return isLegalMaskedLoad(DataType, Alignment); 4181 } 4182 4183 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 4184 unsigned DataSize = DL.getTypeStoreSize(DataType); 4185 // The only supported nontemporal loads are for aligned vectors of 16 or 32 4186 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 4187 // (the equivalent stores only require AVX). 4188 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 4189 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 4190 4191 return false; 4192 } 4193 4194 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 4195 unsigned DataSize = DL.getTypeStoreSize(DataType); 4196 4197 // SSE4A supports nontemporal stores of float and double at arbitrary 4198 // alignment. 4199 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 4200 return true; 4201 4202 // Besides the SSE4A subtarget exception above, only aligned stores are 4203 // available nontemporaly on any other subtarget. And only stores with a size 4204 // of 4..32 bytes (powers of 2, only) are permitted. 4205 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 4206 !isPowerOf2_32(DataSize)) 4207 return false; 4208 4209 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 4210 // loads require AVX2). 4211 if (DataSize == 32) 4212 return ST->hasAVX(); 4213 else if (DataSize == 16) 4214 return ST->hasSSE1(); 4215 return true; 4216 } 4217 4218 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 4219 if (!isa<VectorType>(DataTy)) 4220 return false; 4221 4222 if (!ST->hasAVX512()) 4223 return false; 4224 4225 // The backend can't handle a single element vector. 4226 if (cast<FixedVectorType>(DataTy)->getNumElements() == 1) 4227 return false; 4228 4229 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 4230 4231 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4232 return true; 4233 4234 if (!ScalarTy->isIntegerTy()) 4235 return false; 4236 4237 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4238 return IntWidth == 32 || IntWidth == 64 || 4239 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 4240 } 4241 4242 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 4243 return isLegalMaskedExpandLoad(DataTy); 4244 } 4245 4246 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, Align Alignment) { 4247 // Some CPUs have better gather performance than others. 4248 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 4249 // enable gather with a -march. 4250 if (!(ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()))) 4251 return false; 4252 4253 // This function is called now in two cases: from the Loop Vectorizer 4254 // and from the Scalarizer. 4255 // When the Loop Vectorizer asks about legality of the feature, 4256 // the vectorization factor is not calculated yet. The Loop Vectorizer 4257 // sends a scalar type and the decision is based on the width of the 4258 // scalar element. 4259 // Later on, the cost model will estimate usage this intrinsic based on 4260 // the vector type. 4261 // The Scalarizer asks again about legality. It sends a vector type. 4262 // In this case we can reject non-power-of-2 vectors. 4263 // We also reject single element vectors as the type legalizer can't 4264 // scalarize it. 4265 if (auto *DataVTy = dyn_cast<FixedVectorType>(DataTy)) { 4266 unsigned NumElts = DataVTy->getNumElements(); 4267 if (NumElts == 1 || !isPowerOf2_32(NumElts)) 4268 return false; 4269 } 4270 Type *ScalarTy = DataTy->getScalarType(); 4271 if (ScalarTy->isPointerTy()) 4272 return true; 4273 4274 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4275 return true; 4276 4277 if (!ScalarTy->isIntegerTy()) 4278 return false; 4279 4280 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4281 return IntWidth == 32 || IntWidth == 64; 4282 } 4283 4284 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, Align Alignment) { 4285 // AVX2 doesn't support scatter 4286 if (!ST->hasAVX512()) 4287 return false; 4288 return isLegalMaskedGather(DataType, Alignment); 4289 } 4290 4291 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 4292 EVT VT = TLI->getValueType(DL, DataType); 4293 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 4294 } 4295 4296 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 4297 return false; 4298 } 4299 4300 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 4301 const Function *Callee) const { 4302 const TargetMachine &TM = getTLI()->getTargetMachine(); 4303 4304 // Work this as a subsetting of subtarget features. 4305 const FeatureBitset &CallerBits = 4306 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 4307 const FeatureBitset &CalleeBits = 4308 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 4309 4310 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 4311 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 4312 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 4313 } 4314 4315 bool X86TTIImpl::areFunctionArgsABICompatible( 4316 const Function *Caller, const Function *Callee, 4317 SmallPtrSetImpl<Argument *> &Args) const { 4318 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args)) 4319 return false; 4320 4321 // If we get here, we know the target features match. If one function 4322 // considers 512-bit vectors legal and the other does not, consider them 4323 // incompatible. 4324 const TargetMachine &TM = getTLI()->getTargetMachine(); 4325 4326 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 4327 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs()) 4328 return true; 4329 4330 // Consider the arguments compatible if they aren't vectors or aggregates. 4331 // FIXME: Look at the size of vectors. 4332 // FIXME: Look at the element types of aggregates to see if there are vectors. 4333 // FIXME: The API of this function seems intended to allow arguments 4334 // to be removed from the set, but the caller doesn't check if the set 4335 // becomes empty so that may not work in practice. 4336 return llvm::none_of(Args, [](Argument *A) { 4337 auto *EltTy = cast<PointerType>(A->getType())->getElementType(); 4338 return EltTy->isVectorTy() || EltTy->isAggregateType(); 4339 }); 4340 } 4341 4342 X86TTIImpl::TTI::MemCmpExpansionOptions 4343 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 4344 TTI::MemCmpExpansionOptions Options; 4345 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 4346 Options.NumLoadsPerBlock = 2; 4347 // All GPR and vector loads can be unaligned. 4348 Options.AllowOverlappingLoads = true; 4349 if (IsZeroCmp) { 4350 // Only enable vector loads for equality comparison. Right now the vector 4351 // version is not as fast for three way compare (see #33329). 4352 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 4353 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 4354 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 4355 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 4356 } 4357 if (ST->is64Bit()) { 4358 Options.LoadSizes.push_back(8); 4359 } 4360 Options.LoadSizes.push_back(4); 4361 Options.LoadSizes.push_back(2); 4362 Options.LoadSizes.push_back(1); 4363 return Options; 4364 } 4365 4366 bool X86TTIImpl::enableInterleavedAccessVectorization() { 4367 // TODO: We expect this to be beneficial regardless of arch, 4368 // but there are currently some unexplained performance artifacts on Atom. 4369 // As a temporary solution, disable on Atom. 4370 return !(ST->isAtom()); 4371 } 4372 4373 // Get estimation for interleaved load/store operations for AVX2. 4374 // \p Factor is the interleaved-access factor (stride) - number of 4375 // (interleaved) elements in the group. 4376 // \p Indices contains the indices for a strided load: when the 4377 // interleaved load has gaps they indicate which elements are used. 4378 // If Indices is empty (or if the number of indices is equal to the size 4379 // of the interleaved-access as given in \p Factor) the access has no gaps. 4380 // 4381 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 4382 // computing the cost using a generic formula as a function of generic 4383 // shuffles. We therefore use a lookup table instead, filled according to 4384 // the instruction sequences that codegen currently generates. 4385 int X86TTIImpl::getInterleavedMemoryOpCostAVX2( 4386 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 4387 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 4388 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 4389 4390 if (UseMaskForCond || UseMaskForGaps) 4391 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4392 Alignment, AddressSpace, CostKind, 4393 UseMaskForCond, UseMaskForGaps); 4394 4395 // We currently Support only fully-interleaved groups, with no gaps. 4396 // TODO: Support also strided loads (interleaved-groups with gaps). 4397 if (Indices.size() && Indices.size() != Factor) 4398 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4399 Alignment, AddressSpace, 4400 CostKind); 4401 4402 // VecTy for interleave memop is <VF*Factor x Elt>. 4403 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4404 // VecTy = <12 x i32>. 4405 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4406 4407 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 4408 // the VF=2, while v2i128 is an unsupported MVT vector type 4409 // (see MachineValueType.h::getVectorVT()). 4410 if (!LegalVT.isVector()) 4411 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4412 Alignment, AddressSpace, 4413 CostKind); 4414 4415 unsigned VF = VecTy->getNumElements() / Factor; 4416 Type *ScalarTy = VecTy->getElementType(); 4417 4418 // Calculate the number of memory operations (NumOfMemOps), required 4419 // for load/store the VecTy. 4420 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4421 unsigned LegalVTSize = LegalVT.getStoreSize(); 4422 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4423 4424 // Get the cost of one memory operation. 4425 auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(), 4426 LegalVT.getVectorNumElements()); 4427 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 4428 MaybeAlign(Alignment), AddressSpace, 4429 CostKind); 4430 4431 auto *VT = FixedVectorType::get(ScalarTy, VF); 4432 EVT ETy = TLI->getValueType(DL, VT); 4433 if (!ETy.isSimple()) 4434 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4435 Alignment, AddressSpace, 4436 CostKind); 4437 4438 // TODO: Complete for other data-types and strides. 4439 // Each combination of Stride, ElementTy and VF results in a different 4440 // sequence; The cost tables are therefore accessed with: 4441 // Factor (stride) and VectorType=VFxElemType. 4442 // The Cost accounts only for the shuffle sequence; 4443 // The cost of the loads/stores is accounted for separately. 4444 // 4445 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 4446 { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64 4447 { 2, MVT::v4f64, 6 }, //(load 8f64 and) deinterleave into 2 x 4f64 4448 4449 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8 4450 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8 4451 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8 4452 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8 4453 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8 4454 { 3, MVT::v8f32, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32 4455 4456 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8 4457 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8 4458 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8 4459 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8 4460 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8 4461 4462 { 8, MVT::v8f32, 40 } //(load 64f32 and)deinterleave into 8 x 8f32 4463 }; 4464 4465 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 4466 { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store) 4467 { 2, MVT::v4f64, 6 }, //interleave into 2 x 4f64 into 8f64 (and store) 4468 4469 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store) 4470 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store) 4471 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store) 4472 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store) 4473 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store) 4474 4475 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store) 4476 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store) 4477 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store) 4478 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store) 4479 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store) 4480 }; 4481 4482 if (Opcode == Instruction::Load) { 4483 if (const auto *Entry = 4484 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 4485 return NumOfMemOps * MemOpCost + Entry->Cost; 4486 } else { 4487 assert(Opcode == Instruction::Store && 4488 "Expected Store Instruction at this point"); 4489 if (const auto *Entry = 4490 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 4491 return NumOfMemOps * MemOpCost + Entry->Cost; 4492 } 4493 4494 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4495 Alignment, AddressSpace, CostKind); 4496 } 4497 4498 // Get estimation for interleaved load/store operations and strided load. 4499 // \p Indices contains indices for strided load. 4500 // \p Factor - the factor of interleaving. 4501 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 4502 int X86TTIImpl::getInterleavedMemoryOpCostAVX512( 4503 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 4504 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 4505 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 4506 4507 if (UseMaskForCond || UseMaskForGaps) 4508 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4509 Alignment, AddressSpace, CostKind, 4510 UseMaskForCond, UseMaskForGaps); 4511 4512 // VecTy for interleave memop is <VF*Factor x Elt>. 4513 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4514 // VecTy = <12 x i32>. 4515 4516 // Calculate the number of memory operations (NumOfMemOps), required 4517 // for load/store the VecTy. 4518 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4519 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4520 unsigned LegalVTSize = LegalVT.getStoreSize(); 4521 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4522 4523 // Get the cost of one memory operation. 4524 auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(), 4525 LegalVT.getVectorNumElements()); 4526 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 4527 MaybeAlign(Alignment), AddressSpace, 4528 CostKind); 4529 4530 unsigned VF = VecTy->getNumElements() / Factor; 4531 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 4532 4533 if (Opcode == Instruction::Load) { 4534 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 4535 // contain the cost of the optimized shuffle sequence that the 4536 // X86InterleavedAccess pass will generate. 4537 // The cost of loads and stores are computed separately from the table. 4538 4539 // X86InterleavedAccess support only the following interleaved-access group. 4540 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 4541 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 4542 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 4543 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 4544 }; 4545 4546 if (const auto *Entry = 4547 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 4548 return NumOfMemOps * MemOpCost + Entry->Cost; 4549 //If an entry does not exist, fallback to the default implementation. 4550 4551 // Kind of shuffle depends on number of loaded values. 4552 // If we load the entire data in one register, we can use a 1-src shuffle. 4553 // Otherwise, we'll merge 2 sources in each operation. 4554 TTI::ShuffleKind ShuffleKind = 4555 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 4556 4557 unsigned ShuffleCost = 4558 getShuffleCost(ShuffleKind, SingleMemOpTy, 0, nullptr); 4559 4560 unsigned NumOfLoadsInInterleaveGrp = 4561 Indices.size() ? Indices.size() : Factor; 4562 auto *ResultTy = FixedVectorType::get(VecTy->getElementType(), 4563 VecTy->getNumElements() / Factor); 4564 unsigned NumOfResults = 4565 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 4566 NumOfLoadsInInterleaveGrp; 4567 4568 // About a half of the loads may be folded in shuffles when we have only 4569 // one result. If we have more than one result, we do not fold loads at all. 4570 unsigned NumOfUnfoldedLoads = 4571 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 4572 4573 // Get a number of shuffle operations per result. 4574 unsigned NumOfShufflesPerResult = 4575 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 4576 4577 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4578 // When we have more than one destination, we need additional instructions 4579 // to keep sources. 4580 unsigned NumOfMoves = 0; 4581 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 4582 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 4583 4584 int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 4585 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 4586 4587 return Cost; 4588 } 4589 4590 // Store. 4591 assert(Opcode == Instruction::Store && 4592 "Expected Store Instruction at this point"); 4593 // X86InterleavedAccess support only the following interleaved-access group. 4594 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 4595 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 4596 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 4597 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 4598 4599 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 4600 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 4601 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 4602 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 4603 }; 4604 4605 if (const auto *Entry = 4606 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 4607 return NumOfMemOps * MemOpCost + Entry->Cost; 4608 //If an entry does not exist, fallback to the default implementation. 4609 4610 // There is no strided stores meanwhile. And store can't be folded in 4611 // shuffle. 4612 unsigned NumOfSources = Factor; // The number of values to be merged. 4613 unsigned ShuffleCost = 4614 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, 0, nullptr); 4615 unsigned NumOfShufflesPerStore = NumOfSources - 1; 4616 4617 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4618 // We need additional instructions to keep sources. 4619 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 4620 int Cost = NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 4621 NumOfMoves; 4622 return Cost; 4623 } 4624 4625 int X86TTIImpl::getInterleavedMemoryOpCost( 4626 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, 4627 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, 4628 bool UseMaskForCond, bool UseMaskForGaps) { 4629 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 4630 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 4631 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 4632 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 4633 return true; 4634 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 4635 return HasBW; 4636 return false; 4637 }; 4638 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 4639 return getInterleavedMemoryOpCostAVX512( 4640 Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment, 4641 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 4642 if (ST->hasAVX2()) 4643 return getInterleavedMemoryOpCostAVX2( 4644 Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment, 4645 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 4646 4647 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4648 Alignment, AddressSpace, CostKind, 4649 UseMaskForCond, UseMaskForGaps); 4650 } 4651