1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // X86 cost model. 56 // 57 //===----------------------------------------------------------------------===// 58 59 TargetTransformInfo::PopcntSupportKind 60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 61 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 62 // TODO: Currently the __builtin_popcount() implementation using SSE3 63 // instructions is inefficient. Once the problem is fixed, we should 64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 66 } 67 68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 69 TargetTransformInfo::CacheLevel Level) const { 70 switch (Level) { 71 case TargetTransformInfo::CacheLevel::L1D: 72 // - Penryn 73 // - Nehalem 74 // - Westmere 75 // - Sandy Bridge 76 // - Ivy Bridge 77 // - Haswell 78 // - Broadwell 79 // - Skylake 80 // - Kabylake 81 return 32 * 1024; // 32 KByte 82 case TargetTransformInfo::CacheLevel::L2D: 83 // - Penryn 84 // - Nehalem 85 // - Westmere 86 // - Sandy Bridge 87 // - Ivy Bridge 88 // - Haswell 89 // - Broadwell 90 // - Skylake 91 // - Kabylake 92 return 256 * 1024; // 256 KByte 93 } 94 95 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 96 } 97 98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 99 TargetTransformInfo::CacheLevel Level) const { 100 // - Penryn 101 // - Nehalem 102 // - Westmere 103 // - Sandy Bridge 104 // - Ivy Bridge 105 // - Haswell 106 // - Broadwell 107 // - Skylake 108 // - Kabylake 109 switch (Level) { 110 case TargetTransformInfo::CacheLevel::L1D: 111 LLVM_FALLTHROUGH; 112 case TargetTransformInfo::CacheLevel::L2D: 113 return 8; 114 } 115 116 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 117 } 118 119 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 120 bool Vector = (ClassID == 1); 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const { 133 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 134 if (Vector) { 135 if (ST->hasAVX512() && PreferVectorWidth >= 512) 136 return 512; 137 if (ST->hasAVX() && PreferVectorWidth >= 256) 138 return 256; 139 if (ST->hasSSE1() && PreferVectorWidth >= 128) 140 return 128; 141 return 0; 142 } 143 144 if (ST->is64Bit()) 145 return 64; 146 147 return 32; 148 } 149 150 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 151 return getRegisterBitWidth(true); 152 } 153 154 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 155 // If the loop will not be vectorized, don't interleave the loop. 156 // Let regular unroll to unroll the loop, which saves the overflow 157 // check and memory check cost. 158 if (VF == 1) 159 return 1; 160 161 if (ST->isAtom()) 162 return 1; 163 164 // Sandybridge and Haswell have multiple execution ports and pipelined 165 // vector units. 166 if (ST->hasAVX()) 167 return 4; 168 169 return 2; 170 } 171 172 int X86TTIImpl::getArithmeticInstrCost(unsigned Opcode, Type *Ty, 173 TTI::OperandValueKind Op1Info, 174 TTI::OperandValueKind Op2Info, 175 TTI::OperandValueProperties Opd1PropInfo, 176 TTI::OperandValueProperties Opd2PropInfo, 177 ArrayRef<const Value *> Args, 178 const Instruction *CxtI) { 179 // Legalize the type. 180 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 181 182 int ISD = TLI->InstructionOpcodeToISD(Opcode); 183 assert(ISD && "Invalid opcode"); 184 185 static const CostTblEntry GLMCostTable[] = { 186 { ISD::FDIV, MVT::f32, 18 }, // divss 187 { ISD::FDIV, MVT::v4f32, 35 }, // divps 188 { ISD::FDIV, MVT::f64, 33 }, // divsd 189 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 190 }; 191 192 if (ST->useGLMDivSqrtCosts()) 193 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 194 LT.second)) 195 return LT.first * Entry->Cost; 196 197 static const CostTblEntry SLMCostTable[] = { 198 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 199 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 200 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. 201 { ISD::FMUL, MVT::f64, 2 }, // mulsd 202 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 203 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 204 { ISD::FDIV, MVT::f32, 17 }, // divss 205 { ISD::FDIV, MVT::v4f32, 39 }, // divps 206 { ISD::FDIV, MVT::f64, 32 }, // divsd 207 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 208 { ISD::FADD, MVT::v2f64, 2 }, // addpd 209 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 210 // v2i64/v4i64 mul is custom lowered as a series of long: 211 // multiplies(3), shifts(3) and adds(2) 212 // slm muldq version throughput is 2 and addq throughput 4 213 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 214 // 3X4 (addq throughput) = 17 215 { ISD::MUL, MVT::v2i64, 17 }, 216 // slm addq\subq throughput is 4 217 { ISD::ADD, MVT::v2i64, 4 }, 218 { ISD::SUB, MVT::v2i64, 4 }, 219 }; 220 221 if (ST->isSLM()) { 222 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 223 // Check if the operands can be shrinked into a smaller datatype. 224 bool Op1Signed = false; 225 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 226 bool Op2Signed = false; 227 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 228 229 bool signedMode = Op1Signed | Op2Signed; 230 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 231 232 if (OpMinSize <= 7) 233 return LT.first * 3; // pmullw/sext 234 if (!signedMode && OpMinSize <= 8) 235 return LT.first * 3; // pmullw/zext 236 if (OpMinSize <= 15) 237 return LT.first * 5; // pmullw/pmulhw/pshuf 238 if (!signedMode && OpMinSize <= 16) 239 return LT.first * 5; // pmullw/pmulhw/pshuf 240 } 241 242 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 243 LT.second)) { 244 return LT.first * Entry->Cost; 245 } 246 } 247 248 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 249 ISD == ISD::UREM) && 250 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 251 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 252 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 253 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 254 // On X86, vector signed division by constants power-of-two are 255 // normally expanded to the sequence SRA + SRL + ADD + SRA. 256 // The OperandValue properties may not be the same as that of the previous 257 // operation; conservatively assume OP_None. 258 int Cost = 259 2 * getArithmeticInstrCost(Instruction::AShr, Ty, Op1Info, Op2Info, 260 TargetTransformInfo::OP_None, 261 TargetTransformInfo::OP_None); 262 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 263 TargetTransformInfo::OP_None, 264 TargetTransformInfo::OP_None); 265 Cost += getArithmeticInstrCost(Instruction::Add, Ty, Op1Info, Op2Info, 266 TargetTransformInfo::OP_None, 267 TargetTransformInfo::OP_None); 268 269 if (ISD == ISD::SREM) { 270 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 271 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info); 272 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, Op1Info, Op2Info); 273 } 274 275 return Cost; 276 } 277 278 // Vector unsigned division/remainder will be simplified to shifts/masks. 279 if (ISD == ISD::UDIV) 280 return getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 281 TargetTransformInfo::OP_None, 282 TargetTransformInfo::OP_None); 283 284 else // UREM 285 return getArithmeticInstrCost(Instruction::And, Ty, Op1Info, Op2Info, 286 TargetTransformInfo::OP_None, 287 TargetTransformInfo::OP_None); 288 } 289 290 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 291 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 292 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 293 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 294 }; 295 296 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 297 ST->hasBWI()) { 298 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 299 LT.second)) 300 return LT.first * Entry->Cost; 301 } 302 303 static const CostTblEntry AVX512UniformConstCostTable[] = { 304 { ISD::SRA, MVT::v2i64, 1 }, 305 { ISD::SRA, MVT::v4i64, 1 }, 306 { ISD::SRA, MVT::v8i64, 1 }, 307 308 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 309 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 310 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 311 }; 312 313 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 314 ST->hasAVX512()) { 315 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 316 LT.second)) 317 return LT.first * Entry->Cost; 318 } 319 320 static const CostTblEntry AVX2UniformConstCostTable[] = { 321 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 322 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 323 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 324 325 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 326 }; 327 328 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 329 ST->hasAVX2()) { 330 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 331 LT.second)) 332 return LT.first * Entry->Cost; 333 } 334 335 static const CostTblEntry SSE2UniformConstCostTable[] = { 336 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 337 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 338 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 339 340 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 341 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 342 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 343 }; 344 345 // XOP has faster vXi8 shifts. 346 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 347 ST->hasSSE2() && !ST->hasXOP()) { 348 if (const auto *Entry = 349 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 350 return LT.first * Entry->Cost; 351 } 352 353 static const CostTblEntry AVX512BWConstCostTable[] = { 354 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 355 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 356 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 357 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 358 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 359 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 360 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 361 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 362 }; 363 364 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 365 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 366 ST->hasBWI()) { 367 if (const auto *Entry = 368 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 369 return LT.first * Entry->Cost; 370 } 371 372 static const CostTblEntry AVX512ConstCostTable[] = { 373 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 374 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 375 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 376 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 377 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 378 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 379 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 380 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 381 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 382 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 383 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 384 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 385 }; 386 387 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 388 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 389 ST->hasAVX512()) { 390 if (const auto *Entry = 391 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 392 return LT.first * Entry->Cost; 393 } 394 395 static const CostTblEntry AVX2ConstCostTable[] = { 396 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 397 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 398 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 399 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 400 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 401 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 402 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 403 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 404 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 405 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 406 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 407 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 408 }; 409 410 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 411 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 412 ST->hasAVX2()) { 413 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 414 return LT.first * Entry->Cost; 415 } 416 417 static const CostTblEntry SSE2ConstCostTable[] = { 418 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 419 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 420 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 421 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 422 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 423 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 424 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 425 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 426 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 427 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 428 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 429 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 430 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 431 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 432 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 433 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 434 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 435 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 436 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 437 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 438 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 439 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 440 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 441 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 442 }; 443 444 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 445 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 446 ST->hasSSE2()) { 447 // pmuldq sequence. 448 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 449 return LT.first * 32; 450 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 451 return LT.first * 38; 452 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 453 return LT.first * 15; 454 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 455 return LT.first * 20; 456 457 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 458 return LT.first * Entry->Cost; 459 } 460 461 static const CostTblEntry AVX512BWShiftCostTable[] = { 462 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 463 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 464 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 465 466 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 467 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 468 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 469 470 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 471 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 472 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 473 }; 474 475 if (ST->hasBWI()) 476 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 477 return LT.first * Entry->Cost; 478 479 static const CostTblEntry AVX2UniformCostTable[] = { 480 // Uniform splats are cheaper for the following instructions. 481 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 482 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 483 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 484 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 485 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 486 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 487 }; 488 489 if (ST->hasAVX2() && 490 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 491 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 492 if (const auto *Entry = 493 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 494 return LT.first * Entry->Cost; 495 } 496 497 static const CostTblEntry SSE2UniformCostTable[] = { 498 // Uniform splats are cheaper for the following instructions. 499 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 500 { ISD::SHL, MVT::v4i32, 1 }, // pslld 501 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 502 503 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 504 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 505 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 506 507 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 508 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 509 }; 510 511 if (ST->hasSSE2() && 512 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 513 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 514 if (const auto *Entry = 515 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 516 return LT.first * Entry->Cost; 517 } 518 519 static const CostTblEntry AVX512DQCostTable[] = { 520 { ISD::MUL, MVT::v2i64, 1 }, 521 { ISD::MUL, MVT::v4i64, 1 }, 522 { ISD::MUL, MVT::v8i64, 1 } 523 }; 524 525 // Look for AVX512DQ lowering tricks for custom cases. 526 if (ST->hasDQI()) 527 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 528 return LT.first * Entry->Cost; 529 530 static const CostTblEntry AVX512BWCostTable[] = { 531 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 532 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 533 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 534 535 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence. 536 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence. 537 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence. 538 }; 539 540 // Look for AVX512BW lowering tricks for custom cases. 541 if (ST->hasBWI()) 542 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 543 return LT.first * Entry->Cost; 544 545 static const CostTblEntry AVX512CostTable[] = { 546 { ISD::SHL, MVT::v16i32, 1 }, 547 { ISD::SRL, MVT::v16i32, 1 }, 548 { ISD::SRA, MVT::v16i32, 1 }, 549 550 { ISD::SHL, MVT::v8i64, 1 }, 551 { ISD::SRL, MVT::v8i64, 1 }, 552 553 { ISD::SRA, MVT::v2i64, 1 }, 554 { ISD::SRA, MVT::v4i64, 1 }, 555 { ISD::SRA, MVT::v8i64, 1 }, 556 557 { ISD::MUL, MVT::v64i8, 26 }, // extend/pmullw/trunc sequence. 558 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence. 559 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence. 560 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 561 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 562 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 563 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add 564 565 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 566 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 567 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 568 569 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 570 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 571 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 572 }; 573 574 if (ST->hasAVX512()) 575 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 576 return LT.first * Entry->Cost; 577 578 static const CostTblEntry AVX2ShiftCostTable[] = { 579 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 580 // customize them to detect the cases where shift amount is a scalar one. 581 { ISD::SHL, MVT::v4i32, 1 }, 582 { ISD::SRL, MVT::v4i32, 1 }, 583 { ISD::SRA, MVT::v4i32, 1 }, 584 { ISD::SHL, MVT::v8i32, 1 }, 585 { ISD::SRL, MVT::v8i32, 1 }, 586 { ISD::SRA, MVT::v8i32, 1 }, 587 { ISD::SHL, MVT::v2i64, 1 }, 588 { ISD::SRL, MVT::v2i64, 1 }, 589 { ISD::SHL, MVT::v4i64, 1 }, 590 { ISD::SRL, MVT::v4i64, 1 }, 591 }; 592 593 if (ST->hasAVX512()) { 594 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 595 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 596 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 597 // On AVX512, a packed v32i16 shift left by a constant build_vector 598 // is lowered into a vector multiply (vpmullw). 599 return getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info, 600 TargetTransformInfo::OP_None, 601 TargetTransformInfo::OP_None); 602 } 603 604 // Look for AVX2 lowering tricks. 605 if (ST->hasAVX2()) { 606 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 607 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 608 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 609 // On AVX2, a packed v16i16 shift left by a constant build_vector 610 // is lowered into a vector multiply (vpmullw). 611 return getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info, 612 TargetTransformInfo::OP_None, 613 TargetTransformInfo::OP_None); 614 615 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 616 return LT.first * Entry->Cost; 617 } 618 619 static const CostTblEntry XOPShiftCostTable[] = { 620 // 128bit shifts take 1cy, but right shifts require negation beforehand. 621 { ISD::SHL, MVT::v16i8, 1 }, 622 { ISD::SRL, MVT::v16i8, 2 }, 623 { ISD::SRA, MVT::v16i8, 2 }, 624 { ISD::SHL, MVT::v8i16, 1 }, 625 { ISD::SRL, MVT::v8i16, 2 }, 626 { ISD::SRA, MVT::v8i16, 2 }, 627 { ISD::SHL, MVT::v4i32, 1 }, 628 { ISD::SRL, MVT::v4i32, 2 }, 629 { ISD::SRA, MVT::v4i32, 2 }, 630 { ISD::SHL, MVT::v2i64, 1 }, 631 { ISD::SRL, MVT::v2i64, 2 }, 632 { ISD::SRA, MVT::v2i64, 2 }, 633 // 256bit shifts require splitting if AVX2 didn't catch them above. 634 { ISD::SHL, MVT::v32i8, 2+2 }, 635 { ISD::SRL, MVT::v32i8, 4+2 }, 636 { ISD::SRA, MVT::v32i8, 4+2 }, 637 { ISD::SHL, MVT::v16i16, 2+2 }, 638 { ISD::SRL, MVT::v16i16, 4+2 }, 639 { ISD::SRA, MVT::v16i16, 4+2 }, 640 { ISD::SHL, MVT::v8i32, 2+2 }, 641 { ISD::SRL, MVT::v8i32, 4+2 }, 642 { ISD::SRA, MVT::v8i32, 4+2 }, 643 { ISD::SHL, MVT::v4i64, 2+2 }, 644 { ISD::SRL, MVT::v4i64, 4+2 }, 645 { ISD::SRA, MVT::v4i64, 4+2 }, 646 }; 647 648 // Look for XOP lowering tricks. 649 if (ST->hasXOP()) { 650 // If the right shift is constant then we'll fold the negation so 651 // it's as cheap as a left shift. 652 int ShiftISD = ISD; 653 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 654 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 655 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 656 ShiftISD = ISD::SHL; 657 if (const auto *Entry = 658 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 659 return LT.first * Entry->Cost; 660 } 661 662 static const CostTblEntry SSE2UniformShiftCostTable[] = { 663 // Uniform splats are cheaper for the following instructions. 664 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 665 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 666 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 667 668 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 669 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 670 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 671 672 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 673 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 674 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 675 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 676 }; 677 678 if (ST->hasSSE2() && 679 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 680 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 681 682 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 683 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 684 return LT.first * 4; // 2*psrad + shuffle. 685 686 if (const auto *Entry = 687 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 688 return LT.first * Entry->Cost; 689 } 690 691 if (ISD == ISD::SHL && 692 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 693 MVT VT = LT.second; 694 // Vector shift left by non uniform constant can be lowered 695 // into vector multiply. 696 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 697 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 698 ISD = ISD::MUL; 699 } 700 701 static const CostTblEntry AVX2CostTable[] = { 702 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. 703 { ISD::SHL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. 704 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 705 { ISD::SHL, MVT::v32i16, 20 }, // 2*extend/vpsrlvd/pack sequence. 706 707 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. 708 { ISD::SRL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. 709 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 710 { ISD::SRL, MVT::v32i16, 20 }, // 2*extend/vpsrlvd/pack sequence. 711 712 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. 713 { ISD::SRA, MVT::v64i8, 48 }, // 2*vpblendvb sequence. 714 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. 715 { ISD::SRA, MVT::v32i16, 20 }, // 2*extend/vpsravd/pack sequence. 716 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. 717 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 718 719 { ISD::SUB, MVT::v32i8, 1 }, // psubb 720 { ISD::ADD, MVT::v32i8, 1 }, // paddb 721 { ISD::SUB, MVT::v16i16, 1 }, // psubw 722 { ISD::ADD, MVT::v16i16, 1 }, // paddw 723 { ISD::SUB, MVT::v8i32, 1 }, // psubd 724 { ISD::ADD, MVT::v8i32, 1 }, // paddd 725 { ISD::SUB, MVT::v4i64, 1 }, // psubq 726 { ISD::ADD, MVT::v4i64, 1 }, // paddq 727 728 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence. 729 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence. 730 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 731 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 732 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add 733 734 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 735 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 736 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 737 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 738 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 739 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 740 741 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 742 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 743 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 744 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 745 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 746 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 747 }; 748 749 // Look for AVX2 lowering tricks for custom cases. 750 if (ST->hasAVX2()) 751 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 752 return LT.first * Entry->Cost; 753 754 static const CostTblEntry AVX1CostTable[] = { 755 // We don't have to scalarize unsupported ops. We can issue two half-sized 756 // operations and we only need to extract the upper YMM half. 757 // Two ops + 1 extract + 1 insert = 4. 758 { ISD::MUL, MVT::v16i16, 4 }, 759 { ISD::MUL, MVT::v8i32, 4 }, 760 { ISD::SUB, MVT::v32i8, 4 }, 761 { ISD::ADD, MVT::v32i8, 4 }, 762 { ISD::SUB, MVT::v16i16, 4 }, 763 { ISD::ADD, MVT::v16i16, 4 }, 764 { ISD::SUB, MVT::v8i32, 4 }, 765 { ISD::ADD, MVT::v8i32, 4 }, 766 { ISD::SUB, MVT::v4i64, 4 }, 767 { ISD::ADD, MVT::v4i64, 4 }, 768 769 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 770 // are lowered as a series of long multiplies(3), shifts(3) and adds(2) 771 // Because we believe v4i64 to be a legal type, we must also include the 772 // extract+insert in the cost table. Therefore, the cost here is 18 773 // instead of 8. 774 { ISD::MUL, MVT::v4i64, 18 }, 775 776 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence. 777 778 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 779 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 780 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 781 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 782 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 783 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 784 }; 785 786 if (ST->hasAVX()) 787 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 788 return LT.first * Entry->Cost; 789 790 static const CostTblEntry SSE42CostTable[] = { 791 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 792 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 793 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 794 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 795 796 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 797 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 798 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 799 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 800 801 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 802 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 803 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 804 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 805 806 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 807 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 808 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 809 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 810 }; 811 812 if (ST->hasSSE42()) 813 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 814 return LT.first * Entry->Cost; 815 816 static const CostTblEntry SSE41CostTable[] = { 817 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 818 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split. 819 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 820 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 821 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 822 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split 823 824 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 825 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split. 826 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 827 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 828 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 829 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split. 830 831 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 832 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split. 833 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 834 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 835 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 836 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split. 837 838 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 839 }; 840 841 if (ST->hasSSE41()) 842 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 843 return LT.first * Entry->Cost; 844 845 static const CostTblEntry SSE2CostTable[] = { 846 // We don't correctly identify costs of casts because they are marked as 847 // custom. 848 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 849 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 850 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 851 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 852 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 853 854 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 855 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 856 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 857 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 858 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 859 860 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 861 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 862 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 863 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 864 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split. 865 866 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence. 867 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 868 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 869 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 870 871 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 872 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 873 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 874 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 875 876 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 877 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 878 879 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 880 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 881 }; 882 883 if (ST->hasSSE2()) 884 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 885 return LT.first * Entry->Cost; 886 887 static const CostTblEntry SSE1CostTable[] = { 888 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 889 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 890 891 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 892 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 893 894 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 895 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 896 897 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 898 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 899 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 900 901 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 902 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 903 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 904 }; 905 906 if (ST->hasSSE1()) 907 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 908 return LT.first * Entry->Cost; 909 910 // It is not a good idea to vectorize division. We have to scalarize it and 911 // in the process we will often end up having to spilling regular 912 // registers. The overhead of division is going to dominate most kernels 913 // anyways so try hard to prevent vectorization of division - it is 914 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 915 // to hide "20 cycles" for each lane. 916 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 917 ISD == ISD::UDIV || ISD == ISD::UREM)) { 918 int ScalarCost = getArithmeticInstrCost( 919 Opcode, Ty->getScalarType(), Op1Info, Op2Info, 920 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 921 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 922 } 923 924 // Fallback to the default implementation. 925 return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info); 926 } 927 928 int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, VectorType *BaseTp, 929 int Index, VectorType *SubTp) { 930 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 931 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 932 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 933 934 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 935 if (Kind == TTI::SK_Transpose) 936 Kind = TTI::SK_PermuteTwoSrc; 937 938 // For Broadcasts we are splatting the first element from the first input 939 // register, so only need to reference that input and all the output 940 // registers are the same. 941 if (Kind == TTI::SK_Broadcast) 942 LT.first = 1; 943 944 // Subvector extractions are free if they start at the beginning of a 945 // vector and cheap if the subvectors are aligned. 946 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 947 int NumElts = LT.second.getVectorNumElements(); 948 if ((Index % NumElts) == 0) 949 return 0; 950 std::pair<int, MVT> SubLT = TLI->getTypeLegalizationCost(DL, SubTp); 951 if (SubLT.second.isVector()) { 952 int NumSubElts = SubLT.second.getVectorNumElements(); 953 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 954 return SubLT.first; 955 // Handle some cases for widening legalization. For now we only handle 956 // cases where the original subvector was naturally aligned and evenly 957 // fit in its legalized subvector type. 958 // FIXME: Remove some of the alignment restrictions. 959 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 960 // vectors. 961 int OrigSubElts = cast<VectorType>(SubTp)->getNumElements(); 962 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 963 (NumSubElts % OrigSubElts) == 0 && 964 LT.second.getVectorElementType() == 965 SubLT.second.getVectorElementType() && 966 LT.second.getVectorElementType().getSizeInBits() == 967 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 968 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 969 "Unexpected number of elements!"); 970 VectorType *VecTy = VectorType::get(BaseTp->getElementType(), 971 LT.second.getVectorNumElements()); 972 VectorType *SubTy = 973 VectorType::get(BaseTp->getElementType(), 974 SubLT.second.getVectorNumElements()); 975 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 976 int ExtractCost = getShuffleCost(TTI::SK_ExtractSubvector, VecTy, 977 ExtractIndex, SubTy); 978 979 // If the original size is 32-bits or more, we can use pshufd. Otherwise 980 // if we have SSSE3 we can use pshufb. 981 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 982 return ExtractCost + 1; // pshufd or pshufb 983 984 assert(SubTp->getPrimitiveSizeInBits() == 16 && 985 "Unexpected vector size"); 986 987 return ExtractCost + 2; // worst case pshufhw + pshufd 988 } 989 } 990 } 991 992 // Handle some common (illegal) sub-vector types as they are often very cheap 993 // to shuffle even on targets without PSHUFB. 994 EVT VT = TLI->getValueType(DL, BaseTp); 995 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 996 !ST->hasSSSE3()) { 997 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 998 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 999 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1000 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1001 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1002 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1003 1004 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1005 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1006 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1007 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1008 1009 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1010 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1011 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1012 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1013 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1014 1015 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1016 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1017 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1018 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1019 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1020 }; 1021 1022 if (ST->hasSSE2()) 1023 if (const auto *Entry = 1024 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1025 return Entry->Cost; 1026 } 1027 1028 // We are going to permute multiple sources and the result will be in multiple 1029 // destinations. Providing an accurate cost only for splits where the element 1030 // type remains the same. 1031 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1032 MVT LegalVT = LT.second; 1033 if (LegalVT.isVector() && 1034 LegalVT.getVectorElementType().getSizeInBits() == 1035 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1036 LegalVT.getVectorNumElements() < BaseTp->getNumElements()) { 1037 1038 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1039 unsigned LegalVTSize = LegalVT.getStoreSize(); 1040 // Number of source vectors after legalization: 1041 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1042 // Number of destination vectors after legalization: 1043 unsigned NumOfDests = LT.first; 1044 1045 VectorType *SingleOpTy = 1046 VectorType::get(BaseTp->getElementType(), 1047 LegalVT.getVectorNumElements()); 1048 1049 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1050 return NumOfShuffles * 1051 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 0, nullptr); 1052 } 1053 1054 return BaseT::getShuffleCost(Kind, BaseTp, Index, SubTp); 1055 } 1056 1057 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1058 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1059 // We assume that source and destination have the same vector type. 1060 int NumOfDests = LT.first; 1061 int NumOfShufflesPerDest = LT.first * 2 - 1; 1062 LT.first = NumOfDests * NumOfShufflesPerDest; 1063 } 1064 1065 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1066 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1067 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1068 1069 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1070 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1071 1072 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 1}, // vpermt2b 1073 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 1}, // vpermt2b 1074 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1} // vpermt2b 1075 }; 1076 1077 if (ST->hasVBMI()) 1078 if (const auto *Entry = 1079 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1080 return LT.first * Entry->Cost; 1081 1082 static const CostTblEntry AVX512BWShuffleTbl[] = { 1083 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1084 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1085 1086 {TTI::SK_Reverse, MVT::v32i16, 1}, // vpermw 1087 {TTI::SK_Reverse, MVT::v16i16, 1}, // vpermw 1088 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1089 1090 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 1}, // vpermw 1091 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 1}, // vpermw 1092 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // vpermw 1093 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1094 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 3}, // vpermw + zext/trunc 1095 1096 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 1}, // vpermt2w 1097 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 1}, // vpermt2w 1098 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpermt2w 1099 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 3}, // zext + vpermt2w + trunc 1100 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1101 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3} // zext + vpermt2w + trunc 1102 }; 1103 1104 if (ST->hasBWI()) 1105 if (const auto *Entry = 1106 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1107 return LT.first * Entry->Cost; 1108 1109 static const CostTblEntry AVX512ShuffleTbl[] = { 1110 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1111 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1112 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1113 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1114 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1115 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1116 1117 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1118 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1119 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1120 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1121 1122 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1123 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1124 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1125 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1126 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1127 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1128 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1129 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1130 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1131 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1132 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1133 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1134 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1135 1136 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1137 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1138 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1139 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1140 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1141 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1142 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1143 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1144 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1145 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1146 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1147 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1148 1149 // FIXME: This just applies the type legalization cost rules above 1150 // assuming these completely split. 1151 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1152 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1153 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1154 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1155 }; 1156 1157 if (ST->hasAVX512()) 1158 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1159 return LT.first * Entry->Cost; 1160 1161 static const CostTblEntry AVX2ShuffleTbl[] = { 1162 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1163 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1164 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1165 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1166 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1167 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1168 1169 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1170 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1171 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1172 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1173 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1174 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1175 1176 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1177 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1178 1179 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1180 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1181 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1182 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1183 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1184 // + vpblendvb 1185 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1186 // + vpblendvb 1187 1188 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1189 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1190 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1191 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1192 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1193 // + vpblendvb 1194 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1195 // + vpblendvb 1196 }; 1197 1198 if (ST->hasAVX2()) 1199 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1200 return LT.first * Entry->Cost; 1201 1202 static const CostTblEntry XOPShuffleTbl[] = { 1203 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1204 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1205 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1206 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1207 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1208 // + vinsertf128 1209 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1210 // + vinsertf128 1211 1212 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1213 // + vinsertf128 1214 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1215 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1216 // + vinsertf128 1217 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1218 }; 1219 1220 if (ST->hasXOP()) 1221 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1222 return LT.first * Entry->Cost; 1223 1224 static const CostTblEntry AVX1ShuffleTbl[] = { 1225 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1226 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1227 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1228 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1229 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1230 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1231 1232 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1233 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1234 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1235 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1236 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1237 // + vinsertf128 1238 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1239 // + vinsertf128 1240 1241 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1242 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1243 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1244 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1245 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1246 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1247 1248 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1249 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1250 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1251 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1252 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1253 // + 2*por + vinsertf128 1254 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1255 // + 2*por + vinsertf128 1256 1257 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1258 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1259 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1260 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1261 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1262 // + 4*por + vinsertf128 1263 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1264 // + 4*por + vinsertf128 1265 }; 1266 1267 if (ST->hasAVX()) 1268 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1269 return LT.first * Entry->Cost; 1270 1271 static const CostTblEntry SSE41ShuffleTbl[] = { 1272 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1273 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1274 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1275 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1276 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1277 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1278 }; 1279 1280 if (ST->hasSSE41()) 1281 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1282 return LT.first * Entry->Cost; 1283 1284 static const CostTblEntry SSSE3ShuffleTbl[] = { 1285 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1286 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1287 1288 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1289 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1290 1291 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1292 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1293 1294 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1295 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1296 1297 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1298 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1299 }; 1300 1301 if (ST->hasSSSE3()) 1302 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1303 return LT.first * Entry->Cost; 1304 1305 static const CostTblEntry SSE2ShuffleTbl[] = { 1306 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1307 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1308 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1309 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1310 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1311 1312 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1313 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1314 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1315 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1316 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1317 // + 2*pshufd + 2*unpck + packus 1318 1319 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1320 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1321 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1322 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1323 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1324 1325 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1326 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1327 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1328 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1329 // + pshufd/unpck 1330 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1331 // + 2*pshufd + 2*unpck + 2*packus 1332 1333 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1334 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1335 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1336 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1337 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1338 }; 1339 1340 if (ST->hasSSE2()) 1341 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1342 return LT.first * Entry->Cost; 1343 1344 static const CostTblEntry SSE1ShuffleTbl[] = { 1345 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1346 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1347 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1348 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1349 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1350 }; 1351 1352 if (ST->hasSSE1()) 1353 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1354 return LT.first * Entry->Cost; 1355 1356 return BaseT::getShuffleCost(Kind, BaseTp, Index, SubTp); 1357 } 1358 1359 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 1360 const Instruction *I) { 1361 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1362 assert(ISD && "Invalid opcode"); 1363 1364 // FIXME: Need a better design of the cost table to handle non-simple types of 1365 // potential massive combinations (elem_num x src_type x dst_type). 1366 1367 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1368 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1369 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1370 1371 // Mask sign extend has an instruction. 1372 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1373 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1374 1375 // Mask zero extend is a load + broadcast. 1376 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1377 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1378 1379 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 1 }, 1380 }; 1381 1382 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1383 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1384 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1385 1386 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1387 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1388 1389 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1390 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1391 1392 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1393 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1394 }; 1395 1396 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1397 // 256-bit wide vectors. 1398 1399 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1400 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1401 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1402 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1403 1404 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 }, 1405 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 }, 1406 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, 1407 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 }, 1408 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 1409 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 7 },// 2*vpmovqd+concat+vpmovdb 1410 1411 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 9 }, // FIXME 1412 1413 // v16i1 -> v16i32 - load + broadcast 1414 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1415 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1416 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1417 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1418 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1419 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1420 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1421 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1422 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1423 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1424 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1425 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1426 1427 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1428 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1429 1430 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1431 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1432 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1433 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1434 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1435 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1436 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1437 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1438 1439 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1440 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1441 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1442 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1443 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1444 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1445 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1446 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1447 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1448 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1449 1450 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1451 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 2 }, 1452 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 2 }, 1453 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1454 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 2 }, 1455 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 2 }, 1456 }; 1457 1458 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1459 // Mask sign extend has an instruction. 1460 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1461 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1462 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1463 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1464 1465 // Mask zero extend is a load + broadcast. 1466 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1467 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1468 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1469 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1470 }; 1471 1472 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1473 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1474 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1475 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1476 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1477 1478 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1479 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1480 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1481 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1482 1483 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1484 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1485 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1486 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1487 1488 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1489 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1490 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1491 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1492 }; 1493 1494 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 1495 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1496 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1497 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1498 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1499 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1500 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1501 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1502 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1503 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1504 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1505 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1506 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1507 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1508 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1509 1510 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 1511 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1512 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 1513 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 1514 1515 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1516 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1517 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1518 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1519 }; 1520 1521 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1522 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1523 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1524 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1525 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1526 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1527 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1528 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1529 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1530 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1531 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1532 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1533 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1534 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1535 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1536 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1537 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1538 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1539 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1540 1541 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 1542 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 1543 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1544 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 1545 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1546 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 }, 1547 1548 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1549 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1550 1551 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1552 }; 1553 1554 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1555 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1556 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1557 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1558 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1559 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1560 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1561 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1562 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1563 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1564 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1565 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 4 }, 1566 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1567 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1568 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1569 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1570 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1571 1572 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 1573 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1574 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1575 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1576 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 1577 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 }, 1578 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 11 }, 1579 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 9 }, 1580 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 }, 1581 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 11 }, 1582 1583 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1584 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1585 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1586 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1587 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1588 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1589 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1590 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1591 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1592 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1593 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1594 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1595 1596 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1597 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1598 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1599 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1600 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1601 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1602 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1603 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1604 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1605 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 }, 1606 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 1607 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1608 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 1609 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1610 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1611 // The generic code to compute the scalar overhead is currently broken. 1612 // Workaround this limitation by estimating the scalarization overhead 1613 // here. We have roughly 10 instructions per scalar element. 1614 // Multiply that by the vector width. 1615 // FIXME: remove that when PR19268 is fixed. 1616 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1617 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1618 1619 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 }, 1620 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 }, 1621 // This node is expanded into scalarized operations but BasicTTI is overly 1622 // optimistic estimating its cost. It computes 3 per element (one 1623 // vector-extract, one scalar conversion and one vector-insert). The 1624 // problem is that the inserts form a read-modify-write chain so latency 1625 // should be factored in too. Inflating the cost per element by 1. 1626 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, 1627 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 1628 1629 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 1630 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 1631 }; 1632 1633 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 1634 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1635 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1636 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1637 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1638 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1639 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1640 1641 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1642 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 }, 1643 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1644 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1645 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1646 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1647 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1648 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1649 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1650 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1651 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1652 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1653 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1654 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1655 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1656 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1657 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1658 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1659 1660 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, 1661 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 1662 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 1663 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 1664 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 1665 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 1666 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 1667 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 1 }, // PSHUFB 1668 1669 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 1670 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 1671 }; 1672 1673 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 1674 // These are somewhat magic numbers justified by looking at the output of 1675 // Intel's IACA, running some kernels and making sure when we take 1676 // legalization into account the throughput will be overestimated. 1677 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1678 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1679 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1680 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1681 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1682 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 2*10 }, 1683 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2*10 }, 1684 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1685 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 1686 1687 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1688 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1689 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1690 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1691 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1692 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, 1693 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 }, 1694 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1695 1696 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, 1697 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, 1698 1699 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 3 }, 1700 1701 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 6 }, 1702 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 }, 1703 1704 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 1705 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 1706 1707 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1708 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 1709 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 1710 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 1711 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1712 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 1713 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1714 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 1715 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1716 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1717 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1718 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1719 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 1720 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 1721 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1722 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 1723 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1724 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 1725 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1726 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1727 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 1728 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 1729 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1730 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 1731 1732 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // PAND+PACKUSWB 1733 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 4 }, 1734 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, 1735 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 1736 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 3 }, // PAND+3*PACKUSWB 1737 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 1738 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 1739 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 1740 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1741 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 1742 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1743 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 1744 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 1745 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 1746 { ISD::TRUNCATE, MVT::v2i32, MVT::v2i64, 1 }, // PSHUFD 1747 }; 1748 1749 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 1750 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst); 1751 1752 if (ST->hasSSE2() && !ST->hasAVX()) { 1753 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1754 LTDest.second, LTSrc.second)) 1755 return LTSrc.first * Entry->Cost; 1756 } 1757 1758 EVT SrcTy = TLI->getValueType(DL, Src); 1759 EVT DstTy = TLI->getValueType(DL, Dst); 1760 1761 // The function getSimpleVT only handles simple value types. 1762 if (!SrcTy.isSimple() || !DstTy.isSimple()) 1763 return BaseT::getCastInstrCost(Opcode, Dst, Src); 1764 1765 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 1766 MVT SimpleDstTy = DstTy.getSimpleVT(); 1767 1768 if (ST->useAVX512Regs()) { 1769 if (ST->hasBWI()) 1770 if (const auto *Entry = ConvertCostTableLookup(AVX512BWConversionTbl, ISD, 1771 SimpleDstTy, SimpleSrcTy)) 1772 return Entry->Cost; 1773 1774 if (ST->hasDQI()) 1775 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 1776 SimpleDstTy, SimpleSrcTy)) 1777 return Entry->Cost; 1778 1779 if (ST->hasAVX512()) 1780 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 1781 SimpleDstTy, SimpleSrcTy)) 1782 return Entry->Cost; 1783 } 1784 1785 if (ST->hasBWI()) 1786 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 1787 SimpleDstTy, SimpleSrcTy)) 1788 return Entry->Cost; 1789 1790 if (ST->hasDQI()) 1791 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 1792 SimpleDstTy, SimpleSrcTy)) 1793 return Entry->Cost; 1794 1795 if (ST->hasAVX512()) 1796 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 1797 SimpleDstTy, SimpleSrcTy)) 1798 return Entry->Cost; 1799 1800 if (ST->hasAVX2()) { 1801 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 1802 SimpleDstTy, SimpleSrcTy)) 1803 return Entry->Cost; 1804 } 1805 1806 if (ST->hasAVX()) { 1807 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 1808 SimpleDstTy, SimpleSrcTy)) 1809 return Entry->Cost; 1810 } 1811 1812 if (ST->hasSSE41()) { 1813 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 1814 SimpleDstTy, SimpleSrcTy)) 1815 return Entry->Cost; 1816 } 1817 1818 if (ST->hasSSE2()) { 1819 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1820 SimpleDstTy, SimpleSrcTy)) 1821 return Entry->Cost; 1822 } 1823 1824 return BaseT::getCastInstrCost(Opcode, Dst, Src, I); 1825 } 1826 1827 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 1828 const Instruction *I) { 1829 // Legalize the type. 1830 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 1831 1832 MVT MTy = LT.second; 1833 1834 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1835 assert(ISD && "Invalid opcode"); 1836 1837 unsigned ExtraCost = 0; 1838 if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) { 1839 // Some vector comparison predicates cost extra instructions. 1840 if (MTy.isVector() && 1841 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 1842 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 1843 ST->hasBWI())) { 1844 switch (cast<CmpInst>(I)->getPredicate()) { 1845 case CmpInst::Predicate::ICMP_NE: 1846 // xor(cmpeq(x,y),-1) 1847 ExtraCost = 1; 1848 break; 1849 case CmpInst::Predicate::ICMP_SGE: 1850 case CmpInst::Predicate::ICMP_SLE: 1851 // xor(cmpgt(x,y),-1) 1852 ExtraCost = 1; 1853 break; 1854 case CmpInst::Predicate::ICMP_ULT: 1855 case CmpInst::Predicate::ICMP_UGT: 1856 // cmpgt(xor(x,signbit),xor(y,signbit)) 1857 // xor(cmpeq(pmaxu(x,y),x),-1) 1858 ExtraCost = 2; 1859 break; 1860 case CmpInst::Predicate::ICMP_ULE: 1861 case CmpInst::Predicate::ICMP_UGE: 1862 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 1863 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 1864 // cmpeq(psubus(x,y),0) 1865 // cmpeq(pminu(x,y),x) 1866 ExtraCost = 1; 1867 } else { 1868 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 1869 ExtraCost = 3; 1870 } 1871 break; 1872 default: 1873 break; 1874 } 1875 } 1876 } 1877 1878 static const CostTblEntry SLMCostTbl[] = { 1879 // slm pcmpeq/pcmpgt throughput is 2 1880 { ISD::SETCC, MVT::v2i64, 2 }, 1881 }; 1882 1883 static const CostTblEntry AVX512BWCostTbl[] = { 1884 { ISD::SETCC, MVT::v32i16, 1 }, 1885 { ISD::SETCC, MVT::v64i8, 1 }, 1886 1887 { ISD::SELECT, MVT::v32i16, 1 }, 1888 { ISD::SELECT, MVT::v64i8, 1 }, 1889 }; 1890 1891 static const CostTblEntry AVX512CostTbl[] = { 1892 { ISD::SETCC, MVT::v8i64, 1 }, 1893 { ISD::SETCC, MVT::v16i32, 1 }, 1894 { ISD::SETCC, MVT::v8f64, 1 }, 1895 { ISD::SETCC, MVT::v16f32, 1 }, 1896 1897 { ISD::SELECT, MVT::v8i64, 1 }, 1898 { ISD::SELECT, MVT::v16i32, 1 }, 1899 { ISD::SELECT, MVT::v8f64, 1 }, 1900 { ISD::SELECT, MVT::v16f32, 1 }, 1901 1902 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 1903 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 1904 1905 { ISD::SELECT, MVT::v32i16, 2 }, // FIXME: should be 3 1906 { ISD::SELECT, MVT::v64i8, 2 }, // FIXME: should be 3 1907 }; 1908 1909 static const CostTblEntry AVX2CostTbl[] = { 1910 { ISD::SETCC, MVT::v4i64, 1 }, 1911 { ISD::SETCC, MVT::v8i32, 1 }, 1912 { ISD::SETCC, MVT::v16i16, 1 }, 1913 { ISD::SETCC, MVT::v32i8, 1 }, 1914 1915 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 1916 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 1917 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 1918 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 1919 }; 1920 1921 static const CostTblEntry AVX1CostTbl[] = { 1922 { ISD::SETCC, MVT::v4f64, 1 }, 1923 { ISD::SETCC, MVT::v8f32, 1 }, 1924 // AVX1 does not support 8-wide integer compare. 1925 { ISD::SETCC, MVT::v4i64, 4 }, 1926 { ISD::SETCC, MVT::v8i32, 4 }, 1927 { ISD::SETCC, MVT::v16i16, 4 }, 1928 { ISD::SETCC, MVT::v32i8, 4 }, 1929 1930 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 1931 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 1932 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 1933 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 1934 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 1935 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 1936 }; 1937 1938 static const CostTblEntry SSE42CostTbl[] = { 1939 { ISD::SETCC, MVT::v2f64, 1 }, 1940 { ISD::SETCC, MVT::v4f32, 1 }, 1941 { ISD::SETCC, MVT::v2i64, 1 }, 1942 }; 1943 1944 static const CostTblEntry SSE41CostTbl[] = { 1945 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 1946 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 1947 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 1948 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 1949 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 1950 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 1951 }; 1952 1953 static const CostTblEntry SSE2CostTbl[] = { 1954 { ISD::SETCC, MVT::v2f64, 2 }, 1955 { ISD::SETCC, MVT::f64, 1 }, 1956 { ISD::SETCC, MVT::v2i64, 8 }, 1957 { ISD::SETCC, MVT::v4i32, 1 }, 1958 { ISD::SETCC, MVT::v8i16, 1 }, 1959 { ISD::SETCC, MVT::v16i8, 1 }, 1960 1961 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 1962 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 1963 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 1964 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 1965 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 1966 }; 1967 1968 static const CostTblEntry SSE1CostTbl[] = { 1969 { ISD::SETCC, MVT::v4f32, 2 }, 1970 { ISD::SETCC, MVT::f32, 1 }, 1971 1972 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 1973 }; 1974 1975 if (ST->isSLM()) 1976 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 1977 return LT.first * (ExtraCost + Entry->Cost); 1978 1979 if (ST->hasBWI()) 1980 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 1981 return LT.first * (ExtraCost + Entry->Cost); 1982 1983 if (ST->hasAVX512()) 1984 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 1985 return LT.first * (ExtraCost + Entry->Cost); 1986 1987 if (ST->hasAVX2()) 1988 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 1989 return LT.first * (ExtraCost + Entry->Cost); 1990 1991 if (ST->hasAVX()) 1992 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 1993 return LT.first * (ExtraCost + Entry->Cost); 1994 1995 if (ST->hasSSE42()) 1996 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 1997 return LT.first * (ExtraCost + Entry->Cost); 1998 1999 if (ST->hasSSE41()) 2000 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2001 return LT.first * (ExtraCost + Entry->Cost); 2002 2003 if (ST->hasSSE2()) 2004 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2005 return LT.first * (ExtraCost + Entry->Cost); 2006 2007 if (ST->hasSSE1()) 2008 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2009 return LT.first * (ExtraCost + Entry->Cost); 2010 2011 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I); 2012 } 2013 2014 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2015 2016 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 2017 ArrayRef<Type *> Tys, FastMathFlags FMF, 2018 unsigned ScalarizationCostPassed, 2019 const Instruction *I) { 2020 // Costs should match the codegen from: 2021 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2022 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2023 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2024 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2025 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2026 static const CostTblEntry AVX512CDCostTbl[] = { 2027 { ISD::CTLZ, MVT::v8i64, 1 }, 2028 { ISD::CTLZ, MVT::v16i32, 1 }, 2029 { ISD::CTLZ, MVT::v32i16, 8 }, 2030 { ISD::CTLZ, MVT::v64i8, 20 }, 2031 { ISD::CTLZ, MVT::v4i64, 1 }, 2032 { ISD::CTLZ, MVT::v8i32, 1 }, 2033 { ISD::CTLZ, MVT::v16i16, 4 }, 2034 { ISD::CTLZ, MVT::v32i8, 10 }, 2035 { ISD::CTLZ, MVT::v2i64, 1 }, 2036 { ISD::CTLZ, MVT::v4i32, 1 }, 2037 { ISD::CTLZ, MVT::v8i16, 4 }, 2038 { ISD::CTLZ, MVT::v16i8, 4 }, 2039 }; 2040 static const CostTblEntry AVX512BWCostTbl[] = { 2041 { ISD::BITREVERSE, MVT::v8i64, 5 }, 2042 { ISD::BITREVERSE, MVT::v16i32, 5 }, 2043 { ISD::BITREVERSE, MVT::v32i16, 5 }, 2044 { ISD::BITREVERSE, MVT::v64i8, 5 }, 2045 { ISD::CTLZ, MVT::v8i64, 23 }, 2046 { ISD::CTLZ, MVT::v16i32, 22 }, 2047 { ISD::CTLZ, MVT::v32i16, 18 }, 2048 { ISD::CTLZ, MVT::v64i8, 17 }, 2049 { ISD::CTPOP, MVT::v8i64, 7 }, 2050 { ISD::CTPOP, MVT::v16i32, 11 }, 2051 { ISD::CTPOP, MVT::v32i16, 9 }, 2052 { ISD::CTPOP, MVT::v64i8, 6 }, 2053 { ISD::CTTZ, MVT::v8i64, 10 }, 2054 { ISD::CTTZ, MVT::v16i32, 14 }, 2055 { ISD::CTTZ, MVT::v32i16, 12 }, 2056 { ISD::CTTZ, MVT::v64i8, 9 }, 2057 { ISD::SADDSAT, MVT::v32i16, 1 }, 2058 { ISD::SADDSAT, MVT::v64i8, 1 }, 2059 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2060 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2061 { ISD::UADDSAT, MVT::v32i16, 1 }, 2062 { ISD::UADDSAT, MVT::v64i8, 1 }, 2063 { ISD::USUBSAT, MVT::v32i16, 1 }, 2064 { ISD::USUBSAT, MVT::v64i8, 1 }, 2065 }; 2066 static const CostTblEntry AVX512CostTbl[] = { 2067 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2068 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2069 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2070 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2071 { ISD::CTLZ, MVT::v8i64, 29 }, 2072 { ISD::CTLZ, MVT::v16i32, 35 }, 2073 { ISD::CTLZ, MVT::v32i16, 28 }, 2074 { ISD::CTLZ, MVT::v64i8, 18 }, 2075 { ISD::CTPOP, MVT::v8i64, 16 }, 2076 { ISD::CTPOP, MVT::v16i32, 24 }, 2077 { ISD::CTPOP, MVT::v32i16, 18 }, 2078 { ISD::CTPOP, MVT::v64i8, 12 }, 2079 { ISD::CTTZ, MVT::v8i64, 20 }, 2080 { ISD::CTTZ, MVT::v16i32, 28 }, 2081 { ISD::CTTZ, MVT::v32i16, 24 }, 2082 { ISD::CTTZ, MVT::v64i8, 18 }, 2083 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2084 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2085 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2086 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2087 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2088 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2089 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2090 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2091 { ISD::SADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2092 { ISD::SADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2093 { ISD::SSUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2094 { ISD::SSUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2095 { ISD::UADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2096 { ISD::UADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2097 { ISD::USUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2098 { ISD::USUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2099 { ISD::FMAXNUM, MVT::f32, 2 }, 2100 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2101 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2102 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2103 { ISD::FMAXNUM, MVT::f64, 2 }, 2104 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2105 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2106 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2107 }; 2108 static const CostTblEntry XOPCostTbl[] = { 2109 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2110 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2111 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2112 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2113 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2114 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2115 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2116 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2117 { ISD::BITREVERSE, MVT::i64, 3 }, 2118 { ISD::BITREVERSE, MVT::i32, 3 }, 2119 { ISD::BITREVERSE, MVT::i16, 3 }, 2120 { ISD::BITREVERSE, MVT::i8, 3 } 2121 }; 2122 static const CostTblEntry AVX2CostTbl[] = { 2123 { ISD::BITREVERSE, MVT::v4i64, 5 }, 2124 { ISD::BITREVERSE, MVT::v8i32, 5 }, 2125 { ISD::BITREVERSE, MVT::v16i16, 5 }, 2126 { ISD::BITREVERSE, MVT::v32i8, 5 }, 2127 { ISD::BSWAP, MVT::v4i64, 1 }, 2128 { ISD::BSWAP, MVT::v8i32, 1 }, 2129 { ISD::BSWAP, MVT::v16i16, 1 }, 2130 { ISD::CTLZ, MVT::v4i64, 23 }, 2131 { ISD::CTLZ, MVT::v8i32, 18 }, 2132 { ISD::CTLZ, MVT::v16i16, 14 }, 2133 { ISD::CTLZ, MVT::v32i8, 9 }, 2134 { ISD::CTPOP, MVT::v4i64, 7 }, 2135 { ISD::CTPOP, MVT::v8i32, 11 }, 2136 { ISD::CTPOP, MVT::v16i16, 9 }, 2137 { ISD::CTPOP, MVT::v32i8, 6 }, 2138 { ISD::CTTZ, MVT::v4i64, 10 }, 2139 { ISD::CTTZ, MVT::v8i32, 14 }, 2140 { ISD::CTTZ, MVT::v16i16, 12 }, 2141 { ISD::CTTZ, MVT::v32i8, 9 }, 2142 { ISD::SADDSAT, MVT::v16i16, 1 }, 2143 { ISD::SADDSAT, MVT::v32i8, 1 }, 2144 { ISD::SSUBSAT, MVT::v16i16, 1 }, 2145 { ISD::SSUBSAT, MVT::v32i8, 1 }, 2146 { ISD::UADDSAT, MVT::v16i16, 1 }, 2147 { ISD::UADDSAT, MVT::v32i8, 1 }, 2148 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 2149 { ISD::USUBSAT, MVT::v16i16, 1 }, 2150 { ISD::USUBSAT, MVT::v32i8, 1 }, 2151 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2152 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2153 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2154 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2155 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2156 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2157 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2158 }; 2159 static const CostTblEntry AVX1CostTbl[] = { 2160 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 2161 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 2162 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 2163 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 2164 { ISD::BSWAP, MVT::v4i64, 4 }, 2165 { ISD::BSWAP, MVT::v8i32, 4 }, 2166 { ISD::BSWAP, MVT::v16i16, 4 }, 2167 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 2168 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 2169 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 2170 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2171 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 2172 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 2173 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 2174 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 2175 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 2176 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 2177 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 2178 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2179 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2180 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2181 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2182 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2183 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2184 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2185 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 2186 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2187 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2188 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 2189 { ISD::FMAXNUM, MVT::f32, 3 }, 2190 { ISD::FMAXNUM, MVT::v4f32, 3 }, 2191 { ISD::FMAXNUM, MVT::v8f32, 5 }, 2192 { ISD::FMAXNUM, MVT::f64, 3 }, 2193 { ISD::FMAXNUM, MVT::v2f64, 3 }, 2194 { ISD::FMAXNUM, MVT::v4f64, 5 }, 2195 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 2196 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 2197 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 2198 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 2199 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 2200 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 2201 }; 2202 static const CostTblEntry GLMCostTbl[] = { 2203 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 2204 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 2205 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 2206 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 2207 }; 2208 static const CostTblEntry SLMCostTbl[] = { 2209 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 2210 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 2211 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 2212 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 2213 }; 2214 static const CostTblEntry SSE42CostTbl[] = { 2215 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 2216 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 2217 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 2218 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 2219 }; 2220 static const CostTblEntry SSSE3CostTbl[] = { 2221 { ISD::BITREVERSE, MVT::v2i64, 5 }, 2222 { ISD::BITREVERSE, MVT::v4i32, 5 }, 2223 { ISD::BITREVERSE, MVT::v8i16, 5 }, 2224 { ISD::BITREVERSE, MVT::v16i8, 5 }, 2225 { ISD::BSWAP, MVT::v2i64, 1 }, 2226 { ISD::BSWAP, MVT::v4i32, 1 }, 2227 { ISD::BSWAP, MVT::v8i16, 1 }, 2228 { ISD::CTLZ, MVT::v2i64, 23 }, 2229 { ISD::CTLZ, MVT::v4i32, 18 }, 2230 { ISD::CTLZ, MVT::v8i16, 14 }, 2231 { ISD::CTLZ, MVT::v16i8, 9 }, 2232 { ISD::CTPOP, MVT::v2i64, 7 }, 2233 { ISD::CTPOP, MVT::v4i32, 11 }, 2234 { ISD::CTPOP, MVT::v8i16, 9 }, 2235 { ISD::CTPOP, MVT::v16i8, 6 }, 2236 { ISD::CTTZ, MVT::v2i64, 10 }, 2237 { ISD::CTTZ, MVT::v4i32, 14 }, 2238 { ISD::CTTZ, MVT::v8i16, 12 }, 2239 { ISD::CTTZ, MVT::v16i8, 9 } 2240 }; 2241 static const CostTblEntry SSE2CostTbl[] = { 2242 { ISD::BITREVERSE, MVT::v2i64, 29 }, 2243 { ISD::BITREVERSE, MVT::v4i32, 27 }, 2244 { ISD::BITREVERSE, MVT::v8i16, 27 }, 2245 { ISD::BITREVERSE, MVT::v16i8, 20 }, 2246 { ISD::BSWAP, MVT::v2i64, 7 }, 2247 { ISD::BSWAP, MVT::v4i32, 7 }, 2248 { ISD::BSWAP, MVT::v8i16, 7 }, 2249 { ISD::CTLZ, MVT::v2i64, 25 }, 2250 { ISD::CTLZ, MVT::v4i32, 26 }, 2251 { ISD::CTLZ, MVT::v8i16, 20 }, 2252 { ISD::CTLZ, MVT::v16i8, 17 }, 2253 { ISD::CTPOP, MVT::v2i64, 12 }, 2254 { ISD::CTPOP, MVT::v4i32, 15 }, 2255 { ISD::CTPOP, MVT::v8i16, 13 }, 2256 { ISD::CTPOP, MVT::v16i8, 10 }, 2257 { ISD::CTTZ, MVT::v2i64, 14 }, 2258 { ISD::CTTZ, MVT::v4i32, 18 }, 2259 { ISD::CTTZ, MVT::v8i16, 16 }, 2260 { ISD::CTTZ, MVT::v16i8, 13 }, 2261 { ISD::SADDSAT, MVT::v8i16, 1 }, 2262 { ISD::SADDSAT, MVT::v16i8, 1 }, 2263 { ISD::SSUBSAT, MVT::v8i16, 1 }, 2264 { ISD::SSUBSAT, MVT::v16i8, 1 }, 2265 { ISD::UADDSAT, MVT::v8i16, 1 }, 2266 { ISD::UADDSAT, MVT::v16i8, 1 }, 2267 { ISD::USUBSAT, MVT::v8i16, 1 }, 2268 { ISD::USUBSAT, MVT::v16i8, 1 }, 2269 { ISD::FMAXNUM, MVT::f64, 4 }, 2270 { ISD::FMAXNUM, MVT::v2f64, 4 }, 2271 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 2272 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 2273 }; 2274 static const CostTblEntry SSE1CostTbl[] = { 2275 { ISD::FMAXNUM, MVT::f32, 4 }, 2276 { ISD::FMAXNUM, MVT::v4f32, 4 }, 2277 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 2278 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 2279 }; 2280 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 2281 { ISD::CTTZ, MVT::i64, 1 }, 2282 }; 2283 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 2284 { ISD::CTTZ, MVT::i32, 1 }, 2285 { ISD::CTTZ, MVT::i16, 1 }, 2286 { ISD::CTTZ, MVT::i8, 1 }, 2287 }; 2288 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 2289 { ISD::CTLZ, MVT::i64, 1 }, 2290 }; 2291 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 2292 { ISD::CTLZ, MVT::i32, 1 }, 2293 { ISD::CTLZ, MVT::i16, 1 }, 2294 { ISD::CTLZ, MVT::i8, 1 }, 2295 }; 2296 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 2297 { ISD::CTPOP, MVT::i64, 1 }, 2298 }; 2299 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 2300 { ISD::CTPOP, MVT::i32, 1 }, 2301 { ISD::CTPOP, MVT::i16, 1 }, 2302 { ISD::CTPOP, MVT::i8, 1 }, 2303 }; 2304 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2305 { ISD::BITREVERSE, MVT::i64, 14 }, 2306 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 2307 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 2308 { ISD::CTPOP, MVT::i64, 10 }, 2309 { ISD::SADDO, MVT::i64, 1 }, 2310 { ISD::UADDO, MVT::i64, 1 }, 2311 }; 2312 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2313 { ISD::BITREVERSE, MVT::i32, 14 }, 2314 { ISD::BITREVERSE, MVT::i16, 14 }, 2315 { ISD::BITREVERSE, MVT::i8, 11 }, 2316 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 2317 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 2318 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 2319 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 2320 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 2321 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 2322 { ISD::CTPOP, MVT::i32, 8 }, 2323 { ISD::CTPOP, MVT::i16, 9 }, 2324 { ISD::CTPOP, MVT::i8, 7 }, 2325 { ISD::SADDO, MVT::i32, 1 }, 2326 { ISD::SADDO, MVT::i16, 1 }, 2327 { ISD::SADDO, MVT::i8, 1 }, 2328 { ISD::UADDO, MVT::i32, 1 }, 2329 { ISD::UADDO, MVT::i16, 1 }, 2330 { ISD::UADDO, MVT::i8, 1 }, 2331 }; 2332 2333 Type *OpTy = RetTy; 2334 unsigned ISD = ISD::DELETED_NODE; 2335 switch (IID) { 2336 default: 2337 break; 2338 case Intrinsic::bitreverse: 2339 ISD = ISD::BITREVERSE; 2340 break; 2341 case Intrinsic::bswap: 2342 ISD = ISD::BSWAP; 2343 break; 2344 case Intrinsic::ctlz: 2345 ISD = ISD::CTLZ; 2346 break; 2347 case Intrinsic::ctpop: 2348 ISD = ISD::CTPOP; 2349 break; 2350 case Intrinsic::cttz: 2351 ISD = ISD::CTTZ; 2352 break; 2353 case Intrinsic::maxnum: 2354 case Intrinsic::minnum: 2355 // FMINNUM has same costs so don't duplicate. 2356 ISD = ISD::FMAXNUM; 2357 break; 2358 case Intrinsic::sadd_sat: 2359 ISD = ISD::SADDSAT; 2360 break; 2361 case Intrinsic::ssub_sat: 2362 ISD = ISD::SSUBSAT; 2363 break; 2364 case Intrinsic::uadd_sat: 2365 ISD = ISD::UADDSAT; 2366 break; 2367 case Intrinsic::usub_sat: 2368 ISD = ISD::USUBSAT; 2369 break; 2370 case Intrinsic::sqrt: 2371 ISD = ISD::FSQRT; 2372 break; 2373 case Intrinsic::sadd_with_overflow: 2374 case Intrinsic::ssub_with_overflow: 2375 // SSUBO has same costs so don't duplicate. 2376 ISD = ISD::SADDO; 2377 OpTy = RetTy->getContainedType(0); 2378 break; 2379 case Intrinsic::uadd_with_overflow: 2380 case Intrinsic::usub_with_overflow: 2381 // USUBO has same costs so don't duplicate. 2382 ISD = ISD::UADDO; 2383 OpTy = RetTy->getContainedType(0); 2384 break; 2385 } 2386 2387 if (ISD != ISD::DELETED_NODE) { 2388 // Legalize the type. 2389 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 2390 MVT MTy = LT.second; 2391 2392 // Attempt to lookup cost. 2393 if (ST->useGLMDivSqrtCosts()) 2394 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 2395 return LT.first * Entry->Cost; 2396 2397 if (ST->isSLM()) 2398 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2399 return LT.first * Entry->Cost; 2400 2401 if (ST->hasCDI()) 2402 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 2403 return LT.first * Entry->Cost; 2404 2405 if (ST->hasBWI()) 2406 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2407 return LT.first * Entry->Cost; 2408 2409 if (ST->hasAVX512()) 2410 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2411 return LT.first * Entry->Cost; 2412 2413 if (ST->hasXOP()) 2414 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2415 return LT.first * Entry->Cost; 2416 2417 if (ST->hasAVX2()) 2418 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2419 return LT.first * Entry->Cost; 2420 2421 if (ST->hasAVX()) 2422 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2423 return LT.first * Entry->Cost; 2424 2425 if (ST->hasSSE42()) 2426 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2427 return LT.first * Entry->Cost; 2428 2429 if (ST->hasSSSE3()) 2430 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 2431 return LT.first * Entry->Cost; 2432 2433 if (ST->hasSSE2()) 2434 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2435 return LT.first * Entry->Cost; 2436 2437 if (ST->hasSSE1()) 2438 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2439 return LT.first * Entry->Cost; 2440 2441 if (ST->hasBMI()) { 2442 if (ST->is64Bit()) 2443 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 2444 return LT.first * Entry->Cost; 2445 2446 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 2447 return LT.first * Entry->Cost; 2448 } 2449 2450 if (ST->hasLZCNT()) { 2451 if (ST->is64Bit()) 2452 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 2453 return LT.first * Entry->Cost; 2454 2455 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 2456 return LT.first * Entry->Cost; 2457 } 2458 2459 if (ST->hasPOPCNT()) { 2460 if (ST->is64Bit()) 2461 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 2462 return LT.first * Entry->Cost; 2463 2464 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 2465 return LT.first * Entry->Cost; 2466 } 2467 2468 // TODO - add BMI (TZCNT) scalar handling 2469 2470 if (ST->is64Bit()) 2471 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2472 return LT.first * Entry->Cost; 2473 2474 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2475 return LT.first * Entry->Cost; 2476 } 2477 2478 return BaseT::getIntrinsicInstrCost(IID, RetTy, Tys, FMF, 2479 ScalarizationCostPassed, I); 2480 } 2481 2482 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 2483 ArrayRef<Value *> Args, FastMathFlags FMF, 2484 unsigned VF, const Instruction *I) { 2485 static const CostTblEntry AVX512CostTbl[] = { 2486 { ISD::ROTL, MVT::v8i64, 1 }, 2487 { ISD::ROTL, MVT::v4i64, 1 }, 2488 { ISD::ROTL, MVT::v2i64, 1 }, 2489 { ISD::ROTL, MVT::v16i32, 1 }, 2490 { ISD::ROTL, MVT::v8i32, 1 }, 2491 { ISD::ROTL, MVT::v4i32, 1 }, 2492 { ISD::ROTR, MVT::v8i64, 1 }, 2493 { ISD::ROTR, MVT::v4i64, 1 }, 2494 { ISD::ROTR, MVT::v2i64, 1 }, 2495 { ISD::ROTR, MVT::v16i32, 1 }, 2496 { ISD::ROTR, MVT::v8i32, 1 }, 2497 { ISD::ROTR, MVT::v4i32, 1 } 2498 }; 2499 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 2500 static const CostTblEntry XOPCostTbl[] = { 2501 { ISD::ROTL, MVT::v4i64, 4 }, 2502 { ISD::ROTL, MVT::v8i32, 4 }, 2503 { ISD::ROTL, MVT::v16i16, 4 }, 2504 { ISD::ROTL, MVT::v32i8, 4 }, 2505 { ISD::ROTL, MVT::v2i64, 1 }, 2506 { ISD::ROTL, MVT::v4i32, 1 }, 2507 { ISD::ROTL, MVT::v8i16, 1 }, 2508 { ISD::ROTL, MVT::v16i8, 1 }, 2509 { ISD::ROTR, MVT::v4i64, 6 }, 2510 { ISD::ROTR, MVT::v8i32, 6 }, 2511 { ISD::ROTR, MVT::v16i16, 6 }, 2512 { ISD::ROTR, MVT::v32i8, 6 }, 2513 { ISD::ROTR, MVT::v2i64, 2 }, 2514 { ISD::ROTR, MVT::v4i32, 2 }, 2515 { ISD::ROTR, MVT::v8i16, 2 }, 2516 { ISD::ROTR, MVT::v16i8, 2 } 2517 }; 2518 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2519 { ISD::ROTL, MVT::i64, 1 }, 2520 { ISD::ROTR, MVT::i64, 1 }, 2521 { ISD::FSHL, MVT::i64, 4 } 2522 }; 2523 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2524 { ISD::ROTL, MVT::i32, 1 }, 2525 { ISD::ROTL, MVT::i16, 1 }, 2526 { ISD::ROTL, MVT::i8, 1 }, 2527 { ISD::ROTR, MVT::i32, 1 }, 2528 { ISD::ROTR, MVT::i16, 1 }, 2529 { ISD::ROTR, MVT::i8, 1 }, 2530 { ISD::FSHL, MVT::i32, 4 }, 2531 { ISD::FSHL, MVT::i16, 4 }, 2532 { ISD::FSHL, MVT::i8, 4 } 2533 }; 2534 2535 unsigned ISD = ISD::DELETED_NODE; 2536 switch (IID) { 2537 default: 2538 break; 2539 case Intrinsic::fshl: 2540 ISD = ISD::FSHL; 2541 if (Args[0] == Args[1]) 2542 ISD = ISD::ROTL; 2543 break; 2544 case Intrinsic::fshr: 2545 // FSHR has same costs so don't duplicate. 2546 ISD = ISD::FSHL; 2547 if (Args[0] == Args[1]) 2548 ISD = ISD::ROTR; 2549 break; 2550 } 2551 2552 if (ISD != ISD::DELETED_NODE) { 2553 // Legalize the type. 2554 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 2555 MVT MTy = LT.second; 2556 2557 // Attempt to lookup cost. 2558 if (ST->hasAVX512()) 2559 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2560 return LT.first * Entry->Cost; 2561 2562 if (ST->hasXOP()) 2563 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2564 return LT.first * Entry->Cost; 2565 2566 if (ST->is64Bit()) 2567 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2568 return LT.first * Entry->Cost; 2569 2570 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2571 return LT.first * Entry->Cost; 2572 } 2573 2574 return BaseT::getIntrinsicInstrCost(IID, RetTy, Args, FMF, VF, I); 2575 } 2576 2577 int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { 2578 static const CostTblEntry SLMCostTbl[] = { 2579 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 2580 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 2581 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 2582 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 2583 }; 2584 2585 assert(Val->isVectorTy() && "This must be a vector type"); 2586 Type *ScalarType = Val->getScalarType(); 2587 int RegisterFileMoveCost = 0; 2588 2589 if (Index != -1U && (Opcode == Instruction::ExtractElement || 2590 Opcode == Instruction::InsertElement)) { 2591 // Legalize the type. 2592 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 2593 2594 // This type is legalized to a scalar type. 2595 if (!LT.second.isVector()) 2596 return 0; 2597 2598 // The type may be split. Normalize the index to the new type. 2599 unsigned NumElts = LT.second.getVectorNumElements(); 2600 unsigned SubNumElts = NumElts; 2601 Index = Index % NumElts; 2602 2603 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 2604 // For inserts, we also need to insert the subvector back. 2605 if (LT.second.getSizeInBits() > 128) { 2606 assert((LT.second.getSizeInBits() % 128) == 0 && "Illegal vector"); 2607 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 2608 SubNumElts = NumElts / NumSubVecs; 2609 if (SubNumElts <= Index) { 2610 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 2611 Index %= SubNumElts; 2612 } 2613 } 2614 2615 if (Index == 0) { 2616 // Floating point scalars are already located in index #0. 2617 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 2618 // true for all. 2619 if (ScalarType->isFloatingPointTy()) 2620 return RegisterFileMoveCost; 2621 2622 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 2623 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 2624 return 1 + RegisterFileMoveCost; 2625 } 2626 2627 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2628 assert(ISD && "Unexpected vector opcode"); 2629 MVT MScalarTy = LT.second.getScalarType(); 2630 if (ST->isSLM()) 2631 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 2632 return Entry->Cost + RegisterFileMoveCost; 2633 2634 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 2635 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 2636 (MScalarTy.isInteger() && ST->hasSSE41())) 2637 return 1 + RegisterFileMoveCost; 2638 2639 // Assume insertps is relatively cheap on all targets. 2640 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 2641 Opcode == Instruction::InsertElement) 2642 return 1 + RegisterFileMoveCost; 2643 2644 // For extractions we just need to shuffle the element to index 0, which 2645 // should be very cheap (assume cost = 1). For insertions we need to shuffle 2646 // the elements to its destination. In both cases we must handle the 2647 // subvector move(s). 2648 // If the vector type is already less than 128-bits then don't reduce it. 2649 // TODO: Under what circumstances should we shuffle using the full width? 2650 int ShuffleCost = 1; 2651 if (Opcode == Instruction::InsertElement) { 2652 auto *SubTy = cast<VectorType>(Val); 2653 EVT VT = TLI->getValueType(DL, Val); 2654 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 2655 SubTy = VectorType::get(ScalarType, SubNumElts); 2656 ShuffleCost = getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, 0, SubTy); 2657 } 2658 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 2659 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 2660 } 2661 2662 // Add to the base cost if we know that the extracted element of a vector is 2663 // destined to be moved to and used in the integer register file. 2664 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 2665 RegisterFileMoveCost += 1; 2666 2667 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 2668 } 2669 2670 unsigned X86TTIImpl::getScalarizationOverhead(Type *Ty, bool Insert, 2671 bool Extract) { 2672 return BaseT::getScalarizationOverhead(Ty, Insert, Extract); 2673 } 2674 2675 int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 2676 MaybeAlign Alignment, unsigned AddressSpace, 2677 const Instruction *I) { 2678 // Handle non-power-of-two vectors such as <3 x float> 2679 if (VectorType *VTy = dyn_cast<VectorType>(Src)) { 2680 unsigned NumElem = VTy->getNumElements(); 2681 2682 // Handle a few common cases: 2683 // <3 x float> 2684 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 2685 // Cost = 64 bit store + extract + 32 bit store. 2686 return 3; 2687 2688 // <3 x double> 2689 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 2690 // Cost = 128 bit store + unpack + 64 bit store. 2691 return 3; 2692 2693 // Assume that all other non-power-of-two numbers are scalarized. 2694 if (!isPowerOf2_32(NumElem)) { 2695 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment, 2696 AddressSpace); 2697 int SplitCost = getScalarizationOverhead(Src, Opcode == Instruction::Load, 2698 Opcode == Instruction::Store); 2699 return NumElem * Cost + SplitCost; 2700 } 2701 } 2702 2703 // Legalize the type. 2704 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 2705 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 2706 "Invalid Opcode"); 2707 2708 // Each load/store unit costs 1. 2709 int Cost = LT.first * 1; 2710 2711 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a 2712 // proxy for a double-pumped AVX memory interface such as on Sandybridge. 2713 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow()) 2714 Cost *= 2; 2715 2716 return Cost; 2717 } 2718 2719 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, 2720 unsigned Alignment, 2721 unsigned AddressSpace) { 2722 bool IsLoad = (Instruction::Load == Opcode); 2723 bool IsStore = (Instruction::Store == Opcode); 2724 2725 VectorType *SrcVTy = dyn_cast<VectorType>(SrcTy); 2726 if (!SrcVTy) 2727 // To calculate scalar take the regular cost, without mask 2728 return getMemoryOpCost(Opcode, SrcTy, MaybeAlign(Alignment), AddressSpace); 2729 2730 unsigned NumElem = SrcVTy->getNumElements(); 2731 VectorType *MaskTy = 2732 VectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 2733 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, MaybeAlign(Alignment))) || 2734 (IsStore && !isLegalMaskedStore(SrcVTy, MaybeAlign(Alignment))) || 2735 !isPowerOf2_32(NumElem)) { 2736 // Scalarization 2737 int MaskSplitCost = getScalarizationOverhead(MaskTy, false, true); 2738 int ScalarCompareCost = getCmpSelInstrCost( 2739 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr); 2740 int BranchCost = getCFInstrCost(Instruction::Br); 2741 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 2742 2743 int ValueSplitCost = getScalarizationOverhead(SrcVTy, IsLoad, IsStore); 2744 int MemopCost = 2745 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2746 MaybeAlign(Alignment), AddressSpace); 2747 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 2748 } 2749 2750 // Legalize the type. 2751 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 2752 auto VT = TLI->getValueType(DL, SrcVTy); 2753 int Cost = 0; 2754 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 2755 LT.second.getVectorNumElements() == NumElem) 2756 // Promotion requires expand/truncate for data and a shuffle for mask. 2757 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, 0, nullptr) + 2758 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, 0, nullptr); 2759 2760 else if (LT.second.getVectorNumElements() > NumElem) { 2761 VectorType *NewMaskTy = VectorType::get(MaskTy->getElementType(), 2762 LT.second.getVectorNumElements()); 2763 // Expanding requires fill mask with zeroes 2764 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, 0, MaskTy); 2765 } 2766 2767 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 2768 if (!ST->hasAVX512()) 2769 return Cost + LT.first * (IsLoad ? 2 : 8); 2770 2771 // AVX-512 masked load/store is cheapper 2772 return Cost + LT.first; 2773 } 2774 2775 int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE, 2776 const SCEV *Ptr) { 2777 // Address computations in vectorized code with non-consecutive addresses will 2778 // likely result in more instructions compared to scalar code where the 2779 // computation can more often be merged into the index mode. The resulting 2780 // extra micro-ops can significantly decrease throughput. 2781 const unsigned NumVectorInstToHideOverhead = 10; 2782 2783 // Cost modeling of Strided Access Computation is hidden by the indexing 2784 // modes of X86 regardless of the stride value. We dont believe that there 2785 // is a difference between constant strided access in gerenal and constant 2786 // strided value which is less than or equal to 64. 2787 // Even in the case of (loop invariant) stride whose value is not known at 2788 // compile time, the address computation will not incur more than one extra 2789 // ADD instruction. 2790 if (Ty->isVectorTy() && SE) { 2791 if (!BaseT::isStridedAccess(Ptr)) 2792 return NumVectorInstToHideOverhead; 2793 if (!BaseT::getConstantStrideStep(SE, Ptr)) 2794 return 1; 2795 } 2796 2797 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 2798 } 2799 2800 int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 2801 bool IsPairwise) { 2802 // Just use the default implementation for pair reductions. 2803 if (IsPairwise) 2804 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise); 2805 2806 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 2807 // and make it as the cost. 2808 2809 static const CostTblEntry SLMCostTblNoPairWise[] = { 2810 { ISD::FADD, MVT::v2f64, 3 }, 2811 { ISD::ADD, MVT::v2i64, 5 }, 2812 }; 2813 2814 static const CostTblEntry SSE2CostTblNoPairWise[] = { 2815 { ISD::FADD, MVT::v2f64, 2 }, 2816 { ISD::FADD, MVT::v4f32, 4 }, 2817 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 2818 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 2819 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 2820 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 2821 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 2822 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 2823 { ISD::ADD, MVT::v2i8, 2 }, 2824 { ISD::ADD, MVT::v4i8, 2 }, 2825 { ISD::ADD, MVT::v8i8, 2 }, 2826 { ISD::ADD, MVT::v16i8, 3 }, 2827 }; 2828 2829 static const CostTblEntry AVX1CostTblNoPairWise[] = { 2830 { ISD::FADD, MVT::v4f64, 3 }, 2831 { ISD::FADD, MVT::v4f32, 3 }, 2832 { ISD::FADD, MVT::v8f32, 4 }, 2833 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 2834 { ISD::ADD, MVT::v4i64, 3 }, 2835 { ISD::ADD, MVT::v8i32, 5 }, 2836 { ISD::ADD, MVT::v16i16, 5 }, 2837 { ISD::ADD, MVT::v32i8, 4 }, 2838 }; 2839 2840 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2841 assert(ISD && "Invalid opcode"); 2842 2843 // Before legalizing the type, give a chance to look up illegal narrow types 2844 // in the table. 2845 // FIXME: Is there a better way to do this? 2846 EVT VT = TLI->getValueType(DL, ValTy); 2847 if (VT.isSimple()) { 2848 MVT MTy = VT.getSimpleVT(); 2849 if (ST->isSLM()) 2850 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 2851 return Entry->Cost; 2852 2853 if (ST->hasAVX()) 2854 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 2855 return Entry->Cost; 2856 2857 if (ST->hasSSE2()) 2858 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 2859 return Entry->Cost; 2860 } 2861 2862 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2863 2864 MVT MTy = LT.second; 2865 2866 auto *ValVTy = cast<VectorType>(ValTy); 2867 2868 unsigned ArithmeticCost = 0; 2869 if (LT.first != 1 && MTy.isVector() && 2870 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 2871 // Type needs to be split. We need LT.first - 1 arithmetic ops. 2872 VectorType *SingleOpTy = 2873 VectorType::get(ValVTy->getElementType(), MTy.getVectorNumElements()); 2874 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy); 2875 ArithmeticCost *= LT.first - 1; 2876 } 2877 2878 if (ST->isSLM()) 2879 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 2880 return ArithmeticCost + Entry->Cost; 2881 2882 if (ST->hasAVX()) 2883 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 2884 return ArithmeticCost + Entry->Cost; 2885 2886 if (ST->hasSSE2()) 2887 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 2888 return ArithmeticCost + Entry->Cost; 2889 2890 // FIXME: These assume a naive kshift+binop lowering, which is probably 2891 // conservative in most cases. 2892 static const CostTblEntry AVX512BoolReduction[] = { 2893 { ISD::AND, MVT::v2i1, 3 }, 2894 { ISD::AND, MVT::v4i1, 5 }, 2895 { ISD::AND, MVT::v8i1, 7 }, 2896 { ISD::AND, MVT::v16i1, 9 }, 2897 { ISD::AND, MVT::v32i1, 11 }, 2898 { ISD::AND, MVT::v64i1, 13 }, 2899 { ISD::OR, MVT::v2i1, 3 }, 2900 { ISD::OR, MVT::v4i1, 5 }, 2901 { ISD::OR, MVT::v8i1, 7 }, 2902 { ISD::OR, MVT::v16i1, 9 }, 2903 { ISD::OR, MVT::v32i1, 11 }, 2904 { ISD::OR, MVT::v64i1, 13 }, 2905 }; 2906 2907 static const CostTblEntry AVX2BoolReduction[] = { 2908 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 2909 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 2910 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 2911 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 2912 }; 2913 2914 static const CostTblEntry AVX1BoolReduction[] = { 2915 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 2916 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 2917 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 2918 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 2919 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 2920 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 2921 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 2922 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 2923 }; 2924 2925 static const CostTblEntry SSE2BoolReduction[] = { 2926 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 2927 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 2928 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 2929 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 2930 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 2931 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 2932 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 2933 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 2934 }; 2935 2936 // Handle bool allof/anyof patterns. 2937 if (ValVTy->getElementType()->isIntegerTy(1)) { 2938 unsigned ArithmeticCost = 0; 2939 if (LT.first != 1 && MTy.isVector() && 2940 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 2941 // Type needs to be split. We need LT.first - 1 arithmetic ops. 2942 Type *SingleOpTy = 2943 VectorType::get(ValVTy->getElementType(), MTy.getVectorNumElements()); 2944 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy); 2945 ArithmeticCost *= LT.first - 1; 2946 } 2947 2948 if (ST->hasAVX512()) 2949 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 2950 return ArithmeticCost + Entry->Cost; 2951 if (ST->hasAVX2()) 2952 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 2953 return ArithmeticCost + Entry->Cost; 2954 if (ST->hasAVX()) 2955 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 2956 return ArithmeticCost + Entry->Cost; 2957 if (ST->hasSSE2()) 2958 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 2959 return ArithmeticCost + Entry->Cost; 2960 2961 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise); 2962 } 2963 2964 unsigned NumVecElts = ValVTy->getNumElements(); 2965 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 2966 2967 // Special case power of 2 reductions where the scalar type isn't changed 2968 // by type legalization. 2969 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 2970 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise); 2971 2972 unsigned ReductionCost = 0; 2973 2974 auto *Ty = ValVTy; 2975 if (LT.first != 1 && MTy.isVector() && 2976 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 2977 // Type needs to be split. We need LT.first - 1 arithmetic ops. 2978 Ty = VectorType::get(ValVTy->getElementType(), MTy.getVectorNumElements()); 2979 ReductionCost = getArithmeticInstrCost(Opcode, Ty); 2980 ReductionCost *= LT.first - 1; 2981 NumVecElts = MTy.getVectorNumElements(); 2982 } 2983 2984 // Now handle reduction with the legal type, taking into account size changes 2985 // at each level. 2986 while (NumVecElts > 1) { 2987 // Determine the size of the remaining vector we need to reduce. 2988 unsigned Size = NumVecElts * ScalarSize; 2989 NumVecElts /= 2; 2990 // If we're reducing from 256/512 bits, use an extract_subvector. 2991 if (Size > 128) { 2992 auto *SubTy = VectorType::get(ValVTy->getElementType(), NumVecElts); 2993 ReductionCost += 2994 getShuffleCost(TTI::SK_ExtractSubvector, Ty, NumVecElts, SubTy); 2995 Ty = SubTy; 2996 } else if (Size == 128) { 2997 // Reducing from 128 bits is a permute of v2f64/v2i64. 2998 VectorType *ShufTy; 2999 if (ValVTy->isFloatingPointTy()) 3000 ShufTy = VectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 3001 else 3002 ShufTy = VectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 3003 ReductionCost += 3004 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3005 } else if (Size == 64) { 3006 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3007 VectorType *ShufTy; 3008 if (ValVTy->isFloatingPointTy()) 3009 ShufTy = VectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 3010 else 3011 ShufTy = VectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 3012 ReductionCost += 3013 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3014 } else { 3015 // Reducing from smaller size is a shift by immediate. 3016 auto *ShiftTy = VectorType::get( 3017 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 3018 ReductionCost += getArithmeticInstrCost( 3019 Instruction::LShr, ShiftTy, TargetTransformInfo::OK_AnyValue, 3020 TargetTransformInfo::OK_UniformConstantValue, 3021 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3022 } 3023 3024 // Add the arithmetic op for this level. 3025 ReductionCost += getArithmeticInstrCost(Opcode, Ty); 3026 } 3027 3028 // Add the final extract element to the cost. 3029 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3030 } 3031 3032 int X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, bool IsUnsigned) { 3033 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3034 3035 MVT MTy = LT.second; 3036 3037 int ISD; 3038 if (Ty->isIntOrIntVectorTy()) { 3039 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3040 } else { 3041 assert(Ty->isFPOrFPVectorTy() && 3042 "Expected float point or integer vector type."); 3043 ISD = ISD::FMINNUM; 3044 } 3045 3046 static const CostTblEntry SSE1CostTbl[] = { 3047 {ISD::FMINNUM, MVT::v4f32, 1}, 3048 }; 3049 3050 static const CostTblEntry SSE2CostTbl[] = { 3051 {ISD::FMINNUM, MVT::v2f64, 1}, 3052 {ISD::SMIN, MVT::v8i16, 1}, 3053 {ISD::UMIN, MVT::v16i8, 1}, 3054 }; 3055 3056 static const CostTblEntry SSE41CostTbl[] = { 3057 {ISD::SMIN, MVT::v4i32, 1}, 3058 {ISD::UMIN, MVT::v4i32, 1}, 3059 {ISD::UMIN, MVT::v8i16, 1}, 3060 {ISD::SMIN, MVT::v16i8, 1}, 3061 }; 3062 3063 static const CostTblEntry SSE42CostTbl[] = { 3064 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 3065 }; 3066 3067 static const CostTblEntry AVX1CostTbl[] = { 3068 {ISD::FMINNUM, MVT::v8f32, 1}, 3069 {ISD::FMINNUM, MVT::v4f64, 1}, 3070 {ISD::SMIN, MVT::v8i32, 3}, 3071 {ISD::UMIN, MVT::v8i32, 3}, 3072 {ISD::SMIN, MVT::v16i16, 3}, 3073 {ISD::UMIN, MVT::v16i16, 3}, 3074 {ISD::SMIN, MVT::v32i8, 3}, 3075 {ISD::UMIN, MVT::v32i8, 3}, 3076 }; 3077 3078 static const CostTblEntry AVX2CostTbl[] = { 3079 {ISD::SMIN, MVT::v8i32, 1}, 3080 {ISD::UMIN, MVT::v8i32, 1}, 3081 {ISD::SMIN, MVT::v16i16, 1}, 3082 {ISD::UMIN, MVT::v16i16, 1}, 3083 {ISD::SMIN, MVT::v32i8, 1}, 3084 {ISD::UMIN, MVT::v32i8, 1}, 3085 }; 3086 3087 static const CostTblEntry AVX512CostTbl[] = { 3088 {ISD::FMINNUM, MVT::v16f32, 1}, 3089 {ISD::FMINNUM, MVT::v8f64, 1}, 3090 {ISD::SMIN, MVT::v2i64, 1}, 3091 {ISD::UMIN, MVT::v2i64, 1}, 3092 {ISD::SMIN, MVT::v4i64, 1}, 3093 {ISD::UMIN, MVT::v4i64, 1}, 3094 {ISD::SMIN, MVT::v8i64, 1}, 3095 {ISD::UMIN, MVT::v8i64, 1}, 3096 {ISD::SMIN, MVT::v16i32, 1}, 3097 {ISD::UMIN, MVT::v16i32, 1}, 3098 }; 3099 3100 static const CostTblEntry AVX512BWCostTbl[] = { 3101 {ISD::SMIN, MVT::v32i16, 1}, 3102 {ISD::UMIN, MVT::v32i16, 1}, 3103 {ISD::SMIN, MVT::v64i8, 1}, 3104 {ISD::UMIN, MVT::v64i8, 1}, 3105 }; 3106 3107 // If we have a native MIN/MAX instruction for this type, use it. 3108 if (ST->hasBWI()) 3109 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3110 return LT.first * Entry->Cost; 3111 3112 if (ST->hasAVX512()) 3113 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3114 return LT.first * Entry->Cost; 3115 3116 if (ST->hasAVX2()) 3117 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3118 return LT.first * Entry->Cost; 3119 3120 if (ST->hasAVX()) 3121 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3122 return LT.first * Entry->Cost; 3123 3124 if (ST->hasSSE42()) 3125 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3126 return LT.first * Entry->Cost; 3127 3128 if (ST->hasSSE41()) 3129 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3130 return LT.first * Entry->Cost; 3131 3132 if (ST->hasSSE2()) 3133 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3134 return LT.first * Entry->Cost; 3135 3136 if (ST->hasSSE1()) 3137 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3138 return LT.first * Entry->Cost; 3139 3140 unsigned CmpOpcode; 3141 if (Ty->isFPOrFPVectorTy()) { 3142 CmpOpcode = Instruction::FCmp; 3143 } else { 3144 assert(Ty->isIntOrIntVectorTy() && 3145 "expecting floating point or integer type for min/max reduction"); 3146 CmpOpcode = Instruction::ICmp; 3147 } 3148 3149 // Otherwise fall back to cmp+select. 3150 return getCmpSelInstrCost(CmpOpcode, Ty, CondTy, nullptr) + 3151 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, nullptr); 3152 } 3153 3154 int X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 3155 bool IsPairwise, bool IsUnsigned) { 3156 // Just use the default implementation for pair reductions. 3157 if (IsPairwise) 3158 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned); 3159 3160 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3161 3162 MVT MTy = LT.second; 3163 3164 int ISD; 3165 if (ValTy->isIntOrIntVectorTy()) { 3166 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3167 } else { 3168 assert(ValTy->isFPOrFPVectorTy() && 3169 "Expected float point or integer vector type."); 3170 ISD = ISD::FMINNUM; 3171 } 3172 3173 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3174 // and make it as the cost. 3175 3176 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3177 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 3178 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 3179 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 3180 }; 3181 3182 static const CostTblEntry SSE41CostTblNoPairWise[] = { 3183 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 3184 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 3185 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 3186 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 3187 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 3188 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 3189 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 3190 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 3191 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 3192 {ISD::SMIN, MVT::v16i8, 6}, 3193 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 3194 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 3195 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 3196 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 3197 }; 3198 3199 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3200 {ISD::SMIN, MVT::v16i16, 6}, 3201 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 3202 {ISD::SMIN, MVT::v32i8, 8}, 3203 {ISD::UMIN, MVT::v32i8, 8}, 3204 }; 3205 3206 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 3207 {ISD::SMIN, MVT::v32i16, 8}, 3208 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 3209 {ISD::SMIN, MVT::v64i8, 10}, 3210 {ISD::UMIN, MVT::v64i8, 10}, 3211 }; 3212 3213 // Before legalizing the type, give a chance to look up illegal narrow types 3214 // in the table. 3215 // FIXME: Is there a better way to do this? 3216 EVT VT = TLI->getValueType(DL, ValTy); 3217 if (VT.isSimple()) { 3218 MVT MTy = VT.getSimpleVT(); 3219 if (ST->hasBWI()) 3220 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3221 return Entry->Cost; 3222 3223 if (ST->hasAVX()) 3224 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3225 return Entry->Cost; 3226 3227 if (ST->hasSSE41()) 3228 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3229 return Entry->Cost; 3230 3231 if (ST->hasSSE2()) 3232 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3233 return Entry->Cost; 3234 } 3235 3236 auto *ValVTy = cast<VectorType>(ValTy); 3237 unsigned NumVecElts = ValVTy->getNumElements(); 3238 3239 auto *Ty = ValVTy; 3240 unsigned MinMaxCost = 0; 3241 if (LT.first != 1 && MTy.isVector() && 3242 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3243 // Type needs to be split. We need LT.first - 1 operations ops. 3244 Ty = VectorType::get(ValVTy->getElementType(), MTy.getVectorNumElements()); 3245 auto *SubCondTy = VectorType::get( 3246 cast<VectorType>(CondTy)->getElementType(), MTy.getVectorNumElements()); 3247 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3248 MinMaxCost *= LT.first - 1; 3249 NumVecElts = MTy.getVectorNumElements(); 3250 } 3251 3252 if (ST->hasBWI()) 3253 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3254 return MinMaxCost + Entry->Cost; 3255 3256 if (ST->hasAVX()) 3257 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3258 return MinMaxCost + Entry->Cost; 3259 3260 if (ST->hasSSE41()) 3261 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3262 return MinMaxCost + Entry->Cost; 3263 3264 if (ST->hasSSE2()) 3265 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3266 return MinMaxCost + Entry->Cost; 3267 3268 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 3269 3270 // Special case power of 2 reductions where the scalar type isn't changed 3271 // by type legalization. 3272 if (!isPowerOf2_32(ValVTy->getNumElements()) || 3273 ScalarSize != MTy.getScalarSizeInBits()) 3274 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned); 3275 3276 // Now handle reduction with the legal type, taking into account size changes 3277 // at each level. 3278 while (NumVecElts > 1) { 3279 // Determine the size of the remaining vector we need to reduce. 3280 unsigned Size = NumVecElts * ScalarSize; 3281 NumVecElts /= 2; 3282 // If we're reducing from 256/512 bits, use an extract_subvector. 3283 if (Size > 128) { 3284 auto *SubTy = VectorType::get(ValVTy->getElementType(), NumVecElts); 3285 MinMaxCost += 3286 getShuffleCost(TTI::SK_ExtractSubvector, Ty, NumVecElts, SubTy); 3287 Ty = SubTy; 3288 } else if (Size == 128) { 3289 // Reducing from 128 bits is a permute of v2f64/v2i64. 3290 VectorType *ShufTy; 3291 if (ValTy->isFloatingPointTy()) 3292 ShufTy = VectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 3293 else 3294 ShufTy = VectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 3295 MinMaxCost += 3296 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3297 } else if (Size == 64) { 3298 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3299 VectorType *ShufTy; 3300 if (ValTy->isFloatingPointTy()) 3301 ShufTy = VectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 3302 else 3303 ShufTy = VectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 3304 MinMaxCost += 3305 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3306 } else { 3307 // Reducing from smaller size is a shift by immediate. 3308 VectorType *ShiftTy = VectorType::get( 3309 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 3310 MinMaxCost += getArithmeticInstrCost( 3311 Instruction::LShr, ShiftTy, TargetTransformInfo::OK_AnyValue, 3312 TargetTransformInfo::OK_UniformConstantValue, 3313 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3314 } 3315 3316 // Add the arithmetic op for this level. 3317 auto *SubCondTy = VectorType::get(CondTy->getElementType(), 3318 Ty->getNumElements()); 3319 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3320 } 3321 3322 // Add the final extract element to the cost. 3323 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3324 } 3325 3326 /// Calculate the cost of materializing a 64-bit value. This helper 3327 /// method might only calculate a fraction of a larger immediate. Therefore it 3328 /// is valid to return a cost of ZERO. 3329 int X86TTIImpl::getIntImmCost(int64_t Val) { 3330 if (Val == 0) 3331 return TTI::TCC_Free; 3332 3333 if (isInt<32>(Val)) 3334 return TTI::TCC_Basic; 3335 3336 return 2 * TTI::TCC_Basic; 3337 } 3338 3339 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { 3340 assert(Ty->isIntegerTy()); 3341 3342 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3343 if (BitSize == 0) 3344 return ~0U; 3345 3346 // Never hoist constants larger than 128bit, because this might lead to 3347 // incorrect code generation or assertions in codegen. 3348 // Fixme: Create a cost model for types larger than i128 once the codegen 3349 // issues have been fixed. 3350 if (BitSize > 128) 3351 return TTI::TCC_Free; 3352 3353 if (Imm == 0) 3354 return TTI::TCC_Free; 3355 3356 // Sign-extend all constants to a multiple of 64-bit. 3357 APInt ImmVal = Imm; 3358 if (BitSize % 64 != 0) 3359 ImmVal = Imm.sext(alignTo(BitSize, 64)); 3360 3361 // Split the constant into 64-bit chunks and calculate the cost for each 3362 // chunk. 3363 int Cost = 0; 3364 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 3365 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 3366 int64_t Val = Tmp.getSExtValue(); 3367 Cost += getIntImmCost(Val); 3368 } 3369 // We need at least one instruction to materialize the constant. 3370 return std::max(1, Cost); 3371 } 3372 3373 int X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, 3374 Type *Ty) { 3375 assert(Ty->isIntegerTy()); 3376 3377 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3378 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3379 // here, so that constant hoisting will ignore this constant. 3380 if (BitSize == 0) 3381 return TTI::TCC_Free; 3382 3383 unsigned ImmIdx = ~0U; 3384 switch (Opcode) { 3385 default: 3386 return TTI::TCC_Free; 3387 case Instruction::GetElementPtr: 3388 // Always hoist the base address of a GetElementPtr. This prevents the 3389 // creation of new constants for every base constant that gets constant 3390 // folded with the offset. 3391 if (Idx == 0) 3392 return 2 * TTI::TCC_Basic; 3393 return TTI::TCC_Free; 3394 case Instruction::Store: 3395 ImmIdx = 0; 3396 break; 3397 case Instruction::ICmp: 3398 // This is an imperfect hack to prevent constant hoisting of 3399 // compares that might be trying to check if a 64-bit value fits in 3400 // 32-bits. The backend can optimize these cases using a right shift by 32. 3401 // Ideally we would check the compare predicate here. There also other 3402 // similar immediates the backend can use shifts for. 3403 if (Idx == 1 && Imm.getBitWidth() == 64) { 3404 uint64_t ImmVal = Imm.getZExtValue(); 3405 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 3406 return TTI::TCC_Free; 3407 } 3408 ImmIdx = 1; 3409 break; 3410 case Instruction::And: 3411 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 3412 // by using a 32-bit operation with implicit zero extension. Detect such 3413 // immediates here as the normal path expects bit 31 to be sign extended. 3414 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 3415 return TTI::TCC_Free; 3416 ImmIdx = 1; 3417 break; 3418 case Instruction::Add: 3419 case Instruction::Sub: 3420 // For add/sub, we can use the opposite instruction for INT32_MIN. 3421 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 3422 return TTI::TCC_Free; 3423 ImmIdx = 1; 3424 break; 3425 case Instruction::UDiv: 3426 case Instruction::SDiv: 3427 case Instruction::URem: 3428 case Instruction::SRem: 3429 // Division by constant is typically expanded later into a different 3430 // instruction sequence. This completely changes the constants. 3431 // Report them as "free" to stop ConstantHoist from marking them as opaque. 3432 return TTI::TCC_Free; 3433 case Instruction::Mul: 3434 case Instruction::Or: 3435 case Instruction::Xor: 3436 ImmIdx = 1; 3437 break; 3438 // Always return TCC_Free for the shift value of a shift instruction. 3439 case Instruction::Shl: 3440 case Instruction::LShr: 3441 case Instruction::AShr: 3442 if (Idx == 1) 3443 return TTI::TCC_Free; 3444 break; 3445 case Instruction::Trunc: 3446 case Instruction::ZExt: 3447 case Instruction::SExt: 3448 case Instruction::IntToPtr: 3449 case Instruction::PtrToInt: 3450 case Instruction::BitCast: 3451 case Instruction::PHI: 3452 case Instruction::Call: 3453 case Instruction::Select: 3454 case Instruction::Ret: 3455 case Instruction::Load: 3456 break; 3457 } 3458 3459 if (Idx == ImmIdx) { 3460 int NumConstants = divideCeil(BitSize, 64); 3461 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty); 3462 return (Cost <= NumConstants * TTI::TCC_Basic) 3463 ? static_cast<int>(TTI::TCC_Free) 3464 : Cost; 3465 } 3466 3467 return X86TTIImpl::getIntImmCost(Imm, Ty); 3468 } 3469 3470 int X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 3471 const APInt &Imm, Type *Ty) { 3472 assert(Ty->isIntegerTy()); 3473 3474 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3475 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3476 // here, so that constant hoisting will ignore this constant. 3477 if (BitSize == 0) 3478 return TTI::TCC_Free; 3479 3480 switch (IID) { 3481 default: 3482 return TTI::TCC_Free; 3483 case Intrinsic::sadd_with_overflow: 3484 case Intrinsic::uadd_with_overflow: 3485 case Intrinsic::ssub_with_overflow: 3486 case Intrinsic::usub_with_overflow: 3487 case Intrinsic::smul_with_overflow: 3488 case Intrinsic::umul_with_overflow: 3489 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 3490 return TTI::TCC_Free; 3491 break; 3492 case Intrinsic::experimental_stackmap: 3493 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 3494 return TTI::TCC_Free; 3495 break; 3496 case Intrinsic::experimental_patchpoint_void: 3497 case Intrinsic::experimental_patchpoint_i64: 3498 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 3499 return TTI::TCC_Free; 3500 break; 3501 } 3502 return X86TTIImpl::getIntImmCost(Imm, Ty); 3503 } 3504 3505 unsigned X86TTIImpl::getUserCost(const User *U, 3506 ArrayRef<const Value *> Operands) { 3507 if (isa<StoreInst>(U)) { 3508 Value *Ptr = U->getOperand(1); 3509 // Store instruction with index and scale costs 2 Uops. 3510 // Check the preceding GEP to identify non-const indices. 3511 if (auto GEP = dyn_cast<GetElementPtrInst>(Ptr)) { 3512 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3513 return TTI::TCC_Basic * 2; 3514 } 3515 return TTI::TCC_Basic; 3516 } 3517 return BaseT::getUserCost(U, Operands); 3518 } 3519 3520 // Return an average cost of Gather / Scatter instruction, maybe improved later 3521 int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, Value *Ptr, 3522 unsigned Alignment, unsigned AddressSpace) { 3523 3524 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 3525 unsigned VF = cast<VectorType>(SrcVTy)->getNumElements(); 3526 3527 // Try to reduce index size from 64 bit (default for GEP) 3528 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 3529 // operation will use 16 x 64 indices which do not fit in a zmm and needs 3530 // to split. Also check that the base pointer is the same for all lanes, 3531 // and that there's at most one variable index. 3532 auto getIndexSizeInBits = [](Value *Ptr, const DataLayout& DL) { 3533 unsigned IndexSize = DL.getPointerSizeInBits(); 3534 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 3535 if (IndexSize < 64 || !GEP) 3536 return IndexSize; 3537 3538 unsigned NumOfVarIndices = 0; 3539 Value *Ptrs = GEP->getPointerOperand(); 3540 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 3541 return IndexSize; 3542 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 3543 if (isa<Constant>(GEP->getOperand(i))) 3544 continue; 3545 Type *IndxTy = GEP->getOperand(i)->getType(); 3546 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 3547 IndxTy = IndexVTy->getElementType(); 3548 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 3549 !isa<SExtInst>(GEP->getOperand(i))) || 3550 ++NumOfVarIndices > 1) 3551 return IndexSize; // 64 3552 } 3553 return (unsigned)32; 3554 }; 3555 3556 3557 // Trying to reduce IndexSize to 32 bits for vector 16. 3558 // By default the IndexSize is equal to pointer size. 3559 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 3560 ? getIndexSizeInBits(Ptr, DL) 3561 : DL.getPointerSizeInBits(); 3562 3563 Type *IndexVTy = VectorType::get(IntegerType::get(SrcVTy->getContext(), 3564 IndexSize), VF); 3565 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy); 3566 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3567 int SplitFactor = std::max(IdxsLT.first, SrcLT.first); 3568 if (SplitFactor > 1) { 3569 // Handle splitting of vector of pointers 3570 Type *SplitSrcTy = VectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 3571 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 3572 AddressSpace); 3573 } 3574 3575 // The gather / scatter cost is given by Intel architects. It is a rough 3576 // number since we are looking at one instruction in a time. 3577 const int GSOverhead = (Opcode == Instruction::Load) 3578 ? ST->getGatherOverhead() 3579 : ST->getScatterOverhead(); 3580 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3581 MaybeAlign(Alignment), AddressSpace); 3582 } 3583 3584 /// Return the cost of full scalarization of gather / scatter operation. 3585 /// 3586 /// Opcode - Load or Store instruction. 3587 /// SrcVTy - The type of the data vector that should be gathered or scattered. 3588 /// VariableMask - The mask is non-constant at compile time. 3589 /// Alignment - Alignment for one element. 3590 /// AddressSpace - pointer[s] address space. 3591 /// 3592 int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 3593 bool VariableMask, unsigned Alignment, 3594 unsigned AddressSpace) { 3595 unsigned VF = cast<VectorType>(SrcVTy)->getNumElements(); 3596 3597 int MaskUnpackCost = 0; 3598 if (VariableMask) { 3599 VectorType *MaskTy = 3600 VectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 3601 MaskUnpackCost = getScalarizationOverhead(MaskTy, false, true); 3602 int ScalarCompareCost = 3603 getCmpSelInstrCost(Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), 3604 nullptr); 3605 int BranchCost = getCFInstrCost(Instruction::Br); 3606 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 3607 } 3608 3609 // The cost of the scalar loads/stores. 3610 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3611 MaybeAlign(Alignment), AddressSpace); 3612 3613 int InsertExtractCost = 0; 3614 if (Opcode == Instruction::Load) 3615 for (unsigned i = 0; i < VF; ++i) 3616 // Add the cost of inserting each scalar load into the vector 3617 InsertExtractCost += 3618 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 3619 else 3620 for (unsigned i = 0; i < VF; ++i) 3621 // Add the cost of extracting each element out of the data vector 3622 InsertExtractCost += 3623 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 3624 3625 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 3626 } 3627 3628 /// Calculate the cost of Gather / Scatter operation 3629 int X86TTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *SrcVTy, 3630 Value *Ptr, bool VariableMask, 3631 unsigned Alignment, 3632 const Instruction *I = nullptr) { 3633 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 3634 unsigned VF = cast<VectorType>(SrcVTy)->getNumElements(); 3635 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 3636 if (!PtrTy && Ptr->getType()->isVectorTy()) 3637 PtrTy = dyn_cast<PointerType>( 3638 cast<VectorType>(Ptr->getType())->getElementType()); 3639 assert(PtrTy && "Unexpected type for Ptr argument"); 3640 unsigned AddressSpace = PtrTy->getAddressSpace(); 3641 3642 bool Scalarize = false; 3643 if ((Opcode == Instruction::Load && 3644 !isLegalMaskedGather(SrcVTy, MaybeAlign(Alignment))) || 3645 (Opcode == Instruction::Store && 3646 !isLegalMaskedScatter(SrcVTy, MaybeAlign(Alignment)))) 3647 Scalarize = true; 3648 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 3649 // Vector-4 of gather/scatter instruction does not exist on KNL. 3650 // We can extend it to 8 elements, but zeroing upper bits of 3651 // the mask vector will add more instructions. Right now we give the scalar 3652 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 3653 // is better in the VariableMask case. 3654 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 3655 Scalarize = true; 3656 3657 if (Scalarize) 3658 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 3659 AddressSpace); 3660 3661 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 3662 } 3663 3664 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 3665 TargetTransformInfo::LSRCost &C2) { 3666 // X86 specific here are "instruction number 1st priority". 3667 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 3668 C1.NumIVMuls, C1.NumBaseAdds, 3669 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 3670 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 3671 C2.NumIVMuls, C2.NumBaseAdds, 3672 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 3673 } 3674 3675 bool X86TTIImpl::canMacroFuseCmp() { 3676 return ST->hasMacroFusion() || ST->hasBranchFusion(); 3677 } 3678 3679 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, MaybeAlign Alignment) { 3680 if (!ST->hasAVX()) 3681 return false; 3682 3683 // The backend can't handle a single element vector. 3684 if (isa<VectorType>(DataTy) && 3685 cast<VectorType>(DataTy)->getNumElements() == 1) 3686 return false; 3687 Type *ScalarTy = DataTy->getScalarType(); 3688 3689 if (ScalarTy->isPointerTy()) 3690 return true; 3691 3692 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 3693 return true; 3694 3695 if (!ScalarTy->isIntegerTy()) 3696 return false; 3697 3698 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 3699 return IntWidth == 32 || IntWidth == 64 || 3700 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 3701 } 3702 3703 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, MaybeAlign Alignment) { 3704 return isLegalMaskedLoad(DataType, Alignment); 3705 } 3706 3707 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 3708 unsigned DataSize = DL.getTypeStoreSize(DataType); 3709 // The only supported nontemporal loads are for aligned vectors of 16 or 32 3710 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 3711 // (the equivalent stores only require AVX). 3712 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 3713 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 3714 3715 return false; 3716 } 3717 3718 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 3719 unsigned DataSize = DL.getTypeStoreSize(DataType); 3720 3721 // SSE4A supports nontemporal stores of float and double at arbitrary 3722 // alignment. 3723 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 3724 return true; 3725 3726 // Besides the SSE4A subtarget exception above, only aligned stores are 3727 // available nontemporaly on any other subtarget. And only stores with a size 3728 // of 4..32 bytes (powers of 2, only) are permitted. 3729 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 3730 !isPowerOf2_32(DataSize)) 3731 return false; 3732 3733 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 3734 // loads require AVX2). 3735 if (DataSize == 32) 3736 return ST->hasAVX(); 3737 else if (DataSize == 16) 3738 return ST->hasSSE1(); 3739 return true; 3740 } 3741 3742 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 3743 if (!isa<VectorType>(DataTy)) 3744 return false; 3745 3746 if (!ST->hasAVX512()) 3747 return false; 3748 3749 // The backend can't handle a single element vector. 3750 if (cast<VectorType>(DataTy)->getNumElements() == 1) 3751 return false; 3752 3753 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 3754 3755 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 3756 return true; 3757 3758 if (!ScalarTy->isIntegerTy()) 3759 return false; 3760 3761 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 3762 return IntWidth == 32 || IntWidth == 64 || 3763 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 3764 } 3765 3766 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 3767 return isLegalMaskedExpandLoad(DataTy); 3768 } 3769 3770 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, MaybeAlign Alignment) { 3771 // Some CPUs have better gather performance than others. 3772 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 3773 // enable gather with a -march. 3774 if (!(ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()))) 3775 return false; 3776 3777 // This function is called now in two cases: from the Loop Vectorizer 3778 // and from the Scalarizer. 3779 // When the Loop Vectorizer asks about legality of the feature, 3780 // the vectorization factor is not calculated yet. The Loop Vectorizer 3781 // sends a scalar type and the decision is based on the width of the 3782 // scalar element. 3783 // Later on, the cost model will estimate usage this intrinsic based on 3784 // the vector type. 3785 // The Scalarizer asks again about legality. It sends a vector type. 3786 // In this case we can reject non-power-of-2 vectors. 3787 // We also reject single element vectors as the type legalizer can't 3788 // scalarize it. 3789 if (auto *DataVTy = dyn_cast<VectorType>(DataTy)) { 3790 unsigned NumElts = DataVTy->getNumElements(); 3791 if (NumElts == 1 || !isPowerOf2_32(NumElts)) 3792 return false; 3793 } 3794 Type *ScalarTy = DataTy->getScalarType(); 3795 if (ScalarTy->isPointerTy()) 3796 return true; 3797 3798 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 3799 return true; 3800 3801 if (!ScalarTy->isIntegerTy()) 3802 return false; 3803 3804 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 3805 return IntWidth == 32 || IntWidth == 64; 3806 } 3807 3808 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, MaybeAlign Alignment) { 3809 // AVX2 doesn't support scatter 3810 if (!ST->hasAVX512()) 3811 return false; 3812 return isLegalMaskedGather(DataType, Alignment); 3813 } 3814 3815 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 3816 EVT VT = TLI->getValueType(DL, DataType); 3817 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 3818 } 3819 3820 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 3821 return false; 3822 } 3823 3824 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 3825 const Function *Callee) const { 3826 const TargetMachine &TM = getTLI()->getTargetMachine(); 3827 3828 // Work this as a subsetting of subtarget features. 3829 const FeatureBitset &CallerBits = 3830 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 3831 const FeatureBitset &CalleeBits = 3832 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 3833 3834 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 3835 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 3836 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 3837 } 3838 3839 bool X86TTIImpl::areFunctionArgsABICompatible( 3840 const Function *Caller, const Function *Callee, 3841 SmallPtrSetImpl<Argument *> &Args) const { 3842 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args)) 3843 return false; 3844 3845 // If we get here, we know the target features match. If one function 3846 // considers 512-bit vectors legal and the other does not, consider them 3847 // incompatible. 3848 // FIXME Look at the arguments and only consider 512 bit or larger vectors? 3849 const TargetMachine &TM = getTLI()->getTargetMachine(); 3850 3851 return TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 3852 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs(); 3853 } 3854 3855 X86TTIImpl::TTI::MemCmpExpansionOptions 3856 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 3857 TTI::MemCmpExpansionOptions Options; 3858 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 3859 Options.NumLoadsPerBlock = 2; 3860 // All GPR and vector loads can be unaligned. 3861 Options.AllowOverlappingLoads = true; 3862 if (IsZeroCmp) { 3863 // Only enable vector loads for equality comparison. Right now the vector 3864 // version is not as fast for three way compare (see #33329). 3865 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 3866 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 3867 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 3868 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 3869 } 3870 if (ST->is64Bit()) { 3871 Options.LoadSizes.push_back(8); 3872 } 3873 Options.LoadSizes.push_back(4); 3874 Options.LoadSizes.push_back(2); 3875 Options.LoadSizes.push_back(1); 3876 return Options; 3877 } 3878 3879 bool X86TTIImpl::enableInterleavedAccessVectorization() { 3880 // TODO: We expect this to be beneficial regardless of arch, 3881 // but there are currently some unexplained performance artifacts on Atom. 3882 // As a temporary solution, disable on Atom. 3883 return !(ST->isAtom()); 3884 } 3885 3886 // Get estimation for interleaved load/store operations for AVX2. 3887 // \p Factor is the interleaved-access factor (stride) - number of 3888 // (interleaved) elements in the group. 3889 // \p Indices contains the indices for a strided load: when the 3890 // interleaved load has gaps they indicate which elements are used. 3891 // If Indices is empty (or if the number of indices is equal to the size 3892 // of the interleaved-access as given in \p Factor) the access has no gaps. 3893 // 3894 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 3895 // computing the cost using a generic formula as a function of generic 3896 // shuffles. We therefore use a lookup table instead, filled according to 3897 // the instruction sequences that codegen currently generates. 3898 int X86TTIImpl::getInterleavedMemoryOpCostAVX2(unsigned Opcode, Type *VecTy, 3899 unsigned Factor, 3900 ArrayRef<unsigned> Indices, 3901 unsigned Alignment, 3902 unsigned AddressSpace, 3903 bool UseMaskForCond, 3904 bool UseMaskForGaps) { 3905 3906 if (UseMaskForCond || UseMaskForGaps) 3907 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3908 Alignment, AddressSpace, 3909 UseMaskForCond, UseMaskForGaps); 3910 3911 // We currently Support only fully-interleaved groups, with no gaps. 3912 // TODO: Support also strided loads (interleaved-groups with gaps). 3913 if (Indices.size() && Indices.size() != Factor) 3914 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3915 Alignment, AddressSpace); 3916 3917 // VecTy for interleave memop is <VF*Factor x Elt>. 3918 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 3919 // VecTy = <12 x i32>. 3920 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 3921 3922 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 3923 // the VF=2, while v2i128 is an unsupported MVT vector type 3924 // (see MachineValueType.h::getVectorVT()). 3925 if (!LegalVT.isVector()) 3926 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3927 Alignment, AddressSpace); 3928 3929 unsigned VF = cast<VectorType>(VecTy)->getNumElements() / Factor; 3930 Type *ScalarTy = cast<VectorType>(VecTy)->getElementType(); 3931 3932 // Calculate the number of memory operations (NumOfMemOps), required 3933 // for load/store the VecTy. 3934 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 3935 unsigned LegalVTSize = LegalVT.getStoreSize(); 3936 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 3937 3938 // Get the cost of one memory operation. 3939 Type *SingleMemOpTy = 3940 VectorType::get(cast<VectorType>(VecTy)->getElementType(), 3941 LegalVT.getVectorNumElements()); 3942 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 3943 MaybeAlign(Alignment), AddressSpace); 3944 3945 VectorType *VT = VectorType::get(ScalarTy, VF); 3946 EVT ETy = TLI->getValueType(DL, VT); 3947 if (!ETy.isSimple()) 3948 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3949 Alignment, AddressSpace); 3950 3951 // TODO: Complete for other data-types and strides. 3952 // Each combination of Stride, ElementTy and VF results in a different 3953 // sequence; The cost tables are therefore accessed with: 3954 // Factor (stride) and VectorType=VFxElemType. 3955 // The Cost accounts only for the shuffle sequence; 3956 // The cost of the loads/stores is accounted for separately. 3957 // 3958 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 3959 { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64 3960 { 2, MVT::v4f64, 6 }, //(load 8f64 and) deinterleave into 2 x 4f64 3961 3962 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8 3963 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8 3964 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8 3965 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8 3966 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8 3967 { 3, MVT::v8f32, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32 3968 3969 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8 3970 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8 3971 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8 3972 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8 3973 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8 3974 3975 { 8, MVT::v8f32, 40 } //(load 64f32 and)deinterleave into 8 x 8f32 3976 }; 3977 3978 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 3979 { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store) 3980 { 2, MVT::v4f64, 6 }, //interleave into 2 x 4f64 into 8f64 (and store) 3981 3982 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store) 3983 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store) 3984 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store) 3985 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store) 3986 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store) 3987 3988 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store) 3989 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store) 3990 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store) 3991 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store) 3992 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store) 3993 }; 3994 3995 if (Opcode == Instruction::Load) { 3996 if (const auto *Entry = 3997 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 3998 return NumOfMemOps * MemOpCost + Entry->Cost; 3999 } else { 4000 assert(Opcode == Instruction::Store && 4001 "Expected Store Instruction at this point"); 4002 if (const auto *Entry = 4003 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 4004 return NumOfMemOps * MemOpCost + Entry->Cost; 4005 } 4006 4007 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4008 Alignment, AddressSpace); 4009 } 4010 4011 // Get estimation for interleaved load/store operations and strided load. 4012 // \p Indices contains indices for strided load. 4013 // \p Factor - the factor of interleaving. 4014 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 4015 int X86TTIImpl::getInterleavedMemoryOpCostAVX512(unsigned Opcode, Type *VecTy, 4016 unsigned Factor, 4017 ArrayRef<unsigned> Indices, 4018 unsigned Alignment, 4019 unsigned AddressSpace, 4020 bool UseMaskForCond, 4021 bool UseMaskForGaps) { 4022 4023 if (UseMaskForCond || UseMaskForGaps) 4024 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4025 Alignment, AddressSpace, 4026 UseMaskForCond, UseMaskForGaps); 4027 4028 // VecTy for interleave memop is <VF*Factor x Elt>. 4029 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4030 // VecTy = <12 x i32>. 4031 4032 // Calculate the number of memory operations (NumOfMemOps), required 4033 // for load/store the VecTy. 4034 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4035 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4036 unsigned LegalVTSize = LegalVT.getStoreSize(); 4037 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4038 4039 // Get the cost of one memory operation. 4040 auto *SingleMemOpTy = 4041 VectorType::get(cast<VectorType>(VecTy)->getElementType(), 4042 LegalVT.getVectorNumElements()); 4043 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 4044 MaybeAlign(Alignment), AddressSpace); 4045 4046 unsigned VF = cast<VectorType>(VecTy)->getNumElements() / Factor; 4047 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 4048 4049 if (Opcode == Instruction::Load) { 4050 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 4051 // contain the cost of the optimized shuffle sequence that the 4052 // X86InterleavedAccess pass will generate. 4053 // The cost of loads and stores are computed separately from the table. 4054 4055 // X86InterleavedAccess support only the following interleaved-access group. 4056 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 4057 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 4058 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 4059 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 4060 }; 4061 4062 if (const auto *Entry = 4063 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 4064 return NumOfMemOps * MemOpCost + Entry->Cost; 4065 //If an entry does not exist, fallback to the default implementation. 4066 4067 // Kind of shuffle depends on number of loaded values. 4068 // If we load the entire data in one register, we can use a 1-src shuffle. 4069 // Otherwise, we'll merge 2 sources in each operation. 4070 TTI::ShuffleKind ShuffleKind = 4071 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 4072 4073 unsigned ShuffleCost = 4074 getShuffleCost(ShuffleKind, SingleMemOpTy, 0, nullptr); 4075 4076 unsigned NumOfLoadsInInterleaveGrp = 4077 Indices.size() ? Indices.size() : Factor; 4078 Type *ResultTy = 4079 VectorType::get(cast<VectorType>(VecTy)->getElementType(), 4080 cast<VectorType>(VecTy)->getNumElements() / Factor); 4081 unsigned NumOfResults = 4082 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 4083 NumOfLoadsInInterleaveGrp; 4084 4085 // About a half of the loads may be folded in shuffles when we have only 4086 // one result. If we have more than one result, we do not fold loads at all. 4087 unsigned NumOfUnfoldedLoads = 4088 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 4089 4090 // Get a number of shuffle operations per result. 4091 unsigned NumOfShufflesPerResult = 4092 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 4093 4094 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4095 // When we have more than one destination, we need additional instructions 4096 // to keep sources. 4097 unsigned NumOfMoves = 0; 4098 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 4099 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 4100 4101 int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 4102 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 4103 4104 return Cost; 4105 } 4106 4107 // Store. 4108 assert(Opcode == Instruction::Store && 4109 "Expected Store Instruction at this point"); 4110 // X86InterleavedAccess support only the following interleaved-access group. 4111 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 4112 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 4113 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 4114 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 4115 4116 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 4117 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 4118 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 4119 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 4120 }; 4121 4122 if (const auto *Entry = 4123 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 4124 return NumOfMemOps * MemOpCost + Entry->Cost; 4125 //If an entry does not exist, fallback to the default implementation. 4126 4127 // There is no strided stores meanwhile. And store can't be folded in 4128 // shuffle. 4129 unsigned NumOfSources = Factor; // The number of values to be merged. 4130 unsigned ShuffleCost = 4131 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, 0, nullptr); 4132 unsigned NumOfShufflesPerStore = NumOfSources - 1; 4133 4134 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4135 // We need additional instructions to keep sources. 4136 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 4137 int Cost = NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 4138 NumOfMoves; 4139 return Cost; 4140 } 4141 4142 int X86TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, 4143 unsigned Factor, 4144 ArrayRef<unsigned> Indices, 4145 unsigned Alignment, 4146 unsigned AddressSpace, 4147 bool UseMaskForCond, 4148 bool UseMaskForGaps) { 4149 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 4150 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 4151 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 4152 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 4153 return true; 4154 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 4155 return HasBW; 4156 return false; 4157 }; 4158 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 4159 return getInterleavedMemoryOpCostAVX512(Opcode, VecTy, Factor, Indices, 4160 Alignment, AddressSpace, 4161 UseMaskForCond, UseMaskForGaps); 4162 if (ST->hasAVX2()) 4163 return getInterleavedMemoryOpCostAVX2(Opcode, VecTy, Factor, Indices, 4164 Alignment, AddressSpace, 4165 UseMaskForCond, UseMaskForGaps); 4166 4167 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4168 Alignment, AddressSpace, 4169 UseMaskForCond, UseMaskForGaps); 4170 } 4171