1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // X86 cost model. 56 // 57 //===----------------------------------------------------------------------===// 58 59 TargetTransformInfo::PopcntSupportKind 60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 61 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 62 // TODO: Currently the __builtin_popcount() implementation using SSE3 63 // instructions is inefficient. Once the problem is fixed, we should 64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 66 } 67 68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 69 TargetTransformInfo::CacheLevel Level) const { 70 switch (Level) { 71 case TargetTransformInfo::CacheLevel::L1D: 72 // - Penryn 73 // - Nehalem 74 // - Westmere 75 // - Sandy Bridge 76 // - Ivy Bridge 77 // - Haswell 78 // - Broadwell 79 // - Skylake 80 // - Kabylake 81 return 32 * 1024; // 32 KByte 82 case TargetTransformInfo::CacheLevel::L2D: 83 // - Penryn 84 // - Nehalem 85 // - Westmere 86 // - Sandy Bridge 87 // - Ivy Bridge 88 // - Haswell 89 // - Broadwell 90 // - Skylake 91 // - Kabylake 92 return 256 * 1024; // 256 KByte 93 } 94 95 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 96 } 97 98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 99 TargetTransformInfo::CacheLevel Level) const { 100 // - Penryn 101 // - Nehalem 102 // - Westmere 103 // - Sandy Bridge 104 // - Ivy Bridge 105 // - Haswell 106 // - Broadwell 107 // - Skylake 108 // - Kabylake 109 switch (Level) { 110 case TargetTransformInfo::CacheLevel::L1D: 111 LLVM_FALLTHROUGH; 112 case TargetTransformInfo::CacheLevel::L2D: 113 return 8; 114 } 115 116 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 117 } 118 119 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 120 bool Vector = (ClassID == 1); 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 TypeSize 133 X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { 134 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 135 switch (K) { 136 case TargetTransformInfo::RGK_Scalar: 137 return TypeSize::getFixed(ST->is64Bit() ? 64 : 32); 138 case TargetTransformInfo::RGK_FixedWidthVector: 139 if (ST->hasAVX512() && PreferVectorWidth >= 512) 140 return TypeSize::getFixed(512); 141 if (ST->hasAVX() && PreferVectorWidth >= 256) 142 return TypeSize::getFixed(256); 143 if (ST->hasSSE1() && PreferVectorWidth >= 128) 144 return TypeSize::getFixed(128); 145 return TypeSize::getFixed(0); 146 case TargetTransformInfo::RGK_ScalableVector: 147 return TypeSize::getScalable(0); 148 } 149 150 llvm_unreachable("Unsupported register kind"); 151 } 152 153 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 154 return getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector) 155 .getFixedSize(); 156 } 157 158 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 159 // If the loop will not be vectorized, don't interleave the loop. 160 // Let regular unroll to unroll the loop, which saves the overflow 161 // check and memory check cost. 162 if (VF == 1) 163 return 1; 164 165 if (ST->isAtom()) 166 return 1; 167 168 // Sandybridge and Haswell have multiple execution ports and pipelined 169 // vector units. 170 if (ST->hasAVX()) 171 return 4; 172 173 return 2; 174 } 175 176 InstructionCost X86TTIImpl::getArithmeticInstrCost( 177 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, 178 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 179 TTI::OperandValueProperties Opd1PropInfo, 180 TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, 181 const Instruction *CxtI) { 182 // TODO: Handle more cost kinds. 183 if (CostKind != TTI::TCK_RecipThroughput) 184 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, 185 Op2Info, Opd1PropInfo, 186 Opd2PropInfo, Args, CxtI); 187 188 // vXi8 multiplications are always promoted to vXi16. 189 if (Opcode == Instruction::Mul && Ty->isVectorTy() && 190 Ty->getScalarSizeInBits() == 8) { 191 Type *WideVecTy = 192 VectorType::getExtendedElementVectorType(cast<VectorType>(Ty)); 193 return getCastInstrCost(Instruction::ZExt, WideVecTy, Ty, 194 TargetTransformInfo::CastContextHint::None, 195 CostKind) + 196 getCastInstrCost(Instruction::Trunc, Ty, WideVecTy, 197 TargetTransformInfo::CastContextHint::None, 198 CostKind) + 199 getArithmeticInstrCost(Opcode, WideVecTy, CostKind, Op1Info, Op2Info, 200 Opd1PropInfo, Opd2PropInfo); 201 } 202 203 // Legalize the type. 204 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 205 206 int ISD = TLI->InstructionOpcodeToISD(Opcode); 207 assert(ISD && "Invalid opcode"); 208 209 static const CostTblEntry GLMCostTable[] = { 210 { ISD::FDIV, MVT::f32, 18 }, // divss 211 { ISD::FDIV, MVT::v4f32, 35 }, // divps 212 { ISD::FDIV, MVT::f64, 33 }, // divsd 213 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 214 }; 215 216 if (ST->useGLMDivSqrtCosts()) 217 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 218 LT.second)) 219 return LT.first * Entry->Cost; 220 221 static const CostTblEntry SLMCostTable[] = { 222 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 223 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 224 { ISD::FMUL, MVT::f64, 2 }, // mulsd 225 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 226 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 227 { ISD::FDIV, MVT::f32, 17 }, // divss 228 { ISD::FDIV, MVT::v4f32, 39 }, // divps 229 { ISD::FDIV, MVT::f64, 32 }, // divsd 230 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 231 { ISD::FADD, MVT::v2f64, 2 }, // addpd 232 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 233 // v2i64/v4i64 mul is custom lowered as a series of long: 234 // multiplies(3), shifts(3) and adds(2) 235 // slm muldq version throughput is 2 and addq throughput 4 236 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 237 // 3X4 (addq throughput) = 17 238 { ISD::MUL, MVT::v2i64, 17 }, 239 // slm addq\subq throughput is 4 240 { ISD::ADD, MVT::v2i64, 4 }, 241 { ISD::SUB, MVT::v2i64, 4 }, 242 }; 243 244 if (ST->isSLM()) { 245 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 246 // Check if the operands can be shrinked into a smaller datatype. 247 bool Op1Signed = false; 248 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 249 bool Op2Signed = false; 250 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 251 252 bool SignedMode = Op1Signed || Op2Signed; 253 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 254 255 if (OpMinSize <= 7) 256 return LT.first * 3; // pmullw/sext 257 if (!SignedMode && OpMinSize <= 8) 258 return LT.first * 3; // pmullw/zext 259 if (OpMinSize <= 15) 260 return LT.first * 5; // pmullw/pmulhw/pshuf 261 if (!SignedMode && OpMinSize <= 16) 262 return LT.first * 5; // pmullw/pmulhw/pshuf 263 } 264 265 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 266 LT.second)) { 267 return LT.first * Entry->Cost; 268 } 269 } 270 271 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 272 ISD == ISD::UREM) && 273 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 274 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 275 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 276 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 277 // On X86, vector signed division by constants power-of-two are 278 // normally expanded to the sequence SRA + SRL + ADD + SRA. 279 // The OperandValue properties may not be the same as that of the previous 280 // operation; conservatively assume OP_None. 281 InstructionCost Cost = 282 2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Op1Info, 283 Op2Info, TargetTransformInfo::OP_None, 284 TargetTransformInfo::OP_None); 285 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 286 Op2Info, 287 TargetTransformInfo::OP_None, 288 TargetTransformInfo::OP_None); 289 Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind, Op1Info, 290 Op2Info, 291 TargetTransformInfo::OP_None, 292 TargetTransformInfo::OP_None); 293 294 if (ISD == ISD::SREM) { 295 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 296 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info, 297 Op2Info); 298 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info, 299 Op2Info); 300 } 301 302 return Cost; 303 } 304 305 // Vector unsigned division/remainder will be simplified to shifts/masks. 306 if (ISD == ISD::UDIV) 307 return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, 308 Op1Info, Op2Info, 309 TargetTransformInfo::OP_None, 310 TargetTransformInfo::OP_None); 311 312 else // UREM 313 return getArithmeticInstrCost(Instruction::And, Ty, CostKind, 314 Op1Info, Op2Info, 315 TargetTransformInfo::OP_None, 316 TargetTransformInfo::OP_None); 317 } 318 319 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 320 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 321 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 322 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 323 }; 324 325 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 326 ST->hasBWI()) { 327 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 328 LT.second)) 329 return LT.first * Entry->Cost; 330 } 331 332 static const CostTblEntry AVX512UniformConstCostTable[] = { 333 { ISD::SRA, MVT::v2i64, 1 }, 334 { ISD::SRA, MVT::v4i64, 1 }, 335 { ISD::SRA, MVT::v8i64, 1 }, 336 337 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 338 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 339 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 340 341 { ISD::SDIV, MVT::v16i32, 6 }, // pmuludq sequence 342 { ISD::SREM, MVT::v16i32, 8 }, // pmuludq+mul+sub sequence 343 { ISD::UDIV, MVT::v16i32, 5 }, // pmuludq sequence 344 { ISD::UREM, MVT::v16i32, 7 }, // pmuludq+mul+sub sequence 345 }; 346 347 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 348 ST->hasAVX512()) { 349 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 350 LT.second)) 351 return LT.first * Entry->Cost; 352 } 353 354 static const CostTblEntry AVX2UniformConstCostTable[] = { 355 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 356 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 357 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 358 359 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 360 361 { ISD::SDIV, MVT::v8i32, 6 }, // pmuludq sequence 362 { ISD::SREM, MVT::v8i32, 8 }, // pmuludq+mul+sub sequence 363 { ISD::UDIV, MVT::v8i32, 5 }, // pmuludq sequence 364 { ISD::UREM, MVT::v8i32, 7 }, // pmuludq+mul+sub sequence 365 }; 366 367 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 368 ST->hasAVX2()) { 369 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 370 LT.second)) 371 return LT.first * Entry->Cost; 372 } 373 374 static const CostTblEntry SSE2UniformConstCostTable[] = { 375 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 376 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 377 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 378 379 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 380 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 381 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 382 383 { ISD::SDIV, MVT::v8i32, 12+2 }, // 2*pmuludq sequence + split. 384 { ISD::SREM, MVT::v8i32, 16+2 }, // 2*pmuludq+mul+sub sequence + split. 385 { ISD::SDIV, MVT::v4i32, 6 }, // pmuludq sequence 386 { ISD::SREM, MVT::v4i32, 8 }, // pmuludq+mul+sub sequence 387 { ISD::UDIV, MVT::v8i32, 10+2 }, // 2*pmuludq sequence + split. 388 { ISD::UREM, MVT::v8i32, 14+2 }, // 2*pmuludq+mul+sub sequence + split. 389 { ISD::UDIV, MVT::v4i32, 5 }, // pmuludq sequence 390 { ISD::UREM, MVT::v4i32, 7 }, // pmuludq+mul+sub sequence 391 }; 392 393 // XOP has faster vXi8 shifts. 394 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 395 ST->hasSSE2() && !ST->hasXOP()) { 396 if (const auto *Entry = 397 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 398 return LT.first * Entry->Cost; 399 } 400 401 static const CostTblEntry AVX512BWConstCostTable[] = { 402 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 403 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 404 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 405 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 406 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 407 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 408 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 409 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 410 }; 411 412 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 413 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 414 ST->hasBWI()) { 415 if (const auto *Entry = 416 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 417 return LT.first * Entry->Cost; 418 } 419 420 static const CostTblEntry AVX512ConstCostTable[] = { 421 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 422 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 423 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 424 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 425 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 426 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 427 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 428 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 429 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 430 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 431 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 432 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 433 }; 434 435 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 436 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 437 ST->hasAVX512()) { 438 if (const auto *Entry = 439 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 440 return LT.first * Entry->Cost; 441 } 442 443 static const CostTblEntry AVX2ConstCostTable[] = { 444 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 445 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 446 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 447 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 448 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 449 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 450 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 451 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 452 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 453 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 454 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 455 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 456 }; 457 458 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 459 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 460 ST->hasAVX2()) { 461 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 462 return LT.first * Entry->Cost; 463 } 464 465 static const CostTblEntry SSE2ConstCostTable[] = { 466 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 467 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 468 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 469 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 470 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 471 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 472 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 473 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 474 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 475 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 476 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 477 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 478 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 479 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 480 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 481 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 482 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 483 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 484 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 485 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 486 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 487 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 488 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 489 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 490 }; 491 492 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 493 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 494 ST->hasSSE2()) { 495 // pmuldq sequence. 496 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 497 return LT.first * 32; 498 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 499 return LT.first * 38; 500 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 501 return LT.first * 15; 502 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 503 return LT.first * 20; 504 505 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 506 return LT.first * Entry->Cost; 507 } 508 509 static const CostTblEntry AVX512BWShiftCostTable[] = { 510 { ISD::SHL, MVT::v16i8, 4 }, // extend/vpsllvw/pack sequence. 511 { ISD::SRL, MVT::v16i8, 4 }, // extend/vpsrlvw/pack sequence. 512 { ISD::SRA, MVT::v16i8, 4 }, // extend/vpsravw/pack sequence. 513 { ISD::SHL, MVT::v32i8, 4 }, // extend/vpsllvw/pack sequence. 514 { ISD::SRL, MVT::v32i8, 4 }, // extend/vpsrlvw/pack sequence. 515 { ISD::SRA, MVT::v32i8, 6 }, // extend/vpsravw/pack sequence. 516 { ISD::SHL, MVT::v64i8, 6 }, // extend/vpsllvw/pack sequence. 517 { ISD::SRL, MVT::v64i8, 7 }, // extend/vpsrlvw/pack sequence. 518 { ISD::SRA, MVT::v64i8, 15 }, // extend/vpsravw/pack sequence. 519 520 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 521 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 522 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 523 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 524 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 525 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 526 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 527 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 528 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 529 }; 530 531 if (ST->hasBWI()) 532 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 533 return LT.first * Entry->Cost; 534 535 static const CostTblEntry AVX2UniformCostTable[] = { 536 // Uniform splats are cheaper for the following instructions. 537 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 538 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 539 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 540 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 541 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 542 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 543 544 { ISD::SHL, MVT::v8i32, 1 }, // pslld 545 { ISD::SRL, MVT::v8i32, 1 }, // psrld 546 { ISD::SRA, MVT::v8i32, 1 }, // psrad 547 { ISD::SHL, MVT::v4i64, 1 }, // psllq 548 { ISD::SRL, MVT::v4i64, 1 }, // psrlq 549 }; 550 551 if (ST->hasAVX2() && 552 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 553 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 554 if (const auto *Entry = 555 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 556 return LT.first * Entry->Cost; 557 } 558 559 static const CostTblEntry SSE2UniformCostTable[] = { 560 // Uniform splats are cheaper for the following instructions. 561 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 562 { ISD::SHL, MVT::v4i32, 1 }, // pslld 563 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 564 565 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 566 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 567 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 568 569 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 570 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 571 }; 572 573 if (ST->hasSSE2() && 574 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 575 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 576 if (const auto *Entry = 577 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 578 return LT.first * Entry->Cost; 579 } 580 581 static const CostTblEntry AVX512DQCostTable[] = { 582 { ISD::MUL, MVT::v2i64, 2 }, // pmullq 583 { ISD::MUL, MVT::v4i64, 2 }, // pmullq 584 { ISD::MUL, MVT::v8i64, 2 } // pmullq 585 }; 586 587 // Look for AVX512DQ lowering tricks for custom cases. 588 if (ST->hasDQI()) 589 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 590 return LT.first * Entry->Cost; 591 592 static const CostTblEntry AVX512BWCostTable[] = { 593 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 594 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 595 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 596 }; 597 598 // Look for AVX512BW lowering tricks for custom cases. 599 if (ST->hasBWI()) 600 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 601 return LT.first * Entry->Cost; 602 603 static const CostTblEntry AVX512CostTable[] = { 604 { ISD::SHL, MVT::v4i32, 1 }, 605 { ISD::SRL, MVT::v4i32, 1 }, 606 { ISD::SRA, MVT::v4i32, 1 }, 607 { ISD::SHL, MVT::v8i32, 1 }, 608 { ISD::SRL, MVT::v8i32, 1 }, 609 { ISD::SRA, MVT::v8i32, 1 }, 610 { ISD::SHL, MVT::v16i32, 1 }, 611 { ISD::SRL, MVT::v16i32, 1 }, 612 { ISD::SRA, MVT::v16i32, 1 }, 613 614 { ISD::SHL, MVT::v2i64, 1 }, 615 { ISD::SRL, MVT::v2i64, 1 }, 616 { ISD::SHL, MVT::v4i64, 1 }, 617 { ISD::SRL, MVT::v4i64, 1 }, 618 { ISD::SHL, MVT::v8i64, 1 }, 619 { ISD::SRL, MVT::v8i64, 1 }, 620 621 { ISD::SRA, MVT::v2i64, 1 }, 622 { ISD::SRA, MVT::v4i64, 1 }, 623 { ISD::SRA, MVT::v8i64, 1 }, 624 625 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 626 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 627 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 628 { ISD::MUL, MVT::v8i64, 6 }, // 3*pmuludq/3*shift/2*add 629 630 { ISD::FNEG, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 631 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 632 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 633 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 634 { ISD::FDIV, MVT::f64, 4 }, // Skylake from http://www.agner.org/ 635 { ISD::FDIV, MVT::v2f64, 4 }, // Skylake from http://www.agner.org/ 636 { ISD::FDIV, MVT::v4f64, 8 }, // Skylake from http://www.agner.org/ 637 { ISD::FDIV, MVT::v8f64, 16 }, // Skylake from http://www.agner.org/ 638 639 { ISD::FNEG, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 640 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 641 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 642 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 643 { ISD::FDIV, MVT::f32, 3 }, // Skylake from http://www.agner.org/ 644 { ISD::FDIV, MVT::v4f32, 3 }, // Skylake from http://www.agner.org/ 645 { ISD::FDIV, MVT::v8f32, 5 }, // Skylake from http://www.agner.org/ 646 { ISD::FDIV, MVT::v16f32, 10 }, // Skylake from http://www.agner.org/ 647 }; 648 649 if (ST->hasAVX512()) 650 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 651 return LT.first * Entry->Cost; 652 653 static const CostTblEntry AVX2ShiftCostTable[] = { 654 // Shifts on vXi64/vXi32 on AVX2 is legal even though we declare to 655 // customize them to detect the cases where shift amount is a scalar one. 656 { ISD::SHL, MVT::v4i32, 2 }, // vpsllvd (Haswell from agner.org) 657 { ISD::SRL, MVT::v4i32, 2 }, // vpsrlvd (Haswell from agner.org) 658 { ISD::SRA, MVT::v4i32, 2 }, // vpsravd (Haswell from agner.org) 659 { ISD::SHL, MVT::v8i32, 2 }, // vpsllvd (Haswell from agner.org) 660 { ISD::SRL, MVT::v8i32, 2 }, // vpsrlvd (Haswell from agner.org) 661 { ISD::SRA, MVT::v8i32, 2 }, // vpsravd (Haswell from agner.org) 662 { ISD::SHL, MVT::v2i64, 1 }, // vpsllvq (Haswell from agner.org) 663 { ISD::SRL, MVT::v2i64, 1 }, // vpsrlvq (Haswell from agner.org) 664 { ISD::SHL, MVT::v4i64, 1 }, // vpsllvq (Haswell from agner.org) 665 { ISD::SRL, MVT::v4i64, 1 }, // vpsrlvq (Haswell from agner.org) 666 }; 667 668 if (ST->hasAVX512()) { 669 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 670 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 671 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 672 // On AVX512, a packed v32i16 shift left by a constant build_vector 673 // is lowered into a vector multiply (vpmullw). 674 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 675 Op1Info, Op2Info, 676 TargetTransformInfo::OP_None, 677 TargetTransformInfo::OP_None); 678 } 679 680 // Look for AVX2 lowering tricks (XOP is always better at v4i32 shifts). 681 if (ST->hasAVX2() && !(ST->hasXOP() && LT.second == MVT::v4i32)) { 682 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 683 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 684 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 685 // On AVX2, a packed v16i16 shift left by a constant build_vector 686 // is lowered into a vector multiply (vpmullw). 687 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 688 Op1Info, Op2Info, 689 TargetTransformInfo::OP_None, 690 TargetTransformInfo::OP_None); 691 692 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 693 return LT.first * Entry->Cost; 694 } 695 696 static const CostTblEntry XOPShiftCostTable[] = { 697 // 128bit shifts take 1cy, but right shifts require negation beforehand. 698 { ISD::SHL, MVT::v16i8, 1 }, 699 { ISD::SRL, MVT::v16i8, 2 }, 700 { ISD::SRA, MVT::v16i8, 2 }, 701 { ISD::SHL, MVT::v8i16, 1 }, 702 { ISD::SRL, MVT::v8i16, 2 }, 703 { ISD::SRA, MVT::v8i16, 2 }, 704 { ISD::SHL, MVT::v4i32, 1 }, 705 { ISD::SRL, MVT::v4i32, 2 }, 706 { ISD::SRA, MVT::v4i32, 2 }, 707 { ISD::SHL, MVT::v2i64, 1 }, 708 { ISD::SRL, MVT::v2i64, 2 }, 709 { ISD::SRA, MVT::v2i64, 2 }, 710 // 256bit shifts require splitting if AVX2 didn't catch them above. 711 { ISD::SHL, MVT::v32i8, 2+2 }, 712 { ISD::SRL, MVT::v32i8, 4+2 }, 713 { ISD::SRA, MVT::v32i8, 4+2 }, 714 { ISD::SHL, MVT::v16i16, 2+2 }, 715 { ISD::SRL, MVT::v16i16, 4+2 }, 716 { ISD::SRA, MVT::v16i16, 4+2 }, 717 { ISD::SHL, MVT::v8i32, 2+2 }, 718 { ISD::SRL, MVT::v8i32, 4+2 }, 719 { ISD::SRA, MVT::v8i32, 4+2 }, 720 { ISD::SHL, MVT::v4i64, 2+2 }, 721 { ISD::SRL, MVT::v4i64, 4+2 }, 722 { ISD::SRA, MVT::v4i64, 4+2 }, 723 }; 724 725 // Look for XOP lowering tricks. 726 if (ST->hasXOP()) { 727 // If the right shift is constant then we'll fold the negation so 728 // it's as cheap as a left shift. 729 int ShiftISD = ISD; 730 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 731 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 732 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 733 ShiftISD = ISD::SHL; 734 if (const auto *Entry = 735 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 736 return LT.first * Entry->Cost; 737 } 738 739 static const CostTblEntry SSE2UniformShiftCostTable[] = { 740 // Uniform splats are cheaper for the following instructions. 741 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 742 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 743 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 744 745 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 746 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 747 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 748 749 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 750 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 751 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 752 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 753 }; 754 755 if (ST->hasSSE2() && 756 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 757 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 758 759 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 760 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 761 return LT.first * 4; // 2*psrad + shuffle. 762 763 if (const auto *Entry = 764 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 765 return LT.first * Entry->Cost; 766 } 767 768 if (ISD == ISD::SHL && 769 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 770 MVT VT = LT.second; 771 // Vector shift left by non uniform constant can be lowered 772 // into vector multiply. 773 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 774 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 775 ISD = ISD::MUL; 776 } 777 778 static const CostTblEntry AVX2CostTable[] = { 779 { ISD::SHL, MVT::v16i8, 6 }, // vpblendvb sequence. 780 { ISD::SHL, MVT::v32i8, 6 }, // vpblendvb sequence. 781 { ISD::SHL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 782 { ISD::SHL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 783 { ISD::SHL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 784 { ISD::SHL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 785 786 { ISD::SRL, MVT::v16i8, 6 }, // vpblendvb sequence. 787 { ISD::SRL, MVT::v32i8, 6 }, // vpblendvb sequence. 788 { ISD::SRL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 789 { ISD::SRL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 790 { ISD::SRL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 791 { ISD::SRL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 792 793 { ISD::SRA, MVT::v16i8, 17 }, // vpblendvb sequence. 794 { ISD::SRA, MVT::v32i8, 17 }, // vpblendvb sequence. 795 { ISD::SRA, MVT::v64i8, 34 }, // 2*vpblendvb sequence. 796 { ISD::SRA, MVT::v8i16, 5 }, // extend/vpsravd/pack sequence. 797 { ISD::SRA, MVT::v16i16, 7 }, // extend/vpsravd/pack sequence. 798 { ISD::SRA, MVT::v32i16, 14 }, // 2*extend/vpsravd/pack sequence. 799 { ISD::SRA, MVT::v2i64, 2 }, // srl/xor/sub sequence. 800 { ISD::SRA, MVT::v4i64, 2 }, // srl/xor/sub sequence. 801 802 { ISD::SUB, MVT::v32i8, 1 }, // psubb 803 { ISD::ADD, MVT::v32i8, 1 }, // paddb 804 { ISD::SUB, MVT::v16i16, 1 }, // psubw 805 { ISD::ADD, MVT::v16i16, 1 }, // paddw 806 { ISD::SUB, MVT::v8i32, 1 }, // psubd 807 { ISD::ADD, MVT::v8i32, 1 }, // paddd 808 { ISD::SUB, MVT::v4i64, 1 }, // psubq 809 { ISD::ADD, MVT::v4i64, 1 }, // paddq 810 811 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 812 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 813 { ISD::MUL, MVT::v4i64, 6 }, // 3*pmuludq/3*shift/2*add 814 815 { ISD::FNEG, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 816 { ISD::FNEG, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 817 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 818 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 819 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 820 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 821 { ISD::FMUL, MVT::f64, 1 }, // Haswell from http://www.agner.org/ 822 { ISD::FMUL, MVT::v2f64, 1 }, // Haswell from http://www.agner.org/ 823 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 824 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 825 826 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 827 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 828 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 829 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 830 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 831 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 832 }; 833 834 // Look for AVX2 lowering tricks for custom cases. 835 if (ST->hasAVX2()) 836 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 837 return LT.first * Entry->Cost; 838 839 static const CostTblEntry AVX1CostTable[] = { 840 // We don't have to scalarize unsupported ops. We can issue two half-sized 841 // operations and we only need to extract the upper YMM half. 842 // Two ops + 1 extract + 1 insert = 4. 843 { ISD::MUL, MVT::v16i16, 4 }, 844 { ISD::MUL, MVT::v8i32, 5 }, // BTVER2 from http://www.agner.org/ 845 { ISD::MUL, MVT::v4i64, 12 }, 846 847 { ISD::SUB, MVT::v32i8, 4 }, 848 { ISD::ADD, MVT::v32i8, 4 }, 849 { ISD::SUB, MVT::v16i16, 4 }, 850 { ISD::ADD, MVT::v16i16, 4 }, 851 { ISD::SUB, MVT::v8i32, 4 }, 852 { ISD::ADD, MVT::v8i32, 4 }, 853 { ISD::SUB, MVT::v4i64, 4 }, 854 { ISD::ADD, MVT::v4i64, 4 }, 855 856 { ISD::SHL, MVT::v16i8, 10 }, // pblendvb sequence . 857 { ISD::SHL, MVT::v32i8, 22 }, // pblendvb sequence + split. 858 { ISD::SHL, MVT::v8i16, 6 }, // pblendvb sequence. 859 { ISD::SHL, MVT::v16i16, 13 }, // pblendvb sequence + split. 860 { ISD::SHL, MVT::v4i32, 3 }, // pslld/paddd/cvttps2dq/pmulld 861 { ISD::SHL, MVT::v8i32, 9 }, // pslld/paddd/cvttps2dq/pmulld + split 862 { ISD::SHL, MVT::v2i64, 2 }, // Shift each lane + blend. 863 { ISD::SHL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 864 865 { ISD::SRL, MVT::v16i8, 11 }, // pblendvb sequence. 866 { ISD::SRL, MVT::v32i8, 23 }, // pblendvb sequence + split. 867 { ISD::SRL, MVT::v8i16, 13 }, // pblendvb sequence. 868 { ISD::SRL, MVT::v16i16, 28 }, // pblendvb sequence + split. 869 { ISD::SRL, MVT::v4i32, 6 }, // Shift each lane + blend. 870 { ISD::SRL, MVT::v8i32, 14 }, // Shift each lane + blend + split. 871 { ISD::SRL, MVT::v2i64, 2 }, // Shift each lane + blend. 872 { ISD::SRL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 873 874 { ISD::SRA, MVT::v16i8, 21 }, // pblendvb sequence. 875 { ISD::SRA, MVT::v32i8, 44 }, // pblendvb sequence + split. 876 { ISD::SRA, MVT::v8i16, 13 }, // pblendvb sequence. 877 { ISD::SRA, MVT::v16i16, 28 }, // pblendvb sequence + split. 878 { ISD::SRA, MVT::v4i32, 6 }, // Shift each lane + blend. 879 { ISD::SRA, MVT::v8i32, 14 }, // Shift each lane + blend + split. 880 { ISD::SRA, MVT::v2i64, 5 }, // Shift each lane + blend. 881 { ISD::SRA, MVT::v4i64, 12 }, // Shift each lane + blend + split. 882 883 { ISD::FNEG, MVT::v4f64, 2 }, // BTVER2 from http://www.agner.org/ 884 { ISD::FNEG, MVT::v8f32, 2 }, // BTVER2 from http://www.agner.org/ 885 886 { ISD::FMUL, MVT::f64, 2 }, // BTVER2 from http://www.agner.org/ 887 { ISD::FMUL, MVT::v2f64, 2 }, // BTVER2 from http://www.agner.org/ 888 { ISD::FMUL, MVT::v4f64, 4 }, // BTVER2 from http://www.agner.org/ 889 890 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 891 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 892 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 893 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 894 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 895 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 896 }; 897 898 if (ST->hasAVX()) 899 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 900 return LT.first * Entry->Cost; 901 902 static const CostTblEntry SSE42CostTable[] = { 903 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 904 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 905 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 906 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 907 908 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 909 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 910 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 911 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 912 913 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 914 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 915 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 916 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 917 918 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 919 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 920 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 921 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 922 923 { ISD::MUL, MVT::v2i64, 6 } // 3*pmuludq/3*shift/2*add 924 }; 925 926 if (ST->hasSSE42()) 927 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 928 return LT.first * Entry->Cost; 929 930 static const CostTblEntry SSE41CostTable[] = { 931 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 932 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 933 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 934 935 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 936 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 937 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 938 939 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 940 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 941 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 942 943 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 944 }; 945 946 if (ST->hasSSE41()) 947 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 948 return LT.first * Entry->Cost; 949 950 static const CostTblEntry SSE2CostTable[] = { 951 // We don't correctly identify costs of casts because they are marked as 952 // custom. 953 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 954 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 955 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 956 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 957 958 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 959 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 960 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 961 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 962 963 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 964 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 965 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 966 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 967 968 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 969 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 970 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 971 972 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 973 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 974 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 975 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 976 977 { ISD::FNEG, MVT::f32, 1 }, // Pentium IV from http://www.agner.org/ 978 { ISD::FNEG, MVT::f64, 1 }, // Pentium IV from http://www.agner.org/ 979 { ISD::FNEG, MVT::v4f32, 1 }, // Pentium IV from http://www.agner.org/ 980 { ISD::FNEG, MVT::v2f64, 1 }, // Pentium IV from http://www.agner.org/ 981 982 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 983 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 984 985 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 986 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 987 }; 988 989 if (ST->hasSSE2()) 990 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 991 return LT.first * Entry->Cost; 992 993 static const CostTblEntry SSE1CostTable[] = { 994 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 995 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 996 997 { ISD::FNEG, MVT::f32, 2 }, // Pentium III from http://www.agner.org/ 998 { ISD::FNEG, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 999 1000 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1001 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1002 1003 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1004 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1005 }; 1006 1007 if (ST->hasSSE1()) 1008 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 1009 return LT.first * Entry->Cost; 1010 1011 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 1012 { ISD::ADD, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1013 { ISD::SUB, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1014 }; 1015 1016 if (ST->is64Bit()) 1017 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, LT.second)) 1018 return LT.first * Entry->Cost; 1019 1020 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 1021 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1022 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1023 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1024 1025 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1026 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1027 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1028 }; 1029 1030 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, LT.second)) 1031 return LT.first * Entry->Cost; 1032 1033 // It is not a good idea to vectorize division. We have to scalarize it and 1034 // in the process we will often end up having to spilling regular 1035 // registers. The overhead of division is going to dominate most kernels 1036 // anyways so try hard to prevent vectorization of division - it is 1037 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 1038 // to hide "20 cycles" for each lane. 1039 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 1040 ISD == ISD::UDIV || ISD == ISD::UREM)) { 1041 InstructionCost ScalarCost = getArithmeticInstrCost( 1042 Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info, 1043 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 1044 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 1045 } 1046 1047 // Fallback to the default implementation. 1048 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info); 1049 } 1050 1051 InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, 1052 VectorType *BaseTp, 1053 ArrayRef<int> Mask, int Index, 1054 VectorType *SubTp) { 1055 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 1056 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 1057 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 1058 1059 Kind = improveShuffleKindFromMask(Kind, Mask); 1060 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 1061 if (Kind == TTI::SK_Transpose) 1062 Kind = TTI::SK_PermuteTwoSrc; 1063 1064 // For Broadcasts we are splatting the first element from the first input 1065 // register, so only need to reference that input and all the output 1066 // registers are the same. 1067 if (Kind == TTI::SK_Broadcast) 1068 LT.first = 1; 1069 1070 // Subvector extractions are free if they start at the beginning of a 1071 // vector and cheap if the subvectors are aligned. 1072 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 1073 int NumElts = LT.second.getVectorNumElements(); 1074 if ((Index % NumElts) == 0) 1075 return 0; 1076 std::pair<InstructionCost, MVT> SubLT = 1077 TLI->getTypeLegalizationCost(DL, SubTp); 1078 if (SubLT.second.isVector()) { 1079 int NumSubElts = SubLT.second.getVectorNumElements(); 1080 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1081 return SubLT.first; 1082 // Handle some cases for widening legalization. For now we only handle 1083 // cases where the original subvector was naturally aligned and evenly 1084 // fit in its legalized subvector type. 1085 // FIXME: Remove some of the alignment restrictions. 1086 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 1087 // vectors. 1088 int OrigSubElts = cast<FixedVectorType>(SubTp)->getNumElements(); 1089 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 1090 (NumSubElts % OrigSubElts) == 0 && 1091 LT.second.getVectorElementType() == 1092 SubLT.second.getVectorElementType() && 1093 LT.second.getVectorElementType().getSizeInBits() == 1094 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 1095 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 1096 "Unexpected number of elements!"); 1097 auto *VecTy = FixedVectorType::get(BaseTp->getElementType(), 1098 LT.second.getVectorNumElements()); 1099 auto *SubTy = FixedVectorType::get(BaseTp->getElementType(), 1100 SubLT.second.getVectorNumElements()); 1101 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 1102 InstructionCost ExtractCost = getShuffleCost( 1103 TTI::SK_ExtractSubvector, VecTy, None, ExtractIndex, SubTy); 1104 1105 // If the original size is 32-bits or more, we can use pshufd. Otherwise 1106 // if we have SSSE3 we can use pshufb. 1107 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 1108 return ExtractCost + 1; // pshufd or pshufb 1109 1110 assert(SubTp->getPrimitiveSizeInBits() == 16 && 1111 "Unexpected vector size"); 1112 1113 return ExtractCost + 2; // worst case pshufhw + pshufd 1114 } 1115 } 1116 } 1117 1118 // Subvector insertions are cheap if the subvectors are aligned. 1119 // Note that in general, the insertion starting at the beginning of a vector 1120 // isn't free, because we need to preserve the rest of the wide vector. 1121 if (Kind == TTI::SK_InsertSubvector && LT.second.isVector()) { 1122 int NumElts = LT.second.getVectorNumElements(); 1123 std::pair<InstructionCost, MVT> SubLT = 1124 TLI->getTypeLegalizationCost(DL, SubTp); 1125 if (SubLT.second.isVector()) { 1126 int NumSubElts = SubLT.second.getVectorNumElements(); 1127 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1128 return SubLT.first; 1129 } 1130 } 1131 1132 // Handle some common (illegal) sub-vector types as they are often very cheap 1133 // to shuffle even on targets without PSHUFB. 1134 EVT VT = TLI->getValueType(DL, BaseTp); 1135 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 1136 !ST->hasSSSE3()) { 1137 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 1138 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 1139 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1140 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1141 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1142 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1143 1144 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1145 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1146 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1147 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1148 1149 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1150 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1151 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1152 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1153 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1154 1155 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1156 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1157 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1158 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1159 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1160 }; 1161 1162 if (ST->hasSSE2()) 1163 if (const auto *Entry = 1164 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1165 return Entry->Cost; 1166 } 1167 1168 // We are going to permute multiple sources and the result will be in multiple 1169 // destinations. Providing an accurate cost only for splits where the element 1170 // type remains the same. 1171 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1172 MVT LegalVT = LT.second; 1173 if (LegalVT.isVector() && 1174 LegalVT.getVectorElementType().getSizeInBits() == 1175 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1176 LegalVT.getVectorNumElements() < 1177 cast<FixedVectorType>(BaseTp)->getNumElements()) { 1178 1179 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1180 unsigned LegalVTSize = LegalVT.getStoreSize(); 1181 // Number of source vectors after legalization: 1182 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1183 // Number of destination vectors after legalization: 1184 InstructionCost NumOfDests = LT.first; 1185 1186 auto *SingleOpTy = FixedVectorType::get(BaseTp->getElementType(), 1187 LegalVT.getVectorNumElements()); 1188 1189 InstructionCost NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1190 return NumOfShuffles * getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 1191 None, 0, nullptr); 1192 } 1193 1194 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1195 } 1196 1197 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1198 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1199 // We assume that source and destination have the same vector type. 1200 InstructionCost NumOfDests = LT.first; 1201 InstructionCost NumOfShufflesPerDest = LT.first * 2 - 1; 1202 LT.first = NumOfDests * NumOfShufflesPerDest; 1203 } 1204 1205 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1206 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1207 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1208 1209 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1210 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1211 1212 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b 1213 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b 1214 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2} // vpermt2b 1215 }; 1216 1217 if (ST->hasVBMI()) 1218 if (const auto *Entry = 1219 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1220 return LT.first * Entry->Cost; 1221 1222 static const CostTblEntry AVX512BWShuffleTbl[] = { 1223 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1224 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1225 1226 {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw 1227 {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw 1228 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1229 1230 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw 1231 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw 1232 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1233 1234 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w 1235 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w 1236 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2}, // vpermt2w 1237 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1238 1239 {TTI::SK_Select, MVT::v32i16, 1}, // vblendmw 1240 {TTI::SK_Select, MVT::v64i8, 1}, // vblendmb 1241 }; 1242 1243 if (ST->hasBWI()) 1244 if (const auto *Entry = 1245 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1246 return LT.first * Entry->Cost; 1247 1248 static const CostTblEntry AVX512ShuffleTbl[] = { 1249 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1250 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1251 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1252 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1253 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1254 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1255 1256 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1257 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1258 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1259 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1260 {TTI::SK_Reverse, MVT::v32i16, 7}, // per mca 1261 {TTI::SK_Reverse, MVT::v64i8, 7}, // per mca 1262 1263 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1264 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1265 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1266 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1267 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1268 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1269 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1270 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1271 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1272 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1273 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1274 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1275 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1276 1277 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1278 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1279 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1280 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1281 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1282 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1283 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1284 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1285 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1286 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1287 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1288 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1289 1290 // FIXME: This just applies the type legalization cost rules above 1291 // assuming these completely split. 1292 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1293 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1294 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1295 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1296 1297 {TTI::SK_Select, MVT::v32i16, 1}, // vpternlogq 1298 {TTI::SK_Select, MVT::v64i8, 1}, // vpternlogq 1299 {TTI::SK_Select, MVT::v8f64, 1}, // vblendmpd 1300 {TTI::SK_Select, MVT::v16f32, 1}, // vblendmps 1301 {TTI::SK_Select, MVT::v8i64, 1}, // vblendmq 1302 {TTI::SK_Select, MVT::v16i32, 1}, // vblendmd 1303 }; 1304 1305 if (ST->hasAVX512()) 1306 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1307 return LT.first * Entry->Cost; 1308 1309 static const CostTblEntry AVX2ShuffleTbl[] = { 1310 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1311 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1312 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1313 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1314 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1315 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1316 1317 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1318 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1319 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1320 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1321 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1322 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1323 1324 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1325 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1326 1327 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1328 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1329 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1330 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1331 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1332 // + vpblendvb 1333 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1334 // + vpblendvb 1335 1336 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1337 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1338 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1339 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1340 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1341 // + vpblendvb 1342 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1343 // + vpblendvb 1344 }; 1345 1346 if (ST->hasAVX2()) 1347 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1348 return LT.first * Entry->Cost; 1349 1350 static const CostTblEntry XOPShuffleTbl[] = { 1351 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1352 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1353 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1354 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1355 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1356 // + vinsertf128 1357 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1358 // + vinsertf128 1359 1360 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1361 // + vinsertf128 1362 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1363 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1364 // + vinsertf128 1365 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1366 }; 1367 1368 if (ST->hasXOP()) 1369 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1370 return LT.first * Entry->Cost; 1371 1372 static const CostTblEntry AVX1ShuffleTbl[] = { 1373 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1374 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1375 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1376 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1377 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1378 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1379 1380 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1381 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1382 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1383 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1384 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1385 // + vinsertf128 1386 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1387 // + vinsertf128 1388 1389 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1390 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1391 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1392 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1393 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1394 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1395 1396 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1397 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1398 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1399 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1400 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1401 // + 2*por + vinsertf128 1402 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1403 // + 2*por + vinsertf128 1404 1405 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1406 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1407 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1408 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1409 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1410 // + 4*por + vinsertf128 1411 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1412 // + 4*por + vinsertf128 1413 }; 1414 1415 if (ST->hasAVX()) 1416 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1417 return LT.first * Entry->Cost; 1418 1419 static const CostTblEntry SSE41ShuffleTbl[] = { 1420 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1421 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1422 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1423 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1424 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1425 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1426 }; 1427 1428 if (ST->hasSSE41()) 1429 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1430 return LT.first * Entry->Cost; 1431 1432 static const CostTblEntry SSSE3ShuffleTbl[] = { 1433 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1434 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1435 1436 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1437 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1438 1439 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1440 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1441 1442 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1443 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1444 1445 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1446 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1447 }; 1448 1449 if (ST->hasSSSE3()) 1450 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1451 return LT.first * Entry->Cost; 1452 1453 static const CostTblEntry SSE2ShuffleTbl[] = { 1454 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1455 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1456 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1457 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1458 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1459 1460 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1461 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1462 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1463 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1464 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1465 // + 2*pshufd + 2*unpck + packus 1466 1467 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1468 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1469 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1470 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1471 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1472 1473 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1474 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1475 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1476 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1477 // + pshufd/unpck 1478 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1479 // + 2*pshufd + 2*unpck + 2*packus 1480 1481 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1482 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1483 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1484 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1485 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1486 }; 1487 1488 if (ST->hasSSE2()) 1489 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1490 return LT.first * Entry->Cost; 1491 1492 static const CostTblEntry SSE1ShuffleTbl[] = { 1493 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1494 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1495 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1496 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1497 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1498 }; 1499 1500 if (ST->hasSSE1()) 1501 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1502 return LT.first * Entry->Cost; 1503 1504 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1505 } 1506 1507 InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, 1508 Type *Src, 1509 TTI::CastContextHint CCH, 1510 TTI::TargetCostKind CostKind, 1511 const Instruction *I) { 1512 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1513 assert(ISD && "Invalid opcode"); 1514 1515 // TODO: Allow non-throughput costs that aren't binary. 1516 auto AdjustCost = [&CostKind](InstructionCost Cost) -> InstructionCost { 1517 if (CostKind != TTI::TCK_RecipThroughput) 1518 return Cost == 0 ? 0 : 1; 1519 return Cost; 1520 }; 1521 1522 // The cost tables include both specific, custom (non-legal) src/dst type 1523 // conversions and generic, legalized types. We test for customs first, before 1524 // falling back to legalization. 1525 // FIXME: Need a better design of the cost table to handle non-simple types of 1526 // potential massive combinations (elem_num x src_type x dst_type). 1527 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1528 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1529 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1530 1531 // Mask sign extend has an instruction. 1532 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1533 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1534 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1535 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1536 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1537 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1538 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1539 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1540 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1541 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1542 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1543 1544 // Mask zero extend is a sext + shift. 1545 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1546 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1547 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1548 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1549 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1550 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1551 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1552 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1553 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1554 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1555 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1556 1557 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, 1558 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm 1559 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // widen to zmm 1560 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // widen to zmm 1561 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // vpmovwb 1562 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // widen to zmm 1563 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // widen to zmm 1564 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // vpmovwb 1565 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // widen to zmm 1566 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // widen to zmm 1567 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // vpmovwb 1568 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // widen to zmm 1569 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // widen to zmm 1570 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // widen to zmm 1571 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, 1572 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, 1573 }; 1574 1575 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1576 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1577 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1578 1579 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1580 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1581 1582 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1583 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1584 1585 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1586 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1587 }; 1588 1589 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1590 // 256-bit wide vectors. 1591 1592 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1593 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1594 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1595 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1596 1597 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1598 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1599 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1600 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd 1601 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1602 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1603 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1604 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd 1605 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd 1606 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd 1607 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd 1608 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd 1609 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq 1610 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq 1611 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq 1612 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 2 }, // vpmovdb 1613 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 2 }, // vpmovdb 1614 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, // vpmovdb 1615 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, // vpmovdb 1616 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 2 }, // vpmovqb 1617 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 1 }, // vpshufb 1618 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, // vpmovqb 1619 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, // vpmovqw 1620 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, // vpmovqd 1621 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd 1622 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb 1623 1624 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32 1625 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, 1626 1627 // Sign extend is zmm vpternlogd+vptruncdb. 1628 // Zero extend is zmm broadcast load+vptruncdw. 1629 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 }, 1630 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 }, 1631 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, 1632 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, 1633 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, 1634 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, 1635 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 }, 1636 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 }, 1637 1638 // Sign extend is zmm vpternlogd+vptruncdw. 1639 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw. 1640 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 }, 1641 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1642 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 }, 1643 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1644 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 }, 1645 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1646 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 }, 1647 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1648 1649 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd 1650 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld 1651 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd 1652 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld 1653 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd 1654 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld 1655 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq 1656 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq 1657 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq 1658 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq 1659 1660 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd 1661 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld 1662 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq 1663 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq 1664 1665 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1666 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1667 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1668 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1669 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1670 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1671 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1672 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1673 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1674 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1675 1676 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1677 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1678 1679 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1680 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1681 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, 1682 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, 1683 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1684 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, 1685 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1686 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1687 1688 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1689 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1690 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, 1691 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, 1692 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1693 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, 1694 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1695 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1696 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1697 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1698 1699 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2 }, 1700 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f64, 7 }, 1701 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f64,15 }, 1702 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f32,11 }, 1703 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f64,31 }, 1704 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, 1705 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f64, 7 }, 1706 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f32, 5 }, 1707 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f64,15 }, 1708 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 1 }, 1709 { ISD::FP_TO_SINT, MVT::v16i32, MVT::v16f64, 3 }, 1710 1711 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1712 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, 1713 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, 1714 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1715 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, 1716 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, 1717 }; 1718 1719 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1720 // Mask sign extend has an instruction. 1721 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1722 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1723 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1724 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1725 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1726 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1727 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1728 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1729 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1730 1731 // Mask zero extend is a sext + shift. 1732 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1733 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1734 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1735 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1736 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1737 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1738 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1739 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1740 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1741 1742 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, 1743 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // vpsllw+vptestmb 1744 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // vpsllw+vptestmw 1745 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // vpsllw+vptestmb 1746 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // vpsllw+vptestmw 1747 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // vpsllw+vptestmb 1748 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // vpsllw+vptestmw 1749 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // vpsllw+vptestmb 1750 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // vpsllw+vptestmw 1751 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // vpsllw+vptestmb 1752 }; 1753 1754 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1755 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1756 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1757 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1758 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1759 1760 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1761 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1762 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1763 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1764 1765 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v4f32, 1 }, 1766 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1767 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1768 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1769 1770 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v4f32, 1 }, 1771 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1772 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1773 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1774 }; 1775 1776 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 1777 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1778 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1779 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1780 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 8 }, // split+2*v8i8 1781 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1782 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1783 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1784 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16 1785 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // vpslld+vptestmd 1786 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd 1787 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // vpslld+vptestmd 1788 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // vpsllq+vptestmq 1789 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // vpsllq+vptestmq 1790 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // vpmovqd 1791 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, // vpmovqb 1792 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, // vpmovqw 1793 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, // vpmovwb 1794 1795 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb 1796 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb 1797 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 }, 1798 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 }, 1799 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 }, 1800 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 }, 1801 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 }, 1802 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 }, 1803 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 }, 1804 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 }, 1805 1806 // sign extend is vpcmpeq+maskedmove+vpmovdw 1807 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw 1808 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1809 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 }, 1810 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1811 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 }, 1812 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1813 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 }, 1814 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 }, 1815 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 }, 1816 1817 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd 1818 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld 1819 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd 1820 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld 1821 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd 1822 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld 1823 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq 1824 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq 1825 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq 1826 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq 1827 1828 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 1 }, 1829 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 1 }, 1830 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 1 }, 1831 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 1 }, 1832 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1833 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1834 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 1 }, 1835 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 1 }, 1836 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1837 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1838 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1839 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1840 1841 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 1842 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 1 }, 1843 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 1844 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 1 }, 1845 1846 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 1847 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1848 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 1849 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 1 }, 1850 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 1851 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 1 }, 1852 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 1853 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1854 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1855 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1856 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1857 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1858 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1859 1860 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v8f32, 2 }, 1861 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2 }, 1862 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f32, 5 }, 1863 1864 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 1865 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 1866 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1867 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 1 }, 1868 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1869 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1870 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1871 }; 1872 1873 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1874 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1875 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1876 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1877 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1878 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1879 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1880 1881 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 2 }, 1882 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 2 }, 1883 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 2 }, 1884 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 2 }, 1885 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1886 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1887 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 2 }, 1888 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 2 }, 1889 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1890 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1891 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1892 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1893 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1894 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1895 1896 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1897 1898 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i16, 1 }, 1899 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 1 }, 1900 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 1 }, 1901 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i32, 4 }, 1902 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i64, 4 }, 1903 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 1 }, 1904 { ISD::TRUNCATE, MVT::v8i16, MVT::v2i64, 1 }, 1905 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i64, 5 }, 1906 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, 1907 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1908 1909 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1910 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1911 1912 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v8f32, 1 }, 1913 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 1 }, 1914 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 1 }, 1915 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 3 }, 1916 1917 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v8f32, 1 }, 1918 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 4 }, 1919 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 7 }, 1920 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 7 }, 1921 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 4 }, 1922 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v4f64, 7 }, 1923 1924 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 2 }, 1925 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 2 }, 1926 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 2 }, 1927 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1928 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1929 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1930 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 3 }, 1931 1932 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 2 }, 1933 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 2 }, 1934 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 2 }, 1935 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1936 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1937 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1938 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 2 }, 1939 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 1940 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 1941 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 }, 1942 }; 1943 1944 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1945 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1946 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1947 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1948 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1949 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1950 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1951 1952 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 3 }, 1953 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 3 }, 1954 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 3 }, 1955 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 3 }, 1956 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1957 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1958 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 3 }, 1959 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 3 }, 1960 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1961 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1962 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1963 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1964 1965 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 4 }, 1966 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 5 }, 1967 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 4 }, 1968 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 9 }, 1969 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, 11 }, 1970 1971 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // and+extract+packuswb 1972 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i32, 5 }, 1973 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1974 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i64, 5 }, 1975 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i64, 3 }, // and+extract+2*packusdw 1976 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1977 1978 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1979 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1980 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1981 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 4 }, 1982 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v16i8, 2 }, 1983 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 1984 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v8i16, 2 }, 1985 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 1986 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 1987 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 }, 1988 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 5 }, 1989 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 8 }, 1990 1991 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1992 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1993 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1994 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 4 }, 1995 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v16i8, 2 }, 1996 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 1997 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v8i16, 2 }, 1998 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 4 }, 1999 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 4 }, 2000 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 2001 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 2002 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 2003 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 10 }, 2004 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 10 }, 2005 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 18 }, 2006 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 2007 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 10 }, 2008 2009 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v8f32, 2 }, 2010 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f64, 2 }, 2011 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v8f32, 2 }, 2012 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v4f64, 2 }, 2013 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 2 }, 2014 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f64, 2 }, 2015 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v8f32, 2 }, 2016 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v4f64, 2 }, 2017 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 2 }, 2018 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 2 }, 2019 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 5 }, 2020 2021 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v8f32, 2 }, 2022 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f64, 2 }, 2023 { ISD::FP_TO_UINT, MVT::v32i8, MVT::v8f32, 2 }, 2024 { ISD::FP_TO_UINT, MVT::v32i8, MVT::v4f64, 2 }, 2025 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 2 }, 2026 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f64, 2 }, 2027 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v8f32, 2 }, 2028 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v4f64, 2 }, 2029 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 9 }, 2030 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 9 }, 2031 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 9 }, 2032 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v4f64, 9 }, 2033 2034 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 2035 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 2036 }; 2037 2038 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 2039 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8, 1 }, 2040 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8, 1 }, 2041 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8, 1 }, 2042 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8, 1 }, 2043 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2044 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2045 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16, 1 }, 2046 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16, 1 }, 2047 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2048 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2049 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2050 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2051 2052 // These truncates end up widening elements. 2053 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 1 }, // PMOVXZBQ 2054 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 1 }, // PMOVXZWQ 2055 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 1 }, // PMOVXZBD 2056 2057 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 2 }, 2058 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 2 }, 2059 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 2 }, 2060 2061 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 1 }, 2062 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 1 }, 2063 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 1 }, 2064 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 1 }, 2065 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 1 }, 2066 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2067 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 1 }, 2068 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2069 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 2070 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 1 }, 2071 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2072 2073 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 1 }, 2074 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 1 }, 2075 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 2076 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 2077 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 1 }, 2078 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2079 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 1 }, 2080 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2081 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 3 }, 2082 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 3 }, 2083 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 2 }, 2084 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 12 }, 2085 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 22 }, 2086 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 4 }, 2087 2088 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 1 }, 2089 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 1 }, 2090 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 1 }, 2091 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 1 }, 2092 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f32, 2 }, 2093 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v2f64, 2 }, 2094 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f32, 1 }, 2095 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v2f64, 1 }, 2096 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, 2097 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v2f64, 1 }, 2098 2099 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 1 }, 2100 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 5 }, 2101 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 1 }, 2102 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 5 }, 2103 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f32, 2 }, 2104 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v2f64, 2 }, 2105 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f32, 1 }, 2106 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v2f64, 1 }, 2107 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 6 }, 2108 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 3 }, 2109 }; 2110 2111 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 2112 // These are somewhat magic numbers justified by comparing the 2113 // output of llvm-mca for our various supported scheduler models 2114 // and basing it off the worst case scenario. 2115 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 3 }, 2116 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 3 }, 2117 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 3 }, 2118 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 3 }, 2119 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 3 }, 2120 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 4 }, 2121 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 3 }, 2122 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 4 }, 2123 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 3 }, 2124 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4 }, 2125 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 8 }, 2126 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 8 }, 2127 2128 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 3 }, 2129 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 3 }, 2130 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 8 }, 2131 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 9 }, 2132 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 4 }, 2133 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 4 }, 2134 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 4 }, 2135 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 4 }, 2136 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 7 }, 2137 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 7 }, 2138 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 2139 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 15 }, 2140 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 18 }, 2141 2142 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 4 }, 2143 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 4 }, 2144 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 4 }, 2145 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 4 }, 2146 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f32, 6 }, 2147 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v2f64, 6 }, 2148 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f32, 5 }, 2149 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v2f64, 5 }, 2150 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 4 }, 2151 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v2f64, 4 }, 2152 2153 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 4 }, 2154 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 2155 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 4 }, 2156 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 15 }, 2157 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f32, 6 }, 2158 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v2f64, 6 }, 2159 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f32, 5 }, 2160 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v2f64, 5 }, 2161 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 8 }, 2162 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 8 }, 2163 2164 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8, 4 }, 2165 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8, 4 }, 2166 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8, 2 }, 2167 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8, 3 }, 2168 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2169 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8, 2 }, 2170 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16, 2 }, 2171 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16, 3 }, 2172 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2173 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16, 2 }, 2174 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2175 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32, 2 }, 2176 2177 // These truncates are really widening elements. 2178 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 1 }, // PSHUFD 2179 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // PUNPCKLWD+DQ 2180 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // PUNPCKLBW+WD+PSHUFD 2181 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 1 }, // PUNPCKLWD 2182 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // PUNPCKLBW+WD 2183 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 1 }, // PUNPCKLBW 2184 2185 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i16, 2 }, // PAND+PACKUSWB 2186 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 2187 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 3 }, // PAND+2*PACKUSWB 2188 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 2189 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 2190 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 3 }, 2191 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2192 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32,10 }, 2193 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 2194 { ISD::TRUNCATE, MVT::v8i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 2195 { ISD::TRUNCATE, MVT::v4i32, MVT::v2i64, 1 }, // PSHUFD 2196 }; 2197 2198 // Attempt to map directly to (simple) MVT types to let us match custom entries. 2199 EVT SrcTy = TLI->getValueType(DL, Src); 2200 EVT DstTy = TLI->getValueType(DL, Dst); 2201 2202 // The function getSimpleVT only handles simple value types. 2203 if (SrcTy.isSimple() && DstTy.isSimple()) { 2204 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 2205 MVT SimpleDstTy = DstTy.getSimpleVT(); 2206 2207 if (ST->useAVX512Regs()) { 2208 if (ST->hasBWI()) 2209 if (const auto *Entry = ConvertCostTableLookup( 2210 AVX512BWConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2211 return AdjustCost(Entry->Cost); 2212 2213 if (ST->hasDQI()) 2214 if (const auto *Entry = ConvertCostTableLookup( 2215 AVX512DQConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2216 return AdjustCost(Entry->Cost); 2217 2218 if (ST->hasAVX512()) 2219 if (const auto *Entry = ConvertCostTableLookup( 2220 AVX512FConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2221 return AdjustCost(Entry->Cost); 2222 } 2223 2224 if (ST->hasBWI()) 2225 if (const auto *Entry = ConvertCostTableLookup( 2226 AVX512BWVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2227 return AdjustCost(Entry->Cost); 2228 2229 if (ST->hasDQI()) 2230 if (const auto *Entry = ConvertCostTableLookup( 2231 AVX512DQVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2232 return AdjustCost(Entry->Cost); 2233 2234 if (ST->hasAVX512()) 2235 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2236 SimpleDstTy, SimpleSrcTy)) 2237 return AdjustCost(Entry->Cost); 2238 2239 if (ST->hasAVX2()) { 2240 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2241 SimpleDstTy, SimpleSrcTy)) 2242 return AdjustCost(Entry->Cost); 2243 } 2244 2245 if (ST->hasAVX()) { 2246 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2247 SimpleDstTy, SimpleSrcTy)) 2248 return AdjustCost(Entry->Cost); 2249 } 2250 2251 if (ST->hasSSE41()) { 2252 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2253 SimpleDstTy, SimpleSrcTy)) 2254 return AdjustCost(Entry->Cost); 2255 } 2256 2257 if (ST->hasSSE2()) { 2258 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2259 SimpleDstTy, SimpleSrcTy)) 2260 return AdjustCost(Entry->Cost); 2261 } 2262 } 2263 2264 // Fall back to legalized types. 2265 std::pair<InstructionCost, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 2266 std::pair<InstructionCost, MVT> LTDest = 2267 TLI->getTypeLegalizationCost(DL, Dst); 2268 2269 if (ST->useAVX512Regs()) { 2270 if (ST->hasBWI()) 2271 if (const auto *Entry = ConvertCostTableLookup( 2272 AVX512BWConversionTbl, ISD, LTDest.second, LTSrc.second)) 2273 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2274 2275 if (ST->hasDQI()) 2276 if (const auto *Entry = ConvertCostTableLookup( 2277 AVX512DQConversionTbl, ISD, LTDest.second, LTSrc.second)) 2278 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2279 2280 if (ST->hasAVX512()) 2281 if (const auto *Entry = ConvertCostTableLookup( 2282 AVX512FConversionTbl, ISD, LTDest.second, LTSrc.second)) 2283 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2284 } 2285 2286 if (ST->hasBWI()) 2287 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 2288 LTDest.second, LTSrc.second)) 2289 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2290 2291 if (ST->hasDQI()) 2292 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 2293 LTDest.second, LTSrc.second)) 2294 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2295 2296 if (ST->hasAVX512()) 2297 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2298 LTDest.second, LTSrc.second)) 2299 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2300 2301 if (ST->hasAVX2()) 2302 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2303 LTDest.second, LTSrc.second)) 2304 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2305 2306 if (ST->hasAVX()) 2307 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2308 LTDest.second, LTSrc.second)) 2309 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2310 2311 if (ST->hasSSE41()) 2312 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2313 LTDest.second, LTSrc.second)) 2314 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2315 2316 if (ST->hasSSE2()) 2317 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2318 LTDest.second, LTSrc.second)) 2319 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2320 2321 // Fallback, for i8/i16 sitofp/uitofp cases we need to extend to i32 for 2322 // sitofp. 2323 if ((ISD == ISD::SINT_TO_FP || ISD == ISD::UINT_TO_FP) && 2324 1 < Src->getScalarSizeInBits() && Src->getScalarSizeInBits() < 32) { 2325 Type *ExtSrc = Src->getWithNewBitWidth(32); 2326 unsigned ExtOpc = 2327 (ISD == ISD::SINT_TO_FP) ? Instruction::SExt : Instruction::ZExt; 2328 2329 // For scalar loads the extend would be free. 2330 InstructionCost ExtCost = 0; 2331 if (!(Src->isIntegerTy() && I && isa<LoadInst>(I->getOperand(0)))) 2332 ExtCost = getCastInstrCost(ExtOpc, ExtSrc, Src, CCH, CostKind); 2333 2334 return ExtCost + getCastInstrCost(Instruction::SIToFP, Dst, ExtSrc, 2335 TTI::CastContextHint::None, CostKind); 2336 } 2337 2338 // Fallback for fptosi/fptoui i8/i16 cases we need to truncate from fptosi 2339 // i32. 2340 if ((ISD == ISD::FP_TO_SINT || ISD == ISD::FP_TO_UINT) && 2341 1 < Dst->getScalarSizeInBits() && Dst->getScalarSizeInBits() < 32) { 2342 Type *TruncDst = Dst->getWithNewBitWidth(32); 2343 return getCastInstrCost(Instruction::FPToSI, TruncDst, Src, CCH, CostKind) + 2344 getCastInstrCost(Instruction::Trunc, Dst, TruncDst, 2345 TTI::CastContextHint::None, CostKind); 2346 } 2347 2348 return AdjustCost( 2349 BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I)); 2350 } 2351 2352 InstructionCost X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 2353 Type *CondTy, 2354 CmpInst::Predicate VecPred, 2355 TTI::TargetCostKind CostKind, 2356 const Instruction *I) { 2357 // TODO: Handle other cost kinds. 2358 if (CostKind != TTI::TCK_RecipThroughput) 2359 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, 2360 I); 2361 2362 // Legalize the type. 2363 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2364 2365 MVT MTy = LT.second; 2366 2367 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2368 assert(ISD && "Invalid opcode"); 2369 2370 unsigned ExtraCost = 0; 2371 if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) { 2372 // Some vector comparison predicates cost extra instructions. 2373 if (MTy.isVector() && 2374 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 2375 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 2376 ST->hasBWI())) { 2377 switch (cast<CmpInst>(I)->getPredicate()) { 2378 case CmpInst::Predicate::ICMP_NE: 2379 // xor(cmpeq(x,y),-1) 2380 ExtraCost = 1; 2381 break; 2382 case CmpInst::Predicate::ICMP_SGE: 2383 case CmpInst::Predicate::ICMP_SLE: 2384 // xor(cmpgt(x,y),-1) 2385 ExtraCost = 1; 2386 break; 2387 case CmpInst::Predicate::ICMP_ULT: 2388 case CmpInst::Predicate::ICMP_UGT: 2389 // cmpgt(xor(x,signbit),xor(y,signbit)) 2390 // xor(cmpeq(pmaxu(x,y),x),-1) 2391 ExtraCost = 2; 2392 break; 2393 case CmpInst::Predicate::ICMP_ULE: 2394 case CmpInst::Predicate::ICMP_UGE: 2395 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 2396 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 2397 // cmpeq(psubus(x,y),0) 2398 // cmpeq(pminu(x,y),x) 2399 ExtraCost = 1; 2400 } else { 2401 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 2402 ExtraCost = 3; 2403 } 2404 break; 2405 default: 2406 break; 2407 } 2408 } 2409 } 2410 2411 static const CostTblEntry SLMCostTbl[] = { 2412 // slm pcmpeq/pcmpgt throughput is 2 2413 { ISD::SETCC, MVT::v2i64, 2 }, 2414 }; 2415 2416 static const CostTblEntry AVX512BWCostTbl[] = { 2417 { ISD::SETCC, MVT::v32i16, 1 }, 2418 { ISD::SETCC, MVT::v64i8, 1 }, 2419 2420 { ISD::SELECT, MVT::v32i16, 1 }, 2421 { ISD::SELECT, MVT::v64i8, 1 }, 2422 }; 2423 2424 static const CostTblEntry AVX512CostTbl[] = { 2425 { ISD::SETCC, MVT::v8i64, 1 }, 2426 { ISD::SETCC, MVT::v16i32, 1 }, 2427 { ISD::SETCC, MVT::v8f64, 1 }, 2428 { ISD::SETCC, MVT::v16f32, 1 }, 2429 2430 { ISD::SELECT, MVT::v8i64, 1 }, 2431 { ISD::SELECT, MVT::v16i32, 1 }, 2432 { ISD::SELECT, MVT::v8f64, 1 }, 2433 { ISD::SELECT, MVT::v16f32, 1 }, 2434 2435 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 2436 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 2437 2438 { ISD::SELECT, MVT::v32i16, 2 }, // FIXME: should be 3 2439 { ISD::SELECT, MVT::v64i8, 2 }, // FIXME: should be 3 2440 }; 2441 2442 static const CostTblEntry AVX2CostTbl[] = { 2443 { ISD::SETCC, MVT::v4i64, 1 }, 2444 { ISD::SETCC, MVT::v8i32, 1 }, 2445 { ISD::SETCC, MVT::v16i16, 1 }, 2446 { ISD::SETCC, MVT::v32i8, 1 }, 2447 2448 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 2449 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 2450 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 2451 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 2452 }; 2453 2454 static const CostTblEntry AVX1CostTbl[] = { 2455 { ISD::SETCC, MVT::v4f64, 1 }, 2456 { ISD::SETCC, MVT::v8f32, 1 }, 2457 // AVX1 does not support 8-wide integer compare. 2458 { ISD::SETCC, MVT::v4i64, 4 }, 2459 { ISD::SETCC, MVT::v8i32, 4 }, 2460 { ISD::SETCC, MVT::v16i16, 4 }, 2461 { ISD::SETCC, MVT::v32i8, 4 }, 2462 2463 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 2464 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 2465 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 2466 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 2467 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 2468 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 2469 }; 2470 2471 static const CostTblEntry SSE42CostTbl[] = { 2472 { ISD::SETCC, MVT::v2f64, 1 }, 2473 { ISD::SETCC, MVT::v4f32, 1 }, 2474 { ISD::SETCC, MVT::v2i64, 1 }, 2475 }; 2476 2477 static const CostTblEntry SSE41CostTbl[] = { 2478 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 2479 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 2480 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 2481 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 2482 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 2483 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 2484 }; 2485 2486 static const CostTblEntry SSE2CostTbl[] = { 2487 { ISD::SETCC, MVT::v2f64, 2 }, 2488 { ISD::SETCC, MVT::f64, 1 }, 2489 { ISD::SETCC, MVT::v2i64, 8 }, 2490 { ISD::SETCC, MVT::v4i32, 1 }, 2491 { ISD::SETCC, MVT::v8i16, 1 }, 2492 { ISD::SETCC, MVT::v16i8, 1 }, 2493 2494 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 2495 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 2496 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 2497 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 2498 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 2499 }; 2500 2501 static const CostTblEntry SSE1CostTbl[] = { 2502 { ISD::SETCC, MVT::v4f32, 2 }, 2503 { ISD::SETCC, MVT::f32, 1 }, 2504 2505 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 2506 }; 2507 2508 if (ST->isSLM()) 2509 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2510 return LT.first * (ExtraCost + Entry->Cost); 2511 2512 if (ST->hasBWI()) 2513 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2514 return LT.first * (ExtraCost + Entry->Cost); 2515 2516 if (ST->hasAVX512()) 2517 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2518 return LT.first * (ExtraCost + Entry->Cost); 2519 2520 if (ST->hasAVX2()) 2521 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2522 return LT.first * (ExtraCost + Entry->Cost); 2523 2524 if (ST->hasAVX()) 2525 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2526 return LT.first * (ExtraCost + Entry->Cost); 2527 2528 if (ST->hasSSE42()) 2529 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2530 return LT.first * (ExtraCost + Entry->Cost); 2531 2532 if (ST->hasSSE41()) 2533 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2534 return LT.first * (ExtraCost + Entry->Cost); 2535 2536 if (ST->hasSSE2()) 2537 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2538 return LT.first * (ExtraCost + Entry->Cost); 2539 2540 if (ST->hasSSE1()) 2541 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2542 return LT.first * (ExtraCost + Entry->Cost); 2543 2544 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I); 2545 } 2546 2547 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2548 2549 InstructionCost 2550 X86TTIImpl::getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 2551 TTI::TargetCostKind CostKind) { 2552 2553 // Costs should match the codegen from: 2554 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2555 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2556 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2557 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2558 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2559 2560 // TODO: Overflow intrinsics (*ADDO, *SUBO, *MULO) with vector types are not 2561 // specialized in these tables yet. 2562 static const CostTblEntry AVX512CDCostTbl[] = { 2563 { ISD::CTLZ, MVT::v8i64, 1 }, 2564 { ISD::CTLZ, MVT::v16i32, 1 }, 2565 { ISD::CTLZ, MVT::v32i16, 8 }, 2566 { ISD::CTLZ, MVT::v64i8, 20 }, 2567 { ISD::CTLZ, MVT::v4i64, 1 }, 2568 { ISD::CTLZ, MVT::v8i32, 1 }, 2569 { ISD::CTLZ, MVT::v16i16, 4 }, 2570 { ISD::CTLZ, MVT::v32i8, 10 }, 2571 { ISD::CTLZ, MVT::v2i64, 1 }, 2572 { ISD::CTLZ, MVT::v4i32, 1 }, 2573 { ISD::CTLZ, MVT::v8i16, 4 }, 2574 { ISD::CTLZ, MVT::v16i8, 4 }, 2575 }; 2576 static const CostTblEntry AVX512BWCostTbl[] = { 2577 { ISD::ABS, MVT::v32i16, 1 }, 2578 { ISD::ABS, MVT::v64i8, 1 }, 2579 { ISD::BITREVERSE, MVT::v8i64, 5 }, 2580 { ISD::BITREVERSE, MVT::v16i32, 5 }, 2581 { ISD::BITREVERSE, MVT::v32i16, 5 }, 2582 { ISD::BITREVERSE, MVT::v64i8, 5 }, 2583 { ISD::BSWAP, MVT::v8i64, 1 }, 2584 { ISD::BSWAP, MVT::v16i32, 1 }, 2585 { ISD::BSWAP, MVT::v32i16, 1 }, 2586 { ISD::CTLZ, MVT::v8i64, 23 }, 2587 { ISD::CTLZ, MVT::v16i32, 22 }, 2588 { ISD::CTLZ, MVT::v32i16, 18 }, 2589 { ISD::CTLZ, MVT::v64i8, 17 }, 2590 { ISD::CTPOP, MVT::v8i64, 7 }, 2591 { ISD::CTPOP, MVT::v16i32, 11 }, 2592 { ISD::CTPOP, MVT::v32i16, 9 }, 2593 { ISD::CTPOP, MVT::v64i8, 6 }, 2594 { ISD::CTTZ, MVT::v8i64, 10 }, 2595 { ISD::CTTZ, MVT::v16i32, 14 }, 2596 { ISD::CTTZ, MVT::v32i16, 12 }, 2597 { ISD::CTTZ, MVT::v64i8, 9 }, 2598 { ISD::SADDSAT, MVT::v32i16, 1 }, 2599 { ISD::SADDSAT, MVT::v64i8, 1 }, 2600 { ISD::SMAX, MVT::v32i16, 1 }, 2601 { ISD::SMAX, MVT::v64i8, 1 }, 2602 { ISD::SMIN, MVT::v32i16, 1 }, 2603 { ISD::SMIN, MVT::v64i8, 1 }, 2604 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2605 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2606 { ISD::UADDSAT, MVT::v32i16, 1 }, 2607 { ISD::UADDSAT, MVT::v64i8, 1 }, 2608 { ISD::UMAX, MVT::v32i16, 1 }, 2609 { ISD::UMAX, MVT::v64i8, 1 }, 2610 { ISD::UMIN, MVT::v32i16, 1 }, 2611 { ISD::UMIN, MVT::v64i8, 1 }, 2612 { ISD::USUBSAT, MVT::v32i16, 1 }, 2613 { ISD::USUBSAT, MVT::v64i8, 1 }, 2614 }; 2615 static const CostTblEntry AVX512CostTbl[] = { 2616 { ISD::ABS, MVT::v8i64, 1 }, 2617 { ISD::ABS, MVT::v16i32, 1 }, 2618 { ISD::ABS, MVT::v32i16, 2 }, // FIXME: include split 2619 { ISD::ABS, MVT::v64i8, 2 }, // FIXME: include split 2620 { ISD::ABS, MVT::v4i64, 1 }, 2621 { ISD::ABS, MVT::v2i64, 1 }, 2622 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2623 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2624 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2625 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2626 { ISD::BSWAP, MVT::v8i64, 4 }, 2627 { ISD::BSWAP, MVT::v16i32, 4 }, 2628 { ISD::BSWAP, MVT::v32i16, 4 }, 2629 { ISD::CTLZ, MVT::v8i64, 29 }, 2630 { ISD::CTLZ, MVT::v16i32, 35 }, 2631 { ISD::CTLZ, MVT::v32i16, 28 }, 2632 { ISD::CTLZ, MVT::v64i8, 18 }, 2633 { ISD::CTPOP, MVT::v8i64, 16 }, 2634 { ISD::CTPOP, MVT::v16i32, 24 }, 2635 { ISD::CTPOP, MVT::v32i16, 18 }, 2636 { ISD::CTPOP, MVT::v64i8, 12 }, 2637 { ISD::CTTZ, MVT::v8i64, 20 }, 2638 { ISD::CTTZ, MVT::v16i32, 28 }, 2639 { ISD::CTTZ, MVT::v32i16, 24 }, 2640 { ISD::CTTZ, MVT::v64i8, 18 }, 2641 { ISD::SMAX, MVT::v8i64, 1 }, 2642 { ISD::SMAX, MVT::v16i32, 1 }, 2643 { ISD::SMAX, MVT::v32i16, 2 }, // FIXME: include split 2644 { ISD::SMAX, MVT::v64i8, 2 }, // FIXME: include split 2645 { ISD::SMAX, MVT::v4i64, 1 }, 2646 { ISD::SMAX, MVT::v2i64, 1 }, 2647 { ISD::SMIN, MVT::v8i64, 1 }, 2648 { ISD::SMIN, MVT::v16i32, 1 }, 2649 { ISD::SMIN, MVT::v32i16, 2 }, // FIXME: include split 2650 { ISD::SMIN, MVT::v64i8, 2 }, // FIXME: include split 2651 { ISD::SMIN, MVT::v4i64, 1 }, 2652 { ISD::SMIN, MVT::v2i64, 1 }, 2653 { ISD::UMAX, MVT::v8i64, 1 }, 2654 { ISD::UMAX, MVT::v16i32, 1 }, 2655 { ISD::UMAX, MVT::v32i16, 2 }, // FIXME: include split 2656 { ISD::UMAX, MVT::v64i8, 2 }, // FIXME: include split 2657 { ISD::UMAX, MVT::v4i64, 1 }, 2658 { ISD::UMAX, MVT::v2i64, 1 }, 2659 { ISD::UMIN, MVT::v8i64, 1 }, 2660 { ISD::UMIN, MVT::v16i32, 1 }, 2661 { ISD::UMIN, MVT::v32i16, 2 }, // FIXME: include split 2662 { ISD::UMIN, MVT::v64i8, 2 }, // FIXME: include split 2663 { ISD::UMIN, MVT::v4i64, 1 }, 2664 { ISD::UMIN, MVT::v2i64, 1 }, 2665 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2666 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2667 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2668 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2669 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2670 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2671 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2672 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2673 { ISD::SADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2674 { ISD::SADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2675 { ISD::SSUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2676 { ISD::SSUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2677 { ISD::UADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2678 { ISD::UADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2679 { ISD::USUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2680 { ISD::USUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2681 { ISD::FMAXNUM, MVT::f32, 2 }, 2682 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2683 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2684 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2685 { ISD::FMAXNUM, MVT::f64, 2 }, 2686 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2687 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2688 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2689 }; 2690 static const CostTblEntry XOPCostTbl[] = { 2691 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2692 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2693 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2694 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2695 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2696 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2697 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2698 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2699 { ISD::BITREVERSE, MVT::i64, 3 }, 2700 { ISD::BITREVERSE, MVT::i32, 3 }, 2701 { ISD::BITREVERSE, MVT::i16, 3 }, 2702 { ISD::BITREVERSE, MVT::i8, 3 } 2703 }; 2704 static const CostTblEntry AVX2CostTbl[] = { 2705 { ISD::ABS, MVT::v4i64, 2 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2706 { ISD::ABS, MVT::v8i32, 1 }, 2707 { ISD::ABS, MVT::v16i16, 1 }, 2708 { ISD::ABS, MVT::v32i8, 1 }, 2709 { ISD::BITREVERSE, MVT::v4i64, 5 }, 2710 { ISD::BITREVERSE, MVT::v8i32, 5 }, 2711 { ISD::BITREVERSE, MVT::v16i16, 5 }, 2712 { ISD::BITREVERSE, MVT::v32i8, 5 }, 2713 { ISD::BSWAP, MVT::v4i64, 1 }, 2714 { ISD::BSWAP, MVT::v8i32, 1 }, 2715 { ISD::BSWAP, MVT::v16i16, 1 }, 2716 { ISD::CTLZ, MVT::v4i64, 23 }, 2717 { ISD::CTLZ, MVT::v8i32, 18 }, 2718 { ISD::CTLZ, MVT::v16i16, 14 }, 2719 { ISD::CTLZ, MVT::v32i8, 9 }, 2720 { ISD::CTPOP, MVT::v4i64, 7 }, 2721 { ISD::CTPOP, MVT::v8i32, 11 }, 2722 { ISD::CTPOP, MVT::v16i16, 9 }, 2723 { ISD::CTPOP, MVT::v32i8, 6 }, 2724 { ISD::CTTZ, MVT::v4i64, 10 }, 2725 { ISD::CTTZ, MVT::v8i32, 14 }, 2726 { ISD::CTTZ, MVT::v16i16, 12 }, 2727 { ISD::CTTZ, MVT::v32i8, 9 }, 2728 { ISD::SADDSAT, MVT::v16i16, 1 }, 2729 { ISD::SADDSAT, MVT::v32i8, 1 }, 2730 { ISD::SMAX, MVT::v8i32, 1 }, 2731 { ISD::SMAX, MVT::v16i16, 1 }, 2732 { ISD::SMAX, MVT::v32i8, 1 }, 2733 { ISD::SMIN, MVT::v8i32, 1 }, 2734 { ISD::SMIN, MVT::v16i16, 1 }, 2735 { ISD::SMIN, MVT::v32i8, 1 }, 2736 { ISD::SSUBSAT, MVT::v16i16, 1 }, 2737 { ISD::SSUBSAT, MVT::v32i8, 1 }, 2738 { ISD::UADDSAT, MVT::v16i16, 1 }, 2739 { ISD::UADDSAT, MVT::v32i8, 1 }, 2740 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 2741 { ISD::UMAX, MVT::v8i32, 1 }, 2742 { ISD::UMAX, MVT::v16i16, 1 }, 2743 { ISD::UMAX, MVT::v32i8, 1 }, 2744 { ISD::UMIN, MVT::v8i32, 1 }, 2745 { ISD::UMIN, MVT::v16i16, 1 }, 2746 { ISD::UMIN, MVT::v32i8, 1 }, 2747 { ISD::USUBSAT, MVT::v16i16, 1 }, 2748 { ISD::USUBSAT, MVT::v32i8, 1 }, 2749 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2750 { ISD::FMAXNUM, MVT::v8f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2751 { ISD::FMAXNUM, MVT::v4f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2752 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2753 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2754 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2755 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2756 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2757 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2758 }; 2759 static const CostTblEntry AVX1CostTbl[] = { 2760 { ISD::ABS, MVT::v4i64, 5 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2761 { ISD::ABS, MVT::v8i32, 3 }, 2762 { ISD::ABS, MVT::v16i16, 3 }, 2763 { ISD::ABS, MVT::v32i8, 3 }, 2764 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 2765 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 2766 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 2767 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 2768 { ISD::BSWAP, MVT::v4i64, 4 }, 2769 { ISD::BSWAP, MVT::v8i32, 4 }, 2770 { ISD::BSWAP, MVT::v16i16, 4 }, 2771 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 2772 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 2773 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 2774 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2775 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 2776 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 2777 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 2778 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 2779 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 2780 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 2781 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 2782 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2783 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2784 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2785 { ISD::SMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2786 { ISD::SMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2787 { ISD::SMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2788 { ISD::SMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2789 { ISD::SMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2790 { ISD::SMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2791 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2792 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2793 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2794 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2795 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 2796 { ISD::UMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2797 { ISD::UMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2798 { ISD::UMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2799 { ISD::UMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2800 { ISD::UMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2801 { ISD::UMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2802 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2803 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2804 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 2805 { ISD::FMAXNUM, MVT::f32, 3 }, // MAXSS + CMPUNORDSS + BLENDVPS 2806 { ISD::FMAXNUM, MVT::v4f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2807 { ISD::FMAXNUM, MVT::v8f32, 5 }, // MAXPS + CMPUNORDPS + BLENDVPS + ? 2808 { ISD::FMAXNUM, MVT::f64, 3 }, // MAXSD + CMPUNORDSD + BLENDVPD 2809 { ISD::FMAXNUM, MVT::v2f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2810 { ISD::FMAXNUM, MVT::v4f64, 5 }, // MAXPD + CMPUNORDPD + BLENDVPD + ? 2811 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 2812 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 2813 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 2814 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 2815 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 2816 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 2817 }; 2818 static const CostTblEntry GLMCostTbl[] = { 2819 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 2820 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 2821 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 2822 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 2823 }; 2824 static const CostTblEntry SLMCostTbl[] = { 2825 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 2826 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 2827 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 2828 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 2829 }; 2830 static const CostTblEntry SSE42CostTbl[] = { 2831 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 2832 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 2833 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 2834 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 2835 }; 2836 static const CostTblEntry SSE41CostTbl[] = { 2837 { ISD::ABS, MVT::v2i64, 2 }, // BLENDVPD(X,PSUBQ(0,X),X) 2838 { ISD::SMAX, MVT::v4i32, 1 }, 2839 { ISD::SMAX, MVT::v16i8, 1 }, 2840 { ISD::SMIN, MVT::v4i32, 1 }, 2841 { ISD::SMIN, MVT::v16i8, 1 }, 2842 { ISD::UMAX, MVT::v4i32, 1 }, 2843 { ISD::UMAX, MVT::v8i16, 1 }, 2844 { ISD::UMIN, MVT::v4i32, 1 }, 2845 { ISD::UMIN, MVT::v8i16, 1 }, 2846 }; 2847 static const CostTblEntry SSSE3CostTbl[] = { 2848 { ISD::ABS, MVT::v4i32, 1 }, 2849 { ISD::ABS, MVT::v8i16, 1 }, 2850 { ISD::ABS, MVT::v16i8, 1 }, 2851 { ISD::BITREVERSE, MVT::v2i64, 5 }, 2852 { ISD::BITREVERSE, MVT::v4i32, 5 }, 2853 { ISD::BITREVERSE, MVT::v8i16, 5 }, 2854 { ISD::BITREVERSE, MVT::v16i8, 5 }, 2855 { ISD::BSWAP, MVT::v2i64, 1 }, 2856 { ISD::BSWAP, MVT::v4i32, 1 }, 2857 { ISD::BSWAP, MVT::v8i16, 1 }, 2858 { ISD::CTLZ, MVT::v2i64, 23 }, 2859 { ISD::CTLZ, MVT::v4i32, 18 }, 2860 { ISD::CTLZ, MVT::v8i16, 14 }, 2861 { ISD::CTLZ, MVT::v16i8, 9 }, 2862 { ISD::CTPOP, MVT::v2i64, 7 }, 2863 { ISD::CTPOP, MVT::v4i32, 11 }, 2864 { ISD::CTPOP, MVT::v8i16, 9 }, 2865 { ISD::CTPOP, MVT::v16i8, 6 }, 2866 { ISD::CTTZ, MVT::v2i64, 10 }, 2867 { ISD::CTTZ, MVT::v4i32, 14 }, 2868 { ISD::CTTZ, MVT::v8i16, 12 }, 2869 { ISD::CTTZ, MVT::v16i8, 9 } 2870 }; 2871 static const CostTblEntry SSE2CostTbl[] = { 2872 { ISD::ABS, MVT::v2i64, 4 }, 2873 { ISD::ABS, MVT::v4i32, 3 }, 2874 { ISD::ABS, MVT::v8i16, 2 }, 2875 { ISD::ABS, MVT::v16i8, 2 }, 2876 { ISD::BITREVERSE, MVT::v2i64, 29 }, 2877 { ISD::BITREVERSE, MVT::v4i32, 27 }, 2878 { ISD::BITREVERSE, MVT::v8i16, 27 }, 2879 { ISD::BITREVERSE, MVT::v16i8, 20 }, 2880 { ISD::BSWAP, MVT::v2i64, 7 }, 2881 { ISD::BSWAP, MVT::v4i32, 7 }, 2882 { ISD::BSWAP, MVT::v8i16, 7 }, 2883 { ISD::CTLZ, MVT::v2i64, 25 }, 2884 { ISD::CTLZ, MVT::v4i32, 26 }, 2885 { ISD::CTLZ, MVT::v8i16, 20 }, 2886 { ISD::CTLZ, MVT::v16i8, 17 }, 2887 { ISD::CTPOP, MVT::v2i64, 12 }, 2888 { ISD::CTPOP, MVT::v4i32, 15 }, 2889 { ISD::CTPOP, MVT::v8i16, 13 }, 2890 { ISD::CTPOP, MVT::v16i8, 10 }, 2891 { ISD::CTTZ, MVT::v2i64, 14 }, 2892 { ISD::CTTZ, MVT::v4i32, 18 }, 2893 { ISD::CTTZ, MVT::v8i16, 16 }, 2894 { ISD::CTTZ, MVT::v16i8, 13 }, 2895 { ISD::SADDSAT, MVT::v8i16, 1 }, 2896 { ISD::SADDSAT, MVT::v16i8, 1 }, 2897 { ISD::SMAX, MVT::v8i16, 1 }, 2898 { ISD::SMIN, MVT::v8i16, 1 }, 2899 { ISD::SSUBSAT, MVT::v8i16, 1 }, 2900 { ISD::SSUBSAT, MVT::v16i8, 1 }, 2901 { ISD::UADDSAT, MVT::v8i16, 1 }, 2902 { ISD::UADDSAT, MVT::v16i8, 1 }, 2903 { ISD::UMAX, MVT::v8i16, 2 }, 2904 { ISD::UMAX, MVT::v16i8, 1 }, 2905 { ISD::UMIN, MVT::v8i16, 2 }, 2906 { ISD::UMIN, MVT::v16i8, 1 }, 2907 { ISD::USUBSAT, MVT::v8i16, 1 }, 2908 { ISD::USUBSAT, MVT::v16i8, 1 }, 2909 { ISD::FMAXNUM, MVT::f64, 4 }, 2910 { ISD::FMAXNUM, MVT::v2f64, 4 }, 2911 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 2912 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 2913 }; 2914 static const CostTblEntry SSE1CostTbl[] = { 2915 { ISD::FMAXNUM, MVT::f32, 4 }, 2916 { ISD::FMAXNUM, MVT::v4f32, 4 }, 2917 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 2918 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 2919 }; 2920 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 2921 { ISD::CTTZ, MVT::i64, 1 }, 2922 }; 2923 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 2924 { ISD::CTTZ, MVT::i32, 1 }, 2925 { ISD::CTTZ, MVT::i16, 1 }, 2926 { ISD::CTTZ, MVT::i8, 1 }, 2927 }; 2928 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 2929 { ISD::CTLZ, MVT::i64, 1 }, 2930 }; 2931 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 2932 { ISD::CTLZ, MVT::i32, 1 }, 2933 { ISD::CTLZ, MVT::i16, 1 }, 2934 { ISD::CTLZ, MVT::i8, 1 }, 2935 }; 2936 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 2937 { ISD::CTPOP, MVT::i64, 1 }, 2938 }; 2939 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 2940 { ISD::CTPOP, MVT::i32, 1 }, 2941 { ISD::CTPOP, MVT::i16, 1 }, 2942 { ISD::CTPOP, MVT::i8, 1 }, 2943 }; 2944 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2945 { ISD::ABS, MVT::i64, 2 }, // SUB+CMOV 2946 { ISD::BITREVERSE, MVT::i64, 14 }, 2947 { ISD::BSWAP, MVT::i64, 1 }, 2948 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 2949 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 2950 { ISD::CTPOP, MVT::i64, 10 }, 2951 { ISD::SADDO, MVT::i64, 1 }, 2952 { ISD::UADDO, MVT::i64, 1 }, 2953 { ISD::UMULO, MVT::i64, 2 }, // mulq + seto 2954 }; 2955 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2956 { ISD::ABS, MVT::i32, 2 }, // SUB+CMOV 2957 { ISD::ABS, MVT::i16, 2 }, // SUB+CMOV 2958 { ISD::BITREVERSE, MVT::i32, 14 }, 2959 { ISD::BITREVERSE, MVT::i16, 14 }, 2960 { ISD::BITREVERSE, MVT::i8, 11 }, 2961 { ISD::BSWAP, MVT::i32, 1 }, 2962 { ISD::BSWAP, MVT::i16, 1 }, // ROL 2963 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 2964 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 2965 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 2966 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 2967 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 2968 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 2969 { ISD::CTPOP, MVT::i32, 8 }, 2970 { ISD::CTPOP, MVT::i16, 9 }, 2971 { ISD::CTPOP, MVT::i8, 7 }, 2972 { ISD::SADDO, MVT::i32, 1 }, 2973 { ISD::SADDO, MVT::i16, 1 }, 2974 { ISD::SADDO, MVT::i8, 1 }, 2975 { ISD::UADDO, MVT::i32, 1 }, 2976 { ISD::UADDO, MVT::i16, 1 }, 2977 { ISD::UADDO, MVT::i8, 1 }, 2978 { ISD::UMULO, MVT::i32, 2 }, // mul + seto 2979 { ISD::UMULO, MVT::i16, 2 }, 2980 { ISD::UMULO, MVT::i8, 2 }, 2981 }; 2982 2983 Type *RetTy = ICA.getReturnType(); 2984 Type *OpTy = RetTy; 2985 Intrinsic::ID IID = ICA.getID(); 2986 unsigned ISD = ISD::DELETED_NODE; 2987 switch (IID) { 2988 default: 2989 break; 2990 case Intrinsic::abs: 2991 ISD = ISD::ABS; 2992 break; 2993 case Intrinsic::bitreverse: 2994 ISD = ISD::BITREVERSE; 2995 break; 2996 case Intrinsic::bswap: 2997 ISD = ISD::BSWAP; 2998 break; 2999 case Intrinsic::ctlz: 3000 ISD = ISD::CTLZ; 3001 break; 3002 case Intrinsic::ctpop: 3003 ISD = ISD::CTPOP; 3004 break; 3005 case Intrinsic::cttz: 3006 ISD = ISD::CTTZ; 3007 break; 3008 case Intrinsic::maxnum: 3009 case Intrinsic::minnum: 3010 // FMINNUM has same costs so don't duplicate. 3011 ISD = ISD::FMAXNUM; 3012 break; 3013 case Intrinsic::sadd_sat: 3014 ISD = ISD::SADDSAT; 3015 break; 3016 case Intrinsic::smax: 3017 ISD = ISD::SMAX; 3018 break; 3019 case Intrinsic::smin: 3020 ISD = ISD::SMIN; 3021 break; 3022 case Intrinsic::ssub_sat: 3023 ISD = ISD::SSUBSAT; 3024 break; 3025 case Intrinsic::uadd_sat: 3026 ISD = ISD::UADDSAT; 3027 break; 3028 case Intrinsic::umax: 3029 ISD = ISD::UMAX; 3030 break; 3031 case Intrinsic::umin: 3032 ISD = ISD::UMIN; 3033 break; 3034 case Intrinsic::usub_sat: 3035 ISD = ISD::USUBSAT; 3036 break; 3037 case Intrinsic::sqrt: 3038 ISD = ISD::FSQRT; 3039 break; 3040 case Intrinsic::sadd_with_overflow: 3041 case Intrinsic::ssub_with_overflow: 3042 // SSUBO has same costs so don't duplicate. 3043 ISD = ISD::SADDO; 3044 OpTy = RetTy->getContainedType(0); 3045 break; 3046 case Intrinsic::uadd_with_overflow: 3047 case Intrinsic::usub_with_overflow: 3048 // USUBO has same costs so don't duplicate. 3049 ISD = ISD::UADDO; 3050 OpTy = RetTy->getContainedType(0); 3051 break; 3052 case Intrinsic::umul_with_overflow: 3053 case Intrinsic::smul_with_overflow: 3054 // SMULO has same costs so don't duplicate. 3055 ISD = ISD::UMULO; 3056 OpTy = RetTy->getContainedType(0); 3057 break; 3058 } 3059 3060 if (ISD != ISD::DELETED_NODE) { 3061 // Legalize the type. 3062 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 3063 MVT MTy = LT.second; 3064 3065 // Attempt to lookup cost. 3066 if (ISD == ISD::BITREVERSE && ST->hasGFNI() && ST->hasSSSE3() && 3067 MTy.isVector()) { 3068 // With PSHUFB the code is very similar for all types. If we have integer 3069 // byte operations, we just need a GF2P8AFFINEQB for vXi8. For other types 3070 // we also need a PSHUFB. 3071 unsigned Cost = MTy.getVectorElementType() == MVT::i8 ? 1 : 2; 3072 3073 // Without byte operations, we need twice as many GF2P8AFFINEQB and PSHUFB 3074 // instructions. We also need an extract and an insert. 3075 if (!(MTy.is128BitVector() || (ST->hasAVX2() && MTy.is256BitVector()) || 3076 (ST->hasBWI() && MTy.is512BitVector()))) 3077 Cost = Cost * 2 + 2; 3078 3079 return LT.first * Cost; 3080 } 3081 3082 auto adjustTableCost = [](const CostTblEntry &Entry, 3083 InstructionCost LegalizationCost, 3084 FastMathFlags FMF) { 3085 // If there are no NANs to deal with, then these are reduced to a 3086 // single MIN** or MAX** instruction instead of the MIN/CMP/SELECT that we 3087 // assume is used in the non-fast case. 3088 if (Entry.ISD == ISD::FMAXNUM || Entry.ISD == ISD::FMINNUM) { 3089 if (FMF.noNaNs()) 3090 return LegalizationCost * 1; 3091 } 3092 return LegalizationCost * (int)Entry.Cost; 3093 }; 3094 3095 if (ST->useGLMDivSqrtCosts()) 3096 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 3097 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3098 3099 if (ST->isSLM()) 3100 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 3101 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3102 3103 if (ST->hasCDI()) 3104 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 3105 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3106 3107 if (ST->hasBWI()) 3108 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3109 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3110 3111 if (ST->hasAVX512()) 3112 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3113 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3114 3115 if (ST->hasXOP()) 3116 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3117 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3118 3119 if (ST->hasAVX2()) 3120 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3121 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3122 3123 if (ST->hasAVX()) 3124 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3125 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3126 3127 if (ST->hasSSE42()) 3128 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3129 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3130 3131 if (ST->hasSSE41()) 3132 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3133 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3134 3135 if (ST->hasSSSE3()) 3136 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 3137 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3138 3139 if (ST->hasSSE2()) 3140 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3141 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3142 3143 if (ST->hasSSE1()) 3144 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3145 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3146 3147 if (ST->hasBMI()) { 3148 if (ST->is64Bit()) 3149 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 3150 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3151 3152 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 3153 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3154 } 3155 3156 if (ST->hasLZCNT()) { 3157 if (ST->is64Bit()) 3158 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 3159 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3160 3161 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 3162 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3163 } 3164 3165 if (ST->hasPOPCNT()) { 3166 if (ST->is64Bit()) 3167 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 3168 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3169 3170 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 3171 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3172 } 3173 3174 if (ISD == ISD::BSWAP && ST->hasMOVBE() && ST->hasFastMOVBE()) { 3175 if (const Instruction *II = ICA.getInst()) { 3176 if (II->hasOneUse() && isa<StoreInst>(II->user_back())) 3177 return TTI::TCC_Free; 3178 if (auto *LI = dyn_cast<LoadInst>(II->getOperand(0))) { 3179 if (LI->hasOneUse()) 3180 return TTI::TCC_Free; 3181 } 3182 } 3183 } 3184 3185 // TODO - add BMI (TZCNT) scalar handling 3186 3187 if (ST->is64Bit()) 3188 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3189 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3190 3191 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3192 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3193 } 3194 3195 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3196 } 3197 3198 InstructionCost 3199 X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 3200 TTI::TargetCostKind CostKind) { 3201 if (ICA.isTypeBasedOnly()) 3202 return getTypeBasedIntrinsicInstrCost(ICA, CostKind); 3203 3204 static const CostTblEntry AVX512CostTbl[] = { 3205 { ISD::ROTL, MVT::v8i64, 1 }, 3206 { ISD::ROTL, MVT::v4i64, 1 }, 3207 { ISD::ROTL, MVT::v2i64, 1 }, 3208 { ISD::ROTL, MVT::v16i32, 1 }, 3209 { ISD::ROTL, MVT::v8i32, 1 }, 3210 { ISD::ROTL, MVT::v4i32, 1 }, 3211 { ISD::ROTR, MVT::v8i64, 1 }, 3212 { ISD::ROTR, MVT::v4i64, 1 }, 3213 { ISD::ROTR, MVT::v2i64, 1 }, 3214 { ISD::ROTR, MVT::v16i32, 1 }, 3215 { ISD::ROTR, MVT::v8i32, 1 }, 3216 { ISD::ROTR, MVT::v4i32, 1 } 3217 }; 3218 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 3219 static const CostTblEntry XOPCostTbl[] = { 3220 { ISD::ROTL, MVT::v4i64, 4 }, 3221 { ISD::ROTL, MVT::v8i32, 4 }, 3222 { ISD::ROTL, MVT::v16i16, 4 }, 3223 { ISD::ROTL, MVT::v32i8, 4 }, 3224 { ISD::ROTL, MVT::v2i64, 1 }, 3225 { ISD::ROTL, MVT::v4i32, 1 }, 3226 { ISD::ROTL, MVT::v8i16, 1 }, 3227 { ISD::ROTL, MVT::v16i8, 1 }, 3228 { ISD::ROTR, MVT::v4i64, 6 }, 3229 { ISD::ROTR, MVT::v8i32, 6 }, 3230 { ISD::ROTR, MVT::v16i16, 6 }, 3231 { ISD::ROTR, MVT::v32i8, 6 }, 3232 { ISD::ROTR, MVT::v2i64, 2 }, 3233 { ISD::ROTR, MVT::v4i32, 2 }, 3234 { ISD::ROTR, MVT::v8i16, 2 }, 3235 { ISD::ROTR, MVT::v16i8, 2 } 3236 }; 3237 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 3238 { ISD::ROTL, MVT::i64, 1 }, 3239 { ISD::ROTR, MVT::i64, 1 }, 3240 { ISD::FSHL, MVT::i64, 4 } 3241 }; 3242 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 3243 { ISD::ROTL, MVT::i32, 1 }, 3244 { ISD::ROTL, MVT::i16, 1 }, 3245 { ISD::ROTL, MVT::i8, 1 }, 3246 { ISD::ROTR, MVT::i32, 1 }, 3247 { ISD::ROTR, MVT::i16, 1 }, 3248 { ISD::ROTR, MVT::i8, 1 }, 3249 { ISD::FSHL, MVT::i32, 4 }, 3250 { ISD::FSHL, MVT::i16, 4 }, 3251 { ISD::FSHL, MVT::i8, 4 } 3252 }; 3253 3254 Intrinsic::ID IID = ICA.getID(); 3255 Type *RetTy = ICA.getReturnType(); 3256 const SmallVectorImpl<const Value *> &Args = ICA.getArgs(); 3257 unsigned ISD = ISD::DELETED_NODE; 3258 switch (IID) { 3259 default: 3260 break; 3261 case Intrinsic::fshl: 3262 ISD = ISD::FSHL; 3263 if (Args[0] == Args[1]) 3264 ISD = ISD::ROTL; 3265 break; 3266 case Intrinsic::fshr: 3267 // FSHR has same costs so don't duplicate. 3268 ISD = ISD::FSHL; 3269 if (Args[0] == Args[1]) 3270 ISD = ISD::ROTR; 3271 break; 3272 } 3273 3274 if (ISD != ISD::DELETED_NODE) { 3275 // Legalize the type. 3276 std::pair<InstructionCost, MVT> LT = 3277 TLI->getTypeLegalizationCost(DL, RetTy); 3278 MVT MTy = LT.second; 3279 3280 // Attempt to lookup cost. 3281 if (ST->hasAVX512()) 3282 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3283 return LT.first * Entry->Cost; 3284 3285 if (ST->hasXOP()) 3286 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3287 return LT.first * Entry->Cost; 3288 3289 if (ST->is64Bit()) 3290 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3291 return LT.first * Entry->Cost; 3292 3293 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3294 return LT.first * Entry->Cost; 3295 } 3296 3297 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3298 } 3299 3300 InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, 3301 unsigned Index) { 3302 static const CostTblEntry SLMCostTbl[] = { 3303 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 3304 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 3305 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 3306 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 3307 }; 3308 3309 assert(Val->isVectorTy() && "This must be a vector type"); 3310 Type *ScalarType = Val->getScalarType(); 3311 int RegisterFileMoveCost = 0; 3312 3313 // Non-immediate extraction/insertion can be handled as a sequence of 3314 // aliased loads+stores via the stack. 3315 if (Index == -1U && (Opcode == Instruction::ExtractElement || 3316 Opcode == Instruction::InsertElement)) { 3317 // TODO: On some SSE41+ targets, we expand to cmp+splat+select patterns: 3318 // inselt N0, N1, N2 --> select (SplatN2 == {0,1,2...}) ? SplatN1 : N0. 3319 3320 // TODO: Move this to BasicTTIImpl.h? We'd need better gep + index handling. 3321 assert(isa<FixedVectorType>(Val) && "Fixed vector type expected"); 3322 Align VecAlign = DL.getPrefTypeAlign(Val); 3323 Align SclAlign = DL.getPrefTypeAlign(ScalarType); 3324 3325 // Extract - store vector to stack, load scalar. 3326 if (Opcode == Instruction::ExtractElement) { 3327 return getMemoryOpCost(Instruction::Store, Val, VecAlign, 0, 3328 TTI::TargetCostKind::TCK_RecipThroughput) + 3329 getMemoryOpCost(Instruction::Load, ScalarType, SclAlign, 0, 3330 TTI::TargetCostKind::TCK_RecipThroughput); 3331 } 3332 // Insert - store vector to stack, store scalar, load vector. 3333 if (Opcode == Instruction::InsertElement) { 3334 return getMemoryOpCost(Instruction::Store, Val, VecAlign, 0, 3335 TTI::TargetCostKind::TCK_RecipThroughput) + 3336 getMemoryOpCost(Instruction::Store, ScalarType, SclAlign, 0, 3337 TTI::TargetCostKind::TCK_RecipThroughput) + 3338 getMemoryOpCost(Instruction::Load, Val, VecAlign, 0, 3339 TTI::TargetCostKind::TCK_RecipThroughput); 3340 } 3341 } 3342 3343 if (Index != -1U && (Opcode == Instruction::ExtractElement || 3344 Opcode == Instruction::InsertElement)) { 3345 // Legalize the type. 3346 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 3347 3348 // This type is legalized to a scalar type. 3349 if (!LT.second.isVector()) 3350 return 0; 3351 3352 // The type may be split. Normalize the index to the new type. 3353 unsigned NumElts = LT.second.getVectorNumElements(); 3354 unsigned SubNumElts = NumElts; 3355 Index = Index % NumElts; 3356 3357 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 3358 // For inserts, we also need to insert the subvector back. 3359 if (LT.second.getSizeInBits() > 128) { 3360 assert((LT.second.getSizeInBits() % 128) == 0 && "Illegal vector"); 3361 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 3362 SubNumElts = NumElts / NumSubVecs; 3363 if (SubNumElts <= Index) { 3364 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 3365 Index %= SubNumElts; 3366 } 3367 } 3368 3369 if (Index == 0) { 3370 // Floating point scalars are already located in index #0. 3371 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 3372 // true for all. 3373 if (ScalarType->isFloatingPointTy()) 3374 return RegisterFileMoveCost; 3375 3376 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 3377 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 3378 return 1 + RegisterFileMoveCost; 3379 } 3380 3381 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3382 assert(ISD && "Unexpected vector opcode"); 3383 MVT MScalarTy = LT.second.getScalarType(); 3384 if (ST->isSLM()) 3385 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 3386 return Entry->Cost + RegisterFileMoveCost; 3387 3388 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 3389 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3390 (MScalarTy.isInteger() && ST->hasSSE41())) 3391 return 1 + RegisterFileMoveCost; 3392 3393 // Assume insertps is relatively cheap on all targets. 3394 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 3395 Opcode == Instruction::InsertElement) 3396 return 1 + RegisterFileMoveCost; 3397 3398 // For extractions we just need to shuffle the element to index 0, which 3399 // should be very cheap (assume cost = 1). For insertions we need to shuffle 3400 // the elements to its destination. In both cases we must handle the 3401 // subvector move(s). 3402 // If the vector type is already less than 128-bits then don't reduce it. 3403 // TODO: Under what circumstances should we shuffle using the full width? 3404 InstructionCost ShuffleCost = 1; 3405 if (Opcode == Instruction::InsertElement) { 3406 auto *SubTy = cast<VectorType>(Val); 3407 EVT VT = TLI->getValueType(DL, Val); 3408 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 3409 SubTy = FixedVectorType::get(ScalarType, SubNumElts); 3410 ShuffleCost = 3411 getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, None, 0, SubTy); 3412 } 3413 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 3414 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 3415 } 3416 3417 // Add to the base cost if we know that the extracted element of a vector is 3418 // destined to be moved to and used in the integer register file. 3419 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 3420 RegisterFileMoveCost += 1; 3421 3422 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 3423 } 3424 3425 InstructionCost X86TTIImpl::getScalarizationOverhead(VectorType *Ty, 3426 const APInt &DemandedElts, 3427 bool Insert, 3428 bool Extract) { 3429 InstructionCost Cost = 0; 3430 3431 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much 3432 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT. 3433 if (Insert) { 3434 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3435 MVT MScalarTy = LT.second.getScalarType(); 3436 3437 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3438 (MScalarTy.isInteger() && ST->hasSSE41()) || 3439 (MScalarTy == MVT::f32 && ST->hasSSE41())) { 3440 // For types we can insert directly, insertion into 128-bit sub vectors is 3441 // cheap, followed by a cheap chain of concatenations. 3442 if (LT.second.getSizeInBits() <= 128) { 3443 Cost += 3444 BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, false); 3445 } else { 3446 // In each 128-lane, if at least one index is demanded but not all 3447 // indices are demanded and this 128-lane is not the first 128-lane of 3448 // the legalized-vector, then this 128-lane needs a extracti128; If in 3449 // each 128-lane, there is at least one demanded index, this 128-lane 3450 // needs a inserti128. 3451 3452 // The following cases will help you build a better understanding: 3453 // Assume we insert several elements into a v8i32 vector in avx2, 3454 // Case#1: inserting into 1th index needs vpinsrd + inserti128. 3455 // Case#2: inserting into 5th index needs extracti128 + vpinsrd + 3456 // inserti128. 3457 // Case#3: inserting into 4,5,6,7 index needs 4*vpinsrd + inserti128. 3458 const int CostValue = *LT.first.getValue(); 3459 assert(CostValue >= 0 && "Negative cost!"); 3460 unsigned Num128Lanes = LT.second.getSizeInBits() / 128 * CostValue; 3461 unsigned NumElts = LT.second.getVectorNumElements() * CostValue; 3462 APInt WidenedDemandedElts = DemandedElts.zextOrSelf(NumElts); 3463 unsigned Scale = NumElts / Num128Lanes; 3464 // We iterate each 128-lane, and check if we need a 3465 // extracti128/inserti128 for this 128-lane. 3466 for (unsigned I = 0; I < NumElts; I += Scale) { 3467 APInt Mask = WidenedDemandedElts.getBitsSet(NumElts, I, I + Scale); 3468 APInt MaskedDE = Mask & WidenedDemandedElts; 3469 unsigned Population = MaskedDE.countPopulation(); 3470 Cost += (Population > 0 && Population != Scale && 3471 I % LT.second.getVectorNumElements() != 0); 3472 Cost += Population > 0; 3473 } 3474 Cost += DemandedElts.countPopulation(); 3475 3476 // For vXf32 cases, insertion into the 0'th index in each v4f32 3477 // 128-bit vector is free. 3478 // NOTE: This assumes legalization widens vXf32 vectors. 3479 if (MScalarTy == MVT::f32) 3480 for (unsigned i = 0, e = cast<FixedVectorType>(Ty)->getNumElements(); 3481 i < e; i += 4) 3482 if (DemandedElts[i]) 3483 Cost--; 3484 } 3485 } else if (LT.second.isVector()) { 3486 // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded 3487 // integer element as a SCALAR_TO_VECTOR, then we build the vector as a 3488 // series of UNPCK followed by CONCAT_VECTORS - all of these can be 3489 // considered cheap. 3490 if (Ty->isIntOrIntVectorTy()) 3491 Cost += DemandedElts.countPopulation(); 3492 3493 // Get the smaller of the legalized or original pow2-extended number of 3494 // vector elements, which represents the number of unpacks we'll end up 3495 // performing. 3496 unsigned NumElts = LT.second.getVectorNumElements(); 3497 unsigned Pow2Elts = 3498 PowerOf2Ceil(cast<FixedVectorType>(Ty)->getNumElements()); 3499 Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first; 3500 } 3501 } 3502 3503 // TODO: Use default extraction for now, but we should investigate extending this 3504 // to handle repeated subvector extraction. 3505 if (Extract) 3506 Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, false, Extract); 3507 3508 return Cost; 3509 } 3510 3511 InstructionCost X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 3512 MaybeAlign Alignment, 3513 unsigned AddressSpace, 3514 TTI::TargetCostKind CostKind, 3515 const Instruction *I) { 3516 // TODO: Handle other cost kinds. 3517 if (CostKind != TTI::TCK_RecipThroughput) { 3518 if (auto *SI = dyn_cast_or_null<StoreInst>(I)) { 3519 // Store instruction with index and scale costs 2 Uops. 3520 // Check the preceding GEP to identify non-const indices. 3521 if (auto *GEP = dyn_cast<GetElementPtrInst>(SI->getPointerOperand())) { 3522 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3523 return TTI::TCC_Basic * 2; 3524 } 3525 } 3526 return TTI::TCC_Basic; 3527 } 3528 3529 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 3530 "Invalid Opcode"); 3531 // Type legalization can't handle structs 3532 if (TLI->getValueType(DL, Src, true) == MVT::Other) 3533 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3534 CostKind); 3535 3536 // Legalize the type. 3537 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 3538 3539 auto *VTy = dyn_cast<FixedVectorType>(Src); 3540 3541 // Handle the simple case of non-vectors. 3542 // NOTE: this assumes that legalization never creates vector from scalars! 3543 if (!VTy || !LT.second.isVector()) 3544 // Each load/store unit costs 1. 3545 return LT.first * 1; 3546 3547 bool IsLoad = Opcode == Instruction::Load; 3548 3549 Type *EltTy = VTy->getElementType(); 3550 3551 const int EltTyBits = DL.getTypeSizeInBits(EltTy); 3552 3553 InstructionCost Cost = 0; 3554 3555 // Source of truth: how many elements were there in the original IR vector? 3556 const unsigned SrcNumElt = VTy->getNumElements(); 3557 3558 // How far have we gotten? 3559 int NumEltRemaining = SrcNumElt; 3560 // Note that we intentionally capture by-reference, NumEltRemaining changes. 3561 auto NumEltDone = [&]() { return SrcNumElt - NumEltRemaining; }; 3562 3563 const int MaxLegalOpSizeBytes = divideCeil(LT.second.getSizeInBits(), 8); 3564 3565 // Note that even if we can store 64 bits of an XMM, we still operate on XMM. 3566 const unsigned XMMBits = 128; 3567 if (XMMBits % EltTyBits != 0) 3568 // Vector size must be a multiple of the element size. I.e. no padding. 3569 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3570 CostKind); 3571 const int NumEltPerXMM = XMMBits / EltTyBits; 3572 3573 auto *XMMVecTy = FixedVectorType::get(EltTy, NumEltPerXMM); 3574 3575 for (int CurrOpSizeBytes = MaxLegalOpSizeBytes, SubVecEltsLeft = 0; 3576 NumEltRemaining > 0; CurrOpSizeBytes /= 2) { 3577 // How many elements would a single op deal with at once? 3578 if ((8 * CurrOpSizeBytes) % EltTyBits != 0) 3579 // Vector size must be a multiple of the element size. I.e. no padding. 3580 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3581 CostKind); 3582 int CurrNumEltPerOp = (8 * CurrOpSizeBytes) / EltTyBits; 3583 3584 assert(CurrOpSizeBytes > 0 && CurrNumEltPerOp > 0 && "How'd we get here?"); 3585 assert((((NumEltRemaining * EltTyBits) < (2 * 8 * CurrOpSizeBytes)) || 3586 (CurrOpSizeBytes == MaxLegalOpSizeBytes)) && 3587 "Unless we haven't halved the op size yet, " 3588 "we have less than two op's sized units of work left."); 3589 3590 auto *CurrVecTy = CurrNumEltPerOp > NumEltPerXMM 3591 ? FixedVectorType::get(EltTy, CurrNumEltPerOp) 3592 : XMMVecTy; 3593 3594 assert(CurrVecTy->getNumElements() % CurrNumEltPerOp == 0 && 3595 "After halving sizes, the vector elt count is no longer a multiple " 3596 "of number of elements per operation?"); 3597 auto *CoalescedVecTy = 3598 CurrNumEltPerOp == 1 3599 ? CurrVecTy 3600 : FixedVectorType::get( 3601 IntegerType::get(Src->getContext(), 3602 EltTyBits * CurrNumEltPerOp), 3603 CurrVecTy->getNumElements() / CurrNumEltPerOp); 3604 assert(DL.getTypeSizeInBits(CoalescedVecTy) == 3605 DL.getTypeSizeInBits(CurrVecTy) && 3606 "coalesciing elements doesn't change vector width."); 3607 3608 while (NumEltRemaining > 0) { 3609 assert(SubVecEltsLeft >= 0 && "Subreg element count overconsumtion?"); 3610 3611 // Can we use this vector size, as per the remaining element count? 3612 // Iff the vector is naturally aligned, we can do a wide load regardless. 3613 if (NumEltRemaining < CurrNumEltPerOp && 3614 (!IsLoad || Alignment.valueOrOne() < CurrOpSizeBytes) && 3615 CurrOpSizeBytes != 1) 3616 break; // Try smalled vector size. 3617 3618 bool Is0thSubVec = (NumEltDone() % LT.second.getVectorNumElements()) == 0; 3619 3620 // If we have fully processed the previous reg, we need to replenish it. 3621 if (SubVecEltsLeft == 0) { 3622 SubVecEltsLeft += CurrVecTy->getNumElements(); 3623 // And that's free only for the 0'th subvector of a legalized vector. 3624 if (!Is0thSubVec) 3625 Cost += getShuffleCost(IsLoad ? TTI::ShuffleKind::SK_InsertSubvector 3626 : TTI::ShuffleKind::SK_ExtractSubvector, 3627 VTy, None, NumEltDone(), CurrVecTy); 3628 } 3629 3630 // While we can directly load/store ZMM, YMM, and 64-bit halves of XMM, 3631 // for smaller widths (32/16/8) we have to insert/extract them separately. 3632 // Again, it's free for the 0'th subreg (if op is 32/64 bit wide, 3633 // but let's pretend that it is also true for 16/8 bit wide ops...) 3634 if (CurrOpSizeBytes <= 32 / 8 && !Is0thSubVec) { 3635 int NumEltDoneInCurrXMM = NumEltDone() % NumEltPerXMM; 3636 assert(NumEltDoneInCurrXMM % CurrNumEltPerOp == 0 && ""); 3637 int CoalescedVecEltIdx = NumEltDoneInCurrXMM / CurrNumEltPerOp; 3638 APInt DemandedElts = 3639 APInt::getBitsSet(CoalescedVecTy->getNumElements(), 3640 CoalescedVecEltIdx, CoalescedVecEltIdx + 1); 3641 assert(DemandedElts.countPopulation() == 1 && "Inserting single value"); 3642 Cost += getScalarizationOverhead(CoalescedVecTy, DemandedElts, IsLoad, 3643 !IsLoad); 3644 } 3645 3646 // This isn't exactly right. We're using slow unaligned 32-byte accesses 3647 // as a proxy for a double-pumped AVX memory interface such as on 3648 // Sandybridge. 3649 if (CurrOpSizeBytes == 32 && ST->isUnalignedMem32Slow()) 3650 Cost += 2; 3651 else 3652 Cost += 1; 3653 3654 SubVecEltsLeft -= CurrNumEltPerOp; 3655 NumEltRemaining -= CurrNumEltPerOp; 3656 Alignment = commonAlignment(Alignment.valueOrOne(), CurrOpSizeBytes); 3657 } 3658 } 3659 3660 assert(NumEltRemaining <= 0 && "Should have processed all the elements."); 3661 3662 return Cost; 3663 } 3664 3665 InstructionCost 3666 X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, Align Alignment, 3667 unsigned AddressSpace, 3668 TTI::TargetCostKind CostKind) { 3669 bool IsLoad = (Instruction::Load == Opcode); 3670 bool IsStore = (Instruction::Store == Opcode); 3671 3672 auto *SrcVTy = dyn_cast<FixedVectorType>(SrcTy); 3673 if (!SrcVTy) 3674 // To calculate scalar take the regular cost, without mask 3675 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace, CostKind); 3676 3677 unsigned NumElem = SrcVTy->getNumElements(); 3678 auto *MaskTy = 3679 FixedVectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 3680 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, Alignment)) || 3681 (IsStore && !isLegalMaskedStore(SrcVTy, Alignment))) { 3682 // Scalarization 3683 APInt DemandedElts = APInt::getAllOnesValue(NumElem); 3684 InstructionCost MaskSplitCost = 3685 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 3686 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 3687 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr, 3688 CmpInst::BAD_ICMP_PREDICATE, CostKind); 3689 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 3690 InstructionCost MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 3691 InstructionCost ValueSplitCost = 3692 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore); 3693 InstructionCost MemopCost = 3694 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3695 Alignment, AddressSpace, CostKind); 3696 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 3697 } 3698 3699 // Legalize the type. 3700 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3701 auto VT = TLI->getValueType(DL, SrcVTy); 3702 InstructionCost Cost = 0; 3703 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 3704 LT.second.getVectorNumElements() == NumElem) 3705 // Promotion requires extend/truncate for data and a shuffle for mask. 3706 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, None, 0, nullptr) + 3707 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, None, 0, nullptr); 3708 3709 else if (LT.first * LT.second.getVectorNumElements() > NumElem) { 3710 auto *NewMaskTy = FixedVectorType::get(MaskTy->getElementType(), 3711 LT.second.getVectorNumElements()); 3712 // Expanding requires fill mask with zeroes 3713 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, None, 0, MaskTy); 3714 } 3715 3716 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 3717 if (!ST->hasAVX512()) 3718 return Cost + LT.first * (IsLoad ? 2 : 8); 3719 3720 // AVX-512 masked load/store is cheapper 3721 return Cost + LT.first; 3722 } 3723 3724 InstructionCost X86TTIImpl::getAddressComputationCost(Type *Ty, 3725 ScalarEvolution *SE, 3726 const SCEV *Ptr) { 3727 // Address computations in vectorized code with non-consecutive addresses will 3728 // likely result in more instructions compared to scalar code where the 3729 // computation can more often be merged into the index mode. The resulting 3730 // extra micro-ops can significantly decrease throughput. 3731 const unsigned NumVectorInstToHideOverhead = 10; 3732 3733 // Cost modeling of Strided Access Computation is hidden by the indexing 3734 // modes of X86 regardless of the stride value. We dont believe that there 3735 // is a difference between constant strided access in gerenal and constant 3736 // strided value which is less than or equal to 64. 3737 // Even in the case of (loop invariant) stride whose value is not known at 3738 // compile time, the address computation will not incur more than one extra 3739 // ADD instruction. 3740 if (Ty->isVectorTy() && SE) { 3741 if (!BaseT::isStridedAccess(Ptr)) 3742 return NumVectorInstToHideOverhead; 3743 if (!BaseT::getConstantStrideStep(SE, Ptr)) 3744 return 1; 3745 } 3746 3747 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 3748 } 3749 3750 InstructionCost 3751 X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 3752 TTI::TargetCostKind CostKind) { 3753 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3754 // and make it as the cost. 3755 3756 static const CostTblEntry SLMCostTblNoPairWise[] = { 3757 { ISD::FADD, MVT::v2f64, 3 }, 3758 { ISD::ADD, MVT::v2i64, 5 }, 3759 }; 3760 3761 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3762 { ISD::FADD, MVT::v2f64, 2 }, 3763 { ISD::FADD, MVT::v2f32, 2 }, 3764 { ISD::FADD, MVT::v4f32, 4 }, 3765 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 3766 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 3767 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 3768 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 3769 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 3770 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 3771 { ISD::ADD, MVT::v2i8, 2 }, 3772 { ISD::ADD, MVT::v4i8, 2 }, 3773 { ISD::ADD, MVT::v8i8, 2 }, 3774 { ISD::ADD, MVT::v16i8, 3 }, 3775 }; 3776 3777 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3778 { ISD::FADD, MVT::v4f64, 3 }, 3779 { ISD::FADD, MVT::v4f32, 3 }, 3780 { ISD::FADD, MVT::v8f32, 4 }, 3781 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 3782 { ISD::ADD, MVT::v4i64, 3 }, 3783 { ISD::ADD, MVT::v8i32, 5 }, 3784 { ISD::ADD, MVT::v16i16, 5 }, 3785 { ISD::ADD, MVT::v32i8, 4 }, 3786 }; 3787 3788 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3789 assert(ISD && "Invalid opcode"); 3790 3791 // Before legalizing the type, give a chance to look up illegal narrow types 3792 // in the table. 3793 // FIXME: Is there a better way to do this? 3794 EVT VT = TLI->getValueType(DL, ValTy); 3795 if (VT.isSimple()) { 3796 MVT MTy = VT.getSimpleVT(); 3797 if (ST->isSLM()) 3798 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3799 return Entry->Cost; 3800 3801 if (ST->hasAVX()) 3802 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3803 return Entry->Cost; 3804 3805 if (ST->hasSSE2()) 3806 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3807 return Entry->Cost; 3808 } 3809 3810 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3811 3812 MVT MTy = LT.second; 3813 3814 auto *ValVTy = cast<FixedVectorType>(ValTy); 3815 3816 // Special case: vXi8 mul reductions are performed as vXi16. 3817 if (ISD == ISD::MUL && MTy.getScalarType() == MVT::i8) { 3818 auto *WideSclTy = IntegerType::get(ValVTy->getContext(), 16); 3819 auto *WideVecTy = FixedVectorType::get(WideSclTy, ValVTy->getNumElements()); 3820 return getCastInstrCost(Instruction::ZExt, WideVecTy, ValTy, 3821 TargetTransformInfo::CastContextHint::None, 3822 CostKind) + 3823 getArithmeticReductionCost(Opcode, WideVecTy, CostKind); 3824 } 3825 3826 InstructionCost ArithmeticCost = 0; 3827 if (LT.first != 1 && MTy.isVector() && 3828 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3829 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3830 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3831 MTy.getVectorNumElements()); 3832 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3833 ArithmeticCost *= LT.first - 1; 3834 } 3835 3836 if (ST->isSLM()) 3837 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3838 return ArithmeticCost + Entry->Cost; 3839 3840 if (ST->hasAVX()) 3841 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3842 return ArithmeticCost + Entry->Cost; 3843 3844 if (ST->hasSSE2()) 3845 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3846 return ArithmeticCost + Entry->Cost; 3847 3848 // FIXME: These assume a naive kshift+binop lowering, which is probably 3849 // conservative in most cases. 3850 static const CostTblEntry AVX512BoolReduction[] = { 3851 { ISD::AND, MVT::v2i1, 3 }, 3852 { ISD::AND, MVT::v4i1, 5 }, 3853 { ISD::AND, MVT::v8i1, 7 }, 3854 { ISD::AND, MVT::v16i1, 9 }, 3855 { ISD::AND, MVT::v32i1, 11 }, 3856 { ISD::AND, MVT::v64i1, 13 }, 3857 { ISD::OR, MVT::v2i1, 3 }, 3858 { ISD::OR, MVT::v4i1, 5 }, 3859 { ISD::OR, MVT::v8i1, 7 }, 3860 { ISD::OR, MVT::v16i1, 9 }, 3861 { ISD::OR, MVT::v32i1, 11 }, 3862 { ISD::OR, MVT::v64i1, 13 }, 3863 }; 3864 3865 static const CostTblEntry AVX2BoolReduction[] = { 3866 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 3867 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 3868 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 3869 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 3870 }; 3871 3872 static const CostTblEntry AVX1BoolReduction[] = { 3873 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 3874 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 3875 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3876 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3877 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 3878 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 3879 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3880 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3881 }; 3882 3883 static const CostTblEntry SSE2BoolReduction[] = { 3884 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 3885 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 3886 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 3887 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 3888 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 3889 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 3890 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 3891 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 3892 }; 3893 3894 // Handle bool allof/anyof patterns. 3895 if (ValVTy->getElementType()->isIntegerTy(1)) { 3896 InstructionCost ArithmeticCost = 0; 3897 if (LT.first != 1 && MTy.isVector() && 3898 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3899 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3900 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3901 MTy.getVectorNumElements()); 3902 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3903 ArithmeticCost *= LT.first - 1; 3904 } 3905 3906 if (ST->hasAVX512()) 3907 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 3908 return ArithmeticCost + Entry->Cost; 3909 if (ST->hasAVX2()) 3910 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 3911 return ArithmeticCost + Entry->Cost; 3912 if (ST->hasAVX()) 3913 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 3914 return ArithmeticCost + Entry->Cost; 3915 if (ST->hasSSE2()) 3916 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 3917 return ArithmeticCost + Entry->Cost; 3918 3919 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, CostKind); 3920 } 3921 3922 unsigned NumVecElts = ValVTy->getNumElements(); 3923 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 3924 3925 // Special case power of 2 reductions where the scalar type isn't changed 3926 // by type legalization. 3927 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 3928 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, CostKind); 3929 3930 InstructionCost ReductionCost = 0; 3931 3932 auto *Ty = ValVTy; 3933 if (LT.first != 1 && MTy.isVector() && 3934 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3935 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3936 Ty = FixedVectorType::get(ValVTy->getElementType(), 3937 MTy.getVectorNumElements()); 3938 ReductionCost = getArithmeticInstrCost(Opcode, Ty, CostKind); 3939 ReductionCost *= LT.first - 1; 3940 NumVecElts = MTy.getVectorNumElements(); 3941 } 3942 3943 // Now handle reduction with the legal type, taking into account size changes 3944 // at each level. 3945 while (NumVecElts > 1) { 3946 // Determine the size of the remaining vector we need to reduce. 3947 unsigned Size = NumVecElts * ScalarSize; 3948 NumVecElts /= 2; 3949 // If we're reducing from 256/512 bits, use an extract_subvector. 3950 if (Size > 128) { 3951 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 3952 ReductionCost += 3953 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 3954 Ty = SubTy; 3955 } else if (Size == 128) { 3956 // Reducing from 128 bits is a permute of v2f64/v2i64. 3957 FixedVectorType *ShufTy; 3958 if (ValVTy->isFloatingPointTy()) 3959 ShufTy = 3960 FixedVectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 3961 else 3962 ShufTy = 3963 FixedVectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 3964 ReductionCost += 3965 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3966 } else if (Size == 64) { 3967 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3968 FixedVectorType *ShufTy; 3969 if (ValVTy->isFloatingPointTy()) 3970 ShufTy = 3971 FixedVectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 3972 else 3973 ShufTy = 3974 FixedVectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 3975 ReductionCost += 3976 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3977 } else { 3978 // Reducing from smaller size is a shift by immediate. 3979 auto *ShiftTy = FixedVectorType::get( 3980 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 3981 ReductionCost += getArithmeticInstrCost( 3982 Instruction::LShr, ShiftTy, CostKind, 3983 TargetTransformInfo::OK_AnyValue, 3984 TargetTransformInfo::OK_UniformConstantValue, 3985 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3986 } 3987 3988 // Add the arithmetic op for this level. 3989 ReductionCost += getArithmeticInstrCost(Opcode, Ty, CostKind); 3990 } 3991 3992 // Add the final extract element to the cost. 3993 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3994 } 3995 3996 InstructionCost X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, 3997 bool IsUnsigned) { 3998 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3999 4000 MVT MTy = LT.second; 4001 4002 int ISD; 4003 if (Ty->isIntOrIntVectorTy()) { 4004 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 4005 } else { 4006 assert(Ty->isFPOrFPVectorTy() && 4007 "Expected float point or integer vector type."); 4008 ISD = ISD::FMINNUM; 4009 } 4010 4011 static const CostTblEntry SSE1CostTbl[] = { 4012 {ISD::FMINNUM, MVT::v4f32, 1}, 4013 }; 4014 4015 static const CostTblEntry SSE2CostTbl[] = { 4016 {ISD::FMINNUM, MVT::v2f64, 1}, 4017 {ISD::SMIN, MVT::v8i16, 1}, 4018 {ISD::UMIN, MVT::v16i8, 1}, 4019 }; 4020 4021 static const CostTblEntry SSE41CostTbl[] = { 4022 {ISD::SMIN, MVT::v4i32, 1}, 4023 {ISD::UMIN, MVT::v4i32, 1}, 4024 {ISD::UMIN, MVT::v8i16, 1}, 4025 {ISD::SMIN, MVT::v16i8, 1}, 4026 }; 4027 4028 static const CostTblEntry SSE42CostTbl[] = { 4029 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 4030 }; 4031 4032 static const CostTblEntry AVX1CostTbl[] = { 4033 {ISD::FMINNUM, MVT::v8f32, 1}, 4034 {ISD::FMINNUM, MVT::v4f64, 1}, 4035 {ISD::SMIN, MVT::v8i32, 3}, 4036 {ISD::UMIN, MVT::v8i32, 3}, 4037 {ISD::SMIN, MVT::v16i16, 3}, 4038 {ISD::UMIN, MVT::v16i16, 3}, 4039 {ISD::SMIN, MVT::v32i8, 3}, 4040 {ISD::UMIN, MVT::v32i8, 3}, 4041 }; 4042 4043 static const CostTblEntry AVX2CostTbl[] = { 4044 {ISD::SMIN, MVT::v8i32, 1}, 4045 {ISD::UMIN, MVT::v8i32, 1}, 4046 {ISD::SMIN, MVT::v16i16, 1}, 4047 {ISD::UMIN, MVT::v16i16, 1}, 4048 {ISD::SMIN, MVT::v32i8, 1}, 4049 {ISD::UMIN, MVT::v32i8, 1}, 4050 }; 4051 4052 static const CostTblEntry AVX512CostTbl[] = { 4053 {ISD::FMINNUM, MVT::v16f32, 1}, 4054 {ISD::FMINNUM, MVT::v8f64, 1}, 4055 {ISD::SMIN, MVT::v2i64, 1}, 4056 {ISD::UMIN, MVT::v2i64, 1}, 4057 {ISD::SMIN, MVT::v4i64, 1}, 4058 {ISD::UMIN, MVT::v4i64, 1}, 4059 {ISD::SMIN, MVT::v8i64, 1}, 4060 {ISD::UMIN, MVT::v8i64, 1}, 4061 {ISD::SMIN, MVT::v16i32, 1}, 4062 {ISD::UMIN, MVT::v16i32, 1}, 4063 }; 4064 4065 static const CostTblEntry AVX512BWCostTbl[] = { 4066 {ISD::SMIN, MVT::v32i16, 1}, 4067 {ISD::UMIN, MVT::v32i16, 1}, 4068 {ISD::SMIN, MVT::v64i8, 1}, 4069 {ISD::UMIN, MVT::v64i8, 1}, 4070 }; 4071 4072 // If we have a native MIN/MAX instruction for this type, use it. 4073 if (ST->hasBWI()) 4074 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 4075 return LT.first * Entry->Cost; 4076 4077 if (ST->hasAVX512()) 4078 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 4079 return LT.first * Entry->Cost; 4080 4081 if (ST->hasAVX2()) 4082 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 4083 return LT.first * Entry->Cost; 4084 4085 if (ST->hasAVX()) 4086 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 4087 return LT.first * Entry->Cost; 4088 4089 if (ST->hasSSE42()) 4090 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 4091 return LT.first * Entry->Cost; 4092 4093 if (ST->hasSSE41()) 4094 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 4095 return LT.first * Entry->Cost; 4096 4097 if (ST->hasSSE2()) 4098 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 4099 return LT.first * Entry->Cost; 4100 4101 if (ST->hasSSE1()) 4102 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 4103 return LT.first * Entry->Cost; 4104 4105 unsigned CmpOpcode; 4106 if (Ty->isFPOrFPVectorTy()) { 4107 CmpOpcode = Instruction::FCmp; 4108 } else { 4109 assert(Ty->isIntOrIntVectorTy() && 4110 "expecting floating point or integer type for min/max reduction"); 4111 CmpOpcode = Instruction::ICmp; 4112 } 4113 4114 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4115 // Otherwise fall back to cmp+select. 4116 InstructionCost Result = 4117 getCmpSelInstrCost(CmpOpcode, Ty, CondTy, CmpInst::BAD_ICMP_PREDICATE, 4118 CostKind) + 4119 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, 4120 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4121 return Result; 4122 } 4123 4124 InstructionCost 4125 X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 4126 bool IsUnsigned, 4127 TTI::TargetCostKind CostKind) { 4128 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 4129 4130 MVT MTy = LT.second; 4131 4132 int ISD; 4133 if (ValTy->isIntOrIntVectorTy()) { 4134 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 4135 } else { 4136 assert(ValTy->isFPOrFPVectorTy() && 4137 "Expected float point or integer vector type."); 4138 ISD = ISD::FMINNUM; 4139 } 4140 4141 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 4142 // and make it as the cost. 4143 4144 static const CostTblEntry SSE2CostTblNoPairWise[] = { 4145 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 4146 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 4147 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 4148 }; 4149 4150 static const CostTblEntry SSE41CostTblNoPairWise[] = { 4151 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 4152 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 4153 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 4154 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 4155 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 4156 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 4157 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 4158 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 4159 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 4160 {ISD::SMIN, MVT::v16i8, 6}, 4161 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 4162 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 4163 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 4164 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 4165 }; 4166 4167 static const CostTblEntry AVX1CostTblNoPairWise[] = { 4168 {ISD::SMIN, MVT::v16i16, 6}, 4169 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 4170 {ISD::SMIN, MVT::v32i8, 8}, 4171 {ISD::UMIN, MVT::v32i8, 8}, 4172 }; 4173 4174 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 4175 {ISD::SMIN, MVT::v32i16, 8}, 4176 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 4177 {ISD::SMIN, MVT::v64i8, 10}, 4178 {ISD::UMIN, MVT::v64i8, 10}, 4179 }; 4180 4181 // Before legalizing the type, give a chance to look up illegal narrow types 4182 // in the table. 4183 // FIXME: Is there a better way to do this? 4184 EVT VT = TLI->getValueType(DL, ValTy); 4185 if (VT.isSimple()) { 4186 MVT MTy = VT.getSimpleVT(); 4187 if (ST->hasBWI()) 4188 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4189 return Entry->Cost; 4190 4191 if (ST->hasAVX()) 4192 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4193 return Entry->Cost; 4194 4195 if (ST->hasSSE41()) 4196 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4197 return Entry->Cost; 4198 4199 if (ST->hasSSE2()) 4200 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4201 return Entry->Cost; 4202 } 4203 4204 auto *ValVTy = cast<FixedVectorType>(ValTy); 4205 unsigned NumVecElts = ValVTy->getNumElements(); 4206 4207 auto *Ty = ValVTy; 4208 InstructionCost MinMaxCost = 0; 4209 if (LT.first != 1 && MTy.isVector() && 4210 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4211 // Type needs to be split. We need LT.first - 1 operations ops. 4212 Ty = FixedVectorType::get(ValVTy->getElementType(), 4213 MTy.getVectorNumElements()); 4214 auto *SubCondTy = FixedVectorType::get(CondTy->getElementType(), 4215 MTy.getVectorNumElements()); 4216 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4217 MinMaxCost *= LT.first - 1; 4218 NumVecElts = MTy.getVectorNumElements(); 4219 } 4220 4221 if (ST->hasBWI()) 4222 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4223 return MinMaxCost + Entry->Cost; 4224 4225 if (ST->hasAVX()) 4226 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4227 return MinMaxCost + Entry->Cost; 4228 4229 if (ST->hasSSE41()) 4230 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4231 return MinMaxCost + Entry->Cost; 4232 4233 if (ST->hasSSE2()) 4234 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4235 return MinMaxCost + Entry->Cost; 4236 4237 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 4238 4239 // Special case power of 2 reductions where the scalar type isn't changed 4240 // by type legalization. 4241 if (!isPowerOf2_32(ValVTy->getNumElements()) || 4242 ScalarSize != MTy.getScalarSizeInBits()) 4243 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsUnsigned, CostKind); 4244 4245 // Now handle reduction with the legal type, taking into account size changes 4246 // at each level. 4247 while (NumVecElts > 1) { 4248 // Determine the size of the remaining vector we need to reduce. 4249 unsigned Size = NumVecElts * ScalarSize; 4250 NumVecElts /= 2; 4251 // If we're reducing from 256/512 bits, use an extract_subvector. 4252 if (Size > 128) { 4253 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 4254 MinMaxCost += 4255 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 4256 Ty = SubTy; 4257 } else if (Size == 128) { 4258 // Reducing from 128 bits is a permute of v2f64/v2i64. 4259 VectorType *ShufTy; 4260 if (ValTy->isFloatingPointTy()) 4261 ShufTy = 4262 FixedVectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 4263 else 4264 ShufTy = FixedVectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 4265 MinMaxCost += 4266 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4267 } else if (Size == 64) { 4268 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 4269 FixedVectorType *ShufTy; 4270 if (ValTy->isFloatingPointTy()) 4271 ShufTy = FixedVectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 4272 else 4273 ShufTy = FixedVectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 4274 MinMaxCost += 4275 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4276 } else { 4277 // Reducing from smaller size is a shift by immediate. 4278 auto *ShiftTy = FixedVectorType::get( 4279 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 4280 MinMaxCost += getArithmeticInstrCost( 4281 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, 4282 TargetTransformInfo::OK_AnyValue, 4283 TargetTransformInfo::OK_UniformConstantValue, 4284 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 4285 } 4286 4287 // Add the arithmetic op for this level. 4288 auto *SubCondTy = 4289 FixedVectorType::get(CondTy->getElementType(), Ty->getNumElements()); 4290 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4291 } 4292 4293 // Add the final extract element to the cost. 4294 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 4295 } 4296 4297 /// Calculate the cost of materializing a 64-bit value. This helper 4298 /// method might only calculate a fraction of a larger immediate. Therefore it 4299 /// is valid to return a cost of ZERO. 4300 InstructionCost X86TTIImpl::getIntImmCost(int64_t Val) { 4301 if (Val == 0) 4302 return TTI::TCC_Free; 4303 4304 if (isInt<32>(Val)) 4305 return TTI::TCC_Basic; 4306 4307 return 2 * TTI::TCC_Basic; 4308 } 4309 4310 InstructionCost X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 4311 TTI::TargetCostKind CostKind) { 4312 assert(Ty->isIntegerTy()); 4313 4314 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4315 if (BitSize == 0) 4316 return ~0U; 4317 4318 // Never hoist constants larger than 128bit, because this might lead to 4319 // incorrect code generation or assertions in codegen. 4320 // Fixme: Create a cost model for types larger than i128 once the codegen 4321 // issues have been fixed. 4322 if (BitSize > 128) 4323 return TTI::TCC_Free; 4324 4325 if (Imm == 0) 4326 return TTI::TCC_Free; 4327 4328 // Sign-extend all constants to a multiple of 64-bit. 4329 APInt ImmVal = Imm; 4330 if (BitSize % 64 != 0) 4331 ImmVal = Imm.sext(alignTo(BitSize, 64)); 4332 4333 // Split the constant into 64-bit chunks and calculate the cost for each 4334 // chunk. 4335 InstructionCost Cost = 0; 4336 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 4337 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 4338 int64_t Val = Tmp.getSExtValue(); 4339 Cost += getIntImmCost(Val); 4340 } 4341 // We need at least one instruction to materialize the constant. 4342 return std::max<InstructionCost>(1, Cost); 4343 } 4344 4345 InstructionCost X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, 4346 const APInt &Imm, Type *Ty, 4347 TTI::TargetCostKind CostKind, 4348 Instruction *Inst) { 4349 assert(Ty->isIntegerTy()); 4350 4351 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4352 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4353 // here, so that constant hoisting will ignore this constant. 4354 if (BitSize == 0) 4355 return TTI::TCC_Free; 4356 4357 unsigned ImmIdx = ~0U; 4358 switch (Opcode) { 4359 default: 4360 return TTI::TCC_Free; 4361 case Instruction::GetElementPtr: 4362 // Always hoist the base address of a GetElementPtr. This prevents the 4363 // creation of new constants for every base constant that gets constant 4364 // folded with the offset. 4365 if (Idx == 0) 4366 return 2 * TTI::TCC_Basic; 4367 return TTI::TCC_Free; 4368 case Instruction::Store: 4369 ImmIdx = 0; 4370 break; 4371 case Instruction::ICmp: 4372 // This is an imperfect hack to prevent constant hoisting of 4373 // compares that might be trying to check if a 64-bit value fits in 4374 // 32-bits. The backend can optimize these cases using a right shift by 32. 4375 // Ideally we would check the compare predicate here. There also other 4376 // similar immediates the backend can use shifts for. 4377 if (Idx == 1 && Imm.getBitWidth() == 64) { 4378 uint64_t ImmVal = Imm.getZExtValue(); 4379 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 4380 return TTI::TCC_Free; 4381 } 4382 ImmIdx = 1; 4383 break; 4384 case Instruction::And: 4385 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 4386 // by using a 32-bit operation with implicit zero extension. Detect such 4387 // immediates here as the normal path expects bit 31 to be sign extended. 4388 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 4389 return TTI::TCC_Free; 4390 ImmIdx = 1; 4391 break; 4392 case Instruction::Add: 4393 case Instruction::Sub: 4394 // For add/sub, we can use the opposite instruction for INT32_MIN. 4395 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 4396 return TTI::TCC_Free; 4397 ImmIdx = 1; 4398 break; 4399 case Instruction::UDiv: 4400 case Instruction::SDiv: 4401 case Instruction::URem: 4402 case Instruction::SRem: 4403 // Division by constant is typically expanded later into a different 4404 // instruction sequence. This completely changes the constants. 4405 // Report them as "free" to stop ConstantHoist from marking them as opaque. 4406 return TTI::TCC_Free; 4407 case Instruction::Mul: 4408 case Instruction::Or: 4409 case Instruction::Xor: 4410 ImmIdx = 1; 4411 break; 4412 // Always return TCC_Free for the shift value of a shift instruction. 4413 case Instruction::Shl: 4414 case Instruction::LShr: 4415 case Instruction::AShr: 4416 if (Idx == 1) 4417 return TTI::TCC_Free; 4418 break; 4419 case Instruction::Trunc: 4420 case Instruction::ZExt: 4421 case Instruction::SExt: 4422 case Instruction::IntToPtr: 4423 case Instruction::PtrToInt: 4424 case Instruction::BitCast: 4425 case Instruction::PHI: 4426 case Instruction::Call: 4427 case Instruction::Select: 4428 case Instruction::Ret: 4429 case Instruction::Load: 4430 break; 4431 } 4432 4433 if (Idx == ImmIdx) { 4434 int NumConstants = divideCeil(BitSize, 64); 4435 InstructionCost Cost = X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4436 return (Cost <= NumConstants * TTI::TCC_Basic) 4437 ? static_cast<int>(TTI::TCC_Free) 4438 : Cost; 4439 } 4440 4441 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4442 } 4443 4444 InstructionCost X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 4445 const APInt &Imm, Type *Ty, 4446 TTI::TargetCostKind CostKind) { 4447 assert(Ty->isIntegerTy()); 4448 4449 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4450 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4451 // here, so that constant hoisting will ignore this constant. 4452 if (BitSize == 0) 4453 return TTI::TCC_Free; 4454 4455 switch (IID) { 4456 default: 4457 return TTI::TCC_Free; 4458 case Intrinsic::sadd_with_overflow: 4459 case Intrinsic::uadd_with_overflow: 4460 case Intrinsic::ssub_with_overflow: 4461 case Intrinsic::usub_with_overflow: 4462 case Intrinsic::smul_with_overflow: 4463 case Intrinsic::umul_with_overflow: 4464 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 4465 return TTI::TCC_Free; 4466 break; 4467 case Intrinsic::experimental_stackmap: 4468 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4469 return TTI::TCC_Free; 4470 break; 4471 case Intrinsic::experimental_patchpoint_void: 4472 case Intrinsic::experimental_patchpoint_i64: 4473 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4474 return TTI::TCC_Free; 4475 break; 4476 } 4477 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4478 } 4479 4480 InstructionCost X86TTIImpl::getCFInstrCost(unsigned Opcode, 4481 TTI::TargetCostKind CostKind, 4482 const Instruction *I) { 4483 if (CostKind != TTI::TCK_RecipThroughput) 4484 return Opcode == Instruction::PHI ? 0 : 1; 4485 // Branches are assumed to be predicted. 4486 return 0; 4487 } 4488 4489 int X86TTIImpl::getGatherOverhead() const { 4490 // Some CPUs have more overhead for gather. The specified overhead is relative 4491 // to the Load operation. "2" is the number provided by Intel architects. This 4492 // parameter is used for cost estimation of Gather Op and comparison with 4493 // other alternatives. 4494 // TODO: Remove the explicit hasAVX512()?, That would mean we would only 4495 // enable gather with a -march. 4496 if (ST->hasAVX512() || (ST->hasAVX2() && ST->hasFastGather())) 4497 return 2; 4498 4499 return 1024; 4500 } 4501 4502 int X86TTIImpl::getScatterOverhead() const { 4503 if (ST->hasAVX512()) 4504 return 2; 4505 4506 return 1024; 4507 } 4508 4509 // Return an average cost of Gather / Scatter instruction, maybe improved later. 4510 // FIXME: Add TargetCostKind support. 4511 InstructionCost X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, 4512 const Value *Ptr, Align Alignment, 4513 unsigned AddressSpace) { 4514 4515 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 4516 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4517 4518 // Try to reduce index size from 64 bit (default for GEP) 4519 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 4520 // operation will use 16 x 64 indices which do not fit in a zmm and needs 4521 // to split. Also check that the base pointer is the same for all lanes, 4522 // and that there's at most one variable index. 4523 auto getIndexSizeInBits = [](const Value *Ptr, const DataLayout &DL) { 4524 unsigned IndexSize = DL.getPointerSizeInBits(); 4525 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 4526 if (IndexSize < 64 || !GEP) 4527 return IndexSize; 4528 4529 unsigned NumOfVarIndices = 0; 4530 const Value *Ptrs = GEP->getPointerOperand(); 4531 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 4532 return IndexSize; 4533 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 4534 if (isa<Constant>(GEP->getOperand(i))) 4535 continue; 4536 Type *IndxTy = GEP->getOperand(i)->getType(); 4537 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 4538 IndxTy = IndexVTy->getElementType(); 4539 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 4540 !isa<SExtInst>(GEP->getOperand(i))) || 4541 ++NumOfVarIndices > 1) 4542 return IndexSize; // 64 4543 } 4544 return (unsigned)32; 4545 }; 4546 4547 // Trying to reduce IndexSize to 32 bits for vector 16. 4548 // By default the IndexSize is equal to pointer size. 4549 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 4550 ? getIndexSizeInBits(Ptr, DL) 4551 : DL.getPointerSizeInBits(); 4552 4553 auto *IndexVTy = FixedVectorType::get( 4554 IntegerType::get(SrcVTy->getContext(), IndexSize), VF); 4555 std::pair<InstructionCost, MVT> IdxsLT = 4556 TLI->getTypeLegalizationCost(DL, IndexVTy); 4557 std::pair<InstructionCost, MVT> SrcLT = 4558 TLI->getTypeLegalizationCost(DL, SrcVTy); 4559 InstructionCost::CostType SplitFactor = 4560 *std::max(IdxsLT.first, SrcLT.first).getValue(); 4561 if (SplitFactor > 1) { 4562 // Handle splitting of vector of pointers 4563 auto *SplitSrcTy = 4564 FixedVectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 4565 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 4566 AddressSpace); 4567 } 4568 4569 // The gather / scatter cost is given by Intel architects. It is a rough 4570 // number since we are looking at one instruction in a time. 4571 const int GSOverhead = (Opcode == Instruction::Load) 4572 ? getGatherOverhead() 4573 : getScatterOverhead(); 4574 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4575 MaybeAlign(Alignment), AddressSpace, 4576 TTI::TCK_RecipThroughput); 4577 } 4578 4579 /// Return the cost of full scalarization of gather / scatter operation. 4580 /// 4581 /// Opcode - Load or Store instruction. 4582 /// SrcVTy - The type of the data vector that should be gathered or scattered. 4583 /// VariableMask - The mask is non-constant at compile time. 4584 /// Alignment - Alignment for one element. 4585 /// AddressSpace - pointer[s] address space. 4586 /// 4587 /// FIXME: Add TargetCostKind support. 4588 InstructionCost X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 4589 bool VariableMask, Align Alignment, 4590 unsigned AddressSpace) { 4591 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4592 APInt DemandedElts = APInt::getAllOnesValue(VF); 4593 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4594 4595 InstructionCost MaskUnpackCost = 0; 4596 if (VariableMask) { 4597 auto *MaskTy = 4598 FixedVectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 4599 MaskUnpackCost = 4600 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 4601 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 4602 Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), nullptr, 4603 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4604 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 4605 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 4606 } 4607 4608 // The cost of the scalar loads/stores. 4609 InstructionCost MemoryOpCost = 4610 VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4611 MaybeAlign(Alignment), AddressSpace, CostKind); 4612 4613 InstructionCost InsertExtractCost = 0; 4614 if (Opcode == Instruction::Load) 4615 for (unsigned i = 0; i < VF; ++i) 4616 // Add the cost of inserting each scalar load into the vector 4617 InsertExtractCost += 4618 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 4619 else 4620 for (unsigned i = 0; i < VF; ++i) 4621 // Add the cost of extracting each element out of the data vector 4622 InsertExtractCost += 4623 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 4624 4625 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 4626 } 4627 4628 /// Calculate the cost of Gather / Scatter operation 4629 InstructionCost X86TTIImpl::getGatherScatterOpCost( 4630 unsigned Opcode, Type *SrcVTy, const Value *Ptr, bool VariableMask, 4631 Align Alignment, TTI::TargetCostKind CostKind, 4632 const Instruction *I = nullptr) { 4633 if (CostKind != TTI::TCK_RecipThroughput) { 4634 if ((Opcode == Instruction::Load && 4635 isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4636 (Opcode == Instruction::Store && 4637 isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4638 return 1; 4639 return BaseT::getGatherScatterOpCost(Opcode, SrcVTy, Ptr, VariableMask, 4640 Alignment, CostKind, I); 4641 } 4642 4643 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 4644 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 4645 if (!PtrTy && Ptr->getType()->isVectorTy()) 4646 PtrTy = dyn_cast<PointerType>( 4647 cast<VectorType>(Ptr->getType())->getElementType()); 4648 assert(PtrTy && "Unexpected type for Ptr argument"); 4649 unsigned AddressSpace = PtrTy->getAddressSpace(); 4650 4651 if ((Opcode == Instruction::Load && 4652 !isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4653 (Opcode == Instruction::Store && 4654 !isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4655 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 4656 AddressSpace); 4657 4658 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 4659 } 4660 4661 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 4662 TargetTransformInfo::LSRCost &C2) { 4663 // X86 specific here are "instruction number 1st priority". 4664 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 4665 C1.NumIVMuls, C1.NumBaseAdds, 4666 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 4667 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 4668 C2.NumIVMuls, C2.NumBaseAdds, 4669 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 4670 } 4671 4672 bool X86TTIImpl::canMacroFuseCmp() { 4673 return ST->hasMacroFusion() || ST->hasBranchFusion(); 4674 } 4675 4676 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, Align Alignment) { 4677 if (!ST->hasAVX()) 4678 return false; 4679 4680 // The backend can't handle a single element vector. 4681 if (isa<VectorType>(DataTy) && 4682 cast<FixedVectorType>(DataTy)->getNumElements() == 1) 4683 return false; 4684 Type *ScalarTy = DataTy->getScalarType(); 4685 4686 if (ScalarTy->isPointerTy()) 4687 return true; 4688 4689 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4690 return true; 4691 4692 if (!ScalarTy->isIntegerTy()) 4693 return false; 4694 4695 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4696 return IntWidth == 32 || IntWidth == 64 || 4697 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 4698 } 4699 4700 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, Align Alignment) { 4701 return isLegalMaskedLoad(DataType, Alignment); 4702 } 4703 4704 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 4705 unsigned DataSize = DL.getTypeStoreSize(DataType); 4706 // The only supported nontemporal loads are for aligned vectors of 16 or 32 4707 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 4708 // (the equivalent stores only require AVX). 4709 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 4710 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 4711 4712 return false; 4713 } 4714 4715 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 4716 unsigned DataSize = DL.getTypeStoreSize(DataType); 4717 4718 // SSE4A supports nontemporal stores of float and double at arbitrary 4719 // alignment. 4720 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 4721 return true; 4722 4723 // Besides the SSE4A subtarget exception above, only aligned stores are 4724 // available nontemporaly on any other subtarget. And only stores with a size 4725 // of 4..32 bytes (powers of 2, only) are permitted. 4726 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 4727 !isPowerOf2_32(DataSize)) 4728 return false; 4729 4730 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 4731 // loads require AVX2). 4732 if (DataSize == 32) 4733 return ST->hasAVX(); 4734 else if (DataSize == 16) 4735 return ST->hasSSE1(); 4736 return true; 4737 } 4738 4739 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 4740 if (!isa<VectorType>(DataTy)) 4741 return false; 4742 4743 if (!ST->hasAVX512()) 4744 return false; 4745 4746 // The backend can't handle a single element vector. 4747 if (cast<FixedVectorType>(DataTy)->getNumElements() == 1) 4748 return false; 4749 4750 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 4751 4752 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4753 return true; 4754 4755 if (!ScalarTy->isIntegerTy()) 4756 return false; 4757 4758 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4759 return IntWidth == 32 || IntWidth == 64 || 4760 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 4761 } 4762 4763 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 4764 return isLegalMaskedExpandLoad(DataTy); 4765 } 4766 4767 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, Align Alignment) { 4768 // Some CPUs have better gather performance than others. 4769 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 4770 // enable gather with a -march. 4771 if (!(ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()))) 4772 return false; 4773 4774 // This function is called now in two cases: from the Loop Vectorizer 4775 // and from the Scalarizer. 4776 // When the Loop Vectorizer asks about legality of the feature, 4777 // the vectorization factor is not calculated yet. The Loop Vectorizer 4778 // sends a scalar type and the decision is based on the width of the 4779 // scalar element. 4780 // Later on, the cost model will estimate usage this intrinsic based on 4781 // the vector type. 4782 // The Scalarizer asks again about legality. It sends a vector type. 4783 // In this case we can reject non-power-of-2 vectors. 4784 // We also reject single element vectors as the type legalizer can't 4785 // scalarize it. 4786 if (auto *DataVTy = dyn_cast<FixedVectorType>(DataTy)) { 4787 unsigned NumElts = DataVTy->getNumElements(); 4788 if (NumElts == 1) 4789 return false; 4790 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 4791 // Vector-4 of gather/scatter instruction does not exist on KNL. 4792 // We can extend it to 8 elements, but zeroing upper bits of 4793 // the mask vector will add more instructions. Right now we give the scalar 4794 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter 4795 // instruction is better in the VariableMask case. 4796 if (ST->hasAVX512() && (NumElts == 2 || (NumElts == 4 && !ST->hasVLX()))) 4797 return false; 4798 } 4799 Type *ScalarTy = DataTy->getScalarType(); 4800 if (ScalarTy->isPointerTy()) 4801 return true; 4802 4803 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4804 return true; 4805 4806 if (!ScalarTy->isIntegerTy()) 4807 return false; 4808 4809 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4810 return IntWidth == 32 || IntWidth == 64; 4811 } 4812 4813 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, Align Alignment) { 4814 // AVX2 doesn't support scatter 4815 if (!ST->hasAVX512()) 4816 return false; 4817 return isLegalMaskedGather(DataType, Alignment); 4818 } 4819 4820 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 4821 EVT VT = TLI->getValueType(DL, DataType); 4822 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 4823 } 4824 4825 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 4826 return false; 4827 } 4828 4829 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 4830 const Function *Callee) const { 4831 const TargetMachine &TM = getTLI()->getTargetMachine(); 4832 4833 // Work this as a subsetting of subtarget features. 4834 const FeatureBitset &CallerBits = 4835 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 4836 const FeatureBitset &CalleeBits = 4837 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 4838 4839 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 4840 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 4841 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 4842 } 4843 4844 bool X86TTIImpl::areFunctionArgsABICompatible( 4845 const Function *Caller, const Function *Callee, 4846 SmallPtrSetImpl<Argument *> &Args) const { 4847 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args)) 4848 return false; 4849 4850 // If we get here, we know the target features match. If one function 4851 // considers 512-bit vectors legal and the other does not, consider them 4852 // incompatible. 4853 const TargetMachine &TM = getTLI()->getTargetMachine(); 4854 4855 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 4856 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs()) 4857 return true; 4858 4859 // Consider the arguments compatible if they aren't vectors or aggregates. 4860 // FIXME: Look at the size of vectors. 4861 // FIXME: Look at the element types of aggregates to see if there are vectors. 4862 // FIXME: The API of this function seems intended to allow arguments 4863 // to be removed from the set, but the caller doesn't check if the set 4864 // becomes empty so that may not work in practice. 4865 return llvm::none_of(Args, [](Argument *A) { 4866 auto *EltTy = cast<PointerType>(A->getType())->getElementType(); 4867 return EltTy->isVectorTy() || EltTy->isAggregateType(); 4868 }); 4869 } 4870 4871 X86TTIImpl::TTI::MemCmpExpansionOptions 4872 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 4873 TTI::MemCmpExpansionOptions Options; 4874 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 4875 Options.NumLoadsPerBlock = 2; 4876 // All GPR and vector loads can be unaligned. 4877 Options.AllowOverlappingLoads = true; 4878 if (IsZeroCmp) { 4879 // Only enable vector loads for equality comparison. Right now the vector 4880 // version is not as fast for three way compare (see #33329). 4881 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 4882 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 4883 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 4884 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 4885 } 4886 if (ST->is64Bit()) { 4887 Options.LoadSizes.push_back(8); 4888 } 4889 Options.LoadSizes.push_back(4); 4890 Options.LoadSizes.push_back(2); 4891 Options.LoadSizes.push_back(1); 4892 return Options; 4893 } 4894 4895 bool X86TTIImpl::enableInterleavedAccessVectorization() { 4896 // TODO: We expect this to be beneficial regardless of arch, 4897 // but there are currently some unexplained performance artifacts on Atom. 4898 // As a temporary solution, disable on Atom. 4899 return !(ST->isAtom()); 4900 } 4901 4902 // Get estimation for interleaved load/store operations for AVX2. 4903 // \p Factor is the interleaved-access factor (stride) - number of 4904 // (interleaved) elements in the group. 4905 // \p Indices contains the indices for a strided load: when the 4906 // interleaved load has gaps they indicate which elements are used. 4907 // If Indices is empty (or if the number of indices is equal to the size 4908 // of the interleaved-access as given in \p Factor) the access has no gaps. 4909 // 4910 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 4911 // computing the cost using a generic formula as a function of generic 4912 // shuffles. We therefore use a lookup table instead, filled according to 4913 // the instruction sequences that codegen currently generates. 4914 InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2( 4915 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 4916 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 4917 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 4918 4919 if (UseMaskForCond || UseMaskForGaps) 4920 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4921 Alignment, AddressSpace, CostKind, 4922 UseMaskForCond, UseMaskForGaps); 4923 4924 // We currently Support only fully-interleaved groups, with no gaps. 4925 // TODO: Support also strided loads (interleaved-groups with gaps). 4926 if (Indices.size() && Indices.size() != Factor) 4927 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4928 Alignment, AddressSpace, CostKind); 4929 4930 // VecTy for interleave memop is <VF*Factor x Elt>. 4931 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4932 // VecTy = <12 x i32>. 4933 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4934 4935 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 4936 // the VF=2, while v2i128 is an unsupported MVT vector type 4937 // (see MachineValueType.h::getVectorVT()). 4938 if (!LegalVT.isVector()) 4939 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4940 Alignment, AddressSpace, CostKind); 4941 4942 unsigned VF = VecTy->getNumElements() / Factor; 4943 Type *ScalarTy = VecTy->getElementType(); 4944 // Deduplicate entries, model floats/pointers as appropriately-sized integers. 4945 if (!ScalarTy->isIntegerTy()) 4946 ScalarTy = 4947 Type::getIntNTy(ScalarTy->getContext(), DL.getTypeSizeInBits(ScalarTy)); 4948 4949 // Get the cost of all the memory operations. 4950 InstructionCost MemOpCosts = getMemoryOpCost( 4951 Opcode, VecTy, MaybeAlign(Alignment), AddressSpace, CostKind); 4952 4953 auto *VT = FixedVectorType::get(ScalarTy, VF); 4954 EVT ETy = TLI->getValueType(DL, VT); 4955 if (!ETy.isSimple()) 4956 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4957 Alignment, AddressSpace, CostKind); 4958 4959 // TODO: Complete for other data-types and strides. 4960 // Each combination of Stride, element bit width and VF results in a different 4961 // sequence; The cost tables are therefore accessed with: 4962 // Factor (stride) and VectorType=VFxiN. 4963 // The Cost accounts only for the shuffle sequence; 4964 // The cost of the loads/stores is accounted for separately. 4965 // 4966 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 4967 {2, MVT::v4i64, 6}, // (load 8i64 and) deinterleave into 2 x 4i64 4968 4969 {3, MVT::v2i8, 10}, // (load 6i8 and) deinterleave into 3 x 2i8 4970 {3, MVT::v4i8, 4}, // (load 12i8 and) deinterleave into 3 x 4i8 4971 {3, MVT::v8i8, 9}, // (load 24i8 and) deinterleave into 3 x 8i8 4972 {3, MVT::v16i8, 11}, // (load 48i8 and) deinterleave into 3 x 16i8 4973 {3, MVT::v32i8, 13}, // (load 96i8 and) deinterleave into 3 x 32i8 4974 4975 {3, MVT::v8i32, 17}, // (load 24i32 and) deinterleave into 3 x 8i32 4976 4977 {4, MVT::v2i8, 12}, // (load 8i8 and) deinterleave into 4 x 2i8 4978 {4, MVT::v4i8, 4}, // (load 16i8 and) deinterleave into 4 x 4i8 4979 {4, MVT::v8i8, 20}, // (load 32i8 and) deinterleave into 4 x 8i8 4980 {4, MVT::v16i8, 39}, // (load 64i8 and) deinterleave into 4 x 16i8 4981 {4, MVT::v32i8, 80}, // (load 128i8 and) deinterleave into 4 x 32i8 4982 4983 {8, MVT::v8i32, 40} // (load 64i32 and) deinterleave into 8 x 8i32 4984 }; 4985 4986 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 4987 {2, MVT::v4i64, 6}, // interleave 2 x 4i64 into 8i64 (and store) 4988 4989 {3, MVT::v2i8, 7}, // interleave 3 x 2i8 into 6i8 (and store) 4990 {3, MVT::v4i8, 8}, // interleave 3 x 4i8 into 12i8 (and store) 4991 {3, MVT::v8i8, 11}, // interleave 3 x 8i8 into 24i8 (and store) 4992 {3, MVT::v16i8, 11}, // interleave 3 x 16i8 into 48i8 (and store) 4993 {3, MVT::v32i8, 13}, // interleave 3 x 32i8 into 96i8 (and store) 4994 4995 {4, MVT::v2i8, 12}, // interleave 4 x 2i8 into 8i8 (and store) 4996 {4, MVT::v4i8, 9}, // interleave 4 x 4i8 into 16i8 (and store) 4997 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 4998 {4, MVT::v16i8, 10}, // interleave 4 x 16i8 into 64i8 (and store) 4999 {4, MVT::v32i8, 12} // interleave 4 x 32i8 into 128i8 (and store) 5000 }; 5001 5002 if (Opcode == Instruction::Load) { 5003 if (const auto *Entry = 5004 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 5005 return MemOpCosts + Entry->Cost; 5006 } else { 5007 assert(Opcode == Instruction::Store && 5008 "Expected Store Instruction at this point"); 5009 if (const auto *Entry = 5010 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 5011 return MemOpCosts + Entry->Cost; 5012 } 5013 5014 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5015 Alignment, AddressSpace, CostKind); 5016 } 5017 5018 // Get estimation for interleaved load/store operations and strided load. 5019 // \p Indices contains indices for strided load. 5020 // \p Factor - the factor of interleaving. 5021 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 5022 InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX512( 5023 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 5024 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 5025 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 5026 5027 if (UseMaskForCond || UseMaskForGaps) 5028 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5029 Alignment, AddressSpace, CostKind, 5030 UseMaskForCond, UseMaskForGaps); 5031 5032 // VecTy for interleave memop is <VF*Factor x Elt>. 5033 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 5034 // VecTy = <12 x i32>. 5035 5036 // Calculate the number of memory operations (NumOfMemOps), required 5037 // for load/store the VecTy. 5038 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 5039 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 5040 unsigned LegalVTSize = LegalVT.getStoreSize(); 5041 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 5042 5043 // Get the cost of one memory operation. 5044 auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(), 5045 LegalVT.getVectorNumElements()); 5046 InstructionCost MemOpCost = getMemoryOpCost( 5047 Opcode, SingleMemOpTy, MaybeAlign(Alignment), AddressSpace, CostKind); 5048 5049 unsigned VF = VecTy->getNumElements() / Factor; 5050 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 5051 5052 if (Opcode == Instruction::Load) { 5053 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 5054 // contain the cost of the optimized shuffle sequence that the 5055 // X86InterleavedAccess pass will generate. 5056 // The cost of loads and stores are computed separately from the table. 5057 5058 // X86InterleavedAccess support only the following interleaved-access group. 5059 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 5060 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 5061 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 5062 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 5063 }; 5064 5065 if (const auto *Entry = 5066 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 5067 return NumOfMemOps * MemOpCost + Entry->Cost; 5068 //If an entry does not exist, fallback to the default implementation. 5069 5070 // Kind of shuffle depends on number of loaded values. 5071 // If we load the entire data in one register, we can use a 1-src shuffle. 5072 // Otherwise, we'll merge 2 sources in each operation. 5073 TTI::ShuffleKind ShuffleKind = 5074 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 5075 5076 InstructionCost ShuffleCost = 5077 getShuffleCost(ShuffleKind, SingleMemOpTy, None, 0, nullptr); 5078 5079 unsigned NumOfLoadsInInterleaveGrp = 5080 Indices.size() ? Indices.size() : Factor; 5081 auto *ResultTy = FixedVectorType::get(VecTy->getElementType(), 5082 VecTy->getNumElements() / Factor); 5083 InstructionCost NumOfResults = 5084 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 5085 NumOfLoadsInInterleaveGrp; 5086 5087 // About a half of the loads may be folded in shuffles when we have only 5088 // one result. If we have more than one result, we do not fold loads at all. 5089 unsigned NumOfUnfoldedLoads = 5090 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 5091 5092 // Get a number of shuffle operations per result. 5093 unsigned NumOfShufflesPerResult = 5094 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 5095 5096 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 5097 // When we have more than one destination, we need additional instructions 5098 // to keep sources. 5099 InstructionCost NumOfMoves = 0; 5100 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 5101 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 5102 5103 InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 5104 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 5105 5106 return Cost; 5107 } 5108 5109 // Store. 5110 assert(Opcode == Instruction::Store && 5111 "Expected Store Instruction at this point"); 5112 // X86InterleavedAccess support only the following interleaved-access group. 5113 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 5114 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 5115 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 5116 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 5117 5118 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 5119 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 5120 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 5121 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 5122 }; 5123 5124 if (const auto *Entry = 5125 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 5126 return NumOfMemOps * MemOpCost + Entry->Cost; 5127 //If an entry does not exist, fallback to the default implementation. 5128 5129 // There is no strided stores meanwhile. And store can't be folded in 5130 // shuffle. 5131 unsigned NumOfSources = Factor; // The number of values to be merged. 5132 InstructionCost ShuffleCost = 5133 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, None, 0, nullptr); 5134 unsigned NumOfShufflesPerStore = NumOfSources - 1; 5135 5136 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 5137 // We need additional instructions to keep sources. 5138 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 5139 InstructionCost Cost = 5140 NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 5141 NumOfMoves; 5142 return Cost; 5143 } 5144 5145 InstructionCost X86TTIImpl::getInterleavedMemoryOpCost( 5146 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, 5147 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, 5148 bool UseMaskForCond, bool UseMaskForGaps) { 5149 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 5150 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 5151 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 5152 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 5153 return true; 5154 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 5155 return HasBW; 5156 return false; 5157 }; 5158 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 5159 return getInterleavedMemoryOpCostAVX512( 5160 Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment, 5161 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 5162 if (ST->hasAVX2()) 5163 return getInterleavedMemoryOpCostAVX2( 5164 Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment, 5165 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 5166 5167 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5168 Alignment, AddressSpace, CostKind, 5169 UseMaskForCond, UseMaskForGaps); 5170 } 5171