1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// \file 10 /// This file implements a TargetTransformInfo analysis pass specific to the 11 /// X86 target machine. It uses the target's detailed information to provide 12 /// more precise answers to certain TTI queries, while letting the target 13 /// independent and default TTI implementations handle the rest. 14 /// 15 //===----------------------------------------------------------------------===// 16 /// About Cost Model numbers used below it's necessary to say the following: 17 /// the numbers correspond to some "generic" X86 CPU instead of usage of 18 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 19 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 20 /// the lookups below the cost is based on Nehalem as that was the first CPU 21 /// to support that feature level and thus has most likely the worst case cost. 22 /// Some examples of other technologies/CPUs: 23 /// SSE 3 - Pentium4 / Athlon64 24 /// SSE 4.1 - Penryn 25 /// SSE 4.2 - Nehalem 26 /// AVX - Sandy Bridge 27 /// AVX2 - Haswell 28 /// AVX-512 - Xeon Phi / Skylake 29 /// And some examples of instruction target dependent costs (latency) 30 /// divss sqrtss rsqrtss 31 /// AMD K7 11-16 19 3 32 /// Piledriver 9-24 13-15 5 33 /// Jaguar 14 16 2 34 /// Pentium II,III 18 30 2 35 /// Nehalem 7-14 7-18 3 36 /// Haswell 10-13 11 5 37 /// TODO: Develop and implement the target dependent cost model and 38 /// specialize cost numbers for different Cost Model Targets such as throughput, 39 /// code size, latency and uop count. 40 //===----------------------------------------------------------------------===// 41 42 #include "X86TargetTransformInfo.h" 43 #include "llvm/Analysis/TargetTransformInfo.h" 44 #include "llvm/CodeGen/BasicTTIImpl.h" 45 #include "llvm/IR/IntrinsicInst.h" 46 #include "llvm/Support/Debug.h" 47 #include "llvm/Target/CostTable.h" 48 #include "llvm/Target/TargetLowering.h" 49 50 using namespace llvm; 51 52 #define DEBUG_TYPE "x86tti" 53 54 //===----------------------------------------------------------------------===// 55 // 56 // X86 cost model. 57 // 58 //===----------------------------------------------------------------------===// 59 60 TargetTransformInfo::PopcntSupportKind 61 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 62 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 63 // TODO: Currently the __builtin_popcount() implementation using SSE3 64 // instructions is inefficient. Once the problem is fixed, we should 65 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 66 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 67 } 68 69 unsigned X86TTIImpl::getNumberOfRegisters(bool Vector) { 70 if (Vector && !ST->hasSSE1()) 71 return 0; 72 73 if (ST->is64Bit()) { 74 if (Vector && ST->hasAVX512()) 75 return 32; 76 return 16; 77 } 78 return 8; 79 } 80 81 unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) { 82 if (Vector) { 83 if (ST->hasAVX512()) return 512; 84 if (ST->hasAVX()) return 256; 85 if (ST->hasSSE1()) return 128; 86 return 0; 87 } 88 89 if (ST->is64Bit()) 90 return 64; 91 92 return 32; 93 } 94 95 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 96 // If the loop will not be vectorized, don't interleave the loop. 97 // Let regular unroll to unroll the loop, which saves the overflow 98 // check and memory check cost. 99 if (VF == 1) 100 return 1; 101 102 if (ST->isAtom()) 103 return 1; 104 105 // Sandybridge and Haswell have multiple execution ports and pipelined 106 // vector units. 107 if (ST->hasAVX()) 108 return 4; 109 110 return 2; 111 } 112 113 int X86TTIImpl::getArithmeticInstrCost( 114 unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info, 115 TTI::OperandValueKind Op2Info, TTI::OperandValueProperties Opd1PropInfo, 116 TTI::OperandValueProperties Opd2PropInfo) { 117 // Legalize the type. 118 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 119 120 int ISD = TLI->InstructionOpcodeToISD(Opcode); 121 assert(ISD && "Invalid opcode"); 122 123 if (ISD == ISD::SDIV && 124 Op2Info == TargetTransformInfo::OK_UniformConstantValue && 125 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 126 // On X86, vector signed division by constants power-of-two are 127 // normally expanded to the sequence SRA + SRL + ADD + SRA. 128 // The OperandValue properties many not be same as that of previous 129 // operation;conservatively assume OP_None. 130 int Cost = 2 * getArithmeticInstrCost(Instruction::AShr, Ty, Op1Info, 131 Op2Info, TargetTransformInfo::OP_None, 132 TargetTransformInfo::OP_None); 133 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 134 TargetTransformInfo::OP_None, 135 TargetTransformInfo::OP_None); 136 Cost += getArithmeticInstrCost(Instruction::Add, Ty, Op1Info, Op2Info, 137 TargetTransformInfo::OP_None, 138 TargetTransformInfo::OP_None); 139 140 return Cost; 141 } 142 143 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 144 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 145 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 146 }; 147 148 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 149 ST->hasBWI()) { 150 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 151 LT.second)) 152 return LT.first * Entry->Cost; 153 } 154 155 static const CostTblEntry AVX512UniformConstCostTable[] = { 156 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 157 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 158 }; 159 160 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 161 ST->hasAVX512()) { 162 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 163 LT.second)) 164 return LT.first * Entry->Cost; 165 } 166 167 static const CostTblEntry AVX2UniformConstCostTable[] = { 168 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 169 170 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 171 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 172 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 173 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 174 }; 175 176 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 177 ST->hasAVX2()) { 178 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 179 LT.second)) 180 return LT.first * Entry->Cost; 181 } 182 183 static const CostTblEntry SSE2UniformConstCostTable[] = { 184 { ISD::SDIV, MVT::v16i16, 12 }, // pmulhw sequence 185 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 186 { ISD::UDIV, MVT::v16i16, 12 }, // pmulhuw sequence 187 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 188 { ISD::SDIV, MVT::v8i32, 38 }, // pmuludq sequence 189 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 190 { ISD::UDIV, MVT::v8i32, 30 }, // pmuludq sequence 191 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 192 }; 193 194 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 195 ST->hasSSE2()) { 196 // pmuldq sequence. 197 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 198 return LT.first * 30; 199 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 200 return LT.first * 15; 201 202 if (const auto *Entry = CostTableLookup(SSE2UniformConstCostTable, ISD, 203 LT.second)) 204 return LT.first * Entry->Cost; 205 } 206 207 static const CostTblEntry AVX512BWCostTable[] = { 208 // Vectorizing division is a bad idea. See the SSE2 table for more comments. 209 { ISD::SDIV, MVT::v64i8, 64*20 }, 210 { ISD::SDIV, MVT::v32i16, 32*20 }, 211 { ISD::SDIV, MVT::v16i32, 16*20 }, 212 { ISD::SDIV, MVT::v8i64, 8*20 }, 213 { ISD::UDIV, MVT::v64i8, 64*20 }, 214 { ISD::UDIV, MVT::v32i16, 32*20 }, 215 { ISD::UDIV, MVT::v16i32, 16*20 }, 216 { ISD::UDIV, MVT::v8i64, 8*20 }, 217 }; 218 219 // Look for AVX512BW lowering tricks for custom cases. 220 if (ST->hasBWI()) { 221 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, 222 LT.second)) 223 return LT.first * Entry->Cost; 224 } 225 226 static const CostTblEntry AVX512CostTable[] = { 227 { ISD::SHL, MVT::v16i32, 1 }, 228 { ISD::SRL, MVT::v16i32, 1 }, 229 { ISD::SRA, MVT::v16i32, 1 }, 230 { ISD::SHL, MVT::v8i64, 1 }, 231 { ISD::SRL, MVT::v8i64, 1 }, 232 { ISD::SRA, MVT::v8i64, 1 }, 233 }; 234 235 if (ST->hasAVX512()) { 236 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 237 return LT.first * Entry->Cost; 238 } 239 240 static const CostTblEntry AVX2CostTable[] = { 241 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 242 // customize them to detect the cases where shift amount is a scalar one. 243 { ISD::SHL, MVT::v4i32, 1 }, 244 { ISD::SRL, MVT::v4i32, 1 }, 245 { ISD::SRA, MVT::v4i32, 1 }, 246 { ISD::SHL, MVT::v8i32, 1 }, 247 { ISD::SRL, MVT::v8i32, 1 }, 248 { ISD::SRA, MVT::v8i32, 1 }, 249 { ISD::SHL, MVT::v2i64, 1 }, 250 { ISD::SRL, MVT::v2i64, 1 }, 251 { ISD::SHL, MVT::v4i64, 1 }, 252 { ISD::SRL, MVT::v4i64, 1 }, 253 }; 254 255 // Look for AVX2 lowering tricks. 256 if (ST->hasAVX2()) { 257 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 258 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 259 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 260 // On AVX2, a packed v16i16 shift left by a constant build_vector 261 // is lowered into a vector multiply (vpmullw). 262 return LT.first; 263 264 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 265 return LT.first * Entry->Cost; 266 } 267 268 static const CostTblEntry XOPCostTable[] = { 269 // 128bit shifts take 1cy, but right shifts require negation beforehand. 270 { ISD::SHL, MVT::v16i8, 1 }, 271 { ISD::SRL, MVT::v16i8, 2 }, 272 { ISD::SRA, MVT::v16i8, 2 }, 273 { ISD::SHL, MVT::v8i16, 1 }, 274 { ISD::SRL, MVT::v8i16, 2 }, 275 { ISD::SRA, MVT::v8i16, 2 }, 276 { ISD::SHL, MVT::v4i32, 1 }, 277 { ISD::SRL, MVT::v4i32, 2 }, 278 { ISD::SRA, MVT::v4i32, 2 }, 279 { ISD::SHL, MVT::v2i64, 1 }, 280 { ISD::SRL, MVT::v2i64, 2 }, 281 { ISD::SRA, MVT::v2i64, 2 }, 282 // 256bit shifts require splitting if AVX2 didn't catch them above. 283 { ISD::SHL, MVT::v32i8, 2 }, 284 { ISD::SRL, MVT::v32i8, 4 }, 285 { ISD::SRA, MVT::v32i8, 4 }, 286 { ISD::SHL, MVT::v16i16, 2 }, 287 { ISD::SRL, MVT::v16i16, 4 }, 288 { ISD::SRA, MVT::v16i16, 4 }, 289 { ISD::SHL, MVT::v8i32, 2 }, 290 { ISD::SRL, MVT::v8i32, 4 }, 291 { ISD::SRA, MVT::v8i32, 4 }, 292 { ISD::SHL, MVT::v4i64, 2 }, 293 { ISD::SRL, MVT::v4i64, 4 }, 294 { ISD::SRA, MVT::v4i64, 4 }, 295 }; 296 297 // Look for XOP lowering tricks. 298 if (ST->hasXOP()) { 299 if (const auto *Entry = CostTableLookup(XOPCostTable, ISD, LT.second)) 300 return LT.first * Entry->Cost; 301 } 302 303 static const CostTblEntry AVX2CustomCostTable[] = { 304 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. 305 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 306 307 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. 308 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 309 310 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. 311 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. 312 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. 313 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 314 }; 315 316 // Look for AVX2 lowering tricks for custom cases. 317 if (ST->hasAVX2()) { 318 if (const auto *Entry = CostTableLookup(AVX2CustomCostTable, ISD, 319 LT.second)) 320 return LT.first * Entry->Cost; 321 } 322 323 static const CostTblEntry AVXCustomCostTable[] = { 324 // Vectorizing division is a bad idea. See the SSE2 table for more comments. 325 { ISD::SDIV, MVT::v32i8, 32*20 }, 326 { ISD::SDIV, MVT::v16i16, 16*20 }, 327 { ISD::SDIV, MVT::v8i32, 8*20 }, 328 { ISD::SDIV, MVT::v4i64, 4*20 }, 329 { ISD::UDIV, MVT::v32i8, 32*20 }, 330 { ISD::UDIV, MVT::v16i16, 16*20 }, 331 { ISD::UDIV, MVT::v8i32, 8*20 }, 332 { ISD::UDIV, MVT::v4i64, 4*20 }, 333 }; 334 335 // Look for AVX2 lowering tricks for custom cases. 336 if (ST->hasAVX()) { 337 if (const auto *Entry = CostTableLookup(AVXCustomCostTable, ISD, 338 LT.second)) 339 return LT.first * Entry->Cost; 340 } 341 342 static const CostTblEntry 343 SSE2UniformCostTable[] = { 344 // Uniform splats are cheaper for the following instructions. 345 { ISD::SHL, MVT::v16i8, 1 }, // psllw. 346 { ISD::SHL, MVT::v32i8, 2 }, // psllw. 347 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 348 { ISD::SHL, MVT::v16i16, 2 }, // psllw. 349 { ISD::SHL, MVT::v4i32, 1 }, // pslld 350 { ISD::SHL, MVT::v8i32, 2 }, // pslld 351 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 352 { ISD::SHL, MVT::v4i64, 2 }, // psllq. 353 354 { ISD::SRL, MVT::v16i8, 1 }, // psrlw. 355 { ISD::SRL, MVT::v32i8, 2 }, // psrlw. 356 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 357 { ISD::SRL, MVT::v16i16, 2 }, // psrlw. 358 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 359 { ISD::SRL, MVT::v8i32, 2 }, // psrld. 360 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 361 { ISD::SRL, MVT::v4i64, 2 }, // psrlq. 362 363 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 364 { ISD::SRA, MVT::v32i8, 8 }, // psrlw, pand, pxor, psubb. 365 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 366 { ISD::SRA, MVT::v16i16, 2 }, // psraw. 367 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 368 { ISD::SRA, MVT::v8i32, 2 }, // psrad. 369 { ISD::SRA, MVT::v2i64, 4 }, // 2 x psrad + shuffle. 370 { ISD::SRA, MVT::v4i64, 8 }, // 2 x psrad + shuffle. 371 }; 372 373 if (ST->hasSSE2() && 374 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 375 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 376 if (const auto *Entry = 377 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 378 return LT.first * Entry->Cost; 379 } 380 381 if (ISD == ISD::SHL && 382 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 383 MVT VT = LT.second; 384 // Vector shift left by non uniform constant can be lowered 385 // into vector multiply (pmullw/pmulld). 386 if ((VT == MVT::v8i16 && ST->hasSSE2()) || 387 (VT == MVT::v4i32 && ST->hasSSE41())) 388 return LT.first; 389 390 // v16i16 and v8i32 shifts by non-uniform constants are lowered into a 391 // sequence of extract + two vector multiply + insert. 392 if ((VT == MVT::v8i32 || VT == MVT::v16i16) && 393 (ST->hasAVX() && !ST->hasAVX2())) 394 ISD = ISD::MUL; 395 396 // A vector shift left by non uniform constant is converted 397 // into a vector multiply; the new multiply is eventually 398 // lowered into a sequence of shuffles and 2 x pmuludq. 399 if (VT == MVT::v4i32 && ST->hasSSE2()) 400 ISD = ISD::MUL; 401 } 402 403 static const CostTblEntry SSE41CostTable[] = { 404 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 405 { ISD::SHL, MVT::v32i8, 2*11 }, // pblendvb sequence. 406 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 407 { ISD::SHL, MVT::v16i16, 2*14 }, // pblendvb sequence. 408 409 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 410 { ISD::SRL, MVT::v32i8, 2*12 }, // pblendvb sequence. 411 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 412 { ISD::SRL, MVT::v16i16, 2*14 }, // pblendvb sequence. 413 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 414 { ISD::SRL, MVT::v8i32, 2*11 }, // Shift each lane + blend. 415 416 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 417 { ISD::SRA, MVT::v32i8, 2*24 }, // pblendvb sequence. 418 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 419 { ISD::SRA, MVT::v16i16, 2*14 }, // pblendvb sequence. 420 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 421 { ISD::SRA, MVT::v8i32, 2*12 }, // Shift each lane + blend. 422 }; 423 424 if (ST->hasSSE41()) { 425 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 426 return LT.first * Entry->Cost; 427 } 428 429 static const CostTblEntry SSE2CostTable[] = { 430 // We don't correctly identify costs of casts because they are marked as 431 // custom. 432 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 433 { ISD::SHL, MVT::v32i8, 2*26 }, // cmpgtb sequence. 434 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 435 { ISD::SHL, MVT::v16i16, 2*32 }, // cmpgtb sequence. 436 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 437 { ISD::SHL, MVT::v8i32, 2*2*5 }, // We optimized this using mul. 438 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 439 { ISD::SHL, MVT::v4i64, 2*4 }, // splat+shuffle sequence. 440 441 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 442 { ISD::SRL, MVT::v32i8, 2*26 }, // cmpgtb sequence. 443 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 444 { ISD::SRL, MVT::v16i16, 2*32 }, // cmpgtb sequence. 445 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 446 { ISD::SRL, MVT::v8i32, 2*16 }, // Shift each lane + blend. 447 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 448 { ISD::SRL, MVT::v4i64, 2*4 }, // splat+shuffle sequence. 449 450 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 451 { ISD::SRA, MVT::v32i8, 2*54 }, // unpacked cmpgtb sequence. 452 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 453 { ISD::SRA, MVT::v16i16, 2*32 }, // cmpgtb sequence. 454 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 455 { ISD::SRA, MVT::v8i32, 2*16 }, // Shift each lane + blend. 456 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 457 { ISD::SRA, MVT::v4i64, 2*12 }, // srl/xor/sub sequence. 458 459 // It is not a good idea to vectorize division. We have to scalarize it and 460 // in the process we will often end up having to spilling regular 461 // registers. The overhead of division is going to dominate most kernels 462 // anyways so try hard to prevent vectorization of division - it is 463 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 464 // to hide "20 cycles" for each lane. 465 { ISD::SDIV, MVT::v16i8, 16*20 }, 466 { ISD::SDIV, MVT::v8i16, 8*20 }, 467 { ISD::SDIV, MVT::v4i32, 4*20 }, 468 { ISD::SDIV, MVT::v2i64, 2*20 }, 469 { ISD::UDIV, MVT::v16i8, 16*20 }, 470 { ISD::UDIV, MVT::v8i16, 8*20 }, 471 { ISD::UDIV, MVT::v4i32, 4*20 }, 472 { ISD::UDIV, MVT::v2i64, 2*20 }, 473 }; 474 475 if (ST->hasSSE2()) { 476 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 477 return LT.first * Entry->Cost; 478 } 479 480 static const CostTblEntry AVX1CostTable[] = { 481 // We don't have to scalarize unsupported ops. We can issue two half-sized 482 // operations and we only need to extract the upper YMM half. 483 // Two ops + 1 extract + 1 insert = 4. 484 { ISD::MUL, MVT::v16i16, 4 }, 485 { ISD::MUL, MVT::v8i32, 4 }, 486 { ISD::SUB, MVT::v8i32, 4 }, 487 { ISD::ADD, MVT::v8i32, 4 }, 488 { ISD::SUB, MVT::v4i64, 4 }, 489 { ISD::ADD, MVT::v4i64, 4 }, 490 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 491 // are lowered as a series of long multiplies(3), shifts(4) and adds(2) 492 // Because we believe v4i64 to be a legal type, we must also include the 493 // split factor of two in the cost table. Therefore, the cost here is 18 494 // instead of 9. 495 { ISD::MUL, MVT::v4i64, 18 }, 496 }; 497 498 // Look for AVX1 lowering tricks. 499 if (ST->hasAVX() && !ST->hasAVX2()) { 500 MVT VT = LT.second; 501 502 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, VT)) 503 return LT.first * Entry->Cost; 504 } 505 506 // Custom lowering of vectors. 507 static const CostTblEntry CustomLowered[] = { 508 // A v2i64/v4i64 and multiply is custom lowered as a series of long 509 // multiplies(3), shifts(4) and adds(2). 510 { ISD::MUL, MVT::v2i64, 9 }, 511 { ISD::MUL, MVT::v4i64, 9 }, 512 }; 513 if (const auto *Entry = CostTableLookup(CustomLowered, ISD, LT.second)) 514 return LT.first * Entry->Cost; 515 516 // Special lowering of v4i32 mul on sse2, sse3: Lower v4i32 mul as 2x shuffle, 517 // 2x pmuludq, 2x shuffle. 518 if (ISD == ISD::MUL && LT.second == MVT::v4i32 && ST->hasSSE2() && 519 !ST->hasSSE41()) 520 return LT.first * 6; 521 522 // Fallback to the default implementation. 523 return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info); 524 } 525 526 int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, 527 Type *SubTp) { 528 // We only estimate the cost of reverse and alternate shuffles. 529 if (Kind != TTI::SK_Reverse && Kind != TTI::SK_Alternate) 530 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 531 532 if (Kind == TTI::SK_Reverse) { 533 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp); 534 int Cost = 1; 535 if (LT.second.getSizeInBits() > 128) 536 Cost = 3; // Extract + insert + copy. 537 538 // Multiple by the number of parts. 539 return Cost * LT.first; 540 } 541 542 if (Kind == TTI::SK_Alternate) { 543 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 544 // 64-bit packed integer vectors (v2i32) are promoted to type v2i64. 545 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp); 546 547 // The backend knows how to generate a single VEX.256 version of 548 // instruction VPBLENDW if the target supports AVX2. 549 if (ST->hasAVX2() && LT.second == MVT::v16i16) 550 return LT.first; 551 552 static const CostTblEntry AVXAltShuffleTbl[] = { 553 {ISD::VECTOR_SHUFFLE, MVT::v4i64, 1}, // vblendpd 554 {ISD::VECTOR_SHUFFLE, MVT::v4f64, 1}, // vblendpd 555 556 {ISD::VECTOR_SHUFFLE, MVT::v8i32, 1}, // vblendps 557 {ISD::VECTOR_SHUFFLE, MVT::v8f32, 1}, // vblendps 558 559 // This shuffle is custom lowered into a sequence of: 560 // 2x vextractf128 , 2x vpblendw , 1x vinsertf128 561 {ISD::VECTOR_SHUFFLE, MVT::v16i16, 5}, 562 563 // This shuffle is custom lowered into a long sequence of: 564 // 2x vextractf128 , 4x vpshufb , 2x vpor , 1x vinsertf128 565 {ISD::VECTOR_SHUFFLE, MVT::v32i8, 9} 566 }; 567 568 if (ST->hasAVX()) 569 if (const auto *Entry = CostTableLookup(AVXAltShuffleTbl, 570 ISD::VECTOR_SHUFFLE, LT.second)) 571 return LT.first * Entry->Cost; 572 573 static const CostTblEntry SSE41AltShuffleTbl[] = { 574 // These are lowered into movsd. 575 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, 576 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, 577 578 // packed float vectors with four elements are lowered into BLENDI dag 579 // nodes. A v4i32/v4f32 BLENDI generates a single 'blendps'/'blendpd'. 580 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 1}, 581 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 1}, 582 583 // This shuffle generates a single pshufw. 584 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 1}, 585 586 // There is no instruction that matches a v16i8 alternate shuffle. 587 // The backend will expand it into the sequence 'pshufb + pshufb + or'. 588 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 3} 589 }; 590 591 if (ST->hasSSE41()) 592 if (const auto *Entry = CostTableLookup(SSE41AltShuffleTbl, ISD::VECTOR_SHUFFLE, 593 LT.second)) 594 return LT.first * Entry->Cost; 595 596 static const CostTblEntry SSSE3AltShuffleTbl[] = { 597 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, // movsd 598 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, // movsd 599 600 // SSE3 doesn't have 'blendps'. The following shuffles are expanded into 601 // the sequence 'shufps + pshufd' 602 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 2}, 603 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2}, 604 605 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 3}, // pshufb + pshufb + or 606 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 3} // pshufb + pshufb + or 607 }; 608 609 if (ST->hasSSSE3()) 610 if (const auto *Entry = CostTableLookup(SSSE3AltShuffleTbl, 611 ISD::VECTOR_SHUFFLE, LT.second)) 612 return LT.first * Entry->Cost; 613 614 static const CostTblEntry SSEAltShuffleTbl[] = { 615 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, // movsd 616 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, // movsd 617 618 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 2}, // shufps + pshufd 619 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2}, // shufps + pshufd 620 621 // This is expanded into a long sequence of four extract + four insert. 622 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 8}, // 4 x pextrw + 4 pinsrw. 623 624 // 8 x (pinsrw + pextrw + and + movb + movzb + or) 625 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 48} 626 }; 627 628 // Fall-back (SSE3 and SSE2). 629 if (const auto *Entry = CostTableLookup(SSEAltShuffleTbl, 630 ISD::VECTOR_SHUFFLE, LT.second)) 631 return LT.first * Entry->Cost; 632 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 633 } 634 635 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 636 } 637 638 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) { 639 int ISD = TLI->InstructionOpcodeToISD(Opcode); 640 assert(ISD && "Invalid opcode"); 641 642 // FIXME: Need a better design of the cost table to handle non-simple types of 643 // potential massive combinations (elem_num x src_type x dst_type). 644 645 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 646 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 647 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 648 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 649 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 650 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 651 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 652 653 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 654 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 655 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 656 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 657 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 658 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 659 }; 660 661 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 662 // 256-bit wide vectors. 663 664 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 665 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 666 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 667 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 668 669 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 }, 670 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 }, 671 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 }, 672 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 673 674 // v16i1 -> v16i32 - load + broadcast 675 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 676 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 677 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 678 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 679 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 680 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 681 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 682 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 683 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 684 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 685 686 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 687 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 688 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 689 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 690 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 691 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 692 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 693 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 694 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 695 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 26 }, 696 697 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 698 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 699 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 700 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 701 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 702 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 703 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 704 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 705 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 706 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 707 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 708 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 709 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 710 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 711 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 712 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 713 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 714 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 715 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 716 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 717 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 718 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 12 }, 719 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 26 }, 720 721 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 722 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 723 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 724 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 725 }; 726 727 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 728 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 729 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 730 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 731 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 732 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 733 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 734 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 735 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 736 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 737 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 738 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 739 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 740 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 741 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 742 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 743 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 744 745 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 746 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 747 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 748 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 749 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 750 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 }, 751 752 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 753 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 754 755 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 756 }; 757 758 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 759 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 760 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 761 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 762 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 763 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 }, 764 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 765 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 7 }, 766 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 767 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 768 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 769 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 }, 770 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 771 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 772 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 773 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 774 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 775 776 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 777 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 778 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 779 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 780 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 781 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 }, 782 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 }, 783 784 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 785 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 786 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 787 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 788 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 789 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 790 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 791 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 792 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 793 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 794 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 795 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 796 797 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 798 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 799 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 800 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 801 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 802 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 803 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 804 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 805 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 806 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 }, 807 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 808 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 809 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 810 // The generic code to compute the scalar overhead is currently broken. 811 // Workaround this limitation by estimating the scalarization overhead 812 // here. We have roughly 10 instructions per scalar element. 813 // Multiply that by the vector width. 814 // FIXME: remove that when PR19268 is fixed. 815 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 10 }, 816 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 20 }, 817 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 818 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 819 820 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 }, 821 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 }, 822 // This node is expanded into scalarized operations but BasicTTI is overly 823 // optimistic estimating its cost. It computes 3 per element (one 824 // vector-extract, one scalar conversion and one vector-insert). The 825 // problem is that the inserts form a read-modify-write chain so latency 826 // should be factored in too. Inflating the cost per element by 1. 827 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, 828 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 829 830 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 831 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 832 }; 833 834 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 835 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 836 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 837 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 838 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 839 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 840 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 841 842 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 843 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 }, 844 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 845 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 846 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 847 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 848 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 849 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 850 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 851 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 852 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 853 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 854 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 855 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 856 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 857 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 858 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 859 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 860 861 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, 862 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 863 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 864 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 865 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 866 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 867 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 868 869 }; 870 871 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 872 // These are somewhat magic numbers justified by looking at the output of 873 // Intel's IACA, running some kernels and making sure when we take 874 // legalization into account the throughput will be overestimated. 875 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 876 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 877 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 878 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 879 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 880 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 881 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 882 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 883 884 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 885 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 886 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 887 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 888 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 889 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, 890 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 891 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 892 893 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 3 }, 894 895 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 896 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 897 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 898 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 899 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 900 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 901 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 902 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 903 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 904 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 905 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 906 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 907 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 908 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 909 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 910 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 911 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 912 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 913 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 914 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 915 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 916 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 917 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 918 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 919 920 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 4 }, 921 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, 922 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 923 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 924 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 925 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 926 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 927 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 928 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 929 }; 930 931 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 932 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst); 933 934 if (ST->hasSSE2() && !ST->hasAVX()) { 935 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 936 LTDest.second, LTSrc.second)) 937 return LTSrc.first * Entry->Cost; 938 } 939 940 EVT SrcTy = TLI->getValueType(DL, Src); 941 EVT DstTy = TLI->getValueType(DL, Dst); 942 943 // The function getSimpleVT only handles simple value types. 944 if (!SrcTy.isSimple() || !DstTy.isSimple()) 945 return BaseT::getCastInstrCost(Opcode, Dst, Src); 946 947 if (ST->hasDQI()) 948 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 949 DstTy.getSimpleVT(), 950 SrcTy.getSimpleVT())) 951 return Entry->Cost; 952 953 if (ST->hasAVX512()) 954 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 955 DstTy.getSimpleVT(), 956 SrcTy.getSimpleVT())) 957 return Entry->Cost; 958 959 if (ST->hasAVX2()) { 960 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 961 DstTy.getSimpleVT(), 962 SrcTy.getSimpleVT())) 963 return Entry->Cost; 964 } 965 966 if (ST->hasAVX()) { 967 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 968 DstTy.getSimpleVT(), 969 SrcTy.getSimpleVT())) 970 return Entry->Cost; 971 } 972 973 if (ST->hasSSE41()) { 974 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 975 DstTy.getSimpleVT(), 976 SrcTy.getSimpleVT())) 977 return Entry->Cost; 978 } 979 980 if (ST->hasSSE2()) { 981 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 982 DstTy.getSimpleVT(), 983 SrcTy.getSimpleVT())) 984 return Entry->Cost; 985 } 986 987 return BaseT::getCastInstrCost(Opcode, Dst, Src); 988 } 989 990 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy) { 991 // Legalize the type. 992 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 993 994 MVT MTy = LT.second; 995 996 int ISD = TLI->InstructionOpcodeToISD(Opcode); 997 assert(ISD && "Invalid opcode"); 998 999 static const CostTblEntry SSE2CostTbl[] = { 1000 { ISD::SETCC, MVT::v2i64, 8 }, 1001 { ISD::SETCC, MVT::v4i32, 1 }, 1002 { ISD::SETCC, MVT::v8i16, 1 }, 1003 { ISD::SETCC, MVT::v16i8, 1 }, 1004 }; 1005 1006 static const CostTblEntry SSE42CostTbl[] = { 1007 { ISD::SETCC, MVT::v2f64, 1 }, 1008 { ISD::SETCC, MVT::v4f32, 1 }, 1009 { ISD::SETCC, MVT::v2i64, 1 }, 1010 }; 1011 1012 static const CostTblEntry AVX1CostTbl[] = { 1013 { ISD::SETCC, MVT::v4f64, 1 }, 1014 { ISD::SETCC, MVT::v8f32, 1 }, 1015 // AVX1 does not support 8-wide integer compare. 1016 { ISD::SETCC, MVT::v4i64, 4 }, 1017 { ISD::SETCC, MVT::v8i32, 4 }, 1018 { ISD::SETCC, MVT::v16i16, 4 }, 1019 { ISD::SETCC, MVT::v32i8, 4 }, 1020 }; 1021 1022 static const CostTblEntry AVX2CostTbl[] = { 1023 { ISD::SETCC, MVT::v4i64, 1 }, 1024 { ISD::SETCC, MVT::v8i32, 1 }, 1025 { ISD::SETCC, MVT::v16i16, 1 }, 1026 { ISD::SETCC, MVT::v32i8, 1 }, 1027 }; 1028 1029 static const CostTblEntry AVX512CostTbl[] = { 1030 { ISD::SETCC, MVT::v8i64, 1 }, 1031 { ISD::SETCC, MVT::v16i32, 1 }, 1032 { ISD::SETCC, MVT::v8f64, 1 }, 1033 { ISD::SETCC, MVT::v16f32, 1 }, 1034 }; 1035 1036 if (ST->hasAVX512()) 1037 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 1038 return LT.first * Entry->Cost; 1039 1040 if (ST->hasAVX2()) 1041 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 1042 return LT.first * Entry->Cost; 1043 1044 if (ST->hasAVX()) 1045 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 1046 return LT.first * Entry->Cost; 1047 1048 if (ST->hasSSE42()) 1049 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 1050 return LT.first * Entry->Cost; 1051 1052 if (ST->hasSSE2()) 1053 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 1054 return LT.first * Entry->Cost; 1055 1056 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy); 1057 } 1058 1059 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 1060 ArrayRef<Type *> Tys, FastMathFlags FMF) { 1061 // Costs should match the codegen from: 1062 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 1063 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 1064 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 1065 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 1066 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 1067 static const CostTblEntry XOPCostTbl[] = { 1068 { ISD::BITREVERSE, MVT::v4i64, 4 }, 1069 { ISD::BITREVERSE, MVT::v8i32, 4 }, 1070 { ISD::BITREVERSE, MVT::v16i16, 4 }, 1071 { ISD::BITREVERSE, MVT::v32i8, 4 }, 1072 { ISD::BITREVERSE, MVT::v2i64, 1 }, 1073 { ISD::BITREVERSE, MVT::v4i32, 1 }, 1074 { ISD::BITREVERSE, MVT::v8i16, 1 }, 1075 { ISD::BITREVERSE, MVT::v16i8, 1 }, 1076 { ISD::BITREVERSE, MVT::i64, 3 }, 1077 { ISD::BITREVERSE, MVT::i32, 3 }, 1078 { ISD::BITREVERSE, MVT::i16, 3 }, 1079 { ISD::BITREVERSE, MVT::i8, 3 } 1080 }; 1081 static const CostTblEntry AVX2CostTbl[] = { 1082 { ISD::BITREVERSE, MVT::v4i64, 5 }, 1083 { ISD::BITREVERSE, MVT::v8i32, 5 }, 1084 { ISD::BITREVERSE, MVT::v16i16, 5 }, 1085 { ISD::BITREVERSE, MVT::v32i8, 5 }, 1086 { ISD::BSWAP, MVT::v4i64, 1 }, 1087 { ISD::BSWAP, MVT::v8i32, 1 }, 1088 { ISD::BSWAP, MVT::v16i16, 1 }, 1089 { ISD::CTLZ, MVT::v4i64, 23 }, 1090 { ISD::CTLZ, MVT::v8i32, 18 }, 1091 { ISD::CTLZ, MVT::v16i16, 14 }, 1092 { ISD::CTLZ, MVT::v32i8, 9 }, 1093 { ISD::CTPOP, MVT::v4i64, 7 }, 1094 { ISD::CTPOP, MVT::v8i32, 11 }, 1095 { ISD::CTPOP, MVT::v16i16, 9 }, 1096 { ISD::CTPOP, MVT::v32i8, 6 }, 1097 { ISD::CTTZ, MVT::v4i64, 10 }, 1098 { ISD::CTTZ, MVT::v8i32, 14 }, 1099 { ISD::CTTZ, MVT::v16i16, 12 }, 1100 { ISD::CTTZ, MVT::v32i8, 9 } 1101 }; 1102 static const CostTblEntry AVX1CostTbl[] = { 1103 { ISD::BITREVERSE, MVT::v4i64, 10 }, 1104 { ISD::BITREVERSE, MVT::v8i32, 10 }, 1105 { ISD::BITREVERSE, MVT::v16i16, 10 }, 1106 { ISD::BITREVERSE, MVT::v32i8, 10 }, 1107 { ISD::BSWAP, MVT::v4i64, 4 }, 1108 { ISD::BSWAP, MVT::v8i32, 4 }, 1109 { ISD::BSWAP, MVT::v16i16, 4 }, 1110 { ISD::CTLZ, MVT::v4i64, 46 }, 1111 { ISD::CTLZ, MVT::v8i32, 36 }, 1112 { ISD::CTLZ, MVT::v16i16, 28 }, 1113 { ISD::CTLZ, MVT::v32i8, 18 }, 1114 { ISD::CTPOP, MVT::v4i64, 14 }, 1115 { ISD::CTPOP, MVT::v8i32, 22 }, 1116 { ISD::CTPOP, MVT::v16i16, 18 }, 1117 { ISD::CTPOP, MVT::v32i8, 12 }, 1118 { ISD::CTTZ, MVT::v4i64, 20 }, 1119 { ISD::CTTZ, MVT::v8i32, 28 }, 1120 { ISD::CTTZ, MVT::v16i16, 24 }, 1121 { ISD::CTTZ, MVT::v32i8, 18 }, 1122 }; 1123 static const CostTblEntry SSSE3CostTbl[] = { 1124 { ISD::BITREVERSE, MVT::v2i64, 5 }, 1125 { ISD::BITREVERSE, MVT::v4i32, 5 }, 1126 { ISD::BITREVERSE, MVT::v8i16, 5 }, 1127 { ISD::BITREVERSE, MVT::v16i8, 5 }, 1128 { ISD::BSWAP, MVT::v2i64, 1 }, 1129 { ISD::BSWAP, MVT::v4i32, 1 }, 1130 { ISD::BSWAP, MVT::v8i16, 1 }, 1131 { ISD::CTLZ, MVT::v2i64, 23 }, 1132 { ISD::CTLZ, MVT::v4i32, 18 }, 1133 { ISD::CTLZ, MVT::v8i16, 14 }, 1134 { ISD::CTLZ, MVT::v16i8, 9 }, 1135 { ISD::CTPOP, MVT::v2i64, 7 }, 1136 { ISD::CTPOP, MVT::v4i32, 11 }, 1137 { ISD::CTPOP, MVT::v8i16, 9 }, 1138 { ISD::CTPOP, MVT::v16i8, 6 }, 1139 { ISD::CTTZ, MVT::v2i64, 10 }, 1140 { ISD::CTTZ, MVT::v4i32, 14 }, 1141 { ISD::CTTZ, MVT::v8i16, 12 }, 1142 { ISD::CTTZ, MVT::v16i8, 9 } 1143 }; 1144 static const CostTblEntry SSE2CostTbl[] = { 1145 { ISD::BSWAP, MVT::v2i64, 7 }, 1146 { ISD::BSWAP, MVT::v4i32, 7 }, 1147 { ISD::BSWAP, MVT::v8i16, 7 }, 1148 /* ISD::CTLZ - currently scalarized pre-SSSE3 */ 1149 { ISD::CTPOP, MVT::v2i64, 12 }, 1150 { ISD::CTPOP, MVT::v4i32, 15 }, 1151 { ISD::CTPOP, MVT::v8i16, 13 }, 1152 { ISD::CTPOP, MVT::v16i8, 10 }, 1153 { ISD::CTTZ, MVT::v2i64, 14 }, 1154 { ISD::CTTZ, MVT::v4i32, 18 }, 1155 { ISD::CTTZ, MVT::v8i16, 16 }, 1156 { ISD::CTTZ, MVT::v16i8, 13 } 1157 }; 1158 1159 unsigned ISD = ISD::DELETED_NODE; 1160 switch (IID) { 1161 default: 1162 break; 1163 case Intrinsic::bitreverse: 1164 ISD = ISD::BITREVERSE; 1165 break; 1166 case Intrinsic::bswap: 1167 ISD = ISD::BSWAP; 1168 break; 1169 case Intrinsic::ctlz: 1170 ISD = ISD::CTLZ; 1171 break; 1172 case Intrinsic::ctpop: 1173 ISD = ISD::CTPOP; 1174 break; 1175 case Intrinsic::cttz: 1176 ISD = ISD::CTTZ; 1177 break; 1178 } 1179 1180 // Legalize the type. 1181 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 1182 MVT MTy = LT.second; 1183 1184 // Attempt to lookup cost. 1185 if (ST->hasXOP()) 1186 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 1187 return LT.first * Entry->Cost; 1188 1189 if (ST->hasAVX2()) 1190 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 1191 return LT.first * Entry->Cost; 1192 1193 if (ST->hasAVX()) 1194 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 1195 return LT.first * Entry->Cost; 1196 1197 if (ST->hasSSSE3()) 1198 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 1199 return LT.first * Entry->Cost; 1200 1201 if (ST->hasSSE2()) 1202 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 1203 return LT.first * Entry->Cost; 1204 1205 return BaseT::getIntrinsicInstrCost(IID, RetTy, Tys, FMF); 1206 } 1207 1208 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 1209 ArrayRef<Value *> Args, FastMathFlags FMF) { 1210 return BaseT::getIntrinsicInstrCost(IID, RetTy, Args, FMF); 1211 } 1212 1213 int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { 1214 assert(Val->isVectorTy() && "This must be a vector type"); 1215 1216 Type *ScalarType = Val->getScalarType(); 1217 1218 if (Index != -1U) { 1219 // Legalize the type. 1220 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 1221 1222 // This type is legalized to a scalar type. 1223 if (!LT.second.isVector()) 1224 return 0; 1225 1226 // The type may be split. Normalize the index to the new type. 1227 unsigned Width = LT.second.getVectorNumElements(); 1228 Index = Index % Width; 1229 1230 // Floating point scalars are already located in index #0. 1231 if (ScalarType->isFloatingPointTy() && Index == 0) 1232 return 0; 1233 } 1234 1235 // Add to the base cost if we know that the extracted element of a vector is 1236 // destined to be moved to and used in the integer register file. 1237 int RegisterFileMoveCost = 0; 1238 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 1239 RegisterFileMoveCost = 1; 1240 1241 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 1242 } 1243 1244 int X86TTIImpl::getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) { 1245 assert (Ty->isVectorTy() && "Can only scalarize vectors"); 1246 int Cost = 0; 1247 1248 for (int i = 0, e = Ty->getVectorNumElements(); i < e; ++i) { 1249 if (Insert) 1250 Cost += getVectorInstrCost(Instruction::InsertElement, Ty, i); 1251 if (Extract) 1252 Cost += getVectorInstrCost(Instruction::ExtractElement, Ty, i); 1253 } 1254 1255 return Cost; 1256 } 1257 1258 int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, 1259 unsigned AddressSpace) { 1260 // Handle non-power-of-two vectors such as <3 x float> 1261 if (VectorType *VTy = dyn_cast<VectorType>(Src)) { 1262 unsigned NumElem = VTy->getVectorNumElements(); 1263 1264 // Handle a few common cases: 1265 // <3 x float> 1266 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 1267 // Cost = 64 bit store + extract + 32 bit store. 1268 return 3; 1269 1270 // <3 x double> 1271 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 1272 // Cost = 128 bit store + unpack + 64 bit store. 1273 return 3; 1274 1275 // Assume that all other non-power-of-two numbers are scalarized. 1276 if (!isPowerOf2_32(NumElem)) { 1277 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment, 1278 AddressSpace); 1279 int SplitCost = getScalarizationOverhead(Src, Opcode == Instruction::Load, 1280 Opcode == Instruction::Store); 1281 return NumElem * Cost + SplitCost; 1282 } 1283 } 1284 1285 // Legalize the type. 1286 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 1287 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 1288 "Invalid Opcode"); 1289 1290 // Each load/store unit costs 1. 1291 int Cost = LT.first * 1; 1292 1293 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a 1294 // proxy for a double-pumped AVX memory interface such as on Sandybridge. 1295 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow()) 1296 Cost *= 2; 1297 1298 return Cost; 1299 } 1300 1301 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, 1302 unsigned Alignment, 1303 unsigned AddressSpace) { 1304 VectorType *SrcVTy = dyn_cast<VectorType>(SrcTy); 1305 if (!SrcVTy) 1306 // To calculate scalar take the regular cost, without mask 1307 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace); 1308 1309 unsigned NumElem = SrcVTy->getVectorNumElements(); 1310 VectorType *MaskTy = 1311 VectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 1312 if ((Opcode == Instruction::Load && !isLegalMaskedLoad(SrcVTy)) || 1313 (Opcode == Instruction::Store && !isLegalMaskedStore(SrcVTy)) || 1314 !isPowerOf2_32(NumElem)) { 1315 // Scalarization 1316 int MaskSplitCost = getScalarizationOverhead(MaskTy, false, true); 1317 int ScalarCompareCost = getCmpSelInstrCost( 1318 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr); 1319 int BranchCost = getCFInstrCost(Instruction::Br); 1320 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 1321 1322 int ValueSplitCost = getScalarizationOverhead( 1323 SrcVTy, Opcode == Instruction::Load, Opcode == Instruction::Store); 1324 int MemopCost = 1325 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 1326 Alignment, AddressSpace); 1327 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 1328 } 1329 1330 // Legalize the type. 1331 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 1332 auto VT = TLI->getValueType(DL, SrcVTy); 1333 int Cost = 0; 1334 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 1335 LT.second.getVectorNumElements() == NumElem) 1336 // Promotion requires expand/truncate for data and a shuffle for mask. 1337 Cost += getShuffleCost(TTI::SK_Alternate, SrcVTy, 0, nullptr) + 1338 getShuffleCost(TTI::SK_Alternate, MaskTy, 0, nullptr); 1339 1340 else if (LT.second.getVectorNumElements() > NumElem) { 1341 VectorType *NewMaskTy = VectorType::get(MaskTy->getVectorElementType(), 1342 LT.second.getVectorNumElements()); 1343 // Expanding requires fill mask with zeroes 1344 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, 0, MaskTy); 1345 } 1346 if (!ST->hasAVX512()) 1347 return Cost + LT.first*4; // Each maskmov costs 4 1348 1349 // AVX-512 masked load/store is cheapper 1350 return Cost+LT.first; 1351 } 1352 1353 int X86TTIImpl::getAddressComputationCost(Type *Ty, bool IsComplex) { 1354 // Address computations in vectorized code with non-consecutive addresses will 1355 // likely result in more instructions compared to scalar code where the 1356 // computation can more often be merged into the index mode. The resulting 1357 // extra micro-ops can significantly decrease throughput. 1358 unsigned NumVectorInstToHideOverhead = 10; 1359 1360 if (Ty->isVectorTy() && IsComplex) 1361 return NumVectorInstToHideOverhead; 1362 1363 return BaseT::getAddressComputationCost(Ty, IsComplex); 1364 } 1365 1366 int X86TTIImpl::getReductionCost(unsigned Opcode, Type *ValTy, 1367 bool IsPairwise) { 1368 1369 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 1370 1371 MVT MTy = LT.second; 1372 1373 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1374 assert(ISD && "Invalid opcode"); 1375 1376 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 1377 // and make it as the cost. 1378 1379 static const CostTblEntry SSE42CostTblPairWise[] = { 1380 { ISD::FADD, MVT::v2f64, 2 }, 1381 { ISD::FADD, MVT::v4f32, 4 }, 1382 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 1383 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5". 1384 { ISD::ADD, MVT::v8i16, 5 }, 1385 }; 1386 1387 static const CostTblEntry AVX1CostTblPairWise[] = { 1388 { ISD::FADD, MVT::v4f32, 4 }, 1389 { ISD::FADD, MVT::v4f64, 5 }, 1390 { ISD::FADD, MVT::v8f32, 7 }, 1391 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 1392 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5". 1393 { ISD::ADD, MVT::v4i64, 5 }, // The data reported by the IACA tool is "4.8". 1394 { ISD::ADD, MVT::v8i16, 5 }, 1395 { ISD::ADD, MVT::v8i32, 5 }, 1396 }; 1397 1398 static const CostTblEntry SSE42CostTblNoPairWise[] = { 1399 { ISD::FADD, MVT::v2f64, 2 }, 1400 { ISD::FADD, MVT::v4f32, 4 }, 1401 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 1402 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 1403 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 1404 }; 1405 1406 static const CostTblEntry AVX1CostTblNoPairWise[] = { 1407 { ISD::FADD, MVT::v4f32, 3 }, 1408 { ISD::FADD, MVT::v4f64, 3 }, 1409 { ISD::FADD, MVT::v8f32, 4 }, 1410 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 1411 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "2.8". 1412 { ISD::ADD, MVT::v4i64, 3 }, 1413 { ISD::ADD, MVT::v8i16, 4 }, 1414 { ISD::ADD, MVT::v8i32, 5 }, 1415 }; 1416 1417 if (IsPairwise) { 1418 if (ST->hasAVX()) 1419 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy)) 1420 return LT.first * Entry->Cost; 1421 1422 if (ST->hasSSE42()) 1423 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy)) 1424 return LT.first * Entry->Cost; 1425 } else { 1426 if (ST->hasAVX()) 1427 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 1428 return LT.first * Entry->Cost; 1429 1430 if (ST->hasSSE42()) 1431 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy)) 1432 return LT.first * Entry->Cost; 1433 } 1434 1435 return BaseT::getReductionCost(Opcode, ValTy, IsPairwise); 1436 } 1437 1438 /// \brief Calculate the cost of materializing a 64-bit value. This helper 1439 /// method might only calculate a fraction of a larger immediate. Therefore it 1440 /// is valid to return a cost of ZERO. 1441 int X86TTIImpl::getIntImmCost(int64_t Val) { 1442 if (Val == 0) 1443 return TTI::TCC_Free; 1444 1445 if (isInt<32>(Val)) 1446 return TTI::TCC_Basic; 1447 1448 return 2 * TTI::TCC_Basic; 1449 } 1450 1451 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { 1452 assert(Ty->isIntegerTy()); 1453 1454 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 1455 if (BitSize == 0) 1456 return ~0U; 1457 1458 // Never hoist constants larger than 128bit, because this might lead to 1459 // incorrect code generation or assertions in codegen. 1460 // Fixme: Create a cost model for types larger than i128 once the codegen 1461 // issues have been fixed. 1462 if (BitSize > 128) 1463 return TTI::TCC_Free; 1464 1465 if (Imm == 0) 1466 return TTI::TCC_Free; 1467 1468 // Sign-extend all constants to a multiple of 64-bit. 1469 APInt ImmVal = Imm; 1470 if (BitSize & 0x3f) 1471 ImmVal = Imm.sext((BitSize + 63) & ~0x3fU); 1472 1473 // Split the constant into 64-bit chunks and calculate the cost for each 1474 // chunk. 1475 int Cost = 0; 1476 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 1477 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 1478 int64_t Val = Tmp.getSExtValue(); 1479 Cost += getIntImmCost(Val); 1480 } 1481 // We need at least one instruction to materialize the constant. 1482 return std::max(1, Cost); 1483 } 1484 1485 int X86TTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, 1486 Type *Ty) { 1487 assert(Ty->isIntegerTy()); 1488 1489 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 1490 // There is no cost model for constants with a bit size of 0. Return TCC_Free 1491 // here, so that constant hoisting will ignore this constant. 1492 if (BitSize == 0) 1493 return TTI::TCC_Free; 1494 1495 unsigned ImmIdx = ~0U; 1496 switch (Opcode) { 1497 default: 1498 return TTI::TCC_Free; 1499 case Instruction::GetElementPtr: 1500 // Always hoist the base address of a GetElementPtr. This prevents the 1501 // creation of new constants for every base constant that gets constant 1502 // folded with the offset. 1503 if (Idx == 0) 1504 return 2 * TTI::TCC_Basic; 1505 return TTI::TCC_Free; 1506 case Instruction::Store: 1507 ImmIdx = 0; 1508 break; 1509 case Instruction::ICmp: 1510 // This is an imperfect hack to prevent constant hoisting of 1511 // compares that might be trying to check if a 64-bit value fits in 1512 // 32-bits. The backend can optimize these cases using a right shift by 32. 1513 // Ideally we would check the compare predicate here. There also other 1514 // similar immediates the backend can use shifts for. 1515 if (Idx == 1 && Imm.getBitWidth() == 64) { 1516 uint64_t ImmVal = Imm.getZExtValue(); 1517 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 1518 return TTI::TCC_Free; 1519 } 1520 ImmIdx = 1; 1521 break; 1522 case Instruction::And: 1523 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 1524 // by using a 32-bit operation with implicit zero extension. Detect such 1525 // immediates here as the normal path expects bit 31 to be sign extended. 1526 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 1527 return TTI::TCC_Free; 1528 LLVM_FALLTHROUGH; 1529 case Instruction::Add: 1530 case Instruction::Sub: 1531 case Instruction::Mul: 1532 case Instruction::UDiv: 1533 case Instruction::SDiv: 1534 case Instruction::URem: 1535 case Instruction::SRem: 1536 case Instruction::Or: 1537 case Instruction::Xor: 1538 ImmIdx = 1; 1539 break; 1540 // Always return TCC_Free for the shift value of a shift instruction. 1541 case Instruction::Shl: 1542 case Instruction::LShr: 1543 case Instruction::AShr: 1544 if (Idx == 1) 1545 return TTI::TCC_Free; 1546 break; 1547 case Instruction::Trunc: 1548 case Instruction::ZExt: 1549 case Instruction::SExt: 1550 case Instruction::IntToPtr: 1551 case Instruction::PtrToInt: 1552 case Instruction::BitCast: 1553 case Instruction::PHI: 1554 case Instruction::Call: 1555 case Instruction::Select: 1556 case Instruction::Ret: 1557 case Instruction::Load: 1558 break; 1559 } 1560 1561 if (Idx == ImmIdx) { 1562 int NumConstants = (BitSize + 63) / 64; 1563 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty); 1564 return (Cost <= NumConstants * TTI::TCC_Basic) 1565 ? static_cast<int>(TTI::TCC_Free) 1566 : Cost; 1567 } 1568 1569 return X86TTIImpl::getIntImmCost(Imm, Ty); 1570 } 1571 1572 int X86TTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, 1573 Type *Ty) { 1574 assert(Ty->isIntegerTy()); 1575 1576 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 1577 // There is no cost model for constants with a bit size of 0. Return TCC_Free 1578 // here, so that constant hoisting will ignore this constant. 1579 if (BitSize == 0) 1580 return TTI::TCC_Free; 1581 1582 switch (IID) { 1583 default: 1584 return TTI::TCC_Free; 1585 case Intrinsic::sadd_with_overflow: 1586 case Intrinsic::uadd_with_overflow: 1587 case Intrinsic::ssub_with_overflow: 1588 case Intrinsic::usub_with_overflow: 1589 case Intrinsic::smul_with_overflow: 1590 case Intrinsic::umul_with_overflow: 1591 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 1592 return TTI::TCC_Free; 1593 break; 1594 case Intrinsic::experimental_stackmap: 1595 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 1596 return TTI::TCC_Free; 1597 break; 1598 case Intrinsic::experimental_patchpoint_void: 1599 case Intrinsic::experimental_patchpoint_i64: 1600 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 1601 return TTI::TCC_Free; 1602 break; 1603 } 1604 return X86TTIImpl::getIntImmCost(Imm, Ty); 1605 } 1606 1607 // Return an average cost of Gather / Scatter instruction, maybe improved later 1608 int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, Value *Ptr, 1609 unsigned Alignment, unsigned AddressSpace) { 1610 1611 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 1612 unsigned VF = SrcVTy->getVectorNumElements(); 1613 1614 // Try to reduce index size from 64 bit (default for GEP) 1615 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 1616 // operation will use 16 x 64 indices which do not fit in a zmm and needs 1617 // to split. Also check that the base pointer is the same for all lanes, 1618 // and that there's at most one variable index. 1619 auto getIndexSizeInBits = [](Value *Ptr, const DataLayout& DL) { 1620 unsigned IndexSize = DL.getPointerSizeInBits(); 1621 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 1622 if (IndexSize < 64 || !GEP) 1623 return IndexSize; 1624 1625 unsigned NumOfVarIndices = 0; 1626 Value *Ptrs = GEP->getPointerOperand(); 1627 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 1628 return IndexSize; 1629 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 1630 if (isa<Constant>(GEP->getOperand(i))) 1631 continue; 1632 Type *IndxTy = GEP->getOperand(i)->getType(); 1633 if (IndxTy->isVectorTy()) 1634 IndxTy = IndxTy->getVectorElementType(); 1635 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 1636 !isa<SExtInst>(GEP->getOperand(i))) || 1637 ++NumOfVarIndices > 1) 1638 return IndexSize; // 64 1639 } 1640 return (unsigned)32; 1641 }; 1642 1643 1644 // Trying to reduce IndexSize to 32 bits for vector 16. 1645 // By default the IndexSize is equal to pointer size. 1646 unsigned IndexSize = (VF >= 16) ? getIndexSizeInBits(Ptr, DL) : 1647 DL.getPointerSizeInBits(); 1648 1649 Type *IndexVTy = VectorType::get(IntegerType::get(SrcVTy->getContext(), 1650 IndexSize), VF); 1651 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy); 1652 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy); 1653 int SplitFactor = std::max(IdxsLT.first, SrcLT.first); 1654 if (SplitFactor > 1) { 1655 // Handle splitting of vector of pointers 1656 Type *SplitSrcTy = VectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 1657 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 1658 AddressSpace); 1659 } 1660 1661 // The gather / scatter cost is given by Intel architects. It is a rough 1662 // number since we are looking at one instruction in a time. 1663 const int GSOverhead = 2; 1664 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 1665 Alignment, AddressSpace); 1666 } 1667 1668 /// Return the cost of full scalarization of gather / scatter operation. 1669 /// 1670 /// Opcode - Load or Store instruction. 1671 /// SrcVTy - The type of the data vector that should be gathered or scattered. 1672 /// VariableMask - The mask is non-constant at compile time. 1673 /// Alignment - Alignment for one element. 1674 /// AddressSpace - pointer[s] address space. 1675 /// 1676 int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 1677 bool VariableMask, unsigned Alignment, 1678 unsigned AddressSpace) { 1679 unsigned VF = SrcVTy->getVectorNumElements(); 1680 1681 int MaskUnpackCost = 0; 1682 if (VariableMask) { 1683 VectorType *MaskTy = 1684 VectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 1685 MaskUnpackCost = getScalarizationOverhead(MaskTy, false, true); 1686 int ScalarCompareCost = 1687 getCmpSelInstrCost(Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), 1688 nullptr); 1689 int BranchCost = getCFInstrCost(Instruction::Br); 1690 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 1691 } 1692 1693 // The cost of the scalar loads/stores. 1694 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 1695 Alignment, AddressSpace); 1696 1697 int InsertExtractCost = 0; 1698 if (Opcode == Instruction::Load) 1699 for (unsigned i = 0; i < VF; ++i) 1700 // Add the cost of inserting each scalar load into the vector 1701 InsertExtractCost += 1702 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 1703 else 1704 for (unsigned i = 0; i < VF; ++i) 1705 // Add the cost of extracting each element out of the data vector 1706 InsertExtractCost += 1707 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 1708 1709 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 1710 } 1711 1712 /// Calculate the cost of Gather / Scatter operation 1713 int X86TTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *SrcVTy, 1714 Value *Ptr, bool VariableMask, 1715 unsigned Alignment) { 1716 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 1717 unsigned VF = SrcVTy->getVectorNumElements(); 1718 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 1719 if (!PtrTy && Ptr->getType()->isVectorTy()) 1720 PtrTy = dyn_cast<PointerType>(Ptr->getType()->getVectorElementType()); 1721 assert(PtrTy && "Unexpected type for Ptr argument"); 1722 unsigned AddressSpace = PtrTy->getAddressSpace(); 1723 1724 bool Scalarize = false; 1725 if ((Opcode == Instruction::Load && !isLegalMaskedGather(SrcVTy)) || 1726 (Opcode == Instruction::Store && !isLegalMaskedScatter(SrcVTy))) 1727 Scalarize = true; 1728 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 1729 // Vector-4 of gather/scatter instruction does not exist on KNL. 1730 // We can extend it to 8 elements, but zeroing upper bits of 1731 // the mask vector will add more instructions. Right now we give the scalar 1732 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction is 1733 // better in the VariableMask case. 1734 if (VF == 2 || (VF == 4 && !ST->hasVLX())) 1735 Scalarize = true; 1736 1737 if (Scalarize) 1738 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, AddressSpace); 1739 1740 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 1741 } 1742 1743 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy) { 1744 Type *ScalarTy = DataTy->getScalarType(); 1745 int DataWidth = isa<PointerType>(ScalarTy) ? 1746 DL.getPointerSizeInBits() : ScalarTy->getPrimitiveSizeInBits(); 1747 1748 return ((DataWidth == 32 || DataWidth == 64) && ST->hasAVX()) || 1749 ((DataWidth == 8 || DataWidth == 16) && ST->hasBWI()); 1750 } 1751 1752 bool X86TTIImpl::isLegalMaskedStore(Type *DataType) { 1753 return isLegalMaskedLoad(DataType); 1754 } 1755 1756 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy) { 1757 // This function is called now in two cases: from the Loop Vectorizer 1758 // and from the Scalarizer. 1759 // When the Loop Vectorizer asks about legality of the feature, 1760 // the vectorization factor is not calculated yet. The Loop Vectorizer 1761 // sends a scalar type and the decision is based on the width of the 1762 // scalar element. 1763 // Later on, the cost model will estimate usage this intrinsic based on 1764 // the vector type. 1765 // The Scalarizer asks again about legality. It sends a vector type. 1766 // In this case we can reject non-power-of-2 vectors. 1767 if (isa<VectorType>(DataTy) && !isPowerOf2_32(DataTy->getVectorNumElements())) 1768 return false; 1769 Type *ScalarTy = DataTy->getScalarType(); 1770 int DataWidth = isa<PointerType>(ScalarTy) ? 1771 DL.getPointerSizeInBits() : ScalarTy->getPrimitiveSizeInBits(); 1772 1773 // AVX-512 allows gather and scatter 1774 return (DataWidth == 32 || DataWidth == 64) && ST->hasAVX512(); 1775 } 1776 1777 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType) { 1778 return isLegalMaskedGather(DataType); 1779 } 1780 1781 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 1782 const Function *Callee) const { 1783 const TargetMachine &TM = getTLI()->getTargetMachine(); 1784 1785 // Work this as a subsetting of subtarget features. 1786 const FeatureBitset &CallerBits = 1787 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 1788 const FeatureBitset &CalleeBits = 1789 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 1790 1791 // FIXME: This is likely too limiting as it will include subtarget features 1792 // that we might not care about for inlining, but it is conservatively 1793 // correct. 1794 return (CallerBits & CalleeBits) == CalleeBits; 1795 } 1796 1797 bool X86TTIImpl::enableInterleavedAccessVectorization() { 1798 // TODO: We expect this to be beneficial regardless of arch, 1799 // but there are currently some unexplained performance artifacts on Atom. 1800 // As a temporary solution, disable on Atom. 1801 return !(ST->isAtom() || ST->isSLM()); 1802 } 1803