1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // X86 cost model. 56 // 57 //===----------------------------------------------------------------------===// 58 59 TargetTransformInfo::PopcntSupportKind 60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 61 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 62 // TODO: Currently the __builtin_popcount() implementation using SSE3 63 // instructions is inefficient. Once the problem is fixed, we should 64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 66 } 67 68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 69 TargetTransformInfo::CacheLevel Level) const { 70 switch (Level) { 71 case TargetTransformInfo::CacheLevel::L1D: 72 // - Penryn 73 // - Nehalem 74 // - Westmere 75 // - Sandy Bridge 76 // - Ivy Bridge 77 // - Haswell 78 // - Broadwell 79 // - Skylake 80 // - Kabylake 81 return 32 * 1024; // 32 KByte 82 case TargetTransformInfo::CacheLevel::L2D: 83 // - Penryn 84 // - Nehalem 85 // - Westmere 86 // - Sandy Bridge 87 // - Ivy Bridge 88 // - Haswell 89 // - Broadwell 90 // - Skylake 91 // - Kabylake 92 return 256 * 1024; // 256 KByte 93 } 94 95 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 96 } 97 98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 99 TargetTransformInfo::CacheLevel Level) const { 100 // - Penryn 101 // - Nehalem 102 // - Westmere 103 // - Sandy Bridge 104 // - Ivy Bridge 105 // - Haswell 106 // - Broadwell 107 // - Skylake 108 // - Kabylake 109 switch (Level) { 110 case TargetTransformInfo::CacheLevel::L1D: 111 LLVM_FALLTHROUGH; 112 case TargetTransformInfo::CacheLevel::L2D: 113 return 8; 114 } 115 116 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 117 } 118 119 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 120 bool Vector = (ClassID == 1); 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 TypeSize 133 X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { 134 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 135 switch (K) { 136 case TargetTransformInfo::RGK_Scalar: 137 return TypeSize::getFixed(ST->is64Bit() ? 64 : 32); 138 case TargetTransformInfo::RGK_FixedWidthVector: 139 if (ST->hasAVX512() && PreferVectorWidth >= 512) 140 return TypeSize::getFixed(512); 141 if (ST->hasAVX() && PreferVectorWidth >= 256) 142 return TypeSize::getFixed(256); 143 if (ST->hasSSE1() && PreferVectorWidth >= 128) 144 return TypeSize::getFixed(128); 145 return TypeSize::getFixed(0); 146 case TargetTransformInfo::RGK_ScalableVector: 147 return TypeSize::getScalable(0); 148 } 149 150 llvm_unreachable("Unsupported register kind"); 151 } 152 153 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 154 return getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector) 155 .getFixedSize(); 156 } 157 158 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 159 // If the loop will not be vectorized, don't interleave the loop. 160 // Let regular unroll to unroll the loop, which saves the overflow 161 // check and memory check cost. 162 if (VF == 1) 163 return 1; 164 165 if (ST->isAtom()) 166 return 1; 167 168 // Sandybridge and Haswell have multiple execution ports and pipelined 169 // vector units. 170 if (ST->hasAVX()) 171 return 4; 172 173 return 2; 174 } 175 176 InstructionCost X86TTIImpl::getArithmeticInstrCost( 177 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, 178 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 179 TTI::OperandValueProperties Opd1PropInfo, 180 TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, 181 const Instruction *CxtI) { 182 // TODO: Handle more cost kinds. 183 if (CostKind != TTI::TCK_RecipThroughput) 184 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, 185 Op2Info, Opd1PropInfo, 186 Opd2PropInfo, Args, CxtI); 187 // Legalize the type. 188 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 189 190 int ISD = TLI->InstructionOpcodeToISD(Opcode); 191 assert(ISD && "Invalid opcode"); 192 193 static const CostTblEntry GLMCostTable[] = { 194 { ISD::FDIV, MVT::f32, 18 }, // divss 195 { ISD::FDIV, MVT::v4f32, 35 }, // divps 196 { ISD::FDIV, MVT::f64, 33 }, // divsd 197 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 198 }; 199 200 if (ST->useGLMDivSqrtCosts()) 201 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 202 LT.second)) 203 return LT.first * Entry->Cost; 204 205 static const CostTblEntry SLMCostTable[] = { 206 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 207 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 208 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. 209 { ISD::FMUL, MVT::f64, 2 }, // mulsd 210 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 211 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 212 { ISD::FDIV, MVT::f32, 17 }, // divss 213 { ISD::FDIV, MVT::v4f32, 39 }, // divps 214 { ISD::FDIV, MVT::f64, 32 }, // divsd 215 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 216 { ISD::FADD, MVT::v2f64, 2 }, // addpd 217 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 218 // v2i64/v4i64 mul is custom lowered as a series of long: 219 // multiplies(3), shifts(3) and adds(2) 220 // slm muldq version throughput is 2 and addq throughput 4 221 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 222 // 3X4 (addq throughput) = 17 223 { ISD::MUL, MVT::v2i64, 17 }, 224 // slm addq\subq throughput is 4 225 { ISD::ADD, MVT::v2i64, 4 }, 226 { ISD::SUB, MVT::v2i64, 4 }, 227 }; 228 229 if (ST->isSLM()) { 230 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 231 // Check if the operands can be shrinked into a smaller datatype. 232 bool Op1Signed = false; 233 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 234 bool Op2Signed = false; 235 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 236 237 bool SignedMode = Op1Signed || Op2Signed; 238 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 239 240 if (OpMinSize <= 7) 241 return LT.first * 3; // pmullw/sext 242 if (!SignedMode && OpMinSize <= 8) 243 return LT.first * 3; // pmullw/zext 244 if (OpMinSize <= 15) 245 return LT.first * 5; // pmullw/pmulhw/pshuf 246 if (!SignedMode && OpMinSize <= 16) 247 return LT.first * 5; // pmullw/pmulhw/pshuf 248 } 249 250 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 251 LT.second)) { 252 return LT.first * Entry->Cost; 253 } 254 } 255 256 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 257 ISD == ISD::UREM) && 258 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 259 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 260 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 261 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 262 // On X86, vector signed division by constants power-of-two are 263 // normally expanded to the sequence SRA + SRL + ADD + SRA. 264 // The OperandValue properties may not be the same as that of the previous 265 // operation; conservatively assume OP_None. 266 InstructionCost Cost = 267 2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Op1Info, 268 Op2Info, TargetTransformInfo::OP_None, 269 TargetTransformInfo::OP_None); 270 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 271 Op2Info, 272 TargetTransformInfo::OP_None, 273 TargetTransformInfo::OP_None); 274 Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind, Op1Info, 275 Op2Info, 276 TargetTransformInfo::OP_None, 277 TargetTransformInfo::OP_None); 278 279 if (ISD == ISD::SREM) { 280 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 281 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info, 282 Op2Info); 283 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info, 284 Op2Info); 285 } 286 287 return Cost; 288 } 289 290 // Vector unsigned division/remainder will be simplified to shifts/masks. 291 if (ISD == ISD::UDIV) 292 return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, 293 Op1Info, Op2Info, 294 TargetTransformInfo::OP_None, 295 TargetTransformInfo::OP_None); 296 297 else // UREM 298 return getArithmeticInstrCost(Instruction::And, Ty, CostKind, 299 Op1Info, Op2Info, 300 TargetTransformInfo::OP_None, 301 TargetTransformInfo::OP_None); 302 } 303 304 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 305 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 306 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 307 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 308 }; 309 310 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 311 ST->hasBWI()) { 312 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 313 LT.second)) 314 return LT.first * Entry->Cost; 315 } 316 317 static const CostTblEntry AVX512UniformConstCostTable[] = { 318 { ISD::SRA, MVT::v2i64, 1 }, 319 { ISD::SRA, MVT::v4i64, 1 }, 320 { ISD::SRA, MVT::v8i64, 1 }, 321 322 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 323 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 324 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 325 326 { ISD::SDIV, MVT::v16i32, 6 }, // pmuludq sequence 327 { ISD::SREM, MVT::v16i32, 8 }, // pmuludq+mul+sub sequence 328 { ISD::UDIV, MVT::v16i32, 5 }, // pmuludq sequence 329 { ISD::UREM, MVT::v16i32, 7 }, // pmuludq+mul+sub sequence 330 }; 331 332 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 333 ST->hasAVX512()) { 334 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 335 LT.second)) 336 return LT.first * Entry->Cost; 337 } 338 339 static const CostTblEntry AVX2UniformConstCostTable[] = { 340 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 341 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 342 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 343 344 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 345 346 { ISD::SDIV, MVT::v8i32, 6 }, // pmuludq sequence 347 { ISD::SREM, MVT::v8i32, 8 }, // pmuludq+mul+sub sequence 348 { ISD::UDIV, MVT::v8i32, 5 }, // pmuludq sequence 349 { ISD::UREM, MVT::v8i32, 7 }, // pmuludq+mul+sub sequence 350 }; 351 352 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 353 ST->hasAVX2()) { 354 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 355 LT.second)) 356 return LT.first * Entry->Cost; 357 } 358 359 static const CostTblEntry SSE2UniformConstCostTable[] = { 360 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 361 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 362 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 363 364 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 365 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 366 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 367 368 { ISD::SDIV, MVT::v8i32, 12+2 }, // 2*pmuludq sequence + split. 369 { ISD::SREM, MVT::v8i32, 16+2 }, // 2*pmuludq+mul+sub sequence + split. 370 { ISD::SDIV, MVT::v4i32, 6 }, // pmuludq sequence 371 { ISD::SREM, MVT::v4i32, 8 }, // pmuludq+mul+sub sequence 372 { ISD::UDIV, MVT::v8i32, 10+2 }, // 2*pmuludq sequence + split. 373 { ISD::UREM, MVT::v8i32, 14+2 }, // 2*pmuludq+mul+sub sequence + split. 374 { ISD::UDIV, MVT::v4i32, 5 }, // pmuludq sequence 375 { ISD::UREM, MVT::v4i32, 7 }, // pmuludq+mul+sub sequence 376 }; 377 378 // XOP has faster vXi8 shifts. 379 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 380 ST->hasSSE2() && !ST->hasXOP()) { 381 if (const auto *Entry = 382 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 383 return LT.first * Entry->Cost; 384 } 385 386 static const CostTblEntry AVX512BWConstCostTable[] = { 387 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 388 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 389 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 390 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 391 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 392 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 393 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 394 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 395 }; 396 397 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 398 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 399 ST->hasBWI()) { 400 if (const auto *Entry = 401 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 402 return LT.first * Entry->Cost; 403 } 404 405 static const CostTblEntry AVX512ConstCostTable[] = { 406 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 407 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 408 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 409 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 410 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 411 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 412 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 413 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 414 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 415 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 416 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 417 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 418 }; 419 420 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 421 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 422 ST->hasAVX512()) { 423 if (const auto *Entry = 424 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 425 return LT.first * Entry->Cost; 426 } 427 428 static const CostTblEntry AVX2ConstCostTable[] = { 429 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 430 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 431 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 432 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 433 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 434 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 435 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 436 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 437 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 438 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 439 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 440 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 441 }; 442 443 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 444 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 445 ST->hasAVX2()) { 446 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 447 return LT.first * Entry->Cost; 448 } 449 450 static const CostTblEntry SSE2ConstCostTable[] = { 451 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 452 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 453 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 454 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 455 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 456 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 457 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 458 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 459 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 460 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 461 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 462 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 463 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 464 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 465 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 466 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 467 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 468 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 469 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 470 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 471 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 472 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 473 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 474 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 475 }; 476 477 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 478 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 479 ST->hasSSE2()) { 480 // pmuldq sequence. 481 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 482 return LT.first * 32; 483 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 484 return LT.first * 38; 485 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 486 return LT.first * 15; 487 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 488 return LT.first * 20; 489 490 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 491 return LT.first * Entry->Cost; 492 } 493 494 static const CostTblEntry AVX512BWShiftCostTable[] = { 495 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 496 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 497 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 498 499 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 500 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 501 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 502 503 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 504 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 505 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 506 }; 507 508 if (ST->hasBWI()) 509 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 510 return LT.first * Entry->Cost; 511 512 static const CostTblEntry AVX2UniformCostTable[] = { 513 // Uniform splats are cheaper for the following instructions. 514 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 515 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 516 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 517 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 518 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 519 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 520 }; 521 522 if (ST->hasAVX2() && 523 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 524 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 525 if (const auto *Entry = 526 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 527 return LT.first * Entry->Cost; 528 } 529 530 static const CostTblEntry SSE2UniformCostTable[] = { 531 // Uniform splats are cheaper for the following instructions. 532 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 533 { ISD::SHL, MVT::v4i32, 1 }, // pslld 534 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 535 536 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 537 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 538 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 539 540 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 541 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 542 }; 543 544 if (ST->hasSSE2() && 545 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 546 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 547 if (const auto *Entry = 548 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 549 return LT.first * Entry->Cost; 550 } 551 552 static const CostTblEntry AVX512DQCostTable[] = { 553 { ISD::MUL, MVT::v2i64, 1 }, 554 { ISD::MUL, MVT::v4i64, 1 }, 555 { ISD::MUL, MVT::v8i64, 1 } 556 }; 557 558 // Look for AVX512DQ lowering tricks for custom cases. 559 if (ST->hasDQI()) 560 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 561 return LT.first * Entry->Cost; 562 563 static const CostTblEntry AVX512BWCostTable[] = { 564 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 565 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 566 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 567 568 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence. 569 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence. 570 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence. 571 }; 572 573 // Look for AVX512BW lowering tricks for custom cases. 574 if (ST->hasBWI()) 575 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 576 return LT.first * Entry->Cost; 577 578 static const CostTblEntry AVX512CostTable[] = { 579 { ISD::SHL, MVT::v16i32, 1 }, 580 { ISD::SRL, MVT::v16i32, 1 }, 581 { ISD::SRA, MVT::v16i32, 1 }, 582 583 { ISD::SHL, MVT::v8i64, 1 }, 584 { ISD::SRL, MVT::v8i64, 1 }, 585 586 { ISD::SRA, MVT::v2i64, 1 }, 587 { ISD::SRA, MVT::v4i64, 1 }, 588 { ISD::SRA, MVT::v8i64, 1 }, 589 590 { ISD::MUL, MVT::v64i8, 26 }, // extend/pmullw/trunc sequence. 591 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence. 592 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence. 593 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 594 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 595 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 596 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add 597 598 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 599 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 600 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 601 602 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 603 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 604 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 605 }; 606 607 if (ST->hasAVX512()) 608 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 609 return LT.first * Entry->Cost; 610 611 static const CostTblEntry AVX2ShiftCostTable[] = { 612 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 613 // customize them to detect the cases where shift amount is a scalar one. 614 { ISD::SHL, MVT::v4i32, 1 }, 615 { ISD::SRL, MVT::v4i32, 1 }, 616 { ISD::SRA, MVT::v4i32, 1 }, 617 { ISD::SHL, MVT::v8i32, 1 }, 618 { ISD::SRL, MVT::v8i32, 1 }, 619 { ISD::SRA, MVT::v8i32, 1 }, 620 { ISD::SHL, MVT::v2i64, 1 }, 621 { ISD::SRL, MVT::v2i64, 1 }, 622 { ISD::SHL, MVT::v4i64, 1 }, 623 { ISD::SRL, MVT::v4i64, 1 }, 624 }; 625 626 if (ST->hasAVX512()) { 627 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 628 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 629 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 630 // On AVX512, a packed v32i16 shift left by a constant build_vector 631 // is lowered into a vector multiply (vpmullw). 632 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 633 Op1Info, Op2Info, 634 TargetTransformInfo::OP_None, 635 TargetTransformInfo::OP_None); 636 } 637 638 // Look for AVX2 lowering tricks. 639 if (ST->hasAVX2()) { 640 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 641 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 642 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 643 // On AVX2, a packed v16i16 shift left by a constant build_vector 644 // is lowered into a vector multiply (vpmullw). 645 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 646 Op1Info, Op2Info, 647 TargetTransformInfo::OP_None, 648 TargetTransformInfo::OP_None); 649 650 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 651 return LT.first * Entry->Cost; 652 } 653 654 static const CostTblEntry XOPShiftCostTable[] = { 655 // 128bit shifts take 1cy, but right shifts require negation beforehand. 656 { ISD::SHL, MVT::v16i8, 1 }, 657 { ISD::SRL, MVT::v16i8, 2 }, 658 { ISD::SRA, MVT::v16i8, 2 }, 659 { ISD::SHL, MVT::v8i16, 1 }, 660 { ISD::SRL, MVT::v8i16, 2 }, 661 { ISD::SRA, MVT::v8i16, 2 }, 662 { ISD::SHL, MVT::v4i32, 1 }, 663 { ISD::SRL, MVT::v4i32, 2 }, 664 { ISD::SRA, MVT::v4i32, 2 }, 665 { ISD::SHL, MVT::v2i64, 1 }, 666 { ISD::SRL, MVT::v2i64, 2 }, 667 { ISD::SRA, MVT::v2i64, 2 }, 668 // 256bit shifts require splitting if AVX2 didn't catch them above. 669 { ISD::SHL, MVT::v32i8, 2+2 }, 670 { ISD::SRL, MVT::v32i8, 4+2 }, 671 { ISD::SRA, MVT::v32i8, 4+2 }, 672 { ISD::SHL, MVT::v16i16, 2+2 }, 673 { ISD::SRL, MVT::v16i16, 4+2 }, 674 { ISD::SRA, MVT::v16i16, 4+2 }, 675 { ISD::SHL, MVT::v8i32, 2+2 }, 676 { ISD::SRL, MVT::v8i32, 4+2 }, 677 { ISD::SRA, MVT::v8i32, 4+2 }, 678 { ISD::SHL, MVT::v4i64, 2+2 }, 679 { ISD::SRL, MVT::v4i64, 4+2 }, 680 { ISD::SRA, MVT::v4i64, 4+2 }, 681 }; 682 683 // Look for XOP lowering tricks. 684 if (ST->hasXOP()) { 685 // If the right shift is constant then we'll fold the negation so 686 // it's as cheap as a left shift. 687 int ShiftISD = ISD; 688 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 689 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 690 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 691 ShiftISD = ISD::SHL; 692 if (const auto *Entry = 693 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 694 return LT.first * Entry->Cost; 695 } 696 697 static const CostTblEntry SSE2UniformShiftCostTable[] = { 698 // Uniform splats are cheaper for the following instructions. 699 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 700 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 701 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 702 703 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 704 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 705 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 706 707 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 708 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 709 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 710 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 711 }; 712 713 if (ST->hasSSE2() && 714 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 715 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 716 717 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 718 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 719 return LT.first * 4; // 2*psrad + shuffle. 720 721 if (const auto *Entry = 722 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 723 return LT.first * Entry->Cost; 724 } 725 726 if (ISD == ISD::SHL && 727 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 728 MVT VT = LT.second; 729 // Vector shift left by non uniform constant can be lowered 730 // into vector multiply. 731 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 732 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 733 ISD = ISD::MUL; 734 } 735 736 static const CostTblEntry AVX2CostTable[] = { 737 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. 738 { ISD::SHL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. 739 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 740 { ISD::SHL, MVT::v32i16, 20 }, // 2*extend/vpsrlvd/pack sequence. 741 742 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. 743 { ISD::SRL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. 744 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 745 { ISD::SRL, MVT::v32i16, 20 }, // 2*extend/vpsrlvd/pack sequence. 746 747 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. 748 { ISD::SRA, MVT::v64i8, 48 }, // 2*vpblendvb sequence. 749 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. 750 { ISD::SRA, MVT::v32i16, 20 }, // 2*extend/vpsravd/pack sequence. 751 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. 752 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 753 754 { ISD::SUB, MVT::v32i8, 1 }, // psubb 755 { ISD::ADD, MVT::v32i8, 1 }, // paddb 756 { ISD::SUB, MVT::v16i16, 1 }, // psubw 757 { ISD::ADD, MVT::v16i16, 1 }, // paddw 758 { ISD::SUB, MVT::v8i32, 1 }, // psubd 759 { ISD::ADD, MVT::v8i32, 1 }, // paddd 760 { ISD::SUB, MVT::v4i64, 1 }, // psubq 761 { ISD::ADD, MVT::v4i64, 1 }, // paddq 762 763 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence. 764 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence. 765 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 766 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 767 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add 768 769 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 770 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 771 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 772 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 773 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 774 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 775 776 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 777 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 778 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 779 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 780 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 781 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 782 }; 783 784 // Look for AVX2 lowering tricks for custom cases. 785 if (ST->hasAVX2()) 786 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 787 return LT.first * Entry->Cost; 788 789 static const CostTblEntry AVX1CostTable[] = { 790 // We don't have to scalarize unsupported ops. We can issue two half-sized 791 // operations and we only need to extract the upper YMM half. 792 // Two ops + 1 extract + 1 insert = 4. 793 { ISD::MUL, MVT::v16i16, 4 }, 794 { ISD::MUL, MVT::v8i32, 4 }, 795 { ISD::SUB, MVT::v32i8, 4 }, 796 { ISD::ADD, MVT::v32i8, 4 }, 797 { ISD::SUB, MVT::v16i16, 4 }, 798 { ISD::ADD, MVT::v16i16, 4 }, 799 { ISD::SUB, MVT::v8i32, 4 }, 800 { ISD::ADD, MVT::v8i32, 4 }, 801 { ISD::SUB, MVT::v4i64, 4 }, 802 { ISD::ADD, MVT::v4i64, 4 }, 803 804 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 805 // are lowered as a series of long multiplies(3), shifts(3) and adds(2) 806 // Because we believe v4i64 to be a legal type, we must also include the 807 // extract+insert in the cost table. Therefore, the cost here is 18 808 // instead of 8. 809 { ISD::MUL, MVT::v4i64, 18 }, 810 811 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence. 812 813 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 814 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 815 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 816 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 817 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 818 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 819 }; 820 821 if (ST->hasAVX()) 822 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 823 return LT.first * Entry->Cost; 824 825 static const CostTblEntry SSE42CostTable[] = { 826 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 827 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 828 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 829 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 830 831 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 832 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 833 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 834 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 835 836 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 837 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 838 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 839 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 840 841 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 842 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 843 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 844 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 845 }; 846 847 if (ST->hasSSE42()) 848 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 849 return LT.first * Entry->Cost; 850 851 static const CostTblEntry SSE41CostTable[] = { 852 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 853 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split. 854 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 855 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 856 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 857 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split 858 859 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 860 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split. 861 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 862 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 863 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 864 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split. 865 866 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 867 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split. 868 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 869 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 870 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 871 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split. 872 873 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 874 }; 875 876 if (ST->hasSSE41()) 877 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 878 return LT.first * Entry->Cost; 879 880 static const CostTblEntry SSE2CostTable[] = { 881 // We don't correctly identify costs of casts because they are marked as 882 // custom. 883 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 884 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 885 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 886 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 887 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 888 889 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 890 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 891 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 892 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 893 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 894 895 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 896 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 897 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 898 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 899 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split. 900 901 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence. 902 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 903 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 904 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 905 906 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 907 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 908 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 909 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 910 911 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 912 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 913 914 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 915 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 916 }; 917 918 if (ST->hasSSE2()) 919 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 920 return LT.first * Entry->Cost; 921 922 static const CostTblEntry SSE1CostTable[] = { 923 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 924 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 925 926 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 927 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 928 929 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 930 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 931 932 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 933 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 934 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 935 936 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 937 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 938 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 939 }; 940 941 if (ST->hasSSE1()) 942 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 943 return LT.first * Entry->Cost; 944 945 // It is not a good idea to vectorize division. We have to scalarize it and 946 // in the process we will often end up having to spilling regular 947 // registers. The overhead of division is going to dominate most kernels 948 // anyways so try hard to prevent vectorization of division - it is 949 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 950 // to hide "20 cycles" for each lane. 951 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 952 ISD == ISD::UDIV || ISD == ISD::UREM)) { 953 InstructionCost ScalarCost = getArithmeticInstrCost( 954 Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info, 955 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 956 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 957 } 958 959 // Fallback to the default implementation. 960 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info); 961 } 962 963 InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, 964 VectorType *BaseTp, 965 ArrayRef<int> Mask, int Index, 966 VectorType *SubTp) { 967 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 968 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 969 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 970 971 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 972 if (Kind == TTI::SK_Transpose) 973 Kind = TTI::SK_PermuteTwoSrc; 974 975 // For Broadcasts we are splatting the first element from the first input 976 // register, so only need to reference that input and all the output 977 // registers are the same. 978 if (Kind == TTI::SK_Broadcast) 979 LT.first = 1; 980 981 // Subvector extractions are free if they start at the beginning of a 982 // vector and cheap if the subvectors are aligned. 983 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 984 int NumElts = LT.second.getVectorNumElements(); 985 if ((Index % NumElts) == 0) 986 return 0; 987 std::pair<int, MVT> SubLT = TLI->getTypeLegalizationCost(DL, SubTp); 988 if (SubLT.second.isVector()) { 989 int NumSubElts = SubLT.second.getVectorNumElements(); 990 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 991 return SubLT.first; 992 // Handle some cases for widening legalization. For now we only handle 993 // cases where the original subvector was naturally aligned and evenly 994 // fit in its legalized subvector type. 995 // FIXME: Remove some of the alignment restrictions. 996 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 997 // vectors. 998 int OrigSubElts = cast<FixedVectorType>(SubTp)->getNumElements(); 999 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 1000 (NumSubElts % OrigSubElts) == 0 && 1001 LT.second.getVectorElementType() == 1002 SubLT.second.getVectorElementType() && 1003 LT.second.getVectorElementType().getSizeInBits() == 1004 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 1005 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 1006 "Unexpected number of elements!"); 1007 auto *VecTy = FixedVectorType::get(BaseTp->getElementType(), 1008 LT.second.getVectorNumElements()); 1009 auto *SubTy = FixedVectorType::get(BaseTp->getElementType(), 1010 SubLT.second.getVectorNumElements()); 1011 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 1012 InstructionCost ExtractCost = getShuffleCost( 1013 TTI::SK_ExtractSubvector, VecTy, None, ExtractIndex, SubTy); 1014 1015 // If the original size is 32-bits or more, we can use pshufd. Otherwise 1016 // if we have SSSE3 we can use pshufb. 1017 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 1018 return ExtractCost + 1; // pshufd or pshufb 1019 1020 assert(SubTp->getPrimitiveSizeInBits() == 16 && 1021 "Unexpected vector size"); 1022 1023 return ExtractCost + 2; // worst case pshufhw + pshufd 1024 } 1025 } 1026 } 1027 1028 // Handle some common (illegal) sub-vector types as they are often very cheap 1029 // to shuffle even on targets without PSHUFB. 1030 EVT VT = TLI->getValueType(DL, BaseTp); 1031 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 1032 !ST->hasSSSE3()) { 1033 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 1034 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 1035 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1036 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1037 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1038 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1039 1040 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1041 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1042 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1043 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1044 1045 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1046 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1047 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1048 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1049 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1050 1051 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1052 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1053 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1054 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1055 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1056 }; 1057 1058 if (ST->hasSSE2()) 1059 if (const auto *Entry = 1060 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1061 return Entry->Cost; 1062 } 1063 1064 // We are going to permute multiple sources and the result will be in multiple 1065 // destinations. Providing an accurate cost only for splits where the element 1066 // type remains the same. 1067 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1068 MVT LegalVT = LT.second; 1069 if (LegalVT.isVector() && 1070 LegalVT.getVectorElementType().getSizeInBits() == 1071 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1072 LegalVT.getVectorNumElements() < 1073 cast<FixedVectorType>(BaseTp)->getNumElements()) { 1074 1075 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1076 unsigned LegalVTSize = LegalVT.getStoreSize(); 1077 // Number of source vectors after legalization: 1078 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1079 // Number of destination vectors after legalization: 1080 unsigned NumOfDests = LT.first; 1081 1082 auto *SingleOpTy = FixedVectorType::get(BaseTp->getElementType(), 1083 LegalVT.getVectorNumElements()); 1084 1085 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1086 return NumOfShuffles * getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 1087 None, 0, nullptr); 1088 } 1089 1090 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1091 } 1092 1093 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1094 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1095 // We assume that source and destination have the same vector type. 1096 int NumOfDests = LT.first; 1097 int NumOfShufflesPerDest = LT.first * 2 - 1; 1098 LT.first = NumOfDests * NumOfShufflesPerDest; 1099 } 1100 1101 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1102 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1103 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1104 1105 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1106 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1107 1108 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b 1109 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b 1110 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2} // vpermt2b 1111 }; 1112 1113 if (ST->hasVBMI()) 1114 if (const auto *Entry = 1115 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1116 return LT.first * Entry->Cost; 1117 1118 static const CostTblEntry AVX512BWShuffleTbl[] = { 1119 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1120 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1121 1122 {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw 1123 {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw 1124 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1125 1126 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw 1127 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw 1128 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1129 1130 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w 1131 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w 1132 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2}, // vpermt2w 1133 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1134 1135 {TTI::SK_Select, MVT::v32i16, 1}, // vblendmw 1136 {TTI::SK_Select, MVT::v64i8, 1}, // vblendmb 1137 }; 1138 1139 if (ST->hasBWI()) 1140 if (const auto *Entry = 1141 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1142 return LT.first * Entry->Cost; 1143 1144 static const CostTblEntry AVX512ShuffleTbl[] = { 1145 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1146 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1147 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1148 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1149 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1150 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1151 1152 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1153 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1154 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1155 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1156 1157 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1158 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1159 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1160 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1161 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1162 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1163 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1164 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1165 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1166 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1167 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1168 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1169 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1170 1171 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1172 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1173 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1174 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1175 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1176 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1177 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1178 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1179 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1180 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1181 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1182 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1183 1184 // FIXME: This just applies the type legalization cost rules above 1185 // assuming these completely split. 1186 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1187 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1188 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1189 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1190 1191 {TTI::SK_Select, MVT::v32i16, 1}, // vpternlogq 1192 {TTI::SK_Select, MVT::v64i8, 1}, // vpternlogq 1193 {TTI::SK_Select, MVT::v8f64, 1}, // vblendmpd 1194 {TTI::SK_Select, MVT::v16f32, 1}, // vblendmps 1195 {TTI::SK_Select, MVT::v8i64, 1}, // vblendmq 1196 {TTI::SK_Select, MVT::v16i32, 1}, // vblendmd 1197 }; 1198 1199 if (ST->hasAVX512()) 1200 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1201 return LT.first * Entry->Cost; 1202 1203 static const CostTblEntry AVX2ShuffleTbl[] = { 1204 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1205 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1206 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1207 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1208 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1209 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1210 1211 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1212 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1213 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1214 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1215 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1216 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1217 1218 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1219 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1220 1221 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1222 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1223 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1224 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1225 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1226 // + vpblendvb 1227 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1228 // + vpblendvb 1229 1230 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1231 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1232 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1233 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1234 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1235 // + vpblendvb 1236 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1237 // + vpblendvb 1238 }; 1239 1240 if (ST->hasAVX2()) 1241 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1242 return LT.first * Entry->Cost; 1243 1244 static const CostTblEntry XOPShuffleTbl[] = { 1245 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1246 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1247 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1248 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1249 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1250 // + vinsertf128 1251 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1252 // + vinsertf128 1253 1254 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1255 // + vinsertf128 1256 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1257 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1258 // + vinsertf128 1259 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1260 }; 1261 1262 if (ST->hasXOP()) 1263 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1264 return LT.first * Entry->Cost; 1265 1266 static const CostTblEntry AVX1ShuffleTbl[] = { 1267 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1268 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1269 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1270 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1271 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1272 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1273 1274 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1275 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1276 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1277 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1278 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1279 // + vinsertf128 1280 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1281 // + vinsertf128 1282 1283 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1284 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1285 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1286 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1287 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1288 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1289 1290 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1291 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1292 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1293 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1294 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1295 // + 2*por + vinsertf128 1296 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1297 // + 2*por + vinsertf128 1298 1299 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1300 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1301 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1302 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1303 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1304 // + 4*por + vinsertf128 1305 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1306 // + 4*por + vinsertf128 1307 }; 1308 1309 if (ST->hasAVX()) 1310 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1311 return LT.first * Entry->Cost; 1312 1313 static const CostTblEntry SSE41ShuffleTbl[] = { 1314 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1315 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1316 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1317 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1318 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1319 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1320 }; 1321 1322 if (ST->hasSSE41()) 1323 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1324 return LT.first * Entry->Cost; 1325 1326 static const CostTblEntry SSSE3ShuffleTbl[] = { 1327 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1328 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1329 1330 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1331 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1332 1333 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1334 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1335 1336 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1337 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1338 1339 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1340 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1341 }; 1342 1343 if (ST->hasSSSE3()) 1344 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1345 return LT.first * Entry->Cost; 1346 1347 static const CostTblEntry SSE2ShuffleTbl[] = { 1348 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1349 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1350 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1351 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1352 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1353 1354 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1355 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1356 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1357 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1358 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1359 // + 2*pshufd + 2*unpck + packus 1360 1361 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1362 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1363 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1364 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1365 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1366 1367 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1368 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1369 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1370 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1371 // + pshufd/unpck 1372 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1373 // + 2*pshufd + 2*unpck + 2*packus 1374 1375 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1376 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1377 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1378 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1379 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1380 }; 1381 1382 if (ST->hasSSE2()) 1383 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1384 return LT.first * Entry->Cost; 1385 1386 static const CostTblEntry SSE1ShuffleTbl[] = { 1387 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1388 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1389 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1390 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1391 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1392 }; 1393 1394 if (ST->hasSSE1()) 1395 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1396 return LT.first * Entry->Cost; 1397 1398 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1399 } 1400 1401 InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, 1402 Type *Src, 1403 TTI::CastContextHint CCH, 1404 TTI::TargetCostKind CostKind, 1405 const Instruction *I) { 1406 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1407 assert(ISD && "Invalid opcode"); 1408 1409 // TODO: Allow non-throughput costs that aren't binary. 1410 auto AdjustCost = [&CostKind](InstructionCost Cost) -> InstructionCost { 1411 if (CostKind != TTI::TCK_RecipThroughput) 1412 return Cost == 0 ? 0 : 1; 1413 return Cost; 1414 }; 1415 1416 // FIXME: Need a better design of the cost table to handle non-simple types of 1417 // potential massive combinations (elem_num x src_type x dst_type). 1418 1419 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1420 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1421 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1422 1423 // Mask sign extend has an instruction. 1424 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1425 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1426 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1427 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1428 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1429 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1430 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1431 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1432 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1433 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1434 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1435 1436 // Mask zero extend is a sext + shift. 1437 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1438 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1439 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1440 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1441 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1442 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1443 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1444 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1445 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1446 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1447 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1448 1449 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, 1450 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm 1451 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // widen to zmm 1452 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // widen to zmm 1453 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // widen to zmm 1454 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // widen to zmm 1455 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // widen to zmm 1456 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // widen to zmm 1457 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // widen to zmm 1458 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // widen to zmm 1459 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // widen to zmm 1460 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, 1461 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, 1462 }; 1463 1464 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1465 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1466 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1467 1468 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1469 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1470 1471 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1472 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1473 1474 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1475 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1476 }; 1477 1478 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1479 // 256-bit wide vectors. 1480 1481 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1482 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1483 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1484 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1485 1486 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1487 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1488 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1489 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd 1490 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1491 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1492 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1493 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd 1494 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd 1495 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd 1496 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd 1497 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd 1498 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq 1499 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq 1500 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq 1501 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, 1502 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, 1503 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, 1504 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, 1505 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 1506 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd 1507 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb 1508 1509 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32 1510 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, 1511 1512 // Sign extend is zmm vpternlogd+vptruncdb. 1513 // Zero extend is zmm broadcast load+vptruncdw. 1514 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 }, 1515 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 }, 1516 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, 1517 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, 1518 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, 1519 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, 1520 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 }, 1521 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 }, 1522 1523 // Sign extend is zmm vpternlogd+vptruncdw. 1524 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw. 1525 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 }, 1526 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1527 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 }, 1528 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1529 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 }, 1530 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1531 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 }, 1532 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1533 1534 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd 1535 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld 1536 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd 1537 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld 1538 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd 1539 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld 1540 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq 1541 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq 1542 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq 1543 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq 1544 1545 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd 1546 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld 1547 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq 1548 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq 1549 1550 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1551 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1552 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1553 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1554 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1555 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1556 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1557 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1558 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1559 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1560 1561 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1562 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1563 1564 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1565 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1566 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1567 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1568 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1569 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1570 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1571 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1572 1573 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1574 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1575 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1576 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1577 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1578 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1579 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1580 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1581 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1582 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1583 1584 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f64, 3 }, 1585 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, 1586 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 3 }, 1587 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 3 }, 1588 1589 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1590 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, 1591 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, 1592 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1593 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, 1594 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, 1595 }; 1596 1597 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1598 // Mask sign extend has an instruction. 1599 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1600 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1601 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1602 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1603 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1604 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1605 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1606 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1607 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1608 1609 // Mask zero extend is a sext + shift. 1610 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1611 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1612 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1613 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1614 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1615 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1616 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1617 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1618 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1619 1620 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, 1621 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // vpsllw+vptestmb 1622 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // vpsllw+vptestmw 1623 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // vpsllw+vptestmb 1624 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // vpsllw+vptestmw 1625 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // vpsllw+vptestmb 1626 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // vpsllw+vptestmw 1627 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // vpsllw+vptestmb 1628 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // vpsllw+vptestmw 1629 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // vpsllw+vptestmb 1630 }; 1631 1632 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1633 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1634 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1635 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1636 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1637 1638 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1639 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1640 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1641 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1642 1643 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1644 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1645 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1646 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1647 1648 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1649 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1650 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1651 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1652 }; 1653 1654 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 1655 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1656 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1657 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1658 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 8 }, // split+2*v8i8 1659 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1660 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1661 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1662 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16 1663 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // vpslld+vptestmd 1664 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd 1665 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // vpslld+vptestmd 1666 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // vpsllq+vptestmq 1667 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // vpsllq+vptestmq 1668 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // vpmovqd 1669 1670 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb 1671 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb 1672 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 }, 1673 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 }, 1674 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 }, 1675 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 }, 1676 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 }, 1677 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 }, 1678 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 }, 1679 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 }, 1680 1681 // sign extend is vpcmpeq+maskedmove+vpmovdw 1682 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw 1683 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1684 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 }, 1685 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1686 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 }, 1687 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1688 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 }, 1689 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 }, 1690 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 }, 1691 1692 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd 1693 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld 1694 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd 1695 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld 1696 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd 1697 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld 1698 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq 1699 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq 1700 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq 1701 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq 1702 1703 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1704 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1705 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1706 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1707 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1708 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1709 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1710 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1711 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1712 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1713 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1714 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1715 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1716 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1717 1718 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 1719 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1720 1721 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 3 }, 1722 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 3 }, 1723 1724 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 1725 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 1726 1727 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1728 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1729 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 1 }, 1730 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1731 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1732 }; 1733 1734 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1735 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1736 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1737 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1738 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1739 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1740 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1741 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1742 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1743 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1744 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1745 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1746 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1747 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1748 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1749 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1750 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1751 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1752 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1753 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1754 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1755 1756 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1757 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1758 1759 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 1760 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 1761 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 1762 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1763 1764 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1765 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1766 1767 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1768 }; 1769 1770 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1771 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1772 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1773 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1774 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1775 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1776 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1777 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1778 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1779 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1780 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1781 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1782 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1783 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 4 }, 1784 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1785 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1786 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1787 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1788 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1789 1790 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 4 }, 1791 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 5 }, 1792 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 4 }, 1793 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 9 }, 1794 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, 11 }, 1795 1796 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 1797 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1798 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1799 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1800 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 1801 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1802 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 11 }, 1803 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 9 }, 1804 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 }, 1805 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 11 }, 1806 1807 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1808 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1809 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1810 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1811 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1812 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1813 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1814 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1815 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1816 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1817 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1818 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1819 1820 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1821 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1822 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1823 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1824 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1825 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1826 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1827 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1828 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1829 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 }, 1830 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 1831 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1832 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 1833 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1834 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1835 // The generic code to compute the scalar overhead is currently broken. 1836 // Workaround this limitation by estimating the scalarization overhead 1837 // here. We have roughly 10 instructions per scalar element. 1838 // Multiply that by the vector width. 1839 // FIXME: remove that when PR19268 is fixed. 1840 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1841 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1842 1843 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 4 }, 1844 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f64, 3 }, 1845 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f64, 2 }, 1846 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 3 }, 1847 1848 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f64, 3 }, 1849 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f64, 2 }, 1850 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 4 }, 1851 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 3 }, 1852 // This node is expanded into scalarized operations but BasicTTI is overly 1853 // optimistic estimating its cost. It computes 3 per element (one 1854 // vector-extract, one scalar conversion and one vector-insert). The 1855 // problem is that the inserts form a read-modify-write chain so latency 1856 // should be factored in too. Inflating the cost per element by 1. 1857 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, 1858 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 1859 1860 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 1861 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 1862 }; 1863 1864 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 1865 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1866 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1867 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1868 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1869 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1870 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1871 1872 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1873 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 }, 1874 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1875 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1876 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1877 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1878 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1879 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1880 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1881 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1882 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1883 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1884 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1885 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1886 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1887 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1888 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1889 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1890 1891 // These truncates end up widening elements. 1892 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 1 }, // PMOVXZBQ 1893 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 1 }, // PMOVXZWQ 1894 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 1 }, // PMOVXZBD 1895 1896 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 1 }, 1897 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 1 }, 1898 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 1899 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 1900 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 1901 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 1902 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 1903 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 1904 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 1 }, // PSHUFB 1905 1906 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 1907 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 1908 1909 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 3 }, 1910 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 3 }, 1911 1912 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 3 }, 1913 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 3 }, 1914 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, 1915 }; 1916 1917 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 1918 // These are somewhat magic numbers justified by looking at the output of 1919 // Intel's IACA, running some kernels and making sure when we take 1920 // legalization into account the throughput will be overestimated. 1921 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1922 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1923 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1924 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1925 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1926 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 2*10 }, 1927 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2*10 }, 1928 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1929 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 1930 1931 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1932 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1933 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1934 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1935 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1936 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, 1937 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 }, 1938 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1939 1940 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 4 }, 1941 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 2 }, 1942 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, 1943 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, 1944 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, 1945 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 4 }, 1946 1947 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 1 }, 1948 1949 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 6 }, 1950 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 }, 1951 1952 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 1953 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 1954 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 4 }, 1955 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 4 }, 1956 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 }, 1957 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 2 }, 1958 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 }, 1959 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 4 }, 1960 1961 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1962 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 1963 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 1964 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 1965 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1966 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 1967 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1968 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 1969 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1970 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1971 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1972 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1973 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 1974 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 1975 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1976 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 1977 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1978 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 1979 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1980 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1981 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 1982 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 1983 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1984 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 1985 1986 // These truncates are really widening elements. 1987 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 1 }, // PSHUFD 1988 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // PUNPCKLWD+DQ 1989 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // PUNPCKLBW+WD+PSHUFD 1990 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 1 }, // PUNPCKLWD 1991 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // PUNPCKLBW+WD 1992 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 1 }, // PUNPCKLBW 1993 1994 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // PAND+PACKUSWB 1995 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // PAND+PACKUSWB 1996 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // PAND+PACKUSWB 1997 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 1998 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 3 }, // PAND+2*PACKUSWB 1999 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 2000 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 2001 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 2002 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 2003 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 2004 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2005 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 2006 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 2007 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 2008 { ISD::TRUNCATE, MVT::v2i32, MVT::v2i64, 1 }, // PSHUFD 2009 }; 2010 2011 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 2012 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst); 2013 2014 if (ST->hasSSE2() && !ST->hasAVX()) { 2015 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2016 LTDest.second, LTSrc.second)) 2017 return AdjustCost(LTSrc.first * Entry->Cost); 2018 } 2019 2020 EVT SrcTy = TLI->getValueType(DL, Src); 2021 EVT DstTy = TLI->getValueType(DL, Dst); 2022 2023 // The function getSimpleVT only handles simple value types. 2024 if (!SrcTy.isSimple() || !DstTy.isSimple()) 2025 return AdjustCost(BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind)); 2026 2027 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 2028 MVT SimpleDstTy = DstTy.getSimpleVT(); 2029 2030 if (ST->useAVX512Regs()) { 2031 if (ST->hasBWI()) 2032 if (const auto *Entry = ConvertCostTableLookup(AVX512BWConversionTbl, ISD, 2033 SimpleDstTy, SimpleSrcTy)) 2034 return AdjustCost(Entry->Cost); 2035 2036 if (ST->hasDQI()) 2037 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 2038 SimpleDstTy, SimpleSrcTy)) 2039 return AdjustCost(Entry->Cost); 2040 2041 if (ST->hasAVX512()) 2042 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 2043 SimpleDstTy, SimpleSrcTy)) 2044 return AdjustCost(Entry->Cost); 2045 } 2046 2047 if (ST->hasBWI()) 2048 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 2049 SimpleDstTy, SimpleSrcTy)) 2050 return AdjustCost(Entry->Cost); 2051 2052 if (ST->hasDQI()) 2053 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 2054 SimpleDstTy, SimpleSrcTy)) 2055 return AdjustCost(Entry->Cost); 2056 2057 if (ST->hasAVX512()) 2058 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2059 SimpleDstTy, SimpleSrcTy)) 2060 return AdjustCost(Entry->Cost); 2061 2062 if (ST->hasAVX2()) { 2063 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2064 SimpleDstTy, SimpleSrcTy)) 2065 return AdjustCost(Entry->Cost); 2066 } 2067 2068 if (ST->hasAVX()) { 2069 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2070 SimpleDstTy, SimpleSrcTy)) 2071 return AdjustCost(Entry->Cost); 2072 } 2073 2074 if (ST->hasSSE41()) { 2075 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2076 SimpleDstTy, SimpleSrcTy)) 2077 return AdjustCost(Entry->Cost); 2078 } 2079 2080 if (ST->hasSSE2()) { 2081 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2082 SimpleDstTy, SimpleSrcTy)) 2083 return AdjustCost(Entry->Cost); 2084 } 2085 2086 return AdjustCost( 2087 BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I)); 2088 } 2089 2090 InstructionCost X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 2091 Type *CondTy, 2092 CmpInst::Predicate VecPred, 2093 TTI::TargetCostKind CostKind, 2094 const Instruction *I) { 2095 // TODO: Handle other cost kinds. 2096 if (CostKind != TTI::TCK_RecipThroughput) 2097 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, 2098 I); 2099 2100 // Legalize the type. 2101 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2102 2103 MVT MTy = LT.second; 2104 2105 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2106 assert(ISD && "Invalid opcode"); 2107 2108 unsigned ExtraCost = 0; 2109 if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) { 2110 // Some vector comparison predicates cost extra instructions. 2111 if (MTy.isVector() && 2112 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 2113 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 2114 ST->hasBWI())) { 2115 switch (cast<CmpInst>(I)->getPredicate()) { 2116 case CmpInst::Predicate::ICMP_NE: 2117 // xor(cmpeq(x,y),-1) 2118 ExtraCost = 1; 2119 break; 2120 case CmpInst::Predicate::ICMP_SGE: 2121 case CmpInst::Predicate::ICMP_SLE: 2122 // xor(cmpgt(x,y),-1) 2123 ExtraCost = 1; 2124 break; 2125 case CmpInst::Predicate::ICMP_ULT: 2126 case CmpInst::Predicate::ICMP_UGT: 2127 // cmpgt(xor(x,signbit),xor(y,signbit)) 2128 // xor(cmpeq(pmaxu(x,y),x),-1) 2129 ExtraCost = 2; 2130 break; 2131 case CmpInst::Predicate::ICMP_ULE: 2132 case CmpInst::Predicate::ICMP_UGE: 2133 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 2134 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 2135 // cmpeq(psubus(x,y),0) 2136 // cmpeq(pminu(x,y),x) 2137 ExtraCost = 1; 2138 } else { 2139 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 2140 ExtraCost = 3; 2141 } 2142 break; 2143 default: 2144 break; 2145 } 2146 } 2147 } 2148 2149 static const CostTblEntry SLMCostTbl[] = { 2150 // slm pcmpeq/pcmpgt throughput is 2 2151 { ISD::SETCC, MVT::v2i64, 2 }, 2152 }; 2153 2154 static const CostTblEntry AVX512BWCostTbl[] = { 2155 { ISD::SETCC, MVT::v32i16, 1 }, 2156 { ISD::SETCC, MVT::v64i8, 1 }, 2157 2158 { ISD::SELECT, MVT::v32i16, 1 }, 2159 { ISD::SELECT, MVT::v64i8, 1 }, 2160 }; 2161 2162 static const CostTblEntry AVX512CostTbl[] = { 2163 { ISD::SETCC, MVT::v8i64, 1 }, 2164 { ISD::SETCC, MVT::v16i32, 1 }, 2165 { ISD::SETCC, MVT::v8f64, 1 }, 2166 { ISD::SETCC, MVT::v16f32, 1 }, 2167 2168 { ISD::SELECT, MVT::v8i64, 1 }, 2169 { ISD::SELECT, MVT::v16i32, 1 }, 2170 { ISD::SELECT, MVT::v8f64, 1 }, 2171 { ISD::SELECT, MVT::v16f32, 1 }, 2172 2173 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 2174 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 2175 2176 { ISD::SELECT, MVT::v32i16, 2 }, // FIXME: should be 3 2177 { ISD::SELECT, MVT::v64i8, 2 }, // FIXME: should be 3 2178 }; 2179 2180 static const CostTblEntry AVX2CostTbl[] = { 2181 { ISD::SETCC, MVT::v4i64, 1 }, 2182 { ISD::SETCC, MVT::v8i32, 1 }, 2183 { ISD::SETCC, MVT::v16i16, 1 }, 2184 { ISD::SETCC, MVT::v32i8, 1 }, 2185 2186 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 2187 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 2188 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 2189 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 2190 }; 2191 2192 static const CostTblEntry AVX1CostTbl[] = { 2193 { ISD::SETCC, MVT::v4f64, 1 }, 2194 { ISD::SETCC, MVT::v8f32, 1 }, 2195 // AVX1 does not support 8-wide integer compare. 2196 { ISD::SETCC, MVT::v4i64, 4 }, 2197 { ISD::SETCC, MVT::v8i32, 4 }, 2198 { ISD::SETCC, MVT::v16i16, 4 }, 2199 { ISD::SETCC, MVT::v32i8, 4 }, 2200 2201 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 2202 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 2203 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 2204 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 2205 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 2206 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 2207 }; 2208 2209 static const CostTblEntry SSE42CostTbl[] = { 2210 { ISD::SETCC, MVT::v2f64, 1 }, 2211 { ISD::SETCC, MVT::v4f32, 1 }, 2212 { ISD::SETCC, MVT::v2i64, 1 }, 2213 }; 2214 2215 static const CostTblEntry SSE41CostTbl[] = { 2216 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 2217 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 2218 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 2219 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 2220 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 2221 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 2222 }; 2223 2224 static const CostTblEntry SSE2CostTbl[] = { 2225 { ISD::SETCC, MVT::v2f64, 2 }, 2226 { ISD::SETCC, MVT::f64, 1 }, 2227 { ISD::SETCC, MVT::v2i64, 8 }, 2228 { ISD::SETCC, MVT::v4i32, 1 }, 2229 { ISD::SETCC, MVT::v8i16, 1 }, 2230 { ISD::SETCC, MVT::v16i8, 1 }, 2231 2232 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 2233 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 2234 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 2235 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 2236 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 2237 }; 2238 2239 static const CostTblEntry SSE1CostTbl[] = { 2240 { ISD::SETCC, MVT::v4f32, 2 }, 2241 { ISD::SETCC, MVT::f32, 1 }, 2242 2243 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 2244 }; 2245 2246 if (ST->isSLM()) 2247 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2248 return LT.first * (ExtraCost + Entry->Cost); 2249 2250 if (ST->hasBWI()) 2251 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2252 return LT.first * (ExtraCost + Entry->Cost); 2253 2254 if (ST->hasAVX512()) 2255 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2256 return LT.first * (ExtraCost + Entry->Cost); 2257 2258 if (ST->hasAVX2()) 2259 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2260 return LT.first * (ExtraCost + Entry->Cost); 2261 2262 if (ST->hasAVX()) 2263 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2264 return LT.first * (ExtraCost + Entry->Cost); 2265 2266 if (ST->hasSSE42()) 2267 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2268 return LT.first * (ExtraCost + Entry->Cost); 2269 2270 if (ST->hasSSE41()) 2271 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2272 return LT.first * (ExtraCost + Entry->Cost); 2273 2274 if (ST->hasSSE2()) 2275 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2276 return LT.first * (ExtraCost + Entry->Cost); 2277 2278 if (ST->hasSSE1()) 2279 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2280 return LT.first * (ExtraCost + Entry->Cost); 2281 2282 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I); 2283 } 2284 2285 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2286 2287 InstructionCost 2288 X86TTIImpl::getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 2289 TTI::TargetCostKind CostKind) { 2290 2291 // Costs should match the codegen from: 2292 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2293 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2294 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2295 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2296 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2297 2298 // TODO: Overflow intrinsics (*ADDO, *SUBO, *MULO) with vector types are not 2299 // specialized in these tables yet. 2300 static const CostTblEntry AVX512CDCostTbl[] = { 2301 { ISD::CTLZ, MVT::v8i64, 1 }, 2302 { ISD::CTLZ, MVT::v16i32, 1 }, 2303 { ISD::CTLZ, MVT::v32i16, 8 }, 2304 { ISD::CTLZ, MVT::v64i8, 20 }, 2305 { ISD::CTLZ, MVT::v4i64, 1 }, 2306 { ISD::CTLZ, MVT::v8i32, 1 }, 2307 { ISD::CTLZ, MVT::v16i16, 4 }, 2308 { ISD::CTLZ, MVT::v32i8, 10 }, 2309 { ISD::CTLZ, MVT::v2i64, 1 }, 2310 { ISD::CTLZ, MVT::v4i32, 1 }, 2311 { ISD::CTLZ, MVT::v8i16, 4 }, 2312 { ISD::CTLZ, MVT::v16i8, 4 }, 2313 }; 2314 static const CostTblEntry AVX512BWCostTbl[] = { 2315 { ISD::ABS, MVT::v32i16, 1 }, 2316 { ISD::ABS, MVT::v64i8, 1 }, 2317 { ISD::BITREVERSE, MVT::v8i64, 5 }, 2318 { ISD::BITREVERSE, MVT::v16i32, 5 }, 2319 { ISD::BITREVERSE, MVT::v32i16, 5 }, 2320 { ISD::BITREVERSE, MVT::v64i8, 5 }, 2321 { ISD::CTLZ, MVT::v8i64, 23 }, 2322 { ISD::CTLZ, MVT::v16i32, 22 }, 2323 { ISD::CTLZ, MVT::v32i16, 18 }, 2324 { ISD::CTLZ, MVT::v64i8, 17 }, 2325 { ISD::CTPOP, MVT::v8i64, 7 }, 2326 { ISD::CTPOP, MVT::v16i32, 11 }, 2327 { ISD::CTPOP, MVT::v32i16, 9 }, 2328 { ISD::CTPOP, MVT::v64i8, 6 }, 2329 { ISD::CTTZ, MVT::v8i64, 10 }, 2330 { ISD::CTTZ, MVT::v16i32, 14 }, 2331 { ISD::CTTZ, MVT::v32i16, 12 }, 2332 { ISD::CTTZ, MVT::v64i8, 9 }, 2333 { ISD::SADDSAT, MVT::v32i16, 1 }, 2334 { ISD::SADDSAT, MVT::v64i8, 1 }, 2335 { ISD::SMAX, MVT::v32i16, 1 }, 2336 { ISD::SMAX, MVT::v64i8, 1 }, 2337 { ISD::SMIN, MVT::v32i16, 1 }, 2338 { ISD::SMIN, MVT::v64i8, 1 }, 2339 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2340 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2341 { ISD::UADDSAT, MVT::v32i16, 1 }, 2342 { ISD::UADDSAT, MVT::v64i8, 1 }, 2343 { ISD::UMAX, MVT::v32i16, 1 }, 2344 { ISD::UMAX, MVT::v64i8, 1 }, 2345 { ISD::UMIN, MVT::v32i16, 1 }, 2346 { ISD::UMIN, MVT::v64i8, 1 }, 2347 { ISD::USUBSAT, MVT::v32i16, 1 }, 2348 { ISD::USUBSAT, MVT::v64i8, 1 }, 2349 }; 2350 static const CostTblEntry AVX512CostTbl[] = { 2351 { ISD::ABS, MVT::v8i64, 1 }, 2352 { ISD::ABS, MVT::v16i32, 1 }, 2353 { ISD::ABS, MVT::v32i16, 2 }, // FIXME: include split 2354 { ISD::ABS, MVT::v64i8, 2 }, // FIXME: include split 2355 { ISD::ABS, MVT::v4i64, 1 }, 2356 { ISD::ABS, MVT::v2i64, 1 }, 2357 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2358 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2359 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2360 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2361 { ISD::CTLZ, MVT::v8i64, 29 }, 2362 { ISD::CTLZ, MVT::v16i32, 35 }, 2363 { ISD::CTLZ, MVT::v32i16, 28 }, 2364 { ISD::CTLZ, MVT::v64i8, 18 }, 2365 { ISD::CTPOP, MVT::v8i64, 16 }, 2366 { ISD::CTPOP, MVT::v16i32, 24 }, 2367 { ISD::CTPOP, MVT::v32i16, 18 }, 2368 { ISD::CTPOP, MVT::v64i8, 12 }, 2369 { ISD::CTTZ, MVT::v8i64, 20 }, 2370 { ISD::CTTZ, MVT::v16i32, 28 }, 2371 { ISD::CTTZ, MVT::v32i16, 24 }, 2372 { ISD::CTTZ, MVT::v64i8, 18 }, 2373 { ISD::SMAX, MVT::v8i64, 1 }, 2374 { ISD::SMAX, MVT::v16i32, 1 }, 2375 { ISD::SMAX, MVT::v32i16, 2 }, // FIXME: include split 2376 { ISD::SMAX, MVT::v64i8, 2 }, // FIXME: include split 2377 { ISD::SMAX, MVT::v4i64, 1 }, 2378 { ISD::SMAX, MVT::v2i64, 1 }, 2379 { ISD::SMIN, MVT::v8i64, 1 }, 2380 { ISD::SMIN, MVT::v16i32, 1 }, 2381 { ISD::SMIN, MVT::v32i16, 2 }, // FIXME: include split 2382 { ISD::SMIN, MVT::v64i8, 2 }, // FIXME: include split 2383 { ISD::SMIN, MVT::v4i64, 1 }, 2384 { ISD::SMIN, MVT::v2i64, 1 }, 2385 { ISD::UMAX, MVT::v8i64, 1 }, 2386 { ISD::UMAX, MVT::v16i32, 1 }, 2387 { ISD::UMAX, MVT::v32i16, 2 }, // FIXME: include split 2388 { ISD::UMAX, MVT::v64i8, 2 }, // FIXME: include split 2389 { ISD::UMAX, MVT::v4i64, 1 }, 2390 { ISD::UMAX, MVT::v2i64, 1 }, 2391 { ISD::UMIN, MVT::v8i64, 1 }, 2392 { ISD::UMIN, MVT::v16i32, 1 }, 2393 { ISD::UMIN, MVT::v32i16, 2 }, // FIXME: include split 2394 { ISD::UMIN, MVT::v64i8, 2 }, // FIXME: include split 2395 { ISD::UMIN, MVT::v4i64, 1 }, 2396 { ISD::UMIN, MVT::v2i64, 1 }, 2397 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2398 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2399 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2400 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2401 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2402 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2403 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2404 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2405 { ISD::SADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2406 { ISD::SADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2407 { ISD::SSUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2408 { ISD::SSUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2409 { ISD::UADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2410 { ISD::UADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2411 { ISD::USUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2412 { ISD::USUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2413 { ISD::FMAXNUM, MVT::f32, 2 }, 2414 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2415 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2416 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2417 { ISD::FMAXNUM, MVT::f64, 2 }, 2418 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2419 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2420 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2421 }; 2422 static const CostTblEntry XOPCostTbl[] = { 2423 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2424 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2425 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2426 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2427 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2428 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2429 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2430 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2431 { ISD::BITREVERSE, MVT::i64, 3 }, 2432 { ISD::BITREVERSE, MVT::i32, 3 }, 2433 { ISD::BITREVERSE, MVT::i16, 3 }, 2434 { ISD::BITREVERSE, MVT::i8, 3 } 2435 }; 2436 static const CostTblEntry AVX2CostTbl[] = { 2437 { ISD::ABS, MVT::v4i64, 2 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2438 { ISD::ABS, MVT::v8i32, 1 }, 2439 { ISD::ABS, MVT::v16i16, 1 }, 2440 { ISD::ABS, MVT::v32i8, 1 }, 2441 { ISD::BITREVERSE, MVT::v4i64, 5 }, 2442 { ISD::BITREVERSE, MVT::v8i32, 5 }, 2443 { ISD::BITREVERSE, MVT::v16i16, 5 }, 2444 { ISD::BITREVERSE, MVT::v32i8, 5 }, 2445 { ISD::BSWAP, MVT::v4i64, 1 }, 2446 { ISD::BSWAP, MVT::v8i32, 1 }, 2447 { ISD::BSWAP, MVT::v16i16, 1 }, 2448 { ISD::CTLZ, MVT::v4i64, 23 }, 2449 { ISD::CTLZ, MVT::v8i32, 18 }, 2450 { ISD::CTLZ, MVT::v16i16, 14 }, 2451 { ISD::CTLZ, MVT::v32i8, 9 }, 2452 { ISD::CTPOP, MVT::v4i64, 7 }, 2453 { ISD::CTPOP, MVT::v8i32, 11 }, 2454 { ISD::CTPOP, MVT::v16i16, 9 }, 2455 { ISD::CTPOP, MVT::v32i8, 6 }, 2456 { ISD::CTTZ, MVT::v4i64, 10 }, 2457 { ISD::CTTZ, MVT::v8i32, 14 }, 2458 { ISD::CTTZ, MVT::v16i16, 12 }, 2459 { ISD::CTTZ, MVT::v32i8, 9 }, 2460 { ISD::SADDSAT, MVT::v16i16, 1 }, 2461 { ISD::SADDSAT, MVT::v32i8, 1 }, 2462 { ISD::SMAX, MVT::v8i32, 1 }, 2463 { ISD::SMAX, MVT::v16i16, 1 }, 2464 { ISD::SMAX, MVT::v32i8, 1 }, 2465 { ISD::SMIN, MVT::v8i32, 1 }, 2466 { ISD::SMIN, MVT::v16i16, 1 }, 2467 { ISD::SMIN, MVT::v32i8, 1 }, 2468 { ISD::SSUBSAT, MVT::v16i16, 1 }, 2469 { ISD::SSUBSAT, MVT::v32i8, 1 }, 2470 { ISD::UADDSAT, MVT::v16i16, 1 }, 2471 { ISD::UADDSAT, MVT::v32i8, 1 }, 2472 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 2473 { ISD::UMAX, MVT::v8i32, 1 }, 2474 { ISD::UMAX, MVT::v16i16, 1 }, 2475 { ISD::UMAX, MVT::v32i8, 1 }, 2476 { ISD::UMIN, MVT::v8i32, 1 }, 2477 { ISD::UMIN, MVT::v16i16, 1 }, 2478 { ISD::UMIN, MVT::v32i8, 1 }, 2479 { ISD::USUBSAT, MVT::v16i16, 1 }, 2480 { ISD::USUBSAT, MVT::v32i8, 1 }, 2481 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2482 { ISD::FMAXNUM, MVT::v8f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2483 { ISD::FMAXNUM, MVT::v4f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2484 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2485 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2486 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2487 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2488 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2489 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2490 }; 2491 static const CostTblEntry AVX1CostTbl[] = { 2492 { ISD::ABS, MVT::v4i64, 5 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2493 { ISD::ABS, MVT::v8i32, 3 }, 2494 { ISD::ABS, MVT::v16i16, 3 }, 2495 { ISD::ABS, MVT::v32i8, 3 }, 2496 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 2497 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 2498 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 2499 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 2500 { ISD::BSWAP, MVT::v4i64, 4 }, 2501 { ISD::BSWAP, MVT::v8i32, 4 }, 2502 { ISD::BSWAP, MVT::v16i16, 4 }, 2503 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 2504 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 2505 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 2506 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2507 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 2508 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 2509 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 2510 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 2511 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 2512 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 2513 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 2514 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2515 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2516 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2517 { ISD::SMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2518 { ISD::SMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2519 { ISD::SMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2520 { ISD::SMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2521 { ISD::SMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2522 { ISD::SMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2523 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2524 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2525 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2526 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2527 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 2528 { ISD::UMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2529 { ISD::UMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2530 { ISD::UMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2531 { ISD::UMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2532 { ISD::UMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2533 { ISD::UMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2534 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2535 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2536 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 2537 { ISD::FMAXNUM, MVT::f32, 3 }, // MAXSS + CMPUNORDSS + BLENDVPS 2538 { ISD::FMAXNUM, MVT::v4f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2539 { ISD::FMAXNUM, MVT::v8f32, 5 }, // MAXPS + CMPUNORDPS + BLENDVPS + ? 2540 { ISD::FMAXNUM, MVT::f64, 3 }, // MAXSD + CMPUNORDSD + BLENDVPD 2541 { ISD::FMAXNUM, MVT::v2f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2542 { ISD::FMAXNUM, MVT::v4f64, 5 }, // MAXPD + CMPUNORDPD + BLENDVPD + ? 2543 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 2544 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 2545 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 2546 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 2547 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 2548 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 2549 }; 2550 static const CostTblEntry GLMCostTbl[] = { 2551 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 2552 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 2553 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 2554 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 2555 }; 2556 static const CostTblEntry SLMCostTbl[] = { 2557 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 2558 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 2559 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 2560 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 2561 }; 2562 static const CostTblEntry SSE42CostTbl[] = { 2563 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 2564 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 2565 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 2566 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 2567 }; 2568 static const CostTblEntry SSE41CostTbl[] = { 2569 { ISD::ABS, MVT::v2i64, 2 }, // BLENDVPD(X,PSUBQ(0,X),X) 2570 { ISD::SMAX, MVT::v4i32, 1 }, 2571 { ISD::SMAX, MVT::v16i8, 1 }, 2572 { ISD::SMIN, MVT::v4i32, 1 }, 2573 { ISD::SMIN, MVT::v16i8, 1 }, 2574 { ISD::UMAX, MVT::v4i32, 1 }, 2575 { ISD::UMAX, MVT::v8i16, 1 }, 2576 { ISD::UMIN, MVT::v4i32, 1 }, 2577 { ISD::UMIN, MVT::v8i16, 1 }, 2578 }; 2579 static const CostTblEntry SSSE3CostTbl[] = { 2580 { ISD::ABS, MVT::v4i32, 1 }, 2581 { ISD::ABS, MVT::v8i16, 1 }, 2582 { ISD::ABS, MVT::v16i8, 1 }, 2583 { ISD::BITREVERSE, MVT::v2i64, 5 }, 2584 { ISD::BITREVERSE, MVT::v4i32, 5 }, 2585 { ISD::BITREVERSE, MVT::v8i16, 5 }, 2586 { ISD::BITREVERSE, MVT::v16i8, 5 }, 2587 { ISD::BSWAP, MVT::v2i64, 1 }, 2588 { ISD::BSWAP, MVT::v4i32, 1 }, 2589 { ISD::BSWAP, MVT::v8i16, 1 }, 2590 { ISD::CTLZ, MVT::v2i64, 23 }, 2591 { ISD::CTLZ, MVT::v4i32, 18 }, 2592 { ISD::CTLZ, MVT::v8i16, 14 }, 2593 { ISD::CTLZ, MVT::v16i8, 9 }, 2594 { ISD::CTPOP, MVT::v2i64, 7 }, 2595 { ISD::CTPOP, MVT::v4i32, 11 }, 2596 { ISD::CTPOP, MVT::v8i16, 9 }, 2597 { ISD::CTPOP, MVT::v16i8, 6 }, 2598 { ISD::CTTZ, MVT::v2i64, 10 }, 2599 { ISD::CTTZ, MVT::v4i32, 14 }, 2600 { ISD::CTTZ, MVT::v8i16, 12 }, 2601 { ISD::CTTZ, MVT::v16i8, 9 } 2602 }; 2603 static const CostTblEntry SSE2CostTbl[] = { 2604 { ISD::ABS, MVT::v2i64, 4 }, 2605 { ISD::ABS, MVT::v4i32, 3 }, 2606 { ISD::ABS, MVT::v8i16, 2 }, 2607 { ISD::ABS, MVT::v16i8, 2 }, 2608 { ISD::BITREVERSE, MVT::v2i64, 29 }, 2609 { ISD::BITREVERSE, MVT::v4i32, 27 }, 2610 { ISD::BITREVERSE, MVT::v8i16, 27 }, 2611 { ISD::BITREVERSE, MVT::v16i8, 20 }, 2612 { ISD::BSWAP, MVT::v2i64, 7 }, 2613 { ISD::BSWAP, MVT::v4i32, 7 }, 2614 { ISD::BSWAP, MVT::v8i16, 7 }, 2615 { ISD::CTLZ, MVT::v2i64, 25 }, 2616 { ISD::CTLZ, MVT::v4i32, 26 }, 2617 { ISD::CTLZ, MVT::v8i16, 20 }, 2618 { ISD::CTLZ, MVT::v16i8, 17 }, 2619 { ISD::CTPOP, MVT::v2i64, 12 }, 2620 { ISD::CTPOP, MVT::v4i32, 15 }, 2621 { ISD::CTPOP, MVT::v8i16, 13 }, 2622 { ISD::CTPOP, MVT::v16i8, 10 }, 2623 { ISD::CTTZ, MVT::v2i64, 14 }, 2624 { ISD::CTTZ, MVT::v4i32, 18 }, 2625 { ISD::CTTZ, MVT::v8i16, 16 }, 2626 { ISD::CTTZ, MVT::v16i8, 13 }, 2627 { ISD::SADDSAT, MVT::v8i16, 1 }, 2628 { ISD::SADDSAT, MVT::v16i8, 1 }, 2629 { ISD::SMAX, MVT::v8i16, 1 }, 2630 { ISD::SMIN, MVT::v8i16, 1 }, 2631 { ISD::SSUBSAT, MVT::v8i16, 1 }, 2632 { ISD::SSUBSAT, MVT::v16i8, 1 }, 2633 { ISD::UADDSAT, MVT::v8i16, 1 }, 2634 { ISD::UADDSAT, MVT::v16i8, 1 }, 2635 { ISD::UMAX, MVT::v8i16, 2 }, 2636 { ISD::UMAX, MVT::v16i8, 1 }, 2637 { ISD::UMIN, MVT::v8i16, 2 }, 2638 { ISD::UMIN, MVT::v16i8, 1 }, 2639 { ISD::USUBSAT, MVT::v8i16, 1 }, 2640 { ISD::USUBSAT, MVT::v16i8, 1 }, 2641 { ISD::FMAXNUM, MVT::f64, 4 }, 2642 { ISD::FMAXNUM, MVT::v2f64, 4 }, 2643 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 2644 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 2645 }; 2646 static const CostTblEntry SSE1CostTbl[] = { 2647 { ISD::FMAXNUM, MVT::f32, 4 }, 2648 { ISD::FMAXNUM, MVT::v4f32, 4 }, 2649 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 2650 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 2651 }; 2652 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 2653 { ISD::CTTZ, MVT::i64, 1 }, 2654 }; 2655 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 2656 { ISD::CTTZ, MVT::i32, 1 }, 2657 { ISD::CTTZ, MVT::i16, 1 }, 2658 { ISD::CTTZ, MVT::i8, 1 }, 2659 }; 2660 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 2661 { ISD::CTLZ, MVT::i64, 1 }, 2662 }; 2663 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 2664 { ISD::CTLZ, MVT::i32, 1 }, 2665 { ISD::CTLZ, MVT::i16, 1 }, 2666 { ISD::CTLZ, MVT::i8, 1 }, 2667 }; 2668 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 2669 { ISD::CTPOP, MVT::i64, 1 }, 2670 }; 2671 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 2672 { ISD::CTPOP, MVT::i32, 1 }, 2673 { ISD::CTPOP, MVT::i16, 1 }, 2674 { ISD::CTPOP, MVT::i8, 1 }, 2675 }; 2676 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2677 { ISD::ABS, MVT::i64, 2 }, // SUB+CMOV 2678 { ISD::BITREVERSE, MVT::i64, 14 }, 2679 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 2680 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 2681 { ISD::CTPOP, MVT::i64, 10 }, 2682 { ISD::SADDO, MVT::i64, 1 }, 2683 { ISD::UADDO, MVT::i64, 1 }, 2684 { ISD::UMULO, MVT::i64, 2 }, // mulq + seto 2685 }; 2686 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2687 { ISD::ABS, MVT::i32, 2 }, // SUB+CMOV 2688 { ISD::ABS, MVT::i16, 2 }, // SUB+CMOV 2689 { ISD::BITREVERSE, MVT::i32, 14 }, 2690 { ISD::BITREVERSE, MVT::i16, 14 }, 2691 { ISD::BITREVERSE, MVT::i8, 11 }, 2692 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 2693 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 2694 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 2695 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 2696 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 2697 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 2698 { ISD::CTPOP, MVT::i32, 8 }, 2699 { ISD::CTPOP, MVT::i16, 9 }, 2700 { ISD::CTPOP, MVT::i8, 7 }, 2701 { ISD::SADDO, MVT::i32, 1 }, 2702 { ISD::SADDO, MVT::i16, 1 }, 2703 { ISD::SADDO, MVT::i8, 1 }, 2704 { ISD::UADDO, MVT::i32, 1 }, 2705 { ISD::UADDO, MVT::i16, 1 }, 2706 { ISD::UADDO, MVT::i8, 1 }, 2707 { ISD::UMULO, MVT::i32, 2 }, // mul + seto 2708 { ISD::UMULO, MVT::i16, 2 }, 2709 { ISD::UMULO, MVT::i8, 2 }, 2710 }; 2711 2712 Type *RetTy = ICA.getReturnType(); 2713 Type *OpTy = RetTy; 2714 Intrinsic::ID IID = ICA.getID(); 2715 unsigned ISD = ISD::DELETED_NODE; 2716 switch (IID) { 2717 default: 2718 break; 2719 case Intrinsic::abs: 2720 ISD = ISD::ABS; 2721 break; 2722 case Intrinsic::bitreverse: 2723 ISD = ISD::BITREVERSE; 2724 break; 2725 case Intrinsic::bswap: 2726 ISD = ISD::BSWAP; 2727 break; 2728 case Intrinsic::ctlz: 2729 ISD = ISD::CTLZ; 2730 break; 2731 case Intrinsic::ctpop: 2732 ISD = ISD::CTPOP; 2733 break; 2734 case Intrinsic::cttz: 2735 ISD = ISD::CTTZ; 2736 break; 2737 case Intrinsic::maxnum: 2738 case Intrinsic::minnum: 2739 // FMINNUM has same costs so don't duplicate. 2740 ISD = ISD::FMAXNUM; 2741 break; 2742 case Intrinsic::sadd_sat: 2743 ISD = ISD::SADDSAT; 2744 break; 2745 case Intrinsic::smax: 2746 ISD = ISD::SMAX; 2747 break; 2748 case Intrinsic::smin: 2749 ISD = ISD::SMIN; 2750 break; 2751 case Intrinsic::ssub_sat: 2752 ISD = ISD::SSUBSAT; 2753 break; 2754 case Intrinsic::uadd_sat: 2755 ISD = ISD::UADDSAT; 2756 break; 2757 case Intrinsic::umax: 2758 ISD = ISD::UMAX; 2759 break; 2760 case Intrinsic::umin: 2761 ISD = ISD::UMIN; 2762 break; 2763 case Intrinsic::usub_sat: 2764 ISD = ISD::USUBSAT; 2765 break; 2766 case Intrinsic::sqrt: 2767 ISD = ISD::FSQRT; 2768 break; 2769 case Intrinsic::sadd_with_overflow: 2770 case Intrinsic::ssub_with_overflow: 2771 // SSUBO has same costs so don't duplicate. 2772 ISD = ISD::SADDO; 2773 OpTy = RetTy->getContainedType(0); 2774 break; 2775 case Intrinsic::uadd_with_overflow: 2776 case Intrinsic::usub_with_overflow: 2777 // USUBO has same costs so don't duplicate. 2778 ISD = ISD::UADDO; 2779 OpTy = RetTy->getContainedType(0); 2780 break; 2781 case Intrinsic::umul_with_overflow: 2782 case Intrinsic::smul_with_overflow: 2783 // SMULO has same costs so don't duplicate. 2784 ISD = ISD::UMULO; 2785 OpTy = RetTy->getContainedType(0); 2786 break; 2787 } 2788 2789 if (ISD != ISD::DELETED_NODE) { 2790 // Legalize the type. 2791 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 2792 MVT MTy = LT.second; 2793 2794 // Attempt to lookup cost. 2795 if (ISD == ISD::BITREVERSE && ST->hasGFNI() && ST->hasSSSE3() && 2796 MTy.isVector()) { 2797 // With PSHUFB the code is very similar for all types. If we have integer 2798 // byte operations, we just need a GF2P8AFFINEQB for vXi8. For other types 2799 // we also need a PSHUFB. 2800 unsigned Cost = MTy.getVectorElementType() == MVT::i8 ? 1 : 2; 2801 2802 // Without byte operations, we need twice as many GF2P8AFFINEQB and PSHUFB 2803 // instructions. We also need an extract and an insert. 2804 if (!(MTy.is128BitVector() || (ST->hasAVX2() && MTy.is256BitVector()) || 2805 (ST->hasBWI() && MTy.is512BitVector()))) 2806 Cost = Cost * 2 + 2; 2807 2808 return LT.first * Cost; 2809 } 2810 2811 auto adjustTableCost = [](const CostTblEntry &Entry, int LegalizationCost, 2812 FastMathFlags FMF) { 2813 // If there are no NANs to deal with, then these are reduced to a 2814 // single MIN** or MAX** instruction instead of the MIN/CMP/SELECT that we 2815 // assume is used in the non-fast case. 2816 if (Entry.ISD == ISD::FMAXNUM || Entry.ISD == ISD::FMINNUM) { 2817 if (FMF.noNaNs()) 2818 return LegalizationCost * 1; 2819 } 2820 return LegalizationCost * (int)Entry.Cost; 2821 }; 2822 2823 if (ST->useGLMDivSqrtCosts()) 2824 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 2825 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2826 2827 if (ST->isSLM()) 2828 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2829 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2830 2831 if (ST->hasCDI()) 2832 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 2833 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2834 2835 if (ST->hasBWI()) 2836 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2837 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2838 2839 if (ST->hasAVX512()) 2840 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2841 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2842 2843 if (ST->hasXOP()) 2844 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2845 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2846 2847 if (ST->hasAVX2()) 2848 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2849 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2850 2851 if (ST->hasAVX()) 2852 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2853 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2854 2855 if (ST->hasSSE42()) 2856 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2857 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2858 2859 if (ST->hasSSE41()) 2860 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2861 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2862 2863 if (ST->hasSSSE3()) 2864 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 2865 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2866 2867 if (ST->hasSSE2()) 2868 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2869 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2870 2871 if (ST->hasSSE1()) 2872 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2873 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2874 2875 if (ST->hasBMI()) { 2876 if (ST->is64Bit()) 2877 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 2878 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2879 2880 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 2881 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2882 } 2883 2884 if (ST->hasLZCNT()) { 2885 if (ST->is64Bit()) 2886 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 2887 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2888 2889 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 2890 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2891 } 2892 2893 if (ST->hasPOPCNT()) { 2894 if (ST->is64Bit()) 2895 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 2896 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2897 2898 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 2899 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2900 } 2901 2902 // TODO - add BMI (TZCNT) scalar handling 2903 2904 if (ST->is64Bit()) 2905 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2906 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2907 2908 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2909 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2910 } 2911 2912 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 2913 } 2914 2915 InstructionCost 2916 X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 2917 TTI::TargetCostKind CostKind) { 2918 if (ICA.isTypeBasedOnly()) 2919 return getTypeBasedIntrinsicInstrCost(ICA, CostKind); 2920 2921 static const CostTblEntry AVX512CostTbl[] = { 2922 { ISD::ROTL, MVT::v8i64, 1 }, 2923 { ISD::ROTL, MVT::v4i64, 1 }, 2924 { ISD::ROTL, MVT::v2i64, 1 }, 2925 { ISD::ROTL, MVT::v16i32, 1 }, 2926 { ISD::ROTL, MVT::v8i32, 1 }, 2927 { ISD::ROTL, MVT::v4i32, 1 }, 2928 { ISD::ROTR, MVT::v8i64, 1 }, 2929 { ISD::ROTR, MVT::v4i64, 1 }, 2930 { ISD::ROTR, MVT::v2i64, 1 }, 2931 { ISD::ROTR, MVT::v16i32, 1 }, 2932 { ISD::ROTR, MVT::v8i32, 1 }, 2933 { ISD::ROTR, MVT::v4i32, 1 } 2934 }; 2935 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 2936 static const CostTblEntry XOPCostTbl[] = { 2937 { ISD::ROTL, MVT::v4i64, 4 }, 2938 { ISD::ROTL, MVT::v8i32, 4 }, 2939 { ISD::ROTL, MVT::v16i16, 4 }, 2940 { ISD::ROTL, MVT::v32i8, 4 }, 2941 { ISD::ROTL, MVT::v2i64, 1 }, 2942 { ISD::ROTL, MVT::v4i32, 1 }, 2943 { ISD::ROTL, MVT::v8i16, 1 }, 2944 { ISD::ROTL, MVT::v16i8, 1 }, 2945 { ISD::ROTR, MVT::v4i64, 6 }, 2946 { ISD::ROTR, MVT::v8i32, 6 }, 2947 { ISD::ROTR, MVT::v16i16, 6 }, 2948 { ISD::ROTR, MVT::v32i8, 6 }, 2949 { ISD::ROTR, MVT::v2i64, 2 }, 2950 { ISD::ROTR, MVT::v4i32, 2 }, 2951 { ISD::ROTR, MVT::v8i16, 2 }, 2952 { ISD::ROTR, MVT::v16i8, 2 } 2953 }; 2954 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2955 { ISD::ROTL, MVT::i64, 1 }, 2956 { ISD::ROTR, MVT::i64, 1 }, 2957 { ISD::FSHL, MVT::i64, 4 } 2958 }; 2959 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2960 { ISD::ROTL, MVT::i32, 1 }, 2961 { ISD::ROTL, MVT::i16, 1 }, 2962 { ISD::ROTL, MVT::i8, 1 }, 2963 { ISD::ROTR, MVT::i32, 1 }, 2964 { ISD::ROTR, MVT::i16, 1 }, 2965 { ISD::ROTR, MVT::i8, 1 }, 2966 { ISD::FSHL, MVT::i32, 4 }, 2967 { ISD::FSHL, MVT::i16, 4 }, 2968 { ISD::FSHL, MVT::i8, 4 } 2969 }; 2970 2971 Intrinsic::ID IID = ICA.getID(); 2972 Type *RetTy = ICA.getReturnType(); 2973 const SmallVectorImpl<const Value *> &Args = ICA.getArgs(); 2974 unsigned ISD = ISD::DELETED_NODE; 2975 switch (IID) { 2976 default: 2977 break; 2978 case Intrinsic::fshl: 2979 ISD = ISD::FSHL; 2980 if (Args[0] == Args[1]) 2981 ISD = ISD::ROTL; 2982 break; 2983 case Intrinsic::fshr: 2984 // FSHR has same costs so don't duplicate. 2985 ISD = ISD::FSHL; 2986 if (Args[0] == Args[1]) 2987 ISD = ISD::ROTR; 2988 break; 2989 } 2990 2991 if (ISD != ISD::DELETED_NODE) { 2992 // Legalize the type. 2993 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 2994 MVT MTy = LT.second; 2995 2996 // Attempt to lookup cost. 2997 if (ST->hasAVX512()) 2998 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2999 return LT.first * Entry->Cost; 3000 3001 if (ST->hasXOP()) 3002 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3003 return LT.first * Entry->Cost; 3004 3005 if (ST->is64Bit()) 3006 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3007 return LT.first * Entry->Cost; 3008 3009 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3010 return LT.first * Entry->Cost; 3011 } 3012 3013 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3014 } 3015 3016 InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, 3017 unsigned Index) { 3018 static const CostTblEntry SLMCostTbl[] = { 3019 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 3020 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 3021 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 3022 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 3023 }; 3024 3025 assert(Val->isVectorTy() && "This must be a vector type"); 3026 Type *ScalarType = Val->getScalarType(); 3027 int RegisterFileMoveCost = 0; 3028 3029 if (Index != -1U && (Opcode == Instruction::ExtractElement || 3030 Opcode == Instruction::InsertElement)) { 3031 // Legalize the type. 3032 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 3033 3034 // This type is legalized to a scalar type. 3035 if (!LT.second.isVector()) 3036 return 0; 3037 3038 // The type may be split. Normalize the index to the new type. 3039 unsigned NumElts = LT.second.getVectorNumElements(); 3040 unsigned SubNumElts = NumElts; 3041 Index = Index % NumElts; 3042 3043 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 3044 // For inserts, we also need to insert the subvector back. 3045 if (LT.second.getSizeInBits() > 128) { 3046 assert((LT.second.getSizeInBits() % 128) == 0 && "Illegal vector"); 3047 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 3048 SubNumElts = NumElts / NumSubVecs; 3049 if (SubNumElts <= Index) { 3050 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 3051 Index %= SubNumElts; 3052 } 3053 } 3054 3055 if (Index == 0) { 3056 // Floating point scalars are already located in index #0. 3057 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 3058 // true for all. 3059 if (ScalarType->isFloatingPointTy()) 3060 return RegisterFileMoveCost; 3061 3062 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 3063 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 3064 return 1 + RegisterFileMoveCost; 3065 } 3066 3067 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3068 assert(ISD && "Unexpected vector opcode"); 3069 MVT MScalarTy = LT.second.getScalarType(); 3070 if (ST->isSLM()) 3071 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 3072 return Entry->Cost + RegisterFileMoveCost; 3073 3074 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 3075 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3076 (MScalarTy.isInteger() && ST->hasSSE41())) 3077 return 1 + RegisterFileMoveCost; 3078 3079 // Assume insertps is relatively cheap on all targets. 3080 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 3081 Opcode == Instruction::InsertElement) 3082 return 1 + RegisterFileMoveCost; 3083 3084 // For extractions we just need to shuffle the element to index 0, which 3085 // should be very cheap (assume cost = 1). For insertions we need to shuffle 3086 // the elements to its destination. In both cases we must handle the 3087 // subvector move(s). 3088 // If the vector type is already less than 128-bits then don't reduce it. 3089 // TODO: Under what circumstances should we shuffle using the full width? 3090 InstructionCost ShuffleCost = 1; 3091 if (Opcode == Instruction::InsertElement) { 3092 auto *SubTy = cast<VectorType>(Val); 3093 EVT VT = TLI->getValueType(DL, Val); 3094 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 3095 SubTy = FixedVectorType::get(ScalarType, SubNumElts); 3096 ShuffleCost = 3097 getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, None, 0, SubTy); 3098 } 3099 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 3100 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 3101 } 3102 3103 // Add to the base cost if we know that the extracted element of a vector is 3104 // destined to be moved to and used in the integer register file. 3105 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 3106 RegisterFileMoveCost += 1; 3107 3108 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 3109 } 3110 3111 unsigned X86TTIImpl::getScalarizationOverhead(VectorType *Ty, 3112 const APInt &DemandedElts, 3113 bool Insert, bool Extract) { 3114 unsigned Cost = 0; 3115 3116 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much 3117 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT. 3118 if (Insert) { 3119 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3120 MVT MScalarTy = LT.second.getScalarType(); 3121 3122 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3123 (MScalarTy.isInteger() && ST->hasSSE41()) || 3124 (MScalarTy == MVT::f32 && ST->hasSSE41())) { 3125 // For types we can insert directly, insertion into 128-bit sub vectors is 3126 // cheap, followed by a cheap chain of concatenations. 3127 if (LT.second.getSizeInBits() <= 128) { 3128 Cost += 3129 BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, false); 3130 } else { 3131 // In each 128-lane, if at least one index is demanded but not all 3132 // indices are demanded and this 128-lane is not the first 128-lane of 3133 // the legalized-vector, then this 128-lane needs a extracti128; If in 3134 // each 128-lane, there is at least one demanded index, this 128-lane 3135 // needs a inserti128. 3136 3137 // The following cases will help you build a better understanding: 3138 // Assume we insert several elements into a v8i32 vector in avx2, 3139 // Case#1: inserting into 1th index needs vpinsrd + inserti128. 3140 // Case#2: inserting into 5th index needs extracti128 + vpinsrd + 3141 // inserti128. 3142 // Case#3: inserting into 4,5,6,7 index needs 4*vpinsrd + inserti128. 3143 unsigned Num128Lanes = LT.second.getSizeInBits() / 128 * LT.first; 3144 unsigned NumElts = LT.second.getVectorNumElements() * LT.first; 3145 APInt WidenedDemandedElts = DemandedElts.zextOrSelf(NumElts); 3146 unsigned Scale = NumElts / Num128Lanes; 3147 // We iterate each 128-lane, and check if we need a 3148 // extracti128/inserti128 for this 128-lane. 3149 for (unsigned I = 0; I < NumElts; I += Scale) { 3150 APInt Mask = WidenedDemandedElts.getBitsSet(NumElts, I, I + Scale); 3151 APInt MaskedDE = Mask & WidenedDemandedElts; 3152 unsigned Population = MaskedDE.countPopulation(); 3153 Cost += (Population > 0 && Population != Scale && 3154 I % LT.second.getVectorNumElements() != 0); 3155 Cost += Population > 0; 3156 } 3157 Cost += DemandedElts.countPopulation(); 3158 3159 // For vXf32 cases, insertion into the 0'th index in each v4f32 3160 // 128-bit vector is free. 3161 // NOTE: This assumes legalization widens vXf32 vectors. 3162 if (MScalarTy == MVT::f32) 3163 for (unsigned i = 0, e = cast<FixedVectorType>(Ty)->getNumElements(); 3164 i < e; i += 4) 3165 if (DemandedElts[i]) 3166 Cost--; 3167 } 3168 } else if (LT.second.isVector()) { 3169 // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded 3170 // integer element as a SCALAR_TO_VECTOR, then we build the vector as a 3171 // series of UNPCK followed by CONCAT_VECTORS - all of these can be 3172 // considered cheap. 3173 if (Ty->isIntOrIntVectorTy()) 3174 Cost += DemandedElts.countPopulation(); 3175 3176 // Get the smaller of the legalized or original pow2-extended number of 3177 // vector elements, which represents the number of unpacks we'll end up 3178 // performing. 3179 unsigned NumElts = LT.second.getVectorNumElements(); 3180 unsigned Pow2Elts = 3181 PowerOf2Ceil(cast<FixedVectorType>(Ty)->getNumElements()); 3182 Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first; 3183 } 3184 } 3185 3186 // TODO: Use default extraction for now, but we should investigate extending this 3187 // to handle repeated subvector extraction. 3188 if (Extract) 3189 Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, false, Extract); 3190 3191 return Cost; 3192 } 3193 3194 InstructionCost X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 3195 MaybeAlign Alignment, 3196 unsigned AddressSpace, 3197 TTI::TargetCostKind CostKind, 3198 const Instruction *I) { 3199 // TODO: Handle other cost kinds. 3200 if (CostKind != TTI::TCK_RecipThroughput) { 3201 if (auto *SI = dyn_cast_or_null<StoreInst>(I)) { 3202 // Store instruction with index and scale costs 2 Uops. 3203 // Check the preceding GEP to identify non-const indices. 3204 if (auto *GEP = dyn_cast<GetElementPtrInst>(SI->getPointerOperand())) { 3205 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3206 return TTI::TCC_Basic * 2; 3207 } 3208 } 3209 return TTI::TCC_Basic; 3210 } 3211 3212 // Handle non-power-of-two vectors such as <3 x float> 3213 if (auto *VTy = dyn_cast<FixedVectorType>(Src)) { 3214 unsigned NumElem = VTy->getNumElements(); 3215 3216 // Handle a few common cases: 3217 // <3 x float> 3218 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 3219 // Cost = 64 bit store + extract + 32 bit store. 3220 return 3; 3221 3222 // <3 x double> 3223 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 3224 // Cost = 128 bit store + unpack + 64 bit store. 3225 return 3; 3226 3227 // Assume that all other non-power-of-two numbers are scalarized. 3228 if (!isPowerOf2_32(NumElem)) { 3229 APInt DemandedElts = APInt::getAllOnesValue(NumElem); 3230 InstructionCost Cost = BaseT::getMemoryOpCost( 3231 Opcode, VTy->getScalarType(), Alignment, AddressSpace, CostKind); 3232 int SplitCost = getScalarizationOverhead(VTy, DemandedElts, 3233 Opcode == Instruction::Load, 3234 Opcode == Instruction::Store); 3235 return NumElem * Cost + SplitCost; 3236 } 3237 } 3238 3239 // Type legalization can't handle structs 3240 if (TLI->getValueType(DL, Src, true) == MVT::Other) 3241 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3242 CostKind); 3243 3244 // Legalize the type. 3245 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 3246 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 3247 "Invalid Opcode"); 3248 3249 // Each load/store unit costs 1. 3250 int Cost = LT.first * 1; 3251 3252 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a 3253 // proxy for a double-pumped AVX memory interface such as on Sandybridge. 3254 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow()) 3255 Cost *= 2; 3256 3257 return Cost; 3258 } 3259 3260 InstructionCost 3261 X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, Align Alignment, 3262 unsigned AddressSpace, 3263 TTI::TargetCostKind CostKind) { 3264 bool IsLoad = (Instruction::Load == Opcode); 3265 bool IsStore = (Instruction::Store == Opcode); 3266 3267 auto *SrcVTy = dyn_cast<FixedVectorType>(SrcTy); 3268 if (!SrcVTy) 3269 // To calculate scalar take the regular cost, without mask 3270 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace, CostKind); 3271 3272 unsigned NumElem = SrcVTy->getNumElements(); 3273 auto *MaskTy = 3274 FixedVectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 3275 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, Alignment)) || 3276 (IsStore && !isLegalMaskedStore(SrcVTy, Alignment)) || 3277 !isPowerOf2_32(NumElem)) { 3278 // Scalarization 3279 APInt DemandedElts = APInt::getAllOnesValue(NumElem); 3280 InstructionCost MaskSplitCost = 3281 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 3282 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 3283 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr, 3284 CmpInst::BAD_ICMP_PREDICATE, CostKind); 3285 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 3286 InstructionCost MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 3287 InstructionCost ValueSplitCost = 3288 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore); 3289 InstructionCost MemopCost = 3290 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3291 Alignment, AddressSpace, CostKind); 3292 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 3293 } 3294 3295 // Legalize the type. 3296 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3297 auto VT = TLI->getValueType(DL, SrcVTy); 3298 InstructionCost Cost = 0; 3299 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 3300 LT.second.getVectorNumElements() == NumElem) 3301 // Promotion requires expand/truncate for data and a shuffle for mask. 3302 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, None, 0, nullptr) + 3303 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, None, 0, nullptr); 3304 3305 else if (LT.second.getVectorNumElements() > NumElem) { 3306 auto *NewMaskTy = FixedVectorType::get(MaskTy->getElementType(), 3307 LT.second.getVectorNumElements()); 3308 // Expanding requires fill mask with zeroes 3309 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, None, 0, MaskTy); 3310 } 3311 3312 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 3313 if (!ST->hasAVX512()) 3314 return Cost + LT.first * (IsLoad ? 2 : 8); 3315 3316 // AVX-512 masked load/store is cheapper 3317 return Cost + LT.first; 3318 } 3319 3320 int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE, 3321 const SCEV *Ptr) { 3322 // Address computations in vectorized code with non-consecutive addresses will 3323 // likely result in more instructions compared to scalar code where the 3324 // computation can more often be merged into the index mode. The resulting 3325 // extra micro-ops can significantly decrease throughput. 3326 const unsigned NumVectorInstToHideOverhead = 10; 3327 3328 // Cost modeling of Strided Access Computation is hidden by the indexing 3329 // modes of X86 regardless of the stride value. We dont believe that there 3330 // is a difference between constant strided access in gerenal and constant 3331 // strided value which is less than or equal to 64. 3332 // Even in the case of (loop invariant) stride whose value is not known at 3333 // compile time, the address computation will not incur more than one extra 3334 // ADD instruction. 3335 if (Ty->isVectorTy() && SE) { 3336 if (!BaseT::isStridedAccess(Ptr)) 3337 return NumVectorInstToHideOverhead; 3338 if (!BaseT::getConstantStrideStep(SE, Ptr)) 3339 return 1; 3340 } 3341 3342 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 3343 } 3344 3345 InstructionCost 3346 X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 3347 bool IsPairwise, 3348 TTI::TargetCostKind CostKind) { 3349 // Just use the default implementation for pair reductions. 3350 if (IsPairwise) 3351 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise, CostKind); 3352 3353 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3354 // and make it as the cost. 3355 3356 static const CostTblEntry SLMCostTblNoPairWise[] = { 3357 { ISD::FADD, MVT::v2f64, 3 }, 3358 { ISD::ADD, MVT::v2i64, 5 }, 3359 }; 3360 3361 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3362 { ISD::FADD, MVT::v2f64, 2 }, 3363 { ISD::FADD, MVT::v4f32, 4 }, 3364 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 3365 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 3366 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 3367 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 3368 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 3369 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 3370 { ISD::ADD, MVT::v2i8, 2 }, 3371 { ISD::ADD, MVT::v4i8, 2 }, 3372 { ISD::ADD, MVT::v8i8, 2 }, 3373 { ISD::ADD, MVT::v16i8, 3 }, 3374 }; 3375 3376 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3377 { ISD::FADD, MVT::v4f64, 3 }, 3378 { ISD::FADD, MVT::v4f32, 3 }, 3379 { ISD::FADD, MVT::v8f32, 4 }, 3380 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 3381 { ISD::ADD, MVT::v4i64, 3 }, 3382 { ISD::ADD, MVT::v8i32, 5 }, 3383 { ISD::ADD, MVT::v16i16, 5 }, 3384 { ISD::ADD, MVT::v32i8, 4 }, 3385 }; 3386 3387 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3388 assert(ISD && "Invalid opcode"); 3389 3390 // Before legalizing the type, give a chance to look up illegal narrow types 3391 // in the table. 3392 // FIXME: Is there a better way to do this? 3393 EVT VT = TLI->getValueType(DL, ValTy); 3394 if (VT.isSimple()) { 3395 MVT MTy = VT.getSimpleVT(); 3396 if (ST->isSLM()) 3397 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3398 return Entry->Cost; 3399 3400 if (ST->hasAVX()) 3401 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3402 return Entry->Cost; 3403 3404 if (ST->hasSSE2()) 3405 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3406 return Entry->Cost; 3407 } 3408 3409 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3410 3411 MVT MTy = LT.second; 3412 3413 auto *ValVTy = cast<FixedVectorType>(ValTy); 3414 3415 // Special case: vXi8 mul reductions are performed as vXi16. 3416 if (ISD == ISD::MUL && MTy.getScalarType() == MVT::i8) { 3417 auto *WideSclTy = IntegerType::get(ValVTy->getContext(), 16); 3418 auto *WideVecTy = FixedVectorType::get(WideSclTy, ValVTy->getNumElements()); 3419 return getCastInstrCost(Instruction::ZExt, WideVecTy, ValTy, 3420 TargetTransformInfo::CastContextHint::None, 3421 CostKind) + 3422 getArithmeticReductionCost(Opcode, WideVecTy, IsPairwise, CostKind); 3423 } 3424 3425 InstructionCost ArithmeticCost = 0; 3426 if (LT.first != 1 && MTy.isVector() && 3427 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3428 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3429 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3430 MTy.getVectorNumElements()); 3431 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3432 ArithmeticCost *= LT.first - 1; 3433 } 3434 3435 if (ST->isSLM()) 3436 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3437 return ArithmeticCost + Entry->Cost; 3438 3439 if (ST->hasAVX()) 3440 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3441 return ArithmeticCost + Entry->Cost; 3442 3443 if (ST->hasSSE2()) 3444 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3445 return ArithmeticCost + Entry->Cost; 3446 3447 // FIXME: These assume a naive kshift+binop lowering, which is probably 3448 // conservative in most cases. 3449 static const CostTblEntry AVX512BoolReduction[] = { 3450 { ISD::AND, MVT::v2i1, 3 }, 3451 { ISD::AND, MVT::v4i1, 5 }, 3452 { ISD::AND, MVT::v8i1, 7 }, 3453 { ISD::AND, MVT::v16i1, 9 }, 3454 { ISD::AND, MVT::v32i1, 11 }, 3455 { ISD::AND, MVT::v64i1, 13 }, 3456 { ISD::OR, MVT::v2i1, 3 }, 3457 { ISD::OR, MVT::v4i1, 5 }, 3458 { ISD::OR, MVT::v8i1, 7 }, 3459 { ISD::OR, MVT::v16i1, 9 }, 3460 { ISD::OR, MVT::v32i1, 11 }, 3461 { ISD::OR, MVT::v64i1, 13 }, 3462 }; 3463 3464 static const CostTblEntry AVX2BoolReduction[] = { 3465 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 3466 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 3467 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 3468 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 3469 }; 3470 3471 static const CostTblEntry AVX1BoolReduction[] = { 3472 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 3473 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 3474 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3475 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3476 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 3477 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 3478 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3479 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3480 }; 3481 3482 static const CostTblEntry SSE2BoolReduction[] = { 3483 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 3484 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 3485 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 3486 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 3487 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 3488 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 3489 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 3490 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 3491 }; 3492 3493 // Handle bool allof/anyof patterns. 3494 if (ValVTy->getElementType()->isIntegerTy(1)) { 3495 InstructionCost ArithmeticCost = 0; 3496 if (LT.first != 1 && MTy.isVector() && 3497 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3498 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3499 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3500 MTy.getVectorNumElements()); 3501 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3502 ArithmeticCost *= LT.first - 1; 3503 } 3504 3505 if (ST->hasAVX512()) 3506 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 3507 return ArithmeticCost + Entry->Cost; 3508 if (ST->hasAVX2()) 3509 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 3510 return ArithmeticCost + Entry->Cost; 3511 if (ST->hasAVX()) 3512 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 3513 return ArithmeticCost + Entry->Cost; 3514 if (ST->hasSSE2()) 3515 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 3516 return ArithmeticCost + Entry->Cost; 3517 3518 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise, 3519 CostKind); 3520 } 3521 3522 unsigned NumVecElts = ValVTy->getNumElements(); 3523 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 3524 3525 // Special case power of 2 reductions where the scalar type isn't changed 3526 // by type legalization. 3527 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 3528 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise, 3529 CostKind); 3530 3531 InstructionCost ReductionCost = 0; 3532 3533 auto *Ty = ValVTy; 3534 if (LT.first != 1 && MTy.isVector() && 3535 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3536 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3537 Ty = FixedVectorType::get(ValVTy->getElementType(), 3538 MTy.getVectorNumElements()); 3539 ReductionCost = getArithmeticInstrCost(Opcode, Ty, CostKind); 3540 ReductionCost *= LT.first - 1; 3541 NumVecElts = MTy.getVectorNumElements(); 3542 } 3543 3544 // Now handle reduction with the legal type, taking into account size changes 3545 // at each level. 3546 while (NumVecElts > 1) { 3547 // Determine the size of the remaining vector we need to reduce. 3548 unsigned Size = NumVecElts * ScalarSize; 3549 NumVecElts /= 2; 3550 // If we're reducing from 256/512 bits, use an extract_subvector. 3551 if (Size > 128) { 3552 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 3553 ReductionCost += 3554 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 3555 Ty = SubTy; 3556 } else if (Size == 128) { 3557 // Reducing from 128 bits is a permute of v2f64/v2i64. 3558 FixedVectorType *ShufTy; 3559 if (ValVTy->isFloatingPointTy()) 3560 ShufTy = 3561 FixedVectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 3562 else 3563 ShufTy = 3564 FixedVectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 3565 ReductionCost += 3566 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3567 } else if (Size == 64) { 3568 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3569 FixedVectorType *ShufTy; 3570 if (ValVTy->isFloatingPointTy()) 3571 ShufTy = 3572 FixedVectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 3573 else 3574 ShufTy = 3575 FixedVectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 3576 ReductionCost += 3577 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3578 } else { 3579 // Reducing from smaller size is a shift by immediate. 3580 auto *ShiftTy = FixedVectorType::get( 3581 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 3582 ReductionCost += getArithmeticInstrCost( 3583 Instruction::LShr, ShiftTy, CostKind, 3584 TargetTransformInfo::OK_AnyValue, 3585 TargetTransformInfo::OK_UniformConstantValue, 3586 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3587 } 3588 3589 // Add the arithmetic op for this level. 3590 ReductionCost += getArithmeticInstrCost(Opcode, Ty, CostKind); 3591 } 3592 3593 // Add the final extract element to the cost. 3594 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3595 } 3596 3597 InstructionCost X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, 3598 bool IsUnsigned) { 3599 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3600 3601 MVT MTy = LT.second; 3602 3603 int ISD; 3604 if (Ty->isIntOrIntVectorTy()) { 3605 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3606 } else { 3607 assert(Ty->isFPOrFPVectorTy() && 3608 "Expected float point or integer vector type."); 3609 ISD = ISD::FMINNUM; 3610 } 3611 3612 static const CostTblEntry SSE1CostTbl[] = { 3613 {ISD::FMINNUM, MVT::v4f32, 1}, 3614 }; 3615 3616 static const CostTblEntry SSE2CostTbl[] = { 3617 {ISD::FMINNUM, MVT::v2f64, 1}, 3618 {ISD::SMIN, MVT::v8i16, 1}, 3619 {ISD::UMIN, MVT::v16i8, 1}, 3620 }; 3621 3622 static const CostTblEntry SSE41CostTbl[] = { 3623 {ISD::SMIN, MVT::v4i32, 1}, 3624 {ISD::UMIN, MVT::v4i32, 1}, 3625 {ISD::UMIN, MVT::v8i16, 1}, 3626 {ISD::SMIN, MVT::v16i8, 1}, 3627 }; 3628 3629 static const CostTblEntry SSE42CostTbl[] = { 3630 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 3631 }; 3632 3633 static const CostTblEntry AVX1CostTbl[] = { 3634 {ISD::FMINNUM, MVT::v8f32, 1}, 3635 {ISD::FMINNUM, MVT::v4f64, 1}, 3636 {ISD::SMIN, MVT::v8i32, 3}, 3637 {ISD::UMIN, MVT::v8i32, 3}, 3638 {ISD::SMIN, MVT::v16i16, 3}, 3639 {ISD::UMIN, MVT::v16i16, 3}, 3640 {ISD::SMIN, MVT::v32i8, 3}, 3641 {ISD::UMIN, MVT::v32i8, 3}, 3642 }; 3643 3644 static const CostTblEntry AVX2CostTbl[] = { 3645 {ISD::SMIN, MVT::v8i32, 1}, 3646 {ISD::UMIN, MVT::v8i32, 1}, 3647 {ISD::SMIN, MVT::v16i16, 1}, 3648 {ISD::UMIN, MVT::v16i16, 1}, 3649 {ISD::SMIN, MVT::v32i8, 1}, 3650 {ISD::UMIN, MVT::v32i8, 1}, 3651 }; 3652 3653 static const CostTblEntry AVX512CostTbl[] = { 3654 {ISD::FMINNUM, MVT::v16f32, 1}, 3655 {ISD::FMINNUM, MVT::v8f64, 1}, 3656 {ISD::SMIN, MVT::v2i64, 1}, 3657 {ISD::UMIN, MVT::v2i64, 1}, 3658 {ISD::SMIN, MVT::v4i64, 1}, 3659 {ISD::UMIN, MVT::v4i64, 1}, 3660 {ISD::SMIN, MVT::v8i64, 1}, 3661 {ISD::UMIN, MVT::v8i64, 1}, 3662 {ISD::SMIN, MVT::v16i32, 1}, 3663 {ISD::UMIN, MVT::v16i32, 1}, 3664 }; 3665 3666 static const CostTblEntry AVX512BWCostTbl[] = { 3667 {ISD::SMIN, MVT::v32i16, 1}, 3668 {ISD::UMIN, MVT::v32i16, 1}, 3669 {ISD::SMIN, MVT::v64i8, 1}, 3670 {ISD::UMIN, MVT::v64i8, 1}, 3671 }; 3672 3673 // If we have a native MIN/MAX instruction for this type, use it. 3674 if (ST->hasBWI()) 3675 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3676 return LT.first * Entry->Cost; 3677 3678 if (ST->hasAVX512()) 3679 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3680 return LT.first * Entry->Cost; 3681 3682 if (ST->hasAVX2()) 3683 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3684 return LT.first * Entry->Cost; 3685 3686 if (ST->hasAVX()) 3687 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3688 return LT.first * Entry->Cost; 3689 3690 if (ST->hasSSE42()) 3691 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3692 return LT.first * Entry->Cost; 3693 3694 if (ST->hasSSE41()) 3695 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3696 return LT.first * Entry->Cost; 3697 3698 if (ST->hasSSE2()) 3699 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3700 return LT.first * Entry->Cost; 3701 3702 if (ST->hasSSE1()) 3703 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3704 return LT.first * Entry->Cost; 3705 3706 unsigned CmpOpcode; 3707 if (Ty->isFPOrFPVectorTy()) { 3708 CmpOpcode = Instruction::FCmp; 3709 } else { 3710 assert(Ty->isIntOrIntVectorTy() && 3711 "expecting floating point or integer type for min/max reduction"); 3712 CmpOpcode = Instruction::ICmp; 3713 } 3714 3715 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 3716 // Otherwise fall back to cmp+select. 3717 InstructionCost Result = 3718 getCmpSelInstrCost(CmpOpcode, Ty, CondTy, CmpInst::BAD_ICMP_PREDICATE, 3719 CostKind) + 3720 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, 3721 CmpInst::BAD_ICMP_PREDICATE, CostKind); 3722 return Result; 3723 } 3724 3725 InstructionCost 3726 X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 3727 bool IsPairwise, bool IsUnsigned, 3728 TTI::TargetCostKind CostKind) { 3729 // Just use the default implementation for pair reductions. 3730 if (IsPairwise) 3731 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned, 3732 CostKind); 3733 3734 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3735 3736 MVT MTy = LT.second; 3737 3738 int ISD; 3739 if (ValTy->isIntOrIntVectorTy()) { 3740 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3741 } else { 3742 assert(ValTy->isFPOrFPVectorTy() && 3743 "Expected float point or integer vector type."); 3744 ISD = ISD::FMINNUM; 3745 } 3746 3747 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3748 // and make it as the cost. 3749 3750 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3751 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 3752 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 3753 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 3754 }; 3755 3756 static const CostTblEntry SSE41CostTblNoPairWise[] = { 3757 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 3758 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 3759 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 3760 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 3761 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 3762 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 3763 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 3764 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 3765 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 3766 {ISD::SMIN, MVT::v16i8, 6}, 3767 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 3768 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 3769 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 3770 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 3771 }; 3772 3773 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3774 {ISD::SMIN, MVT::v16i16, 6}, 3775 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 3776 {ISD::SMIN, MVT::v32i8, 8}, 3777 {ISD::UMIN, MVT::v32i8, 8}, 3778 }; 3779 3780 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 3781 {ISD::SMIN, MVT::v32i16, 8}, 3782 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 3783 {ISD::SMIN, MVT::v64i8, 10}, 3784 {ISD::UMIN, MVT::v64i8, 10}, 3785 }; 3786 3787 // Before legalizing the type, give a chance to look up illegal narrow types 3788 // in the table. 3789 // FIXME: Is there a better way to do this? 3790 EVT VT = TLI->getValueType(DL, ValTy); 3791 if (VT.isSimple()) { 3792 MVT MTy = VT.getSimpleVT(); 3793 if (ST->hasBWI()) 3794 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3795 return Entry->Cost; 3796 3797 if (ST->hasAVX()) 3798 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3799 return Entry->Cost; 3800 3801 if (ST->hasSSE41()) 3802 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3803 return Entry->Cost; 3804 3805 if (ST->hasSSE2()) 3806 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3807 return Entry->Cost; 3808 } 3809 3810 auto *ValVTy = cast<FixedVectorType>(ValTy); 3811 unsigned NumVecElts = ValVTy->getNumElements(); 3812 3813 auto *Ty = ValVTy; 3814 InstructionCost MinMaxCost = 0; 3815 if (LT.first != 1 && MTy.isVector() && 3816 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3817 // Type needs to be split. We need LT.first - 1 operations ops. 3818 Ty = FixedVectorType::get(ValVTy->getElementType(), 3819 MTy.getVectorNumElements()); 3820 auto *SubCondTy = FixedVectorType::get(CondTy->getElementType(), 3821 MTy.getVectorNumElements()); 3822 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3823 MinMaxCost *= LT.first - 1; 3824 NumVecElts = MTy.getVectorNumElements(); 3825 } 3826 3827 if (ST->hasBWI()) 3828 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3829 return MinMaxCost + Entry->Cost; 3830 3831 if (ST->hasAVX()) 3832 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3833 return MinMaxCost + Entry->Cost; 3834 3835 if (ST->hasSSE41()) 3836 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3837 return MinMaxCost + Entry->Cost; 3838 3839 if (ST->hasSSE2()) 3840 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3841 return MinMaxCost + Entry->Cost; 3842 3843 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 3844 3845 // Special case power of 2 reductions where the scalar type isn't changed 3846 // by type legalization. 3847 if (!isPowerOf2_32(ValVTy->getNumElements()) || 3848 ScalarSize != MTy.getScalarSizeInBits()) 3849 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned, 3850 CostKind); 3851 3852 // Now handle reduction with the legal type, taking into account size changes 3853 // at each level. 3854 while (NumVecElts > 1) { 3855 // Determine the size of the remaining vector we need to reduce. 3856 unsigned Size = NumVecElts * ScalarSize; 3857 NumVecElts /= 2; 3858 // If we're reducing from 256/512 bits, use an extract_subvector. 3859 if (Size > 128) { 3860 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 3861 MinMaxCost += 3862 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 3863 Ty = SubTy; 3864 } else if (Size == 128) { 3865 // Reducing from 128 bits is a permute of v2f64/v2i64. 3866 VectorType *ShufTy; 3867 if (ValTy->isFloatingPointTy()) 3868 ShufTy = 3869 FixedVectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 3870 else 3871 ShufTy = FixedVectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 3872 MinMaxCost += 3873 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3874 } else if (Size == 64) { 3875 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3876 FixedVectorType *ShufTy; 3877 if (ValTy->isFloatingPointTy()) 3878 ShufTy = FixedVectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 3879 else 3880 ShufTy = FixedVectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 3881 MinMaxCost += 3882 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3883 } else { 3884 // Reducing from smaller size is a shift by immediate. 3885 auto *ShiftTy = FixedVectorType::get( 3886 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 3887 MinMaxCost += getArithmeticInstrCost( 3888 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, 3889 TargetTransformInfo::OK_AnyValue, 3890 TargetTransformInfo::OK_UniformConstantValue, 3891 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3892 } 3893 3894 // Add the arithmetic op for this level. 3895 auto *SubCondTy = 3896 FixedVectorType::get(CondTy->getElementType(), Ty->getNumElements()); 3897 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3898 } 3899 3900 // Add the final extract element to the cost. 3901 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3902 } 3903 3904 /// Calculate the cost of materializing a 64-bit value. This helper 3905 /// method might only calculate a fraction of a larger immediate. Therefore it 3906 /// is valid to return a cost of ZERO. 3907 int X86TTIImpl::getIntImmCost(int64_t Val) { 3908 if (Val == 0) 3909 return TTI::TCC_Free; 3910 3911 if (isInt<32>(Val)) 3912 return TTI::TCC_Basic; 3913 3914 return 2 * TTI::TCC_Basic; 3915 } 3916 3917 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 3918 TTI::TargetCostKind CostKind) { 3919 assert(Ty->isIntegerTy()); 3920 3921 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3922 if (BitSize == 0) 3923 return ~0U; 3924 3925 // Never hoist constants larger than 128bit, because this might lead to 3926 // incorrect code generation or assertions in codegen. 3927 // Fixme: Create a cost model for types larger than i128 once the codegen 3928 // issues have been fixed. 3929 if (BitSize > 128) 3930 return TTI::TCC_Free; 3931 3932 if (Imm == 0) 3933 return TTI::TCC_Free; 3934 3935 // Sign-extend all constants to a multiple of 64-bit. 3936 APInt ImmVal = Imm; 3937 if (BitSize % 64 != 0) 3938 ImmVal = Imm.sext(alignTo(BitSize, 64)); 3939 3940 // Split the constant into 64-bit chunks and calculate the cost for each 3941 // chunk. 3942 int Cost = 0; 3943 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 3944 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 3945 int64_t Val = Tmp.getSExtValue(); 3946 Cost += getIntImmCost(Val); 3947 } 3948 // We need at least one instruction to materialize the constant. 3949 return std::max(1, Cost); 3950 } 3951 3952 int X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, 3953 const APInt &Imm, Type *Ty, 3954 TTI::TargetCostKind CostKind, 3955 Instruction *Inst) { 3956 assert(Ty->isIntegerTy()); 3957 3958 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3959 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3960 // here, so that constant hoisting will ignore this constant. 3961 if (BitSize == 0) 3962 return TTI::TCC_Free; 3963 3964 unsigned ImmIdx = ~0U; 3965 switch (Opcode) { 3966 default: 3967 return TTI::TCC_Free; 3968 case Instruction::GetElementPtr: 3969 // Always hoist the base address of a GetElementPtr. This prevents the 3970 // creation of new constants for every base constant that gets constant 3971 // folded with the offset. 3972 if (Idx == 0) 3973 return 2 * TTI::TCC_Basic; 3974 return TTI::TCC_Free; 3975 case Instruction::Store: 3976 ImmIdx = 0; 3977 break; 3978 case Instruction::ICmp: 3979 // This is an imperfect hack to prevent constant hoisting of 3980 // compares that might be trying to check if a 64-bit value fits in 3981 // 32-bits. The backend can optimize these cases using a right shift by 32. 3982 // Ideally we would check the compare predicate here. There also other 3983 // similar immediates the backend can use shifts for. 3984 if (Idx == 1 && Imm.getBitWidth() == 64) { 3985 uint64_t ImmVal = Imm.getZExtValue(); 3986 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 3987 return TTI::TCC_Free; 3988 } 3989 ImmIdx = 1; 3990 break; 3991 case Instruction::And: 3992 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 3993 // by using a 32-bit operation with implicit zero extension. Detect such 3994 // immediates here as the normal path expects bit 31 to be sign extended. 3995 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 3996 return TTI::TCC_Free; 3997 ImmIdx = 1; 3998 break; 3999 case Instruction::Add: 4000 case Instruction::Sub: 4001 // For add/sub, we can use the opposite instruction for INT32_MIN. 4002 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 4003 return TTI::TCC_Free; 4004 ImmIdx = 1; 4005 break; 4006 case Instruction::UDiv: 4007 case Instruction::SDiv: 4008 case Instruction::URem: 4009 case Instruction::SRem: 4010 // Division by constant is typically expanded later into a different 4011 // instruction sequence. This completely changes the constants. 4012 // Report them as "free" to stop ConstantHoist from marking them as opaque. 4013 return TTI::TCC_Free; 4014 case Instruction::Mul: 4015 case Instruction::Or: 4016 case Instruction::Xor: 4017 ImmIdx = 1; 4018 break; 4019 // Always return TCC_Free for the shift value of a shift instruction. 4020 case Instruction::Shl: 4021 case Instruction::LShr: 4022 case Instruction::AShr: 4023 if (Idx == 1) 4024 return TTI::TCC_Free; 4025 break; 4026 case Instruction::Trunc: 4027 case Instruction::ZExt: 4028 case Instruction::SExt: 4029 case Instruction::IntToPtr: 4030 case Instruction::PtrToInt: 4031 case Instruction::BitCast: 4032 case Instruction::PHI: 4033 case Instruction::Call: 4034 case Instruction::Select: 4035 case Instruction::Ret: 4036 case Instruction::Load: 4037 break; 4038 } 4039 4040 if (Idx == ImmIdx) { 4041 int NumConstants = divideCeil(BitSize, 64); 4042 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4043 return (Cost <= NumConstants * TTI::TCC_Basic) 4044 ? static_cast<int>(TTI::TCC_Free) 4045 : Cost; 4046 } 4047 4048 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4049 } 4050 4051 int X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 4052 const APInt &Imm, Type *Ty, 4053 TTI::TargetCostKind CostKind) { 4054 assert(Ty->isIntegerTy()); 4055 4056 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4057 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4058 // here, so that constant hoisting will ignore this constant. 4059 if (BitSize == 0) 4060 return TTI::TCC_Free; 4061 4062 switch (IID) { 4063 default: 4064 return TTI::TCC_Free; 4065 case Intrinsic::sadd_with_overflow: 4066 case Intrinsic::uadd_with_overflow: 4067 case Intrinsic::ssub_with_overflow: 4068 case Intrinsic::usub_with_overflow: 4069 case Intrinsic::smul_with_overflow: 4070 case Intrinsic::umul_with_overflow: 4071 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 4072 return TTI::TCC_Free; 4073 break; 4074 case Intrinsic::experimental_stackmap: 4075 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4076 return TTI::TCC_Free; 4077 break; 4078 case Intrinsic::experimental_patchpoint_void: 4079 case Intrinsic::experimental_patchpoint_i64: 4080 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4081 return TTI::TCC_Free; 4082 break; 4083 } 4084 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4085 } 4086 4087 InstructionCost X86TTIImpl::getCFInstrCost(unsigned Opcode, 4088 TTI::TargetCostKind CostKind, 4089 const Instruction *I) { 4090 if (CostKind != TTI::TCK_RecipThroughput) 4091 return Opcode == Instruction::PHI ? 0 : 1; 4092 // Branches are assumed to be predicted. 4093 return 0; 4094 } 4095 4096 int X86TTIImpl::getGatherOverhead() const { 4097 // Some CPUs have more overhead for gather. The specified overhead is relative 4098 // to the Load operation. "2" is the number provided by Intel architects. This 4099 // parameter is used for cost estimation of Gather Op and comparison with 4100 // other alternatives. 4101 // TODO: Remove the explicit hasAVX512()?, That would mean we would only 4102 // enable gather with a -march. 4103 if (ST->hasAVX512() || (ST->hasAVX2() && ST->hasFastGather())) 4104 return 2; 4105 4106 return 1024; 4107 } 4108 4109 int X86TTIImpl::getScatterOverhead() const { 4110 if (ST->hasAVX512()) 4111 return 2; 4112 4113 return 1024; 4114 } 4115 4116 // Return an average cost of Gather / Scatter instruction, maybe improved later. 4117 // FIXME: Add TargetCostKind support. 4118 InstructionCost X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, 4119 const Value *Ptr, Align Alignment, 4120 unsigned AddressSpace) { 4121 4122 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 4123 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4124 4125 // Try to reduce index size from 64 bit (default for GEP) 4126 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 4127 // operation will use 16 x 64 indices which do not fit in a zmm and needs 4128 // to split. Also check that the base pointer is the same for all lanes, 4129 // and that there's at most one variable index. 4130 auto getIndexSizeInBits = [](const Value *Ptr, const DataLayout &DL) { 4131 unsigned IndexSize = DL.getPointerSizeInBits(); 4132 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 4133 if (IndexSize < 64 || !GEP) 4134 return IndexSize; 4135 4136 unsigned NumOfVarIndices = 0; 4137 const Value *Ptrs = GEP->getPointerOperand(); 4138 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 4139 return IndexSize; 4140 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 4141 if (isa<Constant>(GEP->getOperand(i))) 4142 continue; 4143 Type *IndxTy = GEP->getOperand(i)->getType(); 4144 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 4145 IndxTy = IndexVTy->getElementType(); 4146 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 4147 !isa<SExtInst>(GEP->getOperand(i))) || 4148 ++NumOfVarIndices > 1) 4149 return IndexSize; // 64 4150 } 4151 return (unsigned)32; 4152 }; 4153 4154 // Trying to reduce IndexSize to 32 bits for vector 16. 4155 // By default the IndexSize is equal to pointer size. 4156 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 4157 ? getIndexSizeInBits(Ptr, DL) 4158 : DL.getPointerSizeInBits(); 4159 4160 auto *IndexVTy = FixedVectorType::get( 4161 IntegerType::get(SrcVTy->getContext(), IndexSize), VF); 4162 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy); 4163 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy); 4164 int SplitFactor = std::max(IdxsLT.first, SrcLT.first); 4165 if (SplitFactor > 1) { 4166 // Handle splitting of vector of pointers 4167 auto *SplitSrcTy = 4168 FixedVectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 4169 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 4170 AddressSpace); 4171 } 4172 4173 // The gather / scatter cost is given by Intel architects. It is a rough 4174 // number since we are looking at one instruction in a time. 4175 const int GSOverhead = (Opcode == Instruction::Load) 4176 ? getGatherOverhead() 4177 : getScatterOverhead(); 4178 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4179 MaybeAlign(Alignment), AddressSpace, 4180 TTI::TCK_RecipThroughput); 4181 } 4182 4183 /// Return the cost of full scalarization of gather / scatter operation. 4184 /// 4185 /// Opcode - Load or Store instruction. 4186 /// SrcVTy - The type of the data vector that should be gathered or scattered. 4187 /// VariableMask - The mask is non-constant at compile time. 4188 /// Alignment - Alignment for one element. 4189 /// AddressSpace - pointer[s] address space. 4190 /// 4191 /// FIXME: Add TargetCostKind support. 4192 InstructionCost X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 4193 bool VariableMask, Align Alignment, 4194 unsigned AddressSpace) { 4195 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4196 APInt DemandedElts = APInt::getAllOnesValue(VF); 4197 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4198 4199 InstructionCost MaskUnpackCost = 0; 4200 if (VariableMask) { 4201 auto *MaskTy = 4202 FixedVectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 4203 MaskUnpackCost = 4204 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 4205 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 4206 Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), nullptr, 4207 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4208 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 4209 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 4210 } 4211 4212 // The cost of the scalar loads/stores. 4213 InstructionCost MemoryOpCost = 4214 VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4215 MaybeAlign(Alignment), AddressSpace, CostKind); 4216 4217 InstructionCost InsertExtractCost = 0; 4218 if (Opcode == Instruction::Load) 4219 for (unsigned i = 0; i < VF; ++i) 4220 // Add the cost of inserting each scalar load into the vector 4221 InsertExtractCost += 4222 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 4223 else 4224 for (unsigned i = 0; i < VF; ++i) 4225 // Add the cost of extracting each element out of the data vector 4226 InsertExtractCost += 4227 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 4228 4229 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 4230 } 4231 4232 /// Calculate the cost of Gather / Scatter operation 4233 InstructionCost X86TTIImpl::getGatherScatterOpCost( 4234 unsigned Opcode, Type *SrcVTy, const Value *Ptr, bool VariableMask, 4235 Align Alignment, TTI::TargetCostKind CostKind, 4236 const Instruction *I = nullptr) { 4237 if (CostKind != TTI::TCK_RecipThroughput) { 4238 if ((Opcode == Instruction::Load && 4239 isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4240 (Opcode == Instruction::Store && 4241 isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4242 return 1; 4243 return BaseT::getGatherScatterOpCost(Opcode, SrcVTy, Ptr, VariableMask, 4244 Alignment, CostKind, I); 4245 } 4246 4247 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 4248 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4249 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 4250 if (!PtrTy && Ptr->getType()->isVectorTy()) 4251 PtrTy = dyn_cast<PointerType>( 4252 cast<VectorType>(Ptr->getType())->getElementType()); 4253 assert(PtrTy && "Unexpected type for Ptr argument"); 4254 unsigned AddressSpace = PtrTy->getAddressSpace(); 4255 4256 bool Scalarize = false; 4257 if ((Opcode == Instruction::Load && 4258 !isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4259 (Opcode == Instruction::Store && 4260 !isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4261 Scalarize = true; 4262 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 4263 // Vector-4 of gather/scatter instruction does not exist on KNL. 4264 // We can extend it to 8 elements, but zeroing upper bits of 4265 // the mask vector will add more instructions. Right now we give the scalar 4266 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 4267 // is better in the VariableMask case. 4268 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 4269 Scalarize = true; 4270 4271 if (Scalarize) 4272 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 4273 AddressSpace); 4274 4275 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 4276 } 4277 4278 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 4279 TargetTransformInfo::LSRCost &C2) { 4280 // X86 specific here are "instruction number 1st priority". 4281 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 4282 C1.NumIVMuls, C1.NumBaseAdds, 4283 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 4284 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 4285 C2.NumIVMuls, C2.NumBaseAdds, 4286 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 4287 } 4288 4289 bool X86TTIImpl::canMacroFuseCmp() { 4290 return ST->hasMacroFusion() || ST->hasBranchFusion(); 4291 } 4292 4293 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, Align Alignment) { 4294 if (!ST->hasAVX()) 4295 return false; 4296 4297 // The backend can't handle a single element vector. 4298 if (isa<VectorType>(DataTy) && 4299 cast<FixedVectorType>(DataTy)->getNumElements() == 1) 4300 return false; 4301 Type *ScalarTy = DataTy->getScalarType(); 4302 4303 if (ScalarTy->isPointerTy()) 4304 return true; 4305 4306 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4307 return true; 4308 4309 if (!ScalarTy->isIntegerTy()) 4310 return false; 4311 4312 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4313 return IntWidth == 32 || IntWidth == 64 || 4314 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 4315 } 4316 4317 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, Align Alignment) { 4318 return isLegalMaskedLoad(DataType, Alignment); 4319 } 4320 4321 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 4322 unsigned DataSize = DL.getTypeStoreSize(DataType); 4323 // The only supported nontemporal loads are for aligned vectors of 16 or 32 4324 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 4325 // (the equivalent stores only require AVX). 4326 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 4327 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 4328 4329 return false; 4330 } 4331 4332 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 4333 unsigned DataSize = DL.getTypeStoreSize(DataType); 4334 4335 // SSE4A supports nontemporal stores of float and double at arbitrary 4336 // alignment. 4337 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 4338 return true; 4339 4340 // Besides the SSE4A subtarget exception above, only aligned stores are 4341 // available nontemporaly on any other subtarget. And only stores with a size 4342 // of 4..32 bytes (powers of 2, only) are permitted. 4343 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 4344 !isPowerOf2_32(DataSize)) 4345 return false; 4346 4347 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 4348 // loads require AVX2). 4349 if (DataSize == 32) 4350 return ST->hasAVX(); 4351 else if (DataSize == 16) 4352 return ST->hasSSE1(); 4353 return true; 4354 } 4355 4356 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 4357 if (!isa<VectorType>(DataTy)) 4358 return false; 4359 4360 if (!ST->hasAVX512()) 4361 return false; 4362 4363 // The backend can't handle a single element vector. 4364 if (cast<FixedVectorType>(DataTy)->getNumElements() == 1) 4365 return false; 4366 4367 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 4368 4369 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4370 return true; 4371 4372 if (!ScalarTy->isIntegerTy()) 4373 return false; 4374 4375 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4376 return IntWidth == 32 || IntWidth == 64 || 4377 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 4378 } 4379 4380 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 4381 return isLegalMaskedExpandLoad(DataTy); 4382 } 4383 4384 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, Align Alignment) { 4385 // Some CPUs have better gather performance than others. 4386 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 4387 // enable gather with a -march. 4388 if (!(ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()))) 4389 return false; 4390 4391 // This function is called now in two cases: from the Loop Vectorizer 4392 // and from the Scalarizer. 4393 // When the Loop Vectorizer asks about legality of the feature, 4394 // the vectorization factor is not calculated yet. The Loop Vectorizer 4395 // sends a scalar type and the decision is based on the width of the 4396 // scalar element. 4397 // Later on, the cost model will estimate usage this intrinsic based on 4398 // the vector type. 4399 // The Scalarizer asks again about legality. It sends a vector type. 4400 // In this case we can reject non-power-of-2 vectors. 4401 // We also reject single element vectors as the type legalizer can't 4402 // scalarize it. 4403 if (auto *DataVTy = dyn_cast<FixedVectorType>(DataTy)) { 4404 unsigned NumElts = DataVTy->getNumElements(); 4405 if (NumElts == 1) 4406 return false; 4407 } 4408 Type *ScalarTy = DataTy->getScalarType(); 4409 if (ScalarTy->isPointerTy()) 4410 return true; 4411 4412 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4413 return true; 4414 4415 if (!ScalarTy->isIntegerTy()) 4416 return false; 4417 4418 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4419 return IntWidth == 32 || IntWidth == 64; 4420 } 4421 4422 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, Align Alignment) { 4423 // AVX2 doesn't support scatter 4424 if (!ST->hasAVX512()) 4425 return false; 4426 return isLegalMaskedGather(DataType, Alignment); 4427 } 4428 4429 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 4430 EVT VT = TLI->getValueType(DL, DataType); 4431 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 4432 } 4433 4434 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 4435 return false; 4436 } 4437 4438 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 4439 const Function *Callee) const { 4440 const TargetMachine &TM = getTLI()->getTargetMachine(); 4441 4442 // Work this as a subsetting of subtarget features. 4443 const FeatureBitset &CallerBits = 4444 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 4445 const FeatureBitset &CalleeBits = 4446 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 4447 4448 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 4449 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 4450 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 4451 } 4452 4453 bool X86TTIImpl::areFunctionArgsABICompatible( 4454 const Function *Caller, const Function *Callee, 4455 SmallPtrSetImpl<Argument *> &Args) const { 4456 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args)) 4457 return false; 4458 4459 // If we get here, we know the target features match. If one function 4460 // considers 512-bit vectors legal and the other does not, consider them 4461 // incompatible. 4462 const TargetMachine &TM = getTLI()->getTargetMachine(); 4463 4464 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 4465 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs()) 4466 return true; 4467 4468 // Consider the arguments compatible if they aren't vectors or aggregates. 4469 // FIXME: Look at the size of vectors. 4470 // FIXME: Look at the element types of aggregates to see if there are vectors. 4471 // FIXME: The API of this function seems intended to allow arguments 4472 // to be removed from the set, but the caller doesn't check if the set 4473 // becomes empty so that may not work in practice. 4474 return llvm::none_of(Args, [](Argument *A) { 4475 auto *EltTy = cast<PointerType>(A->getType())->getElementType(); 4476 return EltTy->isVectorTy() || EltTy->isAggregateType(); 4477 }); 4478 } 4479 4480 X86TTIImpl::TTI::MemCmpExpansionOptions 4481 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 4482 TTI::MemCmpExpansionOptions Options; 4483 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 4484 Options.NumLoadsPerBlock = 2; 4485 // All GPR and vector loads can be unaligned. 4486 Options.AllowOverlappingLoads = true; 4487 if (IsZeroCmp) { 4488 // Only enable vector loads for equality comparison. Right now the vector 4489 // version is not as fast for three way compare (see #33329). 4490 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 4491 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 4492 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 4493 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 4494 } 4495 if (ST->is64Bit()) { 4496 Options.LoadSizes.push_back(8); 4497 } 4498 Options.LoadSizes.push_back(4); 4499 Options.LoadSizes.push_back(2); 4500 Options.LoadSizes.push_back(1); 4501 return Options; 4502 } 4503 4504 bool X86TTIImpl::enableInterleavedAccessVectorization() { 4505 // TODO: We expect this to be beneficial regardless of arch, 4506 // but there are currently some unexplained performance artifacts on Atom. 4507 // As a temporary solution, disable on Atom. 4508 return !(ST->isAtom()); 4509 } 4510 4511 // Get estimation for interleaved load/store operations for AVX2. 4512 // \p Factor is the interleaved-access factor (stride) - number of 4513 // (interleaved) elements in the group. 4514 // \p Indices contains the indices for a strided load: when the 4515 // interleaved load has gaps they indicate which elements are used. 4516 // If Indices is empty (or if the number of indices is equal to the size 4517 // of the interleaved-access as given in \p Factor) the access has no gaps. 4518 // 4519 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 4520 // computing the cost using a generic formula as a function of generic 4521 // shuffles. We therefore use a lookup table instead, filled according to 4522 // the instruction sequences that codegen currently generates. 4523 InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2( 4524 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 4525 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 4526 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 4527 4528 if (UseMaskForCond || UseMaskForGaps) 4529 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4530 Alignment, AddressSpace, CostKind, 4531 UseMaskForCond, UseMaskForGaps); 4532 4533 // We currently Support only fully-interleaved groups, with no gaps. 4534 // TODO: Support also strided loads (interleaved-groups with gaps). 4535 if (Indices.size() && Indices.size() != Factor) 4536 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4537 Alignment, AddressSpace, 4538 CostKind); 4539 4540 // VecTy for interleave memop is <VF*Factor x Elt>. 4541 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4542 // VecTy = <12 x i32>. 4543 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4544 4545 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 4546 // the VF=2, while v2i128 is an unsupported MVT vector type 4547 // (see MachineValueType.h::getVectorVT()). 4548 if (!LegalVT.isVector()) 4549 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4550 Alignment, AddressSpace, 4551 CostKind); 4552 4553 unsigned VF = VecTy->getNumElements() / Factor; 4554 Type *ScalarTy = VecTy->getElementType(); 4555 4556 // Calculate the number of memory operations (NumOfMemOps), required 4557 // for load/store the VecTy. 4558 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4559 unsigned LegalVTSize = LegalVT.getStoreSize(); 4560 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4561 4562 // Get the cost of one memory operation. 4563 auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(), 4564 LegalVT.getVectorNumElements()); 4565 InstructionCost MemOpCost = getMemoryOpCost( 4566 Opcode, SingleMemOpTy, MaybeAlign(Alignment), AddressSpace, CostKind); 4567 4568 auto *VT = FixedVectorType::get(ScalarTy, VF); 4569 EVT ETy = TLI->getValueType(DL, VT); 4570 if (!ETy.isSimple()) 4571 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4572 Alignment, AddressSpace, 4573 CostKind); 4574 4575 // TODO: Complete for other data-types and strides. 4576 // Each combination of Stride, ElementTy and VF results in a different 4577 // sequence; The cost tables are therefore accessed with: 4578 // Factor (stride) and VectorType=VFxElemType. 4579 // The Cost accounts only for the shuffle sequence; 4580 // The cost of the loads/stores is accounted for separately. 4581 // 4582 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 4583 { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64 4584 { 2, MVT::v4f64, 6 }, //(load 8f64 and) deinterleave into 2 x 4f64 4585 4586 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8 4587 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8 4588 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8 4589 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8 4590 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8 4591 { 3, MVT::v8f32, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32 4592 4593 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8 4594 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8 4595 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8 4596 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8 4597 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8 4598 4599 { 8, MVT::v8f32, 40 } //(load 64f32 and)deinterleave into 8 x 8f32 4600 }; 4601 4602 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 4603 { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store) 4604 { 2, MVT::v4f64, 6 }, //interleave into 2 x 4f64 into 8f64 (and store) 4605 4606 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store) 4607 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store) 4608 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store) 4609 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store) 4610 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store) 4611 4612 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store) 4613 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store) 4614 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store) 4615 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store) 4616 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store) 4617 }; 4618 4619 if (Opcode == Instruction::Load) { 4620 if (const auto *Entry = 4621 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 4622 return NumOfMemOps * MemOpCost + Entry->Cost; 4623 } else { 4624 assert(Opcode == Instruction::Store && 4625 "Expected Store Instruction at this point"); 4626 if (const auto *Entry = 4627 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 4628 return NumOfMemOps * MemOpCost + Entry->Cost; 4629 } 4630 4631 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4632 Alignment, AddressSpace, CostKind); 4633 } 4634 4635 // Get estimation for interleaved load/store operations and strided load. 4636 // \p Indices contains indices for strided load. 4637 // \p Factor - the factor of interleaving. 4638 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 4639 InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX512( 4640 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 4641 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 4642 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 4643 4644 if (UseMaskForCond || UseMaskForGaps) 4645 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4646 Alignment, AddressSpace, CostKind, 4647 UseMaskForCond, UseMaskForGaps); 4648 4649 // VecTy for interleave memop is <VF*Factor x Elt>. 4650 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4651 // VecTy = <12 x i32>. 4652 4653 // Calculate the number of memory operations (NumOfMemOps), required 4654 // for load/store the VecTy. 4655 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4656 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4657 unsigned LegalVTSize = LegalVT.getStoreSize(); 4658 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4659 4660 // Get the cost of one memory operation. 4661 auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(), 4662 LegalVT.getVectorNumElements()); 4663 InstructionCost MemOpCost = getMemoryOpCost( 4664 Opcode, SingleMemOpTy, MaybeAlign(Alignment), AddressSpace, CostKind); 4665 4666 unsigned VF = VecTy->getNumElements() / Factor; 4667 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 4668 4669 if (Opcode == Instruction::Load) { 4670 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 4671 // contain the cost of the optimized shuffle sequence that the 4672 // X86InterleavedAccess pass will generate. 4673 // The cost of loads and stores are computed separately from the table. 4674 4675 // X86InterleavedAccess support only the following interleaved-access group. 4676 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 4677 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 4678 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 4679 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 4680 }; 4681 4682 if (const auto *Entry = 4683 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 4684 return NumOfMemOps * MemOpCost + Entry->Cost; 4685 //If an entry does not exist, fallback to the default implementation. 4686 4687 // Kind of shuffle depends on number of loaded values. 4688 // If we load the entire data in one register, we can use a 1-src shuffle. 4689 // Otherwise, we'll merge 2 sources in each operation. 4690 TTI::ShuffleKind ShuffleKind = 4691 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 4692 4693 InstructionCost ShuffleCost = 4694 getShuffleCost(ShuffleKind, SingleMemOpTy, None, 0, nullptr); 4695 4696 unsigned NumOfLoadsInInterleaveGrp = 4697 Indices.size() ? Indices.size() : Factor; 4698 auto *ResultTy = FixedVectorType::get(VecTy->getElementType(), 4699 VecTy->getNumElements() / Factor); 4700 unsigned NumOfResults = 4701 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 4702 NumOfLoadsInInterleaveGrp; 4703 4704 // About a half of the loads may be folded in shuffles when we have only 4705 // one result. If we have more than one result, we do not fold loads at all. 4706 unsigned NumOfUnfoldedLoads = 4707 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 4708 4709 // Get a number of shuffle operations per result. 4710 unsigned NumOfShufflesPerResult = 4711 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 4712 4713 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4714 // When we have more than one destination, we need additional instructions 4715 // to keep sources. 4716 unsigned NumOfMoves = 0; 4717 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 4718 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 4719 4720 InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 4721 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 4722 4723 return Cost; 4724 } 4725 4726 // Store. 4727 assert(Opcode == Instruction::Store && 4728 "Expected Store Instruction at this point"); 4729 // X86InterleavedAccess support only the following interleaved-access group. 4730 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 4731 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 4732 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 4733 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 4734 4735 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 4736 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 4737 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 4738 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 4739 }; 4740 4741 if (const auto *Entry = 4742 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 4743 return NumOfMemOps * MemOpCost + Entry->Cost; 4744 //If an entry does not exist, fallback to the default implementation. 4745 4746 // There is no strided stores meanwhile. And store can't be folded in 4747 // shuffle. 4748 unsigned NumOfSources = Factor; // The number of values to be merged. 4749 InstructionCost ShuffleCost = 4750 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, None, 0, nullptr); 4751 unsigned NumOfShufflesPerStore = NumOfSources - 1; 4752 4753 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4754 // We need additional instructions to keep sources. 4755 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 4756 InstructionCost Cost = 4757 NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 4758 NumOfMoves; 4759 return Cost; 4760 } 4761 4762 InstructionCost X86TTIImpl::getInterleavedMemoryOpCost( 4763 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, 4764 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, 4765 bool UseMaskForCond, bool UseMaskForGaps) { 4766 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 4767 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 4768 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 4769 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 4770 return true; 4771 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 4772 return HasBW; 4773 return false; 4774 }; 4775 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 4776 return getInterleavedMemoryOpCostAVX512( 4777 Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment, 4778 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 4779 if (ST->hasAVX2()) 4780 return getInterleavedMemoryOpCostAVX2( 4781 Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment, 4782 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 4783 4784 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4785 Alignment, AddressSpace, CostKind, 4786 UseMaskForCond, UseMaskForGaps); 4787 } 4788