1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // X86 cost model. 56 // 57 //===----------------------------------------------------------------------===// 58 59 TargetTransformInfo::PopcntSupportKind 60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 61 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 62 // TODO: Currently the __builtin_popcount() implementation using SSE3 63 // instructions is inefficient. Once the problem is fixed, we should 64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 66 } 67 68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 69 TargetTransformInfo::CacheLevel Level) const { 70 switch (Level) { 71 case TargetTransformInfo::CacheLevel::L1D: 72 // - Penryn 73 // - Nehalem 74 // - Westmere 75 // - Sandy Bridge 76 // - Ivy Bridge 77 // - Haswell 78 // - Broadwell 79 // - Skylake 80 // - Kabylake 81 return 32 * 1024; // 32 KByte 82 case TargetTransformInfo::CacheLevel::L2D: 83 // - Penryn 84 // - Nehalem 85 // - Westmere 86 // - Sandy Bridge 87 // - Ivy Bridge 88 // - Haswell 89 // - Broadwell 90 // - Skylake 91 // - Kabylake 92 return 256 * 1024; // 256 KByte 93 } 94 95 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 96 } 97 98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 99 TargetTransformInfo::CacheLevel Level) const { 100 // - Penryn 101 // - Nehalem 102 // - Westmere 103 // - Sandy Bridge 104 // - Ivy Bridge 105 // - Haswell 106 // - Broadwell 107 // - Skylake 108 // - Kabylake 109 switch (Level) { 110 case TargetTransformInfo::CacheLevel::L1D: 111 LLVM_FALLTHROUGH; 112 case TargetTransformInfo::CacheLevel::L2D: 113 return 8; 114 } 115 116 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 117 } 118 119 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 120 bool Vector = (ClassID == 1); 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 TypeSize 133 X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { 134 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 135 switch (K) { 136 case TargetTransformInfo::RGK_Scalar: 137 return TypeSize::getFixed(ST->is64Bit() ? 64 : 32); 138 case TargetTransformInfo::RGK_FixedWidthVector: 139 if (ST->hasAVX512() && PreferVectorWidth >= 512) 140 return TypeSize::getFixed(512); 141 if (ST->hasAVX() && PreferVectorWidth >= 256) 142 return TypeSize::getFixed(256); 143 if (ST->hasSSE1() && PreferVectorWidth >= 128) 144 return TypeSize::getFixed(128); 145 return TypeSize::getFixed(0); 146 case TargetTransformInfo::RGK_ScalableVector: 147 return TypeSize::getScalable(0); 148 } 149 150 llvm_unreachable("Unsupported register kind"); 151 } 152 153 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 154 return getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector) 155 .getFixedSize(); 156 } 157 158 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 159 // If the loop will not be vectorized, don't interleave the loop. 160 // Let regular unroll to unroll the loop, which saves the overflow 161 // check and memory check cost. 162 if (VF == 1) 163 return 1; 164 165 if (ST->isAtom()) 166 return 1; 167 168 // Sandybridge and Haswell have multiple execution ports and pipelined 169 // vector units. 170 if (ST->hasAVX()) 171 return 4; 172 173 return 2; 174 } 175 176 int X86TTIImpl::getArithmeticInstrCost(unsigned Opcode, Type *Ty, 177 TTI::TargetCostKind CostKind, 178 TTI::OperandValueKind Op1Info, 179 TTI::OperandValueKind Op2Info, 180 TTI::OperandValueProperties Opd1PropInfo, 181 TTI::OperandValueProperties Opd2PropInfo, 182 ArrayRef<const Value *> Args, 183 const Instruction *CxtI) { 184 // TODO: Handle more cost kinds. 185 if (CostKind != TTI::TCK_RecipThroughput) 186 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, 187 Op2Info, Opd1PropInfo, 188 Opd2PropInfo, Args, CxtI); 189 // Legalize the type. 190 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 191 192 int ISD = TLI->InstructionOpcodeToISD(Opcode); 193 assert(ISD && "Invalid opcode"); 194 195 static const CostTblEntry GLMCostTable[] = { 196 { ISD::FDIV, MVT::f32, 18 }, // divss 197 { ISD::FDIV, MVT::v4f32, 35 }, // divps 198 { ISD::FDIV, MVT::f64, 33 }, // divsd 199 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 200 }; 201 202 if (ST->useGLMDivSqrtCosts()) 203 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 204 LT.second)) 205 return LT.first * Entry->Cost; 206 207 static const CostTblEntry SLMCostTable[] = { 208 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 209 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 210 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. 211 { ISD::FMUL, MVT::f64, 2 }, // mulsd 212 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 213 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 214 { ISD::FDIV, MVT::f32, 17 }, // divss 215 { ISD::FDIV, MVT::v4f32, 39 }, // divps 216 { ISD::FDIV, MVT::f64, 32 }, // divsd 217 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 218 { ISD::FADD, MVT::v2f64, 2 }, // addpd 219 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 220 // v2i64/v4i64 mul is custom lowered as a series of long: 221 // multiplies(3), shifts(3) and adds(2) 222 // slm muldq version throughput is 2 and addq throughput 4 223 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 224 // 3X4 (addq throughput) = 17 225 { ISD::MUL, MVT::v2i64, 17 }, 226 // slm addq\subq throughput is 4 227 { ISD::ADD, MVT::v2i64, 4 }, 228 { ISD::SUB, MVT::v2i64, 4 }, 229 }; 230 231 if (ST->isSLM()) { 232 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 233 // Check if the operands can be shrinked into a smaller datatype. 234 bool Op1Signed = false; 235 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 236 bool Op2Signed = false; 237 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 238 239 bool SignedMode = Op1Signed || Op2Signed; 240 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 241 242 if (OpMinSize <= 7) 243 return LT.first * 3; // pmullw/sext 244 if (!SignedMode && OpMinSize <= 8) 245 return LT.first * 3; // pmullw/zext 246 if (OpMinSize <= 15) 247 return LT.first * 5; // pmullw/pmulhw/pshuf 248 if (!SignedMode && OpMinSize <= 16) 249 return LT.first * 5; // pmullw/pmulhw/pshuf 250 } 251 252 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 253 LT.second)) { 254 return LT.first * Entry->Cost; 255 } 256 } 257 258 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 259 ISD == ISD::UREM) && 260 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 261 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 262 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 263 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 264 // On X86, vector signed division by constants power-of-two are 265 // normally expanded to the sequence SRA + SRL + ADD + SRA. 266 // The OperandValue properties may not be the same as that of the previous 267 // operation; conservatively assume OP_None. 268 int Cost = 269 2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Op1Info, 270 Op2Info, 271 TargetTransformInfo::OP_None, 272 TargetTransformInfo::OP_None); 273 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 274 Op2Info, 275 TargetTransformInfo::OP_None, 276 TargetTransformInfo::OP_None); 277 Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind, Op1Info, 278 Op2Info, 279 TargetTransformInfo::OP_None, 280 TargetTransformInfo::OP_None); 281 282 if (ISD == ISD::SREM) { 283 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 284 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info, 285 Op2Info); 286 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info, 287 Op2Info); 288 } 289 290 return Cost; 291 } 292 293 // Vector unsigned division/remainder will be simplified to shifts/masks. 294 if (ISD == ISD::UDIV) 295 return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, 296 Op1Info, Op2Info, 297 TargetTransformInfo::OP_None, 298 TargetTransformInfo::OP_None); 299 300 else // UREM 301 return getArithmeticInstrCost(Instruction::And, Ty, CostKind, 302 Op1Info, Op2Info, 303 TargetTransformInfo::OP_None, 304 TargetTransformInfo::OP_None); 305 } 306 307 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 308 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 309 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 310 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 311 }; 312 313 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 314 ST->hasBWI()) { 315 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 316 LT.second)) 317 return LT.first * Entry->Cost; 318 } 319 320 static const CostTblEntry AVX512UniformConstCostTable[] = { 321 { ISD::SRA, MVT::v2i64, 1 }, 322 { ISD::SRA, MVT::v4i64, 1 }, 323 { ISD::SRA, MVT::v8i64, 1 }, 324 325 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 326 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 327 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 328 329 { ISD::SDIV, MVT::v16i32, 6 }, // pmuludq sequence 330 { ISD::SREM, MVT::v16i32, 8 }, // pmuludq+mul+sub sequence 331 { ISD::UDIV, MVT::v16i32, 5 }, // pmuludq sequence 332 { ISD::UREM, MVT::v16i32, 7 }, // pmuludq+mul+sub sequence 333 }; 334 335 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 336 ST->hasAVX512()) { 337 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 338 LT.second)) 339 return LT.first * Entry->Cost; 340 } 341 342 static const CostTblEntry AVX2UniformConstCostTable[] = { 343 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 344 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 345 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 346 347 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 348 349 { ISD::SDIV, MVT::v8i32, 6 }, // pmuludq sequence 350 { ISD::SREM, MVT::v8i32, 8 }, // pmuludq+mul+sub sequence 351 { ISD::UDIV, MVT::v8i32, 5 }, // pmuludq sequence 352 { ISD::UREM, MVT::v8i32, 7 }, // pmuludq+mul+sub sequence 353 }; 354 355 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 356 ST->hasAVX2()) { 357 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 358 LT.second)) 359 return LT.first * Entry->Cost; 360 } 361 362 static const CostTblEntry SSE2UniformConstCostTable[] = { 363 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 364 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 365 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 366 367 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 368 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 369 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 370 371 { ISD::SDIV, MVT::v8i32, 12+2 }, // 2*pmuludq sequence + split. 372 { ISD::SREM, MVT::v8i32, 16+2 }, // 2*pmuludq+mul+sub sequence + split. 373 { ISD::SDIV, MVT::v4i32, 6 }, // pmuludq sequence 374 { ISD::SREM, MVT::v4i32, 8 }, // pmuludq+mul+sub sequence 375 { ISD::UDIV, MVT::v8i32, 10+2 }, // 2*pmuludq sequence + split. 376 { ISD::UREM, MVT::v8i32, 14+2 }, // 2*pmuludq+mul+sub sequence + split. 377 { ISD::UDIV, MVT::v4i32, 5 }, // pmuludq sequence 378 { ISD::UREM, MVT::v4i32, 7 }, // pmuludq+mul+sub sequence 379 }; 380 381 // XOP has faster vXi8 shifts. 382 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 383 ST->hasSSE2() && !ST->hasXOP()) { 384 if (const auto *Entry = 385 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 386 return LT.first * Entry->Cost; 387 } 388 389 static const CostTblEntry AVX512BWConstCostTable[] = { 390 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 391 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 392 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 393 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 394 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 395 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 396 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 397 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 398 }; 399 400 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 401 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 402 ST->hasBWI()) { 403 if (const auto *Entry = 404 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 405 return LT.first * Entry->Cost; 406 } 407 408 static const CostTblEntry AVX512ConstCostTable[] = { 409 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 410 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 411 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 412 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 413 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 414 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 415 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 416 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 417 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 418 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 419 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 420 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 421 }; 422 423 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 424 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 425 ST->hasAVX512()) { 426 if (const auto *Entry = 427 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 428 return LT.first * Entry->Cost; 429 } 430 431 static const CostTblEntry AVX2ConstCostTable[] = { 432 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 433 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 434 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 435 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 436 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 437 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 438 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 439 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 440 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 441 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 442 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 443 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 444 }; 445 446 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 447 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 448 ST->hasAVX2()) { 449 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 450 return LT.first * Entry->Cost; 451 } 452 453 static const CostTblEntry SSE2ConstCostTable[] = { 454 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 455 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 456 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 457 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 458 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 459 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 460 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 461 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 462 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 463 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 464 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 465 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 466 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 467 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 468 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 469 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 470 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 471 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 472 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 473 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 474 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 475 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 476 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 477 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 478 }; 479 480 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 481 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 482 ST->hasSSE2()) { 483 // pmuldq sequence. 484 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 485 return LT.first * 32; 486 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 487 return LT.first * 38; 488 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 489 return LT.first * 15; 490 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 491 return LT.first * 20; 492 493 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 494 return LT.first * Entry->Cost; 495 } 496 497 static const CostTblEntry AVX512BWShiftCostTable[] = { 498 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 499 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 500 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 501 502 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 503 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 504 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 505 506 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 507 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 508 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 509 }; 510 511 if (ST->hasBWI()) 512 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 513 return LT.first * Entry->Cost; 514 515 static const CostTblEntry AVX2UniformCostTable[] = { 516 // Uniform splats are cheaper for the following instructions. 517 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 518 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 519 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 520 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 521 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 522 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 523 }; 524 525 if (ST->hasAVX2() && 526 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 527 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 528 if (const auto *Entry = 529 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 530 return LT.first * Entry->Cost; 531 } 532 533 static const CostTblEntry SSE2UniformCostTable[] = { 534 // Uniform splats are cheaper for the following instructions. 535 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 536 { ISD::SHL, MVT::v4i32, 1 }, // pslld 537 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 538 539 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 540 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 541 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 542 543 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 544 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 545 }; 546 547 if (ST->hasSSE2() && 548 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 549 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 550 if (const auto *Entry = 551 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 552 return LT.first * Entry->Cost; 553 } 554 555 static const CostTblEntry AVX512DQCostTable[] = { 556 { ISD::MUL, MVT::v2i64, 1 }, 557 { ISD::MUL, MVT::v4i64, 1 }, 558 { ISD::MUL, MVT::v8i64, 1 } 559 }; 560 561 // Look for AVX512DQ lowering tricks for custom cases. 562 if (ST->hasDQI()) 563 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 564 return LT.first * Entry->Cost; 565 566 static const CostTblEntry AVX512BWCostTable[] = { 567 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 568 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 569 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 570 571 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence. 572 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence. 573 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence. 574 }; 575 576 // Look for AVX512BW lowering tricks for custom cases. 577 if (ST->hasBWI()) 578 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 579 return LT.first * Entry->Cost; 580 581 static const CostTblEntry AVX512CostTable[] = { 582 { ISD::SHL, MVT::v16i32, 1 }, 583 { ISD::SRL, MVT::v16i32, 1 }, 584 { ISD::SRA, MVT::v16i32, 1 }, 585 586 { ISD::SHL, MVT::v8i64, 1 }, 587 { ISD::SRL, MVT::v8i64, 1 }, 588 589 { ISD::SRA, MVT::v2i64, 1 }, 590 { ISD::SRA, MVT::v4i64, 1 }, 591 { ISD::SRA, MVT::v8i64, 1 }, 592 593 { ISD::MUL, MVT::v64i8, 26 }, // extend/pmullw/trunc sequence. 594 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence. 595 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence. 596 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 597 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 598 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 599 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add 600 601 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 602 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 603 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 604 605 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 606 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 607 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 608 }; 609 610 if (ST->hasAVX512()) 611 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 612 return LT.first * Entry->Cost; 613 614 static const CostTblEntry AVX2ShiftCostTable[] = { 615 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 616 // customize them to detect the cases where shift amount is a scalar one. 617 { ISD::SHL, MVT::v4i32, 1 }, 618 { ISD::SRL, MVT::v4i32, 1 }, 619 { ISD::SRA, MVT::v4i32, 1 }, 620 { ISD::SHL, MVT::v8i32, 1 }, 621 { ISD::SRL, MVT::v8i32, 1 }, 622 { ISD::SRA, MVT::v8i32, 1 }, 623 { ISD::SHL, MVT::v2i64, 1 }, 624 { ISD::SRL, MVT::v2i64, 1 }, 625 { ISD::SHL, MVT::v4i64, 1 }, 626 { ISD::SRL, MVT::v4i64, 1 }, 627 }; 628 629 if (ST->hasAVX512()) { 630 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 631 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 632 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 633 // On AVX512, a packed v32i16 shift left by a constant build_vector 634 // is lowered into a vector multiply (vpmullw). 635 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 636 Op1Info, Op2Info, 637 TargetTransformInfo::OP_None, 638 TargetTransformInfo::OP_None); 639 } 640 641 // Look for AVX2 lowering tricks. 642 if (ST->hasAVX2()) { 643 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 644 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 645 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 646 // On AVX2, a packed v16i16 shift left by a constant build_vector 647 // is lowered into a vector multiply (vpmullw). 648 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 649 Op1Info, Op2Info, 650 TargetTransformInfo::OP_None, 651 TargetTransformInfo::OP_None); 652 653 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 654 return LT.first * Entry->Cost; 655 } 656 657 static const CostTblEntry XOPShiftCostTable[] = { 658 // 128bit shifts take 1cy, but right shifts require negation beforehand. 659 { ISD::SHL, MVT::v16i8, 1 }, 660 { ISD::SRL, MVT::v16i8, 2 }, 661 { ISD::SRA, MVT::v16i8, 2 }, 662 { ISD::SHL, MVT::v8i16, 1 }, 663 { ISD::SRL, MVT::v8i16, 2 }, 664 { ISD::SRA, MVT::v8i16, 2 }, 665 { ISD::SHL, MVT::v4i32, 1 }, 666 { ISD::SRL, MVT::v4i32, 2 }, 667 { ISD::SRA, MVT::v4i32, 2 }, 668 { ISD::SHL, MVT::v2i64, 1 }, 669 { ISD::SRL, MVT::v2i64, 2 }, 670 { ISD::SRA, MVT::v2i64, 2 }, 671 // 256bit shifts require splitting if AVX2 didn't catch them above. 672 { ISD::SHL, MVT::v32i8, 2+2 }, 673 { ISD::SRL, MVT::v32i8, 4+2 }, 674 { ISD::SRA, MVT::v32i8, 4+2 }, 675 { ISD::SHL, MVT::v16i16, 2+2 }, 676 { ISD::SRL, MVT::v16i16, 4+2 }, 677 { ISD::SRA, MVT::v16i16, 4+2 }, 678 { ISD::SHL, MVT::v8i32, 2+2 }, 679 { ISD::SRL, MVT::v8i32, 4+2 }, 680 { ISD::SRA, MVT::v8i32, 4+2 }, 681 { ISD::SHL, MVT::v4i64, 2+2 }, 682 { ISD::SRL, MVT::v4i64, 4+2 }, 683 { ISD::SRA, MVT::v4i64, 4+2 }, 684 }; 685 686 // Look for XOP lowering tricks. 687 if (ST->hasXOP()) { 688 // If the right shift is constant then we'll fold the negation so 689 // it's as cheap as a left shift. 690 int ShiftISD = ISD; 691 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 692 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 693 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 694 ShiftISD = ISD::SHL; 695 if (const auto *Entry = 696 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 697 return LT.first * Entry->Cost; 698 } 699 700 static const CostTblEntry SSE2UniformShiftCostTable[] = { 701 // Uniform splats are cheaper for the following instructions. 702 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 703 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 704 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 705 706 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 707 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 708 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 709 710 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 711 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 712 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 713 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 714 }; 715 716 if (ST->hasSSE2() && 717 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 718 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 719 720 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 721 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 722 return LT.first * 4; // 2*psrad + shuffle. 723 724 if (const auto *Entry = 725 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 726 return LT.first * Entry->Cost; 727 } 728 729 if (ISD == ISD::SHL && 730 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 731 MVT VT = LT.second; 732 // Vector shift left by non uniform constant can be lowered 733 // into vector multiply. 734 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 735 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 736 ISD = ISD::MUL; 737 } 738 739 static const CostTblEntry AVX2CostTable[] = { 740 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. 741 { ISD::SHL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. 742 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 743 { ISD::SHL, MVT::v32i16, 20 }, // 2*extend/vpsrlvd/pack sequence. 744 745 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. 746 { ISD::SRL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. 747 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 748 { ISD::SRL, MVT::v32i16, 20 }, // 2*extend/vpsrlvd/pack sequence. 749 750 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. 751 { ISD::SRA, MVT::v64i8, 48 }, // 2*vpblendvb sequence. 752 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. 753 { ISD::SRA, MVT::v32i16, 20 }, // 2*extend/vpsravd/pack sequence. 754 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. 755 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 756 757 { ISD::SUB, MVT::v32i8, 1 }, // psubb 758 { ISD::ADD, MVT::v32i8, 1 }, // paddb 759 { ISD::SUB, MVT::v16i16, 1 }, // psubw 760 { ISD::ADD, MVT::v16i16, 1 }, // paddw 761 { ISD::SUB, MVT::v8i32, 1 }, // psubd 762 { ISD::ADD, MVT::v8i32, 1 }, // paddd 763 { ISD::SUB, MVT::v4i64, 1 }, // psubq 764 { ISD::ADD, MVT::v4i64, 1 }, // paddq 765 766 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence. 767 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence. 768 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 769 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 770 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add 771 772 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 773 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 774 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 775 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 776 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 777 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 778 779 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 780 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 781 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 782 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 783 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 784 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 785 }; 786 787 // Look for AVX2 lowering tricks for custom cases. 788 if (ST->hasAVX2()) 789 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 790 return LT.first * Entry->Cost; 791 792 static const CostTblEntry AVX1CostTable[] = { 793 // We don't have to scalarize unsupported ops. We can issue two half-sized 794 // operations and we only need to extract the upper YMM half. 795 // Two ops + 1 extract + 1 insert = 4. 796 { ISD::MUL, MVT::v16i16, 4 }, 797 { ISD::MUL, MVT::v8i32, 4 }, 798 { ISD::SUB, MVT::v32i8, 4 }, 799 { ISD::ADD, MVT::v32i8, 4 }, 800 { ISD::SUB, MVT::v16i16, 4 }, 801 { ISD::ADD, MVT::v16i16, 4 }, 802 { ISD::SUB, MVT::v8i32, 4 }, 803 { ISD::ADD, MVT::v8i32, 4 }, 804 { ISD::SUB, MVT::v4i64, 4 }, 805 { ISD::ADD, MVT::v4i64, 4 }, 806 807 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 808 // are lowered as a series of long multiplies(3), shifts(3) and adds(2) 809 // Because we believe v4i64 to be a legal type, we must also include the 810 // extract+insert in the cost table. Therefore, the cost here is 18 811 // instead of 8. 812 { ISD::MUL, MVT::v4i64, 18 }, 813 814 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence. 815 816 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 817 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 818 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 819 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 820 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 821 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 822 }; 823 824 if (ST->hasAVX()) 825 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 826 return LT.first * Entry->Cost; 827 828 static const CostTblEntry SSE42CostTable[] = { 829 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 830 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 831 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 832 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 833 834 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 835 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 836 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 837 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 838 839 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 840 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 841 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 842 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 843 844 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 845 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 846 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 847 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 848 }; 849 850 if (ST->hasSSE42()) 851 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 852 return LT.first * Entry->Cost; 853 854 static const CostTblEntry SSE41CostTable[] = { 855 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 856 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split. 857 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 858 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 859 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 860 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split 861 862 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 863 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split. 864 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 865 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 866 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 867 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split. 868 869 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 870 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split. 871 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 872 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 873 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 874 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split. 875 876 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 877 }; 878 879 if (ST->hasSSE41()) 880 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 881 return LT.first * Entry->Cost; 882 883 static const CostTblEntry SSE2CostTable[] = { 884 // We don't correctly identify costs of casts because they are marked as 885 // custom. 886 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 887 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 888 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 889 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 890 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 891 892 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 893 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 894 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 895 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 896 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 897 898 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 899 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 900 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 901 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 902 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split. 903 904 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence. 905 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 906 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 907 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 908 909 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 910 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 911 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 912 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 913 914 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 915 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 916 917 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 918 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 919 }; 920 921 if (ST->hasSSE2()) 922 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 923 return LT.first * Entry->Cost; 924 925 static const CostTblEntry SSE1CostTable[] = { 926 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 927 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 928 929 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 930 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 931 932 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 933 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 934 935 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 936 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 937 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 938 939 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 940 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 941 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 942 }; 943 944 if (ST->hasSSE1()) 945 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 946 return LT.first * Entry->Cost; 947 948 // It is not a good idea to vectorize division. We have to scalarize it and 949 // in the process we will often end up having to spilling regular 950 // registers. The overhead of division is going to dominate most kernels 951 // anyways so try hard to prevent vectorization of division - it is 952 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 953 // to hide "20 cycles" for each lane. 954 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 955 ISD == ISD::UDIV || ISD == ISD::UREM)) { 956 int ScalarCost = getArithmeticInstrCost( 957 Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info, 958 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 959 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 960 } 961 962 // Fallback to the default implementation. 963 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info); 964 } 965 966 int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, VectorType *BaseTp, 967 ArrayRef<int> Mask, int Index, 968 VectorType *SubTp) { 969 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 970 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 971 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 972 973 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 974 if (Kind == TTI::SK_Transpose) 975 Kind = TTI::SK_PermuteTwoSrc; 976 977 // For Broadcasts we are splatting the first element from the first input 978 // register, so only need to reference that input and all the output 979 // registers are the same. 980 if (Kind == TTI::SK_Broadcast) 981 LT.first = 1; 982 983 // Subvector extractions are free if they start at the beginning of a 984 // vector and cheap if the subvectors are aligned. 985 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 986 int NumElts = LT.second.getVectorNumElements(); 987 if ((Index % NumElts) == 0) 988 return 0; 989 std::pair<int, MVT> SubLT = TLI->getTypeLegalizationCost(DL, SubTp); 990 if (SubLT.second.isVector()) { 991 int NumSubElts = SubLT.second.getVectorNumElements(); 992 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 993 return SubLT.first; 994 // Handle some cases for widening legalization. For now we only handle 995 // cases where the original subvector was naturally aligned and evenly 996 // fit in its legalized subvector type. 997 // FIXME: Remove some of the alignment restrictions. 998 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 999 // vectors. 1000 int OrigSubElts = cast<FixedVectorType>(SubTp)->getNumElements(); 1001 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 1002 (NumSubElts % OrigSubElts) == 0 && 1003 LT.second.getVectorElementType() == 1004 SubLT.second.getVectorElementType() && 1005 LT.second.getVectorElementType().getSizeInBits() == 1006 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 1007 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 1008 "Unexpected number of elements!"); 1009 auto *VecTy = FixedVectorType::get(BaseTp->getElementType(), 1010 LT.second.getVectorNumElements()); 1011 auto *SubTy = FixedVectorType::get(BaseTp->getElementType(), 1012 SubLT.second.getVectorNumElements()); 1013 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 1014 int ExtractCost = getShuffleCost(TTI::SK_ExtractSubvector, VecTy, None, 1015 ExtractIndex, SubTy); 1016 1017 // If the original size is 32-bits or more, we can use pshufd. Otherwise 1018 // if we have SSSE3 we can use pshufb. 1019 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 1020 return ExtractCost + 1; // pshufd or pshufb 1021 1022 assert(SubTp->getPrimitiveSizeInBits() == 16 && 1023 "Unexpected vector size"); 1024 1025 return ExtractCost + 2; // worst case pshufhw + pshufd 1026 } 1027 } 1028 } 1029 1030 // Handle some common (illegal) sub-vector types as they are often very cheap 1031 // to shuffle even on targets without PSHUFB. 1032 EVT VT = TLI->getValueType(DL, BaseTp); 1033 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 1034 !ST->hasSSSE3()) { 1035 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 1036 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 1037 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1038 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1039 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1040 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1041 1042 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1043 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1044 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1045 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1046 1047 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1048 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1049 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1050 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1051 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1052 1053 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1054 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1055 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1056 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1057 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1058 }; 1059 1060 if (ST->hasSSE2()) 1061 if (const auto *Entry = 1062 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1063 return Entry->Cost; 1064 } 1065 1066 // We are going to permute multiple sources and the result will be in multiple 1067 // destinations. Providing an accurate cost only for splits where the element 1068 // type remains the same. 1069 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1070 MVT LegalVT = LT.second; 1071 if (LegalVT.isVector() && 1072 LegalVT.getVectorElementType().getSizeInBits() == 1073 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1074 LegalVT.getVectorNumElements() < 1075 cast<FixedVectorType>(BaseTp)->getNumElements()) { 1076 1077 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1078 unsigned LegalVTSize = LegalVT.getStoreSize(); 1079 // Number of source vectors after legalization: 1080 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1081 // Number of destination vectors after legalization: 1082 unsigned NumOfDests = LT.first; 1083 1084 auto *SingleOpTy = FixedVectorType::get(BaseTp->getElementType(), 1085 LegalVT.getVectorNumElements()); 1086 1087 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1088 return NumOfShuffles * getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 1089 None, 0, nullptr); 1090 } 1091 1092 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1093 } 1094 1095 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1096 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1097 // We assume that source and destination have the same vector type. 1098 int NumOfDests = LT.first; 1099 int NumOfShufflesPerDest = LT.first * 2 - 1; 1100 LT.first = NumOfDests * NumOfShufflesPerDest; 1101 } 1102 1103 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1104 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1105 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1106 1107 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1108 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1109 1110 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b 1111 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b 1112 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2} // vpermt2b 1113 }; 1114 1115 if (ST->hasVBMI()) 1116 if (const auto *Entry = 1117 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1118 return LT.first * Entry->Cost; 1119 1120 static const CostTblEntry AVX512BWShuffleTbl[] = { 1121 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1122 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1123 1124 {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw 1125 {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw 1126 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1127 1128 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw 1129 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw 1130 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1131 1132 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w 1133 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w 1134 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2}, // vpermt2w 1135 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1136 1137 {TTI::SK_Select, MVT::v32i16, 1}, // vblendmw 1138 {TTI::SK_Select, MVT::v64i8, 1}, // vblendmb 1139 }; 1140 1141 if (ST->hasBWI()) 1142 if (const auto *Entry = 1143 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1144 return LT.first * Entry->Cost; 1145 1146 static const CostTblEntry AVX512ShuffleTbl[] = { 1147 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1148 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1149 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1150 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1151 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1152 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1153 1154 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1155 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1156 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1157 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1158 1159 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1160 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1161 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1162 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1163 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1164 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1165 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1166 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1167 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1168 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1169 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1170 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1171 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1172 1173 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1174 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1175 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1176 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1177 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1178 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1179 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1180 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1181 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1182 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1183 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1184 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1185 1186 // FIXME: This just applies the type legalization cost rules above 1187 // assuming these completely split. 1188 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1189 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1190 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1191 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1192 1193 {TTI::SK_Select, MVT::v32i16, 1}, // vpternlogq 1194 {TTI::SK_Select, MVT::v64i8, 1}, // vpternlogq 1195 {TTI::SK_Select, MVT::v8f64, 1}, // vblendmpd 1196 {TTI::SK_Select, MVT::v16f32, 1}, // vblendmps 1197 {TTI::SK_Select, MVT::v8i64, 1}, // vblendmq 1198 {TTI::SK_Select, MVT::v16i32, 1}, // vblendmd 1199 }; 1200 1201 if (ST->hasAVX512()) 1202 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1203 return LT.first * Entry->Cost; 1204 1205 static const CostTblEntry AVX2ShuffleTbl[] = { 1206 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1207 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1208 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1209 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1210 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1211 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1212 1213 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1214 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1215 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1216 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1217 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1218 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1219 1220 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1221 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1222 1223 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1224 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1225 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1226 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1227 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1228 // + vpblendvb 1229 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1230 // + vpblendvb 1231 1232 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1233 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1234 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1235 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1236 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1237 // + vpblendvb 1238 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1239 // + vpblendvb 1240 }; 1241 1242 if (ST->hasAVX2()) 1243 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1244 return LT.first * Entry->Cost; 1245 1246 static const CostTblEntry XOPShuffleTbl[] = { 1247 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1248 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1249 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1250 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1251 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1252 // + vinsertf128 1253 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1254 // + vinsertf128 1255 1256 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1257 // + vinsertf128 1258 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1259 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1260 // + vinsertf128 1261 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1262 }; 1263 1264 if (ST->hasXOP()) 1265 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1266 return LT.first * Entry->Cost; 1267 1268 static const CostTblEntry AVX1ShuffleTbl[] = { 1269 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1270 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1271 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1272 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1273 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1274 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1275 1276 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1277 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1278 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1279 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1280 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1281 // + vinsertf128 1282 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1283 // + vinsertf128 1284 1285 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1286 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1287 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1288 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1289 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1290 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1291 1292 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1293 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1294 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1295 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1296 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1297 // + 2*por + vinsertf128 1298 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1299 // + 2*por + vinsertf128 1300 1301 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1302 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1303 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1304 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1305 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1306 // + 4*por + vinsertf128 1307 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1308 // + 4*por + vinsertf128 1309 }; 1310 1311 if (ST->hasAVX()) 1312 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1313 return LT.first * Entry->Cost; 1314 1315 static const CostTblEntry SSE41ShuffleTbl[] = { 1316 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1317 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1318 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1319 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1320 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1321 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1322 }; 1323 1324 if (ST->hasSSE41()) 1325 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1326 return LT.first * Entry->Cost; 1327 1328 static const CostTblEntry SSSE3ShuffleTbl[] = { 1329 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1330 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1331 1332 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1333 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1334 1335 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1336 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1337 1338 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1339 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1340 1341 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1342 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1343 }; 1344 1345 if (ST->hasSSSE3()) 1346 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1347 return LT.first * Entry->Cost; 1348 1349 static const CostTblEntry SSE2ShuffleTbl[] = { 1350 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1351 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1352 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1353 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1354 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1355 1356 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1357 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1358 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1359 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1360 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1361 // + 2*pshufd + 2*unpck + packus 1362 1363 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1364 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1365 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1366 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1367 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1368 1369 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1370 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1371 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1372 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1373 // + pshufd/unpck 1374 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1375 // + 2*pshufd + 2*unpck + 2*packus 1376 1377 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1378 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1379 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1380 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1381 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1382 }; 1383 1384 if (ST->hasSSE2()) 1385 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1386 return LT.first * Entry->Cost; 1387 1388 static const CostTblEntry SSE1ShuffleTbl[] = { 1389 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1390 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1391 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1392 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1393 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1394 }; 1395 1396 if (ST->hasSSE1()) 1397 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1398 return LT.first * Entry->Cost; 1399 1400 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1401 } 1402 1403 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 1404 TTI::CastContextHint CCH, 1405 TTI::TargetCostKind CostKind, 1406 const Instruction *I) { 1407 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1408 assert(ISD && "Invalid opcode"); 1409 1410 // TODO: Allow non-throughput costs that aren't binary. 1411 auto AdjustCost = [&CostKind](int Cost) { 1412 if (CostKind != TTI::TCK_RecipThroughput) 1413 return Cost == 0 ? 0 : 1; 1414 return Cost; 1415 }; 1416 1417 // FIXME: Need a better design of the cost table to handle non-simple types of 1418 // potential massive combinations (elem_num x src_type x dst_type). 1419 1420 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1421 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1422 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1423 1424 // Mask sign extend has an instruction. 1425 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1426 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1427 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1428 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1429 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1430 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1431 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1432 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1433 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1434 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1435 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1436 1437 // Mask zero extend is a sext + shift. 1438 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1439 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1440 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1441 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1442 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1443 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1444 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1445 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1446 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1447 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1448 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1449 1450 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, 1451 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm 1452 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // widen to zmm 1453 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // widen to zmm 1454 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // widen to zmm 1455 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // widen to zmm 1456 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // widen to zmm 1457 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // widen to zmm 1458 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // widen to zmm 1459 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // widen to zmm 1460 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // widen to zmm 1461 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, 1462 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, 1463 }; 1464 1465 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1466 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1467 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1468 1469 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1470 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1471 1472 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1473 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1474 1475 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1476 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1477 }; 1478 1479 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1480 // 256-bit wide vectors. 1481 1482 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1483 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1484 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1485 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1486 1487 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1488 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1489 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1490 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd 1491 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1492 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1493 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1494 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd 1495 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd 1496 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd 1497 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd 1498 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd 1499 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq 1500 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq 1501 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq 1502 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, 1503 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, 1504 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, 1505 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, 1506 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 1507 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd 1508 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb 1509 1510 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32 1511 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, 1512 1513 // Sign extend is zmm vpternlogd+vptruncdb. 1514 // Zero extend is zmm broadcast load+vptruncdw. 1515 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 }, 1516 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 }, 1517 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, 1518 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, 1519 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, 1520 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, 1521 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 }, 1522 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 }, 1523 1524 // Sign extend is zmm vpternlogd+vptruncdw. 1525 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw. 1526 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 }, 1527 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1528 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 }, 1529 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1530 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 }, 1531 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1532 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 }, 1533 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1534 1535 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd 1536 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld 1537 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd 1538 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld 1539 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd 1540 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld 1541 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq 1542 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq 1543 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq 1544 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq 1545 1546 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd 1547 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld 1548 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq 1549 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq 1550 1551 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1552 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1553 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1554 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1555 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1556 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1557 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1558 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1559 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1560 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1561 1562 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1563 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1564 1565 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1566 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1567 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1568 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1569 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1570 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1571 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1572 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1573 1574 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1575 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1576 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1577 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1578 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1579 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1580 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1581 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1582 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1583 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1584 1585 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f64, 3 }, 1586 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, 1587 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 3 }, 1588 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 3 }, 1589 1590 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1591 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, 1592 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, 1593 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1594 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, 1595 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, 1596 }; 1597 1598 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1599 // Mask sign extend has an instruction. 1600 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1601 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1602 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1603 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1604 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1605 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1606 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1607 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1608 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1609 1610 // Mask zero extend is a sext + shift. 1611 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1612 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1613 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1614 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1615 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1616 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1617 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1618 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1619 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1620 1621 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, 1622 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // vpsllw+vptestmb 1623 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // vpsllw+vptestmw 1624 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // vpsllw+vptestmb 1625 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // vpsllw+vptestmw 1626 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // vpsllw+vptestmb 1627 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // vpsllw+vptestmw 1628 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // vpsllw+vptestmb 1629 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // vpsllw+vptestmw 1630 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // vpsllw+vptestmb 1631 }; 1632 1633 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1634 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1635 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1636 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1637 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1638 1639 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1640 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1641 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1642 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1643 1644 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1645 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1646 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1647 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1648 1649 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1650 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1651 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1652 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1653 }; 1654 1655 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 1656 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1657 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1658 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1659 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 8 }, // split+2*v8i8 1660 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1661 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1662 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1663 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16 1664 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // vpslld+vptestmd 1665 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd 1666 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // vpslld+vptestmd 1667 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // vpsllq+vptestmq 1668 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // vpsllq+vptestmq 1669 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // vpmovqd 1670 1671 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb 1672 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb 1673 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 }, 1674 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 }, 1675 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 }, 1676 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 }, 1677 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 }, 1678 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 }, 1679 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 }, 1680 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 }, 1681 1682 // sign extend is vpcmpeq+maskedmove+vpmovdw 1683 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw 1684 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1685 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 }, 1686 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1687 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 }, 1688 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1689 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 }, 1690 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 }, 1691 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 }, 1692 1693 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd 1694 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld 1695 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd 1696 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld 1697 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd 1698 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld 1699 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq 1700 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq 1701 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq 1702 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq 1703 1704 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1705 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1706 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1707 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1708 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1709 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1710 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1711 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1712 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1713 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1714 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1715 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1716 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1717 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1718 1719 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 1720 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1721 1722 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 3 }, 1723 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 3 }, 1724 1725 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 1726 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 1727 1728 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1729 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1730 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 1 }, 1731 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1732 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1733 }; 1734 1735 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1736 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1737 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1738 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1739 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1740 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1741 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1742 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1743 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1744 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1745 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1746 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1747 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1748 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1749 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1750 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1751 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1752 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1753 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1754 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1755 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1756 1757 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1758 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1759 1760 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 1761 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 1762 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 1763 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1764 1765 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1766 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1767 1768 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1769 }; 1770 1771 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1772 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1773 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1774 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1775 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1776 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1777 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1778 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1779 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1780 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1781 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1782 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1783 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1784 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 4 }, 1785 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1786 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1787 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1788 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1789 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1790 1791 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 4 }, 1792 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 5 }, 1793 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 4 }, 1794 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 9 }, 1795 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, 11 }, 1796 1797 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 1798 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1799 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1800 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1801 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 1802 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1803 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 11 }, 1804 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 9 }, 1805 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 }, 1806 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 11 }, 1807 1808 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1809 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1810 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1811 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1812 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1813 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1814 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1815 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1816 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1817 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1818 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1819 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1820 1821 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1822 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1823 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1824 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1825 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1826 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1827 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1828 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1829 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1830 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 }, 1831 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 1832 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1833 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 1834 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1835 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1836 // The generic code to compute the scalar overhead is currently broken. 1837 // Workaround this limitation by estimating the scalarization overhead 1838 // here. We have roughly 10 instructions per scalar element. 1839 // Multiply that by the vector width. 1840 // FIXME: remove that when PR19268 is fixed. 1841 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1842 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1843 1844 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 4 }, 1845 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f64, 3 }, 1846 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f64, 2 }, 1847 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 3 }, 1848 1849 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f64, 3 }, 1850 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f64, 2 }, 1851 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 4 }, 1852 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 3 }, 1853 // This node is expanded into scalarized operations but BasicTTI is overly 1854 // optimistic estimating its cost. It computes 3 per element (one 1855 // vector-extract, one scalar conversion and one vector-insert). The 1856 // problem is that the inserts form a read-modify-write chain so latency 1857 // should be factored in too. Inflating the cost per element by 1. 1858 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, 1859 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 1860 1861 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 1862 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 1863 }; 1864 1865 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 1866 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1867 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1868 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1869 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1870 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1871 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1872 1873 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1874 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 }, 1875 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1876 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1877 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1878 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1879 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1880 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1881 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1882 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1883 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1884 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1885 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1886 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1887 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1888 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1889 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1890 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1891 1892 // These truncates end up widening elements. 1893 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 1 }, // PMOVXZBQ 1894 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 1 }, // PMOVXZWQ 1895 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 1 }, // PMOVXZBD 1896 1897 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 1 }, 1898 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 1 }, 1899 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 1900 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 1901 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 1902 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 1903 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 1904 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 1905 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 1 }, // PSHUFB 1906 1907 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 1908 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 1909 1910 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 3 }, 1911 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 3 }, 1912 1913 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 3 }, 1914 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 3 }, 1915 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, 1916 }; 1917 1918 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 1919 // These are somewhat magic numbers justified by looking at the output of 1920 // Intel's IACA, running some kernels and making sure when we take 1921 // legalization into account the throughput will be overestimated. 1922 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1923 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1924 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1925 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1926 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1927 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 2*10 }, 1928 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2*10 }, 1929 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1930 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 1931 1932 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1933 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1934 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1935 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1936 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1937 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, 1938 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 }, 1939 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1940 1941 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 4 }, 1942 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 2 }, 1943 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, 1944 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, 1945 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, 1946 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 4 }, 1947 1948 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 1 }, 1949 1950 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 6 }, 1951 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 }, 1952 1953 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 1954 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 1955 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 4 }, 1956 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 4 }, 1957 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 }, 1958 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 2 }, 1959 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 }, 1960 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 4 }, 1961 1962 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1963 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 1964 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 1965 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 1966 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1967 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 1968 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1969 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 1970 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1971 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1972 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1973 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1974 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 1975 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 1976 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1977 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 1978 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1979 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 1980 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1981 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1982 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 1983 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 1984 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1985 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 1986 1987 // These truncates are really widening elements. 1988 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 1 }, // PSHUFD 1989 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // PUNPCKLWD+DQ 1990 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // PUNPCKLBW+WD+PSHUFD 1991 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 1 }, // PUNPCKLWD 1992 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // PUNPCKLBW+WD 1993 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 1 }, // PUNPCKLBW 1994 1995 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // PAND+PACKUSWB 1996 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // PAND+PACKUSWB 1997 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // PAND+PACKUSWB 1998 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 1999 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 3 }, // PAND+2*PACKUSWB 2000 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 2001 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 2002 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 2003 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 2004 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 2005 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2006 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 2007 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 2008 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 2009 { ISD::TRUNCATE, MVT::v2i32, MVT::v2i64, 1 }, // PSHUFD 2010 }; 2011 2012 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 2013 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst); 2014 2015 if (ST->hasSSE2() && !ST->hasAVX()) { 2016 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2017 LTDest.second, LTSrc.second)) 2018 return AdjustCost(LTSrc.first * Entry->Cost); 2019 } 2020 2021 EVT SrcTy = TLI->getValueType(DL, Src); 2022 EVT DstTy = TLI->getValueType(DL, Dst); 2023 2024 // The function getSimpleVT only handles simple value types. 2025 if (!SrcTy.isSimple() || !DstTy.isSimple()) 2026 return AdjustCost(BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind)); 2027 2028 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 2029 MVT SimpleDstTy = DstTy.getSimpleVT(); 2030 2031 if (ST->useAVX512Regs()) { 2032 if (ST->hasBWI()) 2033 if (const auto *Entry = ConvertCostTableLookup(AVX512BWConversionTbl, ISD, 2034 SimpleDstTy, SimpleSrcTy)) 2035 return AdjustCost(Entry->Cost); 2036 2037 if (ST->hasDQI()) 2038 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 2039 SimpleDstTy, SimpleSrcTy)) 2040 return AdjustCost(Entry->Cost); 2041 2042 if (ST->hasAVX512()) 2043 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 2044 SimpleDstTy, SimpleSrcTy)) 2045 return AdjustCost(Entry->Cost); 2046 } 2047 2048 if (ST->hasBWI()) 2049 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 2050 SimpleDstTy, SimpleSrcTy)) 2051 return AdjustCost(Entry->Cost); 2052 2053 if (ST->hasDQI()) 2054 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 2055 SimpleDstTy, SimpleSrcTy)) 2056 return AdjustCost(Entry->Cost); 2057 2058 if (ST->hasAVX512()) 2059 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2060 SimpleDstTy, SimpleSrcTy)) 2061 return AdjustCost(Entry->Cost); 2062 2063 if (ST->hasAVX2()) { 2064 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2065 SimpleDstTy, SimpleSrcTy)) 2066 return AdjustCost(Entry->Cost); 2067 } 2068 2069 if (ST->hasAVX()) { 2070 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2071 SimpleDstTy, SimpleSrcTy)) 2072 return AdjustCost(Entry->Cost); 2073 } 2074 2075 if (ST->hasSSE41()) { 2076 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2077 SimpleDstTy, SimpleSrcTy)) 2078 return AdjustCost(Entry->Cost); 2079 } 2080 2081 if (ST->hasSSE2()) { 2082 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2083 SimpleDstTy, SimpleSrcTy)) 2084 return AdjustCost(Entry->Cost); 2085 } 2086 2087 return AdjustCost( 2088 BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I)); 2089 } 2090 2091 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 2092 CmpInst::Predicate VecPred, 2093 TTI::TargetCostKind CostKind, 2094 const Instruction *I) { 2095 // TODO: Handle other cost kinds. 2096 if (CostKind != TTI::TCK_RecipThroughput) 2097 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, 2098 I); 2099 2100 // Legalize the type. 2101 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2102 2103 MVT MTy = LT.second; 2104 2105 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2106 assert(ISD && "Invalid opcode"); 2107 2108 unsigned ExtraCost = 0; 2109 if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) { 2110 // Some vector comparison predicates cost extra instructions. 2111 if (MTy.isVector() && 2112 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 2113 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 2114 ST->hasBWI())) { 2115 switch (cast<CmpInst>(I)->getPredicate()) { 2116 case CmpInst::Predicate::ICMP_NE: 2117 // xor(cmpeq(x,y),-1) 2118 ExtraCost = 1; 2119 break; 2120 case CmpInst::Predicate::ICMP_SGE: 2121 case CmpInst::Predicate::ICMP_SLE: 2122 // xor(cmpgt(x,y),-1) 2123 ExtraCost = 1; 2124 break; 2125 case CmpInst::Predicate::ICMP_ULT: 2126 case CmpInst::Predicate::ICMP_UGT: 2127 // cmpgt(xor(x,signbit),xor(y,signbit)) 2128 // xor(cmpeq(pmaxu(x,y),x),-1) 2129 ExtraCost = 2; 2130 break; 2131 case CmpInst::Predicate::ICMP_ULE: 2132 case CmpInst::Predicate::ICMP_UGE: 2133 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 2134 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 2135 // cmpeq(psubus(x,y),0) 2136 // cmpeq(pminu(x,y),x) 2137 ExtraCost = 1; 2138 } else { 2139 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 2140 ExtraCost = 3; 2141 } 2142 break; 2143 default: 2144 break; 2145 } 2146 } 2147 } 2148 2149 static const CostTblEntry SLMCostTbl[] = { 2150 // slm pcmpeq/pcmpgt throughput is 2 2151 { ISD::SETCC, MVT::v2i64, 2 }, 2152 }; 2153 2154 static const CostTblEntry AVX512BWCostTbl[] = { 2155 { ISD::SETCC, MVT::v32i16, 1 }, 2156 { ISD::SETCC, MVT::v64i8, 1 }, 2157 2158 { ISD::SELECT, MVT::v32i16, 1 }, 2159 { ISD::SELECT, MVT::v64i8, 1 }, 2160 }; 2161 2162 static const CostTblEntry AVX512CostTbl[] = { 2163 { ISD::SETCC, MVT::v8i64, 1 }, 2164 { ISD::SETCC, MVT::v16i32, 1 }, 2165 { ISD::SETCC, MVT::v8f64, 1 }, 2166 { ISD::SETCC, MVT::v16f32, 1 }, 2167 2168 { ISD::SELECT, MVT::v8i64, 1 }, 2169 { ISD::SELECT, MVT::v16i32, 1 }, 2170 { ISD::SELECT, MVT::v8f64, 1 }, 2171 { ISD::SELECT, MVT::v16f32, 1 }, 2172 2173 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 2174 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 2175 2176 { ISD::SELECT, MVT::v32i16, 2 }, // FIXME: should be 3 2177 { ISD::SELECT, MVT::v64i8, 2 }, // FIXME: should be 3 2178 }; 2179 2180 static const CostTblEntry AVX2CostTbl[] = { 2181 { ISD::SETCC, MVT::v4i64, 1 }, 2182 { ISD::SETCC, MVT::v8i32, 1 }, 2183 { ISD::SETCC, MVT::v16i16, 1 }, 2184 { ISD::SETCC, MVT::v32i8, 1 }, 2185 2186 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 2187 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 2188 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 2189 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 2190 }; 2191 2192 static const CostTblEntry AVX1CostTbl[] = { 2193 { ISD::SETCC, MVT::v4f64, 1 }, 2194 { ISD::SETCC, MVT::v8f32, 1 }, 2195 // AVX1 does not support 8-wide integer compare. 2196 { ISD::SETCC, MVT::v4i64, 4 }, 2197 { ISD::SETCC, MVT::v8i32, 4 }, 2198 { ISD::SETCC, MVT::v16i16, 4 }, 2199 { ISD::SETCC, MVT::v32i8, 4 }, 2200 2201 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 2202 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 2203 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 2204 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 2205 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 2206 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 2207 }; 2208 2209 static const CostTblEntry SSE42CostTbl[] = { 2210 { ISD::SETCC, MVT::v2f64, 1 }, 2211 { ISD::SETCC, MVT::v4f32, 1 }, 2212 { ISD::SETCC, MVT::v2i64, 1 }, 2213 }; 2214 2215 static const CostTblEntry SSE41CostTbl[] = { 2216 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 2217 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 2218 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 2219 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 2220 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 2221 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 2222 }; 2223 2224 static const CostTblEntry SSE2CostTbl[] = { 2225 { ISD::SETCC, MVT::v2f64, 2 }, 2226 { ISD::SETCC, MVT::f64, 1 }, 2227 { ISD::SETCC, MVT::v2i64, 8 }, 2228 { ISD::SETCC, MVT::v4i32, 1 }, 2229 { ISD::SETCC, MVT::v8i16, 1 }, 2230 { ISD::SETCC, MVT::v16i8, 1 }, 2231 2232 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 2233 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 2234 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 2235 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 2236 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 2237 }; 2238 2239 static const CostTblEntry SSE1CostTbl[] = { 2240 { ISD::SETCC, MVT::v4f32, 2 }, 2241 { ISD::SETCC, MVT::f32, 1 }, 2242 2243 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 2244 }; 2245 2246 if (ST->isSLM()) 2247 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2248 return LT.first * (ExtraCost + Entry->Cost); 2249 2250 if (ST->hasBWI()) 2251 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2252 return LT.first * (ExtraCost + Entry->Cost); 2253 2254 if (ST->hasAVX512()) 2255 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2256 return LT.first * (ExtraCost + Entry->Cost); 2257 2258 if (ST->hasAVX2()) 2259 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2260 return LT.first * (ExtraCost + Entry->Cost); 2261 2262 if (ST->hasAVX()) 2263 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2264 return LT.first * (ExtraCost + Entry->Cost); 2265 2266 if (ST->hasSSE42()) 2267 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2268 return LT.first * (ExtraCost + Entry->Cost); 2269 2270 if (ST->hasSSE41()) 2271 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2272 return LT.first * (ExtraCost + Entry->Cost); 2273 2274 if (ST->hasSSE2()) 2275 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2276 return LT.first * (ExtraCost + Entry->Cost); 2277 2278 if (ST->hasSSE1()) 2279 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2280 return LT.first * (ExtraCost + Entry->Cost); 2281 2282 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I); 2283 } 2284 2285 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2286 2287 int X86TTIImpl::getTypeBasedIntrinsicInstrCost( 2288 const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) { 2289 2290 // Costs should match the codegen from: 2291 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2292 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2293 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2294 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2295 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2296 2297 // TODO: Overflow intrinsics (*ADDO, *SUBO, *MULO) with vector types are not 2298 // specialized in these tables yet. 2299 static const CostTblEntry AVX512CDCostTbl[] = { 2300 { ISD::CTLZ, MVT::v8i64, 1 }, 2301 { ISD::CTLZ, MVT::v16i32, 1 }, 2302 { ISD::CTLZ, MVT::v32i16, 8 }, 2303 { ISD::CTLZ, MVT::v64i8, 20 }, 2304 { ISD::CTLZ, MVT::v4i64, 1 }, 2305 { ISD::CTLZ, MVT::v8i32, 1 }, 2306 { ISD::CTLZ, MVT::v16i16, 4 }, 2307 { ISD::CTLZ, MVT::v32i8, 10 }, 2308 { ISD::CTLZ, MVT::v2i64, 1 }, 2309 { ISD::CTLZ, MVT::v4i32, 1 }, 2310 { ISD::CTLZ, MVT::v8i16, 4 }, 2311 { ISD::CTLZ, MVT::v16i8, 4 }, 2312 }; 2313 static const CostTblEntry AVX512BWCostTbl[] = { 2314 { ISD::ABS, MVT::v32i16, 1 }, 2315 { ISD::ABS, MVT::v64i8, 1 }, 2316 { ISD::BITREVERSE, MVT::v8i64, 5 }, 2317 { ISD::BITREVERSE, MVT::v16i32, 5 }, 2318 { ISD::BITREVERSE, MVT::v32i16, 5 }, 2319 { ISD::BITREVERSE, MVT::v64i8, 5 }, 2320 { ISD::CTLZ, MVT::v8i64, 23 }, 2321 { ISD::CTLZ, MVT::v16i32, 22 }, 2322 { ISD::CTLZ, MVT::v32i16, 18 }, 2323 { ISD::CTLZ, MVT::v64i8, 17 }, 2324 { ISD::CTPOP, MVT::v8i64, 7 }, 2325 { ISD::CTPOP, MVT::v16i32, 11 }, 2326 { ISD::CTPOP, MVT::v32i16, 9 }, 2327 { ISD::CTPOP, MVT::v64i8, 6 }, 2328 { ISD::CTTZ, MVT::v8i64, 10 }, 2329 { ISD::CTTZ, MVT::v16i32, 14 }, 2330 { ISD::CTTZ, MVT::v32i16, 12 }, 2331 { ISD::CTTZ, MVT::v64i8, 9 }, 2332 { ISD::SADDSAT, MVT::v32i16, 1 }, 2333 { ISD::SADDSAT, MVT::v64i8, 1 }, 2334 { ISD::SMAX, MVT::v32i16, 1 }, 2335 { ISD::SMAX, MVT::v64i8, 1 }, 2336 { ISD::SMIN, MVT::v32i16, 1 }, 2337 { ISD::SMIN, MVT::v64i8, 1 }, 2338 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2339 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2340 { ISD::UADDSAT, MVT::v32i16, 1 }, 2341 { ISD::UADDSAT, MVT::v64i8, 1 }, 2342 { ISD::UMAX, MVT::v32i16, 1 }, 2343 { ISD::UMAX, MVT::v64i8, 1 }, 2344 { ISD::UMIN, MVT::v32i16, 1 }, 2345 { ISD::UMIN, MVT::v64i8, 1 }, 2346 { ISD::USUBSAT, MVT::v32i16, 1 }, 2347 { ISD::USUBSAT, MVT::v64i8, 1 }, 2348 }; 2349 static const CostTblEntry AVX512CostTbl[] = { 2350 { ISD::ABS, MVT::v8i64, 1 }, 2351 { ISD::ABS, MVT::v16i32, 1 }, 2352 { ISD::ABS, MVT::v32i16, 2 }, // FIXME: include split 2353 { ISD::ABS, MVT::v64i8, 2 }, // FIXME: include split 2354 { ISD::ABS, MVT::v4i64, 1 }, 2355 { ISD::ABS, MVT::v2i64, 1 }, 2356 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2357 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2358 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2359 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2360 { ISD::CTLZ, MVT::v8i64, 29 }, 2361 { ISD::CTLZ, MVT::v16i32, 35 }, 2362 { ISD::CTLZ, MVT::v32i16, 28 }, 2363 { ISD::CTLZ, MVT::v64i8, 18 }, 2364 { ISD::CTPOP, MVT::v8i64, 16 }, 2365 { ISD::CTPOP, MVT::v16i32, 24 }, 2366 { ISD::CTPOP, MVT::v32i16, 18 }, 2367 { ISD::CTPOP, MVT::v64i8, 12 }, 2368 { ISD::CTTZ, MVT::v8i64, 20 }, 2369 { ISD::CTTZ, MVT::v16i32, 28 }, 2370 { ISD::CTTZ, MVT::v32i16, 24 }, 2371 { ISD::CTTZ, MVT::v64i8, 18 }, 2372 { ISD::SMAX, MVT::v8i64, 1 }, 2373 { ISD::SMAX, MVT::v16i32, 1 }, 2374 { ISD::SMAX, MVT::v32i16, 2 }, // FIXME: include split 2375 { ISD::SMAX, MVT::v64i8, 2 }, // FIXME: include split 2376 { ISD::SMAX, MVT::v4i64, 1 }, 2377 { ISD::SMAX, MVT::v2i64, 1 }, 2378 { ISD::SMIN, MVT::v8i64, 1 }, 2379 { ISD::SMIN, MVT::v16i32, 1 }, 2380 { ISD::SMIN, MVT::v32i16, 2 }, // FIXME: include split 2381 { ISD::SMIN, MVT::v64i8, 2 }, // FIXME: include split 2382 { ISD::SMIN, MVT::v4i64, 1 }, 2383 { ISD::SMIN, MVT::v2i64, 1 }, 2384 { ISD::UMAX, MVT::v8i64, 1 }, 2385 { ISD::UMAX, MVT::v16i32, 1 }, 2386 { ISD::UMAX, MVT::v32i16, 2 }, // FIXME: include split 2387 { ISD::UMAX, MVT::v64i8, 2 }, // FIXME: include split 2388 { ISD::UMAX, MVT::v4i64, 1 }, 2389 { ISD::UMAX, MVT::v2i64, 1 }, 2390 { ISD::UMIN, MVT::v8i64, 1 }, 2391 { ISD::UMIN, MVT::v16i32, 1 }, 2392 { ISD::UMIN, MVT::v32i16, 2 }, // FIXME: include split 2393 { ISD::UMIN, MVT::v64i8, 2 }, // FIXME: include split 2394 { ISD::UMIN, MVT::v4i64, 1 }, 2395 { ISD::UMIN, MVT::v2i64, 1 }, 2396 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2397 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2398 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2399 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2400 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2401 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2402 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2403 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2404 { ISD::SADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2405 { ISD::SADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2406 { ISD::SSUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2407 { ISD::SSUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2408 { ISD::UADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2409 { ISD::UADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2410 { ISD::USUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2411 { ISD::USUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2412 { ISD::FMAXNUM, MVT::f32, 2 }, 2413 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2414 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2415 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2416 { ISD::FMAXNUM, MVT::f64, 2 }, 2417 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2418 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2419 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2420 }; 2421 static const CostTblEntry XOPCostTbl[] = { 2422 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2423 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2424 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2425 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2426 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2427 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2428 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2429 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2430 { ISD::BITREVERSE, MVT::i64, 3 }, 2431 { ISD::BITREVERSE, MVT::i32, 3 }, 2432 { ISD::BITREVERSE, MVT::i16, 3 }, 2433 { ISD::BITREVERSE, MVT::i8, 3 } 2434 }; 2435 static const CostTblEntry AVX2CostTbl[] = { 2436 { ISD::ABS, MVT::v4i64, 2 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2437 { ISD::ABS, MVT::v8i32, 1 }, 2438 { ISD::ABS, MVT::v16i16, 1 }, 2439 { ISD::ABS, MVT::v32i8, 1 }, 2440 { ISD::BITREVERSE, MVT::v4i64, 5 }, 2441 { ISD::BITREVERSE, MVT::v8i32, 5 }, 2442 { ISD::BITREVERSE, MVT::v16i16, 5 }, 2443 { ISD::BITREVERSE, MVT::v32i8, 5 }, 2444 { ISD::BSWAP, MVT::v4i64, 1 }, 2445 { ISD::BSWAP, MVT::v8i32, 1 }, 2446 { ISD::BSWAP, MVT::v16i16, 1 }, 2447 { ISD::CTLZ, MVT::v4i64, 23 }, 2448 { ISD::CTLZ, MVT::v8i32, 18 }, 2449 { ISD::CTLZ, MVT::v16i16, 14 }, 2450 { ISD::CTLZ, MVT::v32i8, 9 }, 2451 { ISD::CTPOP, MVT::v4i64, 7 }, 2452 { ISD::CTPOP, MVT::v8i32, 11 }, 2453 { ISD::CTPOP, MVT::v16i16, 9 }, 2454 { ISD::CTPOP, MVT::v32i8, 6 }, 2455 { ISD::CTTZ, MVT::v4i64, 10 }, 2456 { ISD::CTTZ, MVT::v8i32, 14 }, 2457 { ISD::CTTZ, MVT::v16i16, 12 }, 2458 { ISD::CTTZ, MVT::v32i8, 9 }, 2459 { ISD::SADDSAT, MVT::v16i16, 1 }, 2460 { ISD::SADDSAT, MVT::v32i8, 1 }, 2461 { ISD::SMAX, MVT::v8i32, 1 }, 2462 { ISD::SMAX, MVT::v16i16, 1 }, 2463 { ISD::SMAX, MVT::v32i8, 1 }, 2464 { ISD::SMIN, MVT::v8i32, 1 }, 2465 { ISD::SMIN, MVT::v16i16, 1 }, 2466 { ISD::SMIN, MVT::v32i8, 1 }, 2467 { ISD::SSUBSAT, MVT::v16i16, 1 }, 2468 { ISD::SSUBSAT, MVT::v32i8, 1 }, 2469 { ISD::UADDSAT, MVT::v16i16, 1 }, 2470 { ISD::UADDSAT, MVT::v32i8, 1 }, 2471 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 2472 { ISD::UMAX, MVT::v8i32, 1 }, 2473 { ISD::UMAX, MVT::v16i16, 1 }, 2474 { ISD::UMAX, MVT::v32i8, 1 }, 2475 { ISD::UMIN, MVT::v8i32, 1 }, 2476 { ISD::UMIN, MVT::v16i16, 1 }, 2477 { ISD::UMIN, MVT::v32i8, 1 }, 2478 { ISD::USUBSAT, MVT::v16i16, 1 }, 2479 { ISD::USUBSAT, MVT::v32i8, 1 }, 2480 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2481 { ISD::FMAXNUM, MVT::v8f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2482 { ISD::FMAXNUM, MVT::v4f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2483 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2484 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2485 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2486 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2487 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2488 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2489 }; 2490 static const CostTblEntry AVX1CostTbl[] = { 2491 { ISD::ABS, MVT::v4i64, 5 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2492 { ISD::ABS, MVT::v8i32, 3 }, 2493 { ISD::ABS, MVT::v16i16, 3 }, 2494 { ISD::ABS, MVT::v32i8, 3 }, 2495 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 2496 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 2497 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 2498 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 2499 { ISD::BSWAP, MVT::v4i64, 4 }, 2500 { ISD::BSWAP, MVT::v8i32, 4 }, 2501 { ISD::BSWAP, MVT::v16i16, 4 }, 2502 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 2503 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 2504 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 2505 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2506 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 2507 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 2508 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 2509 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 2510 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 2511 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 2512 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 2513 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2514 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2515 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2516 { ISD::SMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2517 { ISD::SMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2518 { ISD::SMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2519 { ISD::SMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2520 { ISD::SMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2521 { ISD::SMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2522 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2523 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2524 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2525 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2526 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 2527 { ISD::UMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2528 { ISD::UMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2529 { ISD::UMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2530 { ISD::UMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2531 { ISD::UMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2532 { ISD::UMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2533 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2534 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2535 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 2536 { ISD::FMAXNUM, MVT::f32, 3 }, // MAXSS + CMPUNORDSS + BLENDVPS 2537 { ISD::FMAXNUM, MVT::v4f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2538 { ISD::FMAXNUM, MVT::v8f32, 5 }, // MAXPS + CMPUNORDPS + BLENDVPS + ? 2539 { ISD::FMAXNUM, MVT::f64, 3 }, // MAXSD + CMPUNORDSD + BLENDVPD 2540 { ISD::FMAXNUM, MVT::v2f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2541 { ISD::FMAXNUM, MVT::v4f64, 5 }, // MAXPD + CMPUNORDPD + BLENDVPD + ? 2542 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 2543 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 2544 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 2545 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 2546 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 2547 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 2548 }; 2549 static const CostTblEntry GLMCostTbl[] = { 2550 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 2551 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 2552 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 2553 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 2554 }; 2555 static const CostTblEntry SLMCostTbl[] = { 2556 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 2557 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 2558 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 2559 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 2560 }; 2561 static const CostTblEntry SSE42CostTbl[] = { 2562 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 2563 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 2564 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 2565 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 2566 }; 2567 static const CostTblEntry SSE41CostTbl[] = { 2568 { ISD::ABS, MVT::v2i64, 2 }, // BLENDVPD(X,PSUBQ(0,X),X) 2569 { ISD::SMAX, MVT::v4i32, 1 }, 2570 { ISD::SMAX, MVT::v16i8, 1 }, 2571 { ISD::SMIN, MVT::v4i32, 1 }, 2572 { ISD::SMIN, MVT::v16i8, 1 }, 2573 { ISD::UMAX, MVT::v4i32, 1 }, 2574 { ISD::UMAX, MVT::v8i16, 1 }, 2575 { ISD::UMIN, MVT::v4i32, 1 }, 2576 { ISD::UMIN, MVT::v8i16, 1 }, 2577 }; 2578 static const CostTblEntry SSSE3CostTbl[] = { 2579 { ISD::ABS, MVT::v4i32, 1 }, 2580 { ISD::ABS, MVT::v8i16, 1 }, 2581 { ISD::ABS, MVT::v16i8, 1 }, 2582 { ISD::BITREVERSE, MVT::v2i64, 5 }, 2583 { ISD::BITREVERSE, MVT::v4i32, 5 }, 2584 { ISD::BITREVERSE, MVT::v8i16, 5 }, 2585 { ISD::BITREVERSE, MVT::v16i8, 5 }, 2586 { ISD::BSWAP, MVT::v2i64, 1 }, 2587 { ISD::BSWAP, MVT::v4i32, 1 }, 2588 { ISD::BSWAP, MVT::v8i16, 1 }, 2589 { ISD::CTLZ, MVT::v2i64, 23 }, 2590 { ISD::CTLZ, MVT::v4i32, 18 }, 2591 { ISD::CTLZ, MVT::v8i16, 14 }, 2592 { ISD::CTLZ, MVT::v16i8, 9 }, 2593 { ISD::CTPOP, MVT::v2i64, 7 }, 2594 { ISD::CTPOP, MVT::v4i32, 11 }, 2595 { ISD::CTPOP, MVT::v8i16, 9 }, 2596 { ISD::CTPOP, MVT::v16i8, 6 }, 2597 { ISD::CTTZ, MVT::v2i64, 10 }, 2598 { ISD::CTTZ, MVT::v4i32, 14 }, 2599 { ISD::CTTZ, MVT::v8i16, 12 }, 2600 { ISD::CTTZ, MVT::v16i8, 9 } 2601 }; 2602 static const CostTblEntry SSE2CostTbl[] = { 2603 { ISD::ABS, MVT::v2i64, 4 }, 2604 { ISD::ABS, MVT::v4i32, 3 }, 2605 { ISD::ABS, MVT::v8i16, 2 }, 2606 { ISD::ABS, MVT::v16i8, 2 }, 2607 { ISD::BITREVERSE, MVT::v2i64, 29 }, 2608 { ISD::BITREVERSE, MVT::v4i32, 27 }, 2609 { ISD::BITREVERSE, MVT::v8i16, 27 }, 2610 { ISD::BITREVERSE, MVT::v16i8, 20 }, 2611 { ISD::BSWAP, MVT::v2i64, 7 }, 2612 { ISD::BSWAP, MVT::v4i32, 7 }, 2613 { ISD::BSWAP, MVT::v8i16, 7 }, 2614 { ISD::CTLZ, MVT::v2i64, 25 }, 2615 { ISD::CTLZ, MVT::v4i32, 26 }, 2616 { ISD::CTLZ, MVT::v8i16, 20 }, 2617 { ISD::CTLZ, MVT::v16i8, 17 }, 2618 { ISD::CTPOP, MVT::v2i64, 12 }, 2619 { ISD::CTPOP, MVT::v4i32, 15 }, 2620 { ISD::CTPOP, MVT::v8i16, 13 }, 2621 { ISD::CTPOP, MVT::v16i8, 10 }, 2622 { ISD::CTTZ, MVT::v2i64, 14 }, 2623 { ISD::CTTZ, MVT::v4i32, 18 }, 2624 { ISD::CTTZ, MVT::v8i16, 16 }, 2625 { ISD::CTTZ, MVT::v16i8, 13 }, 2626 { ISD::SADDSAT, MVT::v8i16, 1 }, 2627 { ISD::SADDSAT, MVT::v16i8, 1 }, 2628 { ISD::SMAX, MVT::v8i16, 1 }, 2629 { ISD::SMIN, MVT::v8i16, 1 }, 2630 { ISD::SSUBSAT, MVT::v8i16, 1 }, 2631 { ISD::SSUBSAT, MVT::v16i8, 1 }, 2632 { ISD::UADDSAT, MVT::v8i16, 1 }, 2633 { ISD::UADDSAT, MVT::v16i8, 1 }, 2634 { ISD::UMAX, MVT::v8i16, 2 }, 2635 { ISD::UMAX, MVT::v16i8, 1 }, 2636 { ISD::UMIN, MVT::v8i16, 2 }, 2637 { ISD::UMIN, MVT::v16i8, 1 }, 2638 { ISD::USUBSAT, MVT::v8i16, 1 }, 2639 { ISD::USUBSAT, MVT::v16i8, 1 }, 2640 { ISD::FMAXNUM, MVT::f64, 4 }, 2641 { ISD::FMAXNUM, MVT::v2f64, 4 }, 2642 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 2643 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 2644 }; 2645 static const CostTblEntry SSE1CostTbl[] = { 2646 { ISD::FMAXNUM, MVT::f32, 4 }, 2647 { ISD::FMAXNUM, MVT::v4f32, 4 }, 2648 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 2649 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 2650 }; 2651 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 2652 { ISD::CTTZ, MVT::i64, 1 }, 2653 }; 2654 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 2655 { ISD::CTTZ, MVT::i32, 1 }, 2656 { ISD::CTTZ, MVT::i16, 1 }, 2657 { ISD::CTTZ, MVT::i8, 1 }, 2658 }; 2659 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 2660 { ISD::CTLZ, MVT::i64, 1 }, 2661 }; 2662 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 2663 { ISD::CTLZ, MVT::i32, 1 }, 2664 { ISD::CTLZ, MVT::i16, 1 }, 2665 { ISD::CTLZ, MVT::i8, 1 }, 2666 }; 2667 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 2668 { ISD::CTPOP, MVT::i64, 1 }, 2669 }; 2670 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 2671 { ISD::CTPOP, MVT::i32, 1 }, 2672 { ISD::CTPOP, MVT::i16, 1 }, 2673 { ISD::CTPOP, MVT::i8, 1 }, 2674 }; 2675 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2676 { ISD::ABS, MVT::i64, 2 }, // SUB+CMOV 2677 { ISD::BITREVERSE, MVT::i64, 14 }, 2678 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 2679 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 2680 { ISD::CTPOP, MVT::i64, 10 }, 2681 { ISD::SADDO, MVT::i64, 1 }, 2682 { ISD::UADDO, MVT::i64, 1 }, 2683 { ISD::UMULO, MVT::i64, 2 }, // mulq + seto 2684 }; 2685 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2686 { ISD::ABS, MVT::i32, 2 }, // SUB+CMOV 2687 { ISD::ABS, MVT::i16, 2 }, // SUB+CMOV 2688 { ISD::BITREVERSE, MVT::i32, 14 }, 2689 { ISD::BITREVERSE, MVT::i16, 14 }, 2690 { ISD::BITREVERSE, MVT::i8, 11 }, 2691 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 2692 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 2693 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 2694 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 2695 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 2696 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 2697 { ISD::CTPOP, MVT::i32, 8 }, 2698 { ISD::CTPOP, MVT::i16, 9 }, 2699 { ISD::CTPOP, MVT::i8, 7 }, 2700 { ISD::SADDO, MVT::i32, 1 }, 2701 { ISD::SADDO, MVT::i16, 1 }, 2702 { ISD::SADDO, MVT::i8, 1 }, 2703 { ISD::UADDO, MVT::i32, 1 }, 2704 { ISD::UADDO, MVT::i16, 1 }, 2705 { ISD::UADDO, MVT::i8, 1 }, 2706 { ISD::UMULO, MVT::i32, 2 }, // mul + seto 2707 { ISD::UMULO, MVT::i16, 2 }, 2708 { ISD::UMULO, MVT::i8, 2 }, 2709 }; 2710 2711 Type *RetTy = ICA.getReturnType(); 2712 Type *OpTy = RetTy; 2713 Intrinsic::ID IID = ICA.getID(); 2714 unsigned ISD = ISD::DELETED_NODE; 2715 switch (IID) { 2716 default: 2717 break; 2718 case Intrinsic::abs: 2719 ISD = ISD::ABS; 2720 break; 2721 case Intrinsic::bitreverse: 2722 ISD = ISD::BITREVERSE; 2723 break; 2724 case Intrinsic::bswap: 2725 ISD = ISD::BSWAP; 2726 break; 2727 case Intrinsic::ctlz: 2728 ISD = ISD::CTLZ; 2729 break; 2730 case Intrinsic::ctpop: 2731 ISD = ISD::CTPOP; 2732 break; 2733 case Intrinsic::cttz: 2734 ISD = ISD::CTTZ; 2735 break; 2736 case Intrinsic::maxnum: 2737 case Intrinsic::minnum: 2738 // FMINNUM has same costs so don't duplicate. 2739 ISD = ISD::FMAXNUM; 2740 break; 2741 case Intrinsic::sadd_sat: 2742 ISD = ISD::SADDSAT; 2743 break; 2744 case Intrinsic::smax: 2745 ISD = ISD::SMAX; 2746 break; 2747 case Intrinsic::smin: 2748 ISD = ISD::SMIN; 2749 break; 2750 case Intrinsic::ssub_sat: 2751 ISD = ISD::SSUBSAT; 2752 break; 2753 case Intrinsic::uadd_sat: 2754 ISD = ISD::UADDSAT; 2755 break; 2756 case Intrinsic::umax: 2757 ISD = ISD::UMAX; 2758 break; 2759 case Intrinsic::umin: 2760 ISD = ISD::UMIN; 2761 break; 2762 case Intrinsic::usub_sat: 2763 ISD = ISD::USUBSAT; 2764 break; 2765 case Intrinsic::sqrt: 2766 ISD = ISD::FSQRT; 2767 break; 2768 case Intrinsic::sadd_with_overflow: 2769 case Intrinsic::ssub_with_overflow: 2770 // SSUBO has same costs so don't duplicate. 2771 ISD = ISD::SADDO; 2772 OpTy = RetTy->getContainedType(0); 2773 break; 2774 case Intrinsic::uadd_with_overflow: 2775 case Intrinsic::usub_with_overflow: 2776 // USUBO has same costs so don't duplicate. 2777 ISD = ISD::UADDO; 2778 OpTy = RetTy->getContainedType(0); 2779 break; 2780 case Intrinsic::umul_with_overflow: 2781 case Intrinsic::smul_with_overflow: 2782 // SMULO has same costs so don't duplicate. 2783 ISD = ISD::UMULO; 2784 OpTy = RetTy->getContainedType(0); 2785 break; 2786 } 2787 2788 if (ISD != ISD::DELETED_NODE) { 2789 // Legalize the type. 2790 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 2791 MVT MTy = LT.second; 2792 2793 // Attempt to lookup cost. 2794 if (ISD == ISD::BITREVERSE && ST->hasGFNI() && ST->hasSSSE3() && 2795 MTy.isVector()) { 2796 // With PSHUFB the code is very similar for all types. If we have integer 2797 // byte operations, we just need a GF2P8AFFINEQB for vXi8. For other types 2798 // we also need a PSHUFB. 2799 unsigned Cost = MTy.getVectorElementType() == MVT::i8 ? 1 : 2; 2800 2801 // Without byte operations, we need twice as many GF2P8AFFINEQB and PSHUFB 2802 // instructions. We also need an extract and an insert. 2803 if (!(MTy.is128BitVector() || (ST->hasAVX2() && MTy.is256BitVector()) || 2804 (ST->hasBWI() && MTy.is512BitVector()))) 2805 Cost = Cost * 2 + 2; 2806 2807 return LT.first * Cost; 2808 } 2809 2810 auto adjustTableCost = [](const CostTblEntry &Entry, int LegalizationCost, 2811 FastMathFlags FMF) { 2812 // If there are no NANs to deal with, then these are reduced to a 2813 // single MIN** or MAX** instruction instead of the MIN/CMP/SELECT that we 2814 // assume is used in the non-fast case. 2815 if (Entry.ISD == ISD::FMAXNUM || Entry.ISD == ISD::FMINNUM) { 2816 if (FMF.noNaNs()) 2817 return LegalizationCost * 1; 2818 } 2819 return LegalizationCost * (int)Entry.Cost; 2820 }; 2821 2822 if (ST->useGLMDivSqrtCosts()) 2823 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 2824 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2825 2826 if (ST->isSLM()) 2827 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2828 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2829 2830 if (ST->hasCDI()) 2831 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 2832 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2833 2834 if (ST->hasBWI()) 2835 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2836 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2837 2838 if (ST->hasAVX512()) 2839 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2840 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2841 2842 if (ST->hasXOP()) 2843 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2844 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2845 2846 if (ST->hasAVX2()) 2847 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2848 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2849 2850 if (ST->hasAVX()) 2851 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2852 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2853 2854 if (ST->hasSSE42()) 2855 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2856 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2857 2858 if (ST->hasSSE41()) 2859 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2860 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2861 2862 if (ST->hasSSSE3()) 2863 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 2864 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2865 2866 if (ST->hasSSE2()) 2867 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2868 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2869 2870 if (ST->hasSSE1()) 2871 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2872 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2873 2874 if (ST->hasBMI()) { 2875 if (ST->is64Bit()) 2876 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 2877 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2878 2879 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 2880 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2881 } 2882 2883 if (ST->hasLZCNT()) { 2884 if (ST->is64Bit()) 2885 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 2886 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2887 2888 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 2889 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2890 } 2891 2892 if (ST->hasPOPCNT()) { 2893 if (ST->is64Bit()) 2894 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 2895 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2896 2897 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 2898 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2899 } 2900 2901 // TODO - add BMI (TZCNT) scalar handling 2902 2903 if (ST->is64Bit()) 2904 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2905 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2906 2907 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2908 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2909 } 2910 2911 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 2912 } 2913 2914 int X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 2915 TTI::TargetCostKind CostKind) { 2916 if (ICA.isTypeBasedOnly()) 2917 return getTypeBasedIntrinsicInstrCost(ICA, CostKind); 2918 2919 static const CostTblEntry AVX512CostTbl[] = { 2920 { ISD::ROTL, MVT::v8i64, 1 }, 2921 { ISD::ROTL, MVT::v4i64, 1 }, 2922 { ISD::ROTL, MVT::v2i64, 1 }, 2923 { ISD::ROTL, MVT::v16i32, 1 }, 2924 { ISD::ROTL, MVT::v8i32, 1 }, 2925 { ISD::ROTL, MVT::v4i32, 1 }, 2926 { ISD::ROTR, MVT::v8i64, 1 }, 2927 { ISD::ROTR, MVT::v4i64, 1 }, 2928 { ISD::ROTR, MVT::v2i64, 1 }, 2929 { ISD::ROTR, MVT::v16i32, 1 }, 2930 { ISD::ROTR, MVT::v8i32, 1 }, 2931 { ISD::ROTR, MVT::v4i32, 1 } 2932 }; 2933 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 2934 static const CostTblEntry XOPCostTbl[] = { 2935 { ISD::ROTL, MVT::v4i64, 4 }, 2936 { ISD::ROTL, MVT::v8i32, 4 }, 2937 { ISD::ROTL, MVT::v16i16, 4 }, 2938 { ISD::ROTL, MVT::v32i8, 4 }, 2939 { ISD::ROTL, MVT::v2i64, 1 }, 2940 { ISD::ROTL, MVT::v4i32, 1 }, 2941 { ISD::ROTL, MVT::v8i16, 1 }, 2942 { ISD::ROTL, MVT::v16i8, 1 }, 2943 { ISD::ROTR, MVT::v4i64, 6 }, 2944 { ISD::ROTR, MVT::v8i32, 6 }, 2945 { ISD::ROTR, MVT::v16i16, 6 }, 2946 { ISD::ROTR, MVT::v32i8, 6 }, 2947 { ISD::ROTR, MVT::v2i64, 2 }, 2948 { ISD::ROTR, MVT::v4i32, 2 }, 2949 { ISD::ROTR, MVT::v8i16, 2 }, 2950 { ISD::ROTR, MVT::v16i8, 2 } 2951 }; 2952 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2953 { ISD::ROTL, MVT::i64, 1 }, 2954 { ISD::ROTR, MVT::i64, 1 }, 2955 { ISD::FSHL, MVT::i64, 4 } 2956 }; 2957 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2958 { ISD::ROTL, MVT::i32, 1 }, 2959 { ISD::ROTL, MVT::i16, 1 }, 2960 { ISD::ROTL, MVT::i8, 1 }, 2961 { ISD::ROTR, MVT::i32, 1 }, 2962 { ISD::ROTR, MVT::i16, 1 }, 2963 { ISD::ROTR, MVT::i8, 1 }, 2964 { ISD::FSHL, MVT::i32, 4 }, 2965 { ISD::FSHL, MVT::i16, 4 }, 2966 { ISD::FSHL, MVT::i8, 4 } 2967 }; 2968 2969 Intrinsic::ID IID = ICA.getID(); 2970 Type *RetTy = ICA.getReturnType(); 2971 const SmallVectorImpl<const Value *> &Args = ICA.getArgs(); 2972 unsigned ISD = ISD::DELETED_NODE; 2973 switch (IID) { 2974 default: 2975 break; 2976 case Intrinsic::fshl: 2977 ISD = ISD::FSHL; 2978 if (Args[0] == Args[1]) 2979 ISD = ISD::ROTL; 2980 break; 2981 case Intrinsic::fshr: 2982 // FSHR has same costs so don't duplicate. 2983 ISD = ISD::FSHL; 2984 if (Args[0] == Args[1]) 2985 ISD = ISD::ROTR; 2986 break; 2987 } 2988 2989 if (ISD != ISD::DELETED_NODE) { 2990 // Legalize the type. 2991 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 2992 MVT MTy = LT.second; 2993 2994 // Attempt to lookup cost. 2995 if (ST->hasAVX512()) 2996 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2997 return LT.first * Entry->Cost; 2998 2999 if (ST->hasXOP()) 3000 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3001 return LT.first * Entry->Cost; 3002 3003 if (ST->is64Bit()) 3004 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3005 return LT.first * Entry->Cost; 3006 3007 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3008 return LT.first * Entry->Cost; 3009 } 3010 3011 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3012 } 3013 3014 int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { 3015 static const CostTblEntry SLMCostTbl[] = { 3016 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 3017 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 3018 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 3019 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 3020 }; 3021 3022 assert(Val->isVectorTy() && "This must be a vector type"); 3023 Type *ScalarType = Val->getScalarType(); 3024 int RegisterFileMoveCost = 0; 3025 3026 if (Index != -1U && (Opcode == Instruction::ExtractElement || 3027 Opcode == Instruction::InsertElement)) { 3028 // Legalize the type. 3029 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 3030 3031 // This type is legalized to a scalar type. 3032 if (!LT.second.isVector()) 3033 return 0; 3034 3035 // The type may be split. Normalize the index to the new type. 3036 unsigned NumElts = LT.second.getVectorNumElements(); 3037 unsigned SubNumElts = NumElts; 3038 Index = Index % NumElts; 3039 3040 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 3041 // For inserts, we also need to insert the subvector back. 3042 if (LT.second.getSizeInBits() > 128) { 3043 assert((LT.second.getSizeInBits() % 128) == 0 && "Illegal vector"); 3044 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 3045 SubNumElts = NumElts / NumSubVecs; 3046 if (SubNumElts <= Index) { 3047 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 3048 Index %= SubNumElts; 3049 } 3050 } 3051 3052 if (Index == 0) { 3053 // Floating point scalars are already located in index #0. 3054 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 3055 // true for all. 3056 if (ScalarType->isFloatingPointTy()) 3057 return RegisterFileMoveCost; 3058 3059 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 3060 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 3061 return 1 + RegisterFileMoveCost; 3062 } 3063 3064 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3065 assert(ISD && "Unexpected vector opcode"); 3066 MVT MScalarTy = LT.second.getScalarType(); 3067 if (ST->isSLM()) 3068 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 3069 return Entry->Cost + RegisterFileMoveCost; 3070 3071 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 3072 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3073 (MScalarTy.isInteger() && ST->hasSSE41())) 3074 return 1 + RegisterFileMoveCost; 3075 3076 // Assume insertps is relatively cheap on all targets. 3077 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 3078 Opcode == Instruction::InsertElement) 3079 return 1 + RegisterFileMoveCost; 3080 3081 // For extractions we just need to shuffle the element to index 0, which 3082 // should be very cheap (assume cost = 1). For insertions we need to shuffle 3083 // the elements to its destination. In both cases we must handle the 3084 // subvector move(s). 3085 // If the vector type is already less than 128-bits then don't reduce it. 3086 // TODO: Under what circumstances should we shuffle using the full width? 3087 int ShuffleCost = 1; 3088 if (Opcode == Instruction::InsertElement) { 3089 auto *SubTy = cast<VectorType>(Val); 3090 EVT VT = TLI->getValueType(DL, Val); 3091 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 3092 SubTy = FixedVectorType::get(ScalarType, SubNumElts); 3093 ShuffleCost = 3094 getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, None, 0, SubTy); 3095 } 3096 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 3097 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 3098 } 3099 3100 // Add to the base cost if we know that the extracted element of a vector is 3101 // destined to be moved to and used in the integer register file. 3102 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 3103 RegisterFileMoveCost += 1; 3104 3105 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 3106 } 3107 3108 unsigned X86TTIImpl::getScalarizationOverhead(VectorType *Ty, 3109 const APInt &DemandedElts, 3110 bool Insert, bool Extract) { 3111 unsigned Cost = 0; 3112 3113 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much 3114 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT. 3115 if (Insert) { 3116 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3117 MVT MScalarTy = LT.second.getScalarType(); 3118 3119 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3120 (MScalarTy.isInteger() && ST->hasSSE41()) || 3121 (MScalarTy == MVT::f32 && ST->hasSSE41())) { 3122 // For types we can insert directly, insertion into 128-bit sub vectors is 3123 // cheap, followed by a cheap chain of concatenations. 3124 if (LT.second.getSizeInBits() <= 128) { 3125 Cost += 3126 BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, false); 3127 } else { 3128 // In each 128-lane, if at least one index is demanded but not all 3129 // indices are demanded and this 128-lane is not the first 128-lane of 3130 // the legalized-vector, then this 128-lane needs a extracti128; If in 3131 // each 128-lane, there is at least one demanded index, this 128-lane 3132 // needs a inserti128. 3133 3134 // The following cases will help you build a better understanding: 3135 // Assume we insert several elements into a v8i32 vector in avx2, 3136 // Case#1: inserting into 1th index needs vpinsrd + inserti128. 3137 // Case#2: inserting into 5th index needs extracti128 + vpinsrd + 3138 // inserti128. 3139 // Case#3: inserting into 4,5,6,7 index needs 4*vpinsrd + inserti128. 3140 unsigned Num128Lanes = LT.second.getSizeInBits() / 128 * LT.first; 3141 unsigned NumElts = LT.second.getVectorNumElements() * LT.first; 3142 APInt WidenedDemandedElts = DemandedElts.zextOrSelf(NumElts); 3143 unsigned Scale = NumElts / Num128Lanes; 3144 // We iterate each 128-lane, and check if we need a 3145 // extracti128/inserti128 for this 128-lane. 3146 for (unsigned I = 0; I < NumElts; I += Scale) { 3147 APInt Mask = WidenedDemandedElts.getBitsSet(NumElts, I, I + Scale); 3148 APInt MaskedDE = Mask & WidenedDemandedElts; 3149 unsigned Population = MaskedDE.countPopulation(); 3150 Cost += (Population > 0 && Population != Scale && 3151 I % LT.second.getVectorNumElements() != 0); 3152 Cost += Population > 0; 3153 } 3154 Cost += DemandedElts.countPopulation(); 3155 3156 // For vXf32 cases, insertion into the 0'th index in each v4f32 3157 // 128-bit vector is free. 3158 // NOTE: This assumes legalization widens vXf32 vectors. 3159 if (MScalarTy == MVT::f32) 3160 for (unsigned i = 0, e = cast<FixedVectorType>(Ty)->getNumElements(); 3161 i < e; i += 4) 3162 if (DemandedElts[i]) 3163 Cost--; 3164 } 3165 } else if (LT.second.isVector()) { 3166 // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded 3167 // integer element as a SCALAR_TO_VECTOR, then we build the vector as a 3168 // series of UNPCK followed by CONCAT_VECTORS - all of these can be 3169 // considered cheap. 3170 if (Ty->isIntOrIntVectorTy()) 3171 Cost += DemandedElts.countPopulation(); 3172 3173 // Get the smaller of the legalized or original pow2-extended number of 3174 // vector elements, which represents the number of unpacks we'll end up 3175 // performing. 3176 unsigned NumElts = LT.second.getVectorNumElements(); 3177 unsigned Pow2Elts = 3178 PowerOf2Ceil(cast<FixedVectorType>(Ty)->getNumElements()); 3179 Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first; 3180 } 3181 } 3182 3183 // TODO: Use default extraction for now, but we should investigate extending this 3184 // to handle repeated subvector extraction. 3185 if (Extract) 3186 Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, false, Extract); 3187 3188 return Cost; 3189 } 3190 3191 int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 3192 MaybeAlign Alignment, unsigned AddressSpace, 3193 TTI::TargetCostKind CostKind, 3194 const Instruction *I) { 3195 // TODO: Handle other cost kinds. 3196 if (CostKind != TTI::TCK_RecipThroughput) { 3197 if (auto *SI = dyn_cast_or_null<StoreInst>(I)) { 3198 // Store instruction with index and scale costs 2 Uops. 3199 // Check the preceding GEP to identify non-const indices. 3200 if (auto *GEP = dyn_cast<GetElementPtrInst>(SI->getPointerOperand())) { 3201 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3202 return TTI::TCC_Basic * 2; 3203 } 3204 } 3205 return TTI::TCC_Basic; 3206 } 3207 3208 // Handle non-power-of-two vectors such as <3 x float> 3209 if (auto *VTy = dyn_cast<FixedVectorType>(Src)) { 3210 unsigned NumElem = VTy->getNumElements(); 3211 3212 // Handle a few common cases: 3213 // <3 x float> 3214 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 3215 // Cost = 64 bit store + extract + 32 bit store. 3216 return 3; 3217 3218 // <3 x double> 3219 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 3220 // Cost = 128 bit store + unpack + 64 bit store. 3221 return 3; 3222 3223 // Assume that all other non-power-of-two numbers are scalarized. 3224 if (!isPowerOf2_32(NumElem)) { 3225 APInt DemandedElts = APInt::getAllOnesValue(NumElem); 3226 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment, 3227 AddressSpace, CostKind); 3228 int SplitCost = getScalarizationOverhead(VTy, DemandedElts, 3229 Opcode == Instruction::Load, 3230 Opcode == Instruction::Store); 3231 return NumElem * Cost + SplitCost; 3232 } 3233 } 3234 3235 // Type legalization can't handle structs 3236 if (TLI->getValueType(DL, Src, true) == MVT::Other) 3237 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3238 CostKind); 3239 3240 // Legalize the type. 3241 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 3242 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 3243 "Invalid Opcode"); 3244 3245 // Each load/store unit costs 1. 3246 int Cost = LT.first * 1; 3247 3248 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a 3249 // proxy for a double-pumped AVX memory interface such as on Sandybridge. 3250 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow()) 3251 Cost *= 2; 3252 3253 return Cost; 3254 } 3255 3256 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, 3257 Align Alignment, unsigned AddressSpace, 3258 TTI::TargetCostKind CostKind) { 3259 bool IsLoad = (Instruction::Load == Opcode); 3260 bool IsStore = (Instruction::Store == Opcode); 3261 3262 auto *SrcVTy = dyn_cast<FixedVectorType>(SrcTy); 3263 if (!SrcVTy) 3264 // To calculate scalar take the regular cost, without mask 3265 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace, CostKind); 3266 3267 unsigned NumElem = SrcVTy->getNumElements(); 3268 auto *MaskTy = 3269 FixedVectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 3270 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, Alignment)) || 3271 (IsStore && !isLegalMaskedStore(SrcVTy, Alignment)) || 3272 !isPowerOf2_32(NumElem)) { 3273 // Scalarization 3274 APInt DemandedElts = APInt::getAllOnesValue(NumElem); 3275 int MaskSplitCost = 3276 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 3277 int ScalarCompareCost = getCmpSelInstrCost( 3278 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr, 3279 CmpInst::BAD_ICMP_PREDICATE, CostKind); 3280 int BranchCost = getCFInstrCost(Instruction::Br, CostKind); 3281 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 3282 int ValueSplitCost = 3283 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore); 3284 int MemopCost = 3285 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3286 Alignment, AddressSpace, CostKind); 3287 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 3288 } 3289 3290 // Legalize the type. 3291 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3292 auto VT = TLI->getValueType(DL, SrcVTy); 3293 int Cost = 0; 3294 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 3295 LT.second.getVectorNumElements() == NumElem) 3296 // Promotion requires expand/truncate for data and a shuffle for mask. 3297 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, None, 0, nullptr) + 3298 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, None, 0, nullptr); 3299 3300 else if (LT.second.getVectorNumElements() > NumElem) { 3301 auto *NewMaskTy = FixedVectorType::get(MaskTy->getElementType(), 3302 LT.second.getVectorNumElements()); 3303 // Expanding requires fill mask with zeroes 3304 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, None, 0, MaskTy); 3305 } 3306 3307 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 3308 if (!ST->hasAVX512()) 3309 return Cost + LT.first * (IsLoad ? 2 : 8); 3310 3311 // AVX-512 masked load/store is cheapper 3312 return Cost + LT.first; 3313 } 3314 3315 int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE, 3316 const SCEV *Ptr) { 3317 // Address computations in vectorized code with non-consecutive addresses will 3318 // likely result in more instructions compared to scalar code where the 3319 // computation can more often be merged into the index mode. The resulting 3320 // extra micro-ops can significantly decrease throughput. 3321 const unsigned NumVectorInstToHideOverhead = 10; 3322 3323 // Cost modeling of Strided Access Computation is hidden by the indexing 3324 // modes of X86 regardless of the stride value. We dont believe that there 3325 // is a difference between constant strided access in gerenal and constant 3326 // strided value which is less than or equal to 64. 3327 // Even in the case of (loop invariant) stride whose value is not known at 3328 // compile time, the address computation will not incur more than one extra 3329 // ADD instruction. 3330 if (Ty->isVectorTy() && SE) { 3331 if (!BaseT::isStridedAccess(Ptr)) 3332 return NumVectorInstToHideOverhead; 3333 if (!BaseT::getConstantStrideStep(SE, Ptr)) 3334 return 1; 3335 } 3336 3337 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 3338 } 3339 3340 int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 3341 bool IsPairwise, 3342 TTI::TargetCostKind CostKind) { 3343 // Just use the default implementation for pair reductions. 3344 if (IsPairwise) 3345 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise, CostKind); 3346 3347 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3348 // and make it as the cost. 3349 3350 static const CostTblEntry SLMCostTblNoPairWise[] = { 3351 { ISD::FADD, MVT::v2f64, 3 }, 3352 { ISD::ADD, MVT::v2i64, 5 }, 3353 }; 3354 3355 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3356 { ISD::FADD, MVT::v2f64, 2 }, 3357 { ISD::FADD, MVT::v4f32, 4 }, 3358 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 3359 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 3360 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 3361 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 3362 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 3363 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 3364 { ISD::ADD, MVT::v2i8, 2 }, 3365 { ISD::ADD, MVT::v4i8, 2 }, 3366 { ISD::ADD, MVT::v8i8, 2 }, 3367 { ISD::ADD, MVT::v16i8, 3 }, 3368 }; 3369 3370 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3371 { ISD::FADD, MVT::v4f64, 3 }, 3372 { ISD::FADD, MVT::v4f32, 3 }, 3373 { ISD::FADD, MVT::v8f32, 4 }, 3374 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 3375 { ISD::ADD, MVT::v4i64, 3 }, 3376 { ISD::ADD, MVT::v8i32, 5 }, 3377 { ISD::ADD, MVT::v16i16, 5 }, 3378 { ISD::ADD, MVT::v32i8, 4 }, 3379 }; 3380 3381 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3382 assert(ISD && "Invalid opcode"); 3383 3384 // Before legalizing the type, give a chance to look up illegal narrow types 3385 // in the table. 3386 // FIXME: Is there a better way to do this? 3387 EVT VT = TLI->getValueType(DL, ValTy); 3388 if (VT.isSimple()) { 3389 MVT MTy = VT.getSimpleVT(); 3390 if (ST->isSLM()) 3391 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3392 return Entry->Cost; 3393 3394 if (ST->hasAVX()) 3395 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3396 return Entry->Cost; 3397 3398 if (ST->hasSSE2()) 3399 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3400 return Entry->Cost; 3401 } 3402 3403 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3404 3405 MVT MTy = LT.second; 3406 3407 auto *ValVTy = cast<FixedVectorType>(ValTy); 3408 3409 unsigned ArithmeticCost = 0; 3410 if (LT.first != 1 && MTy.isVector() && 3411 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3412 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3413 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3414 MTy.getVectorNumElements()); 3415 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3416 ArithmeticCost *= LT.first - 1; 3417 } 3418 3419 if (ST->isSLM()) 3420 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3421 return ArithmeticCost + Entry->Cost; 3422 3423 if (ST->hasAVX()) 3424 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3425 return ArithmeticCost + Entry->Cost; 3426 3427 if (ST->hasSSE2()) 3428 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3429 return ArithmeticCost + Entry->Cost; 3430 3431 // FIXME: These assume a naive kshift+binop lowering, which is probably 3432 // conservative in most cases. 3433 static const CostTblEntry AVX512BoolReduction[] = { 3434 { ISD::AND, MVT::v2i1, 3 }, 3435 { ISD::AND, MVT::v4i1, 5 }, 3436 { ISD::AND, MVT::v8i1, 7 }, 3437 { ISD::AND, MVT::v16i1, 9 }, 3438 { ISD::AND, MVT::v32i1, 11 }, 3439 { ISD::AND, MVT::v64i1, 13 }, 3440 { ISD::OR, MVT::v2i1, 3 }, 3441 { ISD::OR, MVT::v4i1, 5 }, 3442 { ISD::OR, MVT::v8i1, 7 }, 3443 { ISD::OR, MVT::v16i1, 9 }, 3444 { ISD::OR, MVT::v32i1, 11 }, 3445 { ISD::OR, MVT::v64i1, 13 }, 3446 }; 3447 3448 static const CostTblEntry AVX2BoolReduction[] = { 3449 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 3450 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 3451 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 3452 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 3453 }; 3454 3455 static const CostTblEntry AVX1BoolReduction[] = { 3456 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 3457 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 3458 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3459 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3460 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 3461 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 3462 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3463 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3464 }; 3465 3466 static const CostTblEntry SSE2BoolReduction[] = { 3467 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 3468 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 3469 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 3470 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 3471 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 3472 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 3473 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 3474 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 3475 }; 3476 3477 // Handle bool allof/anyof patterns. 3478 if (ValVTy->getElementType()->isIntegerTy(1)) { 3479 unsigned ArithmeticCost = 0; 3480 if (LT.first != 1 && MTy.isVector() && 3481 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3482 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3483 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3484 MTy.getVectorNumElements()); 3485 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3486 ArithmeticCost *= LT.first - 1; 3487 } 3488 3489 if (ST->hasAVX512()) 3490 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 3491 return ArithmeticCost + Entry->Cost; 3492 if (ST->hasAVX2()) 3493 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 3494 return ArithmeticCost + Entry->Cost; 3495 if (ST->hasAVX()) 3496 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 3497 return ArithmeticCost + Entry->Cost; 3498 if (ST->hasSSE2()) 3499 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 3500 return ArithmeticCost + Entry->Cost; 3501 3502 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise, 3503 CostKind); 3504 } 3505 3506 unsigned NumVecElts = ValVTy->getNumElements(); 3507 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 3508 3509 // Special case power of 2 reductions where the scalar type isn't changed 3510 // by type legalization. 3511 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 3512 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise, 3513 CostKind); 3514 3515 unsigned ReductionCost = 0; 3516 3517 auto *Ty = ValVTy; 3518 if (LT.first != 1 && MTy.isVector() && 3519 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3520 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3521 Ty = FixedVectorType::get(ValVTy->getElementType(), 3522 MTy.getVectorNumElements()); 3523 ReductionCost = getArithmeticInstrCost(Opcode, Ty, CostKind); 3524 ReductionCost *= LT.first - 1; 3525 NumVecElts = MTy.getVectorNumElements(); 3526 } 3527 3528 // Now handle reduction with the legal type, taking into account size changes 3529 // at each level. 3530 while (NumVecElts > 1) { 3531 // Determine the size of the remaining vector we need to reduce. 3532 unsigned Size = NumVecElts * ScalarSize; 3533 NumVecElts /= 2; 3534 // If we're reducing from 256/512 bits, use an extract_subvector. 3535 if (Size > 128) { 3536 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 3537 ReductionCost += 3538 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 3539 Ty = SubTy; 3540 } else if (Size == 128) { 3541 // Reducing from 128 bits is a permute of v2f64/v2i64. 3542 FixedVectorType *ShufTy; 3543 if (ValVTy->isFloatingPointTy()) 3544 ShufTy = 3545 FixedVectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 3546 else 3547 ShufTy = 3548 FixedVectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 3549 ReductionCost += 3550 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3551 } else if (Size == 64) { 3552 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3553 FixedVectorType *ShufTy; 3554 if (ValVTy->isFloatingPointTy()) 3555 ShufTy = 3556 FixedVectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 3557 else 3558 ShufTy = 3559 FixedVectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 3560 ReductionCost += 3561 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3562 } else { 3563 // Reducing from smaller size is a shift by immediate. 3564 auto *ShiftTy = FixedVectorType::get( 3565 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 3566 ReductionCost += getArithmeticInstrCost( 3567 Instruction::LShr, ShiftTy, CostKind, 3568 TargetTransformInfo::OK_AnyValue, 3569 TargetTransformInfo::OK_UniformConstantValue, 3570 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3571 } 3572 3573 // Add the arithmetic op for this level. 3574 ReductionCost += getArithmeticInstrCost(Opcode, Ty, CostKind); 3575 } 3576 3577 // Add the final extract element to the cost. 3578 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3579 } 3580 3581 int X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, bool IsUnsigned) { 3582 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3583 3584 MVT MTy = LT.second; 3585 3586 int ISD; 3587 if (Ty->isIntOrIntVectorTy()) { 3588 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3589 } else { 3590 assert(Ty->isFPOrFPVectorTy() && 3591 "Expected float point or integer vector type."); 3592 ISD = ISD::FMINNUM; 3593 } 3594 3595 static const CostTblEntry SSE1CostTbl[] = { 3596 {ISD::FMINNUM, MVT::v4f32, 1}, 3597 }; 3598 3599 static const CostTblEntry SSE2CostTbl[] = { 3600 {ISD::FMINNUM, MVT::v2f64, 1}, 3601 {ISD::SMIN, MVT::v8i16, 1}, 3602 {ISD::UMIN, MVT::v16i8, 1}, 3603 }; 3604 3605 static const CostTblEntry SSE41CostTbl[] = { 3606 {ISD::SMIN, MVT::v4i32, 1}, 3607 {ISD::UMIN, MVT::v4i32, 1}, 3608 {ISD::UMIN, MVT::v8i16, 1}, 3609 {ISD::SMIN, MVT::v16i8, 1}, 3610 }; 3611 3612 static const CostTblEntry SSE42CostTbl[] = { 3613 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 3614 }; 3615 3616 static const CostTblEntry AVX1CostTbl[] = { 3617 {ISD::FMINNUM, MVT::v8f32, 1}, 3618 {ISD::FMINNUM, MVT::v4f64, 1}, 3619 {ISD::SMIN, MVT::v8i32, 3}, 3620 {ISD::UMIN, MVT::v8i32, 3}, 3621 {ISD::SMIN, MVT::v16i16, 3}, 3622 {ISD::UMIN, MVT::v16i16, 3}, 3623 {ISD::SMIN, MVT::v32i8, 3}, 3624 {ISD::UMIN, MVT::v32i8, 3}, 3625 }; 3626 3627 static const CostTblEntry AVX2CostTbl[] = { 3628 {ISD::SMIN, MVT::v8i32, 1}, 3629 {ISD::UMIN, MVT::v8i32, 1}, 3630 {ISD::SMIN, MVT::v16i16, 1}, 3631 {ISD::UMIN, MVT::v16i16, 1}, 3632 {ISD::SMIN, MVT::v32i8, 1}, 3633 {ISD::UMIN, MVT::v32i8, 1}, 3634 }; 3635 3636 static const CostTblEntry AVX512CostTbl[] = { 3637 {ISD::FMINNUM, MVT::v16f32, 1}, 3638 {ISD::FMINNUM, MVT::v8f64, 1}, 3639 {ISD::SMIN, MVT::v2i64, 1}, 3640 {ISD::UMIN, MVT::v2i64, 1}, 3641 {ISD::SMIN, MVT::v4i64, 1}, 3642 {ISD::UMIN, MVT::v4i64, 1}, 3643 {ISD::SMIN, MVT::v8i64, 1}, 3644 {ISD::UMIN, MVT::v8i64, 1}, 3645 {ISD::SMIN, MVT::v16i32, 1}, 3646 {ISD::UMIN, MVT::v16i32, 1}, 3647 }; 3648 3649 static const CostTblEntry AVX512BWCostTbl[] = { 3650 {ISD::SMIN, MVT::v32i16, 1}, 3651 {ISD::UMIN, MVT::v32i16, 1}, 3652 {ISD::SMIN, MVT::v64i8, 1}, 3653 {ISD::UMIN, MVT::v64i8, 1}, 3654 }; 3655 3656 // If we have a native MIN/MAX instruction for this type, use it. 3657 if (ST->hasBWI()) 3658 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3659 return LT.first * Entry->Cost; 3660 3661 if (ST->hasAVX512()) 3662 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3663 return LT.first * Entry->Cost; 3664 3665 if (ST->hasAVX2()) 3666 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3667 return LT.first * Entry->Cost; 3668 3669 if (ST->hasAVX()) 3670 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3671 return LT.first * Entry->Cost; 3672 3673 if (ST->hasSSE42()) 3674 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3675 return LT.first * Entry->Cost; 3676 3677 if (ST->hasSSE41()) 3678 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3679 return LT.first * Entry->Cost; 3680 3681 if (ST->hasSSE2()) 3682 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3683 return LT.first * Entry->Cost; 3684 3685 if (ST->hasSSE1()) 3686 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3687 return LT.first * Entry->Cost; 3688 3689 unsigned CmpOpcode; 3690 if (Ty->isFPOrFPVectorTy()) { 3691 CmpOpcode = Instruction::FCmp; 3692 } else { 3693 assert(Ty->isIntOrIntVectorTy() && 3694 "expecting floating point or integer type for min/max reduction"); 3695 CmpOpcode = Instruction::ICmp; 3696 } 3697 3698 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 3699 // Otherwise fall back to cmp+select. 3700 return getCmpSelInstrCost(CmpOpcode, Ty, CondTy, CmpInst::BAD_ICMP_PREDICATE, 3701 CostKind) + 3702 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, 3703 CmpInst::BAD_ICMP_PREDICATE, CostKind); 3704 } 3705 3706 int X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 3707 bool IsPairwise, bool IsUnsigned, 3708 TTI::TargetCostKind CostKind) { 3709 // Just use the default implementation for pair reductions. 3710 if (IsPairwise) 3711 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned, 3712 CostKind); 3713 3714 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3715 3716 MVT MTy = LT.second; 3717 3718 int ISD; 3719 if (ValTy->isIntOrIntVectorTy()) { 3720 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3721 } else { 3722 assert(ValTy->isFPOrFPVectorTy() && 3723 "Expected float point or integer vector type."); 3724 ISD = ISD::FMINNUM; 3725 } 3726 3727 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3728 // and make it as the cost. 3729 3730 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3731 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 3732 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 3733 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 3734 }; 3735 3736 static const CostTblEntry SSE41CostTblNoPairWise[] = { 3737 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 3738 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 3739 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 3740 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 3741 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 3742 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 3743 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 3744 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 3745 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 3746 {ISD::SMIN, MVT::v16i8, 6}, 3747 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 3748 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 3749 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 3750 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 3751 }; 3752 3753 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3754 {ISD::SMIN, MVT::v16i16, 6}, 3755 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 3756 {ISD::SMIN, MVT::v32i8, 8}, 3757 {ISD::UMIN, MVT::v32i8, 8}, 3758 }; 3759 3760 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 3761 {ISD::SMIN, MVT::v32i16, 8}, 3762 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 3763 {ISD::SMIN, MVT::v64i8, 10}, 3764 {ISD::UMIN, MVT::v64i8, 10}, 3765 }; 3766 3767 // Before legalizing the type, give a chance to look up illegal narrow types 3768 // in the table. 3769 // FIXME: Is there a better way to do this? 3770 EVT VT = TLI->getValueType(DL, ValTy); 3771 if (VT.isSimple()) { 3772 MVT MTy = VT.getSimpleVT(); 3773 if (ST->hasBWI()) 3774 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3775 return Entry->Cost; 3776 3777 if (ST->hasAVX()) 3778 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3779 return Entry->Cost; 3780 3781 if (ST->hasSSE41()) 3782 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3783 return Entry->Cost; 3784 3785 if (ST->hasSSE2()) 3786 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3787 return Entry->Cost; 3788 } 3789 3790 auto *ValVTy = cast<FixedVectorType>(ValTy); 3791 unsigned NumVecElts = ValVTy->getNumElements(); 3792 3793 auto *Ty = ValVTy; 3794 unsigned MinMaxCost = 0; 3795 if (LT.first != 1 && MTy.isVector() && 3796 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3797 // Type needs to be split. We need LT.first - 1 operations ops. 3798 Ty = FixedVectorType::get(ValVTy->getElementType(), 3799 MTy.getVectorNumElements()); 3800 auto *SubCondTy = FixedVectorType::get(CondTy->getElementType(), 3801 MTy.getVectorNumElements()); 3802 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3803 MinMaxCost *= LT.first - 1; 3804 NumVecElts = MTy.getVectorNumElements(); 3805 } 3806 3807 if (ST->hasBWI()) 3808 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3809 return MinMaxCost + Entry->Cost; 3810 3811 if (ST->hasAVX()) 3812 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3813 return MinMaxCost + Entry->Cost; 3814 3815 if (ST->hasSSE41()) 3816 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3817 return MinMaxCost + Entry->Cost; 3818 3819 if (ST->hasSSE2()) 3820 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3821 return MinMaxCost + Entry->Cost; 3822 3823 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 3824 3825 // Special case power of 2 reductions where the scalar type isn't changed 3826 // by type legalization. 3827 if (!isPowerOf2_32(ValVTy->getNumElements()) || 3828 ScalarSize != MTy.getScalarSizeInBits()) 3829 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned, 3830 CostKind); 3831 3832 // Now handle reduction with the legal type, taking into account size changes 3833 // at each level. 3834 while (NumVecElts > 1) { 3835 // Determine the size of the remaining vector we need to reduce. 3836 unsigned Size = NumVecElts * ScalarSize; 3837 NumVecElts /= 2; 3838 // If we're reducing from 256/512 bits, use an extract_subvector. 3839 if (Size > 128) { 3840 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 3841 MinMaxCost += 3842 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 3843 Ty = SubTy; 3844 } else if (Size == 128) { 3845 // Reducing from 128 bits is a permute of v2f64/v2i64. 3846 VectorType *ShufTy; 3847 if (ValTy->isFloatingPointTy()) 3848 ShufTy = 3849 FixedVectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 3850 else 3851 ShufTy = FixedVectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 3852 MinMaxCost += 3853 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3854 } else if (Size == 64) { 3855 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3856 FixedVectorType *ShufTy; 3857 if (ValTy->isFloatingPointTy()) 3858 ShufTy = FixedVectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 3859 else 3860 ShufTy = FixedVectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 3861 MinMaxCost += 3862 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3863 } else { 3864 // Reducing from smaller size is a shift by immediate. 3865 auto *ShiftTy = FixedVectorType::get( 3866 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 3867 MinMaxCost += getArithmeticInstrCost( 3868 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, 3869 TargetTransformInfo::OK_AnyValue, 3870 TargetTransformInfo::OK_UniformConstantValue, 3871 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3872 } 3873 3874 // Add the arithmetic op for this level. 3875 auto *SubCondTy = 3876 FixedVectorType::get(CondTy->getElementType(), Ty->getNumElements()); 3877 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3878 } 3879 3880 // Add the final extract element to the cost. 3881 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3882 } 3883 3884 /// Calculate the cost of materializing a 64-bit value. This helper 3885 /// method might only calculate a fraction of a larger immediate. Therefore it 3886 /// is valid to return a cost of ZERO. 3887 int X86TTIImpl::getIntImmCost(int64_t Val) { 3888 if (Val == 0) 3889 return TTI::TCC_Free; 3890 3891 if (isInt<32>(Val)) 3892 return TTI::TCC_Basic; 3893 3894 return 2 * TTI::TCC_Basic; 3895 } 3896 3897 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 3898 TTI::TargetCostKind CostKind) { 3899 assert(Ty->isIntegerTy()); 3900 3901 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3902 if (BitSize == 0) 3903 return ~0U; 3904 3905 // Never hoist constants larger than 128bit, because this might lead to 3906 // incorrect code generation or assertions in codegen. 3907 // Fixme: Create a cost model for types larger than i128 once the codegen 3908 // issues have been fixed. 3909 if (BitSize > 128) 3910 return TTI::TCC_Free; 3911 3912 if (Imm == 0) 3913 return TTI::TCC_Free; 3914 3915 // Sign-extend all constants to a multiple of 64-bit. 3916 APInt ImmVal = Imm; 3917 if (BitSize % 64 != 0) 3918 ImmVal = Imm.sext(alignTo(BitSize, 64)); 3919 3920 // Split the constant into 64-bit chunks and calculate the cost for each 3921 // chunk. 3922 int Cost = 0; 3923 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 3924 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 3925 int64_t Val = Tmp.getSExtValue(); 3926 Cost += getIntImmCost(Val); 3927 } 3928 // We need at least one instruction to materialize the constant. 3929 return std::max(1, Cost); 3930 } 3931 3932 int X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, 3933 const APInt &Imm, Type *Ty, 3934 TTI::TargetCostKind CostKind, 3935 Instruction *Inst) { 3936 assert(Ty->isIntegerTy()); 3937 3938 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3939 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3940 // here, so that constant hoisting will ignore this constant. 3941 if (BitSize == 0) 3942 return TTI::TCC_Free; 3943 3944 unsigned ImmIdx = ~0U; 3945 switch (Opcode) { 3946 default: 3947 return TTI::TCC_Free; 3948 case Instruction::GetElementPtr: 3949 // Always hoist the base address of a GetElementPtr. This prevents the 3950 // creation of new constants for every base constant that gets constant 3951 // folded with the offset. 3952 if (Idx == 0) 3953 return 2 * TTI::TCC_Basic; 3954 return TTI::TCC_Free; 3955 case Instruction::Store: 3956 ImmIdx = 0; 3957 break; 3958 case Instruction::ICmp: 3959 // This is an imperfect hack to prevent constant hoisting of 3960 // compares that might be trying to check if a 64-bit value fits in 3961 // 32-bits. The backend can optimize these cases using a right shift by 32. 3962 // Ideally we would check the compare predicate here. There also other 3963 // similar immediates the backend can use shifts for. 3964 if (Idx == 1 && Imm.getBitWidth() == 64) { 3965 uint64_t ImmVal = Imm.getZExtValue(); 3966 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 3967 return TTI::TCC_Free; 3968 } 3969 ImmIdx = 1; 3970 break; 3971 case Instruction::And: 3972 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 3973 // by using a 32-bit operation with implicit zero extension. Detect such 3974 // immediates here as the normal path expects bit 31 to be sign extended. 3975 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 3976 return TTI::TCC_Free; 3977 ImmIdx = 1; 3978 break; 3979 case Instruction::Add: 3980 case Instruction::Sub: 3981 // For add/sub, we can use the opposite instruction for INT32_MIN. 3982 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 3983 return TTI::TCC_Free; 3984 ImmIdx = 1; 3985 break; 3986 case Instruction::UDiv: 3987 case Instruction::SDiv: 3988 case Instruction::URem: 3989 case Instruction::SRem: 3990 // Division by constant is typically expanded later into a different 3991 // instruction sequence. This completely changes the constants. 3992 // Report them as "free" to stop ConstantHoist from marking them as opaque. 3993 return TTI::TCC_Free; 3994 case Instruction::Mul: 3995 case Instruction::Or: 3996 case Instruction::Xor: 3997 ImmIdx = 1; 3998 break; 3999 // Always return TCC_Free for the shift value of a shift instruction. 4000 case Instruction::Shl: 4001 case Instruction::LShr: 4002 case Instruction::AShr: 4003 if (Idx == 1) 4004 return TTI::TCC_Free; 4005 break; 4006 case Instruction::Trunc: 4007 case Instruction::ZExt: 4008 case Instruction::SExt: 4009 case Instruction::IntToPtr: 4010 case Instruction::PtrToInt: 4011 case Instruction::BitCast: 4012 case Instruction::PHI: 4013 case Instruction::Call: 4014 case Instruction::Select: 4015 case Instruction::Ret: 4016 case Instruction::Load: 4017 break; 4018 } 4019 4020 if (Idx == ImmIdx) { 4021 int NumConstants = divideCeil(BitSize, 64); 4022 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4023 return (Cost <= NumConstants * TTI::TCC_Basic) 4024 ? static_cast<int>(TTI::TCC_Free) 4025 : Cost; 4026 } 4027 4028 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4029 } 4030 4031 int X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 4032 const APInt &Imm, Type *Ty, 4033 TTI::TargetCostKind CostKind) { 4034 assert(Ty->isIntegerTy()); 4035 4036 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4037 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4038 // here, so that constant hoisting will ignore this constant. 4039 if (BitSize == 0) 4040 return TTI::TCC_Free; 4041 4042 switch (IID) { 4043 default: 4044 return TTI::TCC_Free; 4045 case Intrinsic::sadd_with_overflow: 4046 case Intrinsic::uadd_with_overflow: 4047 case Intrinsic::ssub_with_overflow: 4048 case Intrinsic::usub_with_overflow: 4049 case Intrinsic::smul_with_overflow: 4050 case Intrinsic::umul_with_overflow: 4051 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 4052 return TTI::TCC_Free; 4053 break; 4054 case Intrinsic::experimental_stackmap: 4055 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4056 return TTI::TCC_Free; 4057 break; 4058 case Intrinsic::experimental_patchpoint_void: 4059 case Intrinsic::experimental_patchpoint_i64: 4060 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4061 return TTI::TCC_Free; 4062 break; 4063 } 4064 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4065 } 4066 4067 unsigned 4068 X86TTIImpl::getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind) { 4069 if (CostKind != TTI::TCK_RecipThroughput) 4070 return Opcode == Instruction::PHI ? 0 : 1; 4071 // Branches are assumed to be predicted. 4072 return CostKind == TTI::TCK_RecipThroughput ? 0 : 1; 4073 } 4074 4075 int X86TTIImpl::getGatherOverhead() const { 4076 // Some CPUs have more overhead for gather. The specified overhead is relative 4077 // to the Load operation. "2" is the number provided by Intel architects. This 4078 // parameter is used for cost estimation of Gather Op and comparison with 4079 // other alternatives. 4080 // TODO: Remove the explicit hasAVX512()?, That would mean we would only 4081 // enable gather with a -march. 4082 if (ST->hasAVX512() || (ST->hasAVX2() && ST->hasFastGather())) 4083 return 2; 4084 4085 return 1024; 4086 } 4087 4088 int X86TTIImpl::getScatterOverhead() const { 4089 if (ST->hasAVX512()) 4090 return 2; 4091 4092 return 1024; 4093 } 4094 4095 // Return an average cost of Gather / Scatter instruction, maybe improved later. 4096 // FIXME: Add TargetCostKind support. 4097 int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, const Value *Ptr, 4098 Align Alignment, unsigned AddressSpace) { 4099 4100 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 4101 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4102 4103 // Try to reduce index size from 64 bit (default for GEP) 4104 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 4105 // operation will use 16 x 64 indices which do not fit in a zmm and needs 4106 // to split. Also check that the base pointer is the same for all lanes, 4107 // and that there's at most one variable index. 4108 auto getIndexSizeInBits = [](const Value *Ptr, const DataLayout &DL) { 4109 unsigned IndexSize = DL.getPointerSizeInBits(); 4110 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 4111 if (IndexSize < 64 || !GEP) 4112 return IndexSize; 4113 4114 unsigned NumOfVarIndices = 0; 4115 const Value *Ptrs = GEP->getPointerOperand(); 4116 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 4117 return IndexSize; 4118 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 4119 if (isa<Constant>(GEP->getOperand(i))) 4120 continue; 4121 Type *IndxTy = GEP->getOperand(i)->getType(); 4122 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 4123 IndxTy = IndexVTy->getElementType(); 4124 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 4125 !isa<SExtInst>(GEP->getOperand(i))) || 4126 ++NumOfVarIndices > 1) 4127 return IndexSize; // 64 4128 } 4129 return (unsigned)32; 4130 }; 4131 4132 // Trying to reduce IndexSize to 32 bits for vector 16. 4133 // By default the IndexSize is equal to pointer size. 4134 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 4135 ? getIndexSizeInBits(Ptr, DL) 4136 : DL.getPointerSizeInBits(); 4137 4138 auto *IndexVTy = FixedVectorType::get( 4139 IntegerType::get(SrcVTy->getContext(), IndexSize), VF); 4140 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy); 4141 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy); 4142 int SplitFactor = std::max(IdxsLT.first, SrcLT.first); 4143 if (SplitFactor > 1) { 4144 // Handle splitting of vector of pointers 4145 auto *SplitSrcTy = 4146 FixedVectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 4147 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 4148 AddressSpace); 4149 } 4150 4151 // The gather / scatter cost is given by Intel architects. It is a rough 4152 // number since we are looking at one instruction in a time. 4153 const int GSOverhead = (Opcode == Instruction::Load) 4154 ? getGatherOverhead() 4155 : getScatterOverhead(); 4156 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4157 MaybeAlign(Alignment), AddressSpace, 4158 TTI::TCK_RecipThroughput); 4159 } 4160 4161 /// Return the cost of full scalarization of gather / scatter operation. 4162 /// 4163 /// Opcode - Load or Store instruction. 4164 /// SrcVTy - The type of the data vector that should be gathered or scattered. 4165 /// VariableMask - The mask is non-constant at compile time. 4166 /// Alignment - Alignment for one element. 4167 /// AddressSpace - pointer[s] address space. 4168 /// 4169 /// FIXME: Add TargetCostKind support. 4170 int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 4171 bool VariableMask, Align Alignment, 4172 unsigned AddressSpace) { 4173 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4174 APInt DemandedElts = APInt::getAllOnesValue(VF); 4175 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4176 4177 int MaskUnpackCost = 0; 4178 if (VariableMask) { 4179 auto *MaskTy = 4180 FixedVectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 4181 MaskUnpackCost = 4182 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 4183 int ScalarCompareCost = getCmpSelInstrCost( 4184 Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), nullptr, 4185 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4186 int BranchCost = getCFInstrCost(Instruction::Br, CostKind); 4187 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 4188 } 4189 4190 // The cost of the scalar loads/stores. 4191 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4192 MaybeAlign(Alignment), AddressSpace, 4193 CostKind); 4194 4195 int InsertExtractCost = 0; 4196 if (Opcode == Instruction::Load) 4197 for (unsigned i = 0; i < VF; ++i) 4198 // Add the cost of inserting each scalar load into the vector 4199 InsertExtractCost += 4200 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 4201 else 4202 for (unsigned i = 0; i < VF; ++i) 4203 // Add the cost of extracting each element out of the data vector 4204 InsertExtractCost += 4205 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 4206 4207 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 4208 } 4209 4210 /// Calculate the cost of Gather / Scatter operation 4211 int X86TTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *SrcVTy, 4212 const Value *Ptr, bool VariableMask, 4213 Align Alignment, 4214 TTI::TargetCostKind CostKind, 4215 const Instruction *I = nullptr) { 4216 if (CostKind != TTI::TCK_RecipThroughput) { 4217 if ((Opcode == Instruction::Load && 4218 isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4219 (Opcode == Instruction::Store && 4220 isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4221 return 1; 4222 return BaseT::getGatherScatterOpCost(Opcode, SrcVTy, Ptr, VariableMask, 4223 Alignment, CostKind, I); 4224 } 4225 4226 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 4227 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4228 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 4229 if (!PtrTy && Ptr->getType()->isVectorTy()) 4230 PtrTy = dyn_cast<PointerType>( 4231 cast<VectorType>(Ptr->getType())->getElementType()); 4232 assert(PtrTy && "Unexpected type for Ptr argument"); 4233 unsigned AddressSpace = PtrTy->getAddressSpace(); 4234 4235 bool Scalarize = false; 4236 if ((Opcode == Instruction::Load && 4237 !isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4238 (Opcode == Instruction::Store && 4239 !isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4240 Scalarize = true; 4241 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 4242 // Vector-4 of gather/scatter instruction does not exist on KNL. 4243 // We can extend it to 8 elements, but zeroing upper bits of 4244 // the mask vector will add more instructions. Right now we give the scalar 4245 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 4246 // is better in the VariableMask case. 4247 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 4248 Scalarize = true; 4249 4250 if (Scalarize) 4251 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 4252 AddressSpace); 4253 4254 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 4255 } 4256 4257 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 4258 TargetTransformInfo::LSRCost &C2) { 4259 // X86 specific here are "instruction number 1st priority". 4260 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 4261 C1.NumIVMuls, C1.NumBaseAdds, 4262 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 4263 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 4264 C2.NumIVMuls, C2.NumBaseAdds, 4265 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 4266 } 4267 4268 bool X86TTIImpl::canMacroFuseCmp() { 4269 return ST->hasMacroFusion() || ST->hasBranchFusion(); 4270 } 4271 4272 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, Align Alignment) { 4273 if (!ST->hasAVX()) 4274 return false; 4275 4276 // The backend can't handle a single element vector. 4277 if (isa<VectorType>(DataTy) && 4278 cast<FixedVectorType>(DataTy)->getNumElements() == 1) 4279 return false; 4280 Type *ScalarTy = DataTy->getScalarType(); 4281 4282 if (ScalarTy->isPointerTy()) 4283 return true; 4284 4285 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4286 return true; 4287 4288 if (!ScalarTy->isIntegerTy()) 4289 return false; 4290 4291 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4292 return IntWidth == 32 || IntWidth == 64 || 4293 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 4294 } 4295 4296 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, Align Alignment) { 4297 return isLegalMaskedLoad(DataType, Alignment); 4298 } 4299 4300 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 4301 unsigned DataSize = DL.getTypeStoreSize(DataType); 4302 // The only supported nontemporal loads are for aligned vectors of 16 or 32 4303 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 4304 // (the equivalent stores only require AVX). 4305 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 4306 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 4307 4308 return false; 4309 } 4310 4311 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 4312 unsigned DataSize = DL.getTypeStoreSize(DataType); 4313 4314 // SSE4A supports nontemporal stores of float and double at arbitrary 4315 // alignment. 4316 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 4317 return true; 4318 4319 // Besides the SSE4A subtarget exception above, only aligned stores are 4320 // available nontemporaly on any other subtarget. And only stores with a size 4321 // of 4..32 bytes (powers of 2, only) are permitted. 4322 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 4323 !isPowerOf2_32(DataSize)) 4324 return false; 4325 4326 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 4327 // loads require AVX2). 4328 if (DataSize == 32) 4329 return ST->hasAVX(); 4330 else if (DataSize == 16) 4331 return ST->hasSSE1(); 4332 return true; 4333 } 4334 4335 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 4336 if (!isa<VectorType>(DataTy)) 4337 return false; 4338 4339 if (!ST->hasAVX512()) 4340 return false; 4341 4342 // The backend can't handle a single element vector. 4343 if (cast<FixedVectorType>(DataTy)->getNumElements() == 1) 4344 return false; 4345 4346 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 4347 4348 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4349 return true; 4350 4351 if (!ScalarTy->isIntegerTy()) 4352 return false; 4353 4354 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4355 return IntWidth == 32 || IntWidth == 64 || 4356 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 4357 } 4358 4359 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 4360 return isLegalMaskedExpandLoad(DataTy); 4361 } 4362 4363 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, Align Alignment) { 4364 // Some CPUs have better gather performance than others. 4365 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 4366 // enable gather with a -march. 4367 if (!(ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()))) 4368 return false; 4369 4370 // This function is called now in two cases: from the Loop Vectorizer 4371 // and from the Scalarizer. 4372 // When the Loop Vectorizer asks about legality of the feature, 4373 // the vectorization factor is not calculated yet. The Loop Vectorizer 4374 // sends a scalar type and the decision is based on the width of the 4375 // scalar element. 4376 // Later on, the cost model will estimate usage this intrinsic based on 4377 // the vector type. 4378 // The Scalarizer asks again about legality. It sends a vector type. 4379 // In this case we can reject non-power-of-2 vectors. 4380 // We also reject single element vectors as the type legalizer can't 4381 // scalarize it. 4382 if (auto *DataVTy = dyn_cast<FixedVectorType>(DataTy)) { 4383 unsigned NumElts = DataVTy->getNumElements(); 4384 if (NumElts == 1) 4385 return false; 4386 } 4387 Type *ScalarTy = DataTy->getScalarType(); 4388 if (ScalarTy->isPointerTy()) 4389 return true; 4390 4391 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4392 return true; 4393 4394 if (!ScalarTy->isIntegerTy()) 4395 return false; 4396 4397 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4398 return IntWidth == 32 || IntWidth == 64; 4399 } 4400 4401 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, Align Alignment) { 4402 // AVX2 doesn't support scatter 4403 if (!ST->hasAVX512()) 4404 return false; 4405 return isLegalMaskedGather(DataType, Alignment); 4406 } 4407 4408 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 4409 EVT VT = TLI->getValueType(DL, DataType); 4410 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 4411 } 4412 4413 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 4414 return false; 4415 } 4416 4417 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 4418 const Function *Callee) const { 4419 const TargetMachine &TM = getTLI()->getTargetMachine(); 4420 4421 // Work this as a subsetting of subtarget features. 4422 const FeatureBitset &CallerBits = 4423 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 4424 const FeatureBitset &CalleeBits = 4425 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 4426 4427 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 4428 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 4429 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 4430 } 4431 4432 bool X86TTIImpl::areFunctionArgsABICompatible( 4433 const Function *Caller, const Function *Callee, 4434 SmallPtrSetImpl<Argument *> &Args) const { 4435 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args)) 4436 return false; 4437 4438 // If we get here, we know the target features match. If one function 4439 // considers 512-bit vectors legal and the other does not, consider them 4440 // incompatible. 4441 const TargetMachine &TM = getTLI()->getTargetMachine(); 4442 4443 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 4444 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs()) 4445 return true; 4446 4447 // Consider the arguments compatible if they aren't vectors or aggregates. 4448 // FIXME: Look at the size of vectors. 4449 // FIXME: Look at the element types of aggregates to see if there are vectors. 4450 // FIXME: The API of this function seems intended to allow arguments 4451 // to be removed from the set, but the caller doesn't check if the set 4452 // becomes empty so that may not work in practice. 4453 return llvm::none_of(Args, [](Argument *A) { 4454 auto *EltTy = cast<PointerType>(A->getType())->getElementType(); 4455 return EltTy->isVectorTy() || EltTy->isAggregateType(); 4456 }); 4457 } 4458 4459 X86TTIImpl::TTI::MemCmpExpansionOptions 4460 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 4461 TTI::MemCmpExpansionOptions Options; 4462 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 4463 Options.NumLoadsPerBlock = 2; 4464 // All GPR and vector loads can be unaligned. 4465 Options.AllowOverlappingLoads = true; 4466 if (IsZeroCmp) { 4467 // Only enable vector loads for equality comparison. Right now the vector 4468 // version is not as fast for three way compare (see #33329). 4469 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 4470 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 4471 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 4472 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 4473 } 4474 if (ST->is64Bit()) { 4475 Options.LoadSizes.push_back(8); 4476 } 4477 Options.LoadSizes.push_back(4); 4478 Options.LoadSizes.push_back(2); 4479 Options.LoadSizes.push_back(1); 4480 return Options; 4481 } 4482 4483 bool X86TTIImpl::enableInterleavedAccessVectorization() { 4484 // TODO: We expect this to be beneficial regardless of arch, 4485 // but there are currently some unexplained performance artifacts on Atom. 4486 // As a temporary solution, disable on Atom. 4487 return !(ST->isAtom()); 4488 } 4489 4490 // Get estimation for interleaved load/store operations for AVX2. 4491 // \p Factor is the interleaved-access factor (stride) - number of 4492 // (interleaved) elements in the group. 4493 // \p Indices contains the indices for a strided load: when the 4494 // interleaved load has gaps they indicate which elements are used. 4495 // If Indices is empty (or if the number of indices is equal to the size 4496 // of the interleaved-access as given in \p Factor) the access has no gaps. 4497 // 4498 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 4499 // computing the cost using a generic formula as a function of generic 4500 // shuffles. We therefore use a lookup table instead, filled according to 4501 // the instruction sequences that codegen currently generates. 4502 int X86TTIImpl::getInterleavedMemoryOpCostAVX2( 4503 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 4504 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 4505 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 4506 4507 if (UseMaskForCond || UseMaskForGaps) 4508 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4509 Alignment, AddressSpace, CostKind, 4510 UseMaskForCond, UseMaskForGaps); 4511 4512 // We currently Support only fully-interleaved groups, with no gaps. 4513 // TODO: Support also strided loads (interleaved-groups with gaps). 4514 if (Indices.size() && Indices.size() != Factor) 4515 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4516 Alignment, AddressSpace, 4517 CostKind); 4518 4519 // VecTy for interleave memop is <VF*Factor x Elt>. 4520 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4521 // VecTy = <12 x i32>. 4522 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4523 4524 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 4525 // the VF=2, while v2i128 is an unsupported MVT vector type 4526 // (see MachineValueType.h::getVectorVT()). 4527 if (!LegalVT.isVector()) 4528 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4529 Alignment, AddressSpace, 4530 CostKind); 4531 4532 unsigned VF = VecTy->getNumElements() / Factor; 4533 Type *ScalarTy = VecTy->getElementType(); 4534 4535 // Calculate the number of memory operations (NumOfMemOps), required 4536 // for load/store the VecTy. 4537 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4538 unsigned LegalVTSize = LegalVT.getStoreSize(); 4539 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4540 4541 // Get the cost of one memory operation. 4542 auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(), 4543 LegalVT.getVectorNumElements()); 4544 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 4545 MaybeAlign(Alignment), AddressSpace, 4546 CostKind); 4547 4548 auto *VT = FixedVectorType::get(ScalarTy, VF); 4549 EVT ETy = TLI->getValueType(DL, VT); 4550 if (!ETy.isSimple()) 4551 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4552 Alignment, AddressSpace, 4553 CostKind); 4554 4555 // TODO: Complete for other data-types and strides. 4556 // Each combination of Stride, ElementTy and VF results in a different 4557 // sequence; The cost tables are therefore accessed with: 4558 // Factor (stride) and VectorType=VFxElemType. 4559 // The Cost accounts only for the shuffle sequence; 4560 // The cost of the loads/stores is accounted for separately. 4561 // 4562 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 4563 { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64 4564 { 2, MVT::v4f64, 6 }, //(load 8f64 and) deinterleave into 2 x 4f64 4565 4566 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8 4567 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8 4568 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8 4569 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8 4570 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8 4571 { 3, MVT::v8f32, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32 4572 4573 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8 4574 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8 4575 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8 4576 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8 4577 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8 4578 4579 { 8, MVT::v8f32, 40 } //(load 64f32 and)deinterleave into 8 x 8f32 4580 }; 4581 4582 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 4583 { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store) 4584 { 2, MVT::v4f64, 6 }, //interleave into 2 x 4f64 into 8f64 (and store) 4585 4586 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store) 4587 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store) 4588 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store) 4589 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store) 4590 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store) 4591 4592 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store) 4593 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store) 4594 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store) 4595 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store) 4596 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store) 4597 }; 4598 4599 if (Opcode == Instruction::Load) { 4600 if (const auto *Entry = 4601 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 4602 return NumOfMemOps * MemOpCost + Entry->Cost; 4603 } else { 4604 assert(Opcode == Instruction::Store && 4605 "Expected Store Instruction at this point"); 4606 if (const auto *Entry = 4607 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 4608 return NumOfMemOps * MemOpCost + Entry->Cost; 4609 } 4610 4611 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4612 Alignment, AddressSpace, CostKind); 4613 } 4614 4615 // Get estimation for interleaved load/store operations and strided load. 4616 // \p Indices contains indices for strided load. 4617 // \p Factor - the factor of interleaving. 4618 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 4619 int X86TTIImpl::getInterleavedMemoryOpCostAVX512( 4620 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 4621 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 4622 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 4623 4624 if (UseMaskForCond || UseMaskForGaps) 4625 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4626 Alignment, AddressSpace, CostKind, 4627 UseMaskForCond, UseMaskForGaps); 4628 4629 // VecTy for interleave memop is <VF*Factor x Elt>. 4630 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4631 // VecTy = <12 x i32>. 4632 4633 // Calculate the number of memory operations (NumOfMemOps), required 4634 // for load/store the VecTy. 4635 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4636 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4637 unsigned LegalVTSize = LegalVT.getStoreSize(); 4638 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4639 4640 // Get the cost of one memory operation. 4641 auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(), 4642 LegalVT.getVectorNumElements()); 4643 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 4644 MaybeAlign(Alignment), AddressSpace, 4645 CostKind); 4646 4647 unsigned VF = VecTy->getNumElements() / Factor; 4648 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 4649 4650 if (Opcode == Instruction::Load) { 4651 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 4652 // contain the cost of the optimized shuffle sequence that the 4653 // X86InterleavedAccess pass will generate. 4654 // The cost of loads and stores are computed separately from the table. 4655 4656 // X86InterleavedAccess support only the following interleaved-access group. 4657 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 4658 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 4659 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 4660 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 4661 }; 4662 4663 if (const auto *Entry = 4664 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 4665 return NumOfMemOps * MemOpCost + Entry->Cost; 4666 //If an entry does not exist, fallback to the default implementation. 4667 4668 // Kind of shuffle depends on number of loaded values. 4669 // If we load the entire data in one register, we can use a 1-src shuffle. 4670 // Otherwise, we'll merge 2 sources in each operation. 4671 TTI::ShuffleKind ShuffleKind = 4672 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 4673 4674 unsigned ShuffleCost = 4675 getShuffleCost(ShuffleKind, SingleMemOpTy, None, 0, nullptr); 4676 4677 unsigned NumOfLoadsInInterleaveGrp = 4678 Indices.size() ? Indices.size() : Factor; 4679 auto *ResultTy = FixedVectorType::get(VecTy->getElementType(), 4680 VecTy->getNumElements() / Factor); 4681 unsigned NumOfResults = 4682 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 4683 NumOfLoadsInInterleaveGrp; 4684 4685 // About a half of the loads may be folded in shuffles when we have only 4686 // one result. If we have more than one result, we do not fold loads at all. 4687 unsigned NumOfUnfoldedLoads = 4688 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 4689 4690 // Get a number of shuffle operations per result. 4691 unsigned NumOfShufflesPerResult = 4692 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 4693 4694 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4695 // When we have more than one destination, we need additional instructions 4696 // to keep sources. 4697 unsigned NumOfMoves = 0; 4698 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 4699 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 4700 4701 int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 4702 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 4703 4704 return Cost; 4705 } 4706 4707 // Store. 4708 assert(Opcode == Instruction::Store && 4709 "Expected Store Instruction at this point"); 4710 // X86InterleavedAccess support only the following interleaved-access group. 4711 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 4712 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 4713 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 4714 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 4715 4716 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 4717 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 4718 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 4719 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 4720 }; 4721 4722 if (const auto *Entry = 4723 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 4724 return NumOfMemOps * MemOpCost + Entry->Cost; 4725 //If an entry does not exist, fallback to the default implementation. 4726 4727 // There is no strided stores meanwhile. And store can't be folded in 4728 // shuffle. 4729 unsigned NumOfSources = Factor; // The number of values to be merged. 4730 unsigned ShuffleCost = 4731 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, None, 0, nullptr); 4732 unsigned NumOfShufflesPerStore = NumOfSources - 1; 4733 4734 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4735 // We need additional instructions to keep sources. 4736 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 4737 int Cost = NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 4738 NumOfMoves; 4739 return Cost; 4740 } 4741 4742 int X86TTIImpl::getInterleavedMemoryOpCost( 4743 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, 4744 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, 4745 bool UseMaskForCond, bool UseMaskForGaps) { 4746 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 4747 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 4748 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 4749 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 4750 return true; 4751 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 4752 return HasBW; 4753 return false; 4754 }; 4755 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 4756 return getInterleavedMemoryOpCostAVX512( 4757 Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment, 4758 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 4759 if (ST->hasAVX2()) 4760 return getInterleavedMemoryOpCostAVX2( 4761 Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment, 4762 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 4763 4764 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4765 Alignment, AddressSpace, CostKind, 4766 UseMaskForCond, UseMaskForGaps); 4767 } 4768