1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // X86 cost model. 56 // 57 //===----------------------------------------------------------------------===// 58 59 TargetTransformInfo::PopcntSupportKind 60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 61 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 62 // TODO: Currently the __builtin_popcount() implementation using SSE3 63 // instructions is inefficient. Once the problem is fixed, we should 64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 66 } 67 68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 69 TargetTransformInfo::CacheLevel Level) const { 70 switch (Level) { 71 case TargetTransformInfo::CacheLevel::L1D: 72 // - Penryn 73 // - Nehalem 74 // - Westmere 75 // - Sandy Bridge 76 // - Ivy Bridge 77 // - Haswell 78 // - Broadwell 79 // - Skylake 80 // - Kabylake 81 return 32 * 1024; // 32 KByte 82 case TargetTransformInfo::CacheLevel::L2D: 83 // - Penryn 84 // - Nehalem 85 // - Westmere 86 // - Sandy Bridge 87 // - Ivy Bridge 88 // - Haswell 89 // - Broadwell 90 // - Skylake 91 // - Kabylake 92 return 256 * 1024; // 256 KByte 93 } 94 95 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 96 } 97 98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 99 TargetTransformInfo::CacheLevel Level) const { 100 // - Penryn 101 // - Nehalem 102 // - Westmere 103 // - Sandy Bridge 104 // - Ivy Bridge 105 // - Haswell 106 // - Broadwell 107 // - Skylake 108 // - Kabylake 109 switch (Level) { 110 case TargetTransformInfo::CacheLevel::L1D: 111 LLVM_FALLTHROUGH; 112 case TargetTransformInfo::CacheLevel::L2D: 113 return 8; 114 } 115 116 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 117 } 118 119 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 120 bool Vector = (ClassID == 1); 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 TypeSize 133 X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { 134 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 135 switch (K) { 136 case TargetTransformInfo::RGK_Scalar: 137 return TypeSize::getFixed(ST->is64Bit() ? 64 : 32); 138 case TargetTransformInfo::RGK_FixedWidthVector: 139 if (ST->hasAVX512() && PreferVectorWidth >= 512) 140 return TypeSize::getFixed(512); 141 if (ST->hasAVX() && PreferVectorWidth >= 256) 142 return TypeSize::getFixed(256); 143 if (ST->hasSSE1() && PreferVectorWidth >= 128) 144 return TypeSize::getFixed(128); 145 return TypeSize::getFixed(0); 146 case TargetTransformInfo::RGK_ScalableVector: 147 return TypeSize::getScalable(0); 148 } 149 150 llvm_unreachable("Unsupported register kind"); 151 } 152 153 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 154 return getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector) 155 .getFixedSize(); 156 } 157 158 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 159 // If the loop will not be vectorized, don't interleave the loop. 160 // Let regular unroll to unroll the loop, which saves the overflow 161 // check and memory check cost. 162 if (VF == 1) 163 return 1; 164 165 if (ST->isAtom()) 166 return 1; 167 168 // Sandybridge and Haswell have multiple execution ports and pipelined 169 // vector units. 170 if (ST->hasAVX()) 171 return 4; 172 173 return 2; 174 } 175 176 InstructionCost X86TTIImpl::getArithmeticInstrCost( 177 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, 178 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 179 TTI::OperandValueProperties Opd1PropInfo, 180 TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, 181 const Instruction *CxtI) { 182 // TODO: Handle more cost kinds. 183 if (CostKind != TTI::TCK_RecipThroughput) 184 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, 185 Op2Info, Opd1PropInfo, 186 Opd2PropInfo, Args, CxtI); 187 188 // vXi8 multiplications are always promoted to vXi16. 189 if (Opcode == Instruction::Mul && Ty->isVectorTy() && 190 Ty->getScalarSizeInBits() == 8) { 191 Type *WideVecTy = 192 VectorType::getExtendedElementVectorType(cast<VectorType>(Ty)); 193 return getCastInstrCost(Instruction::ZExt, WideVecTy, Ty, 194 TargetTransformInfo::CastContextHint::None, 195 CostKind) + 196 getCastInstrCost(Instruction::Trunc, Ty, WideVecTy, 197 TargetTransformInfo::CastContextHint::None, 198 CostKind) + 199 getArithmeticInstrCost(Opcode, WideVecTy, CostKind, Op1Info, Op2Info, 200 Opd1PropInfo, Opd2PropInfo); 201 } 202 203 // Legalize the type. 204 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 205 206 int ISD = TLI->InstructionOpcodeToISD(Opcode); 207 assert(ISD && "Invalid opcode"); 208 209 if (ISD == ISD::MUL && Args.size() == 2 && LT.second.isVector() && 210 LT.second.getScalarType() == MVT::i32) { 211 // Check if the operands can be represented as a smaller datatype. 212 bool Op1Signed = false, Op2Signed = false; 213 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 214 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 215 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 216 217 // If both are representable as i15 and at least one is constant, 218 // zero-extended, or sign-extended from vXi16 (or less pre-SSE41) then we 219 // can treat this as PMADDWD which has the same costs as a vXi16 multiply. 220 if (OpMinSize <= 15 && !ST->isPMADDWDSlow()) { 221 bool Op1Constant = 222 isa<ConstantDataVector>(Args[0]) || isa<ConstantVector>(Args[0]); 223 bool Op2Constant = 224 isa<ConstantDataVector>(Args[1]) || isa<ConstantVector>(Args[1]); 225 bool Op1Sext = isa<SExtInst>(Args[0]) && 226 (Op1MinSize == 15 || (Op1MinSize < 15 && !ST->hasSSE41())); 227 bool Op2Sext = isa<SExtInst>(Args[1]) && 228 (Op2MinSize == 15 || (Op2MinSize < 15 && !ST->hasSSE41())); 229 230 bool IsZeroExtended = !Op1Signed || !Op2Signed; 231 bool IsConstant = Op1Constant || Op2Constant; 232 bool IsSext = Op1Sext || Op2Sext; 233 if (IsConstant || IsZeroExtended || IsSext) 234 LT.second = 235 MVT::getVectorVT(MVT::i16, 2 * LT.second.getVectorNumElements()); 236 } 237 } 238 239 if ((ISD == ISD::MUL || ISD == ISD::SDIV || ISD == ISD::SREM || 240 ISD == ISD::UDIV || ISD == ISD::UREM) && 241 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 242 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 243 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 244 // Vector multiply by pow2 will be simplified to shifts. 245 if (ISD == ISD::MUL) { 246 InstructionCost Cost = getArithmeticInstrCost( 247 Instruction::Shl, Ty, CostKind, Op1Info, Op2Info, 248 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 249 return Cost; 250 } 251 252 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 253 // On X86, vector signed division by constants power-of-two are 254 // normally expanded to the sequence SRA + SRL + ADD + SRA. 255 // The OperandValue properties may not be the same as that of the previous 256 // operation; conservatively assume OP_None. 257 InstructionCost Cost = 258 2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Op1Info, 259 Op2Info, TargetTransformInfo::OP_None, 260 TargetTransformInfo::OP_None); 261 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 262 Op2Info, TargetTransformInfo::OP_None, 263 TargetTransformInfo::OP_None); 264 Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind, Op1Info, 265 Op2Info, TargetTransformInfo::OP_None, 266 TargetTransformInfo::OP_None); 267 268 if (ISD == ISD::SREM) { 269 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 270 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info, 271 Op2Info); 272 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info, 273 Op2Info); 274 } 275 276 return Cost; 277 } 278 279 // Vector unsigned division/remainder will be simplified to shifts/masks. 280 if (ISD == ISD::UDIV) 281 return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 282 Op2Info, TargetTransformInfo::OP_None, 283 TargetTransformInfo::OP_None); 284 // UREM 285 return getArithmeticInstrCost(Instruction::And, Ty, CostKind, Op1Info, 286 Op2Info, TargetTransformInfo::OP_None, 287 TargetTransformInfo::OP_None); 288 } 289 290 static const CostTblEntry GLMCostTable[] = { 291 { ISD::FDIV, MVT::f32, 18 }, // divss 292 { ISD::FDIV, MVT::v4f32, 35 }, // divps 293 { ISD::FDIV, MVT::f64, 33 }, // divsd 294 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 295 }; 296 297 if (ST->useGLMDivSqrtCosts()) 298 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 299 LT.second)) 300 return LT.first * Entry->Cost; 301 302 static const CostTblEntry SLMCostTable[] = { 303 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 304 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 305 { ISD::FMUL, MVT::f64, 2 }, // mulsd 306 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 307 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 308 { ISD::FDIV, MVT::f32, 17 }, // divss 309 { ISD::FDIV, MVT::v4f32, 39 }, // divps 310 { ISD::FDIV, MVT::f64, 32 }, // divsd 311 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 312 { ISD::FADD, MVT::v2f64, 2 }, // addpd 313 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 314 // v2i64/v4i64 mul is custom lowered as a series of long: 315 // multiplies(3), shifts(3) and adds(2) 316 // slm muldq version throughput is 2 and addq throughput 4 317 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 318 // 3X4 (addq throughput) = 17 319 { ISD::MUL, MVT::v2i64, 17 }, 320 // slm addq\subq throughput is 4 321 { ISD::ADD, MVT::v2i64, 4 }, 322 { ISD::SUB, MVT::v2i64, 4 }, 323 }; 324 325 if (ST->useSLMArithCosts()) { 326 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 327 // Check if the operands can be shrinked into a smaller datatype. 328 // TODO: Merge this into generiic vXi32 MUL patterns above. 329 bool Op1Signed = false; 330 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 331 bool Op2Signed = false; 332 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 333 334 bool SignedMode = Op1Signed || Op2Signed; 335 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 336 337 if (OpMinSize <= 7) 338 return LT.first * 3; // pmullw/sext 339 if (!SignedMode && OpMinSize <= 8) 340 return LT.first * 3; // pmullw/zext 341 if (OpMinSize <= 15) 342 return LT.first * 5; // pmullw/pmulhw/pshuf 343 if (!SignedMode && OpMinSize <= 16) 344 return LT.first * 5; // pmullw/pmulhw/pshuf 345 } 346 347 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 348 LT.second)) { 349 return LT.first * Entry->Cost; 350 } 351 } 352 353 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 354 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 355 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 356 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 357 }; 358 359 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 360 ST->hasBWI()) { 361 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 362 LT.second)) 363 return LT.first * Entry->Cost; 364 } 365 366 static const CostTblEntry AVX512UniformConstCostTable[] = { 367 { ISD::SRA, MVT::v2i64, 1 }, 368 { ISD::SRA, MVT::v4i64, 1 }, 369 { ISD::SRA, MVT::v8i64, 1 }, 370 371 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 372 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 373 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 374 375 { ISD::SDIV, MVT::v16i32, 6 }, // pmuludq sequence 376 { ISD::SREM, MVT::v16i32, 8 }, // pmuludq+mul+sub sequence 377 { ISD::UDIV, MVT::v16i32, 5 }, // pmuludq sequence 378 { ISD::UREM, MVT::v16i32, 7 }, // pmuludq+mul+sub sequence 379 }; 380 381 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 382 ST->hasAVX512()) { 383 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 384 LT.second)) 385 return LT.first * Entry->Cost; 386 } 387 388 static const CostTblEntry AVX2UniformConstCostTable[] = { 389 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 390 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 391 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 392 393 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 394 395 { ISD::SDIV, MVT::v8i32, 6 }, // pmuludq sequence 396 { ISD::SREM, MVT::v8i32, 8 }, // pmuludq+mul+sub sequence 397 { ISD::UDIV, MVT::v8i32, 5 }, // pmuludq sequence 398 { ISD::UREM, MVT::v8i32, 7 }, // pmuludq+mul+sub sequence 399 }; 400 401 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 402 ST->hasAVX2()) { 403 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 404 LT.second)) 405 return LT.first * Entry->Cost; 406 } 407 408 static const CostTblEntry SSE2UniformConstCostTable[] = { 409 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 410 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 411 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 412 413 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 414 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 415 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 416 417 { ISD::SDIV, MVT::v8i32, 12+2 }, // 2*pmuludq sequence + split. 418 { ISD::SREM, MVT::v8i32, 16+2 }, // 2*pmuludq+mul+sub sequence + split. 419 { ISD::SDIV, MVT::v4i32, 6 }, // pmuludq sequence 420 { ISD::SREM, MVT::v4i32, 8 }, // pmuludq+mul+sub sequence 421 { ISD::UDIV, MVT::v8i32, 10+2 }, // 2*pmuludq sequence + split. 422 { ISD::UREM, MVT::v8i32, 14+2 }, // 2*pmuludq+mul+sub sequence + split. 423 { ISD::UDIV, MVT::v4i32, 5 }, // pmuludq sequence 424 { ISD::UREM, MVT::v4i32, 7 }, // pmuludq+mul+sub sequence 425 }; 426 427 // XOP has faster vXi8 shifts. 428 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 429 ST->hasSSE2() && !ST->hasXOP()) { 430 if (const auto *Entry = 431 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 432 return LT.first * Entry->Cost; 433 } 434 435 static const CostTblEntry AVX512BWConstCostTable[] = { 436 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 437 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 438 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 439 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 440 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 441 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 442 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 443 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 444 }; 445 446 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 447 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 448 ST->hasBWI()) { 449 if (const auto *Entry = 450 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 451 return LT.first * Entry->Cost; 452 } 453 454 static const CostTblEntry AVX512ConstCostTable[] = { 455 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 456 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 457 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 458 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 459 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 460 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 461 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 462 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 463 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 464 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 465 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 466 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 467 }; 468 469 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 470 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 471 ST->hasAVX512()) { 472 if (const auto *Entry = 473 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 474 return LT.first * Entry->Cost; 475 } 476 477 static const CostTblEntry AVX2ConstCostTable[] = { 478 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 479 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 480 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 481 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 482 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 483 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 484 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 485 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 486 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 487 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 488 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 489 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 490 }; 491 492 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 493 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 494 ST->hasAVX2()) { 495 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 496 return LT.first * Entry->Cost; 497 } 498 499 static const CostTblEntry SSE2ConstCostTable[] = { 500 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 501 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 502 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 503 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 504 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 505 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 506 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 507 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 508 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 509 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 510 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 511 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 512 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 513 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 514 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 515 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 516 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 517 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 518 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 519 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 520 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 521 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 522 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 523 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 524 }; 525 526 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 527 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 528 ST->hasSSE2()) { 529 // pmuldq sequence. 530 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 531 return LT.first * 32; 532 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 533 return LT.first * 38; 534 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 535 return LT.first * 15; 536 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 537 return LT.first * 20; 538 539 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 540 return LT.first * Entry->Cost; 541 } 542 543 static const CostTblEntry AVX512BWShiftCostTable[] = { 544 { ISD::SHL, MVT::v16i8, 4 }, // extend/vpsllvw/pack sequence. 545 { ISD::SRL, MVT::v16i8, 4 }, // extend/vpsrlvw/pack sequence. 546 { ISD::SRA, MVT::v16i8, 4 }, // extend/vpsravw/pack sequence. 547 { ISD::SHL, MVT::v32i8, 4 }, // extend/vpsllvw/pack sequence. 548 { ISD::SRL, MVT::v32i8, 4 }, // extend/vpsrlvw/pack sequence. 549 { ISD::SRA, MVT::v32i8, 6 }, // extend/vpsravw/pack sequence. 550 { ISD::SHL, MVT::v64i8, 6 }, // extend/vpsllvw/pack sequence. 551 { ISD::SRL, MVT::v64i8, 7 }, // extend/vpsrlvw/pack sequence. 552 { ISD::SRA, MVT::v64i8, 15 }, // extend/vpsravw/pack sequence. 553 554 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 555 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 556 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 557 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 558 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 559 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 560 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 561 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 562 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 563 }; 564 565 if (ST->hasBWI()) 566 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 567 return LT.first * Entry->Cost; 568 569 static const CostTblEntry AVX2UniformCostTable[] = { 570 // Uniform splats are cheaper for the following instructions. 571 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 572 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 573 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 574 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 575 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 576 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 577 578 { ISD::SHL, MVT::v8i32, 1 }, // pslld 579 { ISD::SRL, MVT::v8i32, 1 }, // psrld 580 { ISD::SRA, MVT::v8i32, 1 }, // psrad 581 { ISD::SHL, MVT::v4i64, 1 }, // psllq 582 { ISD::SRL, MVT::v4i64, 1 }, // psrlq 583 }; 584 585 if (ST->hasAVX2() && 586 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 587 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 588 if (const auto *Entry = 589 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 590 return LT.first * Entry->Cost; 591 } 592 593 static const CostTblEntry SSE2UniformCostTable[] = { 594 // Uniform splats are cheaper for the following instructions. 595 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 596 { ISD::SHL, MVT::v4i32, 1 }, // pslld 597 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 598 599 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 600 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 601 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 602 603 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 604 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 605 }; 606 607 if (ST->hasSSE2() && 608 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 609 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 610 if (const auto *Entry = 611 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 612 return LT.first * Entry->Cost; 613 } 614 615 static const CostTblEntry AVX512DQCostTable[] = { 616 { ISD::MUL, MVT::v2i64, 2 }, // pmullq 617 { ISD::MUL, MVT::v4i64, 2 }, // pmullq 618 { ISD::MUL, MVT::v8i64, 2 } // pmullq 619 }; 620 621 // Look for AVX512DQ lowering tricks for custom cases. 622 if (ST->hasDQI()) 623 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 624 return LT.first * Entry->Cost; 625 626 static const CostTblEntry AVX512BWCostTable[] = { 627 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 628 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 629 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 630 }; 631 632 // Look for AVX512BW lowering tricks for custom cases. 633 if (ST->hasBWI()) 634 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 635 return LT.first * Entry->Cost; 636 637 static const CostTblEntry AVX512CostTable[] = { 638 { ISD::SHL, MVT::v4i32, 1 }, 639 { ISD::SRL, MVT::v4i32, 1 }, 640 { ISD::SRA, MVT::v4i32, 1 }, 641 { ISD::SHL, MVT::v8i32, 1 }, 642 { ISD::SRL, MVT::v8i32, 1 }, 643 { ISD::SRA, MVT::v8i32, 1 }, 644 { ISD::SHL, MVT::v16i32, 1 }, 645 { ISD::SRL, MVT::v16i32, 1 }, 646 { ISD::SRA, MVT::v16i32, 1 }, 647 648 { ISD::SHL, MVT::v2i64, 1 }, 649 { ISD::SRL, MVT::v2i64, 1 }, 650 { ISD::SHL, MVT::v4i64, 1 }, 651 { ISD::SRL, MVT::v4i64, 1 }, 652 { ISD::SHL, MVT::v8i64, 1 }, 653 { ISD::SRL, MVT::v8i64, 1 }, 654 655 { ISD::SRA, MVT::v2i64, 1 }, 656 { ISD::SRA, MVT::v4i64, 1 }, 657 { ISD::SRA, MVT::v8i64, 1 }, 658 659 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 660 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 661 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 662 { ISD::MUL, MVT::v8i64, 6 }, // 3*pmuludq/3*shift/2*add 663 { ISD::MUL, MVT::i64, 1 }, // Skylake from http://www.agner.org/ 664 665 { ISD::FNEG, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 666 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 667 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 668 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 669 { ISD::FDIV, MVT::f64, 4 }, // Skylake from http://www.agner.org/ 670 { ISD::FDIV, MVT::v2f64, 4 }, // Skylake from http://www.agner.org/ 671 { ISD::FDIV, MVT::v4f64, 8 }, // Skylake from http://www.agner.org/ 672 { ISD::FDIV, MVT::v8f64, 16 }, // Skylake from http://www.agner.org/ 673 674 { ISD::FNEG, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 675 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 676 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 677 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 678 { ISD::FDIV, MVT::f32, 3 }, // Skylake from http://www.agner.org/ 679 { ISD::FDIV, MVT::v4f32, 3 }, // Skylake from http://www.agner.org/ 680 { ISD::FDIV, MVT::v8f32, 5 }, // Skylake from http://www.agner.org/ 681 { ISD::FDIV, MVT::v16f32, 10 }, // Skylake from http://www.agner.org/ 682 }; 683 684 if (ST->hasAVX512()) 685 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 686 return LT.first * Entry->Cost; 687 688 static const CostTblEntry AVX2ShiftCostTable[] = { 689 // Shifts on vXi64/vXi32 on AVX2 is legal even though we declare to 690 // customize them to detect the cases where shift amount is a scalar one. 691 { ISD::SHL, MVT::v4i32, 2 }, // vpsllvd (Haswell from agner.org) 692 { ISD::SRL, MVT::v4i32, 2 }, // vpsrlvd (Haswell from agner.org) 693 { ISD::SRA, MVT::v4i32, 2 }, // vpsravd (Haswell from agner.org) 694 { ISD::SHL, MVT::v8i32, 2 }, // vpsllvd (Haswell from agner.org) 695 { ISD::SRL, MVT::v8i32, 2 }, // vpsrlvd (Haswell from agner.org) 696 { ISD::SRA, MVT::v8i32, 2 }, // vpsravd (Haswell from agner.org) 697 { ISD::SHL, MVT::v2i64, 1 }, // vpsllvq (Haswell from agner.org) 698 { ISD::SRL, MVT::v2i64, 1 }, // vpsrlvq (Haswell from agner.org) 699 { ISD::SHL, MVT::v4i64, 1 }, // vpsllvq (Haswell from agner.org) 700 { ISD::SRL, MVT::v4i64, 1 }, // vpsrlvq (Haswell from agner.org) 701 }; 702 703 if (ST->hasAVX512()) { 704 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 705 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 706 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 707 // On AVX512, a packed v32i16 shift left by a constant build_vector 708 // is lowered into a vector multiply (vpmullw). 709 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 710 Op1Info, Op2Info, 711 TargetTransformInfo::OP_None, 712 TargetTransformInfo::OP_None); 713 } 714 715 // Look for AVX2 lowering tricks (XOP is always better at v4i32 shifts). 716 if (ST->hasAVX2() && !(ST->hasXOP() && LT.second == MVT::v4i32)) { 717 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 718 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 719 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 720 // On AVX2, a packed v16i16 shift left by a constant build_vector 721 // is lowered into a vector multiply (vpmullw). 722 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 723 Op1Info, Op2Info, 724 TargetTransformInfo::OP_None, 725 TargetTransformInfo::OP_None); 726 727 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 728 return LT.first * Entry->Cost; 729 } 730 731 static const CostTblEntry XOPShiftCostTable[] = { 732 // 128bit shifts take 1cy, but right shifts require negation beforehand. 733 { ISD::SHL, MVT::v16i8, 1 }, 734 { ISD::SRL, MVT::v16i8, 2 }, 735 { ISD::SRA, MVT::v16i8, 2 }, 736 { ISD::SHL, MVT::v8i16, 1 }, 737 { ISD::SRL, MVT::v8i16, 2 }, 738 { ISD::SRA, MVT::v8i16, 2 }, 739 { ISD::SHL, MVT::v4i32, 1 }, 740 { ISD::SRL, MVT::v4i32, 2 }, 741 { ISD::SRA, MVT::v4i32, 2 }, 742 { ISD::SHL, MVT::v2i64, 1 }, 743 { ISD::SRL, MVT::v2i64, 2 }, 744 { ISD::SRA, MVT::v2i64, 2 }, 745 // 256bit shifts require splitting if AVX2 didn't catch them above. 746 { ISD::SHL, MVT::v32i8, 2+2 }, 747 { ISD::SRL, MVT::v32i8, 4+2 }, 748 { ISD::SRA, MVT::v32i8, 4+2 }, 749 { ISD::SHL, MVT::v16i16, 2+2 }, 750 { ISD::SRL, MVT::v16i16, 4+2 }, 751 { ISD::SRA, MVT::v16i16, 4+2 }, 752 { ISD::SHL, MVT::v8i32, 2+2 }, 753 { ISD::SRL, MVT::v8i32, 4+2 }, 754 { ISD::SRA, MVT::v8i32, 4+2 }, 755 { ISD::SHL, MVT::v4i64, 2+2 }, 756 { ISD::SRL, MVT::v4i64, 4+2 }, 757 { ISD::SRA, MVT::v4i64, 4+2 }, 758 }; 759 760 // Look for XOP lowering tricks. 761 if (ST->hasXOP()) { 762 // If the right shift is constant then we'll fold the negation so 763 // it's as cheap as a left shift. 764 int ShiftISD = ISD; 765 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 766 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 767 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 768 ShiftISD = ISD::SHL; 769 if (const auto *Entry = 770 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 771 return LT.first * Entry->Cost; 772 } 773 774 static const CostTblEntry SSE2UniformShiftCostTable[] = { 775 // Uniform splats are cheaper for the following instructions. 776 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 777 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 778 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 779 780 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 781 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 782 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 783 784 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 785 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 786 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 787 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 788 }; 789 790 if (ST->hasSSE2() && 791 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 792 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 793 794 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 795 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 796 return LT.first * 4; // 2*psrad + shuffle. 797 798 if (const auto *Entry = 799 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 800 return LT.first * Entry->Cost; 801 } 802 803 if (ISD == ISD::SHL && 804 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 805 MVT VT = LT.second; 806 // Vector shift left by non uniform constant can be lowered 807 // into vector multiply. 808 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 809 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 810 ISD = ISD::MUL; 811 } 812 813 static const CostTblEntry AVX2CostTable[] = { 814 { ISD::SHL, MVT::v16i8, 6 }, // vpblendvb sequence. 815 { ISD::SHL, MVT::v32i8, 6 }, // vpblendvb sequence. 816 { ISD::SHL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 817 { ISD::SHL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 818 { ISD::SHL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 819 { ISD::SHL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 820 821 { ISD::SRL, MVT::v16i8, 6 }, // vpblendvb sequence. 822 { ISD::SRL, MVT::v32i8, 6 }, // vpblendvb sequence. 823 { ISD::SRL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 824 { ISD::SRL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 825 { ISD::SRL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 826 { ISD::SRL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 827 828 { ISD::SRA, MVT::v16i8, 17 }, // vpblendvb sequence. 829 { ISD::SRA, MVT::v32i8, 17 }, // vpblendvb sequence. 830 { ISD::SRA, MVT::v64i8, 34 }, // 2*vpblendvb sequence. 831 { ISD::SRA, MVT::v8i16, 5 }, // extend/vpsravd/pack sequence. 832 { ISD::SRA, MVT::v16i16, 7 }, // extend/vpsravd/pack sequence. 833 { ISD::SRA, MVT::v32i16, 14 }, // 2*extend/vpsravd/pack sequence. 834 { ISD::SRA, MVT::v2i64, 2 }, // srl/xor/sub sequence. 835 { ISD::SRA, MVT::v4i64, 2 }, // srl/xor/sub sequence. 836 837 { ISD::SUB, MVT::v32i8, 1 }, // psubb 838 { ISD::ADD, MVT::v32i8, 1 }, // paddb 839 { ISD::SUB, MVT::v16i16, 1 }, // psubw 840 { ISD::ADD, MVT::v16i16, 1 }, // paddw 841 { ISD::SUB, MVT::v8i32, 1 }, // psubd 842 { ISD::ADD, MVT::v8i32, 1 }, // paddd 843 { ISD::SUB, MVT::v4i64, 1 }, // psubq 844 { ISD::ADD, MVT::v4i64, 1 }, // paddq 845 846 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 847 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 848 { ISD::MUL, MVT::v4i64, 6 }, // 3*pmuludq/3*shift/2*add 849 850 { ISD::FNEG, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 851 { ISD::FNEG, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 852 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 853 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 854 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 855 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 856 { ISD::FMUL, MVT::f64, 1 }, // Haswell from http://www.agner.org/ 857 { ISD::FMUL, MVT::v2f64, 1 }, // Haswell from http://www.agner.org/ 858 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 859 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 860 861 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 862 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 863 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 864 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 865 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 866 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 867 }; 868 869 // Look for AVX2 lowering tricks for custom cases. 870 if (ST->hasAVX2()) 871 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 872 return LT.first * Entry->Cost; 873 874 static const CostTblEntry AVX1CostTable[] = { 875 // We don't have to scalarize unsupported ops. We can issue two half-sized 876 // operations and we only need to extract the upper YMM half. 877 // Two ops + 1 extract + 1 insert = 4. 878 { ISD::MUL, MVT::v16i16, 4 }, 879 { ISD::MUL, MVT::v8i32, 5 }, // BTVER2 from http://www.agner.org/ 880 { ISD::MUL, MVT::v4i64, 12 }, 881 882 { ISD::SUB, MVT::v32i8, 4 }, 883 { ISD::ADD, MVT::v32i8, 4 }, 884 { ISD::SUB, MVT::v16i16, 4 }, 885 { ISD::ADD, MVT::v16i16, 4 }, 886 { ISD::SUB, MVT::v8i32, 4 }, 887 { ISD::ADD, MVT::v8i32, 4 }, 888 { ISD::SUB, MVT::v4i64, 4 }, 889 { ISD::ADD, MVT::v4i64, 4 }, 890 891 { ISD::SHL, MVT::v32i8, 22 }, // pblendvb sequence + split. 892 { ISD::SHL, MVT::v8i16, 6 }, // pblendvb sequence. 893 { ISD::SHL, MVT::v16i16, 13 }, // pblendvb sequence + split. 894 { ISD::SHL, MVT::v4i32, 3 }, // pslld/paddd/cvttps2dq/pmulld 895 { ISD::SHL, MVT::v8i32, 9 }, // pslld/paddd/cvttps2dq/pmulld + split 896 { ISD::SHL, MVT::v2i64, 2 }, // Shift each lane + blend. 897 { ISD::SHL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 898 899 { ISD::SRL, MVT::v32i8, 23 }, // pblendvb sequence + split. 900 { ISD::SRL, MVT::v16i16, 28 }, // pblendvb sequence + split. 901 { ISD::SRL, MVT::v4i32, 6 }, // Shift each lane + blend. 902 { ISD::SRL, MVT::v8i32, 14 }, // Shift each lane + blend + split. 903 { ISD::SRL, MVT::v2i64, 2 }, // Shift each lane + blend. 904 { ISD::SRL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 905 906 { ISD::SRA, MVT::v32i8, 44 }, // pblendvb sequence + split. 907 { ISD::SRA, MVT::v16i16, 28 }, // pblendvb sequence + split. 908 { ISD::SRA, MVT::v4i32, 6 }, // Shift each lane + blend. 909 { ISD::SRA, MVT::v8i32, 14 }, // Shift each lane + blend + split. 910 { ISD::SRA, MVT::v2i64, 5 }, // Shift each lane + blend. 911 { ISD::SRA, MVT::v4i64, 12 }, // Shift each lane + blend + split. 912 913 { ISD::FNEG, MVT::v4f64, 2 }, // BTVER2 from http://www.agner.org/ 914 { ISD::FNEG, MVT::v8f32, 2 }, // BTVER2 from http://www.agner.org/ 915 916 { ISD::FMUL, MVT::f64, 2 }, // BTVER2 from http://www.agner.org/ 917 { ISD::FMUL, MVT::v2f64, 2 }, // BTVER2 from http://www.agner.org/ 918 { ISD::FMUL, MVT::v4f64, 4 }, // BTVER2 from http://www.agner.org/ 919 920 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 921 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 922 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 923 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 924 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 925 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 926 }; 927 928 if (ST->hasAVX()) 929 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 930 return LT.first * Entry->Cost; 931 932 static const CostTblEntry SSE42CostTable[] = { 933 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 934 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 935 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 936 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 937 938 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 939 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 940 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 941 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 942 943 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 944 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 945 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 946 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 947 948 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 949 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 950 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 951 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 952 953 { ISD::MUL, MVT::v2i64, 6 } // 3*pmuludq/3*shift/2*add 954 }; 955 956 if (ST->hasSSE42()) 957 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 958 return LT.first * Entry->Cost; 959 960 static const CostTblEntry SSE41CostTable[] = { 961 { ISD::SHL, MVT::v16i8, 10 }, // pblendvb sequence. 962 { ISD::SHL, MVT::v8i16, 11 }, // pblendvb sequence. 963 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 964 965 { ISD::SRL, MVT::v16i8, 11 }, // pblendvb sequence. 966 { ISD::SRL, MVT::v8i16, 13 }, // pblendvb sequence. 967 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 968 969 { ISD::SRA, MVT::v16i8, 21 }, // pblendvb sequence. 970 { ISD::SRA, MVT::v8i16, 13 }, // pblendvb sequence. 971 972 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 973 }; 974 975 if (ST->hasSSE41()) 976 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 977 return LT.first * Entry->Cost; 978 979 static const CostTblEntry SSE2CostTable[] = { 980 // We don't correctly identify costs of casts because they are marked as 981 // custom. 982 { ISD::SHL, MVT::v16i8, 13 }, // cmpgtb sequence. 983 { ISD::SHL, MVT::v8i16, 25 }, // cmpgtw sequence. 984 { ISD::SHL, MVT::v4i32, 16 }, // pslld/paddd/cvttps2dq/pmuludq. 985 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 986 987 { ISD::SRL, MVT::v16i8, 14 }, // cmpgtb sequence. 988 { ISD::SRL, MVT::v8i16, 16 }, // cmpgtw sequence. 989 { ISD::SRL, MVT::v4i32, 12 }, // Shift each lane + blend. 990 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 991 992 { ISD::SRA, MVT::v16i8, 27 }, // unpacked cmpgtb sequence. 993 { ISD::SRA, MVT::v8i16, 16 }, // cmpgtw sequence. 994 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 995 { ISD::SRA, MVT::v2i64, 8 }, // srl/xor/sub splat+shuffle sequence. 996 997 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 998 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 999 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 1000 1001 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 1002 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 1003 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 1004 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 1005 1006 { ISD::FNEG, MVT::f32, 1 }, // Pentium IV from http://www.agner.org/ 1007 { ISD::FNEG, MVT::f64, 1 }, // Pentium IV from http://www.agner.org/ 1008 { ISD::FNEG, MVT::v4f32, 1 }, // Pentium IV from http://www.agner.org/ 1009 { ISD::FNEG, MVT::v2f64, 1 }, // Pentium IV from http://www.agner.org/ 1010 1011 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 1012 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 1013 1014 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 1015 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 1016 }; 1017 1018 if (ST->hasSSE2()) 1019 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 1020 return LT.first * Entry->Cost; 1021 1022 static const CostTblEntry SSE1CostTable[] = { 1023 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 1024 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 1025 1026 { ISD::FNEG, MVT::f32, 2 }, // Pentium III from http://www.agner.org/ 1027 { ISD::FNEG, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1028 1029 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1030 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1031 1032 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1033 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1034 }; 1035 1036 if (ST->hasSSE1()) 1037 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 1038 return LT.first * Entry->Cost; 1039 1040 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 1041 { ISD::ADD, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1042 { ISD::SUB, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1043 { ISD::MUL, MVT::i64, 2 }, // Nehalem from http://www.agner.org/ 1044 }; 1045 1046 if (ST->is64Bit()) 1047 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, LT.second)) 1048 return LT.first * Entry->Cost; 1049 1050 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 1051 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1052 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1053 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1054 1055 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1056 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1057 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1058 }; 1059 1060 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, LT.second)) 1061 return LT.first * Entry->Cost; 1062 1063 // It is not a good idea to vectorize division. We have to scalarize it and 1064 // in the process we will often end up having to spilling regular 1065 // registers. The overhead of division is going to dominate most kernels 1066 // anyways so try hard to prevent vectorization of division - it is 1067 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 1068 // to hide "20 cycles" for each lane. 1069 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 1070 ISD == ISD::UDIV || ISD == ISD::UREM)) { 1071 InstructionCost ScalarCost = getArithmeticInstrCost( 1072 Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info, 1073 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 1074 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 1075 } 1076 1077 // Fallback to the default implementation. 1078 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info); 1079 } 1080 1081 InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, 1082 VectorType *BaseTp, 1083 ArrayRef<int> Mask, int Index, 1084 VectorType *SubTp) { 1085 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 1086 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 1087 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 1088 1089 Kind = improveShuffleKindFromMask(Kind, Mask); 1090 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 1091 if (Kind == TTI::SK_Transpose) 1092 Kind = TTI::SK_PermuteTwoSrc; 1093 1094 // For Broadcasts we are splatting the first element from the first input 1095 // register, so only need to reference that input and all the output 1096 // registers are the same. 1097 if (Kind == TTI::SK_Broadcast) 1098 LT.first = 1; 1099 1100 // Subvector extractions are free if they start at the beginning of a 1101 // vector and cheap if the subvectors are aligned. 1102 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 1103 int NumElts = LT.second.getVectorNumElements(); 1104 if ((Index % NumElts) == 0) 1105 return 0; 1106 std::pair<InstructionCost, MVT> SubLT = 1107 TLI->getTypeLegalizationCost(DL, SubTp); 1108 if (SubLT.second.isVector()) { 1109 int NumSubElts = SubLT.second.getVectorNumElements(); 1110 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1111 return SubLT.first; 1112 // Handle some cases for widening legalization. For now we only handle 1113 // cases where the original subvector was naturally aligned and evenly 1114 // fit in its legalized subvector type. 1115 // FIXME: Remove some of the alignment restrictions. 1116 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 1117 // vectors. 1118 int OrigSubElts = cast<FixedVectorType>(SubTp)->getNumElements(); 1119 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 1120 (NumSubElts % OrigSubElts) == 0 && 1121 LT.second.getVectorElementType() == 1122 SubLT.second.getVectorElementType() && 1123 LT.second.getVectorElementType().getSizeInBits() == 1124 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 1125 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 1126 "Unexpected number of elements!"); 1127 auto *VecTy = FixedVectorType::get(BaseTp->getElementType(), 1128 LT.second.getVectorNumElements()); 1129 auto *SubTy = FixedVectorType::get(BaseTp->getElementType(), 1130 SubLT.second.getVectorNumElements()); 1131 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 1132 InstructionCost ExtractCost = getShuffleCost( 1133 TTI::SK_ExtractSubvector, VecTy, None, ExtractIndex, SubTy); 1134 1135 // If the original size is 32-bits or more, we can use pshufd. Otherwise 1136 // if we have SSSE3 we can use pshufb. 1137 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 1138 return ExtractCost + 1; // pshufd or pshufb 1139 1140 assert(SubTp->getPrimitiveSizeInBits() == 16 && 1141 "Unexpected vector size"); 1142 1143 return ExtractCost + 2; // worst case pshufhw + pshufd 1144 } 1145 } 1146 } 1147 1148 // Subvector insertions are cheap if the subvectors are aligned. 1149 // Note that in general, the insertion starting at the beginning of a vector 1150 // isn't free, because we need to preserve the rest of the wide vector. 1151 if (Kind == TTI::SK_InsertSubvector && LT.second.isVector()) { 1152 int NumElts = LT.second.getVectorNumElements(); 1153 std::pair<InstructionCost, MVT> SubLT = 1154 TLI->getTypeLegalizationCost(DL, SubTp); 1155 if (SubLT.second.isVector()) { 1156 int NumSubElts = SubLT.second.getVectorNumElements(); 1157 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1158 return SubLT.first; 1159 } 1160 1161 // If the insertion isn't aligned, treat it like a 2-op shuffle. 1162 Kind = TTI::SK_PermuteTwoSrc; 1163 } 1164 1165 // Handle some common (illegal) sub-vector types as they are often very cheap 1166 // to shuffle even on targets without PSHUFB. 1167 EVT VT = TLI->getValueType(DL, BaseTp); 1168 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 1169 !ST->hasSSSE3()) { 1170 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 1171 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 1172 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1173 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1174 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1175 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1176 1177 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1178 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1179 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1180 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1181 1182 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1183 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1184 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1185 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1186 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1187 1188 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1189 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1190 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1191 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1192 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1193 }; 1194 1195 if (ST->hasSSE2()) 1196 if (const auto *Entry = 1197 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1198 return Entry->Cost; 1199 } 1200 1201 // We are going to permute multiple sources and the result will be in multiple 1202 // destinations. Providing an accurate cost only for splits where the element 1203 // type remains the same. 1204 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1205 MVT LegalVT = LT.second; 1206 if (LegalVT.isVector() && 1207 LegalVT.getVectorElementType().getSizeInBits() == 1208 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1209 LegalVT.getVectorNumElements() < 1210 cast<FixedVectorType>(BaseTp)->getNumElements()) { 1211 1212 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1213 unsigned LegalVTSize = LegalVT.getStoreSize(); 1214 // Number of source vectors after legalization: 1215 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1216 // Number of destination vectors after legalization: 1217 InstructionCost NumOfDests = LT.first; 1218 1219 auto *SingleOpTy = FixedVectorType::get(BaseTp->getElementType(), 1220 LegalVT.getVectorNumElements()); 1221 1222 InstructionCost NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1223 return NumOfShuffles * getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 1224 None, 0, nullptr); 1225 } 1226 1227 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1228 } 1229 1230 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1231 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1232 // We assume that source and destination have the same vector type. 1233 InstructionCost NumOfDests = LT.first; 1234 InstructionCost NumOfShufflesPerDest = LT.first * 2 - 1; 1235 LT.first = NumOfDests * NumOfShufflesPerDest; 1236 } 1237 1238 static const CostTblEntry AVX512FP16ShuffleTbl[] = { 1239 {TTI::SK_Broadcast, MVT::v32f16, 1}, // vpbroadcastw 1240 {TTI::SK_Broadcast, MVT::v16f16, 1}, // vpbroadcastw 1241 {TTI::SK_Broadcast, MVT::v8f16, 1}, // vpbroadcastw 1242 1243 {TTI::SK_Reverse, MVT::v32f16, 2}, // vpermw 1244 {TTI::SK_Reverse, MVT::v16f16, 2}, // vpermw 1245 {TTI::SK_Reverse, MVT::v8f16, 1}, // vpshufb 1246 1247 {TTI::SK_PermuteSingleSrc, MVT::v32f16, 2}, // vpermw 1248 {TTI::SK_PermuteSingleSrc, MVT::v16f16, 2}, // vpermw 1249 {TTI::SK_PermuteSingleSrc, MVT::v8f16, 1}, // vpshufb 1250 1251 {TTI::SK_PermuteTwoSrc, MVT::v32f16, 2}, // vpermt2w 1252 {TTI::SK_PermuteTwoSrc, MVT::v16f16, 2}, // vpermt2w 1253 {TTI::SK_PermuteTwoSrc, MVT::v8f16, 2} // vpermt2w 1254 }; 1255 1256 if (!ST->useSoftFloat() && ST->hasFP16()) 1257 if (const auto *Entry = 1258 CostTableLookup(AVX512FP16ShuffleTbl, Kind, LT.second)) 1259 return LT.first * Entry->Cost; 1260 1261 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1262 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1263 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1264 1265 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1266 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1267 1268 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b 1269 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b 1270 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2} // vpermt2b 1271 }; 1272 1273 if (ST->hasVBMI()) 1274 if (const auto *Entry = 1275 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1276 return LT.first * Entry->Cost; 1277 1278 static const CostTblEntry AVX512BWShuffleTbl[] = { 1279 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1280 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1281 1282 {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw 1283 {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw 1284 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1285 1286 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw 1287 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw 1288 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1289 1290 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w 1291 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w 1292 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2}, // vpermt2w 1293 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1294 1295 {TTI::SK_Select, MVT::v32i16, 1}, // vblendmw 1296 {TTI::SK_Select, MVT::v64i8, 1}, // vblendmb 1297 }; 1298 1299 if (ST->hasBWI()) 1300 if (const auto *Entry = 1301 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1302 return LT.first * Entry->Cost; 1303 1304 static const CostTblEntry AVX512ShuffleTbl[] = { 1305 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1306 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1307 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1308 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1309 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1310 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1311 1312 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1313 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1314 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1315 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1316 {TTI::SK_Reverse, MVT::v32i16, 7}, // per mca 1317 {TTI::SK_Reverse, MVT::v64i8, 7}, // per mca 1318 1319 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1320 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1321 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1322 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1323 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1324 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1325 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1326 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1327 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1328 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1329 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1330 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1331 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1332 1333 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1334 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1335 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1336 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1337 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1338 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1339 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1340 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1341 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1342 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1343 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1344 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1345 1346 // FIXME: This just applies the type legalization cost rules above 1347 // assuming these completely split. 1348 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1349 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1350 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1351 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1352 1353 {TTI::SK_Select, MVT::v32i16, 1}, // vpternlogq 1354 {TTI::SK_Select, MVT::v64i8, 1}, // vpternlogq 1355 {TTI::SK_Select, MVT::v8f64, 1}, // vblendmpd 1356 {TTI::SK_Select, MVT::v16f32, 1}, // vblendmps 1357 {TTI::SK_Select, MVT::v8i64, 1}, // vblendmq 1358 {TTI::SK_Select, MVT::v16i32, 1}, // vblendmd 1359 }; 1360 1361 if (ST->hasAVX512()) 1362 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1363 return LT.first * Entry->Cost; 1364 1365 static const CostTblEntry AVX2ShuffleTbl[] = { 1366 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1367 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1368 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1369 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1370 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1371 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1372 1373 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1374 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1375 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1376 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1377 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1378 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1379 1380 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1381 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1382 1383 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1384 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1385 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1386 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1387 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1388 // + vpblendvb 1389 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1390 // + vpblendvb 1391 1392 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1393 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1394 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1395 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1396 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1397 // + vpblendvb 1398 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1399 // + vpblendvb 1400 }; 1401 1402 if (ST->hasAVX2()) 1403 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1404 return LT.first * Entry->Cost; 1405 1406 static const CostTblEntry XOPShuffleTbl[] = { 1407 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1408 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1409 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1410 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1411 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1412 // + vinsertf128 1413 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1414 // + vinsertf128 1415 1416 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1417 // + vinsertf128 1418 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1419 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1420 // + vinsertf128 1421 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1422 }; 1423 1424 if (ST->hasXOP()) 1425 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1426 return LT.first * Entry->Cost; 1427 1428 static const CostTblEntry AVX1ShuffleTbl[] = { 1429 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1430 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1431 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1432 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1433 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1434 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1435 1436 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1437 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1438 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1439 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1440 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1441 // + vinsertf128 1442 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1443 // + vinsertf128 1444 1445 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1446 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1447 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1448 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1449 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1450 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1451 1452 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1453 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1454 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1455 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1456 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1457 // + 2*por + vinsertf128 1458 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1459 // + 2*por + vinsertf128 1460 1461 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1462 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1463 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1464 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1465 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1466 // + 4*por + vinsertf128 1467 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1468 // + 4*por + vinsertf128 1469 }; 1470 1471 if (ST->hasAVX()) 1472 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1473 return LT.first * Entry->Cost; 1474 1475 static const CostTblEntry SSE41ShuffleTbl[] = { 1476 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1477 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1478 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1479 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1480 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1481 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1482 }; 1483 1484 if (ST->hasSSE41()) 1485 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1486 return LT.first * Entry->Cost; 1487 1488 static const CostTblEntry SSSE3ShuffleTbl[] = { 1489 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1490 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1491 1492 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1493 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1494 1495 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1496 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1497 1498 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1499 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1500 1501 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1502 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1503 }; 1504 1505 if (ST->hasSSSE3()) 1506 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1507 return LT.first * Entry->Cost; 1508 1509 static const CostTblEntry SSE2ShuffleTbl[] = { 1510 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1511 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1512 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1513 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1514 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1515 1516 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1517 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1518 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1519 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1520 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1521 // + 2*pshufd + 2*unpck + packus 1522 1523 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1524 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1525 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1526 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1527 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1528 1529 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1530 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1531 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1532 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1533 // + pshufd/unpck 1534 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1535 // + 2*pshufd + 2*unpck + 2*packus 1536 1537 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1538 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1539 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1540 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1541 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1542 }; 1543 1544 if (ST->hasSSE2()) 1545 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1546 return LT.first * Entry->Cost; 1547 1548 static const CostTblEntry SSE1ShuffleTbl[] = { 1549 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1550 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1551 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1552 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1553 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1554 }; 1555 1556 if (ST->hasSSE1()) 1557 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1558 return LT.first * Entry->Cost; 1559 1560 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1561 } 1562 1563 InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, 1564 Type *Src, 1565 TTI::CastContextHint CCH, 1566 TTI::TargetCostKind CostKind, 1567 const Instruction *I) { 1568 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1569 assert(ISD && "Invalid opcode"); 1570 1571 // TODO: Allow non-throughput costs that aren't binary. 1572 auto AdjustCost = [&CostKind](InstructionCost Cost) -> InstructionCost { 1573 if (CostKind != TTI::TCK_RecipThroughput) 1574 return Cost == 0 ? 0 : 1; 1575 return Cost; 1576 }; 1577 1578 // The cost tables include both specific, custom (non-legal) src/dst type 1579 // conversions and generic, legalized types. We test for customs first, before 1580 // falling back to legalization. 1581 // FIXME: Need a better design of the cost table to handle non-simple types of 1582 // potential massive combinations (elem_num x src_type x dst_type). 1583 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1584 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1585 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1586 1587 // Mask sign extend has an instruction. 1588 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1589 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v2i1, 1 }, 1590 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1591 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v2i1, 1 }, 1592 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1593 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v4i1, 1 }, 1594 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1595 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v4i1, 1 }, 1596 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1597 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v8i1, 1 }, 1598 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1599 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1600 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1601 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1602 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1603 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1604 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v64i1, 1 }, 1605 1606 // Mask zero extend is a sext + shift. 1607 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1608 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v2i1, 2 }, 1609 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1610 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v2i1, 2 }, 1611 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1612 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v4i1, 2 }, 1613 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1614 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v4i1, 2 }, 1615 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1616 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v8i1, 2 }, 1617 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1618 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1619 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1620 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1621 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1622 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1623 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v64i1, 2 }, 1624 1625 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, 1626 { ISD::TRUNCATE, MVT::v2i1, MVT::v16i8, 2 }, 1627 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, 1628 { ISD::TRUNCATE, MVT::v2i1, MVT::v8i16, 2 }, 1629 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, 1630 { ISD::TRUNCATE, MVT::v4i1, MVT::v16i8, 2 }, 1631 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, 1632 { ISD::TRUNCATE, MVT::v4i1, MVT::v8i16, 2 }, 1633 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, 1634 { ISD::TRUNCATE, MVT::v8i1, MVT::v16i8, 2 }, 1635 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, 1636 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, 1637 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, 1638 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, 1639 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, 1640 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, 1641 { ISD::TRUNCATE, MVT::v64i1, MVT::v32i16, 2 }, 1642 1643 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, 1644 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm 1645 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // vpmovwb 1646 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // vpmovwb 1647 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // vpmovwb 1648 }; 1649 1650 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1651 // Mask sign extend has an instruction. 1652 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, 1653 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v2i1, 1 }, 1654 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, 1655 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, 1656 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, 1657 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v16i1, 1 }, 1658 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, 1659 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, 1660 1661 // Mask zero extend is a sext + shift. 1662 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, 1663 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v2i1, 2 }, 1664 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, 1665 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, 1666 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, 1667 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v16i1, 2 }, 1668 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, 1669 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1670 1671 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, 1672 { ISD::TRUNCATE, MVT::v2i1, MVT::v4i32, 2 }, 1673 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, 1674 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, 1675 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1676 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, 1677 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, 1678 { ISD::TRUNCATE, MVT::v16i1, MVT::v8i64, 2 }, 1679 1680 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1681 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1682 1683 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1684 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1685 1686 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1687 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1688 1689 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1690 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1691 }; 1692 1693 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1694 // 256-bit wide vectors. 1695 1696 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1697 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1698 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1699 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1700 1701 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1702 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1703 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1704 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd 1705 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1706 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1707 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1708 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd 1709 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd 1710 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd 1711 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd 1712 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd 1713 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq 1714 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq 1715 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq 1716 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 2 }, // vpmovdb 1717 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 2 }, // vpmovdb 1718 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, // vpmovdb 1719 { ISD::TRUNCATE, MVT::v32i8, MVT::v16i32, 2 }, // vpmovdb 1720 { ISD::TRUNCATE, MVT::v64i8, MVT::v16i32, 2 }, // vpmovdb 1721 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, // vpmovdw 1722 { ISD::TRUNCATE, MVT::v32i16, MVT::v16i32, 2 }, // vpmovdw 1723 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 2 }, // vpmovqb 1724 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 1 }, // vpshufb 1725 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, // vpmovqb 1726 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i64, 2 }, // vpmovqb 1727 { ISD::TRUNCATE, MVT::v32i8, MVT::v8i64, 2 }, // vpmovqb 1728 { ISD::TRUNCATE, MVT::v64i8, MVT::v8i64, 2 }, // vpmovqb 1729 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, // vpmovqw 1730 { ISD::TRUNCATE, MVT::v16i16, MVT::v8i64, 2 }, // vpmovqw 1731 { ISD::TRUNCATE, MVT::v32i16, MVT::v8i64, 2 }, // vpmovqw 1732 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, // vpmovqd 1733 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd 1734 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb 1735 1736 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32 1737 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, 1738 { ISD::TRUNCATE, MVT::v64i8, MVT::v32i16, 8 }, 1739 1740 // Sign extend is zmm vpternlogd+vptruncdb. 1741 // Zero extend is zmm broadcast load+vptruncdw. 1742 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 }, 1743 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 }, 1744 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, 1745 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, 1746 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, 1747 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, 1748 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 }, 1749 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 }, 1750 1751 // Sign extend is zmm vpternlogd+vptruncdw. 1752 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw. 1753 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 }, 1754 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1755 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 }, 1756 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1757 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 }, 1758 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1759 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 }, 1760 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1761 1762 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd 1763 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld 1764 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd 1765 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld 1766 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd 1767 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld 1768 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq 1769 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq 1770 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq 1771 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq 1772 1773 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd 1774 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld 1775 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq 1776 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq 1777 1778 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1779 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1780 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1781 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1782 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1783 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1784 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1785 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1786 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1787 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1788 1789 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1790 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1791 1792 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1793 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1794 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, 1795 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, 1796 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1797 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, 1798 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1799 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1800 1801 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1802 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1803 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, 1804 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, 1805 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1806 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, 1807 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1808 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1809 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1810 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1811 1812 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2 }, 1813 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f64, 7 }, 1814 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f64,15 }, 1815 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f32,11 }, 1816 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f64,31 }, 1817 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, 1818 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f64, 7 }, 1819 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f32, 5 }, 1820 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f64,15 }, 1821 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 1 }, 1822 { ISD::FP_TO_SINT, MVT::v16i32, MVT::v16f64, 3 }, 1823 1824 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1825 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, 1826 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, 1827 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1828 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, 1829 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, 1830 }; 1831 1832 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1833 // Mask sign extend has an instruction. 1834 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1835 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v2i1, 1 }, 1836 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1837 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v2i1, 1 }, 1838 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1839 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v4i1, 1 }, 1840 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1841 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v4i1, 1 }, 1842 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1843 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v8i1, 1 }, 1844 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1845 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1846 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1847 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1848 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v32i1, 1 }, 1849 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v64i1, 1 }, 1850 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v64i1, 1 }, 1851 1852 // Mask zero extend is a sext + shift. 1853 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1854 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v2i1, 2 }, 1855 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1856 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v2i1, 2 }, 1857 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1858 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v4i1, 2 }, 1859 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1860 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v4i1, 2 }, 1861 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1862 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v8i1, 2 }, 1863 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1864 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1865 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1866 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1867 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v32i1, 2 }, 1868 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v64i1, 2 }, 1869 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v64i1, 2 }, 1870 1871 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, 1872 { ISD::TRUNCATE, MVT::v2i1, MVT::v16i8, 2 }, 1873 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, 1874 { ISD::TRUNCATE, MVT::v2i1, MVT::v8i16, 2 }, 1875 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, 1876 { ISD::TRUNCATE, MVT::v4i1, MVT::v16i8, 2 }, 1877 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, 1878 { ISD::TRUNCATE, MVT::v4i1, MVT::v8i16, 2 }, 1879 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, 1880 { ISD::TRUNCATE, MVT::v8i1, MVT::v16i8, 2 }, 1881 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, 1882 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, 1883 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, 1884 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, 1885 { ISD::TRUNCATE, MVT::v32i1, MVT::v16i16, 2 }, 1886 { ISD::TRUNCATE, MVT::v64i1, MVT::v32i8, 2 }, 1887 { ISD::TRUNCATE, MVT::v64i1, MVT::v16i16, 2 }, 1888 1889 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, 1890 }; 1891 1892 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1893 // Mask sign extend has an instruction. 1894 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, 1895 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v2i1, 1 }, 1896 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, 1897 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i1, 1 }, 1898 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, 1899 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i1, 1 }, 1900 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i1, 1 }, 1901 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, 1902 1903 // Mask zero extend is a sext + shift. 1904 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, 1905 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v2i1, 2 }, 1906 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, 1907 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i1, 2 }, 1908 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, 1909 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i1, 2 }, 1910 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i1, 2 }, 1911 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, 1912 1913 { ISD::TRUNCATE, MVT::v16i1, MVT::v4i64, 2 }, 1914 { ISD::TRUNCATE, MVT::v16i1, MVT::v8i32, 2 }, 1915 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, 1916 { ISD::TRUNCATE, MVT::v2i1, MVT::v4i32, 2 }, 1917 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, 1918 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, 1919 { ISD::TRUNCATE, MVT::v8i1, MVT::v4i64, 2 }, 1920 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1921 1922 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1923 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1924 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1925 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1926 1927 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1928 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1929 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1930 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1931 1932 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v4f32, 1 }, 1933 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1934 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1935 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1936 1937 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v4f32, 1 }, 1938 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1939 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1940 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1941 }; 1942 1943 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 1944 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1945 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1946 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1947 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 8 }, // split+2*v8i8 1948 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1949 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1950 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1951 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16 1952 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // vpslld+vptestmd 1953 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd 1954 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // vpslld+vptestmd 1955 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // vpsllq+vptestmq 1956 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // vpsllq+vptestmq 1957 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // vpmovqd 1958 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, // vpmovqb 1959 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, // vpmovqw 1960 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, // vpmovwb 1961 1962 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb 1963 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb 1964 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 }, 1965 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 }, 1966 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 }, 1967 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 }, 1968 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 }, 1969 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 }, 1970 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 }, 1971 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 }, 1972 1973 // sign extend is vpcmpeq+maskedmove+vpmovdw 1974 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw 1975 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1976 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 }, 1977 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1978 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 }, 1979 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1980 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 }, 1981 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 }, 1982 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 }, 1983 1984 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd 1985 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld 1986 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd 1987 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld 1988 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd 1989 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld 1990 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq 1991 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq 1992 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq 1993 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq 1994 1995 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 1 }, 1996 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 1 }, 1997 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 1 }, 1998 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 1 }, 1999 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 2000 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 2001 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 1 }, 2002 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 1 }, 2003 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 2004 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 2005 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 2006 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 2007 2008 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2009 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 1 }, 2010 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2011 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 1 }, 2012 2013 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 2014 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 2015 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2016 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 1 }, 2017 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2018 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 1 }, 2019 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 2020 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 2021 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 2022 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 2023 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 2024 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 2025 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 2026 2027 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v8f32, 2 }, 2028 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2 }, 2029 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f32, 5 }, 2030 2031 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 2032 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 2033 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 2034 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 1 }, 2035 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 2036 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 2037 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 2038 }; 2039 2040 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 2041 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 2042 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 2043 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 2044 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 2045 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 2046 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 2047 2048 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 2 }, 2049 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 2 }, 2050 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 2 }, 2051 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 2 }, 2052 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 2053 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 2054 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 2 }, 2055 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 2 }, 2056 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 2057 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 2058 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 2059 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 2060 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 2061 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 2062 2063 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 2064 2065 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 4 }, 2066 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 4 }, 2067 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i16, 1 }, 2068 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 1 }, 2069 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 1 }, 2070 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i32, 4 }, 2071 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i64, 4 }, 2072 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 1 }, 2073 { ISD::TRUNCATE, MVT::v8i16, MVT::v2i64, 1 }, 2074 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i64, 5 }, 2075 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, 2076 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 2077 2078 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 2079 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 2080 2081 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v8f32, 1 }, 2082 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 1 }, 2083 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 1 }, 2084 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 3 }, 2085 2086 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 3 }, 2087 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 3 }, 2088 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v8f32, 1 }, 2089 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 3 }, 2090 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 2091 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4 }, 2092 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 3 }, 2093 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v4f64, 4 }, 2094 2095 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 2 }, 2096 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 2 }, 2097 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 2 }, 2098 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 2099 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 2100 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 2101 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 3 }, 2102 2103 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 2 }, 2104 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 2 }, 2105 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 2 }, 2106 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 2107 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 2108 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 2109 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 2 }, 2110 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2111 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 2112 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 }, 2113 }; 2114 2115 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 2116 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 2117 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 2118 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 2119 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 2120 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 2121 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 2122 2123 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 3 }, 2124 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 3 }, 2125 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 3 }, 2126 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 3 }, 2127 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 2128 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 2129 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 3 }, 2130 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 3 }, 2131 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 2132 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 2133 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 2134 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 2135 2136 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 4 }, 2137 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 5 }, 2138 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 4 }, 2139 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 9 }, 2140 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, 11 }, 2141 2142 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 2143 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, 2144 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // and+extract+packuswb 2145 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i32, 5 }, 2146 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2147 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i64, 5 }, 2148 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i64, 3 }, // and+extract+2*packusdw 2149 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 2150 2151 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 2152 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 2153 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 2154 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 4 }, 2155 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v16i8, 2 }, 2156 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 2157 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v8i16, 2 }, 2158 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2159 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 2160 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 }, 2161 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 5 }, 2162 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 8 }, 2163 2164 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 2165 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 2166 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 2167 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 4 }, 2168 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v16i8, 2 }, 2169 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 2170 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v8i16, 2 }, 2171 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 4 }, 2172 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 4 }, 2173 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 2174 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 2175 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 2176 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 10 }, 2177 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 10 }, 2178 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 18 }, 2179 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 2180 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 10 }, 2181 2182 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v8f32, 2 }, 2183 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f64, 2 }, 2184 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v8f32, 2 }, 2185 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v4f64, 2 }, 2186 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 2 }, 2187 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f64, 2 }, 2188 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v8f32, 2 }, 2189 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v4f64, 2 }, 2190 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 2 }, 2191 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 2 }, 2192 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 5 }, 2193 2194 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v8f32, 2 }, 2195 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f64, 2 }, 2196 { ISD::FP_TO_UINT, MVT::v32i8, MVT::v8f32, 2 }, 2197 { ISD::FP_TO_UINT, MVT::v32i8, MVT::v4f64, 2 }, 2198 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 2 }, 2199 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f64, 2 }, 2200 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v8f32, 2 }, 2201 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v4f64, 2 }, 2202 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 3 }, 2203 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 2204 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 6 }, 2205 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 7 }, 2206 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v4f64, 7 }, 2207 2208 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 2209 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 2210 }; 2211 2212 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 2213 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8, 1 }, 2214 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8, 1 }, 2215 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8, 1 }, 2216 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8, 1 }, 2217 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2218 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2219 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16, 1 }, 2220 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16, 1 }, 2221 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2222 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2223 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2224 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2225 2226 // These truncates end up widening elements. 2227 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 1 }, // PMOVXZBQ 2228 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 1 }, // PMOVXZWQ 2229 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 1 }, // PMOVXZBD 2230 2231 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 2 }, 2232 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 2 }, 2233 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 2 }, 2234 2235 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 1 }, 2236 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 1 }, 2237 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 1 }, 2238 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 1 }, 2239 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 1 }, 2240 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2241 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 1 }, 2242 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2243 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 2244 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 1 }, 2245 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2246 2247 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 1 }, 2248 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 1 }, 2249 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 2250 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 2251 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 1 }, 2252 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2253 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 1 }, 2254 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2255 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 3 }, 2256 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 3 }, 2257 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 2 }, 2258 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 12 }, 2259 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 22 }, 2260 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 4 }, 2261 2262 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 1 }, 2263 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 1 }, 2264 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 1 }, 2265 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 1 }, 2266 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f32, 2 }, 2267 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v2f64, 2 }, 2268 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f32, 1 }, 2269 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v2f64, 1 }, 2270 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, 2271 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v2f64, 1 }, 2272 2273 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 1 }, 2274 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 2275 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 1 }, 2276 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 2277 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f32, 2 }, 2278 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v2f64, 2 }, 2279 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f32, 1 }, 2280 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v2f64, 1 }, 2281 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 4 }, 2282 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 2283 }; 2284 2285 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 2286 // These are somewhat magic numbers justified by comparing the 2287 // output of llvm-mca for our various supported scheduler models 2288 // and basing it off the worst case scenario. 2289 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 3 }, 2290 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 3 }, 2291 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 3 }, 2292 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 3 }, 2293 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 3 }, 2294 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 4 }, 2295 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 3 }, 2296 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 4 }, 2297 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 3 }, 2298 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4 }, 2299 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 8 }, 2300 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 8 }, 2301 2302 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 3 }, 2303 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 3 }, 2304 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 8 }, 2305 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 9 }, 2306 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 4 }, 2307 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 4 }, 2308 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 4 }, 2309 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 4 }, 2310 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 7 }, 2311 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 7 }, 2312 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 2313 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 15 }, 2314 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 18 }, 2315 2316 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 4 }, 2317 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 4 }, 2318 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 4 }, 2319 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 4 }, 2320 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f32, 6 }, 2321 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v2f64, 6 }, 2322 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f32, 5 }, 2323 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v2f64, 5 }, 2324 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 4 }, 2325 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v2f64, 4 }, 2326 2327 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 4 }, 2328 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 2329 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 4 }, 2330 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 15 }, 2331 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f32, 6 }, 2332 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v2f64, 6 }, 2333 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f32, 5 }, 2334 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v2f64, 5 }, 2335 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 8 }, 2336 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 8 }, 2337 2338 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8, 4 }, 2339 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8, 4 }, 2340 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8, 2 }, 2341 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8, 3 }, 2342 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2343 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8, 2 }, 2344 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16, 2 }, 2345 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16, 3 }, 2346 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2347 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16, 2 }, 2348 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2349 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32, 2 }, 2350 2351 // These truncates are really widening elements. 2352 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 1 }, // PSHUFD 2353 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // PUNPCKLWD+DQ 2354 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // PUNPCKLBW+WD+PSHUFD 2355 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 1 }, // PUNPCKLWD 2356 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // PUNPCKLBW+WD 2357 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 1 }, // PUNPCKLBW 2358 2359 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i16, 2 }, // PAND+PACKUSWB 2360 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 2361 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 3 }, // PAND+2*PACKUSWB 2362 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 2363 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 2364 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 3 }, 2365 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2366 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32,10 }, 2367 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 2368 { ISD::TRUNCATE, MVT::v8i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 2369 { ISD::TRUNCATE, MVT::v4i32, MVT::v2i64, 1 }, // PSHUFD 2370 }; 2371 2372 // Attempt to map directly to (simple) MVT types to let us match custom entries. 2373 EVT SrcTy = TLI->getValueType(DL, Src); 2374 EVT DstTy = TLI->getValueType(DL, Dst); 2375 2376 // The function getSimpleVT only handles simple value types. 2377 if (SrcTy.isSimple() && DstTy.isSimple()) { 2378 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 2379 MVT SimpleDstTy = DstTy.getSimpleVT(); 2380 2381 if (ST->useAVX512Regs()) { 2382 if (ST->hasBWI()) 2383 if (const auto *Entry = ConvertCostTableLookup( 2384 AVX512BWConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2385 return AdjustCost(Entry->Cost); 2386 2387 if (ST->hasDQI()) 2388 if (const auto *Entry = ConvertCostTableLookup( 2389 AVX512DQConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2390 return AdjustCost(Entry->Cost); 2391 2392 if (ST->hasAVX512()) 2393 if (const auto *Entry = ConvertCostTableLookup( 2394 AVX512FConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2395 return AdjustCost(Entry->Cost); 2396 } 2397 2398 if (ST->hasBWI()) 2399 if (const auto *Entry = ConvertCostTableLookup( 2400 AVX512BWVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2401 return AdjustCost(Entry->Cost); 2402 2403 if (ST->hasDQI()) 2404 if (const auto *Entry = ConvertCostTableLookup( 2405 AVX512DQVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2406 return AdjustCost(Entry->Cost); 2407 2408 if (ST->hasAVX512()) 2409 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2410 SimpleDstTy, SimpleSrcTy)) 2411 return AdjustCost(Entry->Cost); 2412 2413 if (ST->hasAVX2()) { 2414 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2415 SimpleDstTy, SimpleSrcTy)) 2416 return AdjustCost(Entry->Cost); 2417 } 2418 2419 if (ST->hasAVX()) { 2420 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2421 SimpleDstTy, SimpleSrcTy)) 2422 return AdjustCost(Entry->Cost); 2423 } 2424 2425 if (ST->hasSSE41()) { 2426 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2427 SimpleDstTy, SimpleSrcTy)) 2428 return AdjustCost(Entry->Cost); 2429 } 2430 2431 if (ST->hasSSE2()) { 2432 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2433 SimpleDstTy, SimpleSrcTy)) 2434 return AdjustCost(Entry->Cost); 2435 } 2436 } 2437 2438 // Fall back to legalized types. 2439 std::pair<InstructionCost, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 2440 std::pair<InstructionCost, MVT> LTDest = 2441 TLI->getTypeLegalizationCost(DL, Dst); 2442 2443 if (ST->useAVX512Regs()) { 2444 if (ST->hasBWI()) 2445 if (const auto *Entry = ConvertCostTableLookup( 2446 AVX512BWConversionTbl, ISD, LTDest.second, LTSrc.second)) 2447 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2448 2449 if (ST->hasDQI()) 2450 if (const auto *Entry = ConvertCostTableLookup( 2451 AVX512DQConversionTbl, ISD, LTDest.second, LTSrc.second)) 2452 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2453 2454 if (ST->hasAVX512()) 2455 if (const auto *Entry = ConvertCostTableLookup( 2456 AVX512FConversionTbl, ISD, LTDest.second, LTSrc.second)) 2457 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2458 } 2459 2460 if (ST->hasBWI()) 2461 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 2462 LTDest.second, LTSrc.second)) 2463 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2464 2465 if (ST->hasDQI()) 2466 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 2467 LTDest.second, LTSrc.second)) 2468 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2469 2470 if (ST->hasAVX512()) 2471 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2472 LTDest.second, LTSrc.second)) 2473 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2474 2475 if (ST->hasAVX2()) 2476 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2477 LTDest.second, LTSrc.second)) 2478 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2479 2480 if (ST->hasAVX()) 2481 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2482 LTDest.second, LTSrc.second)) 2483 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2484 2485 if (ST->hasSSE41()) 2486 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2487 LTDest.second, LTSrc.second)) 2488 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2489 2490 if (ST->hasSSE2()) 2491 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2492 LTDest.second, LTSrc.second)) 2493 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2494 2495 // Fallback, for i8/i16 sitofp/uitofp cases we need to extend to i32 for 2496 // sitofp. 2497 if ((ISD == ISD::SINT_TO_FP || ISD == ISD::UINT_TO_FP) && 2498 1 < Src->getScalarSizeInBits() && Src->getScalarSizeInBits() < 32) { 2499 Type *ExtSrc = Src->getWithNewBitWidth(32); 2500 unsigned ExtOpc = 2501 (ISD == ISD::SINT_TO_FP) ? Instruction::SExt : Instruction::ZExt; 2502 2503 // For scalar loads the extend would be free. 2504 InstructionCost ExtCost = 0; 2505 if (!(Src->isIntegerTy() && I && isa<LoadInst>(I->getOperand(0)))) 2506 ExtCost = getCastInstrCost(ExtOpc, ExtSrc, Src, CCH, CostKind); 2507 2508 return ExtCost + getCastInstrCost(Instruction::SIToFP, Dst, ExtSrc, 2509 TTI::CastContextHint::None, CostKind); 2510 } 2511 2512 // Fallback for fptosi/fptoui i8/i16 cases we need to truncate from fptosi 2513 // i32. 2514 if ((ISD == ISD::FP_TO_SINT || ISD == ISD::FP_TO_UINT) && 2515 1 < Dst->getScalarSizeInBits() && Dst->getScalarSizeInBits() < 32) { 2516 Type *TruncDst = Dst->getWithNewBitWidth(32); 2517 return getCastInstrCost(Instruction::FPToSI, TruncDst, Src, CCH, CostKind) + 2518 getCastInstrCost(Instruction::Trunc, Dst, TruncDst, 2519 TTI::CastContextHint::None, CostKind); 2520 } 2521 2522 return AdjustCost( 2523 BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I)); 2524 } 2525 2526 InstructionCost X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 2527 Type *CondTy, 2528 CmpInst::Predicate VecPred, 2529 TTI::TargetCostKind CostKind, 2530 const Instruction *I) { 2531 // TODO: Handle other cost kinds. 2532 if (CostKind != TTI::TCK_RecipThroughput) 2533 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, 2534 I); 2535 2536 // Legalize the type. 2537 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2538 2539 MVT MTy = LT.second; 2540 2541 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2542 assert(ISD && "Invalid opcode"); 2543 2544 unsigned ExtraCost = 0; 2545 if (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp) { 2546 // Some vector comparison predicates cost extra instructions. 2547 // TODO: Should we invert this and assume worst case cmp costs 2548 // and reduce for particular predicates? 2549 if (MTy.isVector() && 2550 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 2551 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 2552 ST->hasBWI())) { 2553 // Fallback to I if a specific predicate wasn't specified. 2554 CmpInst::Predicate Pred = VecPred; 2555 if (I && (Pred == CmpInst::BAD_ICMP_PREDICATE || 2556 Pred == CmpInst::BAD_FCMP_PREDICATE)) 2557 Pred = cast<CmpInst>(I)->getPredicate(); 2558 2559 switch (Pred) { 2560 case CmpInst::Predicate::ICMP_NE: 2561 // xor(cmpeq(x,y),-1) 2562 ExtraCost = 1; 2563 break; 2564 case CmpInst::Predicate::ICMP_SGE: 2565 case CmpInst::Predicate::ICMP_SLE: 2566 // xor(cmpgt(x,y),-1) 2567 ExtraCost = 1; 2568 break; 2569 case CmpInst::Predicate::ICMP_ULT: 2570 case CmpInst::Predicate::ICMP_UGT: 2571 // cmpgt(xor(x,signbit),xor(y,signbit)) 2572 // xor(cmpeq(pmaxu(x,y),x),-1) 2573 ExtraCost = 2; 2574 break; 2575 case CmpInst::Predicate::ICMP_ULE: 2576 case CmpInst::Predicate::ICMP_UGE: 2577 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 2578 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 2579 // cmpeq(psubus(x,y),0) 2580 // cmpeq(pminu(x,y),x) 2581 ExtraCost = 1; 2582 } else { 2583 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 2584 ExtraCost = 3; 2585 } 2586 break; 2587 case CmpInst::Predicate::BAD_ICMP_PREDICATE: 2588 case CmpInst::Predicate::BAD_FCMP_PREDICATE: 2589 // Assume worst case scenario and add the maximum extra cost. 2590 ExtraCost = 3; 2591 break; 2592 default: 2593 break; 2594 } 2595 } 2596 } 2597 2598 static const CostTblEntry SLMCostTbl[] = { 2599 // slm pcmpeq/pcmpgt throughput is 2 2600 { ISD::SETCC, MVT::v2i64, 2 }, 2601 }; 2602 2603 static const CostTblEntry AVX512BWCostTbl[] = { 2604 { ISD::SETCC, MVT::v32i16, 1 }, 2605 { ISD::SETCC, MVT::v64i8, 1 }, 2606 2607 { ISD::SELECT, MVT::v32i16, 1 }, 2608 { ISD::SELECT, MVT::v64i8, 1 }, 2609 }; 2610 2611 static const CostTblEntry AVX512CostTbl[] = { 2612 { ISD::SETCC, MVT::v8i64, 1 }, 2613 { ISD::SETCC, MVT::v16i32, 1 }, 2614 { ISD::SETCC, MVT::v8f64, 1 }, 2615 { ISD::SETCC, MVT::v16f32, 1 }, 2616 2617 { ISD::SELECT, MVT::v8i64, 1 }, 2618 { ISD::SELECT, MVT::v16i32, 1 }, 2619 { ISD::SELECT, MVT::v8f64, 1 }, 2620 { ISD::SELECT, MVT::v16f32, 1 }, 2621 2622 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 2623 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 2624 2625 { ISD::SELECT, MVT::v32i16, 2 }, // FIXME: should be 3 2626 { ISD::SELECT, MVT::v64i8, 2 }, // FIXME: should be 3 2627 }; 2628 2629 static const CostTblEntry AVX2CostTbl[] = { 2630 { ISD::SETCC, MVT::v4i64, 1 }, 2631 { ISD::SETCC, MVT::v8i32, 1 }, 2632 { ISD::SETCC, MVT::v16i16, 1 }, 2633 { ISD::SETCC, MVT::v32i8, 1 }, 2634 2635 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 2636 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 2637 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 2638 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 2639 }; 2640 2641 static const CostTblEntry AVX1CostTbl[] = { 2642 { ISD::SETCC, MVT::v4f64, 1 }, 2643 { ISD::SETCC, MVT::v8f32, 1 }, 2644 // AVX1 does not support 8-wide integer compare. 2645 { ISD::SETCC, MVT::v4i64, 4 }, 2646 { ISD::SETCC, MVT::v8i32, 4 }, 2647 { ISD::SETCC, MVT::v16i16, 4 }, 2648 { ISD::SETCC, MVT::v32i8, 4 }, 2649 2650 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 2651 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 2652 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 2653 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 2654 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 2655 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 2656 }; 2657 2658 static const CostTblEntry SSE42CostTbl[] = { 2659 { ISD::SETCC, MVT::v2f64, 1 }, 2660 { ISD::SETCC, MVT::v4f32, 1 }, 2661 { ISD::SETCC, MVT::v2i64, 1 }, 2662 }; 2663 2664 static const CostTblEntry SSE41CostTbl[] = { 2665 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 2666 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 2667 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 2668 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 2669 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 2670 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 2671 }; 2672 2673 static const CostTblEntry SSE2CostTbl[] = { 2674 { ISD::SETCC, MVT::v2f64, 2 }, 2675 { ISD::SETCC, MVT::f64, 1 }, 2676 { ISD::SETCC, MVT::v2i64, 8 }, 2677 { ISD::SETCC, MVT::v4i32, 1 }, 2678 { ISD::SETCC, MVT::v8i16, 1 }, 2679 { ISD::SETCC, MVT::v16i8, 1 }, 2680 2681 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 2682 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 2683 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 2684 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 2685 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 2686 }; 2687 2688 static const CostTblEntry SSE1CostTbl[] = { 2689 { ISD::SETCC, MVT::v4f32, 2 }, 2690 { ISD::SETCC, MVT::f32, 1 }, 2691 2692 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 2693 }; 2694 2695 if (ST->useSLMArithCosts()) 2696 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2697 return LT.first * (ExtraCost + Entry->Cost); 2698 2699 if (ST->hasBWI()) 2700 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2701 return LT.first * (ExtraCost + Entry->Cost); 2702 2703 if (ST->hasAVX512()) 2704 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2705 return LT.first * (ExtraCost + Entry->Cost); 2706 2707 if (ST->hasAVX2()) 2708 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2709 return LT.first * (ExtraCost + Entry->Cost); 2710 2711 if (ST->hasAVX()) 2712 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2713 return LT.first * (ExtraCost + Entry->Cost); 2714 2715 if (ST->hasSSE42()) 2716 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2717 return LT.first * (ExtraCost + Entry->Cost); 2718 2719 if (ST->hasSSE41()) 2720 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2721 return LT.first * (ExtraCost + Entry->Cost); 2722 2723 if (ST->hasSSE2()) 2724 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2725 return LT.first * (ExtraCost + Entry->Cost); 2726 2727 if (ST->hasSSE1()) 2728 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2729 return LT.first * (ExtraCost + Entry->Cost); 2730 2731 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I); 2732 } 2733 2734 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2735 2736 InstructionCost 2737 X86TTIImpl::getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 2738 TTI::TargetCostKind CostKind) { 2739 2740 // Costs should match the codegen from: 2741 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2742 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2743 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2744 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2745 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2746 2747 // TODO: Overflow intrinsics (*ADDO, *SUBO, *MULO) with vector types are not 2748 // specialized in these tables yet. 2749 static const CostTblEntry AVX512BITALGCostTbl[] = { 2750 { ISD::CTPOP, MVT::v32i16, 1 }, 2751 { ISD::CTPOP, MVT::v64i8, 1 }, 2752 { ISD::CTPOP, MVT::v16i16, 1 }, 2753 { ISD::CTPOP, MVT::v32i8, 1 }, 2754 { ISD::CTPOP, MVT::v8i16, 1 }, 2755 { ISD::CTPOP, MVT::v16i8, 1 }, 2756 }; 2757 static const CostTblEntry AVX512VPOPCNTDQCostTbl[] = { 2758 { ISD::CTPOP, MVT::v8i64, 1 }, 2759 { ISD::CTPOP, MVT::v16i32, 1 }, 2760 { ISD::CTPOP, MVT::v4i64, 1 }, 2761 { ISD::CTPOP, MVT::v8i32, 1 }, 2762 { ISD::CTPOP, MVT::v2i64, 1 }, 2763 { ISD::CTPOP, MVT::v4i32, 1 }, 2764 }; 2765 static const CostTblEntry AVX512CDCostTbl[] = { 2766 { ISD::CTLZ, MVT::v8i64, 1 }, 2767 { ISD::CTLZ, MVT::v16i32, 1 }, 2768 { ISD::CTLZ, MVT::v32i16, 8 }, 2769 { ISD::CTLZ, MVT::v64i8, 20 }, 2770 { ISD::CTLZ, MVT::v4i64, 1 }, 2771 { ISD::CTLZ, MVT::v8i32, 1 }, 2772 { ISD::CTLZ, MVT::v16i16, 4 }, 2773 { ISD::CTLZ, MVT::v32i8, 10 }, 2774 { ISD::CTLZ, MVT::v2i64, 1 }, 2775 { ISD::CTLZ, MVT::v4i32, 1 }, 2776 { ISD::CTLZ, MVT::v8i16, 4 }, 2777 { ISD::CTLZ, MVT::v16i8, 4 }, 2778 }; 2779 static const CostTblEntry AVX512BWCostTbl[] = { 2780 { ISD::ABS, MVT::v32i16, 1 }, 2781 { ISD::ABS, MVT::v64i8, 1 }, 2782 { ISD::BITREVERSE, MVT::v8i64, 3 }, 2783 { ISD::BITREVERSE, MVT::v16i32, 3 }, 2784 { ISD::BITREVERSE, MVT::v32i16, 3 }, 2785 { ISD::BITREVERSE, MVT::v64i8, 2 }, 2786 { ISD::BSWAP, MVT::v8i64, 1 }, 2787 { ISD::BSWAP, MVT::v16i32, 1 }, 2788 { ISD::BSWAP, MVT::v32i16, 1 }, 2789 { ISD::CTLZ, MVT::v8i64, 23 }, 2790 { ISD::CTLZ, MVT::v16i32, 22 }, 2791 { ISD::CTLZ, MVT::v32i16, 18 }, 2792 { ISD::CTLZ, MVT::v64i8, 17 }, 2793 { ISD::CTPOP, MVT::v8i64, 7 }, 2794 { ISD::CTPOP, MVT::v16i32, 11 }, 2795 { ISD::CTPOP, MVT::v32i16, 9 }, 2796 { ISD::CTPOP, MVT::v64i8, 6 }, 2797 { ISD::CTTZ, MVT::v8i64, 10 }, 2798 { ISD::CTTZ, MVT::v16i32, 14 }, 2799 { ISD::CTTZ, MVT::v32i16, 12 }, 2800 { ISD::CTTZ, MVT::v64i8, 9 }, 2801 { ISD::SADDSAT, MVT::v32i16, 1 }, 2802 { ISD::SADDSAT, MVT::v64i8, 1 }, 2803 { ISD::SMAX, MVT::v32i16, 1 }, 2804 { ISD::SMAX, MVT::v64i8, 1 }, 2805 { ISD::SMIN, MVT::v32i16, 1 }, 2806 { ISD::SMIN, MVT::v64i8, 1 }, 2807 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2808 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2809 { ISD::UADDSAT, MVT::v32i16, 1 }, 2810 { ISD::UADDSAT, MVT::v64i8, 1 }, 2811 { ISD::UMAX, MVT::v32i16, 1 }, 2812 { ISD::UMAX, MVT::v64i8, 1 }, 2813 { ISD::UMIN, MVT::v32i16, 1 }, 2814 { ISD::UMIN, MVT::v64i8, 1 }, 2815 { ISD::USUBSAT, MVT::v32i16, 1 }, 2816 { ISD::USUBSAT, MVT::v64i8, 1 }, 2817 }; 2818 static const CostTblEntry AVX512CostTbl[] = { 2819 { ISD::ABS, MVT::v8i64, 1 }, 2820 { ISD::ABS, MVT::v16i32, 1 }, 2821 { ISD::ABS, MVT::v32i16, 2 }, 2822 { ISD::ABS, MVT::v64i8, 2 }, 2823 { ISD::ABS, MVT::v4i64, 1 }, 2824 { ISD::ABS, MVT::v2i64, 1 }, 2825 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2826 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2827 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2828 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2829 { ISD::BSWAP, MVT::v8i64, 4 }, 2830 { ISD::BSWAP, MVT::v16i32, 4 }, 2831 { ISD::BSWAP, MVT::v32i16, 4 }, 2832 { ISD::CTLZ, MVT::v8i64, 29 }, 2833 { ISD::CTLZ, MVT::v16i32, 35 }, 2834 { ISD::CTLZ, MVT::v32i16, 28 }, 2835 { ISD::CTLZ, MVT::v64i8, 18 }, 2836 { ISD::CTPOP, MVT::v8i64, 16 }, 2837 { ISD::CTPOP, MVT::v16i32, 24 }, 2838 { ISD::CTPOP, MVT::v32i16, 18 }, 2839 { ISD::CTPOP, MVT::v64i8, 12 }, 2840 { ISD::CTTZ, MVT::v8i64, 20 }, 2841 { ISD::CTTZ, MVT::v16i32, 28 }, 2842 { ISD::CTTZ, MVT::v32i16, 24 }, 2843 { ISD::CTTZ, MVT::v64i8, 18 }, 2844 { ISD::SMAX, MVT::v8i64, 1 }, 2845 { ISD::SMAX, MVT::v16i32, 1 }, 2846 { ISD::SMAX, MVT::v32i16, 2 }, 2847 { ISD::SMAX, MVT::v64i8, 2 }, 2848 { ISD::SMAX, MVT::v4i64, 1 }, 2849 { ISD::SMAX, MVT::v2i64, 1 }, 2850 { ISD::SMIN, MVT::v8i64, 1 }, 2851 { ISD::SMIN, MVT::v16i32, 1 }, 2852 { ISD::SMIN, MVT::v32i16, 2 }, 2853 { ISD::SMIN, MVT::v64i8, 2 }, 2854 { ISD::SMIN, MVT::v4i64, 1 }, 2855 { ISD::SMIN, MVT::v2i64, 1 }, 2856 { ISD::UMAX, MVT::v8i64, 1 }, 2857 { ISD::UMAX, MVT::v16i32, 1 }, 2858 { ISD::UMAX, MVT::v32i16, 2 }, 2859 { ISD::UMAX, MVT::v64i8, 2 }, 2860 { ISD::UMAX, MVT::v4i64, 1 }, 2861 { ISD::UMAX, MVT::v2i64, 1 }, 2862 { ISD::UMIN, MVT::v8i64, 1 }, 2863 { ISD::UMIN, MVT::v16i32, 1 }, 2864 { ISD::UMIN, MVT::v32i16, 2 }, 2865 { ISD::UMIN, MVT::v64i8, 2 }, 2866 { ISD::UMIN, MVT::v4i64, 1 }, 2867 { ISD::UMIN, MVT::v2i64, 1 }, 2868 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2869 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2870 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2871 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2872 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2873 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2874 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2875 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2876 { ISD::SADDSAT, MVT::v32i16, 2 }, 2877 { ISD::SADDSAT, MVT::v64i8, 2 }, 2878 { ISD::SSUBSAT, MVT::v32i16, 2 }, 2879 { ISD::SSUBSAT, MVT::v64i8, 2 }, 2880 { ISD::UADDSAT, MVT::v32i16, 2 }, 2881 { ISD::UADDSAT, MVT::v64i8, 2 }, 2882 { ISD::USUBSAT, MVT::v32i16, 2 }, 2883 { ISD::USUBSAT, MVT::v64i8, 2 }, 2884 { ISD::FMAXNUM, MVT::f32, 2 }, 2885 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2886 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2887 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2888 { ISD::FMAXNUM, MVT::f64, 2 }, 2889 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2890 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2891 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2892 }; 2893 static const CostTblEntry XOPCostTbl[] = { 2894 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2895 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2896 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2897 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2898 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2899 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2900 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2901 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2902 { ISD::BITREVERSE, MVT::i64, 3 }, 2903 { ISD::BITREVERSE, MVT::i32, 3 }, 2904 { ISD::BITREVERSE, MVT::i16, 3 }, 2905 { ISD::BITREVERSE, MVT::i8, 3 } 2906 }; 2907 static const CostTblEntry AVX2CostTbl[] = { 2908 { ISD::ABS, MVT::v4i64, 2 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2909 { ISD::ABS, MVT::v8i32, 1 }, 2910 { ISD::ABS, MVT::v16i16, 1 }, 2911 { ISD::ABS, MVT::v32i8, 1 }, 2912 { ISD::BITREVERSE, MVT::v2i64, 3 }, 2913 { ISD::BITREVERSE, MVT::v4i64, 3 }, 2914 { ISD::BITREVERSE, MVT::v4i32, 3 }, 2915 { ISD::BITREVERSE, MVT::v8i32, 3 }, 2916 { ISD::BITREVERSE, MVT::v8i16, 3 }, 2917 { ISD::BITREVERSE, MVT::v16i16, 3 }, 2918 { ISD::BITREVERSE, MVT::v16i8, 3 }, 2919 { ISD::BITREVERSE, MVT::v32i8, 3 }, 2920 { ISD::BSWAP, MVT::v4i64, 1 }, 2921 { ISD::BSWAP, MVT::v8i32, 1 }, 2922 { ISD::BSWAP, MVT::v16i16, 1 }, 2923 { ISD::CTLZ, MVT::v2i64, 7 }, 2924 { ISD::CTLZ, MVT::v4i64, 7 }, 2925 { ISD::CTLZ, MVT::v4i32, 5 }, 2926 { ISD::CTLZ, MVT::v8i32, 5 }, 2927 { ISD::CTLZ, MVT::v8i16, 4 }, 2928 { ISD::CTLZ, MVT::v16i16, 4 }, 2929 { ISD::CTLZ, MVT::v16i8, 3 }, 2930 { ISD::CTLZ, MVT::v32i8, 3 }, 2931 { ISD::CTPOP, MVT::v2i64, 3 }, 2932 { ISD::CTPOP, MVT::v4i64, 3 }, 2933 { ISD::CTPOP, MVT::v4i32, 7 }, 2934 { ISD::CTPOP, MVT::v8i32, 7 }, 2935 { ISD::CTPOP, MVT::v8i16, 3 }, 2936 { ISD::CTPOP, MVT::v16i16, 3 }, 2937 { ISD::CTPOP, MVT::v16i8, 2 }, 2938 { ISD::CTPOP, MVT::v32i8, 2 }, 2939 { ISD::CTTZ, MVT::v2i64, 4 }, 2940 { ISD::CTTZ, MVT::v4i64, 4 }, 2941 { ISD::CTTZ, MVT::v4i32, 7 }, 2942 { ISD::CTTZ, MVT::v8i32, 7 }, 2943 { ISD::CTTZ, MVT::v8i16, 4 }, 2944 { ISD::CTTZ, MVT::v16i16, 4 }, 2945 { ISD::CTTZ, MVT::v16i8, 3 }, 2946 { ISD::CTTZ, MVT::v32i8, 3 }, 2947 { ISD::SADDSAT, MVT::v16i16, 1 }, 2948 { ISD::SADDSAT, MVT::v32i8, 1 }, 2949 { ISD::SMAX, MVT::v8i32, 1 }, 2950 { ISD::SMAX, MVT::v16i16, 1 }, 2951 { ISD::SMAX, MVT::v32i8, 1 }, 2952 { ISD::SMIN, MVT::v8i32, 1 }, 2953 { ISD::SMIN, MVT::v16i16, 1 }, 2954 { ISD::SMIN, MVT::v32i8, 1 }, 2955 { ISD::SSUBSAT, MVT::v16i16, 1 }, 2956 { ISD::SSUBSAT, MVT::v32i8, 1 }, 2957 { ISD::UADDSAT, MVT::v16i16, 1 }, 2958 { ISD::UADDSAT, MVT::v32i8, 1 }, 2959 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 2960 { ISD::UMAX, MVT::v8i32, 1 }, 2961 { ISD::UMAX, MVT::v16i16, 1 }, 2962 { ISD::UMAX, MVT::v32i8, 1 }, 2963 { ISD::UMIN, MVT::v8i32, 1 }, 2964 { ISD::UMIN, MVT::v16i16, 1 }, 2965 { ISD::UMIN, MVT::v32i8, 1 }, 2966 { ISD::USUBSAT, MVT::v16i16, 1 }, 2967 { ISD::USUBSAT, MVT::v32i8, 1 }, 2968 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2969 { ISD::FMAXNUM, MVT::v8f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2970 { ISD::FMAXNUM, MVT::v4f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2971 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2972 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2973 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2974 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2975 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2976 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2977 }; 2978 static const CostTblEntry AVX1CostTbl[] = { 2979 { ISD::ABS, MVT::v4i64, 5 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2980 { ISD::ABS, MVT::v8i32, 3 }, 2981 { ISD::ABS, MVT::v16i16, 3 }, 2982 { ISD::ABS, MVT::v32i8, 3 }, 2983 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 2984 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 2985 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 2986 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 2987 { ISD::BSWAP, MVT::v4i64, 4 }, 2988 { ISD::BSWAP, MVT::v8i32, 4 }, 2989 { ISD::BSWAP, MVT::v16i16, 4 }, 2990 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 2991 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 2992 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 2993 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2994 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 2995 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 2996 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 2997 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 2998 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 2999 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 3000 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 3001 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 3002 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3003 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3004 { ISD::SMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3005 { ISD::SMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3006 { ISD::SMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3007 { ISD::SMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3008 { ISD::SMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3009 { ISD::SMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3010 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3011 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3012 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3013 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3014 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 3015 { ISD::UMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3016 { ISD::UMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3017 { ISD::UMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3018 { ISD::UMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3019 { ISD::UMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3020 { ISD::UMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3021 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3022 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3023 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 3024 { ISD::FMAXNUM, MVT::f32, 3 }, // MAXSS + CMPUNORDSS + BLENDVPS 3025 { ISD::FMAXNUM, MVT::v4f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 3026 { ISD::FMAXNUM, MVT::v8f32, 5 }, // MAXPS + CMPUNORDPS + BLENDVPS + ? 3027 { ISD::FMAXNUM, MVT::f64, 3 }, // MAXSD + CMPUNORDSD + BLENDVPD 3028 { ISD::FMAXNUM, MVT::v2f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 3029 { ISD::FMAXNUM, MVT::v4f64, 5 }, // MAXPD + CMPUNORDPD + BLENDVPD + ? 3030 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 3031 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 3032 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 3033 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 3034 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 3035 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 3036 }; 3037 static const CostTblEntry GLMCostTbl[] = { 3038 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 3039 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 3040 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 3041 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 3042 }; 3043 static const CostTblEntry SLMCostTbl[] = { 3044 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 3045 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 3046 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 3047 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 3048 }; 3049 static const CostTblEntry SSE42CostTbl[] = { 3050 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 3051 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 3052 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 3053 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 3054 }; 3055 static const CostTblEntry SSE41CostTbl[] = { 3056 { ISD::ABS, MVT::v2i64, 2 }, // BLENDVPD(X,PSUBQ(0,X),X) 3057 { ISD::SMAX, MVT::v4i32, 1 }, 3058 { ISD::SMAX, MVT::v16i8, 1 }, 3059 { ISD::SMIN, MVT::v4i32, 1 }, 3060 { ISD::SMIN, MVT::v16i8, 1 }, 3061 { ISD::UMAX, MVT::v4i32, 1 }, 3062 { ISD::UMAX, MVT::v8i16, 1 }, 3063 { ISD::UMIN, MVT::v4i32, 1 }, 3064 { ISD::UMIN, MVT::v8i16, 1 }, 3065 }; 3066 static const CostTblEntry SSSE3CostTbl[] = { 3067 { ISD::ABS, MVT::v4i32, 1 }, 3068 { ISD::ABS, MVT::v8i16, 1 }, 3069 { ISD::ABS, MVT::v16i8, 1 }, 3070 { ISD::BITREVERSE, MVT::v2i64, 5 }, 3071 { ISD::BITREVERSE, MVT::v4i32, 5 }, 3072 { ISD::BITREVERSE, MVT::v8i16, 5 }, 3073 { ISD::BITREVERSE, MVT::v16i8, 5 }, 3074 { ISD::BSWAP, MVT::v2i64, 1 }, 3075 { ISD::BSWAP, MVT::v4i32, 1 }, 3076 { ISD::BSWAP, MVT::v8i16, 1 }, 3077 { ISD::CTLZ, MVT::v2i64, 23 }, 3078 { ISD::CTLZ, MVT::v4i32, 18 }, 3079 { ISD::CTLZ, MVT::v8i16, 14 }, 3080 { ISD::CTLZ, MVT::v16i8, 9 }, 3081 { ISD::CTPOP, MVT::v2i64, 7 }, 3082 { ISD::CTPOP, MVT::v4i32, 11 }, 3083 { ISD::CTPOP, MVT::v8i16, 9 }, 3084 { ISD::CTPOP, MVT::v16i8, 6 }, 3085 { ISD::CTTZ, MVT::v2i64, 10 }, 3086 { ISD::CTTZ, MVT::v4i32, 14 }, 3087 { ISD::CTTZ, MVT::v8i16, 12 }, 3088 { ISD::CTTZ, MVT::v16i8, 9 } 3089 }; 3090 static const CostTblEntry SSE2CostTbl[] = { 3091 { ISD::ABS, MVT::v2i64, 4 }, 3092 { ISD::ABS, MVT::v4i32, 3 }, 3093 { ISD::ABS, MVT::v8i16, 2 }, 3094 { ISD::ABS, MVT::v16i8, 2 }, 3095 { ISD::BITREVERSE, MVT::v2i64, 29 }, 3096 { ISD::BITREVERSE, MVT::v4i32, 27 }, 3097 { ISD::BITREVERSE, MVT::v8i16, 27 }, 3098 { ISD::BITREVERSE, MVT::v16i8, 20 }, 3099 { ISD::BSWAP, MVT::v2i64, 7 }, 3100 { ISD::BSWAP, MVT::v4i32, 7 }, 3101 { ISD::BSWAP, MVT::v8i16, 7 }, 3102 { ISD::CTLZ, MVT::v2i64, 25 }, 3103 { ISD::CTLZ, MVT::v4i32, 26 }, 3104 { ISD::CTLZ, MVT::v8i16, 20 }, 3105 { ISD::CTLZ, MVT::v16i8, 17 }, 3106 { ISD::CTPOP, MVT::v2i64, 12 }, 3107 { ISD::CTPOP, MVT::v4i32, 15 }, 3108 { ISD::CTPOP, MVT::v8i16, 13 }, 3109 { ISD::CTPOP, MVT::v16i8, 10 }, 3110 { ISD::CTTZ, MVT::v2i64, 14 }, 3111 { ISD::CTTZ, MVT::v4i32, 18 }, 3112 { ISD::CTTZ, MVT::v8i16, 16 }, 3113 { ISD::CTTZ, MVT::v16i8, 13 }, 3114 { ISD::SADDSAT, MVT::v8i16, 1 }, 3115 { ISD::SADDSAT, MVT::v16i8, 1 }, 3116 { ISD::SMAX, MVT::v8i16, 1 }, 3117 { ISD::SMIN, MVT::v8i16, 1 }, 3118 { ISD::SSUBSAT, MVT::v8i16, 1 }, 3119 { ISD::SSUBSAT, MVT::v16i8, 1 }, 3120 { ISD::UADDSAT, MVT::v8i16, 1 }, 3121 { ISD::UADDSAT, MVT::v16i8, 1 }, 3122 { ISD::UMAX, MVT::v8i16, 2 }, 3123 { ISD::UMAX, MVT::v16i8, 1 }, 3124 { ISD::UMIN, MVT::v8i16, 2 }, 3125 { ISD::UMIN, MVT::v16i8, 1 }, 3126 { ISD::USUBSAT, MVT::v8i16, 1 }, 3127 { ISD::USUBSAT, MVT::v16i8, 1 }, 3128 { ISD::FMAXNUM, MVT::f64, 4 }, 3129 { ISD::FMAXNUM, MVT::v2f64, 4 }, 3130 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 3131 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 3132 }; 3133 static const CostTblEntry SSE1CostTbl[] = { 3134 { ISD::FMAXNUM, MVT::f32, 4 }, 3135 { ISD::FMAXNUM, MVT::v4f32, 4 }, 3136 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 3137 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 3138 }; 3139 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 3140 { ISD::CTTZ, MVT::i64, 1 }, 3141 }; 3142 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 3143 { ISD::CTTZ, MVT::i32, 1 }, 3144 { ISD::CTTZ, MVT::i16, 1 }, 3145 { ISD::CTTZ, MVT::i8, 1 }, 3146 }; 3147 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 3148 { ISD::CTLZ, MVT::i64, 1 }, 3149 }; 3150 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 3151 { ISD::CTLZ, MVT::i32, 1 }, 3152 { ISD::CTLZ, MVT::i16, 1 }, 3153 { ISD::CTLZ, MVT::i8, 1 }, 3154 }; 3155 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 3156 { ISD::CTPOP, MVT::i64, 1 }, 3157 }; 3158 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 3159 { ISD::CTPOP, MVT::i32, 1 }, 3160 { ISD::CTPOP, MVT::i16, 1 }, 3161 { ISD::CTPOP, MVT::i8, 1 }, 3162 }; 3163 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 3164 { ISD::ABS, MVT::i64, 2 }, // SUB+CMOV 3165 { ISD::BITREVERSE, MVT::i64, 14 }, 3166 { ISD::BSWAP, MVT::i64, 1 }, 3167 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 3168 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 3169 { ISD::CTPOP, MVT::i64, 10 }, 3170 { ISD::SADDO, MVT::i64, 1 }, 3171 { ISD::UADDO, MVT::i64, 1 }, 3172 { ISD::UMULO, MVT::i64, 2 }, // mulq + seto 3173 }; 3174 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 3175 { ISD::ABS, MVT::i32, 2 }, // SUB+CMOV 3176 { ISD::ABS, MVT::i16, 2 }, // SUB+CMOV 3177 { ISD::BITREVERSE, MVT::i32, 14 }, 3178 { ISD::BITREVERSE, MVT::i16, 14 }, 3179 { ISD::BITREVERSE, MVT::i8, 11 }, 3180 { ISD::BSWAP, MVT::i32, 1 }, 3181 { ISD::BSWAP, MVT::i16, 1 }, // ROL 3182 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 3183 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 3184 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 3185 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 3186 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 3187 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 3188 { ISD::CTPOP, MVT::i32, 8 }, 3189 { ISD::CTPOP, MVT::i16, 9 }, 3190 { ISD::CTPOP, MVT::i8, 7 }, 3191 { ISD::SADDO, MVT::i32, 1 }, 3192 { ISD::SADDO, MVT::i16, 1 }, 3193 { ISD::SADDO, MVT::i8, 1 }, 3194 { ISD::UADDO, MVT::i32, 1 }, 3195 { ISD::UADDO, MVT::i16, 1 }, 3196 { ISD::UADDO, MVT::i8, 1 }, 3197 { ISD::UMULO, MVT::i32, 2 }, // mul + seto 3198 { ISD::UMULO, MVT::i16, 2 }, 3199 { ISD::UMULO, MVT::i8, 2 }, 3200 }; 3201 3202 Type *RetTy = ICA.getReturnType(); 3203 Type *OpTy = RetTy; 3204 Intrinsic::ID IID = ICA.getID(); 3205 unsigned ISD = ISD::DELETED_NODE; 3206 switch (IID) { 3207 default: 3208 break; 3209 case Intrinsic::abs: 3210 ISD = ISD::ABS; 3211 break; 3212 case Intrinsic::bitreverse: 3213 ISD = ISD::BITREVERSE; 3214 break; 3215 case Intrinsic::bswap: 3216 ISD = ISD::BSWAP; 3217 break; 3218 case Intrinsic::ctlz: 3219 ISD = ISD::CTLZ; 3220 break; 3221 case Intrinsic::ctpop: 3222 ISD = ISD::CTPOP; 3223 break; 3224 case Intrinsic::cttz: 3225 ISD = ISD::CTTZ; 3226 break; 3227 case Intrinsic::maxnum: 3228 case Intrinsic::minnum: 3229 // FMINNUM has same costs so don't duplicate. 3230 ISD = ISD::FMAXNUM; 3231 break; 3232 case Intrinsic::sadd_sat: 3233 ISD = ISD::SADDSAT; 3234 break; 3235 case Intrinsic::smax: 3236 ISD = ISD::SMAX; 3237 break; 3238 case Intrinsic::smin: 3239 ISD = ISD::SMIN; 3240 break; 3241 case Intrinsic::ssub_sat: 3242 ISD = ISD::SSUBSAT; 3243 break; 3244 case Intrinsic::uadd_sat: 3245 ISD = ISD::UADDSAT; 3246 break; 3247 case Intrinsic::umax: 3248 ISD = ISD::UMAX; 3249 break; 3250 case Intrinsic::umin: 3251 ISD = ISD::UMIN; 3252 break; 3253 case Intrinsic::usub_sat: 3254 ISD = ISD::USUBSAT; 3255 break; 3256 case Intrinsic::sqrt: 3257 ISD = ISD::FSQRT; 3258 break; 3259 case Intrinsic::sadd_with_overflow: 3260 case Intrinsic::ssub_with_overflow: 3261 // SSUBO has same costs so don't duplicate. 3262 ISD = ISD::SADDO; 3263 OpTy = RetTy->getContainedType(0); 3264 break; 3265 case Intrinsic::uadd_with_overflow: 3266 case Intrinsic::usub_with_overflow: 3267 // USUBO has same costs so don't duplicate. 3268 ISD = ISD::UADDO; 3269 OpTy = RetTy->getContainedType(0); 3270 break; 3271 case Intrinsic::umul_with_overflow: 3272 case Intrinsic::smul_with_overflow: 3273 // SMULO has same costs so don't duplicate. 3274 ISD = ISD::UMULO; 3275 OpTy = RetTy->getContainedType(0); 3276 break; 3277 } 3278 3279 if (ISD != ISD::DELETED_NODE) { 3280 // Legalize the type. 3281 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 3282 MVT MTy = LT.second; 3283 3284 // Attempt to lookup cost. 3285 if (ISD == ISD::BITREVERSE && ST->hasGFNI() && ST->hasSSSE3() && 3286 MTy.isVector()) { 3287 // With PSHUFB the code is very similar for all types. If we have integer 3288 // byte operations, we just need a GF2P8AFFINEQB for vXi8. For other types 3289 // we also need a PSHUFB. 3290 unsigned Cost = MTy.getVectorElementType() == MVT::i8 ? 1 : 2; 3291 3292 // Without byte operations, we need twice as many GF2P8AFFINEQB and PSHUFB 3293 // instructions. We also need an extract and an insert. 3294 if (!(MTy.is128BitVector() || (ST->hasAVX2() && MTy.is256BitVector()) || 3295 (ST->hasBWI() && MTy.is512BitVector()))) 3296 Cost = Cost * 2 + 2; 3297 3298 return LT.first * Cost; 3299 } 3300 3301 auto adjustTableCost = [](const CostTblEntry &Entry, 3302 InstructionCost LegalizationCost, 3303 FastMathFlags FMF) { 3304 // If there are no NANs to deal with, then these are reduced to a 3305 // single MIN** or MAX** instruction instead of the MIN/CMP/SELECT that we 3306 // assume is used in the non-fast case. 3307 if (Entry.ISD == ISD::FMAXNUM || Entry.ISD == ISD::FMINNUM) { 3308 if (FMF.noNaNs()) 3309 return LegalizationCost * 1; 3310 } 3311 return LegalizationCost * (int)Entry.Cost; 3312 }; 3313 3314 if (ST->useGLMDivSqrtCosts()) 3315 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 3316 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3317 3318 if (ST->useSLMArithCosts()) 3319 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 3320 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3321 3322 if (ST->hasBITALG()) 3323 if (const auto *Entry = CostTableLookup(AVX512BITALGCostTbl, ISD, MTy)) 3324 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3325 3326 if (ST->hasVPOPCNTDQ()) 3327 if (const auto *Entry = CostTableLookup(AVX512VPOPCNTDQCostTbl, ISD, MTy)) 3328 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3329 3330 if (ST->hasCDI()) 3331 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 3332 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3333 3334 if (ST->hasBWI()) 3335 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3336 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3337 3338 if (ST->hasAVX512()) 3339 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3340 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3341 3342 if (ST->hasXOP()) 3343 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3344 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3345 3346 if (ST->hasAVX2()) 3347 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3348 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3349 3350 if (ST->hasAVX()) 3351 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3352 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3353 3354 if (ST->hasSSE42()) 3355 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3356 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3357 3358 if (ST->hasSSE41()) 3359 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3360 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3361 3362 if (ST->hasSSSE3()) 3363 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 3364 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3365 3366 if (ST->hasSSE2()) 3367 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3368 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3369 3370 if (ST->hasSSE1()) 3371 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3372 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3373 3374 if (ST->hasBMI()) { 3375 if (ST->is64Bit()) 3376 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 3377 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3378 3379 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 3380 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3381 } 3382 3383 if (ST->hasLZCNT()) { 3384 if (ST->is64Bit()) 3385 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 3386 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3387 3388 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 3389 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3390 } 3391 3392 if (ST->hasPOPCNT()) { 3393 if (ST->is64Bit()) 3394 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 3395 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3396 3397 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 3398 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3399 } 3400 3401 if (ISD == ISD::BSWAP && ST->hasMOVBE() && ST->hasFastMOVBE()) { 3402 if (const Instruction *II = ICA.getInst()) { 3403 if (II->hasOneUse() && isa<StoreInst>(II->user_back())) 3404 return TTI::TCC_Free; 3405 if (auto *LI = dyn_cast<LoadInst>(II->getOperand(0))) { 3406 if (LI->hasOneUse()) 3407 return TTI::TCC_Free; 3408 } 3409 } 3410 } 3411 3412 if (ST->is64Bit()) 3413 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3414 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3415 3416 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3417 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3418 } 3419 3420 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3421 } 3422 3423 InstructionCost 3424 X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 3425 TTI::TargetCostKind CostKind) { 3426 if (ICA.isTypeBasedOnly()) 3427 return getTypeBasedIntrinsicInstrCost(ICA, CostKind); 3428 3429 static const CostTblEntry AVX512CostTbl[] = { 3430 { ISD::ROTL, MVT::v8i64, 1 }, 3431 { ISD::ROTL, MVT::v4i64, 1 }, 3432 { ISD::ROTL, MVT::v2i64, 1 }, 3433 { ISD::ROTL, MVT::v16i32, 1 }, 3434 { ISD::ROTL, MVT::v8i32, 1 }, 3435 { ISD::ROTL, MVT::v4i32, 1 }, 3436 { ISD::ROTR, MVT::v8i64, 1 }, 3437 { ISD::ROTR, MVT::v4i64, 1 }, 3438 { ISD::ROTR, MVT::v2i64, 1 }, 3439 { ISD::ROTR, MVT::v16i32, 1 }, 3440 { ISD::ROTR, MVT::v8i32, 1 }, 3441 { ISD::ROTR, MVT::v4i32, 1 } 3442 }; 3443 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 3444 static const CostTblEntry XOPCostTbl[] = { 3445 { ISD::ROTL, MVT::v4i64, 4 }, 3446 { ISD::ROTL, MVT::v8i32, 4 }, 3447 { ISD::ROTL, MVT::v16i16, 4 }, 3448 { ISD::ROTL, MVT::v32i8, 4 }, 3449 { ISD::ROTL, MVT::v2i64, 1 }, 3450 { ISD::ROTL, MVT::v4i32, 1 }, 3451 { ISD::ROTL, MVT::v8i16, 1 }, 3452 { ISD::ROTL, MVT::v16i8, 1 }, 3453 { ISD::ROTR, MVT::v4i64, 6 }, 3454 { ISD::ROTR, MVT::v8i32, 6 }, 3455 { ISD::ROTR, MVT::v16i16, 6 }, 3456 { ISD::ROTR, MVT::v32i8, 6 }, 3457 { ISD::ROTR, MVT::v2i64, 2 }, 3458 { ISD::ROTR, MVT::v4i32, 2 }, 3459 { ISD::ROTR, MVT::v8i16, 2 }, 3460 { ISD::ROTR, MVT::v16i8, 2 } 3461 }; 3462 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 3463 { ISD::ROTL, MVT::i64, 1 }, 3464 { ISD::ROTR, MVT::i64, 1 }, 3465 { ISD::FSHL, MVT::i64, 4 } 3466 }; 3467 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 3468 { ISD::ROTL, MVT::i32, 1 }, 3469 { ISD::ROTL, MVT::i16, 1 }, 3470 { ISD::ROTL, MVT::i8, 1 }, 3471 { ISD::ROTR, MVT::i32, 1 }, 3472 { ISD::ROTR, MVT::i16, 1 }, 3473 { ISD::ROTR, MVT::i8, 1 }, 3474 { ISD::FSHL, MVT::i32, 4 }, 3475 { ISD::FSHL, MVT::i16, 4 }, 3476 { ISD::FSHL, MVT::i8, 4 } 3477 }; 3478 3479 Intrinsic::ID IID = ICA.getID(); 3480 Type *RetTy = ICA.getReturnType(); 3481 const SmallVectorImpl<const Value *> &Args = ICA.getArgs(); 3482 unsigned ISD = ISD::DELETED_NODE; 3483 switch (IID) { 3484 default: 3485 break; 3486 case Intrinsic::fshl: 3487 ISD = ISD::FSHL; 3488 if (Args[0] == Args[1]) 3489 ISD = ISD::ROTL; 3490 break; 3491 case Intrinsic::fshr: 3492 // FSHR has same costs so don't duplicate. 3493 ISD = ISD::FSHL; 3494 if (Args[0] == Args[1]) 3495 ISD = ISD::ROTR; 3496 break; 3497 } 3498 3499 if (ISD != ISD::DELETED_NODE) { 3500 // Legalize the type. 3501 std::pair<InstructionCost, MVT> LT = 3502 TLI->getTypeLegalizationCost(DL, RetTy); 3503 MVT MTy = LT.second; 3504 3505 // Attempt to lookup cost. 3506 if (ST->hasAVX512()) 3507 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3508 return LT.first * Entry->Cost; 3509 3510 if (ST->hasXOP()) 3511 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3512 return LT.first * Entry->Cost; 3513 3514 if (ST->is64Bit()) 3515 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3516 return LT.first * Entry->Cost; 3517 3518 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3519 return LT.first * Entry->Cost; 3520 } 3521 3522 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3523 } 3524 3525 InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, 3526 unsigned Index) { 3527 static const CostTblEntry SLMCostTbl[] = { 3528 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 3529 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 3530 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 3531 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 3532 }; 3533 3534 assert(Val->isVectorTy() && "This must be a vector type"); 3535 Type *ScalarType = Val->getScalarType(); 3536 int RegisterFileMoveCost = 0; 3537 3538 // Non-immediate extraction/insertion can be handled as a sequence of 3539 // aliased loads+stores via the stack. 3540 if (Index == -1U && (Opcode == Instruction::ExtractElement || 3541 Opcode == Instruction::InsertElement)) { 3542 // TODO: On some SSE41+ targets, we expand to cmp+splat+select patterns: 3543 // inselt N0, N1, N2 --> select (SplatN2 == {0,1,2...}) ? SplatN1 : N0. 3544 3545 // TODO: Move this to BasicTTIImpl.h? We'd need better gep + index handling. 3546 assert(isa<FixedVectorType>(Val) && "Fixed vector type expected"); 3547 Align VecAlign = DL.getPrefTypeAlign(Val); 3548 Align SclAlign = DL.getPrefTypeAlign(ScalarType); 3549 3550 // Extract - store vector to stack, load scalar. 3551 if (Opcode == Instruction::ExtractElement) { 3552 return getMemoryOpCost(Instruction::Store, Val, VecAlign, 0, 3553 TTI::TargetCostKind::TCK_RecipThroughput) + 3554 getMemoryOpCost(Instruction::Load, ScalarType, SclAlign, 0, 3555 TTI::TargetCostKind::TCK_RecipThroughput); 3556 } 3557 // Insert - store vector to stack, store scalar, load vector. 3558 if (Opcode == Instruction::InsertElement) { 3559 return getMemoryOpCost(Instruction::Store, Val, VecAlign, 0, 3560 TTI::TargetCostKind::TCK_RecipThroughput) + 3561 getMemoryOpCost(Instruction::Store, ScalarType, SclAlign, 0, 3562 TTI::TargetCostKind::TCK_RecipThroughput) + 3563 getMemoryOpCost(Instruction::Load, Val, VecAlign, 0, 3564 TTI::TargetCostKind::TCK_RecipThroughput); 3565 } 3566 } 3567 3568 if (Index != -1U && (Opcode == Instruction::ExtractElement || 3569 Opcode == Instruction::InsertElement)) { 3570 // Legalize the type. 3571 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 3572 3573 // This type is legalized to a scalar type. 3574 if (!LT.second.isVector()) 3575 return 0; 3576 3577 // The type may be split. Normalize the index to the new type. 3578 unsigned NumElts = LT.second.getVectorNumElements(); 3579 unsigned SubNumElts = NumElts; 3580 Index = Index % NumElts; 3581 3582 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 3583 // For inserts, we also need to insert the subvector back. 3584 if (LT.second.getSizeInBits() > 128) { 3585 assert((LT.second.getSizeInBits() % 128) == 0 && "Illegal vector"); 3586 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 3587 SubNumElts = NumElts / NumSubVecs; 3588 if (SubNumElts <= Index) { 3589 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 3590 Index %= SubNumElts; 3591 } 3592 } 3593 3594 if (Index == 0) { 3595 // Floating point scalars are already located in index #0. 3596 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 3597 // true for all. 3598 if (ScalarType->isFloatingPointTy()) 3599 return RegisterFileMoveCost; 3600 3601 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 3602 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 3603 return 1 + RegisterFileMoveCost; 3604 } 3605 3606 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3607 assert(ISD && "Unexpected vector opcode"); 3608 MVT MScalarTy = LT.second.getScalarType(); 3609 if (ST->useSLMArithCosts()) 3610 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 3611 return Entry->Cost + RegisterFileMoveCost; 3612 3613 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 3614 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3615 (MScalarTy.isInteger() && ST->hasSSE41())) 3616 return 1 + RegisterFileMoveCost; 3617 3618 // Assume insertps is relatively cheap on all targets. 3619 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 3620 Opcode == Instruction::InsertElement) 3621 return 1 + RegisterFileMoveCost; 3622 3623 // For extractions we just need to shuffle the element to index 0, which 3624 // should be very cheap (assume cost = 1). For insertions we need to shuffle 3625 // the elements to its destination. In both cases we must handle the 3626 // subvector move(s). 3627 // If the vector type is already less than 128-bits then don't reduce it. 3628 // TODO: Under what circumstances should we shuffle using the full width? 3629 InstructionCost ShuffleCost = 1; 3630 if (Opcode == Instruction::InsertElement) { 3631 auto *SubTy = cast<VectorType>(Val); 3632 EVT VT = TLI->getValueType(DL, Val); 3633 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 3634 SubTy = FixedVectorType::get(ScalarType, SubNumElts); 3635 ShuffleCost = 3636 getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, None, 0, SubTy); 3637 } 3638 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 3639 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 3640 } 3641 3642 // Add to the base cost if we know that the extracted element of a vector is 3643 // destined to be moved to and used in the integer register file. 3644 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 3645 RegisterFileMoveCost += 1; 3646 3647 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 3648 } 3649 3650 InstructionCost X86TTIImpl::getScalarizationOverhead(VectorType *Ty, 3651 const APInt &DemandedElts, 3652 bool Insert, 3653 bool Extract) { 3654 InstructionCost Cost = 0; 3655 3656 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much 3657 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT. 3658 if (Insert) { 3659 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3660 MVT MScalarTy = LT.second.getScalarType(); 3661 3662 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3663 (MScalarTy.isInteger() && ST->hasSSE41()) || 3664 (MScalarTy == MVT::f32 && ST->hasSSE41())) { 3665 // For types we can insert directly, insertion into 128-bit sub vectors is 3666 // cheap, followed by a cheap chain of concatenations. 3667 if (LT.second.getSizeInBits() <= 128) { 3668 Cost += 3669 BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, false); 3670 } else { 3671 // In each 128-lane, if at least one index is demanded but not all 3672 // indices are demanded and this 128-lane is not the first 128-lane of 3673 // the legalized-vector, then this 128-lane needs a extracti128; If in 3674 // each 128-lane, there is at least one demanded index, this 128-lane 3675 // needs a inserti128. 3676 3677 // The following cases will help you build a better understanding: 3678 // Assume we insert several elements into a v8i32 vector in avx2, 3679 // Case#1: inserting into 1th index needs vpinsrd + inserti128. 3680 // Case#2: inserting into 5th index needs extracti128 + vpinsrd + 3681 // inserti128. 3682 // Case#3: inserting into 4,5,6,7 index needs 4*vpinsrd + inserti128. 3683 const int CostValue = *LT.first.getValue(); 3684 assert(CostValue >= 0 && "Negative cost!"); 3685 unsigned Num128Lanes = LT.second.getSizeInBits() / 128 * CostValue; 3686 unsigned NumElts = LT.second.getVectorNumElements() * CostValue; 3687 APInt WidenedDemandedElts = DemandedElts.zextOrSelf(NumElts); 3688 unsigned Scale = NumElts / Num128Lanes; 3689 // We iterate each 128-lane, and check if we need a 3690 // extracti128/inserti128 for this 128-lane. 3691 for (unsigned I = 0; I < NumElts; I += Scale) { 3692 APInt Mask = WidenedDemandedElts.getBitsSet(NumElts, I, I + Scale); 3693 APInt MaskedDE = Mask & WidenedDemandedElts; 3694 unsigned Population = MaskedDE.countPopulation(); 3695 Cost += (Population > 0 && Population != Scale && 3696 I % LT.second.getVectorNumElements() != 0); 3697 Cost += Population > 0; 3698 } 3699 Cost += DemandedElts.countPopulation(); 3700 3701 // For vXf32 cases, insertion into the 0'th index in each v4f32 3702 // 128-bit vector is free. 3703 // NOTE: This assumes legalization widens vXf32 vectors. 3704 if (MScalarTy == MVT::f32) 3705 for (unsigned i = 0, e = cast<FixedVectorType>(Ty)->getNumElements(); 3706 i < e; i += 4) 3707 if (DemandedElts[i]) 3708 Cost--; 3709 } 3710 } else if (LT.second.isVector()) { 3711 // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded 3712 // integer element as a SCALAR_TO_VECTOR, then we build the vector as a 3713 // series of UNPCK followed by CONCAT_VECTORS - all of these can be 3714 // considered cheap. 3715 if (Ty->isIntOrIntVectorTy()) 3716 Cost += DemandedElts.countPopulation(); 3717 3718 // Get the smaller of the legalized or original pow2-extended number of 3719 // vector elements, which represents the number of unpacks we'll end up 3720 // performing. 3721 unsigned NumElts = LT.second.getVectorNumElements(); 3722 unsigned Pow2Elts = 3723 PowerOf2Ceil(cast<FixedVectorType>(Ty)->getNumElements()); 3724 Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first; 3725 } 3726 } 3727 3728 // TODO: Use default extraction for now, but we should investigate extending this 3729 // to handle repeated subvector extraction. 3730 if (Extract) 3731 Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, false, Extract); 3732 3733 return Cost; 3734 } 3735 3736 InstructionCost 3737 X86TTIImpl::getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, 3738 int VF, const APInt &DemandedDstElts, 3739 TTI::TargetCostKind CostKind) { 3740 const unsigned EltTyBits = DL.getTypeSizeInBits(EltTy); 3741 // We don't differentiate element types here, only element bit width. 3742 EltTy = IntegerType::getIntNTy(EltTy->getContext(), EltTyBits); 3743 3744 auto bailout = [&]() { 3745 return BaseT::getReplicationShuffleCost(EltTy, ReplicationFactor, VF, 3746 DemandedDstElts, CostKind); 3747 }; 3748 3749 // For now, only deal with AVX512 cases. 3750 if (!ST->hasAVX512()) 3751 return bailout(); 3752 3753 // Do we have a native shuffle for this element type, or should we promote? 3754 unsigned PromEltTyBits = EltTyBits; 3755 switch (EltTyBits) { 3756 case 32: 3757 case 64: 3758 break; // AVX512F. 3759 case 16: 3760 if (!ST->hasBWI()) 3761 PromEltTyBits = 32; // promote to i32, AVX512F. 3762 break; // AVX512BW 3763 case 8: 3764 if (!ST->hasVBMI()) 3765 PromEltTyBits = 32; // promote to i32, AVX512F. 3766 break; // AVX512VBMI 3767 case 1: 3768 // There is no support for shuffling i1 elements. We *must* promote. 3769 if (ST->hasBWI()) { 3770 if (ST->hasVBMI()) 3771 PromEltTyBits = 8; // promote to i8, AVX512VBMI. 3772 else 3773 PromEltTyBits = 16; // promote to i16, AVX512BW. 3774 break; 3775 } 3776 if (ST->hasDQI()) { 3777 PromEltTyBits = 32; // promote to i32, AVX512F. 3778 break; 3779 } 3780 return bailout(); 3781 default: 3782 return bailout(); 3783 } 3784 auto *PromEltTy = IntegerType::getIntNTy(EltTy->getContext(), PromEltTyBits); 3785 3786 auto *SrcVecTy = FixedVectorType::get(EltTy, VF); 3787 auto *PromSrcVecTy = FixedVectorType::get(PromEltTy, VF); 3788 3789 int NumDstElements = VF * ReplicationFactor; 3790 auto *PromDstVecTy = FixedVectorType::get(PromEltTy, NumDstElements); 3791 auto *DstVecTy = FixedVectorType::get(EltTy, NumDstElements); 3792 3793 // Legalize the types. 3794 MVT LegalSrcVecTy = TLI->getTypeLegalizationCost(DL, SrcVecTy).second; 3795 MVT LegalPromSrcVecTy = TLI->getTypeLegalizationCost(DL, PromSrcVecTy).second; 3796 MVT LegalPromDstVecTy = TLI->getTypeLegalizationCost(DL, PromDstVecTy).second; 3797 MVT LegalDstVecTy = TLI->getTypeLegalizationCost(DL, DstVecTy).second; 3798 // They should have legalized into vector types. 3799 if (!LegalSrcVecTy.isVector() || !LegalPromSrcVecTy.isVector() || 3800 !LegalPromDstVecTy.isVector() || !LegalDstVecTy.isVector()) 3801 return bailout(); 3802 3803 if (PromEltTyBits != EltTyBits) { 3804 // If we have to perform the shuffle with wider elt type than our data type, 3805 // then we will first need to anyext (we don't care about the new bits) 3806 // the source elements, and then truncate Dst elements. 3807 InstructionCost PromotionCost; 3808 PromotionCost += getCastInstrCost( 3809 Instruction::SExt, /*Dst=*/PromSrcVecTy, /*Src=*/SrcVecTy, 3810 TargetTransformInfo::CastContextHint::None, CostKind); 3811 PromotionCost += 3812 getCastInstrCost(Instruction::Trunc, /*Dst=*/DstVecTy, 3813 /*Src=*/PromDstVecTy, 3814 TargetTransformInfo::CastContextHint::None, CostKind); 3815 return PromotionCost + getReplicationShuffleCost(PromEltTy, 3816 ReplicationFactor, VF, 3817 DemandedDstElts, CostKind); 3818 } 3819 3820 assert(LegalSrcVecTy.getScalarSizeInBits() == EltTyBits && 3821 LegalSrcVecTy.getScalarType() == LegalDstVecTy.getScalarType() && 3822 "We expect that the legalization doesn't affect the element width, " 3823 "doesn't coalesce/split elements."); 3824 3825 unsigned NumEltsPerDstVec = LegalDstVecTy.getVectorNumElements(); 3826 unsigned NumDstVectors = 3827 divideCeil(DstVecTy->getNumElements(), NumEltsPerDstVec); 3828 3829 auto *SingleDstVecTy = FixedVectorType::get(EltTy, NumEltsPerDstVec); 3830 3831 // Not all the produced Dst elements may be demanded. In our case, 3832 // given that a single Dst vector is formed by a single shuffle, 3833 // if all elements that will form a single Dst vector aren't demanded, 3834 // then we won't need to do that shuffle, so adjust the cost accordingly. 3835 APInt DemandedDstVectors = APIntOps::ScaleBitMask( 3836 DemandedDstElts.zextOrSelf(NumDstVectors * NumEltsPerDstVec), 3837 NumDstVectors); 3838 unsigned NumDstVectorsDemanded = DemandedDstVectors.countPopulation(); 3839 3840 InstructionCost SingleShuffleCost = 3841 getShuffleCost(TTI::SK_PermuteSingleSrc, SingleDstVecTy, 3842 /*Mask=*/None, /*Index=*/0, /*SubTp=*/nullptr); 3843 return NumDstVectorsDemanded * SingleShuffleCost; 3844 } 3845 3846 InstructionCost X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 3847 MaybeAlign Alignment, 3848 unsigned AddressSpace, 3849 TTI::TargetCostKind CostKind, 3850 const Instruction *I) { 3851 // TODO: Handle other cost kinds. 3852 if (CostKind != TTI::TCK_RecipThroughput) { 3853 if (auto *SI = dyn_cast_or_null<StoreInst>(I)) { 3854 // Store instruction with index and scale costs 2 Uops. 3855 // Check the preceding GEP to identify non-const indices. 3856 if (auto *GEP = dyn_cast<GetElementPtrInst>(SI->getPointerOperand())) { 3857 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3858 return TTI::TCC_Basic * 2; 3859 } 3860 } 3861 return TTI::TCC_Basic; 3862 } 3863 3864 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 3865 "Invalid Opcode"); 3866 // Type legalization can't handle structs 3867 if (TLI->getValueType(DL, Src, true) == MVT::Other) 3868 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3869 CostKind); 3870 3871 // Legalize the type. 3872 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 3873 3874 auto *VTy = dyn_cast<FixedVectorType>(Src); 3875 3876 // Handle the simple case of non-vectors. 3877 // NOTE: this assumes that legalization never creates vector from scalars! 3878 if (!VTy || !LT.second.isVector()) 3879 // Each load/store unit costs 1. 3880 return LT.first * 1; 3881 3882 bool IsLoad = Opcode == Instruction::Load; 3883 3884 Type *EltTy = VTy->getElementType(); 3885 3886 const int EltTyBits = DL.getTypeSizeInBits(EltTy); 3887 3888 InstructionCost Cost = 0; 3889 3890 // Source of truth: how many elements were there in the original IR vector? 3891 const unsigned SrcNumElt = VTy->getNumElements(); 3892 3893 // How far have we gotten? 3894 int NumEltRemaining = SrcNumElt; 3895 // Note that we intentionally capture by-reference, NumEltRemaining changes. 3896 auto NumEltDone = [&]() { return SrcNumElt - NumEltRemaining; }; 3897 3898 const int MaxLegalOpSizeBytes = divideCeil(LT.second.getSizeInBits(), 8); 3899 3900 // Note that even if we can store 64 bits of an XMM, we still operate on XMM. 3901 const unsigned XMMBits = 128; 3902 if (XMMBits % EltTyBits != 0) 3903 // Vector size must be a multiple of the element size. I.e. no padding. 3904 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3905 CostKind); 3906 const int NumEltPerXMM = XMMBits / EltTyBits; 3907 3908 auto *XMMVecTy = FixedVectorType::get(EltTy, NumEltPerXMM); 3909 3910 for (int CurrOpSizeBytes = MaxLegalOpSizeBytes, SubVecEltsLeft = 0; 3911 NumEltRemaining > 0; CurrOpSizeBytes /= 2) { 3912 // How many elements would a single op deal with at once? 3913 if ((8 * CurrOpSizeBytes) % EltTyBits != 0) 3914 // Vector size must be a multiple of the element size. I.e. no padding. 3915 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3916 CostKind); 3917 int CurrNumEltPerOp = (8 * CurrOpSizeBytes) / EltTyBits; 3918 3919 assert(CurrOpSizeBytes > 0 && CurrNumEltPerOp > 0 && "How'd we get here?"); 3920 assert((((NumEltRemaining * EltTyBits) < (2 * 8 * CurrOpSizeBytes)) || 3921 (CurrOpSizeBytes == MaxLegalOpSizeBytes)) && 3922 "Unless we haven't halved the op size yet, " 3923 "we have less than two op's sized units of work left."); 3924 3925 auto *CurrVecTy = CurrNumEltPerOp > NumEltPerXMM 3926 ? FixedVectorType::get(EltTy, CurrNumEltPerOp) 3927 : XMMVecTy; 3928 3929 assert(CurrVecTy->getNumElements() % CurrNumEltPerOp == 0 && 3930 "After halving sizes, the vector elt count is no longer a multiple " 3931 "of number of elements per operation?"); 3932 auto *CoalescedVecTy = 3933 CurrNumEltPerOp == 1 3934 ? CurrVecTy 3935 : FixedVectorType::get( 3936 IntegerType::get(Src->getContext(), 3937 EltTyBits * CurrNumEltPerOp), 3938 CurrVecTy->getNumElements() / CurrNumEltPerOp); 3939 assert(DL.getTypeSizeInBits(CoalescedVecTy) == 3940 DL.getTypeSizeInBits(CurrVecTy) && 3941 "coalesciing elements doesn't change vector width."); 3942 3943 while (NumEltRemaining > 0) { 3944 assert(SubVecEltsLeft >= 0 && "Subreg element count overconsumtion?"); 3945 3946 // Can we use this vector size, as per the remaining element count? 3947 // Iff the vector is naturally aligned, we can do a wide load regardless. 3948 if (NumEltRemaining < CurrNumEltPerOp && 3949 (!IsLoad || Alignment.valueOrOne() < CurrOpSizeBytes) && 3950 CurrOpSizeBytes != 1) 3951 break; // Try smalled vector size. 3952 3953 bool Is0thSubVec = (NumEltDone() % LT.second.getVectorNumElements()) == 0; 3954 3955 // If we have fully processed the previous reg, we need to replenish it. 3956 if (SubVecEltsLeft == 0) { 3957 SubVecEltsLeft += CurrVecTy->getNumElements(); 3958 // And that's free only for the 0'th subvector of a legalized vector. 3959 if (!Is0thSubVec) 3960 Cost += getShuffleCost(IsLoad ? TTI::ShuffleKind::SK_InsertSubvector 3961 : TTI::ShuffleKind::SK_ExtractSubvector, 3962 VTy, None, NumEltDone(), CurrVecTy); 3963 } 3964 3965 // While we can directly load/store ZMM, YMM, and 64-bit halves of XMM, 3966 // for smaller widths (32/16/8) we have to insert/extract them separately. 3967 // Again, it's free for the 0'th subreg (if op is 32/64 bit wide, 3968 // but let's pretend that it is also true for 16/8 bit wide ops...) 3969 if (CurrOpSizeBytes <= 32 / 8 && !Is0thSubVec) { 3970 int NumEltDoneInCurrXMM = NumEltDone() % NumEltPerXMM; 3971 assert(NumEltDoneInCurrXMM % CurrNumEltPerOp == 0 && ""); 3972 int CoalescedVecEltIdx = NumEltDoneInCurrXMM / CurrNumEltPerOp; 3973 APInt DemandedElts = 3974 APInt::getBitsSet(CoalescedVecTy->getNumElements(), 3975 CoalescedVecEltIdx, CoalescedVecEltIdx + 1); 3976 assert(DemandedElts.countPopulation() == 1 && "Inserting single value"); 3977 Cost += getScalarizationOverhead(CoalescedVecTy, DemandedElts, IsLoad, 3978 !IsLoad); 3979 } 3980 3981 // This isn't exactly right. We're using slow unaligned 32-byte accesses 3982 // as a proxy for a double-pumped AVX memory interface such as on 3983 // Sandybridge. 3984 if (CurrOpSizeBytes == 32 && ST->isUnalignedMem32Slow()) 3985 Cost += 2; 3986 else 3987 Cost += 1; 3988 3989 SubVecEltsLeft -= CurrNumEltPerOp; 3990 NumEltRemaining -= CurrNumEltPerOp; 3991 Alignment = commonAlignment(Alignment.valueOrOne(), CurrOpSizeBytes); 3992 } 3993 } 3994 3995 assert(NumEltRemaining <= 0 && "Should have processed all the elements."); 3996 3997 return Cost; 3998 } 3999 4000 InstructionCost 4001 X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, Align Alignment, 4002 unsigned AddressSpace, 4003 TTI::TargetCostKind CostKind) { 4004 bool IsLoad = (Instruction::Load == Opcode); 4005 bool IsStore = (Instruction::Store == Opcode); 4006 4007 auto *SrcVTy = dyn_cast<FixedVectorType>(SrcTy); 4008 if (!SrcVTy) 4009 // To calculate scalar take the regular cost, without mask 4010 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace, CostKind); 4011 4012 unsigned NumElem = SrcVTy->getNumElements(); 4013 auto *MaskTy = 4014 FixedVectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 4015 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, Alignment)) || 4016 (IsStore && !isLegalMaskedStore(SrcVTy, Alignment))) { 4017 // Scalarization 4018 APInt DemandedElts = APInt::getAllOnes(NumElem); 4019 InstructionCost MaskSplitCost = 4020 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 4021 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 4022 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr, 4023 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4024 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 4025 InstructionCost MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 4026 InstructionCost ValueSplitCost = 4027 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore); 4028 InstructionCost MemopCost = 4029 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4030 Alignment, AddressSpace, CostKind); 4031 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 4032 } 4033 4034 // Legalize the type. 4035 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 4036 auto VT = TLI->getValueType(DL, SrcVTy); 4037 InstructionCost Cost = 0; 4038 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 4039 LT.second.getVectorNumElements() == NumElem) 4040 // Promotion requires extend/truncate for data and a shuffle for mask. 4041 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, None, 0, nullptr) + 4042 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, None, 0, nullptr); 4043 4044 else if (LT.first * LT.second.getVectorNumElements() > NumElem) { 4045 auto *NewMaskTy = FixedVectorType::get(MaskTy->getElementType(), 4046 LT.second.getVectorNumElements()); 4047 // Expanding requires fill mask with zeroes 4048 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, None, 0, MaskTy); 4049 } 4050 4051 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 4052 if (!ST->hasAVX512()) 4053 return Cost + LT.first * (IsLoad ? 2 : 8); 4054 4055 // AVX-512 masked load/store is cheapper 4056 return Cost + LT.first; 4057 } 4058 4059 InstructionCost X86TTIImpl::getAddressComputationCost(Type *Ty, 4060 ScalarEvolution *SE, 4061 const SCEV *Ptr) { 4062 // Address computations in vectorized code with non-consecutive addresses will 4063 // likely result in more instructions compared to scalar code where the 4064 // computation can more often be merged into the index mode. The resulting 4065 // extra micro-ops can significantly decrease throughput. 4066 const unsigned NumVectorInstToHideOverhead = 10; 4067 4068 // Cost modeling of Strided Access Computation is hidden by the indexing 4069 // modes of X86 regardless of the stride value. We dont believe that there 4070 // is a difference between constant strided access in gerenal and constant 4071 // strided value which is less than or equal to 64. 4072 // Even in the case of (loop invariant) stride whose value is not known at 4073 // compile time, the address computation will not incur more than one extra 4074 // ADD instruction. 4075 if (Ty->isVectorTy() && SE && !ST->hasAVX2()) { 4076 // TODO: AVX2 is the current cut-off because we don't have correct 4077 // interleaving costs for prior ISA's. 4078 if (!BaseT::isStridedAccess(Ptr)) 4079 return NumVectorInstToHideOverhead; 4080 if (!BaseT::getConstantStrideStep(SE, Ptr)) 4081 return 1; 4082 } 4083 4084 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 4085 } 4086 4087 InstructionCost 4088 X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 4089 Optional<FastMathFlags> FMF, 4090 TTI::TargetCostKind CostKind) { 4091 if (TTI::requiresOrderedReduction(FMF)) 4092 return BaseT::getArithmeticReductionCost(Opcode, ValTy, FMF, CostKind); 4093 4094 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 4095 // and make it as the cost. 4096 4097 static const CostTblEntry SLMCostTblNoPairWise[] = { 4098 { ISD::FADD, MVT::v2f64, 3 }, 4099 { ISD::ADD, MVT::v2i64, 5 }, 4100 }; 4101 4102 static const CostTblEntry SSE2CostTblNoPairWise[] = { 4103 { ISD::FADD, MVT::v2f64, 2 }, 4104 { ISD::FADD, MVT::v2f32, 2 }, 4105 { ISD::FADD, MVT::v4f32, 4 }, 4106 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 4107 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 4108 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 4109 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 4110 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 4111 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 4112 { ISD::ADD, MVT::v2i8, 2 }, 4113 { ISD::ADD, MVT::v4i8, 2 }, 4114 { ISD::ADD, MVT::v8i8, 2 }, 4115 { ISD::ADD, MVT::v16i8, 3 }, 4116 }; 4117 4118 static const CostTblEntry AVX1CostTblNoPairWise[] = { 4119 { ISD::FADD, MVT::v4f64, 3 }, 4120 { ISD::FADD, MVT::v4f32, 3 }, 4121 { ISD::FADD, MVT::v8f32, 4 }, 4122 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 4123 { ISD::ADD, MVT::v4i64, 3 }, 4124 { ISD::ADD, MVT::v8i32, 5 }, 4125 { ISD::ADD, MVT::v16i16, 5 }, 4126 { ISD::ADD, MVT::v32i8, 4 }, 4127 }; 4128 4129 int ISD = TLI->InstructionOpcodeToISD(Opcode); 4130 assert(ISD && "Invalid opcode"); 4131 4132 // Before legalizing the type, give a chance to look up illegal narrow types 4133 // in the table. 4134 // FIXME: Is there a better way to do this? 4135 EVT VT = TLI->getValueType(DL, ValTy); 4136 if (VT.isSimple()) { 4137 MVT MTy = VT.getSimpleVT(); 4138 if (ST->useSLMArithCosts()) 4139 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 4140 return Entry->Cost; 4141 4142 if (ST->hasAVX()) 4143 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4144 return Entry->Cost; 4145 4146 if (ST->hasSSE2()) 4147 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4148 return Entry->Cost; 4149 } 4150 4151 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 4152 4153 MVT MTy = LT.second; 4154 4155 auto *ValVTy = cast<FixedVectorType>(ValTy); 4156 4157 // Special case: vXi8 mul reductions are performed as vXi16. 4158 if (ISD == ISD::MUL && MTy.getScalarType() == MVT::i8) { 4159 auto *WideSclTy = IntegerType::get(ValVTy->getContext(), 16); 4160 auto *WideVecTy = FixedVectorType::get(WideSclTy, ValVTy->getNumElements()); 4161 return getCastInstrCost(Instruction::ZExt, WideVecTy, ValTy, 4162 TargetTransformInfo::CastContextHint::None, 4163 CostKind) + 4164 getArithmeticReductionCost(Opcode, WideVecTy, FMF, CostKind); 4165 } 4166 4167 InstructionCost ArithmeticCost = 0; 4168 if (LT.first != 1 && MTy.isVector() && 4169 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4170 // Type needs to be split. We need LT.first - 1 arithmetic ops. 4171 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 4172 MTy.getVectorNumElements()); 4173 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 4174 ArithmeticCost *= LT.first - 1; 4175 } 4176 4177 if (ST->useSLMArithCosts()) 4178 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 4179 return ArithmeticCost + Entry->Cost; 4180 4181 if (ST->hasAVX()) 4182 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4183 return ArithmeticCost + Entry->Cost; 4184 4185 if (ST->hasSSE2()) 4186 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4187 return ArithmeticCost + Entry->Cost; 4188 4189 // FIXME: These assume a naive kshift+binop lowering, which is probably 4190 // conservative in most cases. 4191 static const CostTblEntry AVX512BoolReduction[] = { 4192 { ISD::AND, MVT::v2i1, 3 }, 4193 { ISD::AND, MVT::v4i1, 5 }, 4194 { ISD::AND, MVT::v8i1, 7 }, 4195 { ISD::AND, MVT::v16i1, 9 }, 4196 { ISD::AND, MVT::v32i1, 11 }, 4197 { ISD::AND, MVT::v64i1, 13 }, 4198 { ISD::OR, MVT::v2i1, 3 }, 4199 { ISD::OR, MVT::v4i1, 5 }, 4200 { ISD::OR, MVT::v8i1, 7 }, 4201 { ISD::OR, MVT::v16i1, 9 }, 4202 { ISD::OR, MVT::v32i1, 11 }, 4203 { ISD::OR, MVT::v64i1, 13 }, 4204 }; 4205 4206 static const CostTblEntry AVX2BoolReduction[] = { 4207 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 4208 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 4209 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 4210 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 4211 }; 4212 4213 static const CostTblEntry AVX1BoolReduction[] = { 4214 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 4215 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 4216 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 4217 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 4218 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 4219 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 4220 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 4221 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 4222 }; 4223 4224 static const CostTblEntry SSE2BoolReduction[] = { 4225 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 4226 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 4227 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 4228 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 4229 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 4230 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 4231 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 4232 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 4233 }; 4234 4235 // Handle bool allof/anyof patterns. 4236 if (ValVTy->getElementType()->isIntegerTy(1)) { 4237 InstructionCost ArithmeticCost = 0; 4238 if (LT.first != 1 && MTy.isVector() && 4239 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4240 // Type needs to be split. We need LT.first - 1 arithmetic ops. 4241 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 4242 MTy.getVectorNumElements()); 4243 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 4244 ArithmeticCost *= LT.first - 1; 4245 } 4246 4247 if (ST->hasAVX512()) 4248 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 4249 return ArithmeticCost + Entry->Cost; 4250 if (ST->hasAVX2()) 4251 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 4252 return ArithmeticCost + Entry->Cost; 4253 if (ST->hasAVX()) 4254 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 4255 return ArithmeticCost + Entry->Cost; 4256 if (ST->hasSSE2()) 4257 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 4258 return ArithmeticCost + Entry->Cost; 4259 4260 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, FMF, CostKind); 4261 } 4262 4263 unsigned NumVecElts = ValVTy->getNumElements(); 4264 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 4265 4266 // Special case power of 2 reductions where the scalar type isn't changed 4267 // by type legalization. 4268 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 4269 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, FMF, CostKind); 4270 4271 InstructionCost ReductionCost = 0; 4272 4273 auto *Ty = ValVTy; 4274 if (LT.first != 1 && MTy.isVector() && 4275 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4276 // Type needs to be split. We need LT.first - 1 arithmetic ops. 4277 Ty = FixedVectorType::get(ValVTy->getElementType(), 4278 MTy.getVectorNumElements()); 4279 ReductionCost = getArithmeticInstrCost(Opcode, Ty, CostKind); 4280 ReductionCost *= LT.first - 1; 4281 NumVecElts = MTy.getVectorNumElements(); 4282 } 4283 4284 // Now handle reduction with the legal type, taking into account size changes 4285 // at each level. 4286 while (NumVecElts > 1) { 4287 // Determine the size of the remaining vector we need to reduce. 4288 unsigned Size = NumVecElts * ScalarSize; 4289 NumVecElts /= 2; 4290 // If we're reducing from 256/512 bits, use an extract_subvector. 4291 if (Size > 128) { 4292 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 4293 ReductionCost += 4294 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 4295 Ty = SubTy; 4296 } else if (Size == 128) { 4297 // Reducing from 128 bits is a permute of v2f64/v2i64. 4298 FixedVectorType *ShufTy; 4299 if (ValVTy->isFloatingPointTy()) 4300 ShufTy = 4301 FixedVectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 4302 else 4303 ShufTy = 4304 FixedVectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 4305 ReductionCost += 4306 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4307 } else if (Size == 64) { 4308 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 4309 FixedVectorType *ShufTy; 4310 if (ValVTy->isFloatingPointTy()) 4311 ShufTy = 4312 FixedVectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 4313 else 4314 ShufTy = 4315 FixedVectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 4316 ReductionCost += 4317 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4318 } else { 4319 // Reducing from smaller size is a shift by immediate. 4320 auto *ShiftTy = FixedVectorType::get( 4321 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 4322 ReductionCost += getArithmeticInstrCost( 4323 Instruction::LShr, ShiftTy, CostKind, 4324 TargetTransformInfo::OK_AnyValue, 4325 TargetTransformInfo::OK_UniformConstantValue, 4326 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 4327 } 4328 4329 // Add the arithmetic op for this level. 4330 ReductionCost += getArithmeticInstrCost(Opcode, Ty, CostKind); 4331 } 4332 4333 // Add the final extract element to the cost. 4334 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 4335 } 4336 4337 InstructionCost X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, 4338 bool IsUnsigned) { 4339 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 4340 4341 MVT MTy = LT.second; 4342 4343 int ISD; 4344 if (Ty->isIntOrIntVectorTy()) { 4345 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 4346 } else { 4347 assert(Ty->isFPOrFPVectorTy() && 4348 "Expected float point or integer vector type."); 4349 ISD = ISD::FMINNUM; 4350 } 4351 4352 static const CostTblEntry SSE1CostTbl[] = { 4353 {ISD::FMINNUM, MVT::v4f32, 1}, 4354 }; 4355 4356 static const CostTblEntry SSE2CostTbl[] = { 4357 {ISD::FMINNUM, MVT::v2f64, 1}, 4358 {ISD::SMIN, MVT::v8i16, 1}, 4359 {ISD::UMIN, MVT::v16i8, 1}, 4360 }; 4361 4362 static const CostTblEntry SSE41CostTbl[] = { 4363 {ISD::SMIN, MVT::v4i32, 1}, 4364 {ISD::UMIN, MVT::v4i32, 1}, 4365 {ISD::UMIN, MVT::v8i16, 1}, 4366 {ISD::SMIN, MVT::v16i8, 1}, 4367 }; 4368 4369 static const CostTblEntry SSE42CostTbl[] = { 4370 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 4371 }; 4372 4373 static const CostTblEntry AVX1CostTbl[] = { 4374 {ISD::FMINNUM, MVT::v8f32, 1}, 4375 {ISD::FMINNUM, MVT::v4f64, 1}, 4376 {ISD::SMIN, MVT::v8i32, 3}, 4377 {ISD::UMIN, MVT::v8i32, 3}, 4378 {ISD::SMIN, MVT::v16i16, 3}, 4379 {ISD::UMIN, MVT::v16i16, 3}, 4380 {ISD::SMIN, MVT::v32i8, 3}, 4381 {ISD::UMIN, MVT::v32i8, 3}, 4382 }; 4383 4384 static const CostTblEntry AVX2CostTbl[] = { 4385 {ISD::SMIN, MVT::v8i32, 1}, 4386 {ISD::UMIN, MVT::v8i32, 1}, 4387 {ISD::SMIN, MVT::v16i16, 1}, 4388 {ISD::UMIN, MVT::v16i16, 1}, 4389 {ISD::SMIN, MVT::v32i8, 1}, 4390 {ISD::UMIN, MVT::v32i8, 1}, 4391 }; 4392 4393 static const CostTblEntry AVX512CostTbl[] = { 4394 {ISD::FMINNUM, MVT::v16f32, 1}, 4395 {ISD::FMINNUM, MVT::v8f64, 1}, 4396 {ISD::SMIN, MVT::v2i64, 1}, 4397 {ISD::UMIN, MVT::v2i64, 1}, 4398 {ISD::SMIN, MVT::v4i64, 1}, 4399 {ISD::UMIN, MVT::v4i64, 1}, 4400 {ISD::SMIN, MVT::v8i64, 1}, 4401 {ISD::UMIN, MVT::v8i64, 1}, 4402 {ISD::SMIN, MVT::v16i32, 1}, 4403 {ISD::UMIN, MVT::v16i32, 1}, 4404 }; 4405 4406 static const CostTblEntry AVX512BWCostTbl[] = { 4407 {ISD::SMIN, MVT::v32i16, 1}, 4408 {ISD::UMIN, MVT::v32i16, 1}, 4409 {ISD::SMIN, MVT::v64i8, 1}, 4410 {ISD::UMIN, MVT::v64i8, 1}, 4411 }; 4412 4413 // If we have a native MIN/MAX instruction for this type, use it. 4414 if (ST->hasBWI()) 4415 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 4416 return LT.first * Entry->Cost; 4417 4418 if (ST->hasAVX512()) 4419 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 4420 return LT.first * Entry->Cost; 4421 4422 if (ST->hasAVX2()) 4423 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 4424 return LT.first * Entry->Cost; 4425 4426 if (ST->hasAVX()) 4427 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 4428 return LT.first * Entry->Cost; 4429 4430 if (ST->hasSSE42()) 4431 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 4432 return LT.first * Entry->Cost; 4433 4434 if (ST->hasSSE41()) 4435 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 4436 return LT.first * Entry->Cost; 4437 4438 if (ST->hasSSE2()) 4439 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 4440 return LT.first * Entry->Cost; 4441 4442 if (ST->hasSSE1()) 4443 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 4444 return LT.first * Entry->Cost; 4445 4446 unsigned CmpOpcode; 4447 if (Ty->isFPOrFPVectorTy()) { 4448 CmpOpcode = Instruction::FCmp; 4449 } else { 4450 assert(Ty->isIntOrIntVectorTy() && 4451 "expecting floating point or integer type for min/max reduction"); 4452 CmpOpcode = Instruction::ICmp; 4453 } 4454 4455 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4456 // Otherwise fall back to cmp+select. 4457 InstructionCost Result = 4458 getCmpSelInstrCost(CmpOpcode, Ty, CondTy, CmpInst::BAD_ICMP_PREDICATE, 4459 CostKind) + 4460 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, 4461 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4462 return Result; 4463 } 4464 4465 InstructionCost 4466 X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 4467 bool IsUnsigned, 4468 TTI::TargetCostKind CostKind) { 4469 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 4470 4471 MVT MTy = LT.second; 4472 4473 int ISD; 4474 if (ValTy->isIntOrIntVectorTy()) { 4475 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 4476 } else { 4477 assert(ValTy->isFPOrFPVectorTy() && 4478 "Expected float point or integer vector type."); 4479 ISD = ISD::FMINNUM; 4480 } 4481 4482 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 4483 // and make it as the cost. 4484 4485 static const CostTblEntry SSE2CostTblNoPairWise[] = { 4486 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 4487 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 4488 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 4489 }; 4490 4491 static const CostTblEntry SSE41CostTblNoPairWise[] = { 4492 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 4493 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 4494 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 4495 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 4496 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 4497 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 4498 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 4499 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 4500 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 4501 {ISD::SMIN, MVT::v16i8, 6}, 4502 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 4503 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 4504 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 4505 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 4506 }; 4507 4508 static const CostTblEntry AVX1CostTblNoPairWise[] = { 4509 {ISD::SMIN, MVT::v16i16, 6}, 4510 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 4511 {ISD::SMIN, MVT::v32i8, 8}, 4512 {ISD::UMIN, MVT::v32i8, 8}, 4513 }; 4514 4515 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 4516 {ISD::SMIN, MVT::v32i16, 8}, 4517 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 4518 {ISD::SMIN, MVT::v64i8, 10}, 4519 {ISD::UMIN, MVT::v64i8, 10}, 4520 }; 4521 4522 // Before legalizing the type, give a chance to look up illegal narrow types 4523 // in the table. 4524 // FIXME: Is there a better way to do this? 4525 EVT VT = TLI->getValueType(DL, ValTy); 4526 if (VT.isSimple()) { 4527 MVT MTy = VT.getSimpleVT(); 4528 if (ST->hasBWI()) 4529 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4530 return Entry->Cost; 4531 4532 if (ST->hasAVX()) 4533 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4534 return Entry->Cost; 4535 4536 if (ST->hasSSE41()) 4537 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4538 return Entry->Cost; 4539 4540 if (ST->hasSSE2()) 4541 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4542 return Entry->Cost; 4543 } 4544 4545 auto *ValVTy = cast<FixedVectorType>(ValTy); 4546 unsigned NumVecElts = ValVTy->getNumElements(); 4547 4548 auto *Ty = ValVTy; 4549 InstructionCost MinMaxCost = 0; 4550 if (LT.first != 1 && MTy.isVector() && 4551 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4552 // Type needs to be split. We need LT.first - 1 operations ops. 4553 Ty = FixedVectorType::get(ValVTy->getElementType(), 4554 MTy.getVectorNumElements()); 4555 auto *SubCondTy = FixedVectorType::get(CondTy->getElementType(), 4556 MTy.getVectorNumElements()); 4557 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4558 MinMaxCost *= LT.first - 1; 4559 NumVecElts = MTy.getVectorNumElements(); 4560 } 4561 4562 if (ST->hasBWI()) 4563 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4564 return MinMaxCost + Entry->Cost; 4565 4566 if (ST->hasAVX()) 4567 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4568 return MinMaxCost + Entry->Cost; 4569 4570 if (ST->hasSSE41()) 4571 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4572 return MinMaxCost + Entry->Cost; 4573 4574 if (ST->hasSSE2()) 4575 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4576 return MinMaxCost + Entry->Cost; 4577 4578 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 4579 4580 // Special case power of 2 reductions where the scalar type isn't changed 4581 // by type legalization. 4582 if (!isPowerOf2_32(ValVTy->getNumElements()) || 4583 ScalarSize != MTy.getScalarSizeInBits()) 4584 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsUnsigned, CostKind); 4585 4586 // Now handle reduction with the legal type, taking into account size changes 4587 // at each level. 4588 while (NumVecElts > 1) { 4589 // Determine the size of the remaining vector we need to reduce. 4590 unsigned Size = NumVecElts * ScalarSize; 4591 NumVecElts /= 2; 4592 // If we're reducing from 256/512 bits, use an extract_subvector. 4593 if (Size > 128) { 4594 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 4595 MinMaxCost += 4596 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 4597 Ty = SubTy; 4598 } else if (Size == 128) { 4599 // Reducing from 128 bits is a permute of v2f64/v2i64. 4600 VectorType *ShufTy; 4601 if (ValTy->isFloatingPointTy()) 4602 ShufTy = 4603 FixedVectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 4604 else 4605 ShufTy = FixedVectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 4606 MinMaxCost += 4607 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4608 } else if (Size == 64) { 4609 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 4610 FixedVectorType *ShufTy; 4611 if (ValTy->isFloatingPointTy()) 4612 ShufTy = FixedVectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 4613 else 4614 ShufTy = FixedVectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 4615 MinMaxCost += 4616 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4617 } else { 4618 // Reducing from smaller size is a shift by immediate. 4619 auto *ShiftTy = FixedVectorType::get( 4620 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 4621 MinMaxCost += getArithmeticInstrCost( 4622 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, 4623 TargetTransformInfo::OK_AnyValue, 4624 TargetTransformInfo::OK_UniformConstantValue, 4625 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 4626 } 4627 4628 // Add the arithmetic op for this level. 4629 auto *SubCondTy = 4630 FixedVectorType::get(CondTy->getElementType(), Ty->getNumElements()); 4631 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4632 } 4633 4634 // Add the final extract element to the cost. 4635 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 4636 } 4637 4638 /// Calculate the cost of materializing a 64-bit value. This helper 4639 /// method might only calculate a fraction of a larger immediate. Therefore it 4640 /// is valid to return a cost of ZERO. 4641 InstructionCost X86TTIImpl::getIntImmCost(int64_t Val) { 4642 if (Val == 0) 4643 return TTI::TCC_Free; 4644 4645 if (isInt<32>(Val)) 4646 return TTI::TCC_Basic; 4647 4648 return 2 * TTI::TCC_Basic; 4649 } 4650 4651 InstructionCost X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 4652 TTI::TargetCostKind CostKind) { 4653 assert(Ty->isIntegerTy()); 4654 4655 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4656 if (BitSize == 0) 4657 return ~0U; 4658 4659 // Never hoist constants larger than 128bit, because this might lead to 4660 // incorrect code generation or assertions in codegen. 4661 // Fixme: Create a cost model for types larger than i128 once the codegen 4662 // issues have been fixed. 4663 if (BitSize > 128) 4664 return TTI::TCC_Free; 4665 4666 if (Imm == 0) 4667 return TTI::TCC_Free; 4668 4669 // Sign-extend all constants to a multiple of 64-bit. 4670 APInt ImmVal = Imm; 4671 if (BitSize % 64 != 0) 4672 ImmVal = Imm.sext(alignTo(BitSize, 64)); 4673 4674 // Split the constant into 64-bit chunks and calculate the cost for each 4675 // chunk. 4676 InstructionCost Cost = 0; 4677 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 4678 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 4679 int64_t Val = Tmp.getSExtValue(); 4680 Cost += getIntImmCost(Val); 4681 } 4682 // We need at least one instruction to materialize the constant. 4683 return std::max<InstructionCost>(1, Cost); 4684 } 4685 4686 InstructionCost X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, 4687 const APInt &Imm, Type *Ty, 4688 TTI::TargetCostKind CostKind, 4689 Instruction *Inst) { 4690 assert(Ty->isIntegerTy()); 4691 4692 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4693 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4694 // here, so that constant hoisting will ignore this constant. 4695 if (BitSize == 0) 4696 return TTI::TCC_Free; 4697 4698 unsigned ImmIdx = ~0U; 4699 switch (Opcode) { 4700 default: 4701 return TTI::TCC_Free; 4702 case Instruction::GetElementPtr: 4703 // Always hoist the base address of a GetElementPtr. This prevents the 4704 // creation of new constants for every base constant that gets constant 4705 // folded with the offset. 4706 if (Idx == 0) 4707 return 2 * TTI::TCC_Basic; 4708 return TTI::TCC_Free; 4709 case Instruction::Store: 4710 ImmIdx = 0; 4711 break; 4712 case Instruction::ICmp: 4713 // This is an imperfect hack to prevent constant hoisting of 4714 // compares that might be trying to check if a 64-bit value fits in 4715 // 32-bits. The backend can optimize these cases using a right shift by 32. 4716 // Ideally we would check the compare predicate here. There also other 4717 // similar immediates the backend can use shifts for. 4718 if (Idx == 1 && Imm.getBitWidth() == 64) { 4719 uint64_t ImmVal = Imm.getZExtValue(); 4720 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 4721 return TTI::TCC_Free; 4722 } 4723 ImmIdx = 1; 4724 break; 4725 case Instruction::And: 4726 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 4727 // by using a 32-bit operation with implicit zero extension. Detect such 4728 // immediates here as the normal path expects bit 31 to be sign extended. 4729 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 4730 return TTI::TCC_Free; 4731 ImmIdx = 1; 4732 break; 4733 case Instruction::Add: 4734 case Instruction::Sub: 4735 // For add/sub, we can use the opposite instruction for INT32_MIN. 4736 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 4737 return TTI::TCC_Free; 4738 ImmIdx = 1; 4739 break; 4740 case Instruction::UDiv: 4741 case Instruction::SDiv: 4742 case Instruction::URem: 4743 case Instruction::SRem: 4744 // Division by constant is typically expanded later into a different 4745 // instruction sequence. This completely changes the constants. 4746 // Report them as "free" to stop ConstantHoist from marking them as opaque. 4747 return TTI::TCC_Free; 4748 case Instruction::Mul: 4749 case Instruction::Or: 4750 case Instruction::Xor: 4751 ImmIdx = 1; 4752 break; 4753 // Always return TCC_Free for the shift value of a shift instruction. 4754 case Instruction::Shl: 4755 case Instruction::LShr: 4756 case Instruction::AShr: 4757 if (Idx == 1) 4758 return TTI::TCC_Free; 4759 break; 4760 case Instruction::Trunc: 4761 case Instruction::ZExt: 4762 case Instruction::SExt: 4763 case Instruction::IntToPtr: 4764 case Instruction::PtrToInt: 4765 case Instruction::BitCast: 4766 case Instruction::PHI: 4767 case Instruction::Call: 4768 case Instruction::Select: 4769 case Instruction::Ret: 4770 case Instruction::Load: 4771 break; 4772 } 4773 4774 if (Idx == ImmIdx) { 4775 int NumConstants = divideCeil(BitSize, 64); 4776 InstructionCost Cost = X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4777 return (Cost <= NumConstants * TTI::TCC_Basic) 4778 ? static_cast<int>(TTI::TCC_Free) 4779 : Cost; 4780 } 4781 4782 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4783 } 4784 4785 InstructionCost X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 4786 const APInt &Imm, Type *Ty, 4787 TTI::TargetCostKind CostKind) { 4788 assert(Ty->isIntegerTy()); 4789 4790 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4791 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4792 // here, so that constant hoisting will ignore this constant. 4793 if (BitSize == 0) 4794 return TTI::TCC_Free; 4795 4796 switch (IID) { 4797 default: 4798 return TTI::TCC_Free; 4799 case Intrinsic::sadd_with_overflow: 4800 case Intrinsic::uadd_with_overflow: 4801 case Intrinsic::ssub_with_overflow: 4802 case Intrinsic::usub_with_overflow: 4803 case Intrinsic::smul_with_overflow: 4804 case Intrinsic::umul_with_overflow: 4805 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 4806 return TTI::TCC_Free; 4807 break; 4808 case Intrinsic::experimental_stackmap: 4809 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4810 return TTI::TCC_Free; 4811 break; 4812 case Intrinsic::experimental_patchpoint_void: 4813 case Intrinsic::experimental_patchpoint_i64: 4814 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4815 return TTI::TCC_Free; 4816 break; 4817 } 4818 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4819 } 4820 4821 InstructionCost X86TTIImpl::getCFInstrCost(unsigned Opcode, 4822 TTI::TargetCostKind CostKind, 4823 const Instruction *I) { 4824 if (CostKind != TTI::TCK_RecipThroughput) 4825 return Opcode == Instruction::PHI ? 0 : 1; 4826 // Branches are assumed to be predicted. 4827 return 0; 4828 } 4829 4830 int X86TTIImpl::getGatherOverhead() const { 4831 // Some CPUs have more overhead for gather. The specified overhead is relative 4832 // to the Load operation. "2" is the number provided by Intel architects. This 4833 // parameter is used for cost estimation of Gather Op and comparison with 4834 // other alternatives. 4835 // TODO: Remove the explicit hasAVX512()?, That would mean we would only 4836 // enable gather with a -march. 4837 if (ST->hasAVX512() || (ST->hasAVX2() && ST->hasFastGather())) 4838 return 2; 4839 4840 return 1024; 4841 } 4842 4843 int X86TTIImpl::getScatterOverhead() const { 4844 if (ST->hasAVX512()) 4845 return 2; 4846 4847 return 1024; 4848 } 4849 4850 // Return an average cost of Gather / Scatter instruction, maybe improved later. 4851 // FIXME: Add TargetCostKind support. 4852 InstructionCost X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, 4853 const Value *Ptr, Align Alignment, 4854 unsigned AddressSpace) { 4855 4856 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 4857 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4858 4859 // Try to reduce index size from 64 bit (default for GEP) 4860 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 4861 // operation will use 16 x 64 indices which do not fit in a zmm and needs 4862 // to split. Also check that the base pointer is the same for all lanes, 4863 // and that there's at most one variable index. 4864 auto getIndexSizeInBits = [](const Value *Ptr, const DataLayout &DL) { 4865 unsigned IndexSize = DL.getPointerSizeInBits(); 4866 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 4867 if (IndexSize < 64 || !GEP) 4868 return IndexSize; 4869 4870 unsigned NumOfVarIndices = 0; 4871 const Value *Ptrs = GEP->getPointerOperand(); 4872 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 4873 return IndexSize; 4874 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 4875 if (isa<Constant>(GEP->getOperand(i))) 4876 continue; 4877 Type *IndxTy = GEP->getOperand(i)->getType(); 4878 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 4879 IndxTy = IndexVTy->getElementType(); 4880 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 4881 !isa<SExtInst>(GEP->getOperand(i))) || 4882 ++NumOfVarIndices > 1) 4883 return IndexSize; // 64 4884 } 4885 return (unsigned)32; 4886 }; 4887 4888 // Trying to reduce IndexSize to 32 bits for vector 16. 4889 // By default the IndexSize is equal to pointer size. 4890 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 4891 ? getIndexSizeInBits(Ptr, DL) 4892 : DL.getPointerSizeInBits(); 4893 4894 auto *IndexVTy = FixedVectorType::get( 4895 IntegerType::get(SrcVTy->getContext(), IndexSize), VF); 4896 std::pair<InstructionCost, MVT> IdxsLT = 4897 TLI->getTypeLegalizationCost(DL, IndexVTy); 4898 std::pair<InstructionCost, MVT> SrcLT = 4899 TLI->getTypeLegalizationCost(DL, SrcVTy); 4900 InstructionCost::CostType SplitFactor = 4901 *std::max(IdxsLT.first, SrcLT.first).getValue(); 4902 if (SplitFactor > 1) { 4903 // Handle splitting of vector of pointers 4904 auto *SplitSrcTy = 4905 FixedVectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 4906 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 4907 AddressSpace); 4908 } 4909 4910 // The gather / scatter cost is given by Intel architects. It is a rough 4911 // number since we are looking at one instruction in a time. 4912 const int GSOverhead = (Opcode == Instruction::Load) 4913 ? getGatherOverhead() 4914 : getScatterOverhead(); 4915 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4916 MaybeAlign(Alignment), AddressSpace, 4917 TTI::TCK_RecipThroughput); 4918 } 4919 4920 /// Return the cost of full scalarization of gather / scatter operation. 4921 /// 4922 /// Opcode - Load or Store instruction. 4923 /// SrcVTy - The type of the data vector that should be gathered or scattered. 4924 /// VariableMask - The mask is non-constant at compile time. 4925 /// Alignment - Alignment for one element. 4926 /// AddressSpace - pointer[s] address space. 4927 /// 4928 /// FIXME: Add TargetCostKind support. 4929 InstructionCost X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 4930 bool VariableMask, Align Alignment, 4931 unsigned AddressSpace) { 4932 Type *ScalarTy = SrcVTy->getScalarType(); 4933 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4934 APInt DemandedElts = APInt::getAllOnes(VF); 4935 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4936 4937 InstructionCost MaskUnpackCost = 0; 4938 if (VariableMask) { 4939 auto *MaskTy = 4940 FixedVectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 4941 MaskUnpackCost = getScalarizationOverhead( 4942 MaskTy, DemandedElts, /*Insert=*/false, /*Extract=*/true); 4943 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 4944 Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), nullptr, 4945 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4946 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 4947 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 4948 } 4949 4950 InstructionCost AddressUnpackCost = getScalarizationOverhead( 4951 FixedVectorType::get(ScalarTy->getPointerTo(), VF), DemandedElts, 4952 /*Insert=*/false, /*Extract=*/true); 4953 4954 // The cost of the scalar loads/stores. 4955 InstructionCost MemoryOpCost = 4956 VF * getMemoryOpCost(Opcode, ScalarTy, MaybeAlign(Alignment), 4957 AddressSpace, CostKind); 4958 4959 // The cost of forming the vector from loaded scalars/ 4960 // scalarizing the vector to perform scalar stores. 4961 InstructionCost InsertExtractCost = 4962 getScalarizationOverhead(cast<FixedVectorType>(SrcVTy), DemandedElts, 4963 /*Insert=*/Opcode == Instruction::Load, 4964 /*Extract=*/Opcode == Instruction::Store); 4965 4966 return AddressUnpackCost + MemoryOpCost + MaskUnpackCost + InsertExtractCost; 4967 } 4968 4969 /// Calculate the cost of Gather / Scatter operation 4970 InstructionCost X86TTIImpl::getGatherScatterOpCost( 4971 unsigned Opcode, Type *SrcVTy, const Value *Ptr, bool VariableMask, 4972 Align Alignment, TTI::TargetCostKind CostKind, 4973 const Instruction *I = nullptr) { 4974 if (CostKind != TTI::TCK_RecipThroughput) { 4975 if ((Opcode == Instruction::Load && 4976 isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4977 (Opcode == Instruction::Store && 4978 isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4979 return 1; 4980 return BaseT::getGatherScatterOpCost(Opcode, SrcVTy, Ptr, VariableMask, 4981 Alignment, CostKind, I); 4982 } 4983 4984 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 4985 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 4986 if (!PtrTy && Ptr->getType()->isVectorTy()) 4987 PtrTy = dyn_cast<PointerType>( 4988 cast<VectorType>(Ptr->getType())->getElementType()); 4989 assert(PtrTy && "Unexpected type for Ptr argument"); 4990 unsigned AddressSpace = PtrTy->getAddressSpace(); 4991 4992 if ((Opcode == Instruction::Load && 4993 !isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4994 (Opcode == Instruction::Store && 4995 !isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4996 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 4997 AddressSpace); 4998 4999 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 5000 } 5001 5002 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 5003 TargetTransformInfo::LSRCost &C2) { 5004 // X86 specific here are "instruction number 1st priority". 5005 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 5006 C1.NumIVMuls, C1.NumBaseAdds, 5007 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 5008 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 5009 C2.NumIVMuls, C2.NumBaseAdds, 5010 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 5011 } 5012 5013 bool X86TTIImpl::canMacroFuseCmp() { 5014 return ST->hasMacroFusion() || ST->hasBranchFusion(); 5015 } 5016 5017 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, Align Alignment) { 5018 if (!ST->hasAVX()) 5019 return false; 5020 5021 // The backend can't handle a single element vector. 5022 if (isa<VectorType>(DataTy) && 5023 cast<FixedVectorType>(DataTy)->getNumElements() == 1) 5024 return false; 5025 Type *ScalarTy = DataTy->getScalarType(); 5026 5027 if (ScalarTy->isPointerTy()) 5028 return true; 5029 5030 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 5031 return true; 5032 5033 if (ScalarTy->isHalfTy() && ST->hasBWI() && ST->hasFP16()) 5034 return true; 5035 5036 if (!ScalarTy->isIntegerTy()) 5037 return false; 5038 5039 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 5040 return IntWidth == 32 || IntWidth == 64 || 5041 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 5042 } 5043 5044 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, Align Alignment) { 5045 return isLegalMaskedLoad(DataType, Alignment); 5046 } 5047 5048 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 5049 unsigned DataSize = DL.getTypeStoreSize(DataType); 5050 // The only supported nontemporal loads are for aligned vectors of 16 or 32 5051 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 5052 // (the equivalent stores only require AVX). 5053 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 5054 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 5055 5056 return false; 5057 } 5058 5059 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 5060 unsigned DataSize = DL.getTypeStoreSize(DataType); 5061 5062 // SSE4A supports nontemporal stores of float and double at arbitrary 5063 // alignment. 5064 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 5065 return true; 5066 5067 // Besides the SSE4A subtarget exception above, only aligned stores are 5068 // available nontemporaly on any other subtarget. And only stores with a size 5069 // of 4..32 bytes (powers of 2, only) are permitted. 5070 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 5071 !isPowerOf2_32(DataSize)) 5072 return false; 5073 5074 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 5075 // loads require AVX2). 5076 if (DataSize == 32) 5077 return ST->hasAVX(); 5078 if (DataSize == 16) 5079 return ST->hasSSE1(); 5080 return true; 5081 } 5082 5083 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 5084 if (!isa<VectorType>(DataTy)) 5085 return false; 5086 5087 if (!ST->hasAVX512()) 5088 return false; 5089 5090 // The backend can't handle a single element vector. 5091 if (cast<FixedVectorType>(DataTy)->getNumElements() == 1) 5092 return false; 5093 5094 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 5095 5096 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 5097 return true; 5098 5099 if (!ScalarTy->isIntegerTy()) 5100 return false; 5101 5102 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 5103 return IntWidth == 32 || IntWidth == 64 || 5104 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 5105 } 5106 5107 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 5108 return isLegalMaskedExpandLoad(DataTy); 5109 } 5110 5111 bool X86TTIImpl::supportsGather() const { 5112 // Some CPUs have better gather performance than others. 5113 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 5114 // enable gather with a -march. 5115 return ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()); 5116 } 5117 5118 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, Align Alignment) { 5119 if (!supportsGather()) 5120 return false; 5121 5122 // This function is called now in two cases: from the Loop Vectorizer 5123 // and from the Scalarizer. 5124 // When the Loop Vectorizer asks about legality of the feature, 5125 // the vectorization factor is not calculated yet. The Loop Vectorizer 5126 // sends a scalar type and the decision is based on the width of the 5127 // scalar element. 5128 // Later on, the cost model will estimate usage this intrinsic based on 5129 // the vector type. 5130 // The Scalarizer asks again about legality. It sends a vector type. 5131 // In this case we can reject non-power-of-2 vectors. 5132 // We also reject single element vectors as the type legalizer can't 5133 // scalarize it. 5134 if (auto *DataVTy = dyn_cast<FixedVectorType>(DataTy)) { 5135 unsigned NumElts = DataVTy->getNumElements(); 5136 if (NumElts == 1) 5137 return false; 5138 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 5139 // Vector-4 of gather/scatter instruction does not exist on KNL. 5140 // We can extend it to 8 elements, but zeroing upper bits of 5141 // the mask vector will add more instructions. Right now we give the scalar 5142 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter 5143 // instruction is better in the VariableMask case. 5144 if (ST->hasAVX512() && (NumElts == 2 || (NumElts == 4 && !ST->hasVLX()))) 5145 return false; 5146 } 5147 Type *ScalarTy = DataTy->getScalarType(); 5148 if (ScalarTy->isPointerTy()) 5149 return true; 5150 5151 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 5152 return true; 5153 5154 if (!ScalarTy->isIntegerTy()) 5155 return false; 5156 5157 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 5158 return IntWidth == 32 || IntWidth == 64; 5159 } 5160 5161 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, Align Alignment) { 5162 // AVX2 doesn't support scatter 5163 if (!ST->hasAVX512()) 5164 return false; 5165 return isLegalMaskedGather(DataType, Alignment); 5166 } 5167 5168 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 5169 EVT VT = TLI->getValueType(DL, DataType); 5170 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 5171 } 5172 5173 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 5174 return false; 5175 } 5176 5177 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 5178 const Function *Callee) const { 5179 const TargetMachine &TM = getTLI()->getTargetMachine(); 5180 5181 // Work this as a subsetting of subtarget features. 5182 const FeatureBitset &CallerBits = 5183 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 5184 const FeatureBitset &CalleeBits = 5185 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 5186 5187 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 5188 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 5189 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 5190 } 5191 5192 bool X86TTIImpl::areFunctionArgsABICompatible( 5193 const Function *Caller, const Function *Callee, 5194 SmallPtrSetImpl<Argument *> &Args) const { 5195 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args)) 5196 return false; 5197 5198 // If we get here, we know the target features match. If one function 5199 // considers 512-bit vectors legal and the other does not, consider them 5200 // incompatible. 5201 const TargetMachine &TM = getTLI()->getTargetMachine(); 5202 5203 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 5204 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs()) 5205 return true; 5206 5207 // Consider the arguments compatible if they aren't vectors or aggregates. 5208 // FIXME: Look at the size of vectors. 5209 // FIXME: Look at the element types of aggregates to see if there are vectors. 5210 // FIXME: The API of this function seems intended to allow arguments 5211 // to be removed from the set, but the caller doesn't check if the set 5212 // becomes empty so that may not work in practice. 5213 return llvm::none_of(Args, [](Argument *A) { 5214 auto *EltTy = cast<PointerType>(A->getType())->getElementType(); 5215 return EltTy->isVectorTy() || EltTy->isAggregateType(); 5216 }); 5217 } 5218 5219 X86TTIImpl::TTI::MemCmpExpansionOptions 5220 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 5221 TTI::MemCmpExpansionOptions Options; 5222 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 5223 Options.NumLoadsPerBlock = 2; 5224 // All GPR and vector loads can be unaligned. 5225 Options.AllowOverlappingLoads = true; 5226 if (IsZeroCmp) { 5227 // Only enable vector loads for equality comparison. Right now the vector 5228 // version is not as fast for three way compare (see #33329). 5229 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 5230 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 5231 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 5232 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 5233 } 5234 if (ST->is64Bit()) { 5235 Options.LoadSizes.push_back(8); 5236 } 5237 Options.LoadSizes.push_back(4); 5238 Options.LoadSizes.push_back(2); 5239 Options.LoadSizes.push_back(1); 5240 return Options; 5241 } 5242 5243 bool X86TTIImpl::prefersVectorizedAddressing() const { 5244 return supportsGather(); 5245 } 5246 5247 bool X86TTIImpl::supportsEfficientVectorElementLoadStore() const { 5248 return false; 5249 } 5250 5251 bool X86TTIImpl::enableInterleavedAccessVectorization() { 5252 // TODO: We expect this to be beneficial regardless of arch, 5253 // but there are currently some unexplained performance artifacts on Atom. 5254 // As a temporary solution, disable on Atom. 5255 return !(ST->isAtom()); 5256 } 5257 5258 // Get estimation for interleaved load/store operations and strided load. 5259 // \p Indices contains indices for strided load. 5260 // \p Factor - the factor of interleaving. 5261 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 5262 InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX512( 5263 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 5264 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 5265 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 5266 // VecTy for interleave memop is <VF*Factor x Elt>. 5267 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 5268 // VecTy = <12 x i32>. 5269 5270 // Calculate the number of memory operations (NumOfMemOps), required 5271 // for load/store the VecTy. 5272 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 5273 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 5274 unsigned LegalVTSize = LegalVT.getStoreSize(); 5275 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 5276 5277 // Get the cost of one memory operation. 5278 auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(), 5279 LegalVT.getVectorNumElements()); 5280 InstructionCost MemOpCost; 5281 bool UseMaskedMemOp = UseMaskForCond || UseMaskForGaps; 5282 if (UseMaskedMemOp) 5283 MemOpCost = getMaskedMemoryOpCost(Opcode, SingleMemOpTy, Alignment, 5284 AddressSpace, CostKind); 5285 else 5286 MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, MaybeAlign(Alignment), 5287 AddressSpace, CostKind); 5288 5289 unsigned VF = VecTy->getNumElements() / Factor; 5290 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 5291 5292 InstructionCost MaskCost; 5293 if (UseMaskedMemOp) { 5294 APInt DemandedLoadStoreElts = APInt::getZero(VecTy->getNumElements()); 5295 for (unsigned Index : Indices) { 5296 assert(Index < Factor && "Invalid index for interleaved memory op"); 5297 for (unsigned Elm = 0; Elm < VF; Elm++) 5298 DemandedLoadStoreElts.setBit(Index + Elm * Factor); 5299 } 5300 5301 Type *I1Type = Type::getInt1Ty(VecTy->getContext()); 5302 5303 MaskCost = getReplicationShuffleCost( 5304 I1Type, Factor, VF, 5305 UseMaskForGaps ? DemandedLoadStoreElts 5306 : APInt::getAllOnes(VecTy->getNumElements()), 5307 CostKind); 5308 5309 // The Gaps mask is invariant and created outside the loop, therefore the 5310 // cost of creating it is not accounted for here. However if we have both 5311 // a MaskForGaps and some other mask that guards the execution of the 5312 // memory access, we need to account for the cost of And-ing the two masks 5313 // inside the loop. 5314 if (UseMaskForGaps) { 5315 auto *MaskVT = FixedVectorType::get(I1Type, VecTy->getNumElements()); 5316 MaskCost += getArithmeticInstrCost(BinaryOperator::And, MaskVT, CostKind); 5317 } 5318 } 5319 5320 if (Opcode == Instruction::Load) { 5321 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 5322 // contain the cost of the optimized shuffle sequence that the 5323 // X86InterleavedAccess pass will generate. 5324 // The cost of loads and stores are computed separately from the table. 5325 5326 // X86InterleavedAccess support only the following interleaved-access group. 5327 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 5328 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 5329 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 5330 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 5331 }; 5332 5333 if (const auto *Entry = 5334 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 5335 return MaskCost + NumOfMemOps * MemOpCost + Entry->Cost; 5336 //If an entry does not exist, fallback to the default implementation. 5337 5338 // Kind of shuffle depends on number of loaded values. 5339 // If we load the entire data in one register, we can use a 1-src shuffle. 5340 // Otherwise, we'll merge 2 sources in each operation. 5341 TTI::ShuffleKind ShuffleKind = 5342 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 5343 5344 InstructionCost ShuffleCost = 5345 getShuffleCost(ShuffleKind, SingleMemOpTy, None, 0, nullptr); 5346 5347 unsigned NumOfLoadsInInterleaveGrp = 5348 Indices.size() ? Indices.size() : Factor; 5349 auto *ResultTy = FixedVectorType::get(VecTy->getElementType(), 5350 VecTy->getNumElements() / Factor); 5351 InstructionCost NumOfResults = 5352 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 5353 NumOfLoadsInInterleaveGrp; 5354 5355 // About a half of the loads may be folded in shuffles when we have only 5356 // one result. If we have more than one result, or the loads are masked, 5357 // we do not fold loads at all. 5358 unsigned NumOfUnfoldedLoads = 5359 UseMaskedMemOp || NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 5360 5361 // Get a number of shuffle operations per result. 5362 unsigned NumOfShufflesPerResult = 5363 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 5364 5365 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 5366 // When we have more than one destination, we need additional instructions 5367 // to keep sources. 5368 InstructionCost NumOfMoves = 0; 5369 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 5370 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 5371 5372 InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 5373 MaskCost + NumOfUnfoldedLoads * MemOpCost + 5374 NumOfMoves; 5375 5376 return Cost; 5377 } 5378 5379 // Store. 5380 assert(Opcode == Instruction::Store && 5381 "Expected Store Instruction at this point"); 5382 // X86InterleavedAccess support only the following interleaved-access group. 5383 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 5384 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 5385 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 5386 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 5387 5388 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 5389 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 5390 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 5391 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 5392 }; 5393 5394 if (const auto *Entry = 5395 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 5396 return MaskCost + NumOfMemOps * MemOpCost + Entry->Cost; 5397 //If an entry does not exist, fallback to the default implementation. 5398 5399 // There is no strided stores meanwhile. And store can't be folded in 5400 // shuffle. 5401 unsigned NumOfSources = Factor; // The number of values to be merged. 5402 InstructionCost ShuffleCost = 5403 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, None, 0, nullptr); 5404 unsigned NumOfShufflesPerStore = NumOfSources - 1; 5405 5406 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 5407 // We need additional instructions to keep sources. 5408 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 5409 InstructionCost Cost = 5410 MaskCost + 5411 NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 5412 NumOfMoves; 5413 return Cost; 5414 } 5415 5416 InstructionCost X86TTIImpl::getInterleavedMemoryOpCost( 5417 unsigned Opcode, Type *BaseTy, unsigned Factor, ArrayRef<unsigned> Indices, 5418 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, 5419 bool UseMaskForCond, bool UseMaskForGaps) { 5420 auto *VecTy = cast<FixedVectorType>(BaseTy); 5421 5422 auto isSupportedOnAVX512 = [&](Type *VecTy, bool HasBW) { 5423 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 5424 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 5425 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 5426 return true; 5427 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8) || 5428 (!ST->useSoftFloat() && ST->hasFP16() && EltTy->isHalfTy())) 5429 return HasBW; 5430 return false; 5431 }; 5432 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 5433 return getInterleavedMemoryOpCostAVX512( 5434 Opcode, VecTy, Factor, Indices, Alignment, 5435 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 5436 5437 if (UseMaskForCond || UseMaskForGaps) 5438 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5439 Alignment, AddressSpace, CostKind, 5440 UseMaskForCond, UseMaskForGaps); 5441 5442 // Get estimation for interleaved load/store operations for SSE-AVX2. 5443 // As opposed to AVX-512, SSE-AVX2 do not have generic shuffles that allow 5444 // computing the cost using a generic formula as a function of generic 5445 // shuffles. We therefore use a lookup table instead, filled according to 5446 // the instruction sequences that codegen currently generates. 5447 5448 // VecTy for interleave memop is <VF*Factor x Elt>. 5449 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 5450 // VecTy = <12 x i32>. 5451 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 5452 5453 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 5454 // the VF=2, while v2i128 is an unsupported MVT vector type 5455 // (see MachineValueType.h::getVectorVT()). 5456 if (!LegalVT.isVector()) 5457 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5458 Alignment, AddressSpace, CostKind); 5459 5460 unsigned VF = VecTy->getNumElements() / Factor; 5461 Type *ScalarTy = VecTy->getElementType(); 5462 // Deduplicate entries, model floats/pointers as appropriately-sized integers. 5463 if (!ScalarTy->isIntegerTy()) 5464 ScalarTy = 5465 Type::getIntNTy(ScalarTy->getContext(), DL.getTypeSizeInBits(ScalarTy)); 5466 5467 // Get the cost of all the memory operations. 5468 // FIXME: discount dead loads. 5469 InstructionCost MemOpCosts = getMemoryOpCost( 5470 Opcode, VecTy, MaybeAlign(Alignment), AddressSpace, CostKind); 5471 5472 auto *VT = FixedVectorType::get(ScalarTy, VF); 5473 EVT ETy = TLI->getValueType(DL, VT); 5474 if (!ETy.isSimple()) 5475 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5476 Alignment, AddressSpace, CostKind); 5477 5478 // TODO: Complete for other data-types and strides. 5479 // Each combination of Stride, element bit width and VF results in a different 5480 // sequence; The cost tables are therefore accessed with: 5481 // Factor (stride) and VectorType=VFxiN. 5482 // The Cost accounts only for the shuffle sequence; 5483 // The cost of the loads/stores is accounted for separately. 5484 // 5485 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 5486 {2, MVT::v2i8, 2}, // (load 4i8 and) deinterleave into 2 x 2i8 5487 {2, MVT::v4i8, 2}, // (load 8i8 and) deinterleave into 2 x 4i8 5488 {2, MVT::v8i8, 2}, // (load 16i8 and) deinterleave into 2 x 8i8 5489 {2, MVT::v16i8, 4}, // (load 32i8 and) deinterleave into 2 x 16i8 5490 {2, MVT::v32i8, 6}, // (load 64i8 and) deinterleave into 2 x 32i8 5491 5492 {2, MVT::v8i16, 6}, // (load 16i16 and) deinterleave into 2 x 8i16 5493 {2, MVT::v16i16, 9}, // (load 32i16 and) deinterleave into 2 x 16i16 5494 {2, MVT::v32i16, 18}, // (load 64i16 and) deinterleave into 2 x 32i16 5495 5496 {2, MVT::v8i32, 4}, // (load 16i32 and) deinterleave into 2 x 8i32 5497 {2, MVT::v16i32, 8}, // (load 32i32 and) deinterleave into 2 x 16i32 5498 {2, MVT::v32i32, 16}, // (load 64i32 and) deinterleave into 2 x 32i32 5499 5500 {2, MVT::v4i64, 4}, // (load 8i64 and) deinterleave into 2 x 4i64 5501 {2, MVT::v8i64, 8}, // (load 16i64 and) deinterleave into 2 x 8i64 5502 {2, MVT::v16i64, 16}, // (load 32i64 and) deinterleave into 2 x 16i64 5503 {2, MVT::v32i64, 32}, // (load 64i64 and) deinterleave into 2 x 32i64 5504 5505 {3, MVT::v2i8, 3}, // (load 6i8 and) deinterleave into 3 x 2i8 5506 {3, MVT::v4i8, 3}, // (load 12i8 and) deinterleave into 3 x 4i8 5507 {3, MVT::v8i8, 6}, // (load 24i8 and) deinterleave into 3 x 8i8 5508 {3, MVT::v16i8, 11}, // (load 48i8 and) deinterleave into 3 x 16i8 5509 {3, MVT::v32i8, 14}, // (load 96i8 and) deinterleave into 3 x 32i8 5510 5511 {3, MVT::v2i16, 5}, // (load 6i16 and) deinterleave into 3 x 2i16 5512 {3, MVT::v4i16, 7}, // (load 12i16 and) deinterleave into 3 x 4i16 5513 {3, MVT::v8i16, 9}, // (load 24i16 and) deinterleave into 3 x 8i16 5514 {3, MVT::v16i16, 28}, // (load 48i16 and) deinterleave into 3 x 16i16 5515 {3, MVT::v32i16, 56}, // (load 96i16 and) deinterleave into 3 x 32i16 5516 5517 {3, MVT::v2i32, 3}, // (load 6i32 and) deinterleave into 3 x 2i32 5518 {3, MVT::v4i32, 3}, // (load 12i32 and) deinterleave into 3 x 4i32 5519 {3, MVT::v8i32, 7}, // (load 24i32 and) deinterleave into 3 x 8i32 5520 {3, MVT::v16i32, 14}, // (load 48i32 and) deinterleave into 3 x 16i32 5521 {3, MVT::v32i32, 32}, // (load 96i32 and) deinterleave into 3 x 32i32 5522 5523 {3, MVT::v2i64, 1}, // (load 6i64 and) deinterleave into 3 x 2i64 5524 {3, MVT::v4i64, 5}, // (load 12i64 and) deinterleave into 3 x 4i64 5525 {3, MVT::v8i64, 10}, // (load 24i64 and) deinterleave into 3 x 8i64 5526 {3, MVT::v16i64, 20}, // (load 48i64 and) deinterleave into 3 x 16i64 5527 5528 {4, MVT::v2i8, 4}, // (load 8i8 and) deinterleave into 4 x 2i8 5529 {4, MVT::v4i8, 4}, // (load 16i8 and) deinterleave into 4 x 4i8 5530 {4, MVT::v8i8, 12}, // (load 32i8 and) deinterleave into 4 x 8i8 5531 {4, MVT::v16i8, 24}, // (load 64i8 and) deinterleave into 4 x 16i8 5532 {4, MVT::v32i8, 56}, // (load 128i8 and) deinterleave into 4 x 32i8 5533 5534 {4, MVT::v2i16, 6}, // (load 8i16 and) deinterleave into 4 x 2i16 5535 {4, MVT::v4i16, 17}, // (load 16i16 and) deinterleave into 4 x 4i16 5536 {4, MVT::v8i16, 33}, // (load 32i16 and) deinterleave into 4 x 8i16 5537 {4, MVT::v16i16, 75}, // (load 64i16 and) deinterleave into 4 x 16i16 5538 {4, MVT::v32i16, 150}, // (load 128i16 and) deinterleave into 4 x 32i16 5539 5540 {4, MVT::v2i32, 4}, // (load 8i32 and) deinterleave into 4 x 2i32 5541 {4, MVT::v4i32, 8}, // (load 16i32 and) deinterleave into 4 x 4i32 5542 {4, MVT::v8i32, 16}, // (load 32i32 and) deinterleave into 4 x 8i32 5543 {4, MVT::v16i32, 32}, // (load 64i32 and) deinterleave into 4 x 16i32 5544 {4, MVT::v32i32, 68}, // (load 128i32 and) deinterleave into 4 x 32i32 5545 5546 {4, MVT::v2i64, 6}, // (load 8i64 and) deinterleave into 4 x 2i64 5547 {4, MVT::v4i64, 8}, // (load 16i64 and) deinterleave into 4 x 4i64 5548 {4, MVT::v8i64, 20}, // (load 32i64 and) deinterleave into 4 x 8i64 5549 {4, MVT::v16i64, 40}, // (load 64i64 and) deinterleave into 4 x 16i64 5550 5551 {6, MVT::v2i8, 6}, // (load 12i8 and) deinterleave into 6 x 2i8 5552 {6, MVT::v4i8, 14}, // (load 24i8 and) deinterleave into 6 x 4i8 5553 {6, MVT::v8i8, 18}, // (load 48i8 and) deinterleave into 6 x 8i8 5554 {6, MVT::v16i8, 43}, // (load 96i8 and) deinterleave into 6 x 16i8 5555 {6, MVT::v32i8, 82}, // (load 192i8 and) deinterleave into 6 x 32i8 5556 5557 {6, MVT::v2i16, 13}, // (load 12i16 and) deinterleave into 6 x 2i16 5558 {6, MVT::v4i16, 9}, // (load 24i16 and) deinterleave into 6 x 4i16 5559 {6, MVT::v8i16, 39}, // (load 48i16 and) deinterleave into 6 x 8i16 5560 {6, MVT::v16i16, 106}, // (load 96i16 and) deinterleave into 6 x 16i16 5561 {6, MVT::v32i16, 212}, // (load 192i16 and) deinterleave into 6 x 32i16 5562 5563 {6, MVT::v2i32, 6}, // (load 12i32 and) deinterleave into 6 x 2i32 5564 {6, MVT::v4i32, 15}, // (load 24i32 and) deinterleave into 6 x 4i32 5565 {6, MVT::v8i32, 31}, // (load 48i32 and) deinterleave into 6 x 8i32 5566 {6, MVT::v16i32, 64}, // (load 96i32 and) deinterleave into 6 x 16i32 5567 5568 {6, MVT::v2i64, 6}, // (load 12i64 and) deinterleave into 6 x 2i64 5569 {6, MVT::v4i64, 18}, // (load 24i64 and) deinterleave into 6 x 4i64 5570 {6, MVT::v8i64, 36}, // (load 48i64 and) deinterleave into 6 x 8i64 5571 5572 {8, MVT::v8i32, 40} // (load 64i32 and) deinterleave into 8 x 8i32 5573 }; 5574 5575 static const CostTblEntry SSSE3InterleavedLoadTbl[] = { 5576 {2, MVT::v4i16, 2}, // (load 8i16 and) deinterleave into 2 x 4i16 5577 }; 5578 5579 static const CostTblEntry SSE2InterleavedLoadTbl[] = { 5580 {2, MVT::v2i16, 2}, // (load 4i16 and) deinterleave into 2 x 2i16 5581 {2, MVT::v4i16, 7}, // (load 8i16 and) deinterleave into 2 x 4i16 5582 5583 {2, MVT::v2i32, 2}, // (load 4i32 and) deinterleave into 2 x 2i32 5584 {2, MVT::v4i32, 2}, // (load 8i32 and) deinterleave into 2 x 4i32 5585 5586 {2, MVT::v2i64, 2}, // (load 4i64 and) deinterleave into 2 x 2i64 5587 }; 5588 5589 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 5590 {2, MVT::v16i8, 3}, // interleave 2 x 16i8 into 32i8 (and store) 5591 {2, MVT::v32i8, 4}, // interleave 2 x 32i8 into 64i8 (and store) 5592 5593 {2, MVT::v8i16, 3}, // interleave 2 x 8i16 into 16i16 (and store) 5594 {2, MVT::v16i16, 4}, // interleave 2 x 16i16 into 32i16 (and store) 5595 {2, MVT::v32i16, 8}, // interleave 2 x 32i16 into 64i16 (and store) 5596 5597 {2, MVT::v4i32, 2}, // interleave 2 x 4i32 into 8i32 (and store) 5598 {2, MVT::v8i32, 4}, // interleave 2 x 8i32 into 16i32 (and store) 5599 {2, MVT::v16i32, 8}, // interleave 2 x 16i32 into 32i32 (and store) 5600 {2, MVT::v32i32, 16}, // interleave 2 x 32i32 into 64i32 (and store) 5601 5602 {2, MVT::v2i64, 2}, // interleave 2 x 2i64 into 4i64 (and store) 5603 {2, MVT::v4i64, 4}, // interleave 2 x 4i64 into 8i64 (and store) 5604 {2, MVT::v8i64, 8}, // interleave 2 x 8i64 into 16i64 (and store) 5605 {2, MVT::v16i64, 16}, // interleave 2 x 16i64 into 32i64 (and store) 5606 {2, MVT::v32i64, 32}, // interleave 2 x 32i64 into 64i64 (and store) 5607 5608 {3, MVT::v2i8, 4}, // interleave 3 x 2i8 into 6i8 (and store) 5609 {3, MVT::v4i8, 4}, // interleave 3 x 4i8 into 12i8 (and store) 5610 {3, MVT::v8i8, 6}, // interleave 3 x 8i8 into 24i8 (and store) 5611 {3, MVT::v16i8, 11}, // interleave 3 x 16i8 into 48i8 (and store) 5612 {3, MVT::v32i8, 13}, // interleave 3 x 32i8 into 96i8 (and store) 5613 5614 {3, MVT::v2i16, 4}, // interleave 3 x 2i16 into 6i16 (and store) 5615 {3, MVT::v4i16, 6}, // interleave 3 x 4i16 into 12i16 (and store) 5616 {3, MVT::v8i16, 12}, // interleave 3 x 8i16 into 24i16 (and store) 5617 {3, MVT::v16i16, 27}, // interleave 3 x 16i16 into 48i16 (and store) 5618 {3, MVT::v32i16, 54}, // interleave 3 x 32i16 into 96i16 (and store) 5619 5620 {3, MVT::v2i32, 4}, // interleave 3 x 2i32 into 6i32 (and store) 5621 {3, MVT::v4i32, 5}, // interleave 3 x 4i32 into 12i32 (and store) 5622 {3, MVT::v8i32, 11}, // interleave 3 x 8i32 into 24i32 (and store) 5623 {3, MVT::v16i32, 22}, // interleave 3 x 16i32 into 48i32 (and store) 5624 {3, MVT::v32i32, 48}, // interleave 3 x 32i32 into 96i32 (and store) 5625 5626 {3, MVT::v2i64, 4}, // interleave 3 x 2i64 into 6i64 (and store) 5627 {3, MVT::v4i64, 6}, // interleave 3 x 4i64 into 12i64 (and store) 5628 {3, MVT::v8i64, 12}, // interleave 3 x 8i64 into 24i64 (and store) 5629 {3, MVT::v16i64, 24}, // interleave 3 x 16i64 into 48i64 (and store) 5630 5631 {4, MVT::v2i8, 4}, // interleave 4 x 2i8 into 8i8 (and store) 5632 {4, MVT::v4i8, 4}, // interleave 4 x 4i8 into 16i8 (and store) 5633 {4, MVT::v8i8, 4}, // interleave 4 x 8i8 into 32i8 (and store) 5634 {4, MVT::v16i8, 8}, // interleave 4 x 16i8 into 64i8 (and store) 5635 {4, MVT::v32i8, 12}, // interleave 4 x 32i8 into 128i8 (and store) 5636 5637 {4, MVT::v2i16, 2}, // interleave 4 x 2i16 into 8i16 (and store) 5638 {4, MVT::v4i16, 6}, // interleave 4 x 4i16 into 16i16 (and store) 5639 {4, MVT::v8i16, 10}, // interleave 4 x 8i16 into 32i16 (and store) 5640 {4, MVT::v16i16, 32}, // interleave 4 x 16i16 into 64i16 (and store) 5641 {4, MVT::v32i16, 64}, // interleave 4 x 32i16 into 128i16 (and store) 5642 5643 {4, MVT::v2i32, 5}, // interleave 4 x 2i32 into 8i32 (and store) 5644 {4, MVT::v4i32, 6}, // interleave 4 x 4i32 into 16i32 (and store) 5645 {4, MVT::v8i32, 16}, // interleave 4 x 8i32 into 32i32 (and store) 5646 {4, MVT::v16i32, 32}, // interleave 4 x 16i32 into 64i32 (and store) 5647 {4, MVT::v32i32, 64}, // interleave 4 x 32i32 into 128i32 (and store) 5648 5649 {4, MVT::v2i64, 6}, // interleave 4 x 2i64 into 8i64 (and store) 5650 {4, MVT::v4i64, 8}, // interleave 4 x 4i64 into 16i64 (and store) 5651 {4, MVT::v8i64, 20}, // interleave 4 x 8i64 into 32i64 (and store) 5652 {4, MVT::v16i64, 40}, // interleave 4 x 16i64 into 64i64 (and store) 5653 5654 {6, MVT::v2i8, 7}, // interleave 6 x 2i8 into 12i8 (and store) 5655 {6, MVT::v4i8, 9}, // interleave 6 x 4i8 into 24i8 (and store) 5656 {6, MVT::v8i8, 16}, // interleave 6 x 8i8 into 48i8 (and store) 5657 {6, MVT::v16i8, 27}, // interleave 6 x 16i8 into 96i8 (and store) 5658 {6, MVT::v32i8, 90}, // interleave 6 x 32i8 into 192i8 (and store) 5659 5660 {6, MVT::v2i16, 10}, // interleave 6 x 2i16 into 12i16 (and store) 5661 {6, MVT::v4i16, 15}, // interleave 6 x 4i16 into 24i16 (and store) 5662 {6, MVT::v8i16, 21}, // interleave 6 x 8i16 into 48i16 (and store) 5663 {6, MVT::v16i16, 58}, // interleave 6 x 16i16 into 96i16 (and store) 5664 {6, MVT::v32i16, 90}, // interleave 6 x 32i16 into 192i16 (and store) 5665 5666 {6, MVT::v2i32, 9}, // interleave 6 x 2i32 into 12i32 (and store) 5667 {6, MVT::v4i32, 12}, // interleave 6 x 4i32 into 24i32 (and store) 5668 {6, MVT::v8i32, 33}, // interleave 6 x 8i32 into 48i32 (and store) 5669 {6, MVT::v16i32, 66}, // interleave 6 x 16i32 into 96i32 (and store) 5670 5671 {6, MVT::v2i64, 8}, // interleave 6 x 2i64 into 12i64 (and store) 5672 {6, MVT::v4i64, 15}, // interleave 6 x 4i64 into 24i64 (and store) 5673 {6, MVT::v8i64, 30}, // interleave 6 x 8i64 into 48i64 (and store) 5674 }; 5675 5676 static const CostTblEntry SSE2InterleavedStoreTbl[] = { 5677 {2, MVT::v2i8, 1}, // interleave 2 x 2i8 into 4i8 (and store) 5678 {2, MVT::v4i8, 1}, // interleave 2 x 4i8 into 8i8 (and store) 5679 {2, MVT::v8i8, 1}, // interleave 2 x 8i8 into 16i8 (and store) 5680 5681 {2, MVT::v2i16, 1}, // interleave 2 x 2i16 into 4i16 (and store) 5682 {2, MVT::v4i16, 1}, // interleave 2 x 4i16 into 8i16 (and store) 5683 5684 {2, MVT::v2i32, 1}, // interleave 2 x 2i32 into 4i32 (and store) 5685 }; 5686 5687 if (Opcode == Instruction::Load) { 5688 auto GetDiscountedCost = [Factor, NumMembers = Indices.size(), 5689 MemOpCosts](const CostTblEntry *Entry) { 5690 // NOTE: this is just an approximation! 5691 // It can over/under -estimate the cost! 5692 return MemOpCosts + divideCeil(NumMembers * Entry->Cost, Factor); 5693 }; 5694 5695 if (ST->hasAVX2()) 5696 if (const auto *Entry = CostTableLookup(AVX2InterleavedLoadTbl, Factor, 5697 ETy.getSimpleVT())) 5698 return GetDiscountedCost(Entry); 5699 5700 if (ST->hasSSSE3()) 5701 if (const auto *Entry = CostTableLookup(SSSE3InterleavedLoadTbl, Factor, 5702 ETy.getSimpleVT())) 5703 return GetDiscountedCost(Entry); 5704 5705 if (ST->hasSSE2()) 5706 if (const auto *Entry = CostTableLookup(SSE2InterleavedLoadTbl, Factor, 5707 ETy.getSimpleVT())) 5708 return GetDiscountedCost(Entry); 5709 } else { 5710 assert(Opcode == Instruction::Store && 5711 "Expected Store Instruction at this point"); 5712 assert((!Indices.size() || Indices.size() == Factor) && 5713 "Interleaved store only supports fully-interleaved groups."); 5714 if (ST->hasAVX2()) 5715 if (const auto *Entry = CostTableLookup(AVX2InterleavedStoreTbl, Factor, 5716 ETy.getSimpleVT())) 5717 return MemOpCosts + Entry->Cost; 5718 5719 if (ST->hasSSE2()) 5720 if (const auto *Entry = CostTableLookup(SSE2InterleavedStoreTbl, Factor, 5721 ETy.getSimpleVT())) 5722 return MemOpCosts + Entry->Cost; 5723 } 5724 5725 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5726 Alignment, AddressSpace, CostKind, 5727 UseMaskForCond, UseMaskForGaps); 5728 } 5729