1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/InstIterator.h" 47 #include "llvm/IR/IntrinsicInst.h" 48 #include "llvm/Support/Debug.h" 49 50 using namespace llvm; 51 52 #define DEBUG_TYPE "x86tti" 53 54 //===----------------------------------------------------------------------===// 55 // 56 // X86 cost model. 57 // 58 //===----------------------------------------------------------------------===// 59 60 TargetTransformInfo::PopcntSupportKind 61 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 62 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 63 // TODO: Currently the __builtin_popcount() implementation using SSE3 64 // instructions is inefficient. Once the problem is fixed, we should 65 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 66 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 67 } 68 69 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 70 TargetTransformInfo::CacheLevel Level) const { 71 switch (Level) { 72 case TargetTransformInfo::CacheLevel::L1D: 73 // - Penryn 74 // - Nehalem 75 // - Westmere 76 // - Sandy Bridge 77 // - Ivy Bridge 78 // - Haswell 79 // - Broadwell 80 // - Skylake 81 // - Kabylake 82 return 32 * 1024; // 32 KByte 83 case TargetTransformInfo::CacheLevel::L2D: 84 // - Penryn 85 // - Nehalem 86 // - Westmere 87 // - Sandy Bridge 88 // - Ivy Bridge 89 // - Haswell 90 // - Broadwell 91 // - Skylake 92 // - Kabylake 93 return 256 * 1024; // 256 KByte 94 } 95 96 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 97 } 98 99 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 100 TargetTransformInfo::CacheLevel Level) const { 101 // - Penryn 102 // - Nehalem 103 // - Westmere 104 // - Sandy Bridge 105 // - Ivy Bridge 106 // - Haswell 107 // - Broadwell 108 // - Skylake 109 // - Kabylake 110 switch (Level) { 111 case TargetTransformInfo::CacheLevel::L1D: 112 LLVM_FALLTHROUGH; 113 case TargetTransformInfo::CacheLevel::L2D: 114 return 8; 115 } 116 117 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 118 } 119 120 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 121 bool Vector = (ClassID == 1); 122 if (Vector && !ST->hasSSE1()) 123 return 0; 124 125 if (ST->is64Bit()) { 126 if (Vector && ST->hasAVX512()) 127 return 32; 128 return 16; 129 } 130 return 8; 131 } 132 133 TypeSize 134 X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { 135 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 136 switch (K) { 137 case TargetTransformInfo::RGK_Scalar: 138 return TypeSize::getFixed(ST->is64Bit() ? 64 : 32); 139 case TargetTransformInfo::RGK_FixedWidthVector: 140 if (ST->hasAVX512() && PreferVectorWidth >= 512) 141 return TypeSize::getFixed(512); 142 if (ST->hasAVX() && PreferVectorWidth >= 256) 143 return TypeSize::getFixed(256); 144 if (ST->hasSSE1() && PreferVectorWidth >= 128) 145 return TypeSize::getFixed(128); 146 return TypeSize::getFixed(0); 147 case TargetTransformInfo::RGK_ScalableVector: 148 return TypeSize::getScalable(0); 149 } 150 151 llvm_unreachable("Unsupported register kind"); 152 } 153 154 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 155 return getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector) 156 .getFixedSize(); 157 } 158 159 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 160 // If the loop will not be vectorized, don't interleave the loop. 161 // Let regular unroll to unroll the loop, which saves the overflow 162 // check and memory check cost. 163 if (VF == 1) 164 return 1; 165 166 if (ST->isAtom()) 167 return 1; 168 169 // Sandybridge and Haswell have multiple execution ports and pipelined 170 // vector units. 171 if (ST->hasAVX()) 172 return 4; 173 174 return 2; 175 } 176 177 InstructionCost X86TTIImpl::getArithmeticInstrCost( 178 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, 179 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 180 TTI::OperandValueProperties Opd1PropInfo, 181 TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, 182 const Instruction *CxtI) { 183 // TODO: Handle more cost kinds. 184 if (CostKind != TTI::TCK_RecipThroughput) 185 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, 186 Op2Info, Opd1PropInfo, 187 Opd2PropInfo, Args, CxtI); 188 189 // vXi8 multiplications are always promoted to vXi16. 190 if (Opcode == Instruction::Mul && Ty->isVectorTy() && 191 Ty->getScalarSizeInBits() == 8) { 192 Type *WideVecTy = 193 VectorType::getExtendedElementVectorType(cast<VectorType>(Ty)); 194 return getCastInstrCost(Instruction::ZExt, WideVecTy, Ty, 195 TargetTransformInfo::CastContextHint::None, 196 CostKind) + 197 getCastInstrCost(Instruction::Trunc, Ty, WideVecTy, 198 TargetTransformInfo::CastContextHint::None, 199 CostKind) + 200 getArithmeticInstrCost(Opcode, WideVecTy, CostKind, Op1Info, Op2Info, 201 Opd1PropInfo, Opd2PropInfo); 202 } 203 204 // Legalize the type. 205 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 206 207 int ISD = TLI->InstructionOpcodeToISD(Opcode); 208 assert(ISD && "Invalid opcode"); 209 210 if (ISD == ISD::MUL && Args.size() == 2 && LT.second.isVector() && 211 LT.second.getScalarType() == MVT::i32) { 212 // Check if the operands can be represented as a smaller datatype. 213 bool Op1Signed = false, Op2Signed = false; 214 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 215 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 216 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 217 218 // If both are representable as i15 and at least one is constant, 219 // zero-extended, or sign-extended from vXi16 (or less pre-SSE41) then we 220 // can treat this as PMADDWD which has the same costs as a vXi16 multiply. 221 if (OpMinSize <= 15 && !ST->isPMADDWDSlow()) { 222 bool Op1Constant = 223 isa<ConstantDataVector>(Args[0]) || isa<ConstantVector>(Args[0]); 224 bool Op2Constant = 225 isa<ConstantDataVector>(Args[1]) || isa<ConstantVector>(Args[1]); 226 bool Op1Sext = isa<SExtInst>(Args[0]) && 227 (Op1MinSize == 15 || (Op1MinSize < 15 && !ST->hasSSE41())); 228 bool Op2Sext = isa<SExtInst>(Args[1]) && 229 (Op2MinSize == 15 || (Op2MinSize < 15 && !ST->hasSSE41())); 230 231 bool IsZeroExtended = !Op1Signed || !Op2Signed; 232 bool IsConstant = Op1Constant || Op2Constant; 233 bool IsSext = Op1Sext || Op2Sext; 234 if (IsConstant || IsZeroExtended || IsSext) 235 LT.second = 236 MVT::getVectorVT(MVT::i16, 2 * LT.second.getVectorNumElements()); 237 } 238 } 239 240 // Vector multiply by pow2 will be simplified to shifts. 241 if (ISD == ISD::MUL && 242 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 243 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 244 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) 245 return getArithmeticInstrCost(Instruction::Shl, Ty, CostKind, Op1Info, 246 Op2Info, TargetTransformInfo::OP_None, 247 TargetTransformInfo::OP_None); 248 249 // On X86, vector signed division by constants power-of-two are 250 // normally expanded to the sequence SRA + SRL + ADD + SRA. 251 // The OperandValue properties may not be the same as that of the previous 252 // operation; conservatively assume OP_None. 253 if ((ISD == ISD::SDIV || ISD == ISD::SREM) && 254 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 255 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 256 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 257 InstructionCost Cost = 258 2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Op1Info, 259 Op2Info, TargetTransformInfo::OP_None, 260 TargetTransformInfo::OP_None); 261 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 262 Op2Info, TargetTransformInfo::OP_None, 263 TargetTransformInfo::OP_None); 264 Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind, Op1Info, 265 Op2Info, TargetTransformInfo::OP_None, 266 TargetTransformInfo::OP_None); 267 268 if (ISD == ISD::SREM) { 269 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 270 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info, 271 Op2Info); 272 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info, 273 Op2Info); 274 } 275 276 return Cost; 277 } 278 279 // Vector unsigned division/remainder will be simplified to shifts/masks. 280 if ((ISD == ISD::UDIV || ISD == ISD::UREM) && 281 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 282 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 283 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 284 if (ISD == ISD::UDIV) 285 return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 286 Op2Info, TargetTransformInfo::OP_None, 287 TargetTransformInfo::OP_None); 288 // UREM 289 return getArithmeticInstrCost(Instruction::And, Ty, CostKind, Op1Info, 290 Op2Info, TargetTransformInfo::OP_None, 291 TargetTransformInfo::OP_None); 292 } 293 294 static const CostTblEntry GLMCostTable[] = { 295 { ISD::FDIV, MVT::f32, 18 }, // divss 296 { ISD::FDIV, MVT::v4f32, 35 }, // divps 297 { ISD::FDIV, MVT::f64, 33 }, // divsd 298 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 299 }; 300 301 if (ST->useGLMDivSqrtCosts()) 302 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 303 LT.second)) 304 return LT.first * Entry->Cost; 305 306 static const CostTblEntry SLMCostTable[] = { 307 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 308 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 309 { ISD::FMUL, MVT::f64, 2 }, // mulsd 310 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 311 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 312 { ISD::FDIV, MVT::f32, 17 }, // divss 313 { ISD::FDIV, MVT::v4f32, 39 }, // divps 314 { ISD::FDIV, MVT::f64, 32 }, // divsd 315 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 316 { ISD::FADD, MVT::v2f64, 2 }, // addpd 317 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 318 // v2i64/v4i64 mul is custom lowered as a series of long: 319 // multiplies(3), shifts(3) and adds(2) 320 // slm muldq version throughput is 2 and addq throughput 4 321 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 322 // 3X4 (addq throughput) = 17 323 { ISD::MUL, MVT::v2i64, 17 }, 324 // slm addq\subq throughput is 4 325 { ISD::ADD, MVT::v2i64, 4 }, 326 { ISD::SUB, MVT::v2i64, 4 }, 327 }; 328 329 if (ST->useSLMArithCosts()) { 330 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 331 // Check if the operands can be shrinked into a smaller datatype. 332 // TODO: Merge this into generiic vXi32 MUL patterns above. 333 bool Op1Signed = false; 334 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 335 bool Op2Signed = false; 336 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 337 338 bool SignedMode = Op1Signed || Op2Signed; 339 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 340 341 if (OpMinSize <= 7) 342 return LT.first * 3; // pmullw/sext 343 if (!SignedMode && OpMinSize <= 8) 344 return LT.first * 3; // pmullw/zext 345 if (OpMinSize <= 15) 346 return LT.first * 5; // pmullw/pmulhw/pshuf 347 if (!SignedMode && OpMinSize <= 16) 348 return LT.first * 5; // pmullw/pmulhw/pshuf 349 } 350 351 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 352 LT.second)) { 353 return LT.first * Entry->Cost; 354 } 355 } 356 357 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 358 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 359 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 360 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 361 }; 362 363 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 364 ST->hasBWI()) { 365 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 366 LT.second)) 367 return LT.first * Entry->Cost; 368 } 369 370 static const CostTblEntry AVX512UniformConstCostTable[] = { 371 { ISD::SRA, MVT::v2i64, 1 }, 372 { ISD::SRA, MVT::v4i64, 1 }, 373 { ISD::SRA, MVT::v8i64, 1 }, 374 375 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 376 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 377 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 378 379 { ISD::SDIV, MVT::v16i32, 6 }, // pmuludq sequence 380 { ISD::SREM, MVT::v16i32, 8 }, // pmuludq+mul+sub sequence 381 { ISD::UDIV, MVT::v16i32, 5 }, // pmuludq sequence 382 { ISD::UREM, MVT::v16i32, 7 }, // pmuludq+mul+sub sequence 383 }; 384 385 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 386 ST->hasAVX512()) { 387 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 388 LT.second)) 389 return LT.first * Entry->Cost; 390 } 391 392 static const CostTblEntry AVX2UniformConstCostTable[] = { 393 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 394 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 395 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 396 397 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 398 399 { ISD::SDIV, MVT::v8i32, 6 }, // pmuludq sequence 400 { ISD::SREM, MVT::v8i32, 8 }, // pmuludq+mul+sub sequence 401 { ISD::UDIV, MVT::v8i32, 5 }, // pmuludq sequence 402 { ISD::UREM, MVT::v8i32, 7 }, // pmuludq+mul+sub sequence 403 }; 404 405 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 406 ST->hasAVX2()) { 407 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 408 LT.second)) 409 return LT.first * Entry->Cost; 410 } 411 412 static const CostTblEntry SSE2UniformConstCostTable[] = { 413 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 414 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 415 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 416 417 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 418 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 419 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 420 421 { ISD::SDIV, MVT::v8i32, 12+2 }, // 2*pmuludq sequence + split. 422 { ISD::SREM, MVT::v8i32, 16+2 }, // 2*pmuludq+mul+sub sequence + split. 423 { ISD::SDIV, MVT::v4i32, 6 }, // pmuludq sequence 424 { ISD::SREM, MVT::v4i32, 8 }, // pmuludq+mul+sub sequence 425 { ISD::UDIV, MVT::v8i32, 10+2 }, // 2*pmuludq sequence + split. 426 { ISD::UREM, MVT::v8i32, 14+2 }, // 2*pmuludq+mul+sub sequence + split. 427 { ISD::UDIV, MVT::v4i32, 5 }, // pmuludq sequence 428 { ISD::UREM, MVT::v4i32, 7 }, // pmuludq+mul+sub sequence 429 }; 430 431 // XOP has faster vXi8 shifts. 432 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 433 ST->hasSSE2() && !ST->hasXOP()) { 434 if (const auto *Entry = 435 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 436 return LT.first * Entry->Cost; 437 } 438 439 static const CostTblEntry AVX512BWConstCostTable[] = { 440 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 441 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 442 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 443 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 444 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 445 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 446 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 447 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 448 }; 449 450 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 451 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 452 ST->hasBWI()) { 453 if (const auto *Entry = 454 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 455 return LT.first * Entry->Cost; 456 } 457 458 static const CostTblEntry AVX512ConstCostTable[] = { 459 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 460 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 461 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 462 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 463 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 464 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 465 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 466 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 467 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 468 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 469 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 470 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 471 }; 472 473 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 474 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 475 ST->hasAVX512()) { 476 if (const auto *Entry = 477 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 478 return LT.first * Entry->Cost; 479 } 480 481 static const CostTblEntry AVX2ConstCostTable[] = { 482 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 483 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 484 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 485 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 486 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 487 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 488 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 489 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 490 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 491 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 492 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 493 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 494 }; 495 496 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 497 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 498 ST->hasAVX2()) { 499 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 500 return LT.first * Entry->Cost; 501 } 502 503 static const CostTblEntry SSE2ConstCostTable[] = { 504 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 505 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 506 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 507 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 508 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 509 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 510 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 511 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 512 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 513 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 514 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 515 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 516 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 517 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 518 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 519 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 520 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 521 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 522 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 523 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 524 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 525 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 526 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 527 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 528 }; 529 530 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 531 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 532 ST->hasSSE2()) { 533 // pmuldq sequence. 534 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 535 return LT.first * 32; 536 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 537 return LT.first * 38; 538 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 539 return LT.first * 15; 540 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 541 return LT.first * 20; 542 543 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 544 return LT.first * Entry->Cost; 545 } 546 547 static const CostTblEntry AVX512BWShiftCostTable[] = { 548 { ISD::SHL, MVT::v16i8, 4 }, // extend/vpsllvw/pack sequence. 549 { ISD::SRL, MVT::v16i8, 4 }, // extend/vpsrlvw/pack sequence. 550 { ISD::SRA, MVT::v16i8, 4 }, // extend/vpsravw/pack sequence. 551 { ISD::SHL, MVT::v32i8, 4 }, // extend/vpsllvw/pack sequence. 552 { ISD::SRL, MVT::v32i8, 4 }, // extend/vpsrlvw/pack sequence. 553 { ISD::SRA, MVT::v32i8, 6 }, // extend/vpsravw/pack sequence. 554 { ISD::SHL, MVT::v64i8, 6 }, // extend/vpsllvw/pack sequence. 555 { ISD::SRL, MVT::v64i8, 7 }, // extend/vpsrlvw/pack sequence. 556 { ISD::SRA, MVT::v64i8, 15 }, // extend/vpsravw/pack sequence. 557 558 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 559 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 560 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 561 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 562 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 563 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 564 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 565 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 566 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 567 }; 568 569 if (ST->hasBWI()) 570 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 571 return LT.first * Entry->Cost; 572 573 static const CostTblEntry AVX2UniformCostTable[] = { 574 // Uniform splats are cheaper for the following instructions. 575 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 576 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 577 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 578 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 579 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 580 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 581 582 { ISD::SHL, MVT::v8i32, 1 }, // pslld 583 { ISD::SRL, MVT::v8i32, 1 }, // psrld 584 { ISD::SRA, MVT::v8i32, 1 }, // psrad 585 { ISD::SHL, MVT::v4i64, 1 }, // psllq 586 { ISD::SRL, MVT::v4i64, 1 }, // psrlq 587 }; 588 589 if (ST->hasAVX2() && 590 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 591 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 592 if (const auto *Entry = 593 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 594 return LT.first * Entry->Cost; 595 } 596 597 static const CostTblEntry SSE2UniformCostTable[] = { 598 // Uniform splats are cheaper for the following instructions. 599 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 600 { ISD::SHL, MVT::v4i32, 1 }, // pslld 601 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 602 603 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 604 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 605 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 606 607 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 608 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 609 }; 610 611 if (ST->hasSSE2() && 612 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 613 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 614 if (const auto *Entry = 615 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 616 return LT.first * Entry->Cost; 617 } 618 619 static const CostTblEntry AVX512DQCostTable[] = { 620 { ISD::MUL, MVT::v2i64, 2 }, // pmullq 621 { ISD::MUL, MVT::v4i64, 2 }, // pmullq 622 { ISD::MUL, MVT::v8i64, 2 } // pmullq 623 }; 624 625 // Look for AVX512DQ lowering tricks for custom cases. 626 if (ST->hasDQI()) 627 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 628 return LT.first * Entry->Cost; 629 630 static const CostTblEntry AVX512BWCostTable[] = { 631 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 632 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 633 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 634 }; 635 636 // Look for AVX512BW lowering tricks for custom cases. 637 if (ST->hasBWI()) 638 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 639 return LT.first * Entry->Cost; 640 641 static const CostTblEntry AVX512CostTable[] = { 642 { ISD::SHL, MVT::v4i32, 1 }, 643 { ISD::SRL, MVT::v4i32, 1 }, 644 { ISD::SRA, MVT::v4i32, 1 }, 645 { ISD::SHL, MVT::v8i32, 1 }, 646 { ISD::SRL, MVT::v8i32, 1 }, 647 { ISD::SRA, MVT::v8i32, 1 }, 648 { ISD::SHL, MVT::v16i32, 1 }, 649 { ISD::SRL, MVT::v16i32, 1 }, 650 { ISD::SRA, MVT::v16i32, 1 }, 651 652 { ISD::SHL, MVT::v2i64, 1 }, 653 { ISD::SRL, MVT::v2i64, 1 }, 654 { ISD::SHL, MVT::v4i64, 1 }, 655 { ISD::SRL, MVT::v4i64, 1 }, 656 { ISD::SHL, MVT::v8i64, 1 }, 657 { ISD::SRL, MVT::v8i64, 1 }, 658 659 { ISD::SRA, MVT::v2i64, 1 }, 660 { ISD::SRA, MVT::v4i64, 1 }, 661 { ISD::SRA, MVT::v8i64, 1 }, 662 663 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 664 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 665 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 666 { ISD::MUL, MVT::v8i64, 6 }, // 3*pmuludq/3*shift/2*add 667 { ISD::MUL, MVT::i64, 1 }, // Skylake from http://www.agner.org/ 668 669 { ISD::FNEG, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 670 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 671 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 672 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 673 { ISD::FDIV, MVT::f64, 4 }, // Skylake from http://www.agner.org/ 674 { ISD::FDIV, MVT::v2f64, 4 }, // Skylake from http://www.agner.org/ 675 { ISD::FDIV, MVT::v4f64, 8 }, // Skylake from http://www.agner.org/ 676 { ISD::FDIV, MVT::v8f64, 16 }, // Skylake from http://www.agner.org/ 677 678 { ISD::FNEG, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 679 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 680 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 681 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 682 { ISD::FDIV, MVT::f32, 3 }, // Skylake from http://www.agner.org/ 683 { ISD::FDIV, MVT::v4f32, 3 }, // Skylake from http://www.agner.org/ 684 { ISD::FDIV, MVT::v8f32, 5 }, // Skylake from http://www.agner.org/ 685 { ISD::FDIV, MVT::v16f32, 10 }, // Skylake from http://www.agner.org/ 686 }; 687 688 if (ST->hasAVX512()) 689 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 690 return LT.first * Entry->Cost; 691 692 static const CostTblEntry AVX2ShiftCostTable[] = { 693 // Shifts on vXi64/vXi32 on AVX2 is legal even though we declare to 694 // customize them to detect the cases where shift amount is a scalar one. 695 { ISD::SHL, MVT::v4i32, 2 }, // vpsllvd (Haswell from agner.org) 696 { ISD::SRL, MVT::v4i32, 2 }, // vpsrlvd (Haswell from agner.org) 697 { ISD::SRA, MVT::v4i32, 2 }, // vpsravd (Haswell from agner.org) 698 { ISD::SHL, MVT::v8i32, 2 }, // vpsllvd (Haswell from agner.org) 699 { ISD::SRL, MVT::v8i32, 2 }, // vpsrlvd (Haswell from agner.org) 700 { ISD::SRA, MVT::v8i32, 2 }, // vpsravd (Haswell from agner.org) 701 { ISD::SHL, MVT::v2i64, 1 }, // vpsllvq (Haswell from agner.org) 702 { ISD::SRL, MVT::v2i64, 1 }, // vpsrlvq (Haswell from agner.org) 703 { ISD::SHL, MVT::v4i64, 1 }, // vpsllvq (Haswell from agner.org) 704 { ISD::SRL, MVT::v4i64, 1 }, // vpsrlvq (Haswell from agner.org) 705 }; 706 707 if (ST->hasAVX512()) { 708 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 709 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 710 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 711 // On AVX512, a packed v32i16 shift left by a constant build_vector 712 // is lowered into a vector multiply (vpmullw). 713 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 714 Op1Info, Op2Info, 715 TargetTransformInfo::OP_None, 716 TargetTransformInfo::OP_None); 717 } 718 719 // Look for AVX2 lowering tricks (XOP is always better at v4i32 shifts). 720 if (ST->hasAVX2() && !(ST->hasXOP() && LT.second == MVT::v4i32)) { 721 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 722 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 723 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 724 // On AVX2, a packed v16i16 shift left by a constant build_vector 725 // is lowered into a vector multiply (vpmullw). 726 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 727 Op1Info, Op2Info, 728 TargetTransformInfo::OP_None, 729 TargetTransformInfo::OP_None); 730 731 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 732 return LT.first * Entry->Cost; 733 } 734 735 static const CostTblEntry XOPShiftCostTable[] = { 736 // 128bit shifts take 1cy, but right shifts require negation beforehand. 737 { ISD::SHL, MVT::v16i8, 1 }, 738 { ISD::SRL, MVT::v16i8, 2 }, 739 { ISD::SRA, MVT::v16i8, 2 }, 740 { ISD::SHL, MVT::v8i16, 1 }, 741 { ISD::SRL, MVT::v8i16, 2 }, 742 { ISD::SRA, MVT::v8i16, 2 }, 743 { ISD::SHL, MVT::v4i32, 1 }, 744 { ISD::SRL, MVT::v4i32, 2 }, 745 { ISD::SRA, MVT::v4i32, 2 }, 746 { ISD::SHL, MVT::v2i64, 1 }, 747 { ISD::SRL, MVT::v2i64, 2 }, 748 { ISD::SRA, MVT::v2i64, 2 }, 749 // 256bit shifts require splitting if AVX2 didn't catch them above. 750 { ISD::SHL, MVT::v32i8, 2+2 }, 751 { ISD::SRL, MVT::v32i8, 4+2 }, 752 { ISD::SRA, MVT::v32i8, 4+2 }, 753 { ISD::SHL, MVT::v16i16, 2+2 }, 754 { ISD::SRL, MVT::v16i16, 4+2 }, 755 { ISD::SRA, MVT::v16i16, 4+2 }, 756 { ISD::SHL, MVT::v8i32, 2+2 }, 757 { ISD::SRL, MVT::v8i32, 4+2 }, 758 { ISD::SRA, MVT::v8i32, 4+2 }, 759 { ISD::SHL, MVT::v4i64, 2+2 }, 760 { ISD::SRL, MVT::v4i64, 4+2 }, 761 { ISD::SRA, MVT::v4i64, 4+2 }, 762 }; 763 764 // Look for XOP lowering tricks. 765 if (ST->hasXOP()) { 766 // If the right shift is constant then we'll fold the negation so 767 // it's as cheap as a left shift. 768 int ShiftISD = ISD; 769 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 770 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 771 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 772 ShiftISD = ISD::SHL; 773 if (const auto *Entry = 774 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 775 return LT.first * Entry->Cost; 776 } 777 778 static const CostTblEntry SSE2UniformShiftCostTable[] = { 779 // Uniform splats are cheaper for the following instructions. 780 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 781 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 782 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 783 784 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 785 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 786 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 787 788 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 789 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 790 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 791 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 792 }; 793 794 if (ST->hasSSE2() && 795 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 796 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 797 798 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 799 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 800 return LT.first * 4; // 2*psrad + shuffle. 801 802 if (const auto *Entry = 803 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 804 return LT.first * Entry->Cost; 805 } 806 807 if (ISD == ISD::SHL && 808 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 809 MVT VT = LT.second; 810 // Vector shift left by non uniform constant can be lowered 811 // into vector multiply. 812 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 813 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 814 ISD = ISD::MUL; 815 } 816 817 static const CostTblEntry AVX2CostTable[] = { 818 { ISD::SHL, MVT::v16i8, 6 }, // vpblendvb sequence. 819 { ISD::SHL, MVT::v32i8, 6 }, // vpblendvb sequence. 820 { ISD::SHL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 821 { ISD::SHL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 822 { ISD::SHL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 823 { ISD::SHL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 824 825 { ISD::SRL, MVT::v16i8, 6 }, // vpblendvb sequence. 826 { ISD::SRL, MVT::v32i8, 6 }, // vpblendvb sequence. 827 { ISD::SRL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 828 { ISD::SRL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 829 { ISD::SRL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 830 { ISD::SRL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 831 832 { ISD::SRA, MVT::v16i8, 17 }, // vpblendvb sequence. 833 { ISD::SRA, MVT::v32i8, 17 }, // vpblendvb sequence. 834 { ISD::SRA, MVT::v64i8, 34 }, // 2*vpblendvb sequence. 835 { ISD::SRA, MVT::v8i16, 5 }, // extend/vpsravd/pack sequence. 836 { ISD::SRA, MVT::v16i16, 7 }, // extend/vpsravd/pack sequence. 837 { ISD::SRA, MVT::v32i16, 14 }, // 2*extend/vpsravd/pack sequence. 838 { ISD::SRA, MVT::v2i64, 2 }, // srl/xor/sub sequence. 839 { ISD::SRA, MVT::v4i64, 2 }, // srl/xor/sub sequence. 840 841 { ISD::SUB, MVT::v32i8, 1 }, // psubb 842 { ISD::ADD, MVT::v32i8, 1 }, // paddb 843 { ISD::SUB, MVT::v16i16, 1 }, // psubw 844 { ISD::ADD, MVT::v16i16, 1 }, // paddw 845 { ISD::SUB, MVT::v8i32, 1 }, // psubd 846 { ISD::ADD, MVT::v8i32, 1 }, // paddd 847 { ISD::SUB, MVT::v4i64, 1 }, // psubq 848 { ISD::ADD, MVT::v4i64, 1 }, // paddq 849 850 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 851 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 852 { ISD::MUL, MVT::v4i64, 6 }, // 3*pmuludq/3*shift/2*add 853 854 { ISD::FNEG, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 855 { ISD::FNEG, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 856 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 857 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 858 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 859 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 860 { ISD::FMUL, MVT::f64, 1 }, // Haswell from http://www.agner.org/ 861 { ISD::FMUL, MVT::v2f64, 1 }, // Haswell from http://www.agner.org/ 862 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 863 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 864 865 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 866 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 867 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 868 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 869 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 870 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 871 }; 872 873 // Look for AVX2 lowering tricks for custom cases. 874 if (ST->hasAVX2()) 875 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 876 return LT.first * Entry->Cost; 877 878 static const CostTblEntry AVX1CostTable[] = { 879 // We don't have to scalarize unsupported ops. We can issue two half-sized 880 // operations and we only need to extract the upper YMM half. 881 // Two ops + 1 extract + 1 insert = 4. 882 { ISD::MUL, MVT::v16i16, 4 }, 883 { ISD::MUL, MVT::v8i32, 5 }, // BTVER2 from http://www.agner.org/ 884 { ISD::MUL, MVT::v4i64, 12 }, 885 886 { ISD::SUB, MVT::v32i8, 4 }, 887 { ISD::ADD, MVT::v32i8, 4 }, 888 { ISD::SUB, MVT::v16i16, 4 }, 889 { ISD::ADD, MVT::v16i16, 4 }, 890 { ISD::SUB, MVT::v8i32, 4 }, 891 { ISD::ADD, MVT::v8i32, 4 }, 892 { ISD::SUB, MVT::v4i64, 4 }, 893 { ISD::ADD, MVT::v4i64, 4 }, 894 895 { ISD::SHL, MVT::v32i8, 22 }, // pblendvb sequence + split. 896 { ISD::SHL, MVT::v8i16, 6 }, // pblendvb sequence. 897 { ISD::SHL, MVT::v16i16, 13 }, // pblendvb sequence + split. 898 { ISD::SHL, MVT::v4i32, 3 }, // pslld/paddd/cvttps2dq/pmulld 899 { ISD::SHL, MVT::v8i32, 9 }, // pslld/paddd/cvttps2dq/pmulld + split 900 { ISD::SHL, MVT::v2i64, 2 }, // Shift each lane + blend. 901 { ISD::SHL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 902 903 { ISD::SRL, MVT::v32i8, 23 }, // pblendvb sequence + split. 904 { ISD::SRL, MVT::v16i16, 28 }, // pblendvb sequence + split. 905 { ISD::SRL, MVT::v4i32, 6 }, // Shift each lane + blend. 906 { ISD::SRL, MVT::v8i32, 14 }, // Shift each lane + blend + split. 907 { ISD::SRL, MVT::v2i64, 2 }, // Shift each lane + blend. 908 { ISD::SRL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 909 910 { ISD::SRA, MVT::v32i8, 44 }, // pblendvb sequence + split. 911 { ISD::SRA, MVT::v16i16, 28 }, // pblendvb sequence + split. 912 { ISD::SRA, MVT::v4i32, 6 }, // Shift each lane + blend. 913 { ISD::SRA, MVT::v8i32, 14 }, // Shift each lane + blend + split. 914 { ISD::SRA, MVT::v2i64, 5 }, // Shift each lane + blend. 915 { ISD::SRA, MVT::v4i64, 12 }, // Shift each lane + blend + split. 916 917 { ISD::FNEG, MVT::v4f64, 2 }, // BTVER2 from http://www.agner.org/ 918 { ISD::FNEG, MVT::v8f32, 2 }, // BTVER2 from http://www.agner.org/ 919 920 { ISD::FMUL, MVT::f64, 2 }, // BTVER2 from http://www.agner.org/ 921 { ISD::FMUL, MVT::v2f64, 2 }, // BTVER2 from http://www.agner.org/ 922 { ISD::FMUL, MVT::v4f64, 4 }, // BTVER2 from http://www.agner.org/ 923 924 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 925 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 926 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 927 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 928 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 929 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 930 }; 931 932 if (ST->hasAVX()) 933 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 934 return LT.first * Entry->Cost; 935 936 static const CostTblEntry SSE42CostTable[] = { 937 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 938 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 939 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 940 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 941 942 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 943 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 944 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 945 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 946 947 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 948 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 949 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 950 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 951 952 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 953 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 954 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 955 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 956 957 { ISD::MUL, MVT::v2i64, 6 } // 3*pmuludq/3*shift/2*add 958 }; 959 960 if (ST->hasSSE42()) 961 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 962 return LT.first * Entry->Cost; 963 964 static const CostTblEntry SSE41CostTable[] = { 965 { ISD::SHL, MVT::v16i8, 10 }, // pblendvb sequence. 966 { ISD::SHL, MVT::v8i16, 11 }, // pblendvb sequence. 967 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 968 969 { ISD::SRL, MVT::v16i8, 11 }, // pblendvb sequence. 970 { ISD::SRL, MVT::v8i16, 13 }, // pblendvb sequence. 971 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 972 973 { ISD::SRA, MVT::v16i8, 21 }, // pblendvb sequence. 974 { ISD::SRA, MVT::v8i16, 13 }, // pblendvb sequence. 975 976 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 977 }; 978 979 if (ST->hasSSE41()) 980 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 981 return LT.first * Entry->Cost; 982 983 static const CostTblEntry SSE2CostTable[] = { 984 // We don't correctly identify costs of casts because they are marked as 985 // custom. 986 { ISD::SHL, MVT::v16i8, 13 }, // cmpgtb sequence. 987 { ISD::SHL, MVT::v8i16, 25 }, // cmpgtw sequence. 988 { ISD::SHL, MVT::v4i32, 16 }, // pslld/paddd/cvttps2dq/pmuludq. 989 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 990 991 { ISD::SRL, MVT::v16i8, 14 }, // cmpgtb sequence. 992 { ISD::SRL, MVT::v8i16, 16 }, // cmpgtw sequence. 993 { ISD::SRL, MVT::v4i32, 12 }, // Shift each lane + blend. 994 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 995 996 { ISD::SRA, MVT::v16i8, 27 }, // unpacked cmpgtb sequence. 997 { ISD::SRA, MVT::v8i16, 16 }, // cmpgtw sequence. 998 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 999 { ISD::SRA, MVT::v2i64, 8 }, // srl/xor/sub splat+shuffle sequence. 1000 1001 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 1002 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 1003 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 1004 1005 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 1006 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 1007 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 1008 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 1009 1010 { ISD::FNEG, MVT::f32, 1 }, // Pentium IV from http://www.agner.org/ 1011 { ISD::FNEG, MVT::f64, 1 }, // Pentium IV from http://www.agner.org/ 1012 { ISD::FNEG, MVT::v4f32, 1 }, // Pentium IV from http://www.agner.org/ 1013 { ISD::FNEG, MVT::v2f64, 1 }, // Pentium IV from http://www.agner.org/ 1014 1015 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 1016 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 1017 1018 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 1019 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 1020 }; 1021 1022 if (ST->hasSSE2()) 1023 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 1024 return LT.first * Entry->Cost; 1025 1026 static const CostTblEntry SSE1CostTable[] = { 1027 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 1028 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 1029 1030 { ISD::FNEG, MVT::f32, 2 }, // Pentium III from http://www.agner.org/ 1031 { ISD::FNEG, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1032 1033 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1034 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1035 1036 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1037 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1038 }; 1039 1040 if (ST->hasSSE1()) 1041 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 1042 return LT.first * Entry->Cost; 1043 1044 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 1045 { ISD::ADD, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1046 { ISD::SUB, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1047 { ISD::MUL, MVT::i64, 2 }, // Nehalem from http://www.agner.org/ 1048 }; 1049 1050 if (ST->is64Bit()) 1051 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, LT.second)) 1052 return LT.first * Entry->Cost; 1053 1054 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 1055 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1056 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1057 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1058 1059 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1060 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1061 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1062 }; 1063 1064 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, LT.second)) 1065 return LT.first * Entry->Cost; 1066 1067 // It is not a good idea to vectorize division. We have to scalarize it and 1068 // in the process we will often end up having to spilling regular 1069 // registers. The overhead of division is going to dominate most kernels 1070 // anyways so try hard to prevent vectorization of division - it is 1071 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 1072 // to hide "20 cycles" for each lane. 1073 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 1074 ISD == ISD::UDIV || ISD == ISD::UREM)) { 1075 InstructionCost ScalarCost = getArithmeticInstrCost( 1076 Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info, 1077 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 1078 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 1079 } 1080 1081 // Fallback to the default implementation. 1082 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info); 1083 } 1084 1085 InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, 1086 VectorType *BaseTp, 1087 ArrayRef<int> Mask, int Index, 1088 VectorType *SubTp, 1089 ArrayRef<const Value *> Args) { 1090 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 1091 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 1092 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 1093 1094 Kind = improveShuffleKindFromMask(Kind, Mask); 1095 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 1096 if (Kind == TTI::SK_Transpose) 1097 Kind = TTI::SK_PermuteTwoSrc; 1098 1099 // For Broadcasts we are splatting the first element from the first input 1100 // register, so only need to reference that input and all the output 1101 // registers are the same. 1102 if (Kind == TTI::SK_Broadcast) 1103 LT.first = 1; 1104 1105 // Subvector extractions are free if they start at the beginning of a 1106 // vector and cheap if the subvectors are aligned. 1107 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 1108 int NumElts = LT.second.getVectorNumElements(); 1109 if ((Index % NumElts) == 0) 1110 return 0; 1111 std::pair<InstructionCost, MVT> SubLT = 1112 TLI->getTypeLegalizationCost(DL, SubTp); 1113 if (SubLT.second.isVector()) { 1114 int NumSubElts = SubLT.second.getVectorNumElements(); 1115 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1116 return SubLT.first; 1117 // Handle some cases for widening legalization. For now we only handle 1118 // cases where the original subvector was naturally aligned and evenly 1119 // fit in its legalized subvector type. 1120 // FIXME: Remove some of the alignment restrictions. 1121 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 1122 // vectors. 1123 int OrigSubElts = cast<FixedVectorType>(SubTp)->getNumElements(); 1124 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 1125 (NumSubElts % OrigSubElts) == 0 && 1126 LT.second.getVectorElementType() == 1127 SubLT.second.getVectorElementType() && 1128 LT.second.getVectorElementType().getSizeInBits() == 1129 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 1130 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 1131 "Unexpected number of elements!"); 1132 auto *VecTy = FixedVectorType::get(BaseTp->getElementType(), 1133 LT.second.getVectorNumElements()); 1134 auto *SubTy = FixedVectorType::get(BaseTp->getElementType(), 1135 SubLT.second.getVectorNumElements()); 1136 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 1137 InstructionCost ExtractCost = getShuffleCost( 1138 TTI::SK_ExtractSubvector, VecTy, None, ExtractIndex, SubTy); 1139 1140 // If the original size is 32-bits or more, we can use pshufd. Otherwise 1141 // if we have SSSE3 we can use pshufb. 1142 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 1143 return ExtractCost + 1; // pshufd or pshufb 1144 1145 assert(SubTp->getPrimitiveSizeInBits() == 16 && 1146 "Unexpected vector size"); 1147 1148 return ExtractCost + 2; // worst case pshufhw + pshufd 1149 } 1150 } 1151 } 1152 1153 // Subvector insertions are cheap if the subvectors are aligned. 1154 // Note that in general, the insertion starting at the beginning of a vector 1155 // isn't free, because we need to preserve the rest of the wide vector. 1156 if (Kind == TTI::SK_InsertSubvector && LT.second.isVector()) { 1157 int NumElts = LT.second.getVectorNumElements(); 1158 std::pair<InstructionCost, MVT> SubLT = 1159 TLI->getTypeLegalizationCost(DL, SubTp); 1160 if (SubLT.second.isVector()) { 1161 int NumSubElts = SubLT.second.getVectorNumElements(); 1162 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1163 return SubLT.first; 1164 } 1165 1166 // If the insertion isn't aligned, treat it like a 2-op shuffle. 1167 Kind = TTI::SK_PermuteTwoSrc; 1168 } 1169 1170 // Handle some common (illegal) sub-vector types as they are often very cheap 1171 // to shuffle even on targets without PSHUFB. 1172 EVT VT = TLI->getValueType(DL, BaseTp); 1173 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 1174 !ST->hasSSSE3()) { 1175 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 1176 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 1177 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1178 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1179 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1180 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1181 1182 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1183 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1184 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1185 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1186 1187 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1188 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1189 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1190 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1191 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1192 1193 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1194 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1195 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1196 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1197 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1198 }; 1199 1200 if (ST->hasSSE2()) 1201 if (const auto *Entry = 1202 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1203 return Entry->Cost; 1204 } 1205 1206 // We are going to permute multiple sources and the result will be in multiple 1207 // destinations. Providing an accurate cost only for splits where the element 1208 // type remains the same. 1209 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1210 MVT LegalVT = LT.second; 1211 if (LegalVT.isVector() && 1212 LegalVT.getVectorElementType().getSizeInBits() == 1213 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1214 LegalVT.getVectorNumElements() < 1215 cast<FixedVectorType>(BaseTp)->getNumElements()) { 1216 1217 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1218 unsigned LegalVTSize = LegalVT.getStoreSize(); 1219 // Number of source vectors after legalization: 1220 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1221 // Number of destination vectors after legalization: 1222 InstructionCost NumOfDests = LT.first; 1223 1224 auto *SingleOpTy = FixedVectorType::get(BaseTp->getElementType(), 1225 LegalVT.getVectorNumElements()); 1226 1227 if (!Mask.empty() && NumOfDests.isValid()) { 1228 // Try to perform better estimation of the permutation. 1229 // 1. Split the source/destination vectors into real registers. 1230 // 2. Do the mask analysis to identify which real registers are 1231 // permuted. If more than 1 source registers are used for the 1232 // destination register building, the cost for this destination register 1233 // is (Number_of_source_register - 1) * Cost_PermuteTwoSrc. If only one 1234 // source register is used, build mask and calculate the cost as a cost 1235 // of PermuteSingleSrc. 1236 // Also, for the single register permute we try to identify if the 1237 // destination register is just a copy of the source register or the 1238 // copy of the previous destination register (the cost is 1239 // TTI::TCC_Basic). If the source register is just reused, the cost for 1240 // this operation is 0. 1241 unsigned E = *NumOfDests.getValue(); 1242 unsigned PrevSrcReg = 0; 1243 ArrayRef<int> PrevRegMask; 1244 InstructionCost Cost = 0; 1245 processShuffleMasks( 1246 Mask, NumOfSrcs, E, E, []() {}, 1247 [this, SingleOpTy, &PrevSrcReg, &PrevRegMask, 1248 &Cost](ArrayRef<int> RegMask, unsigned SrcReg, unsigned DestReg) { 1249 if (!ShuffleVectorInst::isIdentityMask(RegMask)) { 1250 // Check if the previous register can be just copied to the next 1251 // one. 1252 if (PrevRegMask.empty() || PrevSrcReg != SrcReg || 1253 PrevRegMask != RegMask) 1254 Cost += getShuffleCost(TTI::SK_PermuteSingleSrc, SingleOpTy, 1255 RegMask, 0, nullptr); 1256 else 1257 // Just a copy of previous destination register. 1258 Cost += TTI::TCC_Basic; 1259 return; 1260 } 1261 if (SrcReg != DestReg && 1262 any_of(RegMask, [](int I) { return I != UndefMaskElem; })) { 1263 // Just a copy of the source register. 1264 Cost += TTI::TCC_Basic; 1265 } 1266 PrevSrcReg = SrcReg; 1267 PrevRegMask = RegMask; 1268 }, 1269 [this, SingleOpTy, &Cost](ArrayRef<int> RegMask, 1270 unsigned /*Unused*/, 1271 unsigned /*Unused*/) { 1272 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, RegMask, 1273 0, nullptr); 1274 }); 1275 return Cost; 1276 } 1277 1278 InstructionCost NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1279 return NumOfShuffles * getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 1280 None, 0, nullptr); 1281 } 1282 1283 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1284 } 1285 1286 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1287 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1288 // We assume that source and destination have the same vector type. 1289 InstructionCost NumOfDests = LT.first; 1290 InstructionCost NumOfShufflesPerDest = LT.first * 2 - 1; 1291 LT.first = NumOfDests * NumOfShufflesPerDest; 1292 } 1293 1294 static const CostTblEntry AVX512FP16ShuffleTbl[] = { 1295 {TTI::SK_Broadcast, MVT::v32f16, 1}, // vpbroadcastw 1296 {TTI::SK_Broadcast, MVT::v16f16, 1}, // vpbroadcastw 1297 {TTI::SK_Broadcast, MVT::v8f16, 1}, // vpbroadcastw 1298 1299 {TTI::SK_Reverse, MVT::v32f16, 2}, // vpermw 1300 {TTI::SK_Reverse, MVT::v16f16, 2}, // vpermw 1301 {TTI::SK_Reverse, MVT::v8f16, 1}, // vpshufb 1302 1303 {TTI::SK_PermuteSingleSrc, MVT::v32f16, 2}, // vpermw 1304 {TTI::SK_PermuteSingleSrc, MVT::v16f16, 2}, // vpermw 1305 {TTI::SK_PermuteSingleSrc, MVT::v8f16, 1}, // vpshufb 1306 1307 {TTI::SK_PermuteTwoSrc, MVT::v32f16, 2}, // vpermt2w 1308 {TTI::SK_PermuteTwoSrc, MVT::v16f16, 2}, // vpermt2w 1309 {TTI::SK_PermuteTwoSrc, MVT::v8f16, 2} // vpermt2w 1310 }; 1311 1312 if (!ST->useSoftFloat() && ST->hasFP16()) 1313 if (const auto *Entry = 1314 CostTableLookup(AVX512FP16ShuffleTbl, Kind, LT.second)) 1315 return LT.first * Entry->Cost; 1316 1317 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1318 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1319 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1320 1321 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1322 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1323 1324 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b 1325 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b 1326 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2} // vpermt2b 1327 }; 1328 1329 if (ST->hasVBMI()) 1330 if (const auto *Entry = 1331 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1332 return LT.first * Entry->Cost; 1333 1334 static const CostTblEntry AVX512BWShuffleTbl[] = { 1335 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1336 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1337 1338 {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw 1339 {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw 1340 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1341 1342 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw 1343 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw 1344 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1345 1346 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w 1347 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w 1348 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2}, // vpermt2w 1349 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1350 1351 {TTI::SK_Select, MVT::v32i16, 1}, // vblendmw 1352 {TTI::SK_Select, MVT::v64i8, 1}, // vblendmb 1353 }; 1354 1355 if (ST->hasBWI()) 1356 if (const auto *Entry = 1357 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1358 return LT.first * Entry->Cost; 1359 1360 static const CostTblEntry AVX512ShuffleTbl[] = { 1361 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1362 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1363 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1364 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1365 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1366 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1367 1368 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1369 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1370 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1371 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1372 {TTI::SK_Reverse, MVT::v32i16, 7}, // per mca 1373 {TTI::SK_Reverse, MVT::v64i8, 7}, // per mca 1374 1375 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1376 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1377 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1378 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1379 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1380 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1381 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1382 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1383 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1384 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1385 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1386 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1387 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1388 1389 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1390 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1391 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1392 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1393 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1394 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1395 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1396 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1397 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1398 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1399 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1400 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1401 1402 // FIXME: This just applies the type legalization cost rules above 1403 // assuming these completely split. 1404 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1405 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1406 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1407 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1408 1409 {TTI::SK_Select, MVT::v32i16, 1}, // vpternlogq 1410 {TTI::SK_Select, MVT::v64i8, 1}, // vpternlogq 1411 {TTI::SK_Select, MVT::v8f64, 1}, // vblendmpd 1412 {TTI::SK_Select, MVT::v16f32, 1}, // vblendmps 1413 {TTI::SK_Select, MVT::v8i64, 1}, // vblendmq 1414 {TTI::SK_Select, MVT::v16i32, 1}, // vblendmd 1415 }; 1416 1417 if (ST->hasAVX512()) 1418 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1419 return LT.first * Entry->Cost; 1420 1421 static const CostTblEntry AVX2ShuffleTbl[] = { 1422 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1423 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1424 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1425 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1426 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1427 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1428 1429 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1430 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1431 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1432 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1433 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1434 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1435 1436 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1437 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1438 1439 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1440 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1441 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1442 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1443 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1444 // + vpblendvb 1445 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1446 // + vpblendvb 1447 1448 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1449 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1450 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1451 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1452 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1453 // + vpblendvb 1454 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1455 // + vpblendvb 1456 }; 1457 1458 if (ST->hasAVX2()) 1459 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1460 return LT.first * Entry->Cost; 1461 1462 static const CostTblEntry XOPShuffleTbl[] = { 1463 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1464 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1465 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1466 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1467 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1468 // + vinsertf128 1469 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1470 // + vinsertf128 1471 1472 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1473 // + vinsertf128 1474 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1475 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1476 // + vinsertf128 1477 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1478 }; 1479 1480 if (ST->hasXOP()) 1481 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1482 return LT.first * Entry->Cost; 1483 1484 static const CostTblEntry AVX1ShuffleTbl[] = { 1485 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1486 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1487 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1488 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1489 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1490 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1491 1492 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1493 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1494 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1495 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1496 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1497 // + vinsertf128 1498 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1499 // + vinsertf128 1500 1501 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1502 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1503 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1504 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1505 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1506 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1507 1508 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1509 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1510 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1511 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1512 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1513 // + 2*por + vinsertf128 1514 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1515 // + 2*por + vinsertf128 1516 1517 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1518 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1519 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1520 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1521 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1522 // + 4*por + vinsertf128 1523 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1524 // + 4*por + vinsertf128 1525 }; 1526 1527 if (ST->hasAVX()) 1528 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1529 return LT.first * Entry->Cost; 1530 1531 static const CostTblEntry SSE41ShuffleTbl[] = { 1532 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1533 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1534 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1535 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1536 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1537 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1538 }; 1539 1540 if (ST->hasSSE41()) 1541 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1542 return LT.first * Entry->Cost; 1543 1544 static const CostTblEntry SSSE3ShuffleTbl[] = { 1545 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1546 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1547 1548 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1549 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1550 1551 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1552 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1553 1554 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1555 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1556 1557 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1558 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1559 }; 1560 1561 if (ST->hasSSSE3()) 1562 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1563 return LT.first * Entry->Cost; 1564 1565 static const CostTblEntry SSE2ShuffleTbl[] = { 1566 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1567 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1568 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1569 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1570 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1571 1572 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1573 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1574 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1575 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1576 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1577 // + 2*pshufd + 2*unpck + packus 1578 1579 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1580 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1581 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1582 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1583 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1584 1585 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1586 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1587 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1588 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1589 // + pshufd/unpck 1590 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1591 // + 2*pshufd + 2*unpck + 2*packus 1592 1593 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1594 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1595 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1596 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1597 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1598 }; 1599 1600 static const CostTblEntry SSE3BroadcastLoadTbl[] = { 1601 {TTI::SK_Broadcast, MVT::v2f64, 0}, // broadcast handled by movddup 1602 }; 1603 1604 if (ST->hasSSE2()) { 1605 bool IsLoad = 1606 llvm::any_of(Args, [](const auto &V) { return isa<LoadInst>(V); }); 1607 if (ST->hasSSE3() && IsLoad) 1608 if (const auto *Entry = 1609 CostTableLookup(SSE3BroadcastLoadTbl, Kind, LT.second)) { 1610 assert(isLegalBroadcastLoad(BaseTp->getElementType(), 1611 LT.second.getVectorElementCount()) && 1612 "Table entry missing from isLegalBroadcastLoad()"); 1613 return LT.first * Entry->Cost; 1614 } 1615 1616 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1617 return LT.first * Entry->Cost; 1618 } 1619 1620 static const CostTblEntry SSE1ShuffleTbl[] = { 1621 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1622 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1623 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1624 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1625 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1626 }; 1627 1628 if (ST->hasSSE1()) 1629 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1630 return LT.first * Entry->Cost; 1631 1632 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1633 } 1634 1635 InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, 1636 Type *Src, 1637 TTI::CastContextHint CCH, 1638 TTI::TargetCostKind CostKind, 1639 const Instruction *I) { 1640 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1641 assert(ISD && "Invalid opcode"); 1642 1643 // TODO: Allow non-throughput costs that aren't binary. 1644 auto AdjustCost = [&CostKind](InstructionCost Cost) -> InstructionCost { 1645 if (CostKind != TTI::TCK_RecipThroughput) 1646 return Cost == 0 ? 0 : 1; 1647 return Cost; 1648 }; 1649 1650 // The cost tables include both specific, custom (non-legal) src/dst type 1651 // conversions and generic, legalized types. We test for customs first, before 1652 // falling back to legalization. 1653 // FIXME: Need a better design of the cost table to handle non-simple types of 1654 // potential massive combinations (elem_num x src_type x dst_type). 1655 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1656 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1657 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1658 1659 // Mask sign extend has an instruction. 1660 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1661 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v2i1, 1 }, 1662 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1663 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v2i1, 1 }, 1664 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1665 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v4i1, 1 }, 1666 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1667 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v4i1, 1 }, 1668 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1669 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v8i1, 1 }, 1670 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1671 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1672 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1673 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1674 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1675 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1676 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v64i1, 1 }, 1677 1678 // Mask zero extend is a sext + shift. 1679 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1680 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v2i1, 2 }, 1681 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1682 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v2i1, 2 }, 1683 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1684 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v4i1, 2 }, 1685 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1686 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v4i1, 2 }, 1687 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1688 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v8i1, 2 }, 1689 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1690 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1691 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1692 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1693 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1694 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1695 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v64i1, 2 }, 1696 1697 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, 1698 { ISD::TRUNCATE, MVT::v2i1, MVT::v16i8, 2 }, 1699 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, 1700 { ISD::TRUNCATE, MVT::v2i1, MVT::v8i16, 2 }, 1701 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, 1702 { ISD::TRUNCATE, MVT::v4i1, MVT::v16i8, 2 }, 1703 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, 1704 { ISD::TRUNCATE, MVT::v4i1, MVT::v8i16, 2 }, 1705 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, 1706 { ISD::TRUNCATE, MVT::v8i1, MVT::v16i8, 2 }, 1707 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, 1708 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, 1709 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, 1710 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, 1711 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, 1712 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, 1713 { ISD::TRUNCATE, MVT::v64i1, MVT::v32i16, 2 }, 1714 1715 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, 1716 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm 1717 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // vpmovwb 1718 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // vpmovwb 1719 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // vpmovwb 1720 }; 1721 1722 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1723 // Mask sign extend has an instruction. 1724 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, 1725 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v2i1, 1 }, 1726 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, 1727 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, 1728 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, 1729 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v16i1, 1 }, 1730 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, 1731 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, 1732 1733 // Mask zero extend is a sext + shift. 1734 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, 1735 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v2i1, 2 }, 1736 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, 1737 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, 1738 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, 1739 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v16i1, 2 }, 1740 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, 1741 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1742 1743 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, 1744 { ISD::TRUNCATE, MVT::v2i1, MVT::v4i32, 2 }, 1745 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, 1746 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, 1747 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1748 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, 1749 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, 1750 { ISD::TRUNCATE, MVT::v16i1, MVT::v8i64, 2 }, 1751 1752 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1753 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1754 1755 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1756 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1757 1758 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1759 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1760 1761 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1762 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1763 }; 1764 1765 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1766 // 256-bit wide vectors. 1767 1768 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1769 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1770 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1771 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1772 1773 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1774 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1775 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1776 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd 1777 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1778 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1779 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1780 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd 1781 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd 1782 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd 1783 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd 1784 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd 1785 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq 1786 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq 1787 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq 1788 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 2 }, // vpmovdb 1789 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 2 }, // vpmovdb 1790 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, // vpmovdb 1791 { ISD::TRUNCATE, MVT::v32i8, MVT::v16i32, 2 }, // vpmovdb 1792 { ISD::TRUNCATE, MVT::v64i8, MVT::v16i32, 2 }, // vpmovdb 1793 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, // vpmovdw 1794 { ISD::TRUNCATE, MVT::v32i16, MVT::v16i32, 2 }, // vpmovdw 1795 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 2 }, // vpmovqb 1796 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 1 }, // vpshufb 1797 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, // vpmovqb 1798 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i64, 2 }, // vpmovqb 1799 { ISD::TRUNCATE, MVT::v32i8, MVT::v8i64, 2 }, // vpmovqb 1800 { ISD::TRUNCATE, MVT::v64i8, MVT::v8i64, 2 }, // vpmovqb 1801 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, // vpmovqw 1802 { ISD::TRUNCATE, MVT::v16i16, MVT::v8i64, 2 }, // vpmovqw 1803 { ISD::TRUNCATE, MVT::v32i16, MVT::v8i64, 2 }, // vpmovqw 1804 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, // vpmovqd 1805 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd 1806 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb 1807 1808 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32 1809 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, 1810 { ISD::TRUNCATE, MVT::v64i8, MVT::v32i16, 8 }, 1811 1812 // Sign extend is zmm vpternlogd+vptruncdb. 1813 // Zero extend is zmm broadcast load+vptruncdw. 1814 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 }, 1815 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 }, 1816 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, 1817 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, 1818 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, 1819 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, 1820 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 }, 1821 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 }, 1822 1823 // Sign extend is zmm vpternlogd+vptruncdw. 1824 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw. 1825 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 }, 1826 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1827 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 }, 1828 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1829 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 }, 1830 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1831 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 }, 1832 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1833 1834 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd 1835 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld 1836 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd 1837 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld 1838 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd 1839 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld 1840 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq 1841 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq 1842 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq 1843 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq 1844 1845 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd 1846 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld 1847 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq 1848 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq 1849 1850 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1851 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1852 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1853 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1854 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1855 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1856 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1857 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1858 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1859 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1860 1861 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1862 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1863 1864 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1865 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1866 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, 1867 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, 1868 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1869 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, 1870 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1871 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1872 1873 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1874 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1875 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, 1876 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, 1877 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1878 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, 1879 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1880 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1881 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1882 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1883 1884 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2 }, 1885 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f64, 7 }, 1886 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f64,15 }, 1887 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f32,11 }, 1888 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f64,31 }, 1889 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, 1890 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f64, 7 }, 1891 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f32, 5 }, 1892 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f64,15 }, 1893 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 1 }, 1894 { ISD::FP_TO_SINT, MVT::v16i32, MVT::v16f64, 3 }, 1895 1896 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1897 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, 1898 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, 1899 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1900 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, 1901 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, 1902 }; 1903 1904 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1905 // Mask sign extend has an instruction. 1906 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1907 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v2i1, 1 }, 1908 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1909 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v2i1, 1 }, 1910 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1911 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v4i1, 1 }, 1912 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1913 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v4i1, 1 }, 1914 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1915 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v8i1, 1 }, 1916 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1917 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1918 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1919 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1920 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v32i1, 1 }, 1921 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v64i1, 1 }, 1922 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v64i1, 1 }, 1923 1924 // Mask zero extend is a sext + shift. 1925 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1926 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v2i1, 2 }, 1927 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1928 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v2i1, 2 }, 1929 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1930 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v4i1, 2 }, 1931 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1932 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v4i1, 2 }, 1933 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1934 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v8i1, 2 }, 1935 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1936 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1937 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1938 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1939 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v32i1, 2 }, 1940 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v64i1, 2 }, 1941 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v64i1, 2 }, 1942 1943 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, 1944 { ISD::TRUNCATE, MVT::v2i1, MVT::v16i8, 2 }, 1945 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, 1946 { ISD::TRUNCATE, MVT::v2i1, MVT::v8i16, 2 }, 1947 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, 1948 { ISD::TRUNCATE, MVT::v4i1, MVT::v16i8, 2 }, 1949 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, 1950 { ISD::TRUNCATE, MVT::v4i1, MVT::v8i16, 2 }, 1951 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, 1952 { ISD::TRUNCATE, MVT::v8i1, MVT::v16i8, 2 }, 1953 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, 1954 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, 1955 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, 1956 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, 1957 { ISD::TRUNCATE, MVT::v32i1, MVT::v16i16, 2 }, 1958 { ISD::TRUNCATE, MVT::v64i1, MVT::v32i8, 2 }, 1959 { ISD::TRUNCATE, MVT::v64i1, MVT::v16i16, 2 }, 1960 1961 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, 1962 }; 1963 1964 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1965 // Mask sign extend has an instruction. 1966 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, 1967 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v2i1, 1 }, 1968 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, 1969 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i1, 1 }, 1970 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, 1971 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i1, 1 }, 1972 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i1, 1 }, 1973 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, 1974 1975 // Mask zero extend is a sext + shift. 1976 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, 1977 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v2i1, 2 }, 1978 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, 1979 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i1, 2 }, 1980 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, 1981 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i1, 2 }, 1982 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i1, 2 }, 1983 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, 1984 1985 { ISD::TRUNCATE, MVT::v16i1, MVT::v4i64, 2 }, 1986 { ISD::TRUNCATE, MVT::v16i1, MVT::v8i32, 2 }, 1987 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, 1988 { ISD::TRUNCATE, MVT::v2i1, MVT::v4i32, 2 }, 1989 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, 1990 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, 1991 { ISD::TRUNCATE, MVT::v8i1, MVT::v4i64, 2 }, 1992 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1993 1994 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1995 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1996 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1997 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1998 1999 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 2000 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 2001 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 2002 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 2003 2004 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v4f32, 1 }, 2005 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 2006 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 2007 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 2008 2009 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v4f32, 1 }, 2010 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 2011 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 2012 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 2013 }; 2014 2015 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 2016 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 2017 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 2018 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 2019 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 8 }, // split+2*v8i8 2020 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 2021 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 2022 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 2023 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16 2024 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // vpslld+vptestmd 2025 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd 2026 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // vpslld+vptestmd 2027 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // vpsllq+vptestmq 2028 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // vpsllq+vptestmq 2029 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // vpmovqd 2030 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, // vpmovqb 2031 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, // vpmovqw 2032 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, // vpmovwb 2033 2034 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb 2035 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb 2036 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 }, 2037 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 }, 2038 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 }, 2039 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 }, 2040 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 }, 2041 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 }, 2042 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 }, 2043 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 }, 2044 2045 // sign extend is vpcmpeq+maskedmove+vpmovdw 2046 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw 2047 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 2048 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 }, 2049 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 2050 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 }, 2051 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 2052 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 }, 2053 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 }, 2054 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 }, 2055 2056 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd 2057 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld 2058 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd 2059 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld 2060 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd 2061 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld 2062 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq 2063 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq 2064 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq 2065 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq 2066 2067 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 1 }, 2068 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 1 }, 2069 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 1 }, 2070 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 1 }, 2071 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 2072 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 2073 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 1 }, 2074 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 1 }, 2075 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 2076 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 2077 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 2078 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 2079 2080 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2081 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 1 }, 2082 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2083 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 1 }, 2084 2085 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 2086 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 2087 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2088 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 1 }, 2089 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2090 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 1 }, 2091 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 2092 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 2093 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 2094 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 2095 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 2096 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 2097 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 2098 2099 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v8f32, 2 }, 2100 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2 }, 2101 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f32, 5 }, 2102 2103 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 2104 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 2105 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 2106 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 1 }, 2107 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 2108 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 2109 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 2110 }; 2111 2112 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 2113 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 2114 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 2115 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 2116 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 2117 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 2118 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 2119 2120 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 2 }, 2121 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 2 }, 2122 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 2 }, 2123 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 2 }, 2124 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 2125 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 2126 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 2 }, 2127 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 2 }, 2128 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 2129 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 2130 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 2131 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 2132 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 2133 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 2134 2135 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 2136 2137 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 4 }, 2138 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 4 }, 2139 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i16, 1 }, 2140 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 1 }, 2141 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 1 }, 2142 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i32, 4 }, 2143 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i64, 4 }, 2144 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 1 }, 2145 { ISD::TRUNCATE, MVT::v8i16, MVT::v2i64, 1 }, 2146 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i64, 5 }, 2147 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, 2148 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 2149 2150 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 2151 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 2152 2153 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v8f32, 1 }, 2154 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 1 }, 2155 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 1 }, 2156 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 3 }, 2157 2158 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 3 }, 2159 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 3 }, 2160 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v8f32, 1 }, 2161 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 3 }, 2162 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 2163 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4 }, 2164 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 3 }, 2165 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v4f64, 4 }, 2166 2167 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 2 }, 2168 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 2 }, 2169 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 2 }, 2170 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 2171 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 2172 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 2173 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 3 }, 2174 2175 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 2 }, 2176 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 2 }, 2177 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 2 }, 2178 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 2179 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 2180 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 2181 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 2 }, 2182 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2183 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 2184 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 }, 2185 }; 2186 2187 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 2188 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 2189 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 2190 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 2191 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 2192 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 2193 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 2194 2195 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 3 }, 2196 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 3 }, 2197 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 3 }, 2198 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 3 }, 2199 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 2200 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 2201 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 3 }, 2202 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 3 }, 2203 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 2204 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 2205 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 2206 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 2207 2208 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 4 }, 2209 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 5 }, 2210 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 4 }, 2211 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 9 }, 2212 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, 11 }, 2213 2214 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 2215 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, 2216 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // and+extract+packuswb 2217 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i32, 5 }, 2218 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2219 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i64, 5 }, 2220 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i64, 3 }, // and+extract+2*packusdw 2221 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 2222 2223 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 2224 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 2225 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 2226 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 4 }, 2227 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v16i8, 2 }, 2228 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 2229 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v8i16, 2 }, 2230 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2231 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 2232 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 }, 2233 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 5 }, 2234 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 8 }, 2235 2236 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 2237 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 2238 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 2239 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 4 }, 2240 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v16i8, 2 }, 2241 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 2242 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v8i16, 2 }, 2243 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 4 }, 2244 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 4 }, 2245 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 2246 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 2247 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 2248 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 10 }, 2249 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 10 }, 2250 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 18 }, 2251 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 2252 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 10 }, 2253 2254 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v8f32, 2 }, 2255 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f64, 2 }, 2256 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v8f32, 2 }, 2257 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v4f64, 2 }, 2258 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 2 }, 2259 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f64, 2 }, 2260 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v8f32, 2 }, 2261 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v4f64, 2 }, 2262 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 2 }, 2263 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 2 }, 2264 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 5 }, 2265 2266 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v8f32, 2 }, 2267 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f64, 2 }, 2268 { ISD::FP_TO_UINT, MVT::v32i8, MVT::v8f32, 2 }, 2269 { ISD::FP_TO_UINT, MVT::v32i8, MVT::v4f64, 2 }, 2270 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 2 }, 2271 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f64, 2 }, 2272 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v8f32, 2 }, 2273 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v4f64, 2 }, 2274 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 3 }, 2275 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 2276 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 6 }, 2277 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 7 }, 2278 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v4f64, 7 }, 2279 2280 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 2281 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 2282 }; 2283 2284 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 2285 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8, 1 }, 2286 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8, 1 }, 2287 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8, 1 }, 2288 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8, 1 }, 2289 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2290 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2291 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16, 1 }, 2292 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16, 1 }, 2293 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2294 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2295 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2296 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2297 2298 // These truncates end up widening elements. 2299 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 1 }, // PMOVXZBQ 2300 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 1 }, // PMOVXZWQ 2301 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 1 }, // PMOVXZBD 2302 2303 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 2 }, 2304 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 2 }, 2305 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 2 }, 2306 2307 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 1 }, 2308 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 1 }, 2309 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 1 }, 2310 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 1 }, 2311 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 1 }, 2312 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2313 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 1 }, 2314 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2315 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 2316 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 1 }, 2317 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2318 2319 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 1 }, 2320 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 1 }, 2321 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 2322 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 2323 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 1 }, 2324 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2325 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 1 }, 2326 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2327 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 3 }, 2328 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 3 }, 2329 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 2 }, 2330 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 12 }, 2331 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 22 }, 2332 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 4 }, 2333 2334 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 1 }, 2335 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 1 }, 2336 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 1 }, 2337 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 1 }, 2338 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f32, 2 }, 2339 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v2f64, 2 }, 2340 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f32, 1 }, 2341 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v2f64, 1 }, 2342 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, 2343 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v2f64, 1 }, 2344 2345 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 1 }, 2346 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 2347 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 1 }, 2348 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 2349 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f32, 2 }, 2350 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v2f64, 2 }, 2351 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f32, 1 }, 2352 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v2f64, 1 }, 2353 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 4 }, 2354 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 2355 }; 2356 2357 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 2358 // These are somewhat magic numbers justified by comparing the 2359 // output of llvm-mca for our various supported scheduler models 2360 // and basing it off the worst case scenario. 2361 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 3 }, 2362 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 3 }, 2363 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 3 }, 2364 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 3 }, 2365 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 3 }, 2366 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 4 }, 2367 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 3 }, 2368 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 4 }, 2369 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 3 }, 2370 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4 }, 2371 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 8 }, 2372 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 8 }, 2373 2374 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 3 }, 2375 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 3 }, 2376 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 8 }, 2377 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 9 }, 2378 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 4 }, 2379 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 4 }, 2380 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 4 }, 2381 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 4 }, 2382 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 7 }, 2383 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 7 }, 2384 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 2385 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 15 }, 2386 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 18 }, 2387 2388 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 4 }, 2389 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 4 }, 2390 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 4 }, 2391 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 4 }, 2392 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f32, 6 }, 2393 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v2f64, 6 }, 2394 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f32, 5 }, 2395 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v2f64, 5 }, 2396 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 4 }, 2397 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v2f64, 4 }, 2398 2399 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 4 }, 2400 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 2401 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 4 }, 2402 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 15 }, 2403 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f32, 6 }, 2404 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v2f64, 6 }, 2405 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f32, 5 }, 2406 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v2f64, 5 }, 2407 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 8 }, 2408 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 8 }, 2409 2410 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8, 4 }, 2411 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8, 4 }, 2412 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8, 2 }, 2413 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8, 3 }, 2414 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2415 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8, 2 }, 2416 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16, 2 }, 2417 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16, 3 }, 2418 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2419 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16, 2 }, 2420 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2421 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32, 2 }, 2422 2423 // These truncates are really widening elements. 2424 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 1 }, // PSHUFD 2425 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // PUNPCKLWD+DQ 2426 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // PUNPCKLBW+WD+PSHUFD 2427 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 1 }, // PUNPCKLWD 2428 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // PUNPCKLBW+WD 2429 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 1 }, // PUNPCKLBW 2430 2431 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i16, 2 }, // PAND+PACKUSWB 2432 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 2433 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 3 }, // PAND+2*PACKUSWB 2434 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 2435 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 2436 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 3 }, 2437 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2438 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32,10 }, 2439 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 2440 { ISD::TRUNCATE, MVT::v8i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 2441 { ISD::TRUNCATE, MVT::v4i32, MVT::v2i64, 1 }, // PSHUFD 2442 }; 2443 2444 // Attempt to map directly to (simple) MVT types to let us match custom entries. 2445 EVT SrcTy = TLI->getValueType(DL, Src); 2446 EVT DstTy = TLI->getValueType(DL, Dst); 2447 2448 // The function getSimpleVT only handles simple value types. 2449 if (SrcTy.isSimple() && DstTy.isSimple()) { 2450 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 2451 MVT SimpleDstTy = DstTy.getSimpleVT(); 2452 2453 if (ST->useAVX512Regs()) { 2454 if (ST->hasBWI()) 2455 if (const auto *Entry = ConvertCostTableLookup( 2456 AVX512BWConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2457 return AdjustCost(Entry->Cost); 2458 2459 if (ST->hasDQI()) 2460 if (const auto *Entry = ConvertCostTableLookup( 2461 AVX512DQConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2462 return AdjustCost(Entry->Cost); 2463 2464 if (ST->hasAVX512()) 2465 if (const auto *Entry = ConvertCostTableLookup( 2466 AVX512FConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2467 return AdjustCost(Entry->Cost); 2468 } 2469 2470 if (ST->hasBWI()) 2471 if (const auto *Entry = ConvertCostTableLookup( 2472 AVX512BWVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2473 return AdjustCost(Entry->Cost); 2474 2475 if (ST->hasDQI()) 2476 if (const auto *Entry = ConvertCostTableLookup( 2477 AVX512DQVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2478 return AdjustCost(Entry->Cost); 2479 2480 if (ST->hasAVX512()) 2481 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2482 SimpleDstTy, SimpleSrcTy)) 2483 return AdjustCost(Entry->Cost); 2484 2485 if (ST->hasAVX2()) { 2486 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2487 SimpleDstTy, SimpleSrcTy)) 2488 return AdjustCost(Entry->Cost); 2489 } 2490 2491 if (ST->hasAVX()) { 2492 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2493 SimpleDstTy, SimpleSrcTy)) 2494 return AdjustCost(Entry->Cost); 2495 } 2496 2497 if (ST->hasSSE41()) { 2498 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2499 SimpleDstTy, SimpleSrcTy)) 2500 return AdjustCost(Entry->Cost); 2501 } 2502 2503 if (ST->hasSSE2()) { 2504 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2505 SimpleDstTy, SimpleSrcTy)) 2506 return AdjustCost(Entry->Cost); 2507 } 2508 } 2509 2510 // Fall back to legalized types. 2511 std::pair<InstructionCost, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 2512 std::pair<InstructionCost, MVT> LTDest = 2513 TLI->getTypeLegalizationCost(DL, Dst); 2514 2515 if (ST->useAVX512Regs()) { 2516 if (ST->hasBWI()) 2517 if (const auto *Entry = ConvertCostTableLookup( 2518 AVX512BWConversionTbl, ISD, LTDest.second, LTSrc.second)) 2519 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2520 2521 if (ST->hasDQI()) 2522 if (const auto *Entry = ConvertCostTableLookup( 2523 AVX512DQConversionTbl, ISD, LTDest.second, LTSrc.second)) 2524 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2525 2526 if (ST->hasAVX512()) 2527 if (const auto *Entry = ConvertCostTableLookup( 2528 AVX512FConversionTbl, ISD, LTDest.second, LTSrc.second)) 2529 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2530 } 2531 2532 if (ST->hasBWI()) 2533 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 2534 LTDest.second, LTSrc.second)) 2535 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2536 2537 if (ST->hasDQI()) 2538 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 2539 LTDest.second, LTSrc.second)) 2540 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2541 2542 if (ST->hasAVX512()) 2543 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2544 LTDest.second, LTSrc.second)) 2545 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2546 2547 if (ST->hasAVX2()) 2548 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2549 LTDest.second, LTSrc.second)) 2550 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2551 2552 if (ST->hasAVX()) 2553 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2554 LTDest.second, LTSrc.second)) 2555 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2556 2557 if (ST->hasSSE41()) 2558 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2559 LTDest.second, LTSrc.second)) 2560 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2561 2562 if (ST->hasSSE2()) 2563 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2564 LTDest.second, LTSrc.second)) 2565 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2566 2567 // Fallback, for i8/i16 sitofp/uitofp cases we need to extend to i32 for 2568 // sitofp. 2569 if ((ISD == ISD::SINT_TO_FP || ISD == ISD::UINT_TO_FP) && 2570 1 < Src->getScalarSizeInBits() && Src->getScalarSizeInBits() < 32) { 2571 Type *ExtSrc = Src->getWithNewBitWidth(32); 2572 unsigned ExtOpc = 2573 (ISD == ISD::SINT_TO_FP) ? Instruction::SExt : Instruction::ZExt; 2574 2575 // For scalar loads the extend would be free. 2576 InstructionCost ExtCost = 0; 2577 if (!(Src->isIntegerTy() && I && isa<LoadInst>(I->getOperand(0)))) 2578 ExtCost = getCastInstrCost(ExtOpc, ExtSrc, Src, CCH, CostKind); 2579 2580 return ExtCost + getCastInstrCost(Instruction::SIToFP, Dst, ExtSrc, 2581 TTI::CastContextHint::None, CostKind); 2582 } 2583 2584 // Fallback for fptosi/fptoui i8/i16 cases we need to truncate from fptosi 2585 // i32. 2586 if ((ISD == ISD::FP_TO_SINT || ISD == ISD::FP_TO_UINT) && 2587 1 < Dst->getScalarSizeInBits() && Dst->getScalarSizeInBits() < 32) { 2588 Type *TruncDst = Dst->getWithNewBitWidth(32); 2589 return getCastInstrCost(Instruction::FPToSI, TruncDst, Src, CCH, CostKind) + 2590 getCastInstrCost(Instruction::Trunc, Dst, TruncDst, 2591 TTI::CastContextHint::None, CostKind); 2592 } 2593 2594 return AdjustCost( 2595 BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I)); 2596 } 2597 2598 InstructionCost X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 2599 Type *CondTy, 2600 CmpInst::Predicate VecPred, 2601 TTI::TargetCostKind CostKind, 2602 const Instruction *I) { 2603 // TODO: Handle other cost kinds. 2604 if (CostKind != TTI::TCK_RecipThroughput) 2605 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, 2606 I); 2607 2608 // Legalize the type. 2609 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2610 2611 MVT MTy = LT.second; 2612 2613 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2614 assert(ISD && "Invalid opcode"); 2615 2616 unsigned ExtraCost = 0; 2617 if (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp) { 2618 // Some vector comparison predicates cost extra instructions. 2619 // TODO: Should we invert this and assume worst case cmp costs 2620 // and reduce for particular predicates? 2621 if (MTy.isVector() && 2622 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 2623 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 2624 ST->hasBWI())) { 2625 // Fallback to I if a specific predicate wasn't specified. 2626 CmpInst::Predicate Pred = VecPred; 2627 if (I && (Pred == CmpInst::BAD_ICMP_PREDICATE || 2628 Pred == CmpInst::BAD_FCMP_PREDICATE)) 2629 Pred = cast<CmpInst>(I)->getPredicate(); 2630 2631 switch (Pred) { 2632 case CmpInst::Predicate::ICMP_NE: 2633 // xor(cmpeq(x,y),-1) 2634 ExtraCost = 1; 2635 break; 2636 case CmpInst::Predicate::ICMP_SGE: 2637 case CmpInst::Predicate::ICMP_SLE: 2638 // xor(cmpgt(x,y),-1) 2639 ExtraCost = 1; 2640 break; 2641 case CmpInst::Predicate::ICMP_ULT: 2642 case CmpInst::Predicate::ICMP_UGT: 2643 // cmpgt(xor(x,signbit),xor(y,signbit)) 2644 // xor(cmpeq(pmaxu(x,y),x),-1) 2645 ExtraCost = 2; 2646 break; 2647 case CmpInst::Predicate::ICMP_ULE: 2648 case CmpInst::Predicate::ICMP_UGE: 2649 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 2650 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 2651 // cmpeq(psubus(x,y),0) 2652 // cmpeq(pminu(x,y),x) 2653 ExtraCost = 1; 2654 } else { 2655 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 2656 ExtraCost = 3; 2657 } 2658 break; 2659 case CmpInst::Predicate::BAD_ICMP_PREDICATE: 2660 case CmpInst::Predicate::BAD_FCMP_PREDICATE: 2661 // Assume worst case scenario and add the maximum extra cost. 2662 ExtraCost = 3; 2663 break; 2664 default: 2665 break; 2666 } 2667 } 2668 } 2669 2670 static const CostTblEntry SLMCostTbl[] = { 2671 // slm pcmpeq/pcmpgt throughput is 2 2672 { ISD::SETCC, MVT::v2i64, 2 }, 2673 }; 2674 2675 static const CostTblEntry AVX512BWCostTbl[] = { 2676 { ISD::SETCC, MVT::v32i16, 1 }, 2677 { ISD::SETCC, MVT::v64i8, 1 }, 2678 2679 { ISD::SELECT, MVT::v32i16, 1 }, 2680 { ISD::SELECT, MVT::v64i8, 1 }, 2681 }; 2682 2683 static const CostTblEntry AVX512CostTbl[] = { 2684 { ISD::SETCC, MVT::v8i64, 1 }, 2685 { ISD::SETCC, MVT::v16i32, 1 }, 2686 { ISD::SETCC, MVT::v8f64, 1 }, 2687 { ISD::SETCC, MVT::v16f32, 1 }, 2688 2689 { ISD::SELECT, MVT::v8i64, 1 }, 2690 { ISD::SELECT, MVT::v16i32, 1 }, 2691 { ISD::SELECT, MVT::v8f64, 1 }, 2692 { ISD::SELECT, MVT::v16f32, 1 }, 2693 2694 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 2695 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 2696 2697 { ISD::SELECT, MVT::v32i16, 2 }, // FIXME: should be 3 2698 { ISD::SELECT, MVT::v64i8, 2 }, // FIXME: should be 3 2699 }; 2700 2701 static const CostTblEntry AVX2CostTbl[] = { 2702 { ISD::SETCC, MVT::v4i64, 1 }, 2703 { ISD::SETCC, MVT::v8i32, 1 }, 2704 { ISD::SETCC, MVT::v16i16, 1 }, 2705 { ISD::SETCC, MVT::v32i8, 1 }, 2706 2707 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 2708 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 2709 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 2710 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 2711 }; 2712 2713 static const CostTblEntry AVX1CostTbl[] = { 2714 { ISD::SETCC, MVT::v4f64, 1 }, 2715 { ISD::SETCC, MVT::v8f32, 1 }, 2716 // AVX1 does not support 8-wide integer compare. 2717 { ISD::SETCC, MVT::v4i64, 4 }, 2718 { ISD::SETCC, MVT::v8i32, 4 }, 2719 { ISD::SETCC, MVT::v16i16, 4 }, 2720 { ISD::SETCC, MVT::v32i8, 4 }, 2721 2722 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 2723 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 2724 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 2725 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 2726 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 2727 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 2728 }; 2729 2730 static const CostTblEntry SSE42CostTbl[] = { 2731 { ISD::SETCC, MVT::v2f64, 1 }, 2732 { ISD::SETCC, MVT::v4f32, 1 }, 2733 { ISD::SETCC, MVT::v2i64, 1 }, 2734 }; 2735 2736 static const CostTblEntry SSE41CostTbl[] = { 2737 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 2738 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 2739 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 2740 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 2741 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 2742 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 2743 }; 2744 2745 static const CostTblEntry SSE2CostTbl[] = { 2746 { ISD::SETCC, MVT::v2f64, 2 }, 2747 { ISD::SETCC, MVT::f64, 1 }, 2748 { ISD::SETCC, MVT::v2i64, 5 }, // pcmpeqd/pcmpgtd expansion 2749 { ISD::SETCC, MVT::v4i32, 1 }, 2750 { ISD::SETCC, MVT::v8i16, 1 }, 2751 { ISD::SETCC, MVT::v16i8, 1 }, 2752 2753 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 2754 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 2755 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 2756 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 2757 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 2758 }; 2759 2760 static const CostTblEntry SSE1CostTbl[] = { 2761 { ISD::SETCC, MVT::v4f32, 2 }, 2762 { ISD::SETCC, MVT::f32, 1 }, 2763 2764 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 2765 }; 2766 2767 if (ST->useSLMArithCosts()) 2768 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2769 return LT.first * (ExtraCost + Entry->Cost); 2770 2771 if (ST->hasBWI()) 2772 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2773 return LT.first * (ExtraCost + Entry->Cost); 2774 2775 if (ST->hasAVX512()) 2776 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2777 return LT.first * (ExtraCost + Entry->Cost); 2778 2779 if (ST->hasAVX2()) 2780 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2781 return LT.first * (ExtraCost + Entry->Cost); 2782 2783 if (ST->hasAVX()) 2784 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2785 return LT.first * (ExtraCost + Entry->Cost); 2786 2787 if (ST->hasSSE42()) 2788 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2789 return LT.first * (ExtraCost + Entry->Cost); 2790 2791 if (ST->hasSSE41()) 2792 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2793 return LT.first * (ExtraCost + Entry->Cost); 2794 2795 if (ST->hasSSE2()) 2796 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2797 return LT.first * (ExtraCost + Entry->Cost); 2798 2799 if (ST->hasSSE1()) 2800 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2801 return LT.first * (ExtraCost + Entry->Cost); 2802 2803 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I); 2804 } 2805 2806 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2807 2808 InstructionCost 2809 X86TTIImpl::getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 2810 TTI::TargetCostKind CostKind) { 2811 2812 // Costs should match the codegen from: 2813 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2814 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2815 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2816 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2817 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2818 2819 // TODO: Overflow intrinsics (*ADDO, *SUBO, *MULO) with vector types are not 2820 // specialized in these tables yet. 2821 static const CostTblEntry AVX512BITALGCostTbl[] = { 2822 { ISD::CTPOP, MVT::v32i16, 1 }, 2823 { ISD::CTPOP, MVT::v64i8, 1 }, 2824 { ISD::CTPOP, MVT::v16i16, 1 }, 2825 { ISD::CTPOP, MVT::v32i8, 1 }, 2826 { ISD::CTPOP, MVT::v8i16, 1 }, 2827 { ISD::CTPOP, MVT::v16i8, 1 }, 2828 }; 2829 static const CostTblEntry AVX512VPOPCNTDQCostTbl[] = { 2830 { ISD::CTPOP, MVT::v8i64, 1 }, 2831 { ISD::CTPOP, MVT::v16i32, 1 }, 2832 { ISD::CTPOP, MVT::v4i64, 1 }, 2833 { ISD::CTPOP, MVT::v8i32, 1 }, 2834 { ISD::CTPOP, MVT::v2i64, 1 }, 2835 { ISD::CTPOP, MVT::v4i32, 1 }, 2836 }; 2837 static const CostTblEntry AVX512CDCostTbl[] = { 2838 { ISD::CTLZ, MVT::v8i64, 1 }, 2839 { ISD::CTLZ, MVT::v16i32, 1 }, 2840 { ISD::CTLZ, MVT::v32i16, 8 }, 2841 { ISD::CTLZ, MVT::v64i8, 20 }, 2842 { ISD::CTLZ, MVT::v4i64, 1 }, 2843 { ISD::CTLZ, MVT::v8i32, 1 }, 2844 { ISD::CTLZ, MVT::v16i16, 4 }, 2845 { ISD::CTLZ, MVT::v32i8, 10 }, 2846 { ISD::CTLZ, MVT::v2i64, 1 }, 2847 { ISD::CTLZ, MVT::v4i32, 1 }, 2848 { ISD::CTLZ, MVT::v8i16, 4 }, 2849 { ISD::CTLZ, MVT::v16i8, 4 }, 2850 }; 2851 static const CostTblEntry AVX512BWCostTbl[] = { 2852 { ISD::ABS, MVT::v32i16, 1 }, 2853 { ISD::ABS, MVT::v64i8, 1 }, 2854 { ISD::BITREVERSE, MVT::v8i64, 3 }, 2855 { ISD::BITREVERSE, MVT::v16i32, 3 }, 2856 { ISD::BITREVERSE, MVT::v32i16, 3 }, 2857 { ISD::BITREVERSE, MVT::v64i8, 2 }, 2858 { ISD::BSWAP, MVT::v8i64, 1 }, 2859 { ISD::BSWAP, MVT::v16i32, 1 }, 2860 { ISD::BSWAP, MVT::v32i16, 1 }, 2861 { ISD::CTLZ, MVT::v8i64, 23 }, 2862 { ISD::CTLZ, MVT::v16i32, 22 }, 2863 { ISD::CTLZ, MVT::v32i16, 18 }, 2864 { ISD::CTLZ, MVT::v64i8, 17 }, 2865 { ISD::CTPOP, MVT::v8i64, 7 }, 2866 { ISD::CTPOP, MVT::v16i32, 11 }, 2867 { ISD::CTPOP, MVT::v32i16, 9 }, 2868 { ISD::CTPOP, MVT::v64i8, 6 }, 2869 { ISD::CTTZ, MVT::v8i64, 10 }, 2870 { ISD::CTTZ, MVT::v16i32, 14 }, 2871 { ISD::CTTZ, MVT::v32i16, 12 }, 2872 { ISD::CTTZ, MVT::v64i8, 9 }, 2873 { ISD::SADDSAT, MVT::v32i16, 1 }, 2874 { ISD::SADDSAT, MVT::v64i8, 1 }, 2875 { ISD::SMAX, MVT::v32i16, 1 }, 2876 { ISD::SMAX, MVT::v64i8, 1 }, 2877 { ISD::SMIN, MVT::v32i16, 1 }, 2878 { ISD::SMIN, MVT::v64i8, 1 }, 2879 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2880 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2881 { ISD::UADDSAT, MVT::v32i16, 1 }, 2882 { ISD::UADDSAT, MVT::v64i8, 1 }, 2883 { ISD::UMAX, MVT::v32i16, 1 }, 2884 { ISD::UMAX, MVT::v64i8, 1 }, 2885 { ISD::UMIN, MVT::v32i16, 1 }, 2886 { ISD::UMIN, MVT::v64i8, 1 }, 2887 { ISD::USUBSAT, MVT::v32i16, 1 }, 2888 { ISD::USUBSAT, MVT::v64i8, 1 }, 2889 }; 2890 static const CostTblEntry AVX512CostTbl[] = { 2891 { ISD::ABS, MVT::v8i64, 1 }, 2892 { ISD::ABS, MVT::v16i32, 1 }, 2893 { ISD::ABS, MVT::v32i16, 2 }, 2894 { ISD::ABS, MVT::v64i8, 2 }, 2895 { ISD::ABS, MVT::v4i64, 1 }, 2896 { ISD::ABS, MVT::v2i64, 1 }, 2897 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2898 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2899 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2900 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2901 { ISD::BSWAP, MVT::v8i64, 4 }, 2902 { ISD::BSWAP, MVT::v16i32, 4 }, 2903 { ISD::BSWAP, MVT::v32i16, 4 }, 2904 { ISD::CTLZ, MVT::v8i64, 29 }, 2905 { ISD::CTLZ, MVT::v16i32, 35 }, 2906 { ISD::CTLZ, MVT::v32i16, 28 }, 2907 { ISD::CTLZ, MVT::v64i8, 18 }, 2908 { ISD::CTPOP, MVT::v8i64, 16 }, 2909 { ISD::CTPOP, MVT::v16i32, 24 }, 2910 { ISD::CTPOP, MVT::v32i16, 18 }, 2911 { ISD::CTPOP, MVT::v64i8, 12 }, 2912 { ISD::CTTZ, MVT::v8i64, 20 }, 2913 { ISD::CTTZ, MVT::v16i32, 28 }, 2914 { ISD::CTTZ, MVT::v32i16, 24 }, 2915 { ISD::CTTZ, MVT::v64i8, 18 }, 2916 { ISD::SMAX, MVT::v8i64, 1 }, 2917 { ISD::SMAX, MVT::v16i32, 1 }, 2918 { ISD::SMAX, MVT::v32i16, 2 }, 2919 { ISD::SMAX, MVT::v64i8, 2 }, 2920 { ISD::SMAX, MVT::v4i64, 1 }, 2921 { ISD::SMAX, MVT::v2i64, 1 }, 2922 { ISD::SMIN, MVT::v8i64, 1 }, 2923 { ISD::SMIN, MVT::v16i32, 1 }, 2924 { ISD::SMIN, MVT::v32i16, 2 }, 2925 { ISD::SMIN, MVT::v64i8, 2 }, 2926 { ISD::SMIN, MVT::v4i64, 1 }, 2927 { ISD::SMIN, MVT::v2i64, 1 }, 2928 { ISD::UMAX, MVT::v8i64, 1 }, 2929 { ISD::UMAX, MVT::v16i32, 1 }, 2930 { ISD::UMAX, MVT::v32i16, 2 }, 2931 { ISD::UMAX, MVT::v64i8, 2 }, 2932 { ISD::UMAX, MVT::v4i64, 1 }, 2933 { ISD::UMAX, MVT::v2i64, 1 }, 2934 { ISD::UMIN, MVT::v8i64, 1 }, 2935 { ISD::UMIN, MVT::v16i32, 1 }, 2936 { ISD::UMIN, MVT::v32i16, 2 }, 2937 { ISD::UMIN, MVT::v64i8, 2 }, 2938 { ISD::UMIN, MVT::v4i64, 1 }, 2939 { ISD::UMIN, MVT::v2i64, 1 }, 2940 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2941 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2942 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2943 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2944 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2945 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2946 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2947 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2948 { ISD::SADDSAT, MVT::v32i16, 2 }, 2949 { ISD::SADDSAT, MVT::v64i8, 2 }, 2950 { ISD::SSUBSAT, MVT::v32i16, 2 }, 2951 { ISD::SSUBSAT, MVT::v64i8, 2 }, 2952 { ISD::UADDSAT, MVT::v32i16, 2 }, 2953 { ISD::UADDSAT, MVT::v64i8, 2 }, 2954 { ISD::USUBSAT, MVT::v32i16, 2 }, 2955 { ISD::USUBSAT, MVT::v64i8, 2 }, 2956 { ISD::FMAXNUM, MVT::f32, 2 }, 2957 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2958 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2959 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2960 { ISD::FMAXNUM, MVT::f64, 2 }, 2961 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2962 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2963 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2964 }; 2965 static const CostTblEntry XOPCostTbl[] = { 2966 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2967 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2968 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2969 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2970 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2971 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2972 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2973 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2974 { ISD::BITREVERSE, MVT::i64, 3 }, 2975 { ISD::BITREVERSE, MVT::i32, 3 }, 2976 { ISD::BITREVERSE, MVT::i16, 3 }, 2977 { ISD::BITREVERSE, MVT::i8, 3 } 2978 }; 2979 static const CostTblEntry AVX2CostTbl[] = { 2980 { ISD::ABS, MVT::v4i64, 2 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2981 { ISD::ABS, MVT::v8i32, 1 }, 2982 { ISD::ABS, MVT::v16i16, 1 }, 2983 { ISD::ABS, MVT::v32i8, 1 }, 2984 { ISD::BITREVERSE, MVT::v2i64, 3 }, 2985 { ISD::BITREVERSE, MVT::v4i64, 3 }, 2986 { ISD::BITREVERSE, MVT::v4i32, 3 }, 2987 { ISD::BITREVERSE, MVT::v8i32, 3 }, 2988 { ISD::BITREVERSE, MVT::v8i16, 3 }, 2989 { ISD::BITREVERSE, MVT::v16i16, 3 }, 2990 { ISD::BITREVERSE, MVT::v16i8, 3 }, 2991 { ISD::BITREVERSE, MVT::v32i8, 3 }, 2992 { ISD::BSWAP, MVT::v4i64, 1 }, 2993 { ISD::BSWAP, MVT::v8i32, 1 }, 2994 { ISD::BSWAP, MVT::v16i16, 1 }, 2995 { ISD::CTLZ, MVT::v2i64, 7 }, 2996 { ISD::CTLZ, MVT::v4i64, 7 }, 2997 { ISD::CTLZ, MVT::v4i32, 5 }, 2998 { ISD::CTLZ, MVT::v8i32, 5 }, 2999 { ISD::CTLZ, MVT::v8i16, 4 }, 3000 { ISD::CTLZ, MVT::v16i16, 4 }, 3001 { ISD::CTLZ, MVT::v16i8, 3 }, 3002 { ISD::CTLZ, MVT::v32i8, 3 }, 3003 { ISD::CTPOP, MVT::v2i64, 3 }, 3004 { ISD::CTPOP, MVT::v4i64, 3 }, 3005 { ISD::CTPOP, MVT::v4i32, 7 }, 3006 { ISD::CTPOP, MVT::v8i32, 7 }, 3007 { ISD::CTPOP, MVT::v8i16, 3 }, 3008 { ISD::CTPOP, MVT::v16i16, 3 }, 3009 { ISD::CTPOP, MVT::v16i8, 2 }, 3010 { ISD::CTPOP, MVT::v32i8, 2 }, 3011 { ISD::CTTZ, MVT::v2i64, 4 }, 3012 { ISD::CTTZ, MVT::v4i64, 4 }, 3013 { ISD::CTTZ, MVT::v4i32, 7 }, 3014 { ISD::CTTZ, MVT::v8i32, 7 }, 3015 { ISD::CTTZ, MVT::v8i16, 4 }, 3016 { ISD::CTTZ, MVT::v16i16, 4 }, 3017 { ISD::CTTZ, MVT::v16i8, 3 }, 3018 { ISD::CTTZ, MVT::v32i8, 3 }, 3019 { ISD::SADDSAT, MVT::v16i16, 1 }, 3020 { ISD::SADDSAT, MVT::v32i8, 1 }, 3021 { ISD::SMAX, MVT::v8i32, 1 }, 3022 { ISD::SMAX, MVT::v16i16, 1 }, 3023 { ISD::SMAX, MVT::v32i8, 1 }, 3024 { ISD::SMIN, MVT::v8i32, 1 }, 3025 { ISD::SMIN, MVT::v16i16, 1 }, 3026 { ISD::SMIN, MVT::v32i8, 1 }, 3027 { ISD::SSUBSAT, MVT::v16i16, 1 }, 3028 { ISD::SSUBSAT, MVT::v32i8, 1 }, 3029 { ISD::UADDSAT, MVT::v16i16, 1 }, 3030 { ISD::UADDSAT, MVT::v32i8, 1 }, 3031 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 3032 { ISD::UMAX, MVT::v8i32, 1 }, 3033 { ISD::UMAX, MVT::v16i16, 1 }, 3034 { ISD::UMAX, MVT::v32i8, 1 }, 3035 { ISD::UMIN, MVT::v8i32, 1 }, 3036 { ISD::UMIN, MVT::v16i16, 1 }, 3037 { ISD::UMIN, MVT::v32i8, 1 }, 3038 { ISD::USUBSAT, MVT::v16i16, 1 }, 3039 { ISD::USUBSAT, MVT::v32i8, 1 }, 3040 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 3041 { ISD::FMAXNUM, MVT::v8f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 3042 { ISD::FMAXNUM, MVT::v4f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 3043 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 3044 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 3045 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 3046 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 3047 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 3048 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 3049 }; 3050 static const CostTblEntry AVX1CostTbl[] = { 3051 { ISD::ABS, MVT::v4i64, 5 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 3052 { ISD::ABS, MVT::v8i32, 3 }, 3053 { ISD::ABS, MVT::v16i16, 3 }, 3054 { ISD::ABS, MVT::v32i8, 3 }, 3055 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 3056 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 3057 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 3058 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 3059 { ISD::BSWAP, MVT::v4i64, 4 }, 3060 { ISD::BSWAP, MVT::v8i32, 4 }, 3061 { ISD::BSWAP, MVT::v16i16, 4 }, 3062 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 3063 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 3064 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 3065 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 3066 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 3067 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 3068 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 3069 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 3070 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 3071 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 3072 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 3073 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 3074 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3075 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3076 { ISD::SMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3077 { ISD::SMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3078 { ISD::SMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3079 { ISD::SMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3080 { ISD::SMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3081 { ISD::SMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3082 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3083 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3084 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3085 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3086 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 3087 { ISD::UMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3088 { ISD::UMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3089 { ISD::UMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3090 { ISD::UMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3091 { ISD::UMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3092 { ISD::UMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3093 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3094 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3095 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 3096 { ISD::FMAXNUM, MVT::f32, 3 }, // MAXSS + CMPUNORDSS + BLENDVPS 3097 { ISD::FMAXNUM, MVT::v4f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 3098 { ISD::FMAXNUM, MVT::v8f32, 5 }, // MAXPS + CMPUNORDPS + BLENDVPS + ? 3099 { ISD::FMAXNUM, MVT::f64, 3 }, // MAXSD + CMPUNORDSD + BLENDVPD 3100 { ISD::FMAXNUM, MVT::v2f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 3101 { ISD::FMAXNUM, MVT::v4f64, 5 }, // MAXPD + CMPUNORDPD + BLENDVPD + ? 3102 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 3103 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 3104 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 3105 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 3106 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 3107 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 3108 }; 3109 static const CostTblEntry GLMCostTbl[] = { 3110 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 3111 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 3112 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 3113 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 3114 }; 3115 static const CostTblEntry SLMCostTbl[] = { 3116 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 3117 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 3118 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 3119 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 3120 }; 3121 static const CostTblEntry SSE42CostTbl[] = { 3122 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 3123 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 3124 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 3125 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 3126 }; 3127 static const CostTblEntry SSE41CostTbl[] = { 3128 { ISD::ABS, MVT::v2i64, 2 }, // BLENDVPD(X,PSUBQ(0,X),X) 3129 { ISD::SMAX, MVT::v4i32, 1 }, 3130 { ISD::SMAX, MVT::v16i8, 1 }, 3131 { ISD::SMIN, MVT::v4i32, 1 }, 3132 { ISD::SMIN, MVT::v16i8, 1 }, 3133 { ISD::UMAX, MVT::v4i32, 1 }, 3134 { ISD::UMAX, MVT::v8i16, 1 }, 3135 { ISD::UMIN, MVT::v4i32, 1 }, 3136 { ISD::UMIN, MVT::v8i16, 1 }, 3137 }; 3138 static const CostTblEntry SSSE3CostTbl[] = { 3139 { ISD::ABS, MVT::v4i32, 1 }, 3140 { ISD::ABS, MVT::v8i16, 1 }, 3141 { ISD::ABS, MVT::v16i8, 1 }, 3142 { ISD::BITREVERSE, MVT::v2i64, 5 }, 3143 { ISD::BITREVERSE, MVT::v4i32, 5 }, 3144 { ISD::BITREVERSE, MVT::v8i16, 5 }, 3145 { ISD::BITREVERSE, MVT::v16i8, 5 }, 3146 { ISD::BSWAP, MVT::v2i64, 1 }, 3147 { ISD::BSWAP, MVT::v4i32, 1 }, 3148 { ISD::BSWAP, MVT::v8i16, 1 }, 3149 { ISD::CTLZ, MVT::v2i64, 23 }, 3150 { ISD::CTLZ, MVT::v4i32, 18 }, 3151 { ISD::CTLZ, MVT::v8i16, 14 }, 3152 { ISD::CTLZ, MVT::v16i8, 9 }, 3153 { ISD::CTPOP, MVT::v2i64, 7 }, 3154 { ISD::CTPOP, MVT::v4i32, 11 }, 3155 { ISD::CTPOP, MVT::v8i16, 9 }, 3156 { ISD::CTPOP, MVT::v16i8, 6 }, 3157 { ISD::CTTZ, MVT::v2i64, 10 }, 3158 { ISD::CTTZ, MVT::v4i32, 14 }, 3159 { ISD::CTTZ, MVT::v8i16, 12 }, 3160 { ISD::CTTZ, MVT::v16i8, 9 } 3161 }; 3162 static const CostTblEntry SSE2CostTbl[] = { 3163 { ISD::ABS, MVT::v2i64, 4 }, 3164 { ISD::ABS, MVT::v4i32, 3 }, 3165 { ISD::ABS, MVT::v8i16, 2 }, 3166 { ISD::ABS, MVT::v16i8, 2 }, 3167 { ISD::BITREVERSE, MVT::v2i64, 29 }, 3168 { ISD::BITREVERSE, MVT::v4i32, 27 }, 3169 { ISD::BITREVERSE, MVT::v8i16, 27 }, 3170 { ISD::BITREVERSE, MVT::v16i8, 20 }, 3171 { ISD::BSWAP, MVT::v2i64, 7 }, 3172 { ISD::BSWAP, MVT::v4i32, 7 }, 3173 { ISD::BSWAP, MVT::v8i16, 7 }, 3174 { ISD::CTLZ, MVT::v2i64, 25 }, 3175 { ISD::CTLZ, MVT::v4i32, 26 }, 3176 { ISD::CTLZ, MVT::v8i16, 20 }, 3177 { ISD::CTLZ, MVT::v16i8, 17 }, 3178 { ISD::CTPOP, MVT::v2i64, 12 }, 3179 { ISD::CTPOP, MVT::v4i32, 15 }, 3180 { ISD::CTPOP, MVT::v8i16, 13 }, 3181 { ISD::CTPOP, MVT::v16i8, 10 }, 3182 { ISD::CTTZ, MVT::v2i64, 14 }, 3183 { ISD::CTTZ, MVT::v4i32, 18 }, 3184 { ISD::CTTZ, MVT::v8i16, 16 }, 3185 { ISD::CTTZ, MVT::v16i8, 13 }, 3186 { ISD::SADDSAT, MVT::v8i16, 1 }, 3187 { ISD::SADDSAT, MVT::v16i8, 1 }, 3188 { ISD::SMAX, MVT::v8i16, 1 }, 3189 { ISD::SMIN, MVT::v8i16, 1 }, 3190 { ISD::SSUBSAT, MVT::v8i16, 1 }, 3191 { ISD::SSUBSAT, MVT::v16i8, 1 }, 3192 { ISD::UADDSAT, MVT::v8i16, 1 }, 3193 { ISD::UADDSAT, MVT::v16i8, 1 }, 3194 { ISD::UMAX, MVT::v8i16, 2 }, 3195 { ISD::UMAX, MVT::v16i8, 1 }, 3196 { ISD::UMIN, MVT::v8i16, 2 }, 3197 { ISD::UMIN, MVT::v16i8, 1 }, 3198 { ISD::USUBSAT, MVT::v8i16, 1 }, 3199 { ISD::USUBSAT, MVT::v16i8, 1 }, 3200 { ISD::FMAXNUM, MVT::f64, 4 }, 3201 { ISD::FMAXNUM, MVT::v2f64, 4 }, 3202 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 3203 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 3204 }; 3205 static const CostTblEntry SSE1CostTbl[] = { 3206 { ISD::FMAXNUM, MVT::f32, 4 }, 3207 { ISD::FMAXNUM, MVT::v4f32, 4 }, 3208 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 3209 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 3210 }; 3211 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 3212 { ISD::CTTZ, MVT::i64, 1 }, 3213 }; 3214 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 3215 { ISD::CTTZ, MVT::i32, 1 }, 3216 { ISD::CTTZ, MVT::i16, 1 }, 3217 { ISD::CTTZ, MVT::i8, 1 }, 3218 }; 3219 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 3220 { ISD::CTLZ, MVT::i64, 1 }, 3221 }; 3222 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 3223 { ISD::CTLZ, MVT::i32, 1 }, 3224 { ISD::CTLZ, MVT::i16, 1 }, 3225 { ISD::CTLZ, MVT::i8, 1 }, 3226 }; 3227 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 3228 { ISD::CTPOP, MVT::i64, 1 }, 3229 }; 3230 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 3231 { ISD::CTPOP, MVT::i32, 1 }, 3232 { ISD::CTPOP, MVT::i16, 1 }, 3233 { ISD::CTPOP, MVT::i8, 1 }, 3234 }; 3235 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 3236 { ISD::ABS, MVT::i64, 2 }, // SUB+CMOV 3237 { ISD::BITREVERSE, MVT::i64, 14 }, 3238 { ISD::BSWAP, MVT::i64, 1 }, 3239 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 3240 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 3241 { ISD::CTPOP, MVT::i64, 10 }, 3242 { ISD::SADDO, MVT::i64, 1 }, 3243 { ISD::UADDO, MVT::i64, 1 }, 3244 { ISD::UMULO, MVT::i64, 2 }, // mulq + seto 3245 }; 3246 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 3247 { ISD::ABS, MVT::i32, 2 }, // SUB+CMOV 3248 { ISD::ABS, MVT::i16, 2 }, // SUB+CMOV 3249 { ISD::BITREVERSE, MVT::i32, 14 }, 3250 { ISD::BITREVERSE, MVT::i16, 14 }, 3251 { ISD::BITREVERSE, MVT::i8, 11 }, 3252 { ISD::BSWAP, MVT::i32, 1 }, 3253 { ISD::BSWAP, MVT::i16, 1 }, // ROL 3254 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 3255 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 3256 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 3257 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 3258 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 3259 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 3260 { ISD::CTPOP, MVT::i32, 8 }, 3261 { ISD::CTPOP, MVT::i16, 9 }, 3262 { ISD::CTPOP, MVT::i8, 7 }, 3263 { ISD::SADDO, MVT::i32, 1 }, 3264 { ISD::SADDO, MVT::i16, 1 }, 3265 { ISD::SADDO, MVT::i8, 1 }, 3266 { ISD::UADDO, MVT::i32, 1 }, 3267 { ISD::UADDO, MVT::i16, 1 }, 3268 { ISD::UADDO, MVT::i8, 1 }, 3269 { ISD::UMULO, MVT::i32, 2 }, // mul + seto 3270 { ISD::UMULO, MVT::i16, 2 }, 3271 { ISD::UMULO, MVT::i8, 2 }, 3272 }; 3273 3274 Type *RetTy = ICA.getReturnType(); 3275 Type *OpTy = RetTy; 3276 Intrinsic::ID IID = ICA.getID(); 3277 unsigned ISD = ISD::DELETED_NODE; 3278 switch (IID) { 3279 default: 3280 break; 3281 case Intrinsic::abs: 3282 ISD = ISD::ABS; 3283 break; 3284 case Intrinsic::bitreverse: 3285 ISD = ISD::BITREVERSE; 3286 break; 3287 case Intrinsic::bswap: 3288 ISD = ISD::BSWAP; 3289 break; 3290 case Intrinsic::ctlz: 3291 ISD = ISD::CTLZ; 3292 break; 3293 case Intrinsic::ctpop: 3294 ISD = ISD::CTPOP; 3295 break; 3296 case Intrinsic::cttz: 3297 ISD = ISD::CTTZ; 3298 break; 3299 case Intrinsic::maxnum: 3300 case Intrinsic::minnum: 3301 // FMINNUM has same costs so don't duplicate. 3302 ISD = ISD::FMAXNUM; 3303 break; 3304 case Intrinsic::sadd_sat: 3305 ISD = ISD::SADDSAT; 3306 break; 3307 case Intrinsic::smax: 3308 ISD = ISD::SMAX; 3309 break; 3310 case Intrinsic::smin: 3311 ISD = ISD::SMIN; 3312 break; 3313 case Intrinsic::ssub_sat: 3314 ISD = ISD::SSUBSAT; 3315 break; 3316 case Intrinsic::uadd_sat: 3317 ISD = ISD::UADDSAT; 3318 break; 3319 case Intrinsic::umax: 3320 ISD = ISD::UMAX; 3321 break; 3322 case Intrinsic::umin: 3323 ISD = ISD::UMIN; 3324 break; 3325 case Intrinsic::usub_sat: 3326 ISD = ISD::USUBSAT; 3327 break; 3328 case Intrinsic::sqrt: 3329 ISD = ISD::FSQRT; 3330 break; 3331 case Intrinsic::sadd_with_overflow: 3332 case Intrinsic::ssub_with_overflow: 3333 // SSUBO has same costs so don't duplicate. 3334 ISD = ISD::SADDO; 3335 OpTy = RetTy->getContainedType(0); 3336 break; 3337 case Intrinsic::uadd_with_overflow: 3338 case Intrinsic::usub_with_overflow: 3339 // USUBO has same costs so don't duplicate. 3340 ISD = ISD::UADDO; 3341 OpTy = RetTy->getContainedType(0); 3342 break; 3343 case Intrinsic::umul_with_overflow: 3344 case Intrinsic::smul_with_overflow: 3345 // SMULO has same costs so don't duplicate. 3346 ISD = ISD::UMULO; 3347 OpTy = RetTy->getContainedType(0); 3348 break; 3349 } 3350 3351 if (ISD != ISD::DELETED_NODE) { 3352 // Legalize the type. 3353 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 3354 MVT MTy = LT.second; 3355 3356 // Attempt to lookup cost. 3357 if (ISD == ISD::BITREVERSE && ST->hasGFNI() && ST->hasSSSE3() && 3358 MTy.isVector()) { 3359 // With PSHUFB the code is very similar for all types. If we have integer 3360 // byte operations, we just need a GF2P8AFFINEQB for vXi8. For other types 3361 // we also need a PSHUFB. 3362 unsigned Cost = MTy.getVectorElementType() == MVT::i8 ? 1 : 2; 3363 3364 // Without byte operations, we need twice as many GF2P8AFFINEQB and PSHUFB 3365 // instructions. We also need an extract and an insert. 3366 if (!(MTy.is128BitVector() || (ST->hasAVX2() && MTy.is256BitVector()) || 3367 (ST->hasBWI() && MTy.is512BitVector()))) 3368 Cost = Cost * 2 + 2; 3369 3370 return LT.first * Cost; 3371 } 3372 3373 auto adjustTableCost = [](const CostTblEntry &Entry, 3374 InstructionCost LegalizationCost, 3375 FastMathFlags FMF) { 3376 // If there are no NANs to deal with, then these are reduced to a 3377 // single MIN** or MAX** instruction instead of the MIN/CMP/SELECT that we 3378 // assume is used in the non-fast case. 3379 if (Entry.ISD == ISD::FMAXNUM || Entry.ISD == ISD::FMINNUM) { 3380 if (FMF.noNaNs()) 3381 return LegalizationCost * 1; 3382 } 3383 return LegalizationCost * (int)Entry.Cost; 3384 }; 3385 3386 if (ST->useGLMDivSqrtCosts()) 3387 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 3388 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3389 3390 if (ST->useSLMArithCosts()) 3391 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 3392 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3393 3394 if (ST->hasBITALG()) 3395 if (const auto *Entry = CostTableLookup(AVX512BITALGCostTbl, ISD, MTy)) 3396 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3397 3398 if (ST->hasVPOPCNTDQ()) 3399 if (const auto *Entry = CostTableLookup(AVX512VPOPCNTDQCostTbl, ISD, MTy)) 3400 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3401 3402 if (ST->hasCDI()) 3403 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 3404 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3405 3406 if (ST->hasBWI()) 3407 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3408 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3409 3410 if (ST->hasAVX512()) 3411 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3412 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3413 3414 if (ST->hasXOP()) 3415 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3416 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3417 3418 if (ST->hasAVX2()) 3419 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3420 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3421 3422 if (ST->hasAVX()) 3423 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3424 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3425 3426 if (ST->hasSSE42()) 3427 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3428 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3429 3430 if (ST->hasSSE41()) 3431 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3432 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3433 3434 if (ST->hasSSSE3()) 3435 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 3436 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3437 3438 if (ST->hasSSE2()) 3439 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3440 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3441 3442 if (ST->hasSSE1()) 3443 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3444 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3445 3446 if (ST->hasBMI()) { 3447 if (ST->is64Bit()) 3448 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 3449 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3450 3451 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 3452 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3453 } 3454 3455 if (ST->hasLZCNT()) { 3456 if (ST->is64Bit()) 3457 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 3458 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3459 3460 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 3461 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3462 } 3463 3464 if (ST->hasPOPCNT()) { 3465 if (ST->is64Bit()) 3466 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 3467 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3468 3469 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 3470 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3471 } 3472 3473 if (ISD == ISD::BSWAP && ST->hasMOVBE() && ST->hasFastMOVBE()) { 3474 if (const Instruction *II = ICA.getInst()) { 3475 if (II->hasOneUse() && isa<StoreInst>(II->user_back())) 3476 return TTI::TCC_Free; 3477 if (auto *LI = dyn_cast<LoadInst>(II->getOperand(0))) { 3478 if (LI->hasOneUse()) 3479 return TTI::TCC_Free; 3480 } 3481 } 3482 } 3483 3484 if (ST->is64Bit()) 3485 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3486 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3487 3488 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3489 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3490 } 3491 3492 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3493 } 3494 3495 InstructionCost 3496 X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 3497 TTI::TargetCostKind CostKind) { 3498 if (ICA.isTypeBasedOnly()) 3499 return getTypeBasedIntrinsicInstrCost(ICA, CostKind); 3500 3501 static const CostTblEntry AVX512BWCostTbl[] = { 3502 { ISD::ROTL, MVT::v32i16, 2 }, 3503 { ISD::ROTL, MVT::v16i16, 2 }, 3504 { ISD::ROTL, MVT::v8i16, 2 }, 3505 { ISD::ROTL, MVT::v64i8, 5 }, 3506 { ISD::ROTL, MVT::v32i8, 5 }, 3507 { ISD::ROTL, MVT::v16i8, 5 }, 3508 { ISD::ROTR, MVT::v32i16, 2 }, 3509 { ISD::ROTR, MVT::v16i16, 2 }, 3510 { ISD::ROTR, MVT::v8i16, 2 }, 3511 { ISD::ROTR, MVT::v64i8, 5 }, 3512 { ISD::ROTR, MVT::v32i8, 5 }, 3513 { ISD::ROTR, MVT::v16i8, 5 } 3514 }; 3515 static const CostTblEntry AVX512CostTbl[] = { 3516 { ISD::ROTL, MVT::v8i64, 1 }, 3517 { ISD::ROTL, MVT::v4i64, 1 }, 3518 { ISD::ROTL, MVT::v2i64, 1 }, 3519 { ISD::ROTL, MVT::v16i32, 1 }, 3520 { ISD::ROTL, MVT::v8i32, 1 }, 3521 { ISD::ROTL, MVT::v4i32, 1 }, 3522 { ISD::ROTR, MVT::v8i64, 1 }, 3523 { ISD::ROTR, MVT::v4i64, 1 }, 3524 { ISD::ROTR, MVT::v2i64, 1 }, 3525 { ISD::ROTR, MVT::v16i32, 1 }, 3526 { ISD::ROTR, MVT::v8i32, 1 }, 3527 { ISD::ROTR, MVT::v4i32, 1 } 3528 }; 3529 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 3530 static const CostTblEntry XOPCostTbl[] = { 3531 { ISD::ROTL, MVT::v4i64, 4 }, 3532 { ISD::ROTL, MVT::v8i32, 4 }, 3533 { ISD::ROTL, MVT::v16i16, 4 }, 3534 { ISD::ROTL, MVT::v32i8, 4 }, 3535 { ISD::ROTL, MVT::v2i64, 1 }, 3536 { ISD::ROTL, MVT::v4i32, 1 }, 3537 { ISD::ROTL, MVT::v8i16, 1 }, 3538 { ISD::ROTL, MVT::v16i8, 1 }, 3539 { ISD::ROTR, MVT::v4i64, 6 }, 3540 { ISD::ROTR, MVT::v8i32, 6 }, 3541 { ISD::ROTR, MVT::v16i16, 6 }, 3542 { ISD::ROTR, MVT::v32i8, 6 }, 3543 { ISD::ROTR, MVT::v2i64, 2 }, 3544 { ISD::ROTR, MVT::v4i32, 2 }, 3545 { ISD::ROTR, MVT::v8i16, 2 }, 3546 { ISD::ROTR, MVT::v16i8, 2 } 3547 }; 3548 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 3549 { ISD::ROTL, MVT::i64, 1 }, 3550 { ISD::ROTR, MVT::i64, 1 }, 3551 { ISD::FSHL, MVT::i64, 4 } 3552 }; 3553 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 3554 { ISD::ROTL, MVT::i32, 1 }, 3555 { ISD::ROTL, MVT::i16, 1 }, 3556 { ISD::ROTL, MVT::i8, 1 }, 3557 { ISD::ROTR, MVT::i32, 1 }, 3558 { ISD::ROTR, MVT::i16, 1 }, 3559 { ISD::ROTR, MVT::i8, 1 }, 3560 { ISD::FSHL, MVT::i32, 4 }, 3561 { ISD::FSHL, MVT::i16, 4 }, 3562 { ISD::FSHL, MVT::i8, 4 } 3563 }; 3564 3565 Intrinsic::ID IID = ICA.getID(); 3566 Type *RetTy = ICA.getReturnType(); 3567 const SmallVectorImpl<const Value *> &Args = ICA.getArgs(); 3568 unsigned ISD = ISD::DELETED_NODE; 3569 switch (IID) { 3570 default: 3571 break; 3572 case Intrinsic::fshl: 3573 ISD = ISD::FSHL; 3574 if (Args[0] == Args[1]) 3575 ISD = ISD::ROTL; 3576 break; 3577 case Intrinsic::fshr: 3578 // FSHR has same costs so don't duplicate. 3579 ISD = ISD::FSHL; 3580 if (Args[0] == Args[1]) 3581 ISD = ISD::ROTR; 3582 break; 3583 } 3584 3585 if (ISD != ISD::DELETED_NODE) { 3586 // Legalize the type. 3587 std::pair<InstructionCost, MVT> LT = 3588 TLI->getTypeLegalizationCost(DL, RetTy); 3589 MVT MTy = LT.second; 3590 3591 // Attempt to lookup cost. 3592 if (ST->hasBWI()) 3593 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3594 return LT.first * Entry->Cost; 3595 3596 if (ST->hasAVX512()) 3597 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3598 return LT.first * Entry->Cost; 3599 3600 if (ST->hasXOP()) 3601 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3602 return LT.first * Entry->Cost; 3603 3604 if (ST->is64Bit()) 3605 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3606 return LT.first * Entry->Cost; 3607 3608 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3609 return LT.first * Entry->Cost; 3610 } 3611 3612 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3613 } 3614 3615 InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, 3616 unsigned Index) { 3617 static const CostTblEntry SLMCostTbl[] = { 3618 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 3619 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 3620 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 3621 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 3622 }; 3623 3624 assert(Val->isVectorTy() && "This must be a vector type"); 3625 Type *ScalarType = Val->getScalarType(); 3626 int RegisterFileMoveCost = 0; 3627 3628 // Non-immediate extraction/insertion can be handled as a sequence of 3629 // aliased loads+stores via the stack. 3630 if (Index == -1U && (Opcode == Instruction::ExtractElement || 3631 Opcode == Instruction::InsertElement)) { 3632 // TODO: On some SSE41+ targets, we expand to cmp+splat+select patterns: 3633 // inselt N0, N1, N2 --> select (SplatN2 == {0,1,2...}) ? SplatN1 : N0. 3634 3635 // TODO: Move this to BasicTTIImpl.h? We'd need better gep + index handling. 3636 assert(isa<FixedVectorType>(Val) && "Fixed vector type expected"); 3637 Align VecAlign = DL.getPrefTypeAlign(Val); 3638 Align SclAlign = DL.getPrefTypeAlign(ScalarType); 3639 3640 // Extract - store vector to stack, load scalar. 3641 if (Opcode == Instruction::ExtractElement) { 3642 return getMemoryOpCost(Instruction::Store, Val, VecAlign, 0, 3643 TTI::TargetCostKind::TCK_RecipThroughput) + 3644 getMemoryOpCost(Instruction::Load, ScalarType, SclAlign, 0, 3645 TTI::TargetCostKind::TCK_RecipThroughput); 3646 } 3647 // Insert - store vector to stack, store scalar, load vector. 3648 if (Opcode == Instruction::InsertElement) { 3649 return getMemoryOpCost(Instruction::Store, Val, VecAlign, 0, 3650 TTI::TargetCostKind::TCK_RecipThroughput) + 3651 getMemoryOpCost(Instruction::Store, ScalarType, SclAlign, 0, 3652 TTI::TargetCostKind::TCK_RecipThroughput) + 3653 getMemoryOpCost(Instruction::Load, Val, VecAlign, 0, 3654 TTI::TargetCostKind::TCK_RecipThroughput); 3655 } 3656 } 3657 3658 if (Index != -1U && (Opcode == Instruction::ExtractElement || 3659 Opcode == Instruction::InsertElement)) { 3660 // Extraction of vXi1 elements are now efficiently handled by MOVMSK. 3661 if (Opcode == Instruction::ExtractElement && 3662 ScalarType->getScalarSizeInBits() == 1 && 3663 cast<FixedVectorType>(Val)->getNumElements() > 1) 3664 return 1; 3665 3666 // Legalize the type. 3667 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 3668 3669 // This type is legalized to a scalar type. 3670 if (!LT.second.isVector()) 3671 return 0; 3672 3673 // The type may be split. Normalize the index to the new type. 3674 unsigned SizeInBits = LT.second.getSizeInBits(); 3675 unsigned NumElts = LT.second.getVectorNumElements(); 3676 unsigned SubNumElts = NumElts; 3677 Index = Index % NumElts; 3678 3679 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 3680 // For inserts, we also need to insert the subvector back. 3681 if (SizeInBits > 128) { 3682 assert((SizeInBits % 128) == 0 && "Illegal vector"); 3683 unsigned NumSubVecs = SizeInBits / 128; 3684 SubNumElts = NumElts / NumSubVecs; 3685 if (SubNumElts <= Index) { 3686 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 3687 Index %= SubNumElts; 3688 } 3689 } 3690 3691 if (Index == 0) { 3692 // Floating point scalars are already located in index #0. 3693 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 3694 // true for all. 3695 if (ScalarType->isFloatingPointTy()) 3696 return RegisterFileMoveCost; 3697 3698 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 3699 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 3700 return 1 + RegisterFileMoveCost; 3701 } 3702 3703 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3704 assert(ISD && "Unexpected vector opcode"); 3705 MVT MScalarTy = LT.second.getScalarType(); 3706 if (ST->useSLMArithCosts()) 3707 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 3708 return Entry->Cost + RegisterFileMoveCost; 3709 3710 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 3711 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3712 (MScalarTy.isInteger() && ST->hasSSE41())) 3713 return 1 + RegisterFileMoveCost; 3714 3715 // Assume insertps is relatively cheap on all targets. 3716 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 3717 Opcode == Instruction::InsertElement) 3718 return 1 + RegisterFileMoveCost; 3719 3720 // For extractions we just need to shuffle the element to index 0, which 3721 // should be very cheap (assume cost = 1). For insertions we need to shuffle 3722 // the elements to its destination. In both cases we must handle the 3723 // subvector move(s). 3724 // If the vector type is already less than 128-bits then don't reduce it. 3725 // TODO: Under what circumstances should we shuffle using the full width? 3726 InstructionCost ShuffleCost = 1; 3727 if (Opcode == Instruction::InsertElement) { 3728 auto *SubTy = cast<VectorType>(Val); 3729 EVT VT = TLI->getValueType(DL, Val); 3730 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 3731 SubTy = FixedVectorType::get(ScalarType, SubNumElts); 3732 ShuffleCost = 3733 getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, None, 0, SubTy); 3734 } 3735 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 3736 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 3737 } 3738 3739 // Add to the base cost if we know that the extracted element of a vector is 3740 // destined to be moved to and used in the integer register file. 3741 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 3742 RegisterFileMoveCost += 1; 3743 3744 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 3745 } 3746 3747 InstructionCost X86TTIImpl::getScalarizationOverhead(VectorType *Ty, 3748 const APInt &DemandedElts, 3749 bool Insert, 3750 bool Extract) { 3751 InstructionCost Cost = 0; 3752 3753 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much 3754 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT. 3755 if (Insert) { 3756 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3757 MVT MScalarTy = LT.second.getScalarType(); 3758 unsigned SizeInBits = LT.second.getSizeInBits(); 3759 3760 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3761 (MScalarTy.isInteger() && ST->hasSSE41()) || 3762 (MScalarTy == MVT::f32 && ST->hasSSE41())) { 3763 // For types we can insert directly, insertion into 128-bit sub vectors is 3764 // cheap, followed by a cheap chain of concatenations. 3765 if (SizeInBits <= 128) { 3766 Cost += 3767 BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, false); 3768 } else { 3769 // In each 128-lane, if at least one index is demanded but not all 3770 // indices are demanded and this 128-lane is not the first 128-lane of 3771 // the legalized-vector, then this 128-lane needs a extracti128; If in 3772 // each 128-lane, there is at least one demanded index, this 128-lane 3773 // needs a inserti128. 3774 3775 // The following cases will help you build a better understanding: 3776 // Assume we insert several elements into a v8i32 vector in avx2, 3777 // Case#1: inserting into 1th index needs vpinsrd + inserti128. 3778 // Case#2: inserting into 5th index needs extracti128 + vpinsrd + 3779 // inserti128. 3780 // Case#3: inserting into 4,5,6,7 index needs 4*vpinsrd + inserti128. 3781 const int CostValue = *LT.first.getValue(); 3782 assert(CostValue >= 0 && "Negative cost!"); 3783 unsigned Num128Lanes = SizeInBits / 128 * CostValue; 3784 unsigned NumElts = LT.second.getVectorNumElements() * CostValue; 3785 APInt WidenedDemandedElts = DemandedElts.zextOrSelf(NumElts); 3786 unsigned Scale = NumElts / Num128Lanes; 3787 // We iterate each 128-lane, and check if we need a 3788 // extracti128/inserti128 for this 128-lane. 3789 for (unsigned I = 0; I < NumElts; I += Scale) { 3790 APInt Mask = WidenedDemandedElts.getBitsSet(NumElts, I, I + Scale); 3791 APInt MaskedDE = Mask & WidenedDemandedElts; 3792 unsigned Population = MaskedDE.countPopulation(); 3793 Cost += (Population > 0 && Population != Scale && 3794 I % LT.second.getVectorNumElements() != 0); 3795 Cost += Population > 0; 3796 } 3797 Cost += DemandedElts.countPopulation(); 3798 3799 // For vXf32 cases, insertion into the 0'th index in each v4f32 3800 // 128-bit vector is free. 3801 // NOTE: This assumes legalization widens vXf32 vectors. 3802 if (MScalarTy == MVT::f32) 3803 for (unsigned i = 0, e = cast<FixedVectorType>(Ty)->getNumElements(); 3804 i < e; i += 4) 3805 if (DemandedElts[i]) 3806 Cost--; 3807 } 3808 } else if (LT.second.isVector()) { 3809 // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded 3810 // integer element as a SCALAR_TO_VECTOR, then we build the vector as a 3811 // series of UNPCK followed by CONCAT_VECTORS - all of these can be 3812 // considered cheap. 3813 if (Ty->isIntOrIntVectorTy()) 3814 Cost += DemandedElts.countPopulation(); 3815 3816 // Get the smaller of the legalized or original pow2-extended number of 3817 // vector elements, which represents the number of unpacks we'll end up 3818 // performing. 3819 unsigned NumElts = LT.second.getVectorNumElements(); 3820 unsigned Pow2Elts = 3821 PowerOf2Ceil(cast<FixedVectorType>(Ty)->getNumElements()); 3822 Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first; 3823 } 3824 } 3825 3826 // TODO: Use default extraction for now, but we should investigate extending this 3827 // to handle repeated subvector extraction. 3828 if (Extract) 3829 Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, false, Extract); 3830 3831 return Cost; 3832 } 3833 3834 InstructionCost 3835 X86TTIImpl::getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, 3836 int VF, const APInt &DemandedDstElts, 3837 TTI::TargetCostKind CostKind) { 3838 const unsigned EltTyBits = DL.getTypeSizeInBits(EltTy); 3839 // We don't differentiate element types here, only element bit width. 3840 EltTy = IntegerType::getIntNTy(EltTy->getContext(), EltTyBits); 3841 3842 auto bailout = [&]() { 3843 return BaseT::getReplicationShuffleCost(EltTy, ReplicationFactor, VF, 3844 DemandedDstElts, CostKind); 3845 }; 3846 3847 // For now, only deal with AVX512 cases. 3848 if (!ST->hasAVX512()) 3849 return bailout(); 3850 3851 // Do we have a native shuffle for this element type, or should we promote? 3852 unsigned PromEltTyBits = EltTyBits; 3853 switch (EltTyBits) { 3854 case 32: 3855 case 64: 3856 break; // AVX512F. 3857 case 16: 3858 if (!ST->hasBWI()) 3859 PromEltTyBits = 32; // promote to i32, AVX512F. 3860 break; // AVX512BW 3861 case 8: 3862 if (!ST->hasVBMI()) 3863 PromEltTyBits = 32; // promote to i32, AVX512F. 3864 break; // AVX512VBMI 3865 case 1: 3866 // There is no support for shuffling i1 elements. We *must* promote. 3867 if (ST->hasBWI()) { 3868 if (ST->hasVBMI()) 3869 PromEltTyBits = 8; // promote to i8, AVX512VBMI. 3870 else 3871 PromEltTyBits = 16; // promote to i16, AVX512BW. 3872 break; 3873 } 3874 if (ST->hasDQI()) { 3875 PromEltTyBits = 32; // promote to i32, AVX512F. 3876 break; 3877 } 3878 return bailout(); 3879 default: 3880 return bailout(); 3881 } 3882 auto *PromEltTy = IntegerType::getIntNTy(EltTy->getContext(), PromEltTyBits); 3883 3884 auto *SrcVecTy = FixedVectorType::get(EltTy, VF); 3885 auto *PromSrcVecTy = FixedVectorType::get(PromEltTy, VF); 3886 3887 int NumDstElements = VF * ReplicationFactor; 3888 auto *PromDstVecTy = FixedVectorType::get(PromEltTy, NumDstElements); 3889 auto *DstVecTy = FixedVectorType::get(EltTy, NumDstElements); 3890 3891 // Legalize the types. 3892 MVT LegalSrcVecTy = TLI->getTypeLegalizationCost(DL, SrcVecTy).second; 3893 MVT LegalPromSrcVecTy = TLI->getTypeLegalizationCost(DL, PromSrcVecTy).second; 3894 MVT LegalPromDstVecTy = TLI->getTypeLegalizationCost(DL, PromDstVecTy).second; 3895 MVT LegalDstVecTy = TLI->getTypeLegalizationCost(DL, DstVecTy).second; 3896 // They should have legalized into vector types. 3897 if (!LegalSrcVecTy.isVector() || !LegalPromSrcVecTy.isVector() || 3898 !LegalPromDstVecTy.isVector() || !LegalDstVecTy.isVector()) 3899 return bailout(); 3900 3901 if (PromEltTyBits != EltTyBits) { 3902 // If we have to perform the shuffle with wider elt type than our data type, 3903 // then we will first need to anyext (we don't care about the new bits) 3904 // the source elements, and then truncate Dst elements. 3905 InstructionCost PromotionCost; 3906 PromotionCost += getCastInstrCost( 3907 Instruction::SExt, /*Dst=*/PromSrcVecTy, /*Src=*/SrcVecTy, 3908 TargetTransformInfo::CastContextHint::None, CostKind); 3909 PromotionCost += 3910 getCastInstrCost(Instruction::Trunc, /*Dst=*/DstVecTy, 3911 /*Src=*/PromDstVecTy, 3912 TargetTransformInfo::CastContextHint::None, CostKind); 3913 return PromotionCost + getReplicationShuffleCost(PromEltTy, 3914 ReplicationFactor, VF, 3915 DemandedDstElts, CostKind); 3916 } 3917 3918 assert(LegalSrcVecTy.getScalarSizeInBits() == EltTyBits && 3919 LegalSrcVecTy.getScalarType() == LegalDstVecTy.getScalarType() && 3920 "We expect that the legalization doesn't affect the element width, " 3921 "doesn't coalesce/split elements."); 3922 3923 unsigned NumEltsPerDstVec = LegalDstVecTy.getVectorNumElements(); 3924 unsigned NumDstVectors = 3925 divideCeil(DstVecTy->getNumElements(), NumEltsPerDstVec); 3926 3927 auto *SingleDstVecTy = FixedVectorType::get(EltTy, NumEltsPerDstVec); 3928 3929 // Not all the produced Dst elements may be demanded. In our case, 3930 // given that a single Dst vector is formed by a single shuffle, 3931 // if all elements that will form a single Dst vector aren't demanded, 3932 // then we won't need to do that shuffle, so adjust the cost accordingly. 3933 APInt DemandedDstVectors = APIntOps::ScaleBitMask( 3934 DemandedDstElts.zextOrSelf(NumDstVectors * NumEltsPerDstVec), 3935 NumDstVectors); 3936 unsigned NumDstVectorsDemanded = DemandedDstVectors.countPopulation(); 3937 3938 InstructionCost SingleShuffleCost = 3939 getShuffleCost(TTI::SK_PermuteSingleSrc, SingleDstVecTy, 3940 /*Mask=*/None, /*Index=*/0, /*SubTp=*/nullptr); 3941 return NumDstVectorsDemanded * SingleShuffleCost; 3942 } 3943 3944 InstructionCost X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 3945 MaybeAlign Alignment, 3946 unsigned AddressSpace, 3947 TTI::TargetCostKind CostKind, 3948 const Instruction *I) { 3949 // TODO: Handle other cost kinds. 3950 if (CostKind != TTI::TCK_RecipThroughput) { 3951 if (auto *SI = dyn_cast_or_null<StoreInst>(I)) { 3952 // Store instruction with index and scale costs 2 Uops. 3953 // Check the preceding GEP to identify non-const indices. 3954 if (auto *GEP = dyn_cast<GetElementPtrInst>(SI->getPointerOperand())) { 3955 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3956 return TTI::TCC_Basic * 2; 3957 } 3958 } 3959 return TTI::TCC_Basic; 3960 } 3961 3962 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 3963 "Invalid Opcode"); 3964 // Type legalization can't handle structs 3965 if (TLI->getValueType(DL, Src, true) == MVT::Other) 3966 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3967 CostKind); 3968 3969 // Legalize the type. 3970 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 3971 3972 auto *VTy = dyn_cast<FixedVectorType>(Src); 3973 3974 // Handle the simple case of non-vectors. 3975 // NOTE: this assumes that legalization never creates vector from scalars! 3976 if (!VTy || !LT.second.isVector()) 3977 // Each load/store unit costs 1. 3978 return LT.first * 1; 3979 3980 bool IsLoad = Opcode == Instruction::Load; 3981 3982 Type *EltTy = VTy->getElementType(); 3983 3984 const int EltTyBits = DL.getTypeSizeInBits(EltTy); 3985 3986 InstructionCost Cost = 0; 3987 3988 // Source of truth: how many elements were there in the original IR vector? 3989 const unsigned SrcNumElt = VTy->getNumElements(); 3990 3991 // How far have we gotten? 3992 int NumEltRemaining = SrcNumElt; 3993 // Note that we intentionally capture by-reference, NumEltRemaining changes. 3994 auto NumEltDone = [&]() { return SrcNumElt - NumEltRemaining; }; 3995 3996 const int MaxLegalOpSizeBytes = divideCeil(LT.second.getSizeInBits(), 8); 3997 3998 // Note that even if we can store 64 bits of an XMM, we still operate on XMM. 3999 const unsigned XMMBits = 128; 4000 if (XMMBits % EltTyBits != 0) 4001 // Vector size must be a multiple of the element size. I.e. no padding. 4002 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 4003 CostKind); 4004 const int NumEltPerXMM = XMMBits / EltTyBits; 4005 4006 auto *XMMVecTy = FixedVectorType::get(EltTy, NumEltPerXMM); 4007 4008 for (int CurrOpSizeBytes = MaxLegalOpSizeBytes, SubVecEltsLeft = 0; 4009 NumEltRemaining > 0; CurrOpSizeBytes /= 2) { 4010 // How many elements would a single op deal with at once? 4011 if ((8 * CurrOpSizeBytes) % EltTyBits != 0) 4012 // Vector size must be a multiple of the element size. I.e. no padding. 4013 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 4014 CostKind); 4015 int CurrNumEltPerOp = (8 * CurrOpSizeBytes) / EltTyBits; 4016 4017 assert(CurrOpSizeBytes > 0 && CurrNumEltPerOp > 0 && "How'd we get here?"); 4018 assert((((NumEltRemaining * EltTyBits) < (2 * 8 * CurrOpSizeBytes)) || 4019 (CurrOpSizeBytes == MaxLegalOpSizeBytes)) && 4020 "Unless we haven't halved the op size yet, " 4021 "we have less than two op's sized units of work left."); 4022 4023 auto *CurrVecTy = CurrNumEltPerOp > NumEltPerXMM 4024 ? FixedVectorType::get(EltTy, CurrNumEltPerOp) 4025 : XMMVecTy; 4026 4027 assert(CurrVecTy->getNumElements() % CurrNumEltPerOp == 0 && 4028 "After halving sizes, the vector elt count is no longer a multiple " 4029 "of number of elements per operation?"); 4030 auto *CoalescedVecTy = 4031 CurrNumEltPerOp == 1 4032 ? CurrVecTy 4033 : FixedVectorType::get( 4034 IntegerType::get(Src->getContext(), 4035 EltTyBits * CurrNumEltPerOp), 4036 CurrVecTy->getNumElements() / CurrNumEltPerOp); 4037 assert(DL.getTypeSizeInBits(CoalescedVecTy) == 4038 DL.getTypeSizeInBits(CurrVecTy) && 4039 "coalesciing elements doesn't change vector width."); 4040 4041 while (NumEltRemaining > 0) { 4042 assert(SubVecEltsLeft >= 0 && "Subreg element count overconsumtion?"); 4043 4044 // Can we use this vector size, as per the remaining element count? 4045 // Iff the vector is naturally aligned, we can do a wide load regardless. 4046 if (NumEltRemaining < CurrNumEltPerOp && 4047 (!IsLoad || Alignment.valueOrOne() < CurrOpSizeBytes) && 4048 CurrOpSizeBytes != 1) 4049 break; // Try smalled vector size. 4050 4051 bool Is0thSubVec = (NumEltDone() % LT.second.getVectorNumElements()) == 0; 4052 4053 // If we have fully processed the previous reg, we need to replenish it. 4054 if (SubVecEltsLeft == 0) { 4055 SubVecEltsLeft += CurrVecTy->getNumElements(); 4056 // And that's free only for the 0'th subvector of a legalized vector. 4057 if (!Is0thSubVec) 4058 Cost += getShuffleCost(IsLoad ? TTI::ShuffleKind::SK_InsertSubvector 4059 : TTI::ShuffleKind::SK_ExtractSubvector, 4060 VTy, None, NumEltDone(), CurrVecTy); 4061 } 4062 4063 // While we can directly load/store ZMM, YMM, and 64-bit halves of XMM, 4064 // for smaller widths (32/16/8) we have to insert/extract them separately. 4065 // Again, it's free for the 0'th subreg (if op is 32/64 bit wide, 4066 // but let's pretend that it is also true for 16/8 bit wide ops...) 4067 if (CurrOpSizeBytes <= 32 / 8 && !Is0thSubVec) { 4068 int NumEltDoneInCurrXMM = NumEltDone() % NumEltPerXMM; 4069 assert(NumEltDoneInCurrXMM % CurrNumEltPerOp == 0 && ""); 4070 int CoalescedVecEltIdx = NumEltDoneInCurrXMM / CurrNumEltPerOp; 4071 APInt DemandedElts = 4072 APInt::getBitsSet(CoalescedVecTy->getNumElements(), 4073 CoalescedVecEltIdx, CoalescedVecEltIdx + 1); 4074 assert(DemandedElts.countPopulation() == 1 && "Inserting single value"); 4075 Cost += getScalarizationOverhead(CoalescedVecTy, DemandedElts, IsLoad, 4076 !IsLoad); 4077 } 4078 4079 // This isn't exactly right. We're using slow unaligned 32-byte accesses 4080 // as a proxy for a double-pumped AVX memory interface such as on 4081 // Sandybridge. 4082 if (CurrOpSizeBytes == 32 && ST->isUnalignedMem32Slow()) 4083 Cost += 2; 4084 else 4085 Cost += 1; 4086 4087 SubVecEltsLeft -= CurrNumEltPerOp; 4088 NumEltRemaining -= CurrNumEltPerOp; 4089 Alignment = commonAlignment(Alignment.valueOrOne(), CurrOpSizeBytes); 4090 } 4091 } 4092 4093 assert(NumEltRemaining <= 0 && "Should have processed all the elements."); 4094 4095 return Cost; 4096 } 4097 4098 InstructionCost 4099 X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, Align Alignment, 4100 unsigned AddressSpace, 4101 TTI::TargetCostKind CostKind) { 4102 bool IsLoad = (Instruction::Load == Opcode); 4103 bool IsStore = (Instruction::Store == Opcode); 4104 4105 auto *SrcVTy = dyn_cast<FixedVectorType>(SrcTy); 4106 if (!SrcVTy) 4107 // To calculate scalar take the regular cost, without mask 4108 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace, CostKind); 4109 4110 unsigned NumElem = SrcVTy->getNumElements(); 4111 auto *MaskTy = 4112 FixedVectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 4113 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, Alignment)) || 4114 (IsStore && !isLegalMaskedStore(SrcVTy, Alignment))) { 4115 // Scalarization 4116 APInt DemandedElts = APInt::getAllOnes(NumElem); 4117 InstructionCost MaskSplitCost = 4118 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 4119 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 4120 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr, 4121 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4122 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 4123 InstructionCost MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 4124 InstructionCost ValueSplitCost = 4125 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore); 4126 InstructionCost MemopCost = 4127 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4128 Alignment, AddressSpace, CostKind); 4129 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 4130 } 4131 4132 // Legalize the type. 4133 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 4134 auto VT = TLI->getValueType(DL, SrcVTy); 4135 InstructionCost Cost = 0; 4136 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 4137 LT.second.getVectorNumElements() == NumElem) 4138 // Promotion requires extend/truncate for data and a shuffle for mask. 4139 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, None, 0, nullptr) + 4140 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, None, 0, nullptr); 4141 4142 else if (LT.first * LT.second.getVectorNumElements() > NumElem) { 4143 auto *NewMaskTy = FixedVectorType::get(MaskTy->getElementType(), 4144 LT.second.getVectorNumElements()); 4145 // Expanding requires fill mask with zeroes 4146 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, None, 0, MaskTy); 4147 } 4148 4149 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 4150 if (!ST->hasAVX512()) 4151 return Cost + LT.first * (IsLoad ? 2 : 8); 4152 4153 // AVX-512 masked load/store is cheapper 4154 return Cost + LT.first; 4155 } 4156 4157 InstructionCost X86TTIImpl::getAddressComputationCost(Type *Ty, 4158 ScalarEvolution *SE, 4159 const SCEV *Ptr) { 4160 // Address computations in vectorized code with non-consecutive addresses will 4161 // likely result in more instructions compared to scalar code where the 4162 // computation can more often be merged into the index mode. The resulting 4163 // extra micro-ops can significantly decrease throughput. 4164 const unsigned NumVectorInstToHideOverhead = 10; 4165 4166 // Cost modeling of Strided Access Computation is hidden by the indexing 4167 // modes of X86 regardless of the stride value. We dont believe that there 4168 // is a difference between constant strided access in gerenal and constant 4169 // strided value which is less than or equal to 64. 4170 // Even in the case of (loop invariant) stride whose value is not known at 4171 // compile time, the address computation will not incur more than one extra 4172 // ADD instruction. 4173 if (Ty->isVectorTy() && SE && !ST->hasAVX2()) { 4174 // TODO: AVX2 is the current cut-off because we don't have correct 4175 // interleaving costs for prior ISA's. 4176 if (!BaseT::isStridedAccess(Ptr)) 4177 return NumVectorInstToHideOverhead; 4178 if (!BaseT::getConstantStrideStep(SE, Ptr)) 4179 return 1; 4180 } 4181 4182 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 4183 } 4184 4185 InstructionCost 4186 X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 4187 Optional<FastMathFlags> FMF, 4188 TTI::TargetCostKind CostKind) { 4189 if (TTI::requiresOrderedReduction(FMF)) 4190 return BaseT::getArithmeticReductionCost(Opcode, ValTy, FMF, CostKind); 4191 4192 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 4193 // and make it as the cost. 4194 4195 static const CostTblEntry SLMCostTblNoPairWise[] = { 4196 { ISD::FADD, MVT::v2f64, 3 }, 4197 { ISD::ADD, MVT::v2i64, 5 }, 4198 }; 4199 4200 static const CostTblEntry SSE2CostTblNoPairWise[] = { 4201 { ISD::FADD, MVT::v2f64, 2 }, 4202 { ISD::FADD, MVT::v2f32, 2 }, 4203 { ISD::FADD, MVT::v4f32, 4 }, 4204 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 4205 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 4206 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 4207 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 4208 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 4209 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 4210 { ISD::ADD, MVT::v2i8, 2 }, 4211 { ISD::ADD, MVT::v4i8, 2 }, 4212 { ISD::ADD, MVT::v8i8, 2 }, 4213 { ISD::ADD, MVT::v16i8, 3 }, 4214 }; 4215 4216 static const CostTblEntry AVX1CostTblNoPairWise[] = { 4217 { ISD::FADD, MVT::v4f64, 3 }, 4218 { ISD::FADD, MVT::v4f32, 3 }, 4219 { ISD::FADD, MVT::v8f32, 4 }, 4220 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 4221 { ISD::ADD, MVT::v4i64, 3 }, 4222 { ISD::ADD, MVT::v8i32, 5 }, 4223 { ISD::ADD, MVT::v16i16, 5 }, 4224 { ISD::ADD, MVT::v32i8, 4 }, 4225 }; 4226 4227 int ISD = TLI->InstructionOpcodeToISD(Opcode); 4228 assert(ISD && "Invalid opcode"); 4229 4230 // Before legalizing the type, give a chance to look up illegal narrow types 4231 // in the table. 4232 // FIXME: Is there a better way to do this? 4233 EVT VT = TLI->getValueType(DL, ValTy); 4234 if (VT.isSimple()) { 4235 MVT MTy = VT.getSimpleVT(); 4236 if (ST->useSLMArithCosts()) 4237 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 4238 return Entry->Cost; 4239 4240 if (ST->hasAVX()) 4241 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4242 return Entry->Cost; 4243 4244 if (ST->hasSSE2()) 4245 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4246 return Entry->Cost; 4247 } 4248 4249 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 4250 4251 MVT MTy = LT.second; 4252 4253 auto *ValVTy = cast<FixedVectorType>(ValTy); 4254 4255 // Special case: vXi8 mul reductions are performed as vXi16. 4256 if (ISD == ISD::MUL && MTy.getScalarType() == MVT::i8) { 4257 auto *WideSclTy = IntegerType::get(ValVTy->getContext(), 16); 4258 auto *WideVecTy = FixedVectorType::get(WideSclTy, ValVTy->getNumElements()); 4259 return getCastInstrCost(Instruction::ZExt, WideVecTy, ValTy, 4260 TargetTransformInfo::CastContextHint::None, 4261 CostKind) + 4262 getArithmeticReductionCost(Opcode, WideVecTy, FMF, CostKind); 4263 } 4264 4265 InstructionCost ArithmeticCost = 0; 4266 if (LT.first != 1 && MTy.isVector() && 4267 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4268 // Type needs to be split. We need LT.first - 1 arithmetic ops. 4269 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 4270 MTy.getVectorNumElements()); 4271 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 4272 ArithmeticCost *= LT.first - 1; 4273 } 4274 4275 if (ST->useSLMArithCosts()) 4276 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 4277 return ArithmeticCost + Entry->Cost; 4278 4279 if (ST->hasAVX()) 4280 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4281 return ArithmeticCost + Entry->Cost; 4282 4283 if (ST->hasSSE2()) 4284 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4285 return ArithmeticCost + Entry->Cost; 4286 4287 // FIXME: These assume a naive kshift+binop lowering, which is probably 4288 // conservative in most cases. 4289 static const CostTblEntry AVX512BoolReduction[] = { 4290 { ISD::AND, MVT::v2i1, 3 }, 4291 { ISD::AND, MVT::v4i1, 5 }, 4292 { ISD::AND, MVT::v8i1, 7 }, 4293 { ISD::AND, MVT::v16i1, 9 }, 4294 { ISD::AND, MVT::v32i1, 11 }, 4295 { ISD::AND, MVT::v64i1, 13 }, 4296 { ISD::OR, MVT::v2i1, 3 }, 4297 { ISD::OR, MVT::v4i1, 5 }, 4298 { ISD::OR, MVT::v8i1, 7 }, 4299 { ISD::OR, MVT::v16i1, 9 }, 4300 { ISD::OR, MVT::v32i1, 11 }, 4301 { ISD::OR, MVT::v64i1, 13 }, 4302 }; 4303 4304 static const CostTblEntry AVX2BoolReduction[] = { 4305 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 4306 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 4307 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 4308 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 4309 }; 4310 4311 static const CostTblEntry AVX1BoolReduction[] = { 4312 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 4313 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 4314 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 4315 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 4316 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 4317 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 4318 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 4319 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 4320 }; 4321 4322 static const CostTblEntry SSE2BoolReduction[] = { 4323 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 4324 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 4325 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 4326 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 4327 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 4328 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 4329 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 4330 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 4331 }; 4332 4333 // Handle bool allof/anyof patterns. 4334 if (ValVTy->getElementType()->isIntegerTy(1)) { 4335 InstructionCost ArithmeticCost = 0; 4336 if (LT.first != 1 && MTy.isVector() && 4337 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4338 // Type needs to be split. We need LT.first - 1 arithmetic ops. 4339 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 4340 MTy.getVectorNumElements()); 4341 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 4342 ArithmeticCost *= LT.first - 1; 4343 } 4344 4345 if (ST->hasAVX512()) 4346 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 4347 return ArithmeticCost + Entry->Cost; 4348 if (ST->hasAVX2()) 4349 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 4350 return ArithmeticCost + Entry->Cost; 4351 if (ST->hasAVX()) 4352 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 4353 return ArithmeticCost + Entry->Cost; 4354 if (ST->hasSSE2()) 4355 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 4356 return ArithmeticCost + Entry->Cost; 4357 4358 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, FMF, CostKind); 4359 } 4360 4361 unsigned NumVecElts = ValVTy->getNumElements(); 4362 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 4363 4364 // Special case power of 2 reductions where the scalar type isn't changed 4365 // by type legalization. 4366 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 4367 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, FMF, CostKind); 4368 4369 InstructionCost ReductionCost = 0; 4370 4371 auto *Ty = ValVTy; 4372 if (LT.first != 1 && MTy.isVector() && 4373 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4374 // Type needs to be split. We need LT.first - 1 arithmetic ops. 4375 Ty = FixedVectorType::get(ValVTy->getElementType(), 4376 MTy.getVectorNumElements()); 4377 ReductionCost = getArithmeticInstrCost(Opcode, Ty, CostKind); 4378 ReductionCost *= LT.first - 1; 4379 NumVecElts = MTy.getVectorNumElements(); 4380 } 4381 4382 // Now handle reduction with the legal type, taking into account size changes 4383 // at each level. 4384 while (NumVecElts > 1) { 4385 // Determine the size of the remaining vector we need to reduce. 4386 unsigned Size = NumVecElts * ScalarSize; 4387 NumVecElts /= 2; 4388 // If we're reducing from 256/512 bits, use an extract_subvector. 4389 if (Size > 128) { 4390 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 4391 ReductionCost += 4392 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 4393 Ty = SubTy; 4394 } else if (Size == 128) { 4395 // Reducing from 128 bits is a permute of v2f64/v2i64. 4396 FixedVectorType *ShufTy; 4397 if (ValVTy->isFloatingPointTy()) 4398 ShufTy = 4399 FixedVectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 4400 else 4401 ShufTy = 4402 FixedVectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 4403 ReductionCost += 4404 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4405 } else if (Size == 64) { 4406 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 4407 FixedVectorType *ShufTy; 4408 if (ValVTy->isFloatingPointTy()) 4409 ShufTy = 4410 FixedVectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 4411 else 4412 ShufTy = 4413 FixedVectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 4414 ReductionCost += 4415 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4416 } else { 4417 // Reducing from smaller size is a shift by immediate. 4418 auto *ShiftTy = FixedVectorType::get( 4419 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 4420 ReductionCost += getArithmeticInstrCost( 4421 Instruction::LShr, ShiftTy, CostKind, 4422 TargetTransformInfo::OK_AnyValue, 4423 TargetTransformInfo::OK_UniformConstantValue, 4424 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 4425 } 4426 4427 // Add the arithmetic op for this level. 4428 ReductionCost += getArithmeticInstrCost(Opcode, Ty, CostKind); 4429 } 4430 4431 // Add the final extract element to the cost. 4432 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 4433 } 4434 4435 InstructionCost X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, 4436 bool IsUnsigned) { 4437 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 4438 4439 MVT MTy = LT.second; 4440 4441 int ISD; 4442 if (Ty->isIntOrIntVectorTy()) { 4443 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 4444 } else { 4445 assert(Ty->isFPOrFPVectorTy() && 4446 "Expected float point or integer vector type."); 4447 ISD = ISD::FMINNUM; 4448 } 4449 4450 static const CostTblEntry SSE1CostTbl[] = { 4451 {ISD::FMINNUM, MVT::v4f32, 1}, 4452 }; 4453 4454 static const CostTblEntry SSE2CostTbl[] = { 4455 {ISD::FMINNUM, MVT::v2f64, 1}, 4456 {ISD::SMIN, MVT::v8i16, 1}, 4457 {ISD::UMIN, MVT::v16i8, 1}, 4458 }; 4459 4460 static const CostTblEntry SSE41CostTbl[] = { 4461 {ISD::SMIN, MVT::v4i32, 1}, 4462 {ISD::UMIN, MVT::v4i32, 1}, 4463 {ISD::UMIN, MVT::v8i16, 1}, 4464 {ISD::SMIN, MVT::v16i8, 1}, 4465 }; 4466 4467 static const CostTblEntry SSE42CostTbl[] = { 4468 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 4469 }; 4470 4471 static const CostTblEntry AVX1CostTbl[] = { 4472 {ISD::FMINNUM, MVT::v8f32, 1}, 4473 {ISD::FMINNUM, MVT::v4f64, 1}, 4474 {ISD::SMIN, MVT::v8i32, 3}, 4475 {ISD::UMIN, MVT::v8i32, 3}, 4476 {ISD::SMIN, MVT::v16i16, 3}, 4477 {ISD::UMIN, MVT::v16i16, 3}, 4478 {ISD::SMIN, MVT::v32i8, 3}, 4479 {ISD::UMIN, MVT::v32i8, 3}, 4480 }; 4481 4482 static const CostTblEntry AVX2CostTbl[] = { 4483 {ISD::SMIN, MVT::v8i32, 1}, 4484 {ISD::UMIN, MVT::v8i32, 1}, 4485 {ISD::SMIN, MVT::v16i16, 1}, 4486 {ISD::UMIN, MVT::v16i16, 1}, 4487 {ISD::SMIN, MVT::v32i8, 1}, 4488 {ISD::UMIN, MVT::v32i8, 1}, 4489 }; 4490 4491 static const CostTblEntry AVX512CostTbl[] = { 4492 {ISD::FMINNUM, MVT::v16f32, 1}, 4493 {ISD::FMINNUM, MVT::v8f64, 1}, 4494 {ISD::SMIN, MVT::v2i64, 1}, 4495 {ISD::UMIN, MVT::v2i64, 1}, 4496 {ISD::SMIN, MVT::v4i64, 1}, 4497 {ISD::UMIN, MVT::v4i64, 1}, 4498 {ISD::SMIN, MVT::v8i64, 1}, 4499 {ISD::UMIN, MVT::v8i64, 1}, 4500 {ISD::SMIN, MVT::v16i32, 1}, 4501 {ISD::UMIN, MVT::v16i32, 1}, 4502 }; 4503 4504 static const CostTblEntry AVX512BWCostTbl[] = { 4505 {ISD::SMIN, MVT::v32i16, 1}, 4506 {ISD::UMIN, MVT::v32i16, 1}, 4507 {ISD::SMIN, MVT::v64i8, 1}, 4508 {ISD::UMIN, MVT::v64i8, 1}, 4509 }; 4510 4511 // If we have a native MIN/MAX instruction for this type, use it. 4512 if (ST->hasBWI()) 4513 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 4514 return LT.first * Entry->Cost; 4515 4516 if (ST->hasAVX512()) 4517 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 4518 return LT.first * Entry->Cost; 4519 4520 if (ST->hasAVX2()) 4521 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 4522 return LT.first * Entry->Cost; 4523 4524 if (ST->hasAVX()) 4525 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 4526 return LT.first * Entry->Cost; 4527 4528 if (ST->hasSSE42()) 4529 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 4530 return LT.first * Entry->Cost; 4531 4532 if (ST->hasSSE41()) 4533 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 4534 return LT.first * Entry->Cost; 4535 4536 if (ST->hasSSE2()) 4537 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 4538 return LT.first * Entry->Cost; 4539 4540 if (ST->hasSSE1()) 4541 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 4542 return LT.first * Entry->Cost; 4543 4544 unsigned CmpOpcode; 4545 if (Ty->isFPOrFPVectorTy()) { 4546 CmpOpcode = Instruction::FCmp; 4547 } else { 4548 assert(Ty->isIntOrIntVectorTy() && 4549 "expecting floating point or integer type for min/max reduction"); 4550 CmpOpcode = Instruction::ICmp; 4551 } 4552 4553 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4554 // Otherwise fall back to cmp+select. 4555 InstructionCost Result = 4556 getCmpSelInstrCost(CmpOpcode, Ty, CondTy, CmpInst::BAD_ICMP_PREDICATE, 4557 CostKind) + 4558 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, 4559 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4560 return Result; 4561 } 4562 4563 InstructionCost 4564 X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 4565 bool IsUnsigned, 4566 TTI::TargetCostKind CostKind) { 4567 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 4568 4569 MVT MTy = LT.second; 4570 4571 int ISD; 4572 if (ValTy->isIntOrIntVectorTy()) { 4573 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 4574 } else { 4575 assert(ValTy->isFPOrFPVectorTy() && 4576 "Expected float point or integer vector type."); 4577 ISD = ISD::FMINNUM; 4578 } 4579 4580 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 4581 // and make it as the cost. 4582 4583 static const CostTblEntry SSE2CostTblNoPairWise[] = { 4584 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 4585 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 4586 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 4587 }; 4588 4589 static const CostTblEntry SSE41CostTblNoPairWise[] = { 4590 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 4591 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 4592 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 4593 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 4594 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 4595 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 4596 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 4597 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 4598 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 4599 {ISD::SMIN, MVT::v16i8, 6}, 4600 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 4601 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 4602 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 4603 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 4604 }; 4605 4606 static const CostTblEntry AVX1CostTblNoPairWise[] = { 4607 {ISD::SMIN, MVT::v16i16, 6}, 4608 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 4609 {ISD::SMIN, MVT::v32i8, 8}, 4610 {ISD::UMIN, MVT::v32i8, 8}, 4611 }; 4612 4613 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 4614 {ISD::SMIN, MVT::v32i16, 8}, 4615 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 4616 {ISD::SMIN, MVT::v64i8, 10}, 4617 {ISD::UMIN, MVT::v64i8, 10}, 4618 }; 4619 4620 // Before legalizing the type, give a chance to look up illegal narrow types 4621 // in the table. 4622 // FIXME: Is there a better way to do this? 4623 EVT VT = TLI->getValueType(DL, ValTy); 4624 if (VT.isSimple()) { 4625 MVT MTy = VT.getSimpleVT(); 4626 if (ST->hasBWI()) 4627 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4628 return Entry->Cost; 4629 4630 if (ST->hasAVX()) 4631 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4632 return Entry->Cost; 4633 4634 if (ST->hasSSE41()) 4635 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4636 return Entry->Cost; 4637 4638 if (ST->hasSSE2()) 4639 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4640 return Entry->Cost; 4641 } 4642 4643 auto *ValVTy = cast<FixedVectorType>(ValTy); 4644 unsigned NumVecElts = ValVTy->getNumElements(); 4645 4646 auto *Ty = ValVTy; 4647 InstructionCost MinMaxCost = 0; 4648 if (LT.first != 1 && MTy.isVector() && 4649 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4650 // Type needs to be split. We need LT.first - 1 operations ops. 4651 Ty = FixedVectorType::get(ValVTy->getElementType(), 4652 MTy.getVectorNumElements()); 4653 auto *SubCondTy = FixedVectorType::get(CondTy->getElementType(), 4654 MTy.getVectorNumElements()); 4655 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4656 MinMaxCost *= LT.first - 1; 4657 NumVecElts = MTy.getVectorNumElements(); 4658 } 4659 4660 if (ST->hasBWI()) 4661 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4662 return MinMaxCost + Entry->Cost; 4663 4664 if (ST->hasAVX()) 4665 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4666 return MinMaxCost + Entry->Cost; 4667 4668 if (ST->hasSSE41()) 4669 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4670 return MinMaxCost + Entry->Cost; 4671 4672 if (ST->hasSSE2()) 4673 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4674 return MinMaxCost + Entry->Cost; 4675 4676 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 4677 4678 // Special case power of 2 reductions where the scalar type isn't changed 4679 // by type legalization. 4680 if (!isPowerOf2_32(ValVTy->getNumElements()) || 4681 ScalarSize != MTy.getScalarSizeInBits()) 4682 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsUnsigned, CostKind); 4683 4684 // Now handle reduction with the legal type, taking into account size changes 4685 // at each level. 4686 while (NumVecElts > 1) { 4687 // Determine the size of the remaining vector we need to reduce. 4688 unsigned Size = NumVecElts * ScalarSize; 4689 NumVecElts /= 2; 4690 // If we're reducing from 256/512 bits, use an extract_subvector. 4691 if (Size > 128) { 4692 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 4693 MinMaxCost += 4694 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 4695 Ty = SubTy; 4696 } else if (Size == 128) { 4697 // Reducing from 128 bits is a permute of v2f64/v2i64. 4698 VectorType *ShufTy; 4699 if (ValTy->isFloatingPointTy()) 4700 ShufTy = 4701 FixedVectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 4702 else 4703 ShufTy = FixedVectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 4704 MinMaxCost += 4705 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4706 } else if (Size == 64) { 4707 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 4708 FixedVectorType *ShufTy; 4709 if (ValTy->isFloatingPointTy()) 4710 ShufTy = FixedVectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 4711 else 4712 ShufTy = FixedVectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 4713 MinMaxCost += 4714 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4715 } else { 4716 // Reducing from smaller size is a shift by immediate. 4717 auto *ShiftTy = FixedVectorType::get( 4718 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 4719 MinMaxCost += getArithmeticInstrCost( 4720 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, 4721 TargetTransformInfo::OK_AnyValue, 4722 TargetTransformInfo::OK_UniformConstantValue, 4723 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 4724 } 4725 4726 // Add the arithmetic op for this level. 4727 auto *SubCondTy = 4728 FixedVectorType::get(CondTy->getElementType(), Ty->getNumElements()); 4729 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4730 } 4731 4732 // Add the final extract element to the cost. 4733 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 4734 } 4735 4736 /// Calculate the cost of materializing a 64-bit value. This helper 4737 /// method might only calculate a fraction of a larger immediate. Therefore it 4738 /// is valid to return a cost of ZERO. 4739 InstructionCost X86TTIImpl::getIntImmCost(int64_t Val) { 4740 if (Val == 0) 4741 return TTI::TCC_Free; 4742 4743 if (isInt<32>(Val)) 4744 return TTI::TCC_Basic; 4745 4746 return 2 * TTI::TCC_Basic; 4747 } 4748 4749 InstructionCost X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 4750 TTI::TargetCostKind CostKind) { 4751 assert(Ty->isIntegerTy()); 4752 4753 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4754 if (BitSize == 0) 4755 return ~0U; 4756 4757 // Never hoist constants larger than 128bit, because this might lead to 4758 // incorrect code generation or assertions in codegen. 4759 // Fixme: Create a cost model for types larger than i128 once the codegen 4760 // issues have been fixed. 4761 if (BitSize > 128) 4762 return TTI::TCC_Free; 4763 4764 if (Imm == 0) 4765 return TTI::TCC_Free; 4766 4767 // Sign-extend all constants to a multiple of 64-bit. 4768 APInt ImmVal = Imm; 4769 if (BitSize % 64 != 0) 4770 ImmVal = Imm.sext(alignTo(BitSize, 64)); 4771 4772 // Split the constant into 64-bit chunks and calculate the cost for each 4773 // chunk. 4774 InstructionCost Cost = 0; 4775 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 4776 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 4777 int64_t Val = Tmp.getSExtValue(); 4778 Cost += getIntImmCost(Val); 4779 } 4780 // We need at least one instruction to materialize the constant. 4781 return std::max<InstructionCost>(1, Cost); 4782 } 4783 4784 InstructionCost X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, 4785 const APInt &Imm, Type *Ty, 4786 TTI::TargetCostKind CostKind, 4787 Instruction *Inst) { 4788 assert(Ty->isIntegerTy()); 4789 4790 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4791 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4792 // here, so that constant hoisting will ignore this constant. 4793 if (BitSize == 0) 4794 return TTI::TCC_Free; 4795 4796 unsigned ImmIdx = ~0U; 4797 switch (Opcode) { 4798 default: 4799 return TTI::TCC_Free; 4800 case Instruction::GetElementPtr: 4801 // Always hoist the base address of a GetElementPtr. This prevents the 4802 // creation of new constants for every base constant that gets constant 4803 // folded with the offset. 4804 if (Idx == 0) 4805 return 2 * TTI::TCC_Basic; 4806 return TTI::TCC_Free; 4807 case Instruction::Store: 4808 ImmIdx = 0; 4809 break; 4810 case Instruction::ICmp: 4811 // This is an imperfect hack to prevent constant hoisting of 4812 // compares that might be trying to check if a 64-bit value fits in 4813 // 32-bits. The backend can optimize these cases using a right shift by 32. 4814 // Ideally we would check the compare predicate here. There also other 4815 // similar immediates the backend can use shifts for. 4816 if (Idx == 1 && Imm.getBitWidth() == 64) { 4817 uint64_t ImmVal = Imm.getZExtValue(); 4818 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 4819 return TTI::TCC_Free; 4820 } 4821 ImmIdx = 1; 4822 break; 4823 case Instruction::And: 4824 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 4825 // by using a 32-bit operation with implicit zero extension. Detect such 4826 // immediates here as the normal path expects bit 31 to be sign extended. 4827 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 4828 return TTI::TCC_Free; 4829 ImmIdx = 1; 4830 break; 4831 case Instruction::Add: 4832 case Instruction::Sub: 4833 // For add/sub, we can use the opposite instruction for INT32_MIN. 4834 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 4835 return TTI::TCC_Free; 4836 ImmIdx = 1; 4837 break; 4838 case Instruction::UDiv: 4839 case Instruction::SDiv: 4840 case Instruction::URem: 4841 case Instruction::SRem: 4842 // Division by constant is typically expanded later into a different 4843 // instruction sequence. This completely changes the constants. 4844 // Report them as "free" to stop ConstantHoist from marking them as opaque. 4845 return TTI::TCC_Free; 4846 case Instruction::Mul: 4847 case Instruction::Or: 4848 case Instruction::Xor: 4849 ImmIdx = 1; 4850 break; 4851 // Always return TCC_Free for the shift value of a shift instruction. 4852 case Instruction::Shl: 4853 case Instruction::LShr: 4854 case Instruction::AShr: 4855 if (Idx == 1) 4856 return TTI::TCC_Free; 4857 break; 4858 case Instruction::Trunc: 4859 case Instruction::ZExt: 4860 case Instruction::SExt: 4861 case Instruction::IntToPtr: 4862 case Instruction::PtrToInt: 4863 case Instruction::BitCast: 4864 case Instruction::PHI: 4865 case Instruction::Call: 4866 case Instruction::Select: 4867 case Instruction::Ret: 4868 case Instruction::Load: 4869 break; 4870 } 4871 4872 if (Idx == ImmIdx) { 4873 int NumConstants = divideCeil(BitSize, 64); 4874 InstructionCost Cost = X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4875 return (Cost <= NumConstants * TTI::TCC_Basic) 4876 ? static_cast<int>(TTI::TCC_Free) 4877 : Cost; 4878 } 4879 4880 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4881 } 4882 4883 InstructionCost X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 4884 const APInt &Imm, Type *Ty, 4885 TTI::TargetCostKind CostKind) { 4886 assert(Ty->isIntegerTy()); 4887 4888 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4889 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4890 // here, so that constant hoisting will ignore this constant. 4891 if (BitSize == 0) 4892 return TTI::TCC_Free; 4893 4894 switch (IID) { 4895 default: 4896 return TTI::TCC_Free; 4897 case Intrinsic::sadd_with_overflow: 4898 case Intrinsic::uadd_with_overflow: 4899 case Intrinsic::ssub_with_overflow: 4900 case Intrinsic::usub_with_overflow: 4901 case Intrinsic::smul_with_overflow: 4902 case Intrinsic::umul_with_overflow: 4903 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 4904 return TTI::TCC_Free; 4905 break; 4906 case Intrinsic::experimental_stackmap: 4907 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4908 return TTI::TCC_Free; 4909 break; 4910 case Intrinsic::experimental_patchpoint_void: 4911 case Intrinsic::experimental_patchpoint_i64: 4912 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4913 return TTI::TCC_Free; 4914 break; 4915 } 4916 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4917 } 4918 4919 InstructionCost X86TTIImpl::getCFInstrCost(unsigned Opcode, 4920 TTI::TargetCostKind CostKind, 4921 const Instruction *I) { 4922 if (CostKind != TTI::TCK_RecipThroughput) 4923 return Opcode == Instruction::PHI ? 0 : 1; 4924 // Branches are assumed to be predicted. 4925 return 0; 4926 } 4927 4928 int X86TTIImpl::getGatherOverhead() const { 4929 // Some CPUs have more overhead for gather. The specified overhead is relative 4930 // to the Load operation. "2" is the number provided by Intel architects. This 4931 // parameter is used for cost estimation of Gather Op and comparison with 4932 // other alternatives. 4933 // TODO: Remove the explicit hasAVX512()?, That would mean we would only 4934 // enable gather with a -march. 4935 if (ST->hasAVX512() || (ST->hasAVX2() && ST->hasFastGather())) 4936 return 2; 4937 4938 return 1024; 4939 } 4940 4941 int X86TTIImpl::getScatterOverhead() const { 4942 if (ST->hasAVX512()) 4943 return 2; 4944 4945 return 1024; 4946 } 4947 4948 // Return an average cost of Gather / Scatter instruction, maybe improved later. 4949 // FIXME: Add TargetCostKind support. 4950 InstructionCost X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, 4951 const Value *Ptr, Align Alignment, 4952 unsigned AddressSpace) { 4953 4954 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 4955 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4956 4957 // Try to reduce index size from 64 bit (default for GEP) 4958 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 4959 // operation will use 16 x 64 indices which do not fit in a zmm and needs 4960 // to split. Also check that the base pointer is the same for all lanes, 4961 // and that there's at most one variable index. 4962 auto getIndexSizeInBits = [](const Value *Ptr, const DataLayout &DL) { 4963 unsigned IndexSize = DL.getPointerSizeInBits(); 4964 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 4965 if (IndexSize < 64 || !GEP) 4966 return IndexSize; 4967 4968 unsigned NumOfVarIndices = 0; 4969 const Value *Ptrs = GEP->getPointerOperand(); 4970 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 4971 return IndexSize; 4972 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 4973 if (isa<Constant>(GEP->getOperand(i))) 4974 continue; 4975 Type *IndxTy = GEP->getOperand(i)->getType(); 4976 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 4977 IndxTy = IndexVTy->getElementType(); 4978 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 4979 !isa<SExtInst>(GEP->getOperand(i))) || 4980 ++NumOfVarIndices > 1) 4981 return IndexSize; // 64 4982 } 4983 return (unsigned)32; 4984 }; 4985 4986 // Trying to reduce IndexSize to 32 bits for vector 16. 4987 // By default the IndexSize is equal to pointer size. 4988 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 4989 ? getIndexSizeInBits(Ptr, DL) 4990 : DL.getPointerSizeInBits(); 4991 4992 auto *IndexVTy = FixedVectorType::get( 4993 IntegerType::get(SrcVTy->getContext(), IndexSize), VF); 4994 std::pair<InstructionCost, MVT> IdxsLT = 4995 TLI->getTypeLegalizationCost(DL, IndexVTy); 4996 std::pair<InstructionCost, MVT> SrcLT = 4997 TLI->getTypeLegalizationCost(DL, SrcVTy); 4998 InstructionCost::CostType SplitFactor = 4999 *std::max(IdxsLT.first, SrcLT.first).getValue(); 5000 if (SplitFactor > 1) { 5001 // Handle splitting of vector of pointers 5002 auto *SplitSrcTy = 5003 FixedVectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 5004 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 5005 AddressSpace); 5006 } 5007 5008 // The gather / scatter cost is given by Intel architects. It is a rough 5009 // number since we are looking at one instruction in a time. 5010 const int GSOverhead = (Opcode == Instruction::Load) 5011 ? getGatherOverhead() 5012 : getScatterOverhead(); 5013 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 5014 MaybeAlign(Alignment), AddressSpace, 5015 TTI::TCK_RecipThroughput); 5016 } 5017 5018 /// Return the cost of full scalarization of gather / scatter operation. 5019 /// 5020 /// Opcode - Load or Store instruction. 5021 /// SrcVTy - The type of the data vector that should be gathered or scattered. 5022 /// VariableMask - The mask is non-constant at compile time. 5023 /// Alignment - Alignment for one element. 5024 /// AddressSpace - pointer[s] address space. 5025 /// 5026 /// FIXME: Add TargetCostKind support. 5027 InstructionCost X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 5028 bool VariableMask, Align Alignment, 5029 unsigned AddressSpace) { 5030 Type *ScalarTy = SrcVTy->getScalarType(); 5031 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 5032 APInt DemandedElts = APInt::getAllOnes(VF); 5033 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 5034 5035 InstructionCost MaskUnpackCost = 0; 5036 if (VariableMask) { 5037 auto *MaskTy = 5038 FixedVectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 5039 MaskUnpackCost = getScalarizationOverhead( 5040 MaskTy, DemandedElts, /*Insert=*/false, /*Extract=*/true); 5041 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 5042 Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), nullptr, 5043 CmpInst::BAD_ICMP_PREDICATE, CostKind); 5044 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 5045 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 5046 } 5047 5048 InstructionCost AddressUnpackCost = getScalarizationOverhead( 5049 FixedVectorType::get(ScalarTy->getPointerTo(), VF), DemandedElts, 5050 /*Insert=*/false, /*Extract=*/true); 5051 5052 // The cost of the scalar loads/stores. 5053 InstructionCost MemoryOpCost = 5054 VF * getMemoryOpCost(Opcode, ScalarTy, MaybeAlign(Alignment), 5055 AddressSpace, CostKind); 5056 5057 // The cost of forming the vector from loaded scalars/ 5058 // scalarizing the vector to perform scalar stores. 5059 InstructionCost InsertExtractCost = 5060 getScalarizationOverhead(cast<FixedVectorType>(SrcVTy), DemandedElts, 5061 /*Insert=*/Opcode == Instruction::Load, 5062 /*Extract=*/Opcode == Instruction::Store); 5063 5064 return AddressUnpackCost + MemoryOpCost + MaskUnpackCost + InsertExtractCost; 5065 } 5066 5067 /// Calculate the cost of Gather / Scatter operation 5068 InstructionCost X86TTIImpl::getGatherScatterOpCost( 5069 unsigned Opcode, Type *SrcVTy, const Value *Ptr, bool VariableMask, 5070 Align Alignment, TTI::TargetCostKind CostKind, 5071 const Instruction *I = nullptr) { 5072 if (CostKind != TTI::TCK_RecipThroughput) { 5073 if ((Opcode == Instruction::Load && 5074 isLegalMaskedGather(SrcVTy, Align(Alignment)) && 5075 !forceScalarizeMaskedGather(cast<VectorType>(SrcVTy), 5076 Align(Alignment))) || 5077 (Opcode == Instruction::Store && 5078 isLegalMaskedScatter(SrcVTy, Align(Alignment)) && 5079 !forceScalarizeMaskedScatter(cast<VectorType>(SrcVTy), 5080 Align(Alignment)))) 5081 return 1; 5082 return BaseT::getGatherScatterOpCost(Opcode, SrcVTy, Ptr, VariableMask, 5083 Alignment, CostKind, I); 5084 } 5085 5086 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 5087 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 5088 if (!PtrTy && Ptr->getType()->isVectorTy()) 5089 PtrTy = dyn_cast<PointerType>( 5090 cast<VectorType>(Ptr->getType())->getElementType()); 5091 assert(PtrTy && "Unexpected type for Ptr argument"); 5092 unsigned AddressSpace = PtrTy->getAddressSpace(); 5093 5094 if ((Opcode == Instruction::Load && 5095 (!isLegalMaskedGather(SrcVTy, Align(Alignment)) || 5096 forceScalarizeMaskedGather(cast<VectorType>(SrcVTy), 5097 Align(Alignment)))) || 5098 (Opcode == Instruction::Store && 5099 (!isLegalMaskedScatter(SrcVTy, Align(Alignment)) || 5100 forceScalarizeMaskedScatter(cast<VectorType>(SrcVTy), 5101 Align(Alignment))))) 5102 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 5103 AddressSpace); 5104 5105 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 5106 } 5107 5108 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 5109 TargetTransformInfo::LSRCost &C2) { 5110 // X86 specific here are "instruction number 1st priority". 5111 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 5112 C1.NumIVMuls, C1.NumBaseAdds, 5113 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 5114 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 5115 C2.NumIVMuls, C2.NumBaseAdds, 5116 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 5117 } 5118 5119 bool X86TTIImpl::canMacroFuseCmp() { 5120 return ST->hasMacroFusion() || ST->hasBranchFusion(); 5121 } 5122 5123 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, Align Alignment) { 5124 if (!ST->hasAVX()) 5125 return false; 5126 5127 // The backend can't handle a single element vector. 5128 if (isa<VectorType>(DataTy) && 5129 cast<FixedVectorType>(DataTy)->getNumElements() == 1) 5130 return false; 5131 Type *ScalarTy = DataTy->getScalarType(); 5132 5133 if (ScalarTy->isPointerTy()) 5134 return true; 5135 5136 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 5137 return true; 5138 5139 if (ScalarTy->isHalfTy() && ST->hasBWI() && ST->hasFP16()) 5140 return true; 5141 5142 if (!ScalarTy->isIntegerTy()) 5143 return false; 5144 5145 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 5146 return IntWidth == 32 || IntWidth == 64 || 5147 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 5148 } 5149 5150 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, Align Alignment) { 5151 return isLegalMaskedLoad(DataType, Alignment); 5152 } 5153 5154 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 5155 unsigned DataSize = DL.getTypeStoreSize(DataType); 5156 // The only supported nontemporal loads are for aligned vectors of 16 or 32 5157 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 5158 // (the equivalent stores only require AVX). 5159 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 5160 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 5161 5162 return false; 5163 } 5164 5165 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 5166 unsigned DataSize = DL.getTypeStoreSize(DataType); 5167 5168 // SSE4A supports nontemporal stores of float and double at arbitrary 5169 // alignment. 5170 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 5171 return true; 5172 5173 // Besides the SSE4A subtarget exception above, only aligned stores are 5174 // available nontemporaly on any other subtarget. And only stores with a size 5175 // of 4..32 bytes (powers of 2, only) are permitted. 5176 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 5177 !isPowerOf2_32(DataSize)) 5178 return false; 5179 5180 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 5181 // loads require AVX2). 5182 if (DataSize == 32) 5183 return ST->hasAVX(); 5184 if (DataSize == 16) 5185 return ST->hasSSE1(); 5186 return true; 5187 } 5188 5189 bool X86TTIImpl::isLegalBroadcastLoad(Type *ElementTy, 5190 ElementCount NumElements) const { 5191 // movddup 5192 return ST->hasSSE3() && !NumElements.isScalable() && 5193 NumElements.getFixedValue() == 2 && 5194 ElementTy == Type::getDoubleTy(ElementTy->getContext()); 5195 } 5196 5197 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 5198 if (!isa<VectorType>(DataTy)) 5199 return false; 5200 5201 if (!ST->hasAVX512()) 5202 return false; 5203 5204 // The backend can't handle a single element vector. 5205 if (cast<FixedVectorType>(DataTy)->getNumElements() == 1) 5206 return false; 5207 5208 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 5209 5210 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 5211 return true; 5212 5213 if (!ScalarTy->isIntegerTy()) 5214 return false; 5215 5216 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 5217 return IntWidth == 32 || IntWidth == 64 || 5218 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 5219 } 5220 5221 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 5222 return isLegalMaskedExpandLoad(DataTy); 5223 } 5224 5225 bool X86TTIImpl::supportsGather() const { 5226 // Some CPUs have better gather performance than others. 5227 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 5228 // enable gather with a -march. 5229 return ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()); 5230 } 5231 5232 bool X86TTIImpl::forceScalarizeMaskedGather(VectorType *VTy, Align Alignment) { 5233 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 5234 // Vector-4 of gather/scatter instruction does not exist on KNL. We can extend 5235 // it to 8 elements, but zeroing upper bits of the mask vector will add more 5236 // instructions. Right now we give the scalar cost of vector-4 for KNL. TODO: 5237 // Check, maybe the gather/scatter instruction is better in the VariableMask 5238 // case. 5239 unsigned NumElts = cast<FixedVectorType>(VTy)->getNumElements(); 5240 return NumElts == 1 || 5241 (ST->hasAVX512() && (NumElts == 2 || (NumElts == 4 && !ST->hasVLX()))); 5242 } 5243 5244 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, Align Alignment) { 5245 if (!supportsGather()) 5246 return false; 5247 Type *ScalarTy = DataTy->getScalarType(); 5248 if (ScalarTy->isPointerTy()) 5249 return true; 5250 5251 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 5252 return true; 5253 5254 if (!ScalarTy->isIntegerTy()) 5255 return false; 5256 5257 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 5258 return IntWidth == 32 || IntWidth == 64; 5259 } 5260 5261 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, Align Alignment) { 5262 // AVX2 doesn't support scatter 5263 if (!ST->hasAVX512()) 5264 return false; 5265 return isLegalMaskedGather(DataType, Alignment); 5266 } 5267 5268 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 5269 EVT VT = TLI->getValueType(DL, DataType); 5270 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 5271 } 5272 5273 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 5274 return false; 5275 } 5276 5277 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 5278 const Function *Callee) const { 5279 const TargetMachine &TM = getTLI()->getTargetMachine(); 5280 5281 // Work this as a subsetting of subtarget features. 5282 const FeatureBitset &CallerBits = 5283 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 5284 const FeatureBitset &CalleeBits = 5285 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 5286 5287 // Check whether features are the same (apart from the ignore list). 5288 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 5289 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 5290 if (RealCallerBits == RealCalleeBits) 5291 return true; 5292 5293 // If the features are a subset, we need to additionally check for calls 5294 // that may become ABI-incompatible as a result of inlining. 5295 if ((RealCallerBits & RealCalleeBits) != RealCalleeBits) 5296 return false; 5297 5298 for (const Instruction &I : instructions(Callee)) { 5299 if (const auto *CB = dyn_cast<CallBase>(&I)) { 5300 SmallVector<Type *, 8> Types; 5301 for (Value *Arg : CB->args()) 5302 Types.push_back(Arg->getType()); 5303 if (!CB->getType()->isVoidTy()) 5304 Types.push_back(CB->getType()); 5305 5306 // Simple types are always ABI compatible. 5307 auto IsSimpleTy = [](Type *Ty) { 5308 return !Ty->isVectorTy() && !Ty->isAggregateType(); 5309 }; 5310 if (all_of(Types, IsSimpleTy)) 5311 continue; 5312 5313 if (Function *NestedCallee = CB->getCalledFunction()) { 5314 // Assume that intrinsics are always ABI compatible. 5315 if (NestedCallee->isIntrinsic()) 5316 continue; 5317 5318 // Do a precise compatibility check. 5319 if (!areTypesABICompatible(Caller, NestedCallee, Types)) 5320 return false; 5321 } else { 5322 // We don't know the target features of the callee, 5323 // assume it is incompatible. 5324 return false; 5325 } 5326 } 5327 } 5328 return true; 5329 } 5330 5331 bool X86TTIImpl::areTypesABICompatible(const Function *Caller, 5332 const Function *Callee, 5333 const ArrayRef<Type *> &Types) const { 5334 if (!BaseT::areTypesABICompatible(Caller, Callee, Types)) 5335 return false; 5336 5337 // If we get here, we know the target features match. If one function 5338 // considers 512-bit vectors legal and the other does not, consider them 5339 // incompatible. 5340 const TargetMachine &TM = getTLI()->getTargetMachine(); 5341 5342 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 5343 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs()) 5344 return true; 5345 5346 // Consider the arguments compatible if they aren't vectors or aggregates. 5347 // FIXME: Look at the size of vectors. 5348 // FIXME: Look at the element types of aggregates to see if there are vectors. 5349 return llvm::none_of(Types, 5350 [](Type *T) { return T->isVectorTy() || T->isAggregateType(); }); 5351 } 5352 5353 X86TTIImpl::TTI::MemCmpExpansionOptions 5354 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 5355 TTI::MemCmpExpansionOptions Options; 5356 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 5357 Options.NumLoadsPerBlock = 2; 5358 // All GPR and vector loads can be unaligned. 5359 Options.AllowOverlappingLoads = true; 5360 if (IsZeroCmp) { 5361 // Only enable vector loads for equality comparison. Right now the vector 5362 // version is not as fast for three way compare (see #33329). 5363 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 5364 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 5365 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 5366 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 5367 } 5368 if (ST->is64Bit()) { 5369 Options.LoadSizes.push_back(8); 5370 } 5371 Options.LoadSizes.push_back(4); 5372 Options.LoadSizes.push_back(2); 5373 Options.LoadSizes.push_back(1); 5374 return Options; 5375 } 5376 5377 bool X86TTIImpl::prefersVectorizedAddressing() const { 5378 return supportsGather(); 5379 } 5380 5381 bool X86TTIImpl::supportsEfficientVectorElementLoadStore() const { 5382 return false; 5383 } 5384 5385 bool X86TTIImpl::enableInterleavedAccessVectorization() { 5386 // TODO: We expect this to be beneficial regardless of arch, 5387 // but there are currently some unexplained performance artifacts on Atom. 5388 // As a temporary solution, disable on Atom. 5389 return !(ST->isAtom()); 5390 } 5391 5392 // Get estimation for interleaved load/store operations and strided load. 5393 // \p Indices contains indices for strided load. 5394 // \p Factor - the factor of interleaving. 5395 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 5396 InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX512( 5397 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 5398 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 5399 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 5400 // VecTy for interleave memop is <VF*Factor x Elt>. 5401 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 5402 // VecTy = <12 x i32>. 5403 5404 // Calculate the number of memory operations (NumOfMemOps), required 5405 // for load/store the VecTy. 5406 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 5407 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 5408 unsigned LegalVTSize = LegalVT.getStoreSize(); 5409 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 5410 5411 // Get the cost of one memory operation. 5412 auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(), 5413 LegalVT.getVectorNumElements()); 5414 InstructionCost MemOpCost; 5415 bool UseMaskedMemOp = UseMaskForCond || UseMaskForGaps; 5416 if (UseMaskedMemOp) 5417 MemOpCost = getMaskedMemoryOpCost(Opcode, SingleMemOpTy, Alignment, 5418 AddressSpace, CostKind); 5419 else 5420 MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, MaybeAlign(Alignment), 5421 AddressSpace, CostKind); 5422 5423 unsigned VF = VecTy->getNumElements() / Factor; 5424 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 5425 5426 InstructionCost MaskCost; 5427 if (UseMaskedMemOp) { 5428 APInt DemandedLoadStoreElts = APInt::getZero(VecTy->getNumElements()); 5429 for (unsigned Index : Indices) { 5430 assert(Index < Factor && "Invalid index for interleaved memory op"); 5431 for (unsigned Elm = 0; Elm < VF; Elm++) 5432 DemandedLoadStoreElts.setBit(Index + Elm * Factor); 5433 } 5434 5435 Type *I1Type = Type::getInt1Ty(VecTy->getContext()); 5436 5437 MaskCost = getReplicationShuffleCost( 5438 I1Type, Factor, VF, 5439 UseMaskForGaps ? DemandedLoadStoreElts 5440 : APInt::getAllOnes(VecTy->getNumElements()), 5441 CostKind); 5442 5443 // The Gaps mask is invariant and created outside the loop, therefore the 5444 // cost of creating it is not accounted for here. However if we have both 5445 // a MaskForGaps and some other mask that guards the execution of the 5446 // memory access, we need to account for the cost of And-ing the two masks 5447 // inside the loop. 5448 if (UseMaskForGaps) { 5449 auto *MaskVT = FixedVectorType::get(I1Type, VecTy->getNumElements()); 5450 MaskCost += getArithmeticInstrCost(BinaryOperator::And, MaskVT, CostKind); 5451 } 5452 } 5453 5454 if (Opcode == Instruction::Load) { 5455 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 5456 // contain the cost of the optimized shuffle sequence that the 5457 // X86InterleavedAccess pass will generate. 5458 // The cost of loads and stores are computed separately from the table. 5459 5460 // X86InterleavedAccess support only the following interleaved-access group. 5461 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 5462 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 5463 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 5464 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 5465 }; 5466 5467 if (const auto *Entry = 5468 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 5469 return MaskCost + NumOfMemOps * MemOpCost + Entry->Cost; 5470 //If an entry does not exist, fallback to the default implementation. 5471 5472 // Kind of shuffle depends on number of loaded values. 5473 // If we load the entire data in one register, we can use a 1-src shuffle. 5474 // Otherwise, we'll merge 2 sources in each operation. 5475 TTI::ShuffleKind ShuffleKind = 5476 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 5477 5478 InstructionCost ShuffleCost = 5479 getShuffleCost(ShuffleKind, SingleMemOpTy, None, 0, nullptr); 5480 5481 unsigned NumOfLoadsInInterleaveGrp = 5482 Indices.size() ? Indices.size() : Factor; 5483 auto *ResultTy = FixedVectorType::get(VecTy->getElementType(), 5484 VecTy->getNumElements() / Factor); 5485 InstructionCost NumOfResults = 5486 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 5487 NumOfLoadsInInterleaveGrp; 5488 5489 // About a half of the loads may be folded in shuffles when we have only 5490 // one result. If we have more than one result, or the loads are masked, 5491 // we do not fold loads at all. 5492 unsigned NumOfUnfoldedLoads = 5493 UseMaskedMemOp || NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 5494 5495 // Get a number of shuffle operations per result. 5496 unsigned NumOfShufflesPerResult = 5497 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 5498 5499 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 5500 // When we have more than one destination, we need additional instructions 5501 // to keep sources. 5502 InstructionCost NumOfMoves = 0; 5503 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 5504 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 5505 5506 InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 5507 MaskCost + NumOfUnfoldedLoads * MemOpCost + 5508 NumOfMoves; 5509 5510 return Cost; 5511 } 5512 5513 // Store. 5514 assert(Opcode == Instruction::Store && 5515 "Expected Store Instruction at this point"); 5516 // X86InterleavedAccess support only the following interleaved-access group. 5517 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 5518 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 5519 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 5520 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 5521 5522 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 5523 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 5524 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 5525 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 5526 }; 5527 5528 if (const auto *Entry = 5529 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 5530 return MaskCost + NumOfMemOps * MemOpCost + Entry->Cost; 5531 //If an entry does not exist, fallback to the default implementation. 5532 5533 // There is no strided stores meanwhile. And store can't be folded in 5534 // shuffle. 5535 unsigned NumOfSources = Factor; // The number of values to be merged. 5536 InstructionCost ShuffleCost = 5537 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, None, 0, nullptr); 5538 unsigned NumOfShufflesPerStore = NumOfSources - 1; 5539 5540 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 5541 // We need additional instructions to keep sources. 5542 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 5543 InstructionCost Cost = 5544 MaskCost + 5545 NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 5546 NumOfMoves; 5547 return Cost; 5548 } 5549 5550 InstructionCost X86TTIImpl::getInterleavedMemoryOpCost( 5551 unsigned Opcode, Type *BaseTy, unsigned Factor, ArrayRef<unsigned> Indices, 5552 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, 5553 bool UseMaskForCond, bool UseMaskForGaps) { 5554 auto *VecTy = cast<FixedVectorType>(BaseTy); 5555 5556 auto isSupportedOnAVX512 = [&](Type *VecTy, bool HasBW) { 5557 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 5558 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 5559 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 5560 return true; 5561 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8) || 5562 (!ST->useSoftFloat() && ST->hasFP16() && EltTy->isHalfTy())) 5563 return HasBW; 5564 return false; 5565 }; 5566 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 5567 return getInterleavedMemoryOpCostAVX512( 5568 Opcode, VecTy, Factor, Indices, Alignment, 5569 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 5570 5571 if (UseMaskForCond || UseMaskForGaps) 5572 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5573 Alignment, AddressSpace, CostKind, 5574 UseMaskForCond, UseMaskForGaps); 5575 5576 // Get estimation for interleaved load/store operations for SSE-AVX2. 5577 // As opposed to AVX-512, SSE-AVX2 do not have generic shuffles that allow 5578 // computing the cost using a generic formula as a function of generic 5579 // shuffles. We therefore use a lookup table instead, filled according to 5580 // the instruction sequences that codegen currently generates. 5581 5582 // VecTy for interleave memop is <VF*Factor x Elt>. 5583 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 5584 // VecTy = <12 x i32>. 5585 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 5586 5587 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 5588 // the VF=2, while v2i128 is an unsupported MVT vector type 5589 // (see MachineValueType.h::getVectorVT()). 5590 if (!LegalVT.isVector()) 5591 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5592 Alignment, AddressSpace, CostKind); 5593 5594 unsigned VF = VecTy->getNumElements() / Factor; 5595 Type *ScalarTy = VecTy->getElementType(); 5596 // Deduplicate entries, model floats/pointers as appropriately-sized integers. 5597 if (!ScalarTy->isIntegerTy()) 5598 ScalarTy = 5599 Type::getIntNTy(ScalarTy->getContext(), DL.getTypeSizeInBits(ScalarTy)); 5600 5601 // Get the cost of all the memory operations. 5602 // FIXME: discount dead loads. 5603 InstructionCost MemOpCosts = getMemoryOpCost( 5604 Opcode, VecTy, MaybeAlign(Alignment), AddressSpace, CostKind); 5605 5606 auto *VT = FixedVectorType::get(ScalarTy, VF); 5607 EVT ETy = TLI->getValueType(DL, VT); 5608 if (!ETy.isSimple()) 5609 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5610 Alignment, AddressSpace, CostKind); 5611 5612 // TODO: Complete for other data-types and strides. 5613 // Each combination of Stride, element bit width and VF results in a different 5614 // sequence; The cost tables are therefore accessed with: 5615 // Factor (stride) and VectorType=VFxiN. 5616 // The Cost accounts only for the shuffle sequence; 5617 // The cost of the loads/stores is accounted for separately. 5618 // 5619 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 5620 {2, MVT::v2i8, 2}, // (load 4i8 and) deinterleave into 2 x 2i8 5621 {2, MVT::v4i8, 2}, // (load 8i8 and) deinterleave into 2 x 4i8 5622 {2, MVT::v8i8, 2}, // (load 16i8 and) deinterleave into 2 x 8i8 5623 {2, MVT::v16i8, 4}, // (load 32i8 and) deinterleave into 2 x 16i8 5624 {2, MVT::v32i8, 6}, // (load 64i8 and) deinterleave into 2 x 32i8 5625 5626 {2, MVT::v8i16, 6}, // (load 16i16 and) deinterleave into 2 x 8i16 5627 {2, MVT::v16i16, 9}, // (load 32i16 and) deinterleave into 2 x 16i16 5628 {2, MVT::v32i16, 18}, // (load 64i16 and) deinterleave into 2 x 32i16 5629 5630 {2, MVT::v8i32, 4}, // (load 16i32 and) deinterleave into 2 x 8i32 5631 {2, MVT::v16i32, 8}, // (load 32i32 and) deinterleave into 2 x 16i32 5632 {2, MVT::v32i32, 16}, // (load 64i32 and) deinterleave into 2 x 32i32 5633 5634 {2, MVT::v4i64, 4}, // (load 8i64 and) deinterleave into 2 x 4i64 5635 {2, MVT::v8i64, 8}, // (load 16i64 and) deinterleave into 2 x 8i64 5636 {2, MVT::v16i64, 16}, // (load 32i64 and) deinterleave into 2 x 16i64 5637 {2, MVT::v32i64, 32}, // (load 64i64 and) deinterleave into 2 x 32i64 5638 5639 {3, MVT::v2i8, 3}, // (load 6i8 and) deinterleave into 3 x 2i8 5640 {3, MVT::v4i8, 3}, // (load 12i8 and) deinterleave into 3 x 4i8 5641 {3, MVT::v8i8, 6}, // (load 24i8 and) deinterleave into 3 x 8i8 5642 {3, MVT::v16i8, 11}, // (load 48i8 and) deinterleave into 3 x 16i8 5643 {3, MVT::v32i8, 14}, // (load 96i8 and) deinterleave into 3 x 32i8 5644 5645 {3, MVT::v2i16, 5}, // (load 6i16 and) deinterleave into 3 x 2i16 5646 {3, MVT::v4i16, 7}, // (load 12i16 and) deinterleave into 3 x 4i16 5647 {3, MVT::v8i16, 9}, // (load 24i16 and) deinterleave into 3 x 8i16 5648 {3, MVT::v16i16, 28}, // (load 48i16 and) deinterleave into 3 x 16i16 5649 {3, MVT::v32i16, 56}, // (load 96i16 and) deinterleave into 3 x 32i16 5650 5651 {3, MVT::v2i32, 3}, // (load 6i32 and) deinterleave into 3 x 2i32 5652 {3, MVT::v4i32, 3}, // (load 12i32 and) deinterleave into 3 x 4i32 5653 {3, MVT::v8i32, 7}, // (load 24i32 and) deinterleave into 3 x 8i32 5654 {3, MVT::v16i32, 14}, // (load 48i32 and) deinterleave into 3 x 16i32 5655 {3, MVT::v32i32, 32}, // (load 96i32 and) deinterleave into 3 x 32i32 5656 5657 {3, MVT::v2i64, 1}, // (load 6i64 and) deinterleave into 3 x 2i64 5658 {3, MVT::v4i64, 5}, // (load 12i64 and) deinterleave into 3 x 4i64 5659 {3, MVT::v8i64, 10}, // (load 24i64 and) deinterleave into 3 x 8i64 5660 {3, MVT::v16i64, 20}, // (load 48i64 and) deinterleave into 3 x 16i64 5661 5662 {4, MVT::v2i8, 4}, // (load 8i8 and) deinterleave into 4 x 2i8 5663 {4, MVT::v4i8, 4}, // (load 16i8 and) deinterleave into 4 x 4i8 5664 {4, MVT::v8i8, 12}, // (load 32i8 and) deinterleave into 4 x 8i8 5665 {4, MVT::v16i8, 24}, // (load 64i8 and) deinterleave into 4 x 16i8 5666 {4, MVT::v32i8, 56}, // (load 128i8 and) deinterleave into 4 x 32i8 5667 5668 {4, MVT::v2i16, 6}, // (load 8i16 and) deinterleave into 4 x 2i16 5669 {4, MVT::v4i16, 17}, // (load 16i16 and) deinterleave into 4 x 4i16 5670 {4, MVT::v8i16, 33}, // (load 32i16 and) deinterleave into 4 x 8i16 5671 {4, MVT::v16i16, 75}, // (load 64i16 and) deinterleave into 4 x 16i16 5672 {4, MVT::v32i16, 150}, // (load 128i16 and) deinterleave into 4 x 32i16 5673 5674 {4, MVT::v2i32, 4}, // (load 8i32 and) deinterleave into 4 x 2i32 5675 {4, MVT::v4i32, 8}, // (load 16i32 and) deinterleave into 4 x 4i32 5676 {4, MVT::v8i32, 16}, // (load 32i32 and) deinterleave into 4 x 8i32 5677 {4, MVT::v16i32, 32}, // (load 64i32 and) deinterleave into 4 x 16i32 5678 {4, MVT::v32i32, 68}, // (load 128i32 and) deinterleave into 4 x 32i32 5679 5680 {4, MVT::v2i64, 6}, // (load 8i64 and) deinterleave into 4 x 2i64 5681 {4, MVT::v4i64, 8}, // (load 16i64 and) deinterleave into 4 x 4i64 5682 {4, MVT::v8i64, 20}, // (load 32i64 and) deinterleave into 4 x 8i64 5683 {4, MVT::v16i64, 40}, // (load 64i64 and) deinterleave into 4 x 16i64 5684 5685 {6, MVT::v2i8, 6}, // (load 12i8 and) deinterleave into 6 x 2i8 5686 {6, MVT::v4i8, 14}, // (load 24i8 and) deinterleave into 6 x 4i8 5687 {6, MVT::v8i8, 18}, // (load 48i8 and) deinterleave into 6 x 8i8 5688 {6, MVT::v16i8, 43}, // (load 96i8 and) deinterleave into 6 x 16i8 5689 {6, MVT::v32i8, 82}, // (load 192i8 and) deinterleave into 6 x 32i8 5690 5691 {6, MVT::v2i16, 13}, // (load 12i16 and) deinterleave into 6 x 2i16 5692 {6, MVT::v4i16, 9}, // (load 24i16 and) deinterleave into 6 x 4i16 5693 {6, MVT::v8i16, 39}, // (load 48i16 and) deinterleave into 6 x 8i16 5694 {6, MVT::v16i16, 106}, // (load 96i16 and) deinterleave into 6 x 16i16 5695 {6, MVT::v32i16, 212}, // (load 192i16 and) deinterleave into 6 x 32i16 5696 5697 {6, MVT::v2i32, 6}, // (load 12i32 and) deinterleave into 6 x 2i32 5698 {6, MVT::v4i32, 15}, // (load 24i32 and) deinterleave into 6 x 4i32 5699 {6, MVT::v8i32, 31}, // (load 48i32 and) deinterleave into 6 x 8i32 5700 {6, MVT::v16i32, 64}, // (load 96i32 and) deinterleave into 6 x 16i32 5701 5702 {6, MVT::v2i64, 6}, // (load 12i64 and) deinterleave into 6 x 2i64 5703 {6, MVT::v4i64, 18}, // (load 24i64 and) deinterleave into 6 x 4i64 5704 {6, MVT::v8i64, 36}, // (load 48i64 and) deinterleave into 6 x 8i64 5705 5706 {8, MVT::v8i32, 40} // (load 64i32 and) deinterleave into 8 x 8i32 5707 }; 5708 5709 static const CostTblEntry SSSE3InterleavedLoadTbl[] = { 5710 {2, MVT::v4i16, 2}, // (load 8i16 and) deinterleave into 2 x 4i16 5711 }; 5712 5713 static const CostTblEntry SSE2InterleavedLoadTbl[] = { 5714 {2, MVT::v2i16, 2}, // (load 4i16 and) deinterleave into 2 x 2i16 5715 {2, MVT::v4i16, 7}, // (load 8i16 and) deinterleave into 2 x 4i16 5716 5717 {2, MVT::v2i32, 2}, // (load 4i32 and) deinterleave into 2 x 2i32 5718 {2, MVT::v4i32, 2}, // (load 8i32 and) deinterleave into 2 x 4i32 5719 5720 {2, MVT::v2i64, 2}, // (load 4i64 and) deinterleave into 2 x 2i64 5721 }; 5722 5723 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 5724 {2, MVT::v16i8, 3}, // interleave 2 x 16i8 into 32i8 (and store) 5725 {2, MVT::v32i8, 4}, // interleave 2 x 32i8 into 64i8 (and store) 5726 5727 {2, MVT::v8i16, 3}, // interleave 2 x 8i16 into 16i16 (and store) 5728 {2, MVT::v16i16, 4}, // interleave 2 x 16i16 into 32i16 (and store) 5729 {2, MVT::v32i16, 8}, // interleave 2 x 32i16 into 64i16 (and store) 5730 5731 {2, MVT::v4i32, 2}, // interleave 2 x 4i32 into 8i32 (and store) 5732 {2, MVT::v8i32, 4}, // interleave 2 x 8i32 into 16i32 (and store) 5733 {2, MVT::v16i32, 8}, // interleave 2 x 16i32 into 32i32 (and store) 5734 {2, MVT::v32i32, 16}, // interleave 2 x 32i32 into 64i32 (and store) 5735 5736 {2, MVT::v2i64, 2}, // interleave 2 x 2i64 into 4i64 (and store) 5737 {2, MVT::v4i64, 4}, // interleave 2 x 4i64 into 8i64 (and store) 5738 {2, MVT::v8i64, 8}, // interleave 2 x 8i64 into 16i64 (and store) 5739 {2, MVT::v16i64, 16}, // interleave 2 x 16i64 into 32i64 (and store) 5740 {2, MVT::v32i64, 32}, // interleave 2 x 32i64 into 64i64 (and store) 5741 5742 {3, MVT::v2i8, 4}, // interleave 3 x 2i8 into 6i8 (and store) 5743 {3, MVT::v4i8, 4}, // interleave 3 x 4i8 into 12i8 (and store) 5744 {3, MVT::v8i8, 6}, // interleave 3 x 8i8 into 24i8 (and store) 5745 {3, MVT::v16i8, 11}, // interleave 3 x 16i8 into 48i8 (and store) 5746 {3, MVT::v32i8, 13}, // interleave 3 x 32i8 into 96i8 (and store) 5747 5748 {3, MVT::v2i16, 4}, // interleave 3 x 2i16 into 6i16 (and store) 5749 {3, MVT::v4i16, 6}, // interleave 3 x 4i16 into 12i16 (and store) 5750 {3, MVT::v8i16, 12}, // interleave 3 x 8i16 into 24i16 (and store) 5751 {3, MVT::v16i16, 27}, // interleave 3 x 16i16 into 48i16 (and store) 5752 {3, MVT::v32i16, 54}, // interleave 3 x 32i16 into 96i16 (and store) 5753 5754 {3, MVT::v2i32, 4}, // interleave 3 x 2i32 into 6i32 (and store) 5755 {3, MVT::v4i32, 5}, // interleave 3 x 4i32 into 12i32 (and store) 5756 {3, MVT::v8i32, 11}, // interleave 3 x 8i32 into 24i32 (and store) 5757 {3, MVT::v16i32, 22}, // interleave 3 x 16i32 into 48i32 (and store) 5758 {3, MVT::v32i32, 48}, // interleave 3 x 32i32 into 96i32 (and store) 5759 5760 {3, MVT::v2i64, 4}, // interleave 3 x 2i64 into 6i64 (and store) 5761 {3, MVT::v4i64, 6}, // interleave 3 x 4i64 into 12i64 (and store) 5762 {3, MVT::v8i64, 12}, // interleave 3 x 8i64 into 24i64 (and store) 5763 {3, MVT::v16i64, 24}, // interleave 3 x 16i64 into 48i64 (and store) 5764 5765 {4, MVT::v2i8, 4}, // interleave 4 x 2i8 into 8i8 (and store) 5766 {4, MVT::v4i8, 4}, // interleave 4 x 4i8 into 16i8 (and store) 5767 {4, MVT::v8i8, 4}, // interleave 4 x 8i8 into 32i8 (and store) 5768 {4, MVT::v16i8, 8}, // interleave 4 x 16i8 into 64i8 (and store) 5769 {4, MVT::v32i8, 12}, // interleave 4 x 32i8 into 128i8 (and store) 5770 5771 {4, MVT::v2i16, 2}, // interleave 4 x 2i16 into 8i16 (and store) 5772 {4, MVT::v4i16, 6}, // interleave 4 x 4i16 into 16i16 (and store) 5773 {4, MVT::v8i16, 10}, // interleave 4 x 8i16 into 32i16 (and store) 5774 {4, MVT::v16i16, 32}, // interleave 4 x 16i16 into 64i16 (and store) 5775 {4, MVT::v32i16, 64}, // interleave 4 x 32i16 into 128i16 (and store) 5776 5777 {4, MVT::v2i32, 5}, // interleave 4 x 2i32 into 8i32 (and store) 5778 {4, MVT::v4i32, 6}, // interleave 4 x 4i32 into 16i32 (and store) 5779 {4, MVT::v8i32, 16}, // interleave 4 x 8i32 into 32i32 (and store) 5780 {4, MVT::v16i32, 32}, // interleave 4 x 16i32 into 64i32 (and store) 5781 {4, MVT::v32i32, 64}, // interleave 4 x 32i32 into 128i32 (and store) 5782 5783 {4, MVT::v2i64, 6}, // interleave 4 x 2i64 into 8i64 (and store) 5784 {4, MVT::v4i64, 8}, // interleave 4 x 4i64 into 16i64 (and store) 5785 {4, MVT::v8i64, 20}, // interleave 4 x 8i64 into 32i64 (and store) 5786 {4, MVT::v16i64, 40}, // interleave 4 x 16i64 into 64i64 (and store) 5787 5788 {6, MVT::v2i8, 7}, // interleave 6 x 2i8 into 12i8 (and store) 5789 {6, MVT::v4i8, 9}, // interleave 6 x 4i8 into 24i8 (and store) 5790 {6, MVT::v8i8, 16}, // interleave 6 x 8i8 into 48i8 (and store) 5791 {6, MVT::v16i8, 27}, // interleave 6 x 16i8 into 96i8 (and store) 5792 {6, MVT::v32i8, 90}, // interleave 6 x 32i8 into 192i8 (and store) 5793 5794 {6, MVT::v2i16, 10}, // interleave 6 x 2i16 into 12i16 (and store) 5795 {6, MVT::v4i16, 15}, // interleave 6 x 4i16 into 24i16 (and store) 5796 {6, MVT::v8i16, 21}, // interleave 6 x 8i16 into 48i16 (and store) 5797 {6, MVT::v16i16, 58}, // interleave 6 x 16i16 into 96i16 (and store) 5798 {6, MVT::v32i16, 90}, // interleave 6 x 32i16 into 192i16 (and store) 5799 5800 {6, MVT::v2i32, 9}, // interleave 6 x 2i32 into 12i32 (and store) 5801 {6, MVT::v4i32, 12}, // interleave 6 x 4i32 into 24i32 (and store) 5802 {6, MVT::v8i32, 33}, // interleave 6 x 8i32 into 48i32 (and store) 5803 {6, MVT::v16i32, 66}, // interleave 6 x 16i32 into 96i32 (and store) 5804 5805 {6, MVT::v2i64, 8}, // interleave 6 x 2i64 into 12i64 (and store) 5806 {6, MVT::v4i64, 15}, // interleave 6 x 4i64 into 24i64 (and store) 5807 {6, MVT::v8i64, 30}, // interleave 6 x 8i64 into 48i64 (and store) 5808 }; 5809 5810 static const CostTblEntry SSE2InterleavedStoreTbl[] = { 5811 {2, MVT::v2i8, 1}, // interleave 2 x 2i8 into 4i8 (and store) 5812 {2, MVT::v4i8, 1}, // interleave 2 x 4i8 into 8i8 (and store) 5813 {2, MVT::v8i8, 1}, // interleave 2 x 8i8 into 16i8 (and store) 5814 5815 {2, MVT::v2i16, 1}, // interleave 2 x 2i16 into 4i16 (and store) 5816 {2, MVT::v4i16, 1}, // interleave 2 x 4i16 into 8i16 (and store) 5817 5818 {2, MVT::v2i32, 1}, // interleave 2 x 2i32 into 4i32 (and store) 5819 }; 5820 5821 if (Opcode == Instruction::Load) { 5822 auto GetDiscountedCost = [Factor, NumMembers = Indices.size(), 5823 MemOpCosts](const CostTblEntry *Entry) { 5824 // NOTE: this is just an approximation! 5825 // It can over/under -estimate the cost! 5826 return MemOpCosts + divideCeil(NumMembers * Entry->Cost, Factor); 5827 }; 5828 5829 if (ST->hasAVX2()) 5830 if (const auto *Entry = CostTableLookup(AVX2InterleavedLoadTbl, Factor, 5831 ETy.getSimpleVT())) 5832 return GetDiscountedCost(Entry); 5833 5834 if (ST->hasSSSE3()) 5835 if (const auto *Entry = CostTableLookup(SSSE3InterleavedLoadTbl, Factor, 5836 ETy.getSimpleVT())) 5837 return GetDiscountedCost(Entry); 5838 5839 if (ST->hasSSE2()) 5840 if (const auto *Entry = CostTableLookup(SSE2InterleavedLoadTbl, Factor, 5841 ETy.getSimpleVT())) 5842 return GetDiscountedCost(Entry); 5843 } else { 5844 assert(Opcode == Instruction::Store && 5845 "Expected Store Instruction at this point"); 5846 assert((!Indices.size() || Indices.size() == Factor) && 5847 "Interleaved store only supports fully-interleaved groups."); 5848 if (ST->hasAVX2()) 5849 if (const auto *Entry = CostTableLookup(AVX2InterleavedStoreTbl, Factor, 5850 ETy.getSimpleVT())) 5851 return MemOpCosts + Entry->Cost; 5852 5853 if (ST->hasSSE2()) 5854 if (const auto *Entry = CostTableLookup(SSE2InterleavedStoreTbl, Factor, 5855 ETy.getSimpleVT())) 5856 return MemOpCosts + Entry->Cost; 5857 } 5858 5859 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5860 Alignment, AddressSpace, CostKind, 5861 UseMaskForCond, UseMaskForGaps); 5862 } 5863