1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // X86 cost model. 56 // 57 //===----------------------------------------------------------------------===// 58 59 TargetTransformInfo::PopcntSupportKind 60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 61 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 62 // TODO: Currently the __builtin_popcount() implementation using SSE3 63 // instructions is inefficient. Once the problem is fixed, we should 64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 66 } 67 68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 69 TargetTransformInfo::CacheLevel Level) const { 70 switch (Level) { 71 case TargetTransformInfo::CacheLevel::L1D: 72 // - Penryn 73 // - Nehalem 74 // - Westmere 75 // - Sandy Bridge 76 // - Ivy Bridge 77 // - Haswell 78 // - Broadwell 79 // - Skylake 80 // - Kabylake 81 return 32 * 1024; // 32 KByte 82 case TargetTransformInfo::CacheLevel::L2D: 83 // - Penryn 84 // - Nehalem 85 // - Westmere 86 // - Sandy Bridge 87 // - Ivy Bridge 88 // - Haswell 89 // - Broadwell 90 // - Skylake 91 // - Kabylake 92 return 256 * 1024; // 256 KByte 93 } 94 95 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 96 } 97 98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 99 TargetTransformInfo::CacheLevel Level) const { 100 // - Penryn 101 // - Nehalem 102 // - Westmere 103 // - Sandy Bridge 104 // - Ivy Bridge 105 // - Haswell 106 // - Broadwell 107 // - Skylake 108 // - Kabylake 109 switch (Level) { 110 case TargetTransformInfo::CacheLevel::L1D: 111 LLVM_FALLTHROUGH; 112 case TargetTransformInfo::CacheLevel::L2D: 113 return 8; 114 } 115 116 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 117 } 118 119 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 120 bool Vector = (ClassID == 1); 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const { 133 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 134 if (Vector) { 135 if (ST->hasAVX512() && PreferVectorWidth >= 512) 136 return 512; 137 if (ST->hasAVX() && PreferVectorWidth >= 256) 138 return 256; 139 if (ST->hasSSE1() && PreferVectorWidth >= 128) 140 return 128; 141 return 0; 142 } 143 144 if (ST->is64Bit()) 145 return 64; 146 147 return 32; 148 } 149 150 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 151 return getRegisterBitWidth(true); 152 } 153 154 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 155 // If the loop will not be vectorized, don't interleave the loop. 156 // Let regular unroll to unroll the loop, which saves the overflow 157 // check and memory check cost. 158 if (VF == 1) 159 return 1; 160 161 if (ST->isAtom()) 162 return 1; 163 164 // Sandybridge and Haswell have multiple execution ports and pipelined 165 // vector units. 166 if (ST->hasAVX()) 167 return 4; 168 169 return 2; 170 } 171 172 int X86TTIImpl::getArithmeticInstrCost(unsigned Opcode, Type *Ty, 173 TTI::OperandValueKind Op1Info, 174 TTI::OperandValueKind Op2Info, 175 TTI::OperandValueProperties Opd1PropInfo, 176 TTI::OperandValueProperties Opd2PropInfo, 177 ArrayRef<const Value *> Args, 178 const Instruction *CxtI) { 179 // Legalize the type. 180 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 181 182 int ISD = TLI->InstructionOpcodeToISD(Opcode); 183 assert(ISD && "Invalid opcode"); 184 185 static const CostTblEntry GLMCostTable[] = { 186 { ISD::FDIV, MVT::f32, 18 }, // divss 187 { ISD::FDIV, MVT::v4f32, 35 }, // divps 188 { ISD::FDIV, MVT::f64, 33 }, // divsd 189 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 190 }; 191 192 if (ST->useGLMDivSqrtCosts()) 193 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 194 LT.second)) 195 return LT.first * Entry->Cost; 196 197 static const CostTblEntry SLMCostTable[] = { 198 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 199 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 200 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. 201 { ISD::FMUL, MVT::f64, 2 }, // mulsd 202 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 203 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 204 { ISD::FDIV, MVT::f32, 17 }, // divss 205 { ISD::FDIV, MVT::v4f32, 39 }, // divps 206 { ISD::FDIV, MVT::f64, 32 }, // divsd 207 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 208 { ISD::FADD, MVT::v2f64, 2 }, // addpd 209 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 210 // v2i64/v4i64 mul is custom lowered as a series of long: 211 // multiplies(3), shifts(3) and adds(2) 212 // slm muldq version throughput is 2 and addq throughput 4 213 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 214 // 3X4 (addq throughput) = 17 215 { ISD::MUL, MVT::v2i64, 17 }, 216 // slm addq\subq throughput is 4 217 { ISD::ADD, MVT::v2i64, 4 }, 218 { ISD::SUB, MVT::v2i64, 4 }, 219 }; 220 221 if (ST->isSLM()) { 222 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 223 // Check if the operands can be shrinked into a smaller datatype. 224 bool Op1Signed = false; 225 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 226 bool Op2Signed = false; 227 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 228 229 bool signedMode = Op1Signed | Op2Signed; 230 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 231 232 if (OpMinSize <= 7) 233 return LT.first * 3; // pmullw/sext 234 if (!signedMode && OpMinSize <= 8) 235 return LT.first * 3; // pmullw/zext 236 if (OpMinSize <= 15) 237 return LT.first * 5; // pmullw/pmulhw/pshuf 238 if (!signedMode && OpMinSize <= 16) 239 return LT.first * 5; // pmullw/pmulhw/pshuf 240 } 241 242 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 243 LT.second)) { 244 return LT.first * Entry->Cost; 245 } 246 } 247 248 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 249 ISD == ISD::UREM) && 250 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 251 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 252 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 253 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 254 // On X86, vector signed division by constants power-of-two are 255 // normally expanded to the sequence SRA + SRL + ADD + SRA. 256 // The OperandValue properties may not be the same as that of the previous 257 // operation; conservatively assume OP_None. 258 int Cost = 259 2 * getArithmeticInstrCost(Instruction::AShr, Ty, Op1Info, Op2Info, 260 TargetTransformInfo::OP_None, 261 TargetTransformInfo::OP_None); 262 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 263 TargetTransformInfo::OP_None, 264 TargetTransformInfo::OP_None); 265 Cost += getArithmeticInstrCost(Instruction::Add, Ty, Op1Info, Op2Info, 266 TargetTransformInfo::OP_None, 267 TargetTransformInfo::OP_None); 268 269 if (ISD == ISD::SREM) { 270 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 271 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info); 272 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, Op1Info, Op2Info); 273 } 274 275 return Cost; 276 } 277 278 // Vector unsigned division/remainder will be simplified to shifts/masks. 279 if (ISD == ISD::UDIV) 280 return getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 281 TargetTransformInfo::OP_None, 282 TargetTransformInfo::OP_None); 283 284 else // UREM 285 return getArithmeticInstrCost(Instruction::And, Ty, Op1Info, Op2Info, 286 TargetTransformInfo::OP_None, 287 TargetTransformInfo::OP_None); 288 } 289 290 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 291 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 292 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 293 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 294 }; 295 296 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 297 ST->hasBWI()) { 298 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 299 LT.second)) 300 return LT.first * Entry->Cost; 301 } 302 303 static const CostTblEntry AVX512UniformConstCostTable[] = { 304 { ISD::SRA, MVT::v2i64, 1 }, 305 { ISD::SRA, MVT::v4i64, 1 }, 306 { ISD::SRA, MVT::v8i64, 1 }, 307 }; 308 309 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 310 ST->hasAVX512()) { 311 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 312 LT.second)) 313 return LT.first * Entry->Cost; 314 } 315 316 static const CostTblEntry AVX2UniformConstCostTable[] = { 317 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 318 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 319 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 320 321 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 322 }; 323 324 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 325 ST->hasAVX2()) { 326 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 327 LT.second)) 328 return LT.first * Entry->Cost; 329 } 330 331 static const CostTblEntry SSE2UniformConstCostTable[] = { 332 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 333 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 334 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 335 336 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 337 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 338 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 339 }; 340 341 // XOP has faster vXi8 shifts. 342 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 343 ST->hasSSE2() && !ST->hasXOP()) { 344 if (const auto *Entry = 345 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 346 return LT.first * Entry->Cost; 347 } 348 349 static const CostTblEntry AVX512BWConstCostTable[] = { 350 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 351 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 352 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 353 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 354 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 355 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 356 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 357 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 358 }; 359 360 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 361 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 362 ST->hasBWI()) { 363 if (const auto *Entry = 364 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 365 return LT.first * Entry->Cost; 366 } 367 368 static const CostTblEntry AVX512ConstCostTable[] = { 369 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 370 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 371 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 372 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 373 }; 374 375 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 376 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 377 ST->hasAVX512()) { 378 if (const auto *Entry = 379 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 380 return LT.first * Entry->Cost; 381 } 382 383 static const CostTblEntry AVX2ConstCostTable[] = { 384 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 385 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 386 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 387 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 388 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 389 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 390 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 391 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 392 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 393 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 394 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 395 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 396 }; 397 398 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 399 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 400 ST->hasAVX2()) { 401 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 402 return LT.first * Entry->Cost; 403 } 404 405 static const CostTblEntry SSE2ConstCostTable[] = { 406 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 407 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 408 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 409 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 410 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 411 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 412 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 413 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 414 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 415 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 416 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 417 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 418 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 419 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 420 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 421 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 422 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 423 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 424 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 425 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 426 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 427 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 428 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 429 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 430 }; 431 432 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 433 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 434 ST->hasSSE2()) { 435 // pmuldq sequence. 436 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 437 return LT.first * 32; 438 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 439 return LT.first * 38; 440 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 441 return LT.first * 15; 442 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 443 return LT.first * 20; 444 445 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 446 return LT.first * Entry->Cost; 447 } 448 449 static const CostTblEntry AVX2UniformCostTable[] = { 450 // Uniform splats are cheaper for the following instructions. 451 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 452 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 453 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 454 }; 455 456 if (ST->hasAVX2() && 457 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 458 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 459 if (const auto *Entry = 460 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 461 return LT.first * Entry->Cost; 462 } 463 464 static const CostTblEntry SSE2UniformCostTable[] = { 465 // Uniform splats are cheaper for the following instructions. 466 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 467 { ISD::SHL, MVT::v4i32, 1 }, // pslld 468 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 469 470 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 471 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 472 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 473 474 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 475 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 476 }; 477 478 if (ST->hasSSE2() && 479 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 480 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 481 if (const auto *Entry = 482 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 483 return LT.first * Entry->Cost; 484 } 485 486 static const CostTblEntry AVX512DQCostTable[] = { 487 { ISD::MUL, MVT::v2i64, 1 }, 488 { ISD::MUL, MVT::v4i64, 1 }, 489 { ISD::MUL, MVT::v8i64, 1 } 490 }; 491 492 // Look for AVX512DQ lowering tricks for custom cases. 493 if (ST->hasDQI()) 494 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 495 return LT.first * Entry->Cost; 496 497 static const CostTblEntry AVX512BWCostTable[] = { 498 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 499 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 500 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 501 502 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 503 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 504 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 505 506 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 507 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 508 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 509 510 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 511 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 512 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 513 514 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence. 515 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence. 516 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence. 517 }; 518 519 // Look for AVX512BW lowering tricks for custom cases. 520 if (ST->hasBWI()) 521 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 522 return LT.first * Entry->Cost; 523 524 static const CostTblEntry AVX512CostTable[] = { 525 { ISD::SHL, MVT::v16i32, 1 }, 526 { ISD::SRL, MVT::v16i32, 1 }, 527 { ISD::SRA, MVT::v16i32, 1 }, 528 529 { ISD::SHL, MVT::v8i64, 1 }, 530 { ISD::SRL, MVT::v8i64, 1 }, 531 532 { ISD::SRA, MVT::v2i64, 1 }, 533 { ISD::SRA, MVT::v4i64, 1 }, 534 { ISD::SRA, MVT::v8i64, 1 }, 535 536 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence. 537 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence. 538 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 539 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 540 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 541 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add 542 543 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 544 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 545 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 546 547 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 548 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 549 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 550 }; 551 552 if (ST->hasAVX512()) 553 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 554 return LT.first * Entry->Cost; 555 556 static const CostTblEntry AVX2ShiftCostTable[] = { 557 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 558 // customize them to detect the cases where shift amount is a scalar one. 559 { ISD::SHL, MVT::v4i32, 1 }, 560 { ISD::SRL, MVT::v4i32, 1 }, 561 { ISD::SRA, MVT::v4i32, 1 }, 562 { ISD::SHL, MVT::v8i32, 1 }, 563 { ISD::SRL, MVT::v8i32, 1 }, 564 { ISD::SRA, MVT::v8i32, 1 }, 565 { ISD::SHL, MVT::v2i64, 1 }, 566 { ISD::SRL, MVT::v2i64, 1 }, 567 { ISD::SHL, MVT::v4i64, 1 }, 568 { ISD::SRL, MVT::v4i64, 1 }, 569 }; 570 571 // Look for AVX2 lowering tricks. 572 if (ST->hasAVX2()) { 573 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 574 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 575 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 576 // On AVX2, a packed v16i16 shift left by a constant build_vector 577 // is lowered into a vector multiply (vpmullw). 578 return getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info, 579 TargetTransformInfo::OP_None, 580 TargetTransformInfo::OP_None); 581 582 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 583 return LT.first * Entry->Cost; 584 } 585 586 static const CostTblEntry XOPShiftCostTable[] = { 587 // 128bit shifts take 1cy, but right shifts require negation beforehand. 588 { ISD::SHL, MVT::v16i8, 1 }, 589 { ISD::SRL, MVT::v16i8, 2 }, 590 { ISD::SRA, MVT::v16i8, 2 }, 591 { ISD::SHL, MVT::v8i16, 1 }, 592 { ISD::SRL, MVT::v8i16, 2 }, 593 { ISD::SRA, MVT::v8i16, 2 }, 594 { ISD::SHL, MVT::v4i32, 1 }, 595 { ISD::SRL, MVT::v4i32, 2 }, 596 { ISD::SRA, MVT::v4i32, 2 }, 597 { ISD::SHL, MVT::v2i64, 1 }, 598 { ISD::SRL, MVT::v2i64, 2 }, 599 { ISD::SRA, MVT::v2i64, 2 }, 600 // 256bit shifts require splitting if AVX2 didn't catch them above. 601 { ISD::SHL, MVT::v32i8, 2+2 }, 602 { ISD::SRL, MVT::v32i8, 4+2 }, 603 { ISD::SRA, MVT::v32i8, 4+2 }, 604 { ISD::SHL, MVT::v16i16, 2+2 }, 605 { ISD::SRL, MVT::v16i16, 4+2 }, 606 { ISD::SRA, MVT::v16i16, 4+2 }, 607 { ISD::SHL, MVT::v8i32, 2+2 }, 608 { ISD::SRL, MVT::v8i32, 4+2 }, 609 { ISD::SRA, MVT::v8i32, 4+2 }, 610 { ISD::SHL, MVT::v4i64, 2+2 }, 611 { ISD::SRL, MVT::v4i64, 4+2 }, 612 { ISD::SRA, MVT::v4i64, 4+2 }, 613 }; 614 615 // Look for XOP lowering tricks. 616 if (ST->hasXOP()) { 617 // If the right shift is constant then we'll fold the negation so 618 // it's as cheap as a left shift. 619 int ShiftISD = ISD; 620 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 621 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 622 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 623 ShiftISD = ISD::SHL; 624 if (const auto *Entry = 625 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 626 return LT.first * Entry->Cost; 627 } 628 629 static const CostTblEntry SSE2UniformShiftCostTable[] = { 630 // Uniform splats are cheaper for the following instructions. 631 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 632 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 633 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 634 635 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 636 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 637 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 638 639 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 640 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 641 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 642 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 643 }; 644 645 if (ST->hasSSE2() && 646 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 647 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 648 649 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 650 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 651 return LT.first * 4; // 2*psrad + shuffle. 652 653 if (const auto *Entry = 654 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 655 return LT.first * Entry->Cost; 656 } 657 658 if (ISD == ISD::SHL && 659 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 660 MVT VT = LT.second; 661 // Vector shift left by non uniform constant can be lowered 662 // into vector multiply. 663 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 664 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 665 ISD = ISD::MUL; 666 } 667 668 static const CostTblEntry AVX2CostTable[] = { 669 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. 670 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 671 672 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. 673 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 674 675 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. 676 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. 677 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. 678 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 679 680 { ISD::SUB, MVT::v32i8, 1 }, // psubb 681 { ISD::ADD, MVT::v32i8, 1 }, // paddb 682 { ISD::SUB, MVT::v16i16, 1 }, // psubw 683 { ISD::ADD, MVT::v16i16, 1 }, // paddw 684 { ISD::SUB, MVT::v8i32, 1 }, // psubd 685 { ISD::ADD, MVT::v8i32, 1 }, // paddd 686 { ISD::SUB, MVT::v4i64, 1 }, // psubq 687 { ISD::ADD, MVT::v4i64, 1 }, // paddq 688 689 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence. 690 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence. 691 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 692 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 693 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add 694 695 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 696 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 697 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 698 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 699 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 700 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 701 702 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 703 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 704 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 705 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 706 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 707 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 708 }; 709 710 // Look for AVX2 lowering tricks for custom cases. 711 if (ST->hasAVX2()) 712 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 713 return LT.first * Entry->Cost; 714 715 static const CostTblEntry AVX1CostTable[] = { 716 // We don't have to scalarize unsupported ops. We can issue two half-sized 717 // operations and we only need to extract the upper YMM half. 718 // Two ops + 1 extract + 1 insert = 4. 719 { ISD::MUL, MVT::v16i16, 4 }, 720 { ISD::MUL, MVT::v8i32, 4 }, 721 { ISD::SUB, MVT::v32i8, 4 }, 722 { ISD::ADD, MVT::v32i8, 4 }, 723 { ISD::SUB, MVT::v16i16, 4 }, 724 { ISD::ADD, MVT::v16i16, 4 }, 725 { ISD::SUB, MVT::v8i32, 4 }, 726 { ISD::ADD, MVT::v8i32, 4 }, 727 { ISD::SUB, MVT::v4i64, 4 }, 728 { ISD::ADD, MVT::v4i64, 4 }, 729 730 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 731 // are lowered as a series of long multiplies(3), shifts(3) and adds(2) 732 // Because we believe v4i64 to be a legal type, we must also include the 733 // extract+insert in the cost table. Therefore, the cost here is 18 734 // instead of 8. 735 { ISD::MUL, MVT::v4i64, 18 }, 736 737 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence. 738 739 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 740 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 741 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 742 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 743 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 744 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 745 }; 746 747 if (ST->hasAVX()) 748 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 749 return LT.first * Entry->Cost; 750 751 static const CostTblEntry SSE42CostTable[] = { 752 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 753 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 754 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 755 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 756 757 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 758 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 759 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 760 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 761 762 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 763 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 764 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 765 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 766 767 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 768 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 769 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 770 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 771 }; 772 773 if (ST->hasSSE42()) 774 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 775 return LT.first * Entry->Cost; 776 777 static const CostTblEntry SSE41CostTable[] = { 778 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 779 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split. 780 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 781 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 782 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 783 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split 784 785 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 786 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split. 787 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 788 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 789 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 790 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split. 791 792 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 793 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split. 794 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 795 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 796 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 797 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split. 798 799 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 800 }; 801 802 if (ST->hasSSE41()) 803 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 804 return LT.first * Entry->Cost; 805 806 static const CostTblEntry SSE2CostTable[] = { 807 // We don't correctly identify costs of casts because they are marked as 808 // custom. 809 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 810 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 811 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 812 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 813 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 814 815 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 816 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 817 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 818 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 819 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 820 821 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 822 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 823 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 824 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 825 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split. 826 827 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence. 828 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 829 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 830 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 831 832 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 833 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 834 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 835 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 836 837 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 838 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 839 840 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 841 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 842 }; 843 844 if (ST->hasSSE2()) 845 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 846 return LT.first * Entry->Cost; 847 848 static const CostTblEntry SSE1CostTable[] = { 849 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 850 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 851 852 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 853 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 854 855 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 856 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 857 858 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 859 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 860 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 861 862 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 863 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 864 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 865 }; 866 867 if (ST->hasSSE1()) 868 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 869 return LT.first * Entry->Cost; 870 871 // It is not a good idea to vectorize division. We have to scalarize it and 872 // in the process we will often end up having to spilling regular 873 // registers. The overhead of division is going to dominate most kernels 874 // anyways so try hard to prevent vectorization of division - it is 875 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 876 // to hide "20 cycles" for each lane. 877 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 878 ISD == ISD::UDIV || ISD == ISD::UREM)) { 879 int ScalarCost = getArithmeticInstrCost( 880 Opcode, Ty->getScalarType(), Op1Info, Op2Info, 881 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 882 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 883 } 884 885 // Fallback to the default implementation. 886 return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info); 887 } 888 889 int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, 890 Type *SubTp) { 891 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 892 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 893 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp); 894 895 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 896 if (Kind == TTI::SK_Transpose) 897 Kind = TTI::SK_PermuteTwoSrc; 898 899 // For Broadcasts we are splatting the first element from the first input 900 // register, so only need to reference that input and all the output 901 // registers are the same. 902 if (Kind == TTI::SK_Broadcast) 903 LT.first = 1; 904 905 // Subvector extractions are free if they start at the beginning of a 906 // vector and cheap if the subvectors are aligned. 907 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 908 int NumElts = LT.second.getVectorNumElements(); 909 if ((Index % NumElts) == 0) 910 return 0; 911 std::pair<int, MVT> SubLT = TLI->getTypeLegalizationCost(DL, SubTp); 912 if (SubLT.second.isVector()) { 913 int NumSubElts = SubLT.second.getVectorNumElements(); 914 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 915 return SubLT.first; 916 // Handle some cases for widening legalization. For now we only handle 917 // cases where the original subvector was naturally aligned and evenly 918 // fit in its legalized subvector type. 919 // FIXME: Remove some of the alignment restrictions. 920 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 921 // vectors. 922 int OrigSubElts = SubTp->getVectorNumElements(); 923 if (NumSubElts > OrigSubElts && 924 (Index % OrigSubElts) == 0 && (NumSubElts % OrigSubElts) == 0 && 925 LT.second.getVectorElementType() == 926 SubLT.second.getVectorElementType() && 927 LT.second.getVectorElementType().getSizeInBits() == 928 Tp->getVectorElementType()->getPrimitiveSizeInBits()) { 929 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 930 "Unexpected number of elements!"); 931 Type *VecTy = VectorType::get(Tp->getVectorElementType(), 932 LT.second.getVectorNumElements()); 933 Type *SubTy = VectorType::get(Tp->getVectorElementType(), 934 SubLT.second.getVectorNumElements()); 935 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 936 int ExtractCost = getShuffleCost(TTI::SK_ExtractSubvector, VecTy, 937 ExtractIndex, SubTy); 938 939 // If the original size is 32-bits or more, we can use pshufd. Otherwise 940 // if we have SSSE3 we can use pshufb. 941 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 942 return ExtractCost + 1; // pshufd or pshufb 943 944 assert(SubTp->getPrimitiveSizeInBits() == 16 && 945 "Unexpected vector size"); 946 947 return ExtractCost + 2; // worst case pshufhw + pshufd 948 } 949 } 950 } 951 952 // Handle some common (illegal) sub-vector types as they are often very cheap 953 // to shuffle even on targets without PSHUFB. 954 EVT VT = TLI->getValueType(DL, Tp); 955 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 956 !ST->hasSSSE3()) { 957 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 958 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 959 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 960 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 961 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 962 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 963 964 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 965 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 966 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 967 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 968 969 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 970 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 971 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 972 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 973 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 974 975 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 976 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 977 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 978 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 979 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 980 }; 981 982 if (ST->hasSSE2()) 983 if (const auto *Entry = 984 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 985 return Entry->Cost; 986 } 987 988 // We are going to permute multiple sources and the result will be in multiple 989 // destinations. Providing an accurate cost only for splits where the element 990 // type remains the same. 991 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 992 MVT LegalVT = LT.second; 993 if (LegalVT.isVector() && 994 LegalVT.getVectorElementType().getSizeInBits() == 995 Tp->getVectorElementType()->getPrimitiveSizeInBits() && 996 LegalVT.getVectorNumElements() < Tp->getVectorNumElements()) { 997 998 unsigned VecTySize = DL.getTypeStoreSize(Tp); 999 unsigned LegalVTSize = LegalVT.getStoreSize(); 1000 // Number of source vectors after legalization: 1001 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1002 // Number of destination vectors after legalization: 1003 unsigned NumOfDests = LT.first; 1004 1005 Type *SingleOpTy = VectorType::get(Tp->getVectorElementType(), 1006 LegalVT.getVectorNumElements()); 1007 1008 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1009 return NumOfShuffles * 1010 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 0, nullptr); 1011 } 1012 1013 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 1014 } 1015 1016 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1017 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1018 // We assume that source and destination have the same vector type. 1019 int NumOfDests = LT.first; 1020 int NumOfShufflesPerDest = LT.first * 2 - 1; 1021 LT.first = NumOfDests * NumOfShufflesPerDest; 1022 } 1023 1024 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1025 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1026 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1027 1028 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1029 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1030 1031 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 1}, // vpermt2b 1032 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 1}, // vpermt2b 1033 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1} // vpermt2b 1034 }; 1035 1036 if (ST->hasVBMI()) 1037 if (const auto *Entry = 1038 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1039 return LT.first * Entry->Cost; 1040 1041 static const CostTblEntry AVX512BWShuffleTbl[] = { 1042 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1043 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1044 1045 {TTI::SK_Reverse, MVT::v32i16, 1}, // vpermw 1046 {TTI::SK_Reverse, MVT::v16i16, 1}, // vpermw 1047 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1048 1049 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 1}, // vpermw 1050 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 1}, // vpermw 1051 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // vpermw 1052 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1053 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 3}, // vpermw + zext/trunc 1054 1055 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 1}, // vpermt2w 1056 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 1}, // vpermt2w 1057 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpermt2w 1058 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 3}, // zext + vpermt2w + trunc 1059 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1060 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3} // zext + vpermt2w + trunc 1061 }; 1062 1063 if (ST->hasBWI()) 1064 if (const auto *Entry = 1065 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1066 return LT.first * Entry->Cost; 1067 1068 static const CostTblEntry AVX512ShuffleTbl[] = { 1069 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1070 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1071 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1072 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1073 1074 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1075 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1076 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1077 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1078 1079 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1080 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1081 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1082 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1083 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1084 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1085 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1086 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1087 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1088 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1089 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1090 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1091 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1092 1093 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1094 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1095 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1096 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1097 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1098 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1099 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1100 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1101 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1102 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1103 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1104 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1} // vpermt2d 1105 }; 1106 1107 if (ST->hasAVX512()) 1108 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1109 return LT.first * Entry->Cost; 1110 1111 static const CostTblEntry AVX2ShuffleTbl[] = { 1112 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1113 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1114 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1115 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1116 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1117 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1118 1119 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1120 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1121 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1122 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1123 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1124 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1125 1126 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1127 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1128 1129 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1130 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1131 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1132 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1133 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1134 // + vpblendvb 1135 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1136 // + vpblendvb 1137 1138 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1139 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1140 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1141 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1142 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1143 // + vpblendvb 1144 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1145 // + vpblendvb 1146 }; 1147 1148 if (ST->hasAVX2()) 1149 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1150 return LT.first * Entry->Cost; 1151 1152 static const CostTblEntry XOPShuffleTbl[] = { 1153 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1154 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1155 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1156 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1157 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1158 // + vinsertf128 1159 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1160 // + vinsertf128 1161 1162 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1163 // + vinsertf128 1164 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1165 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1166 // + vinsertf128 1167 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1168 }; 1169 1170 if (ST->hasXOP()) 1171 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1172 return LT.first * Entry->Cost; 1173 1174 static const CostTblEntry AVX1ShuffleTbl[] = { 1175 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1176 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1177 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1178 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1179 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1180 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1181 1182 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1183 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1184 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1185 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1186 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1187 // + vinsertf128 1188 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1189 // + vinsertf128 1190 1191 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1192 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1193 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1194 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1195 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1196 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1197 1198 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1199 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1200 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1201 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1202 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1203 // + 2*por + vinsertf128 1204 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1205 // + 2*por + vinsertf128 1206 1207 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1208 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1209 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1210 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1211 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1212 // + 4*por + vinsertf128 1213 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1214 // + 4*por + vinsertf128 1215 }; 1216 1217 if (ST->hasAVX()) 1218 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1219 return LT.first * Entry->Cost; 1220 1221 static const CostTblEntry SSE41ShuffleTbl[] = { 1222 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1223 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1224 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1225 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1226 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1227 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1228 }; 1229 1230 if (ST->hasSSE41()) 1231 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1232 return LT.first * Entry->Cost; 1233 1234 static const CostTblEntry SSSE3ShuffleTbl[] = { 1235 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1236 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1237 1238 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1239 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1240 1241 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1242 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1243 1244 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1245 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1246 1247 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1248 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1249 }; 1250 1251 if (ST->hasSSSE3()) 1252 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1253 return LT.first * Entry->Cost; 1254 1255 static const CostTblEntry SSE2ShuffleTbl[] = { 1256 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1257 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1258 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1259 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1260 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1261 1262 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1263 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1264 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1265 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1266 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1267 // + 2*pshufd + 2*unpck + packus 1268 1269 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1270 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1271 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1272 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1273 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1274 1275 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1276 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1277 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1278 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1279 // + pshufd/unpck 1280 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1281 // + 2*pshufd + 2*unpck + 2*packus 1282 1283 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1284 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1285 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1286 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1287 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1288 }; 1289 1290 if (ST->hasSSE2()) 1291 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1292 return LT.first * Entry->Cost; 1293 1294 static const CostTblEntry SSE1ShuffleTbl[] = { 1295 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1296 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1297 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1298 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1299 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1300 }; 1301 1302 if (ST->hasSSE1()) 1303 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1304 return LT.first * Entry->Cost; 1305 1306 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 1307 } 1308 1309 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 1310 const Instruction *I) { 1311 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1312 assert(ISD && "Invalid opcode"); 1313 1314 // FIXME: Need a better design of the cost table to handle non-simple types of 1315 // potential massive combinations (elem_num x src_type x dst_type). 1316 1317 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1318 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1319 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1320 1321 // Mask sign extend has an instruction. 1322 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1323 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1324 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1325 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1326 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1327 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1328 1329 // Mask zero extend is a load + broadcast. 1330 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1331 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1332 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1333 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1334 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1335 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1336 1337 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 1 }, 1338 }; 1339 1340 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1341 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1342 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1343 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1344 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1345 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1346 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1347 1348 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1349 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1350 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1351 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1352 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1353 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1354 1355 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1356 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1357 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1358 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1359 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1360 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1361 1362 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1363 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1364 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1365 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1366 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1367 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1368 }; 1369 1370 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1371 // 256-bit wide vectors. 1372 1373 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1374 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1375 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1376 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1377 1378 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 }, 1379 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 }, 1380 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 }, 1381 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 1382 1383 // v16i1 -> v16i32 - load + broadcast 1384 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1385 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1386 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1387 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1388 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1389 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1390 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1391 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1392 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1393 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1394 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1395 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1396 1397 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1398 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1399 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1400 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1401 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1402 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1403 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1404 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1405 1406 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1407 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1408 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1409 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1410 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1411 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1412 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1413 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1414 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1415 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1416 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1417 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1418 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1419 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1420 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1421 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1422 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1423 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1424 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1425 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1426 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1427 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1428 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1429 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1430 1431 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 1432 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1433 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 1434 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 1435 1436 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1437 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1438 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1439 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1440 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1441 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 2 }, 1442 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 2 }, 1443 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1444 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 2 }, 1445 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 2 }, 1446 }; 1447 1448 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1449 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1450 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1451 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1452 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1453 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1454 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1455 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1456 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1457 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1458 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1459 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1460 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1461 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1462 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1463 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1464 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1465 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1466 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1467 1468 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 1469 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 1470 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1471 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 1472 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1473 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 }, 1474 1475 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1476 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1477 1478 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1479 }; 1480 1481 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1482 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1483 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1484 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1485 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1486 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1487 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1488 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1489 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1490 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1491 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1492 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 4 }, 1493 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1494 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1495 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1496 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1497 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1498 1499 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 1500 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1501 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1502 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1503 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 1504 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 }, 1505 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 11 }, 1506 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 9 }, 1507 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 }, 1508 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 11 }, 1509 1510 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1511 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1512 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1513 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1514 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1515 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1516 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1517 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1518 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1519 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1520 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1521 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1522 1523 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1524 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1525 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1526 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1527 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1528 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1529 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1530 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1531 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1532 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 }, 1533 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 1534 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1535 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 1536 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1537 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1538 // The generic code to compute the scalar overhead is currently broken. 1539 // Workaround this limitation by estimating the scalarization overhead 1540 // here. We have roughly 10 instructions per scalar element. 1541 // Multiply that by the vector width. 1542 // FIXME: remove that when PR19268 is fixed. 1543 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1544 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1545 1546 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 }, 1547 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 }, 1548 // This node is expanded into scalarized operations but BasicTTI is overly 1549 // optimistic estimating its cost. It computes 3 per element (one 1550 // vector-extract, one scalar conversion and one vector-insert). The 1551 // problem is that the inserts form a read-modify-write chain so latency 1552 // should be factored in too. Inflating the cost per element by 1. 1553 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, 1554 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 1555 1556 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 1557 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 1558 }; 1559 1560 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 1561 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1562 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1563 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1564 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1565 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1566 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1567 1568 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1569 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 }, 1570 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1571 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1572 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1573 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1574 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1575 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1576 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1577 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1578 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1579 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1580 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1581 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1582 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1583 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1584 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1585 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1586 1587 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, 1588 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 1589 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 1590 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 1591 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 1592 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 1593 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 1594 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 1 }, // PSHUFB 1595 1596 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 1597 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 1598 }; 1599 1600 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 1601 // These are somewhat magic numbers justified by looking at the output of 1602 // Intel's IACA, running some kernels and making sure when we take 1603 // legalization into account the throughput will be overestimated. 1604 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1605 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1606 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1607 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1608 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1609 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 2*10 }, 1610 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2*10 }, 1611 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1612 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 1613 1614 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1615 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1616 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1617 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1618 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1619 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, 1620 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 }, 1621 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1622 1623 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, 1624 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, 1625 1626 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 3 }, 1627 1628 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 6 }, 1629 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 }, 1630 1631 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 1632 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 1633 1634 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1635 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 1636 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 1637 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 1638 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1639 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 1640 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1641 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 1642 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1643 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1644 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1645 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1646 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 1647 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 1648 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1649 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 1650 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1651 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 1652 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1653 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1654 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 1655 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 1656 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1657 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 1658 1659 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // PAND+PACKUSWB 1660 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 4 }, 1661 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, 1662 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 1663 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 3 }, // PAND+3*PACKUSWB 1664 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 1665 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 1666 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 1667 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1668 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 1669 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1670 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 1671 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 1672 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 1673 { ISD::TRUNCATE, MVT::v2i32, MVT::v2i64, 1 }, // PSHUFD 1674 }; 1675 1676 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 1677 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst); 1678 1679 if (ST->hasSSE2() && !ST->hasAVX()) { 1680 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1681 LTDest.second, LTSrc.second)) 1682 return LTSrc.first * Entry->Cost; 1683 } 1684 1685 EVT SrcTy = TLI->getValueType(DL, Src); 1686 EVT DstTy = TLI->getValueType(DL, Dst); 1687 1688 // The function getSimpleVT only handles simple value types. 1689 if (!SrcTy.isSimple() || !DstTy.isSimple()) 1690 return BaseT::getCastInstrCost(Opcode, Dst, Src); 1691 1692 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 1693 MVT SimpleDstTy = DstTy.getSimpleVT(); 1694 1695 // Make sure that neither type is going to be split before using the 1696 // AVX512 tables. This handles -mprefer-vector-width=256 1697 // with -min-legal-vector-width<=256 1698 if (TLI->getTypeAction(SimpleSrcTy) != TargetLowering::TypeSplitVector && 1699 TLI->getTypeAction(SimpleDstTy) != TargetLowering::TypeSplitVector) { 1700 if (ST->hasBWI()) 1701 if (const auto *Entry = ConvertCostTableLookup(AVX512BWConversionTbl, ISD, 1702 SimpleDstTy, SimpleSrcTy)) 1703 return Entry->Cost; 1704 1705 if (ST->hasDQI()) 1706 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 1707 SimpleDstTy, SimpleSrcTy)) 1708 return Entry->Cost; 1709 1710 if (ST->hasAVX512()) 1711 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 1712 SimpleDstTy, SimpleSrcTy)) 1713 return Entry->Cost; 1714 } 1715 1716 if (ST->hasAVX2()) { 1717 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 1718 SimpleDstTy, SimpleSrcTy)) 1719 return Entry->Cost; 1720 } 1721 1722 if (ST->hasAVX()) { 1723 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 1724 SimpleDstTy, SimpleSrcTy)) 1725 return Entry->Cost; 1726 } 1727 1728 if (ST->hasSSE41()) { 1729 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 1730 SimpleDstTy, SimpleSrcTy)) 1731 return Entry->Cost; 1732 } 1733 1734 if (ST->hasSSE2()) { 1735 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1736 SimpleDstTy, SimpleSrcTy)) 1737 return Entry->Cost; 1738 } 1739 1740 return BaseT::getCastInstrCost(Opcode, Dst, Src, I); 1741 } 1742 1743 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 1744 const Instruction *I) { 1745 // Legalize the type. 1746 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 1747 1748 MVT MTy = LT.second; 1749 1750 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1751 assert(ISD && "Invalid opcode"); 1752 1753 unsigned ExtraCost = 0; 1754 if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) { 1755 // Some vector comparison predicates cost extra instructions. 1756 if (MTy.isVector() && 1757 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 1758 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 1759 ST->hasBWI())) { 1760 switch (cast<CmpInst>(I)->getPredicate()) { 1761 case CmpInst::Predicate::ICMP_NE: 1762 // xor(cmpeq(x,y),-1) 1763 ExtraCost = 1; 1764 break; 1765 case CmpInst::Predicate::ICMP_SGE: 1766 case CmpInst::Predicate::ICMP_SLE: 1767 // xor(cmpgt(x,y),-1) 1768 ExtraCost = 1; 1769 break; 1770 case CmpInst::Predicate::ICMP_ULT: 1771 case CmpInst::Predicate::ICMP_UGT: 1772 // cmpgt(xor(x,signbit),xor(y,signbit)) 1773 // xor(cmpeq(pmaxu(x,y),x),-1) 1774 ExtraCost = 2; 1775 break; 1776 case CmpInst::Predicate::ICMP_ULE: 1777 case CmpInst::Predicate::ICMP_UGE: 1778 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 1779 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 1780 // cmpeq(psubus(x,y),0) 1781 // cmpeq(pminu(x,y),x) 1782 ExtraCost = 1; 1783 } else { 1784 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 1785 ExtraCost = 3; 1786 } 1787 break; 1788 default: 1789 break; 1790 } 1791 } 1792 } 1793 1794 static const CostTblEntry SLMCostTbl[] = { 1795 // slm pcmpeq/pcmpgt throughput is 2 1796 { ISD::SETCC, MVT::v2i64, 2 }, 1797 }; 1798 1799 static const CostTblEntry AVX512BWCostTbl[] = { 1800 { ISD::SETCC, MVT::v32i16, 1 }, 1801 { ISD::SETCC, MVT::v64i8, 1 }, 1802 1803 { ISD::SELECT, MVT::v32i16, 1 }, 1804 { ISD::SELECT, MVT::v64i8, 1 }, 1805 }; 1806 1807 static const CostTblEntry AVX512CostTbl[] = { 1808 { ISD::SETCC, MVT::v8i64, 1 }, 1809 { ISD::SETCC, MVT::v16i32, 1 }, 1810 { ISD::SETCC, MVT::v8f64, 1 }, 1811 { ISD::SETCC, MVT::v16f32, 1 }, 1812 1813 { ISD::SELECT, MVT::v8i64, 1 }, 1814 { ISD::SELECT, MVT::v16i32, 1 }, 1815 { ISD::SELECT, MVT::v8f64, 1 }, 1816 { ISD::SELECT, MVT::v16f32, 1 }, 1817 }; 1818 1819 static const CostTblEntry AVX2CostTbl[] = { 1820 { ISD::SETCC, MVT::v4i64, 1 }, 1821 { ISD::SETCC, MVT::v8i32, 1 }, 1822 { ISD::SETCC, MVT::v16i16, 1 }, 1823 { ISD::SETCC, MVT::v32i8, 1 }, 1824 1825 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 1826 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 1827 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 1828 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 1829 }; 1830 1831 static const CostTblEntry AVX1CostTbl[] = { 1832 { ISD::SETCC, MVT::v4f64, 1 }, 1833 { ISD::SETCC, MVT::v8f32, 1 }, 1834 // AVX1 does not support 8-wide integer compare. 1835 { ISD::SETCC, MVT::v4i64, 4 }, 1836 { ISD::SETCC, MVT::v8i32, 4 }, 1837 { ISD::SETCC, MVT::v16i16, 4 }, 1838 { ISD::SETCC, MVT::v32i8, 4 }, 1839 1840 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 1841 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 1842 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 1843 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 1844 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 1845 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 1846 }; 1847 1848 static const CostTblEntry SSE42CostTbl[] = { 1849 { ISD::SETCC, MVT::v2f64, 1 }, 1850 { ISD::SETCC, MVT::v4f32, 1 }, 1851 { ISD::SETCC, MVT::v2i64, 1 }, 1852 }; 1853 1854 static const CostTblEntry SSE41CostTbl[] = { 1855 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 1856 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 1857 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 1858 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 1859 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 1860 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 1861 }; 1862 1863 static const CostTblEntry SSE2CostTbl[] = { 1864 { ISD::SETCC, MVT::v2f64, 2 }, 1865 { ISD::SETCC, MVT::f64, 1 }, 1866 { ISD::SETCC, MVT::v2i64, 8 }, 1867 { ISD::SETCC, MVT::v4i32, 1 }, 1868 { ISD::SETCC, MVT::v8i16, 1 }, 1869 { ISD::SETCC, MVT::v16i8, 1 }, 1870 1871 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 1872 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 1873 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 1874 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 1875 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 1876 }; 1877 1878 static const CostTblEntry SSE1CostTbl[] = { 1879 { ISD::SETCC, MVT::v4f32, 2 }, 1880 { ISD::SETCC, MVT::f32, 1 }, 1881 1882 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 1883 }; 1884 1885 if (ST->isSLM()) 1886 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 1887 return LT.first * (ExtraCost + Entry->Cost); 1888 1889 if (ST->hasBWI()) 1890 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 1891 return LT.first * (ExtraCost + Entry->Cost); 1892 1893 if (ST->hasAVX512()) 1894 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 1895 return LT.first * (ExtraCost + Entry->Cost); 1896 1897 if (ST->hasAVX2()) 1898 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 1899 return LT.first * (ExtraCost + Entry->Cost); 1900 1901 if (ST->hasAVX()) 1902 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 1903 return LT.first * (ExtraCost + Entry->Cost); 1904 1905 if (ST->hasSSE42()) 1906 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 1907 return LT.first * (ExtraCost + Entry->Cost); 1908 1909 if (ST->hasSSE41()) 1910 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 1911 return LT.first * (ExtraCost + Entry->Cost); 1912 1913 if (ST->hasSSE2()) 1914 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 1915 return LT.first * (ExtraCost + Entry->Cost); 1916 1917 if (ST->hasSSE1()) 1918 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 1919 return LT.first * (ExtraCost + Entry->Cost); 1920 1921 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I); 1922 } 1923 1924 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 1925 1926 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 1927 ArrayRef<Type *> Tys, FastMathFlags FMF, 1928 unsigned ScalarizationCostPassed, 1929 const Instruction *I) { 1930 // Costs should match the codegen from: 1931 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 1932 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 1933 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 1934 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 1935 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 1936 static const CostTblEntry AVX512CDCostTbl[] = { 1937 { ISD::CTLZ, MVT::v8i64, 1 }, 1938 { ISD::CTLZ, MVT::v16i32, 1 }, 1939 { ISD::CTLZ, MVT::v32i16, 8 }, 1940 { ISD::CTLZ, MVT::v64i8, 20 }, 1941 { ISD::CTLZ, MVT::v4i64, 1 }, 1942 { ISD::CTLZ, MVT::v8i32, 1 }, 1943 { ISD::CTLZ, MVT::v16i16, 4 }, 1944 { ISD::CTLZ, MVT::v32i8, 10 }, 1945 { ISD::CTLZ, MVT::v2i64, 1 }, 1946 { ISD::CTLZ, MVT::v4i32, 1 }, 1947 { ISD::CTLZ, MVT::v8i16, 4 }, 1948 { ISD::CTLZ, MVT::v16i8, 4 }, 1949 }; 1950 static const CostTblEntry AVX512BWCostTbl[] = { 1951 { ISD::BITREVERSE, MVT::v8i64, 5 }, 1952 { ISD::BITREVERSE, MVT::v16i32, 5 }, 1953 { ISD::BITREVERSE, MVT::v32i16, 5 }, 1954 { ISD::BITREVERSE, MVT::v64i8, 5 }, 1955 { ISD::CTLZ, MVT::v8i64, 23 }, 1956 { ISD::CTLZ, MVT::v16i32, 22 }, 1957 { ISD::CTLZ, MVT::v32i16, 18 }, 1958 { ISD::CTLZ, MVT::v64i8, 17 }, 1959 { ISD::CTPOP, MVT::v8i64, 7 }, 1960 { ISD::CTPOP, MVT::v16i32, 11 }, 1961 { ISD::CTPOP, MVT::v32i16, 9 }, 1962 { ISD::CTPOP, MVT::v64i8, 6 }, 1963 { ISD::CTTZ, MVT::v8i64, 10 }, 1964 { ISD::CTTZ, MVT::v16i32, 14 }, 1965 { ISD::CTTZ, MVT::v32i16, 12 }, 1966 { ISD::CTTZ, MVT::v64i8, 9 }, 1967 { ISD::SADDSAT, MVT::v32i16, 1 }, 1968 { ISD::SADDSAT, MVT::v64i8, 1 }, 1969 { ISD::SSUBSAT, MVT::v32i16, 1 }, 1970 { ISD::SSUBSAT, MVT::v64i8, 1 }, 1971 { ISD::UADDSAT, MVT::v32i16, 1 }, 1972 { ISD::UADDSAT, MVT::v64i8, 1 }, 1973 { ISD::USUBSAT, MVT::v32i16, 1 }, 1974 { ISD::USUBSAT, MVT::v64i8, 1 }, 1975 }; 1976 static const CostTblEntry AVX512CostTbl[] = { 1977 { ISD::BITREVERSE, MVT::v8i64, 36 }, 1978 { ISD::BITREVERSE, MVT::v16i32, 24 }, 1979 { ISD::CTLZ, MVT::v8i64, 29 }, 1980 { ISD::CTLZ, MVT::v16i32, 35 }, 1981 { ISD::CTPOP, MVT::v8i64, 16 }, 1982 { ISD::CTPOP, MVT::v16i32, 24 }, 1983 { ISD::CTTZ, MVT::v8i64, 20 }, 1984 { ISD::CTTZ, MVT::v16i32, 28 }, 1985 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 1986 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 1987 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 1988 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 1989 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 1990 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 1991 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 1992 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 1993 { ISD::FMAXNUM, MVT::f32, 2 }, 1994 { ISD::FMAXNUM, MVT::v4f32, 2 }, 1995 { ISD::FMAXNUM, MVT::v8f32, 2 }, 1996 { ISD::FMAXNUM, MVT::v16f32, 2 }, 1997 { ISD::FMAXNUM, MVT::f64, 2 }, 1998 { ISD::FMAXNUM, MVT::v2f64, 2 }, 1999 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2000 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2001 }; 2002 static const CostTblEntry XOPCostTbl[] = { 2003 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2004 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2005 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2006 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2007 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2008 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2009 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2010 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2011 { ISD::BITREVERSE, MVT::i64, 3 }, 2012 { ISD::BITREVERSE, MVT::i32, 3 }, 2013 { ISD::BITREVERSE, MVT::i16, 3 }, 2014 { ISD::BITREVERSE, MVT::i8, 3 } 2015 }; 2016 static const CostTblEntry AVX2CostTbl[] = { 2017 { ISD::BITREVERSE, MVT::v4i64, 5 }, 2018 { ISD::BITREVERSE, MVT::v8i32, 5 }, 2019 { ISD::BITREVERSE, MVT::v16i16, 5 }, 2020 { ISD::BITREVERSE, MVT::v32i8, 5 }, 2021 { ISD::BSWAP, MVT::v4i64, 1 }, 2022 { ISD::BSWAP, MVT::v8i32, 1 }, 2023 { ISD::BSWAP, MVT::v16i16, 1 }, 2024 { ISD::CTLZ, MVT::v4i64, 23 }, 2025 { ISD::CTLZ, MVT::v8i32, 18 }, 2026 { ISD::CTLZ, MVT::v16i16, 14 }, 2027 { ISD::CTLZ, MVT::v32i8, 9 }, 2028 { ISD::CTPOP, MVT::v4i64, 7 }, 2029 { ISD::CTPOP, MVT::v8i32, 11 }, 2030 { ISD::CTPOP, MVT::v16i16, 9 }, 2031 { ISD::CTPOP, MVT::v32i8, 6 }, 2032 { ISD::CTTZ, MVT::v4i64, 10 }, 2033 { ISD::CTTZ, MVT::v8i32, 14 }, 2034 { ISD::CTTZ, MVT::v16i16, 12 }, 2035 { ISD::CTTZ, MVT::v32i8, 9 }, 2036 { ISD::SADDSAT, MVT::v16i16, 1 }, 2037 { ISD::SADDSAT, MVT::v32i8, 1 }, 2038 { ISD::SSUBSAT, MVT::v16i16, 1 }, 2039 { ISD::SSUBSAT, MVT::v32i8, 1 }, 2040 { ISD::UADDSAT, MVT::v16i16, 1 }, 2041 { ISD::UADDSAT, MVT::v32i8, 1 }, 2042 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 2043 { ISD::USUBSAT, MVT::v16i16, 1 }, 2044 { ISD::USUBSAT, MVT::v32i8, 1 }, 2045 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2046 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2047 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2048 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2049 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2050 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2051 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2052 }; 2053 static const CostTblEntry AVX1CostTbl[] = { 2054 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 2055 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 2056 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 2057 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 2058 { ISD::BSWAP, MVT::v4i64, 4 }, 2059 { ISD::BSWAP, MVT::v8i32, 4 }, 2060 { ISD::BSWAP, MVT::v16i16, 4 }, 2061 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 2062 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 2063 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 2064 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2065 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 2066 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 2067 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 2068 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 2069 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 2070 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 2071 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 2072 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2073 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2074 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2075 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2076 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2077 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2078 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2079 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 2080 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2081 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2082 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 2083 { ISD::FMAXNUM, MVT::f32, 3 }, 2084 { ISD::FMAXNUM, MVT::v4f32, 3 }, 2085 { ISD::FMAXNUM, MVT::v8f32, 5 }, 2086 { ISD::FMAXNUM, MVT::f64, 3 }, 2087 { ISD::FMAXNUM, MVT::v2f64, 3 }, 2088 { ISD::FMAXNUM, MVT::v4f64, 5 }, 2089 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 2090 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 2091 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 2092 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 2093 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 2094 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 2095 }; 2096 static const CostTblEntry GLMCostTbl[] = { 2097 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 2098 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 2099 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 2100 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 2101 }; 2102 static const CostTblEntry SLMCostTbl[] = { 2103 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 2104 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 2105 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 2106 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 2107 }; 2108 static const CostTblEntry SSE42CostTbl[] = { 2109 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 2110 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 2111 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 2112 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 2113 }; 2114 static const CostTblEntry SSSE3CostTbl[] = { 2115 { ISD::BITREVERSE, MVT::v2i64, 5 }, 2116 { ISD::BITREVERSE, MVT::v4i32, 5 }, 2117 { ISD::BITREVERSE, MVT::v8i16, 5 }, 2118 { ISD::BITREVERSE, MVT::v16i8, 5 }, 2119 { ISD::BSWAP, MVT::v2i64, 1 }, 2120 { ISD::BSWAP, MVT::v4i32, 1 }, 2121 { ISD::BSWAP, MVT::v8i16, 1 }, 2122 { ISD::CTLZ, MVT::v2i64, 23 }, 2123 { ISD::CTLZ, MVT::v4i32, 18 }, 2124 { ISD::CTLZ, MVT::v8i16, 14 }, 2125 { ISD::CTLZ, MVT::v16i8, 9 }, 2126 { ISD::CTPOP, MVT::v2i64, 7 }, 2127 { ISD::CTPOP, MVT::v4i32, 11 }, 2128 { ISD::CTPOP, MVT::v8i16, 9 }, 2129 { ISD::CTPOP, MVT::v16i8, 6 }, 2130 { ISD::CTTZ, MVT::v2i64, 10 }, 2131 { ISD::CTTZ, MVT::v4i32, 14 }, 2132 { ISD::CTTZ, MVT::v8i16, 12 }, 2133 { ISD::CTTZ, MVT::v16i8, 9 } 2134 }; 2135 static const CostTblEntry SSE2CostTbl[] = { 2136 { ISD::BITREVERSE, MVT::v2i64, 29 }, 2137 { ISD::BITREVERSE, MVT::v4i32, 27 }, 2138 { ISD::BITREVERSE, MVT::v8i16, 27 }, 2139 { ISD::BITREVERSE, MVT::v16i8, 20 }, 2140 { ISD::BSWAP, MVT::v2i64, 7 }, 2141 { ISD::BSWAP, MVT::v4i32, 7 }, 2142 { ISD::BSWAP, MVT::v8i16, 7 }, 2143 { ISD::CTLZ, MVT::v2i64, 25 }, 2144 { ISD::CTLZ, MVT::v4i32, 26 }, 2145 { ISD::CTLZ, MVT::v8i16, 20 }, 2146 { ISD::CTLZ, MVT::v16i8, 17 }, 2147 { ISD::CTPOP, MVT::v2i64, 12 }, 2148 { ISD::CTPOP, MVT::v4i32, 15 }, 2149 { ISD::CTPOP, MVT::v8i16, 13 }, 2150 { ISD::CTPOP, MVT::v16i8, 10 }, 2151 { ISD::CTTZ, MVT::v2i64, 14 }, 2152 { ISD::CTTZ, MVT::v4i32, 18 }, 2153 { ISD::CTTZ, MVT::v8i16, 16 }, 2154 { ISD::CTTZ, MVT::v16i8, 13 }, 2155 { ISD::SADDSAT, MVT::v8i16, 1 }, 2156 { ISD::SADDSAT, MVT::v16i8, 1 }, 2157 { ISD::SSUBSAT, MVT::v8i16, 1 }, 2158 { ISD::SSUBSAT, MVT::v16i8, 1 }, 2159 { ISD::UADDSAT, MVT::v8i16, 1 }, 2160 { ISD::UADDSAT, MVT::v16i8, 1 }, 2161 { ISD::USUBSAT, MVT::v8i16, 1 }, 2162 { ISD::USUBSAT, MVT::v16i8, 1 }, 2163 { ISD::FMAXNUM, MVT::f64, 4 }, 2164 { ISD::FMAXNUM, MVT::v2f64, 4 }, 2165 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 2166 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 2167 }; 2168 static const CostTblEntry SSE1CostTbl[] = { 2169 { ISD::FMAXNUM, MVT::f32, 4 }, 2170 { ISD::FMAXNUM, MVT::v4f32, 4 }, 2171 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 2172 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 2173 }; 2174 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 2175 { ISD::CTTZ, MVT::i64, 1 }, 2176 }; 2177 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 2178 { ISD::CTTZ, MVT::i32, 1 }, 2179 { ISD::CTTZ, MVT::i16, 1 }, 2180 { ISD::CTTZ, MVT::i8, 1 }, 2181 }; 2182 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 2183 { ISD::CTLZ, MVT::i64, 1 }, 2184 }; 2185 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 2186 { ISD::CTLZ, MVT::i32, 1 }, 2187 { ISD::CTLZ, MVT::i16, 1 }, 2188 { ISD::CTLZ, MVT::i8, 1 }, 2189 }; 2190 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 2191 { ISD::CTPOP, MVT::i64, 1 }, 2192 }; 2193 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 2194 { ISD::CTPOP, MVT::i32, 1 }, 2195 { ISD::CTPOP, MVT::i16, 1 }, 2196 { ISD::CTPOP, MVT::i8, 1 }, 2197 }; 2198 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2199 { ISD::BITREVERSE, MVT::i64, 14 }, 2200 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 2201 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 2202 { ISD::CTPOP, MVT::i64, 10 }, 2203 { ISD::SADDO, MVT::i64, 1 }, 2204 { ISD::UADDO, MVT::i64, 1 }, 2205 }; 2206 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2207 { ISD::BITREVERSE, MVT::i32, 14 }, 2208 { ISD::BITREVERSE, MVT::i16, 14 }, 2209 { ISD::BITREVERSE, MVT::i8, 11 }, 2210 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 2211 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 2212 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 2213 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 2214 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 2215 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 2216 { ISD::CTPOP, MVT::i32, 8 }, 2217 { ISD::CTPOP, MVT::i16, 9 }, 2218 { ISD::CTPOP, MVT::i8, 7 }, 2219 { ISD::SADDO, MVT::i32, 1 }, 2220 { ISD::SADDO, MVT::i16, 1 }, 2221 { ISD::SADDO, MVT::i8, 1 }, 2222 { ISD::UADDO, MVT::i32, 1 }, 2223 { ISD::UADDO, MVT::i16, 1 }, 2224 { ISD::UADDO, MVT::i8, 1 }, 2225 }; 2226 2227 Type *OpTy = RetTy; 2228 unsigned ISD = ISD::DELETED_NODE; 2229 switch (IID) { 2230 default: 2231 break; 2232 case Intrinsic::bitreverse: 2233 ISD = ISD::BITREVERSE; 2234 break; 2235 case Intrinsic::bswap: 2236 ISD = ISD::BSWAP; 2237 break; 2238 case Intrinsic::ctlz: 2239 ISD = ISD::CTLZ; 2240 break; 2241 case Intrinsic::ctpop: 2242 ISD = ISD::CTPOP; 2243 break; 2244 case Intrinsic::cttz: 2245 ISD = ISD::CTTZ; 2246 break; 2247 case Intrinsic::maxnum: 2248 case Intrinsic::minnum: 2249 // FMINNUM has same costs so don't duplicate. 2250 ISD = ISD::FMAXNUM; 2251 break; 2252 case Intrinsic::sadd_sat: 2253 ISD = ISD::SADDSAT; 2254 break; 2255 case Intrinsic::ssub_sat: 2256 ISD = ISD::SSUBSAT; 2257 break; 2258 case Intrinsic::uadd_sat: 2259 ISD = ISD::UADDSAT; 2260 break; 2261 case Intrinsic::usub_sat: 2262 ISD = ISD::USUBSAT; 2263 break; 2264 case Intrinsic::sqrt: 2265 ISD = ISD::FSQRT; 2266 break; 2267 case Intrinsic::sadd_with_overflow: 2268 case Intrinsic::ssub_with_overflow: 2269 // SSUBO has same costs so don't duplicate. 2270 ISD = ISD::SADDO; 2271 OpTy = RetTy->getContainedType(0); 2272 break; 2273 case Intrinsic::uadd_with_overflow: 2274 case Intrinsic::usub_with_overflow: 2275 // USUBO has same costs so don't duplicate. 2276 ISD = ISD::UADDO; 2277 OpTy = RetTy->getContainedType(0); 2278 break; 2279 } 2280 2281 if (ISD != ISD::DELETED_NODE) { 2282 // Legalize the type. 2283 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 2284 MVT MTy = LT.second; 2285 2286 // Attempt to lookup cost. 2287 if (ST->useGLMDivSqrtCosts()) 2288 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 2289 return LT.first * Entry->Cost; 2290 2291 if (ST->isSLM()) 2292 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2293 return LT.first * Entry->Cost; 2294 2295 if (ST->hasCDI()) 2296 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 2297 return LT.first * Entry->Cost; 2298 2299 if (ST->hasBWI()) 2300 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2301 return LT.first * Entry->Cost; 2302 2303 if (ST->hasAVX512()) 2304 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2305 return LT.first * Entry->Cost; 2306 2307 if (ST->hasXOP()) 2308 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2309 return LT.first * Entry->Cost; 2310 2311 if (ST->hasAVX2()) 2312 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2313 return LT.first * Entry->Cost; 2314 2315 if (ST->hasAVX()) 2316 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2317 return LT.first * Entry->Cost; 2318 2319 if (ST->hasSSE42()) 2320 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2321 return LT.first * Entry->Cost; 2322 2323 if (ST->hasSSSE3()) 2324 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 2325 return LT.first * Entry->Cost; 2326 2327 if (ST->hasSSE2()) 2328 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2329 return LT.first * Entry->Cost; 2330 2331 if (ST->hasSSE1()) 2332 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2333 return LT.first * Entry->Cost; 2334 2335 if (ST->hasBMI()) { 2336 if (ST->is64Bit()) 2337 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 2338 return LT.first * Entry->Cost; 2339 2340 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 2341 return LT.first * Entry->Cost; 2342 } 2343 2344 if (ST->hasLZCNT()) { 2345 if (ST->is64Bit()) 2346 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 2347 return LT.first * Entry->Cost; 2348 2349 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 2350 return LT.first * Entry->Cost; 2351 } 2352 2353 if (ST->hasPOPCNT()) { 2354 if (ST->is64Bit()) 2355 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 2356 return LT.first * Entry->Cost; 2357 2358 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 2359 return LT.first * Entry->Cost; 2360 } 2361 2362 // TODO - add BMI (TZCNT) scalar handling 2363 2364 if (ST->is64Bit()) 2365 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2366 return LT.first * Entry->Cost; 2367 2368 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2369 return LT.first * Entry->Cost; 2370 } 2371 2372 return BaseT::getIntrinsicInstrCost(IID, RetTy, Tys, FMF, 2373 ScalarizationCostPassed, I); 2374 } 2375 2376 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 2377 ArrayRef<Value *> Args, FastMathFlags FMF, 2378 unsigned VF, const Instruction *I) { 2379 static const CostTblEntry AVX512CostTbl[] = { 2380 { ISD::ROTL, MVT::v8i64, 1 }, 2381 { ISD::ROTL, MVT::v4i64, 1 }, 2382 { ISD::ROTL, MVT::v2i64, 1 }, 2383 { ISD::ROTL, MVT::v16i32, 1 }, 2384 { ISD::ROTL, MVT::v8i32, 1 }, 2385 { ISD::ROTL, MVT::v4i32, 1 }, 2386 { ISD::ROTR, MVT::v8i64, 1 }, 2387 { ISD::ROTR, MVT::v4i64, 1 }, 2388 { ISD::ROTR, MVT::v2i64, 1 }, 2389 { ISD::ROTR, MVT::v16i32, 1 }, 2390 { ISD::ROTR, MVT::v8i32, 1 }, 2391 { ISD::ROTR, MVT::v4i32, 1 } 2392 }; 2393 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 2394 static const CostTblEntry XOPCostTbl[] = { 2395 { ISD::ROTL, MVT::v4i64, 4 }, 2396 { ISD::ROTL, MVT::v8i32, 4 }, 2397 { ISD::ROTL, MVT::v16i16, 4 }, 2398 { ISD::ROTL, MVT::v32i8, 4 }, 2399 { ISD::ROTL, MVT::v2i64, 1 }, 2400 { ISD::ROTL, MVT::v4i32, 1 }, 2401 { ISD::ROTL, MVT::v8i16, 1 }, 2402 { ISD::ROTL, MVT::v16i8, 1 }, 2403 { ISD::ROTR, MVT::v4i64, 6 }, 2404 { ISD::ROTR, MVT::v8i32, 6 }, 2405 { ISD::ROTR, MVT::v16i16, 6 }, 2406 { ISD::ROTR, MVT::v32i8, 6 }, 2407 { ISD::ROTR, MVT::v2i64, 2 }, 2408 { ISD::ROTR, MVT::v4i32, 2 }, 2409 { ISD::ROTR, MVT::v8i16, 2 }, 2410 { ISD::ROTR, MVT::v16i8, 2 } 2411 }; 2412 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2413 { ISD::ROTL, MVT::i64, 1 }, 2414 { ISD::ROTR, MVT::i64, 1 }, 2415 { ISD::FSHL, MVT::i64, 4 } 2416 }; 2417 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2418 { ISD::ROTL, MVT::i32, 1 }, 2419 { ISD::ROTL, MVT::i16, 1 }, 2420 { ISD::ROTL, MVT::i8, 1 }, 2421 { ISD::ROTR, MVT::i32, 1 }, 2422 { ISD::ROTR, MVT::i16, 1 }, 2423 { ISD::ROTR, MVT::i8, 1 }, 2424 { ISD::FSHL, MVT::i32, 4 }, 2425 { ISD::FSHL, MVT::i16, 4 }, 2426 { ISD::FSHL, MVT::i8, 4 } 2427 }; 2428 2429 unsigned ISD = ISD::DELETED_NODE; 2430 switch (IID) { 2431 default: 2432 break; 2433 case Intrinsic::fshl: 2434 ISD = ISD::FSHL; 2435 if (Args[0] == Args[1]) 2436 ISD = ISD::ROTL; 2437 break; 2438 case Intrinsic::fshr: 2439 // FSHR has same costs so don't duplicate. 2440 ISD = ISD::FSHL; 2441 if (Args[0] == Args[1]) 2442 ISD = ISD::ROTR; 2443 break; 2444 } 2445 2446 if (ISD != ISD::DELETED_NODE) { 2447 // Legalize the type. 2448 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 2449 MVT MTy = LT.second; 2450 2451 // Attempt to lookup cost. 2452 if (ST->hasAVX512()) 2453 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2454 return LT.first * Entry->Cost; 2455 2456 if (ST->hasXOP()) 2457 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2458 return LT.first * Entry->Cost; 2459 2460 if (ST->is64Bit()) 2461 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2462 return LT.first * Entry->Cost; 2463 2464 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2465 return LT.first * Entry->Cost; 2466 } 2467 2468 return BaseT::getIntrinsicInstrCost(IID, RetTy, Args, FMF, VF, I); 2469 } 2470 2471 int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { 2472 static const CostTblEntry SLMCostTbl[] = { 2473 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 2474 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 2475 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 2476 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 2477 }; 2478 2479 assert(Val->isVectorTy() && "This must be a vector type"); 2480 Type *ScalarType = Val->getScalarType(); 2481 int RegisterFileMoveCost = 0; 2482 2483 if (Index != -1U && (Opcode == Instruction::ExtractElement || 2484 Opcode == Instruction::InsertElement)) { 2485 // Legalize the type. 2486 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 2487 2488 // This type is legalized to a scalar type. 2489 if (!LT.second.isVector()) 2490 return 0; 2491 2492 // The type may be split. Normalize the index to the new type. 2493 unsigned NumElts = LT.second.getVectorNumElements(); 2494 unsigned SubNumElts = NumElts; 2495 Index = Index % NumElts; 2496 2497 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 2498 // For inserts, we also need to insert the subvector back. 2499 if (LT.second.getSizeInBits() > 128) { 2500 assert((LT.second.getSizeInBits() % 128) == 0 && "Illegal vector"); 2501 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 2502 SubNumElts = NumElts / NumSubVecs; 2503 if (SubNumElts <= Index) { 2504 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 2505 Index %= SubNumElts; 2506 } 2507 } 2508 2509 if (Index == 0) { 2510 // Floating point scalars are already located in index #0. 2511 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 2512 // true for all. 2513 if (ScalarType->isFloatingPointTy()) 2514 return RegisterFileMoveCost; 2515 2516 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 2517 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 2518 return 1 + RegisterFileMoveCost; 2519 } 2520 2521 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2522 assert(ISD && "Unexpected vector opcode"); 2523 MVT MScalarTy = LT.second.getScalarType(); 2524 if (ST->isSLM()) 2525 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 2526 return Entry->Cost + RegisterFileMoveCost; 2527 2528 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 2529 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 2530 (MScalarTy.isInteger() && ST->hasSSE41())) 2531 return 1 + RegisterFileMoveCost; 2532 2533 // Assume insertps is relatively cheap on all targets. 2534 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 2535 Opcode == Instruction::InsertElement) 2536 return 1 + RegisterFileMoveCost; 2537 2538 // For extractions we just need to shuffle the element to index 0, which 2539 // should be very cheap (assume cost = 1). For insertions we need to shuffle 2540 // the elements to its destination. In both cases we must handle the 2541 // subvector move(s). 2542 // If the vector type is already less than 128-bits then don't reduce it. 2543 // TODO: Under what circumstances should we shuffle using the full width? 2544 int ShuffleCost = 1; 2545 if (Opcode == Instruction::InsertElement) { 2546 Type *SubTy = Val; 2547 EVT VT = TLI->getValueType(DL, Val); 2548 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 2549 SubTy = VectorType::get(ScalarType, SubNumElts); 2550 ShuffleCost = getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, 0, SubTy); 2551 } 2552 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 2553 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 2554 } 2555 2556 // Add to the base cost if we know that the extracted element of a vector is 2557 // destined to be moved to and used in the integer register file. 2558 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 2559 RegisterFileMoveCost += 1; 2560 2561 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 2562 } 2563 2564 int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 2565 MaybeAlign Alignment, unsigned AddressSpace, 2566 const Instruction *I) { 2567 // Handle non-power-of-two vectors such as <3 x float> 2568 if (VectorType *VTy = dyn_cast<VectorType>(Src)) { 2569 unsigned NumElem = VTy->getVectorNumElements(); 2570 2571 // Handle a few common cases: 2572 // <3 x float> 2573 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 2574 // Cost = 64 bit store + extract + 32 bit store. 2575 return 3; 2576 2577 // <3 x double> 2578 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 2579 // Cost = 128 bit store + unpack + 64 bit store. 2580 return 3; 2581 2582 // Assume that all other non-power-of-two numbers are scalarized. 2583 if (!isPowerOf2_32(NumElem)) { 2584 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment, 2585 AddressSpace); 2586 int SplitCost = getScalarizationOverhead(Src, Opcode == Instruction::Load, 2587 Opcode == Instruction::Store); 2588 return NumElem * Cost + SplitCost; 2589 } 2590 } 2591 2592 // Legalize the type. 2593 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 2594 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 2595 "Invalid Opcode"); 2596 2597 // Each load/store unit costs 1. 2598 int Cost = LT.first * 1; 2599 2600 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a 2601 // proxy for a double-pumped AVX memory interface such as on Sandybridge. 2602 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow()) 2603 Cost *= 2; 2604 2605 return Cost; 2606 } 2607 2608 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, 2609 unsigned Alignment, 2610 unsigned AddressSpace) { 2611 bool IsLoad = (Instruction::Load == Opcode); 2612 bool IsStore = (Instruction::Store == Opcode); 2613 2614 VectorType *SrcVTy = dyn_cast<VectorType>(SrcTy); 2615 if (!SrcVTy) 2616 // To calculate scalar take the regular cost, without mask 2617 return getMemoryOpCost(Opcode, SrcTy, MaybeAlign(Alignment), AddressSpace); 2618 2619 unsigned NumElem = SrcVTy->getVectorNumElements(); 2620 VectorType *MaskTy = 2621 VectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 2622 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, MaybeAlign(Alignment))) || 2623 (IsStore && !isLegalMaskedStore(SrcVTy, MaybeAlign(Alignment))) || 2624 !isPowerOf2_32(NumElem)) { 2625 // Scalarization 2626 int MaskSplitCost = getScalarizationOverhead(MaskTy, false, true); 2627 int ScalarCompareCost = getCmpSelInstrCost( 2628 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr); 2629 int BranchCost = getCFInstrCost(Instruction::Br); 2630 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 2631 2632 int ValueSplitCost = getScalarizationOverhead(SrcVTy, IsLoad, IsStore); 2633 int MemopCost = 2634 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2635 MaybeAlign(Alignment), AddressSpace); 2636 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 2637 } 2638 2639 // Legalize the type. 2640 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 2641 auto VT = TLI->getValueType(DL, SrcVTy); 2642 int Cost = 0; 2643 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 2644 LT.second.getVectorNumElements() == NumElem) 2645 // Promotion requires expand/truncate for data and a shuffle for mask. 2646 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, 0, nullptr) + 2647 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, 0, nullptr); 2648 2649 else if (LT.second.getVectorNumElements() > NumElem) { 2650 VectorType *NewMaskTy = VectorType::get(MaskTy->getVectorElementType(), 2651 LT.second.getVectorNumElements()); 2652 // Expanding requires fill mask with zeroes 2653 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, 0, MaskTy); 2654 } 2655 2656 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 2657 if (!ST->hasAVX512()) 2658 return Cost + LT.first * (IsLoad ? 2 : 8); 2659 2660 // AVX-512 masked load/store is cheapper 2661 return Cost + LT.first; 2662 } 2663 2664 int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE, 2665 const SCEV *Ptr) { 2666 // Address computations in vectorized code with non-consecutive addresses will 2667 // likely result in more instructions compared to scalar code where the 2668 // computation can more often be merged into the index mode. The resulting 2669 // extra micro-ops can significantly decrease throughput. 2670 const unsigned NumVectorInstToHideOverhead = 10; 2671 2672 // Cost modeling of Strided Access Computation is hidden by the indexing 2673 // modes of X86 regardless of the stride value. We dont believe that there 2674 // is a difference between constant strided access in gerenal and constant 2675 // strided value which is less than or equal to 64. 2676 // Even in the case of (loop invariant) stride whose value is not known at 2677 // compile time, the address computation will not incur more than one extra 2678 // ADD instruction. 2679 if (Ty->isVectorTy() && SE) { 2680 if (!BaseT::isStridedAccess(Ptr)) 2681 return NumVectorInstToHideOverhead; 2682 if (!BaseT::getConstantStrideStep(SE, Ptr)) 2683 return 1; 2684 } 2685 2686 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 2687 } 2688 2689 int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, Type *ValTy, 2690 bool IsPairwise) { 2691 // Just use the default implementation for pair reductions. 2692 if (IsPairwise) 2693 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise); 2694 2695 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 2696 // and make it as the cost. 2697 2698 static const CostTblEntry SLMCostTblNoPairWise[] = { 2699 { ISD::FADD, MVT::v2f64, 3 }, 2700 { ISD::ADD, MVT::v2i64, 5 }, 2701 }; 2702 2703 static const CostTblEntry SSE2CostTblNoPairWise[] = { 2704 { ISD::FADD, MVT::v2f64, 2 }, 2705 { ISD::FADD, MVT::v4f32, 4 }, 2706 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 2707 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 2708 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 2709 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 2710 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 2711 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 2712 { ISD::ADD, MVT::v2i8, 2 }, 2713 { ISD::ADD, MVT::v4i8, 2 }, 2714 { ISD::ADD, MVT::v8i8, 2 }, 2715 { ISD::ADD, MVT::v16i8, 3 }, 2716 }; 2717 2718 static const CostTblEntry AVX1CostTblNoPairWise[] = { 2719 { ISD::FADD, MVT::v4f64, 3 }, 2720 { ISD::FADD, MVT::v4f32, 3 }, 2721 { ISD::FADD, MVT::v8f32, 4 }, 2722 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 2723 { ISD::ADD, MVT::v4i64, 3 }, 2724 { ISD::ADD, MVT::v8i32, 5 }, 2725 { ISD::ADD, MVT::v16i16, 5 }, 2726 { ISD::ADD, MVT::v32i8, 4 }, 2727 }; 2728 2729 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2730 assert(ISD && "Invalid opcode"); 2731 2732 // Before legalizing the type, give a chance to look up illegal narrow types 2733 // in the table. 2734 // FIXME: Is there a better way to do this? 2735 EVT VT = TLI->getValueType(DL, ValTy); 2736 if (VT.isSimple()) { 2737 MVT MTy = VT.getSimpleVT(); 2738 if (ST->isSLM()) 2739 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 2740 return Entry->Cost; 2741 2742 if (ST->hasAVX()) 2743 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 2744 return Entry->Cost; 2745 2746 if (ST->hasSSE2()) 2747 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 2748 return Entry->Cost; 2749 } 2750 2751 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2752 2753 MVT MTy = LT.second; 2754 2755 unsigned ArithmeticCost = 0; 2756 if (LT.first != 1 && MTy.isVector() && 2757 MTy.getVectorNumElements() < ValTy->getVectorNumElements()) { 2758 // Type needs to be split. We need LT.first - 1 arithmetic ops. 2759 Type *SingleOpTy = VectorType::get(ValTy->getVectorElementType(), 2760 MTy.getVectorNumElements()); 2761 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy); 2762 ArithmeticCost *= LT.first - 1; 2763 } 2764 2765 if (ST->isSLM()) 2766 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 2767 return ArithmeticCost + Entry->Cost; 2768 2769 if (ST->hasAVX()) 2770 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 2771 return ArithmeticCost + Entry->Cost; 2772 2773 if (ST->hasSSE2()) 2774 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 2775 return ArithmeticCost + Entry->Cost; 2776 2777 // FIXME: These assume a naive kshift+binop lowering, which is probably 2778 // conservative in most cases. 2779 static const CostTblEntry AVX512BoolReduction[] = { 2780 { ISD::AND, MVT::v2i1, 3 }, 2781 { ISD::AND, MVT::v4i1, 5 }, 2782 { ISD::AND, MVT::v8i1, 7 }, 2783 { ISD::AND, MVT::v16i1, 9 }, 2784 { ISD::AND, MVT::v32i1, 11 }, 2785 { ISD::AND, MVT::v64i1, 13 }, 2786 { ISD::OR, MVT::v2i1, 3 }, 2787 { ISD::OR, MVT::v4i1, 5 }, 2788 { ISD::OR, MVT::v8i1, 7 }, 2789 { ISD::OR, MVT::v16i1, 9 }, 2790 { ISD::OR, MVT::v32i1, 11 }, 2791 { ISD::OR, MVT::v64i1, 13 }, 2792 }; 2793 2794 static const CostTblEntry AVX2BoolReduction[] = { 2795 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 2796 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 2797 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 2798 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 2799 }; 2800 2801 static const CostTblEntry AVX1BoolReduction[] = { 2802 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 2803 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 2804 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 2805 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 2806 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 2807 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 2808 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 2809 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 2810 }; 2811 2812 static const CostTblEntry SSE2BoolReduction[] = { 2813 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 2814 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 2815 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 2816 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 2817 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 2818 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 2819 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 2820 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 2821 }; 2822 2823 // Handle bool allof/anyof patterns. 2824 if (ValTy->getVectorElementType()->isIntegerTy(1)) { 2825 unsigned ArithmeticCost = 0; 2826 if (LT.first != 1 && MTy.isVector() && 2827 MTy.getVectorNumElements() < ValTy->getVectorNumElements()) { 2828 // Type needs to be split. We need LT.first - 1 arithmetic ops. 2829 Type *SingleOpTy = VectorType::get(ValTy->getVectorElementType(), 2830 MTy.getVectorNumElements()); 2831 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy); 2832 ArithmeticCost *= LT.first - 1; 2833 } 2834 2835 if (ST->hasAVX512()) 2836 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 2837 return ArithmeticCost + Entry->Cost; 2838 if (ST->hasAVX2()) 2839 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 2840 return ArithmeticCost + Entry->Cost; 2841 if (ST->hasAVX()) 2842 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 2843 return ArithmeticCost + Entry->Cost; 2844 if (ST->hasSSE2()) 2845 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 2846 return ArithmeticCost + Entry->Cost; 2847 2848 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise); 2849 } 2850 2851 unsigned NumVecElts = ValTy->getVectorNumElements(); 2852 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 2853 2854 // Special case power of 2 reductions where the scalar type isn't changed 2855 // by type legalization. 2856 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 2857 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise); 2858 2859 unsigned ReductionCost = 0; 2860 2861 Type *Ty = ValTy; 2862 if (LT.first != 1 && MTy.isVector() && 2863 MTy.getVectorNumElements() < ValTy->getVectorNumElements()) { 2864 // Type needs to be split. We need LT.first - 1 arithmetic ops. 2865 Ty = VectorType::get(ValTy->getVectorElementType(), 2866 MTy.getVectorNumElements()); 2867 ReductionCost = getArithmeticInstrCost(Opcode, Ty); 2868 ReductionCost *= LT.first - 1; 2869 NumVecElts = MTy.getVectorNumElements(); 2870 } 2871 2872 // Now handle reduction with the legal type, taking into account size changes 2873 // at each level. 2874 while (NumVecElts > 1) { 2875 // Determine the size of the remaining vector we need to reduce. 2876 unsigned Size = NumVecElts * ScalarSize; 2877 NumVecElts /= 2; 2878 // If we're reducing from 256/512 bits, use an extract_subvector. 2879 if (Size > 128) { 2880 Type *SubTy = VectorType::get(ValTy->getVectorElementType(), NumVecElts); 2881 ReductionCost += 2882 getShuffleCost(TTI::SK_ExtractSubvector, Ty, NumVecElts, SubTy); 2883 Ty = SubTy; 2884 } else if (Size == 128) { 2885 // Reducing from 128 bits is a permute of v2f64/v2i64. 2886 Type *ShufTy; 2887 if (ValTy->isFloatingPointTy()) 2888 ShufTy = VectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 2889 else 2890 ShufTy = VectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 2891 ReductionCost += 2892 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 2893 } else if (Size == 64) { 2894 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 2895 Type *ShufTy; 2896 if (ValTy->isFloatingPointTy()) 2897 ShufTy = VectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 2898 else 2899 ShufTy = VectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 2900 ReductionCost += 2901 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 2902 } else { 2903 // Reducing from smaller size is a shift by immediate. 2904 Type *ShiftTy = VectorType::get( 2905 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 2906 ReductionCost += getArithmeticInstrCost( 2907 Instruction::LShr, ShiftTy, TargetTransformInfo::OK_AnyValue, 2908 TargetTransformInfo::OK_UniformConstantValue, 2909 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 2910 } 2911 2912 // Add the arithmetic op for this level. 2913 ReductionCost += getArithmeticInstrCost(Opcode, Ty); 2914 } 2915 2916 // Add the final extract element to the cost. 2917 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 2918 } 2919 2920 int X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, bool IsUnsigned) { 2921 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 2922 2923 MVT MTy = LT.second; 2924 2925 int ISD; 2926 if (Ty->isIntOrIntVectorTy()) { 2927 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 2928 } else { 2929 assert(Ty->isFPOrFPVectorTy() && 2930 "Expected float point or integer vector type."); 2931 ISD = ISD::FMINNUM; 2932 } 2933 2934 static const CostTblEntry SSE1CostTbl[] = { 2935 {ISD::FMINNUM, MVT::v4f32, 1}, 2936 }; 2937 2938 static const CostTblEntry SSE2CostTbl[] = { 2939 {ISD::FMINNUM, MVT::v2f64, 1}, 2940 {ISD::SMIN, MVT::v8i16, 1}, 2941 {ISD::UMIN, MVT::v16i8, 1}, 2942 }; 2943 2944 static const CostTblEntry SSE41CostTbl[] = { 2945 {ISD::SMIN, MVT::v4i32, 1}, 2946 {ISD::UMIN, MVT::v4i32, 1}, 2947 {ISD::UMIN, MVT::v8i16, 1}, 2948 {ISD::SMIN, MVT::v16i8, 1}, 2949 }; 2950 2951 static const CostTblEntry SSE42CostTbl[] = { 2952 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 2953 }; 2954 2955 static const CostTblEntry AVX1CostTbl[] = { 2956 {ISD::FMINNUM, MVT::v8f32, 1}, 2957 {ISD::FMINNUM, MVT::v4f64, 1}, 2958 {ISD::SMIN, MVT::v8i32, 3}, 2959 {ISD::UMIN, MVT::v8i32, 3}, 2960 {ISD::SMIN, MVT::v16i16, 3}, 2961 {ISD::UMIN, MVT::v16i16, 3}, 2962 {ISD::SMIN, MVT::v32i8, 3}, 2963 {ISD::UMIN, MVT::v32i8, 3}, 2964 }; 2965 2966 static const CostTblEntry AVX2CostTbl[] = { 2967 {ISD::SMIN, MVT::v8i32, 1}, 2968 {ISD::UMIN, MVT::v8i32, 1}, 2969 {ISD::SMIN, MVT::v16i16, 1}, 2970 {ISD::UMIN, MVT::v16i16, 1}, 2971 {ISD::SMIN, MVT::v32i8, 1}, 2972 {ISD::UMIN, MVT::v32i8, 1}, 2973 }; 2974 2975 static const CostTblEntry AVX512CostTbl[] = { 2976 {ISD::FMINNUM, MVT::v16f32, 1}, 2977 {ISD::FMINNUM, MVT::v8f64, 1}, 2978 {ISD::SMIN, MVT::v2i64, 1}, 2979 {ISD::UMIN, MVT::v2i64, 1}, 2980 {ISD::SMIN, MVT::v4i64, 1}, 2981 {ISD::UMIN, MVT::v4i64, 1}, 2982 {ISD::SMIN, MVT::v8i64, 1}, 2983 {ISD::UMIN, MVT::v8i64, 1}, 2984 {ISD::SMIN, MVT::v16i32, 1}, 2985 {ISD::UMIN, MVT::v16i32, 1}, 2986 }; 2987 2988 static const CostTblEntry AVX512BWCostTbl[] = { 2989 {ISD::SMIN, MVT::v32i16, 1}, 2990 {ISD::UMIN, MVT::v32i16, 1}, 2991 {ISD::SMIN, MVT::v64i8, 1}, 2992 {ISD::UMIN, MVT::v64i8, 1}, 2993 }; 2994 2995 // If we have a native MIN/MAX instruction for this type, use it. 2996 if (ST->hasBWI()) 2997 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2998 return LT.first * Entry->Cost; 2999 3000 if (ST->hasAVX512()) 3001 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3002 return LT.first * Entry->Cost; 3003 3004 if (ST->hasAVX2()) 3005 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3006 return LT.first * Entry->Cost; 3007 3008 if (ST->hasAVX()) 3009 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3010 return LT.first * Entry->Cost; 3011 3012 if (ST->hasSSE42()) 3013 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3014 return LT.first * Entry->Cost; 3015 3016 if (ST->hasSSE41()) 3017 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3018 return LT.first * Entry->Cost; 3019 3020 if (ST->hasSSE2()) 3021 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3022 return LT.first * Entry->Cost; 3023 3024 if (ST->hasSSE1()) 3025 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3026 return LT.first * Entry->Cost; 3027 3028 unsigned CmpOpcode; 3029 if (Ty->isFPOrFPVectorTy()) { 3030 CmpOpcode = Instruction::FCmp; 3031 } else { 3032 assert(Ty->isIntOrIntVectorTy() && 3033 "expecting floating point or integer type for min/max reduction"); 3034 CmpOpcode = Instruction::ICmp; 3035 } 3036 3037 // Otherwise fall back to cmp+select. 3038 return getCmpSelInstrCost(CmpOpcode, Ty, CondTy, nullptr) + 3039 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, nullptr); 3040 } 3041 3042 int X86TTIImpl::getMinMaxReductionCost(Type *ValTy, Type *CondTy, 3043 bool IsPairwise, bool IsUnsigned) { 3044 // Just use the default implementation for pair reductions. 3045 if (IsPairwise) 3046 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned); 3047 3048 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3049 3050 MVT MTy = LT.second; 3051 3052 int ISD; 3053 if (ValTy->isIntOrIntVectorTy()) { 3054 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3055 } else { 3056 assert(ValTy->isFPOrFPVectorTy() && 3057 "Expected float point or integer vector type."); 3058 ISD = ISD::FMINNUM; 3059 } 3060 3061 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3062 // and make it as the cost. 3063 3064 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3065 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 3066 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 3067 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 3068 }; 3069 3070 static const CostTblEntry SSE41CostTblNoPairWise[] = { 3071 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 3072 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 3073 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 3074 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 3075 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 3076 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 3077 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 3078 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 3079 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 3080 {ISD::SMIN, MVT::v16i8, 6}, 3081 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 3082 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 3083 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 3084 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 3085 }; 3086 3087 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3088 {ISD::SMIN, MVT::v16i16, 6}, 3089 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 3090 {ISD::SMIN, MVT::v32i8, 8}, 3091 {ISD::UMIN, MVT::v32i8, 8}, 3092 }; 3093 3094 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 3095 {ISD::SMIN, MVT::v32i16, 8}, 3096 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 3097 {ISD::SMIN, MVT::v64i8, 10}, 3098 {ISD::UMIN, MVT::v64i8, 10}, 3099 }; 3100 3101 // Before legalizing the type, give a chance to look up illegal narrow types 3102 // in the table. 3103 // FIXME: Is there a better way to do this? 3104 EVT VT = TLI->getValueType(DL, ValTy); 3105 if (VT.isSimple()) { 3106 MVT MTy = VT.getSimpleVT(); 3107 if (ST->hasBWI()) 3108 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3109 return Entry->Cost; 3110 3111 if (ST->hasAVX()) 3112 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3113 return Entry->Cost; 3114 3115 if (ST->hasSSE41()) 3116 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3117 return Entry->Cost; 3118 3119 if (ST->hasSSE2()) 3120 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3121 return Entry->Cost; 3122 } 3123 3124 unsigned NumVecElts = ValTy->getVectorNumElements(); 3125 3126 Type *Ty = ValTy; 3127 unsigned MinMaxCost = 0; 3128 if (LT.first != 1 && MTy.isVector() && 3129 MTy.getVectorNumElements() < ValTy->getVectorNumElements()) { 3130 // Type needs to be split. We need LT.first - 1 operations ops. 3131 Ty = VectorType::get(ValTy->getVectorElementType(), 3132 MTy.getVectorNumElements()); 3133 Type *SubCondTy = VectorType::get(CondTy->getVectorElementType(), 3134 MTy.getVectorNumElements()); 3135 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3136 MinMaxCost *= LT.first - 1; 3137 NumVecElts = MTy.getVectorNumElements(); 3138 } 3139 3140 if (ST->hasBWI()) 3141 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3142 return MinMaxCost + Entry->Cost; 3143 3144 if (ST->hasAVX()) 3145 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3146 return MinMaxCost + Entry->Cost; 3147 3148 if (ST->hasSSE41()) 3149 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3150 return MinMaxCost + Entry->Cost; 3151 3152 if (ST->hasSSE2()) 3153 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3154 return MinMaxCost + Entry->Cost; 3155 3156 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 3157 3158 // Special case power of 2 reductions where the scalar type isn't changed 3159 // by type legalization. 3160 if (!isPowerOf2_32(ValTy->getVectorNumElements()) || 3161 ScalarSize != MTy.getScalarSizeInBits()) 3162 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned); 3163 3164 // Now handle reduction with the legal type, taking into account size changes 3165 // at each level. 3166 while (NumVecElts > 1) { 3167 // Determine the size of the remaining vector we need to reduce. 3168 unsigned Size = NumVecElts * ScalarSize; 3169 NumVecElts /= 2; 3170 // If we're reducing from 256/512 bits, use an extract_subvector. 3171 if (Size > 128) { 3172 Type *SubTy = VectorType::get(ValTy->getVectorElementType(), NumVecElts); 3173 MinMaxCost += 3174 getShuffleCost(TTI::SK_ExtractSubvector, Ty, NumVecElts, SubTy); 3175 Ty = SubTy; 3176 } else if (Size == 128) { 3177 // Reducing from 128 bits is a permute of v2f64/v2i64. 3178 Type *ShufTy; 3179 if (ValTy->isFloatingPointTy()) 3180 ShufTy = VectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 3181 else 3182 ShufTy = VectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 3183 MinMaxCost += 3184 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3185 } else if (Size == 64) { 3186 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3187 Type *ShufTy; 3188 if (ValTy->isFloatingPointTy()) 3189 ShufTy = VectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 3190 else 3191 ShufTy = VectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 3192 MinMaxCost += 3193 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3194 } else { 3195 // Reducing from smaller size is a shift by immediate. 3196 Type *ShiftTy = VectorType::get( 3197 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 3198 MinMaxCost += getArithmeticInstrCost( 3199 Instruction::LShr, ShiftTy, TargetTransformInfo::OK_AnyValue, 3200 TargetTransformInfo::OK_UniformConstantValue, 3201 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3202 } 3203 3204 // Add the arithmetic op for this level. 3205 Type *SubCondTy = VectorType::get(CondTy->getVectorElementType(), 3206 Ty->getVectorNumElements()); 3207 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3208 } 3209 3210 // Add the final extract element to the cost. 3211 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3212 } 3213 3214 /// Calculate the cost of materializing a 64-bit value. This helper 3215 /// method might only calculate a fraction of a larger immediate. Therefore it 3216 /// is valid to return a cost of ZERO. 3217 int X86TTIImpl::getIntImmCost(int64_t Val) { 3218 if (Val == 0) 3219 return TTI::TCC_Free; 3220 3221 if (isInt<32>(Val)) 3222 return TTI::TCC_Basic; 3223 3224 return 2 * TTI::TCC_Basic; 3225 } 3226 3227 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { 3228 assert(Ty->isIntegerTy()); 3229 3230 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3231 if (BitSize == 0) 3232 return ~0U; 3233 3234 // Never hoist constants larger than 128bit, because this might lead to 3235 // incorrect code generation or assertions in codegen. 3236 // Fixme: Create a cost model for types larger than i128 once the codegen 3237 // issues have been fixed. 3238 if (BitSize > 128) 3239 return TTI::TCC_Free; 3240 3241 if (Imm == 0) 3242 return TTI::TCC_Free; 3243 3244 // Sign-extend all constants to a multiple of 64-bit. 3245 APInt ImmVal = Imm; 3246 if (BitSize % 64 != 0) 3247 ImmVal = Imm.sext(alignTo(BitSize, 64)); 3248 3249 // Split the constant into 64-bit chunks and calculate the cost for each 3250 // chunk. 3251 int Cost = 0; 3252 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 3253 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 3254 int64_t Val = Tmp.getSExtValue(); 3255 Cost += getIntImmCost(Val); 3256 } 3257 // We need at least one instruction to materialize the constant. 3258 return std::max(1, Cost); 3259 } 3260 3261 int X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, 3262 Type *Ty) { 3263 assert(Ty->isIntegerTy()); 3264 3265 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3266 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3267 // here, so that constant hoisting will ignore this constant. 3268 if (BitSize == 0) 3269 return TTI::TCC_Free; 3270 3271 unsigned ImmIdx = ~0U; 3272 switch (Opcode) { 3273 default: 3274 return TTI::TCC_Free; 3275 case Instruction::GetElementPtr: 3276 // Always hoist the base address of a GetElementPtr. This prevents the 3277 // creation of new constants for every base constant that gets constant 3278 // folded with the offset. 3279 if (Idx == 0) 3280 return 2 * TTI::TCC_Basic; 3281 return TTI::TCC_Free; 3282 case Instruction::Store: 3283 ImmIdx = 0; 3284 break; 3285 case Instruction::ICmp: 3286 // This is an imperfect hack to prevent constant hoisting of 3287 // compares that might be trying to check if a 64-bit value fits in 3288 // 32-bits. The backend can optimize these cases using a right shift by 32. 3289 // Ideally we would check the compare predicate here. There also other 3290 // similar immediates the backend can use shifts for. 3291 if (Idx == 1 && Imm.getBitWidth() == 64) { 3292 uint64_t ImmVal = Imm.getZExtValue(); 3293 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 3294 return TTI::TCC_Free; 3295 } 3296 ImmIdx = 1; 3297 break; 3298 case Instruction::And: 3299 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 3300 // by using a 32-bit operation with implicit zero extension. Detect such 3301 // immediates here as the normal path expects bit 31 to be sign extended. 3302 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 3303 return TTI::TCC_Free; 3304 ImmIdx = 1; 3305 break; 3306 case Instruction::Add: 3307 case Instruction::Sub: 3308 // For add/sub, we can use the opposite instruction for INT32_MIN. 3309 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 3310 return TTI::TCC_Free; 3311 ImmIdx = 1; 3312 break; 3313 case Instruction::UDiv: 3314 case Instruction::SDiv: 3315 case Instruction::URem: 3316 case Instruction::SRem: 3317 // Division by constant is typically expanded later into a different 3318 // instruction sequence. This completely changes the constants. 3319 // Report them as "free" to stop ConstantHoist from marking them as opaque. 3320 return TTI::TCC_Free; 3321 case Instruction::Mul: 3322 case Instruction::Or: 3323 case Instruction::Xor: 3324 ImmIdx = 1; 3325 break; 3326 // Always return TCC_Free for the shift value of a shift instruction. 3327 case Instruction::Shl: 3328 case Instruction::LShr: 3329 case Instruction::AShr: 3330 if (Idx == 1) 3331 return TTI::TCC_Free; 3332 break; 3333 case Instruction::Trunc: 3334 case Instruction::ZExt: 3335 case Instruction::SExt: 3336 case Instruction::IntToPtr: 3337 case Instruction::PtrToInt: 3338 case Instruction::BitCast: 3339 case Instruction::PHI: 3340 case Instruction::Call: 3341 case Instruction::Select: 3342 case Instruction::Ret: 3343 case Instruction::Load: 3344 break; 3345 } 3346 3347 if (Idx == ImmIdx) { 3348 int NumConstants = divideCeil(BitSize, 64); 3349 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty); 3350 return (Cost <= NumConstants * TTI::TCC_Basic) 3351 ? static_cast<int>(TTI::TCC_Free) 3352 : Cost; 3353 } 3354 3355 return X86TTIImpl::getIntImmCost(Imm, Ty); 3356 } 3357 3358 int X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 3359 const APInt &Imm, Type *Ty) { 3360 assert(Ty->isIntegerTy()); 3361 3362 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3363 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3364 // here, so that constant hoisting will ignore this constant. 3365 if (BitSize == 0) 3366 return TTI::TCC_Free; 3367 3368 switch (IID) { 3369 default: 3370 return TTI::TCC_Free; 3371 case Intrinsic::sadd_with_overflow: 3372 case Intrinsic::uadd_with_overflow: 3373 case Intrinsic::ssub_with_overflow: 3374 case Intrinsic::usub_with_overflow: 3375 case Intrinsic::smul_with_overflow: 3376 case Intrinsic::umul_with_overflow: 3377 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 3378 return TTI::TCC_Free; 3379 break; 3380 case Intrinsic::experimental_stackmap: 3381 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 3382 return TTI::TCC_Free; 3383 break; 3384 case Intrinsic::experimental_patchpoint_void: 3385 case Intrinsic::experimental_patchpoint_i64: 3386 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 3387 return TTI::TCC_Free; 3388 break; 3389 } 3390 return X86TTIImpl::getIntImmCost(Imm, Ty); 3391 } 3392 3393 unsigned X86TTIImpl::getUserCost(const User *U, 3394 ArrayRef<const Value *> Operands) { 3395 if (isa<StoreInst>(U)) { 3396 Value *Ptr = U->getOperand(1); 3397 // Store instruction with index and scale costs 2 Uops. 3398 // Check the preceding GEP to identify non-const indices. 3399 if (auto GEP = dyn_cast<GetElementPtrInst>(Ptr)) { 3400 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3401 return TTI::TCC_Basic * 2; 3402 } 3403 return TTI::TCC_Basic; 3404 } 3405 return BaseT::getUserCost(U, Operands); 3406 } 3407 3408 // Return an average cost of Gather / Scatter instruction, maybe improved later 3409 int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, Value *Ptr, 3410 unsigned Alignment, unsigned AddressSpace) { 3411 3412 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 3413 unsigned VF = SrcVTy->getVectorNumElements(); 3414 3415 // Try to reduce index size from 64 bit (default for GEP) 3416 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 3417 // operation will use 16 x 64 indices which do not fit in a zmm and needs 3418 // to split. Also check that the base pointer is the same for all lanes, 3419 // and that there's at most one variable index. 3420 auto getIndexSizeInBits = [](Value *Ptr, const DataLayout& DL) { 3421 unsigned IndexSize = DL.getPointerSizeInBits(); 3422 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 3423 if (IndexSize < 64 || !GEP) 3424 return IndexSize; 3425 3426 unsigned NumOfVarIndices = 0; 3427 Value *Ptrs = GEP->getPointerOperand(); 3428 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 3429 return IndexSize; 3430 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 3431 if (isa<Constant>(GEP->getOperand(i))) 3432 continue; 3433 Type *IndxTy = GEP->getOperand(i)->getType(); 3434 if (IndxTy->isVectorTy()) 3435 IndxTy = IndxTy->getVectorElementType(); 3436 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 3437 !isa<SExtInst>(GEP->getOperand(i))) || 3438 ++NumOfVarIndices > 1) 3439 return IndexSize; // 64 3440 } 3441 return (unsigned)32; 3442 }; 3443 3444 3445 // Trying to reduce IndexSize to 32 bits for vector 16. 3446 // By default the IndexSize is equal to pointer size. 3447 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 3448 ? getIndexSizeInBits(Ptr, DL) 3449 : DL.getPointerSizeInBits(); 3450 3451 Type *IndexVTy = VectorType::get(IntegerType::get(SrcVTy->getContext(), 3452 IndexSize), VF); 3453 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy); 3454 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3455 int SplitFactor = std::max(IdxsLT.first, SrcLT.first); 3456 if (SplitFactor > 1) { 3457 // Handle splitting of vector of pointers 3458 Type *SplitSrcTy = VectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 3459 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 3460 AddressSpace); 3461 } 3462 3463 // The gather / scatter cost is given by Intel architects. It is a rough 3464 // number since we are looking at one instruction in a time. 3465 const int GSOverhead = (Opcode == Instruction::Load) 3466 ? ST->getGatherOverhead() 3467 : ST->getScatterOverhead(); 3468 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3469 MaybeAlign(Alignment), AddressSpace); 3470 } 3471 3472 /// Return the cost of full scalarization of gather / scatter operation. 3473 /// 3474 /// Opcode - Load or Store instruction. 3475 /// SrcVTy - The type of the data vector that should be gathered or scattered. 3476 /// VariableMask - The mask is non-constant at compile time. 3477 /// Alignment - Alignment for one element. 3478 /// AddressSpace - pointer[s] address space. 3479 /// 3480 int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 3481 bool VariableMask, unsigned Alignment, 3482 unsigned AddressSpace) { 3483 unsigned VF = SrcVTy->getVectorNumElements(); 3484 3485 int MaskUnpackCost = 0; 3486 if (VariableMask) { 3487 VectorType *MaskTy = 3488 VectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 3489 MaskUnpackCost = getScalarizationOverhead(MaskTy, false, true); 3490 int ScalarCompareCost = 3491 getCmpSelInstrCost(Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), 3492 nullptr); 3493 int BranchCost = getCFInstrCost(Instruction::Br); 3494 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 3495 } 3496 3497 // The cost of the scalar loads/stores. 3498 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3499 MaybeAlign(Alignment), AddressSpace); 3500 3501 int InsertExtractCost = 0; 3502 if (Opcode == Instruction::Load) 3503 for (unsigned i = 0; i < VF; ++i) 3504 // Add the cost of inserting each scalar load into the vector 3505 InsertExtractCost += 3506 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 3507 else 3508 for (unsigned i = 0; i < VF; ++i) 3509 // Add the cost of extracting each element out of the data vector 3510 InsertExtractCost += 3511 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 3512 3513 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 3514 } 3515 3516 /// Calculate the cost of Gather / Scatter operation 3517 int X86TTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *SrcVTy, 3518 Value *Ptr, bool VariableMask, 3519 unsigned Alignment, 3520 const Instruction *I = nullptr) { 3521 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 3522 unsigned VF = SrcVTy->getVectorNumElements(); 3523 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 3524 if (!PtrTy && Ptr->getType()->isVectorTy()) 3525 PtrTy = dyn_cast<PointerType>(Ptr->getType()->getVectorElementType()); 3526 assert(PtrTy && "Unexpected type for Ptr argument"); 3527 unsigned AddressSpace = PtrTy->getAddressSpace(); 3528 3529 bool Scalarize = false; 3530 if ((Opcode == Instruction::Load && 3531 !isLegalMaskedGather(SrcVTy, MaybeAlign(Alignment))) || 3532 (Opcode == Instruction::Store && 3533 !isLegalMaskedScatter(SrcVTy, MaybeAlign(Alignment)))) 3534 Scalarize = true; 3535 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 3536 // Vector-4 of gather/scatter instruction does not exist on KNL. 3537 // We can extend it to 8 elements, but zeroing upper bits of 3538 // the mask vector will add more instructions. Right now we give the scalar 3539 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 3540 // is better in the VariableMask case. 3541 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 3542 Scalarize = true; 3543 3544 if (Scalarize) 3545 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 3546 AddressSpace); 3547 3548 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 3549 } 3550 3551 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 3552 TargetTransformInfo::LSRCost &C2) { 3553 // X86 specific here are "instruction number 1st priority". 3554 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 3555 C1.NumIVMuls, C1.NumBaseAdds, 3556 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 3557 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 3558 C2.NumIVMuls, C2.NumBaseAdds, 3559 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 3560 } 3561 3562 bool X86TTIImpl::canMacroFuseCmp() { 3563 return ST->hasMacroFusion() || ST->hasBranchFusion(); 3564 } 3565 3566 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, MaybeAlign Alignment) { 3567 if (!ST->hasAVX()) 3568 return false; 3569 3570 // The backend can't handle a single element vector. 3571 if (isa<VectorType>(DataTy) && DataTy->getVectorNumElements() == 1) 3572 return false; 3573 Type *ScalarTy = DataTy->getScalarType(); 3574 3575 if (ScalarTy->isPointerTy()) 3576 return true; 3577 3578 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 3579 return true; 3580 3581 if (!ScalarTy->isIntegerTy()) 3582 return false; 3583 3584 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 3585 return IntWidth == 32 || IntWidth == 64 || 3586 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 3587 } 3588 3589 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, MaybeAlign Alignment) { 3590 return isLegalMaskedLoad(DataType, Alignment); 3591 } 3592 3593 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 3594 unsigned DataSize = DL.getTypeStoreSize(DataType); 3595 // The only supported nontemporal loads are for aligned vectors of 16 or 32 3596 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 3597 // (the equivalent stores only require AVX). 3598 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 3599 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 3600 3601 return false; 3602 } 3603 3604 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 3605 unsigned DataSize = DL.getTypeStoreSize(DataType); 3606 3607 // SSE4A supports nontemporal stores of float and double at arbitrary 3608 // alignment. 3609 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 3610 return true; 3611 3612 // Besides the SSE4A subtarget exception above, only aligned stores are 3613 // available nontemporaly on any other subtarget. And only stores with a size 3614 // of 4..32 bytes (powers of 2, only) are permitted. 3615 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 3616 !isPowerOf2_32(DataSize)) 3617 return false; 3618 3619 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 3620 // loads require AVX2). 3621 if (DataSize == 32) 3622 return ST->hasAVX(); 3623 else if (DataSize == 16) 3624 return ST->hasSSE1(); 3625 return true; 3626 } 3627 3628 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 3629 if (!isa<VectorType>(DataTy)) 3630 return false; 3631 3632 if (!ST->hasAVX512()) 3633 return false; 3634 3635 // The backend can't handle a single element vector. 3636 if (DataTy->getVectorNumElements() == 1) 3637 return false; 3638 3639 Type *ScalarTy = DataTy->getVectorElementType(); 3640 3641 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 3642 return true; 3643 3644 if (!ScalarTy->isIntegerTy()) 3645 return false; 3646 3647 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 3648 return IntWidth == 32 || IntWidth == 64 || 3649 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 3650 } 3651 3652 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 3653 return isLegalMaskedExpandLoad(DataTy); 3654 } 3655 3656 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, MaybeAlign Alignment) { 3657 // Some CPUs have better gather performance than others. 3658 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 3659 // enable gather with a -march. 3660 if (!(ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()))) 3661 return false; 3662 3663 // This function is called now in two cases: from the Loop Vectorizer 3664 // and from the Scalarizer. 3665 // When the Loop Vectorizer asks about legality of the feature, 3666 // the vectorization factor is not calculated yet. The Loop Vectorizer 3667 // sends a scalar type and the decision is based on the width of the 3668 // scalar element. 3669 // Later on, the cost model will estimate usage this intrinsic based on 3670 // the vector type. 3671 // The Scalarizer asks again about legality. It sends a vector type. 3672 // In this case we can reject non-power-of-2 vectors. 3673 // We also reject single element vectors as the type legalizer can't 3674 // scalarize it. 3675 if (isa<VectorType>(DataTy)) { 3676 unsigned NumElts = DataTy->getVectorNumElements(); 3677 if (NumElts == 1 || !isPowerOf2_32(NumElts)) 3678 return false; 3679 } 3680 Type *ScalarTy = DataTy->getScalarType(); 3681 if (ScalarTy->isPointerTy()) 3682 return true; 3683 3684 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 3685 return true; 3686 3687 if (!ScalarTy->isIntegerTy()) 3688 return false; 3689 3690 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 3691 return IntWidth == 32 || IntWidth == 64; 3692 } 3693 3694 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, MaybeAlign Alignment) { 3695 // AVX2 doesn't support scatter 3696 if (!ST->hasAVX512()) 3697 return false; 3698 return isLegalMaskedGather(DataType, Alignment); 3699 } 3700 3701 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 3702 EVT VT = TLI->getValueType(DL, DataType); 3703 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 3704 } 3705 3706 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 3707 return false; 3708 } 3709 3710 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 3711 const Function *Callee) const { 3712 const TargetMachine &TM = getTLI()->getTargetMachine(); 3713 3714 // Work this as a subsetting of subtarget features. 3715 const FeatureBitset &CallerBits = 3716 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 3717 const FeatureBitset &CalleeBits = 3718 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 3719 3720 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 3721 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 3722 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 3723 } 3724 3725 bool X86TTIImpl::areFunctionArgsABICompatible( 3726 const Function *Caller, const Function *Callee, 3727 SmallPtrSetImpl<Argument *> &Args) const { 3728 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args)) 3729 return false; 3730 3731 // If we get here, we know the target features match. If one function 3732 // considers 512-bit vectors legal and the other does not, consider them 3733 // incompatible. 3734 // FIXME Look at the arguments and only consider 512 bit or larger vectors? 3735 const TargetMachine &TM = getTLI()->getTargetMachine(); 3736 3737 return TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 3738 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs(); 3739 } 3740 3741 X86TTIImpl::TTI::MemCmpExpansionOptions 3742 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 3743 TTI::MemCmpExpansionOptions Options; 3744 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 3745 Options.NumLoadsPerBlock = 2; 3746 // All GPR and vector loads can be unaligned. 3747 Options.AllowOverlappingLoads = true; 3748 if (IsZeroCmp) { 3749 // Only enable vector loads for equality comparison. Right now the vector 3750 // version is not as fast for three way compare (see #33329). 3751 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 3752 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 3753 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 3754 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 3755 } 3756 if (ST->is64Bit()) { 3757 Options.LoadSizes.push_back(8); 3758 } 3759 Options.LoadSizes.push_back(4); 3760 Options.LoadSizes.push_back(2); 3761 Options.LoadSizes.push_back(1); 3762 return Options; 3763 } 3764 3765 bool X86TTIImpl::enableInterleavedAccessVectorization() { 3766 // TODO: We expect this to be beneficial regardless of arch, 3767 // but there are currently some unexplained performance artifacts on Atom. 3768 // As a temporary solution, disable on Atom. 3769 return !(ST->isAtom()); 3770 } 3771 3772 // Get estimation for interleaved load/store operations for AVX2. 3773 // \p Factor is the interleaved-access factor (stride) - number of 3774 // (interleaved) elements in the group. 3775 // \p Indices contains the indices for a strided load: when the 3776 // interleaved load has gaps they indicate which elements are used. 3777 // If Indices is empty (or if the number of indices is equal to the size 3778 // of the interleaved-access as given in \p Factor) the access has no gaps. 3779 // 3780 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 3781 // computing the cost using a generic formula as a function of generic 3782 // shuffles. We therefore use a lookup table instead, filled according to 3783 // the instruction sequences that codegen currently generates. 3784 int X86TTIImpl::getInterleavedMemoryOpCostAVX2(unsigned Opcode, Type *VecTy, 3785 unsigned Factor, 3786 ArrayRef<unsigned> Indices, 3787 unsigned Alignment, 3788 unsigned AddressSpace, 3789 bool UseMaskForCond, 3790 bool UseMaskForGaps) { 3791 3792 if (UseMaskForCond || UseMaskForGaps) 3793 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3794 Alignment, AddressSpace, 3795 UseMaskForCond, UseMaskForGaps); 3796 3797 // We currently Support only fully-interleaved groups, with no gaps. 3798 // TODO: Support also strided loads (interleaved-groups with gaps). 3799 if (Indices.size() && Indices.size() != Factor) 3800 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3801 Alignment, AddressSpace); 3802 3803 // VecTy for interleave memop is <VF*Factor x Elt>. 3804 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 3805 // VecTy = <12 x i32>. 3806 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 3807 3808 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 3809 // the VF=2, while v2i128 is an unsupported MVT vector type 3810 // (see MachineValueType.h::getVectorVT()). 3811 if (!LegalVT.isVector()) 3812 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3813 Alignment, AddressSpace); 3814 3815 unsigned VF = VecTy->getVectorNumElements() / Factor; 3816 Type *ScalarTy = VecTy->getVectorElementType(); 3817 3818 // Calculate the number of memory operations (NumOfMemOps), required 3819 // for load/store the VecTy. 3820 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 3821 unsigned LegalVTSize = LegalVT.getStoreSize(); 3822 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 3823 3824 // Get the cost of one memory operation. 3825 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(), 3826 LegalVT.getVectorNumElements()); 3827 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 3828 MaybeAlign(Alignment), AddressSpace); 3829 3830 VectorType *VT = VectorType::get(ScalarTy, VF); 3831 EVT ETy = TLI->getValueType(DL, VT); 3832 if (!ETy.isSimple()) 3833 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3834 Alignment, AddressSpace); 3835 3836 // TODO: Complete for other data-types and strides. 3837 // Each combination of Stride, ElementTy and VF results in a different 3838 // sequence; The cost tables are therefore accessed with: 3839 // Factor (stride) and VectorType=VFxElemType. 3840 // The Cost accounts only for the shuffle sequence; 3841 // The cost of the loads/stores is accounted for separately. 3842 // 3843 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 3844 { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64 3845 { 2, MVT::v4f64, 6 }, //(load 8f64 and) deinterleave into 2 x 4f64 3846 3847 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8 3848 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8 3849 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8 3850 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8 3851 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8 3852 { 3, MVT::v8f32, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32 3853 3854 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8 3855 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8 3856 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8 3857 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8 3858 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8 3859 3860 { 8, MVT::v8f32, 40 } //(load 64f32 and)deinterleave into 8 x 8f32 3861 }; 3862 3863 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 3864 { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store) 3865 { 2, MVT::v4f64, 6 }, //interleave into 2 x 4f64 into 8f64 (and store) 3866 3867 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store) 3868 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store) 3869 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store) 3870 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store) 3871 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store) 3872 3873 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store) 3874 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store) 3875 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store) 3876 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store) 3877 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store) 3878 }; 3879 3880 if (Opcode == Instruction::Load) { 3881 if (const auto *Entry = 3882 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 3883 return NumOfMemOps * MemOpCost + Entry->Cost; 3884 } else { 3885 assert(Opcode == Instruction::Store && 3886 "Expected Store Instruction at this point"); 3887 if (const auto *Entry = 3888 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 3889 return NumOfMemOps * MemOpCost + Entry->Cost; 3890 } 3891 3892 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3893 Alignment, AddressSpace); 3894 } 3895 3896 // Get estimation for interleaved load/store operations and strided load. 3897 // \p Indices contains indices for strided load. 3898 // \p Factor - the factor of interleaving. 3899 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 3900 int X86TTIImpl::getInterleavedMemoryOpCostAVX512(unsigned Opcode, Type *VecTy, 3901 unsigned Factor, 3902 ArrayRef<unsigned> Indices, 3903 unsigned Alignment, 3904 unsigned AddressSpace, 3905 bool UseMaskForCond, 3906 bool UseMaskForGaps) { 3907 3908 if (UseMaskForCond || UseMaskForGaps) 3909 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3910 Alignment, AddressSpace, 3911 UseMaskForCond, UseMaskForGaps); 3912 3913 // VecTy for interleave memop is <VF*Factor x Elt>. 3914 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 3915 // VecTy = <12 x i32>. 3916 3917 // Calculate the number of memory operations (NumOfMemOps), required 3918 // for load/store the VecTy. 3919 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 3920 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 3921 unsigned LegalVTSize = LegalVT.getStoreSize(); 3922 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 3923 3924 // Get the cost of one memory operation. 3925 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(), 3926 LegalVT.getVectorNumElements()); 3927 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 3928 MaybeAlign(Alignment), AddressSpace); 3929 3930 unsigned VF = VecTy->getVectorNumElements() / Factor; 3931 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 3932 3933 if (Opcode == Instruction::Load) { 3934 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 3935 // contain the cost of the optimized shuffle sequence that the 3936 // X86InterleavedAccess pass will generate. 3937 // The cost of loads and stores are computed separately from the table. 3938 3939 // X86InterleavedAccess support only the following interleaved-access group. 3940 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 3941 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 3942 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 3943 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 3944 }; 3945 3946 if (const auto *Entry = 3947 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 3948 return NumOfMemOps * MemOpCost + Entry->Cost; 3949 //If an entry does not exist, fallback to the default implementation. 3950 3951 // Kind of shuffle depends on number of loaded values. 3952 // If we load the entire data in one register, we can use a 1-src shuffle. 3953 // Otherwise, we'll merge 2 sources in each operation. 3954 TTI::ShuffleKind ShuffleKind = 3955 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 3956 3957 unsigned ShuffleCost = 3958 getShuffleCost(ShuffleKind, SingleMemOpTy, 0, nullptr); 3959 3960 unsigned NumOfLoadsInInterleaveGrp = 3961 Indices.size() ? Indices.size() : Factor; 3962 Type *ResultTy = VectorType::get(VecTy->getVectorElementType(), 3963 VecTy->getVectorNumElements() / Factor); 3964 unsigned NumOfResults = 3965 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 3966 NumOfLoadsInInterleaveGrp; 3967 3968 // About a half of the loads may be folded in shuffles when we have only 3969 // one result. If we have more than one result, we do not fold loads at all. 3970 unsigned NumOfUnfoldedLoads = 3971 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 3972 3973 // Get a number of shuffle operations per result. 3974 unsigned NumOfShufflesPerResult = 3975 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 3976 3977 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 3978 // When we have more than one destination, we need additional instructions 3979 // to keep sources. 3980 unsigned NumOfMoves = 0; 3981 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 3982 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 3983 3984 int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 3985 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 3986 3987 return Cost; 3988 } 3989 3990 // Store. 3991 assert(Opcode == Instruction::Store && 3992 "Expected Store Instruction at this point"); 3993 // X86InterleavedAccess support only the following interleaved-access group. 3994 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 3995 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 3996 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 3997 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 3998 3999 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 4000 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 4001 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 4002 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 4003 }; 4004 4005 if (const auto *Entry = 4006 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 4007 return NumOfMemOps * MemOpCost + Entry->Cost; 4008 //If an entry does not exist, fallback to the default implementation. 4009 4010 // There is no strided stores meanwhile. And store can't be folded in 4011 // shuffle. 4012 unsigned NumOfSources = Factor; // The number of values to be merged. 4013 unsigned ShuffleCost = 4014 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, 0, nullptr); 4015 unsigned NumOfShufflesPerStore = NumOfSources - 1; 4016 4017 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4018 // We need additional instructions to keep sources. 4019 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 4020 int Cost = NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 4021 NumOfMoves; 4022 return Cost; 4023 } 4024 4025 int X86TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, 4026 unsigned Factor, 4027 ArrayRef<unsigned> Indices, 4028 unsigned Alignment, 4029 unsigned AddressSpace, 4030 bool UseMaskForCond, 4031 bool UseMaskForGaps) { 4032 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 4033 Type *EltTy = VecTy->getVectorElementType(); 4034 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 4035 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 4036 return true; 4037 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 4038 return HasBW; 4039 return false; 4040 }; 4041 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 4042 return getInterleavedMemoryOpCostAVX512(Opcode, VecTy, Factor, Indices, 4043 Alignment, AddressSpace, 4044 UseMaskForCond, UseMaskForGaps); 4045 if (ST->hasAVX2()) 4046 return getInterleavedMemoryOpCostAVX2(Opcode, VecTy, Factor, Indices, 4047 Alignment, AddressSpace, 4048 UseMaskForCond, UseMaskForGaps); 4049 4050 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4051 Alignment, AddressSpace, 4052 UseMaskForCond, UseMaskForGaps); 4053 } 4054