1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // X86 cost model. 56 // 57 //===----------------------------------------------------------------------===// 58 59 TargetTransformInfo::PopcntSupportKind 60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 61 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 62 // TODO: Currently the __builtin_popcount() implementation using SSE3 63 // instructions is inefficient. Once the problem is fixed, we should 64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 66 } 67 68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 69 TargetTransformInfo::CacheLevel Level) const { 70 switch (Level) { 71 case TargetTransformInfo::CacheLevel::L1D: 72 // - Penryn 73 // - Nehalem 74 // - Westmere 75 // - Sandy Bridge 76 // - Ivy Bridge 77 // - Haswell 78 // - Broadwell 79 // - Skylake 80 // - Kabylake 81 return 32 * 1024; // 32 KByte 82 case TargetTransformInfo::CacheLevel::L2D: 83 // - Penryn 84 // - Nehalem 85 // - Westmere 86 // - Sandy Bridge 87 // - Ivy Bridge 88 // - Haswell 89 // - Broadwell 90 // - Skylake 91 // - Kabylake 92 return 256 * 1024; // 256 KByte 93 } 94 95 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 96 } 97 98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 99 TargetTransformInfo::CacheLevel Level) const { 100 // - Penryn 101 // - Nehalem 102 // - Westmere 103 // - Sandy Bridge 104 // - Ivy Bridge 105 // - Haswell 106 // - Broadwell 107 // - Skylake 108 // - Kabylake 109 switch (Level) { 110 case TargetTransformInfo::CacheLevel::L1D: 111 LLVM_FALLTHROUGH; 112 case TargetTransformInfo::CacheLevel::L2D: 113 return 8; 114 } 115 116 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 117 } 118 119 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 120 bool Vector = (ClassID == 1); 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 TypeSize 133 X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { 134 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 135 switch (K) { 136 case TargetTransformInfo::RGK_Scalar: 137 return TypeSize::getFixed(ST->is64Bit() ? 64 : 32); 138 case TargetTransformInfo::RGK_FixedWidthVector: 139 if (ST->hasAVX512() && PreferVectorWidth >= 512) 140 return TypeSize::getFixed(512); 141 if (ST->hasAVX() && PreferVectorWidth >= 256) 142 return TypeSize::getFixed(256); 143 if (ST->hasSSE1() && PreferVectorWidth >= 128) 144 return TypeSize::getFixed(128); 145 return TypeSize::getFixed(0); 146 case TargetTransformInfo::RGK_ScalableVector: 147 return TypeSize::getScalable(0); 148 } 149 150 llvm_unreachable("Unsupported register kind"); 151 } 152 153 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 154 return getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector) 155 .getFixedSize(); 156 } 157 158 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 159 // If the loop will not be vectorized, don't interleave the loop. 160 // Let regular unroll to unroll the loop, which saves the overflow 161 // check and memory check cost. 162 if (VF == 1) 163 return 1; 164 165 if (ST->isAtom()) 166 return 1; 167 168 // Sandybridge and Haswell have multiple execution ports and pipelined 169 // vector units. 170 if (ST->hasAVX()) 171 return 4; 172 173 return 2; 174 } 175 176 InstructionCost X86TTIImpl::getArithmeticInstrCost( 177 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, 178 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 179 TTI::OperandValueProperties Opd1PropInfo, 180 TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, 181 const Instruction *CxtI) { 182 // TODO: Handle more cost kinds. 183 if (CostKind != TTI::TCK_RecipThroughput) 184 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, 185 Op2Info, Opd1PropInfo, 186 Opd2PropInfo, Args, CxtI); 187 188 // vXi8 multiplications are always promoted to vXi16. 189 if (Opcode == Instruction::Mul && Ty->isVectorTy() && 190 Ty->getScalarSizeInBits() == 8) { 191 Type *WideVecTy = 192 VectorType::getExtendedElementVectorType(cast<VectorType>(Ty)); 193 return getCastInstrCost(Instruction::ZExt, WideVecTy, Ty, 194 TargetTransformInfo::CastContextHint::None, 195 CostKind) + 196 getCastInstrCost(Instruction::Trunc, Ty, WideVecTy, 197 TargetTransformInfo::CastContextHint::None, 198 CostKind) + 199 getArithmeticInstrCost(Opcode, WideVecTy, CostKind, Op1Info, Op2Info, 200 Opd1PropInfo, Opd2PropInfo); 201 } 202 203 // Legalize the type. 204 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 205 206 int ISD = TLI->InstructionOpcodeToISD(Opcode); 207 assert(ISD && "Invalid opcode"); 208 209 if (ISD == ISD::MUL && Args.size() == 2 && LT.second.isVector() && 210 LT.second.getScalarType() == MVT::i32) { 211 // Check if the operands can be represented as a smaller datatype. 212 bool Op1Signed = false, Op2Signed = false; 213 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 214 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 215 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 216 217 // If both are representable as i15 and at least one is constant, 218 // zero-extended, or sign-extended from vXi16 (or less pre-SSE41) then we 219 // can treat this as PMADDWD which has the same costs as a vXi16 multiply. 220 if (OpMinSize <= 15 && !ST->isPMADDWDSlow()) { 221 bool Op1Constant = 222 isa<ConstantDataVector>(Args[0]) || isa<ConstantVector>(Args[0]); 223 bool Op2Constant = 224 isa<ConstantDataVector>(Args[1]) || isa<ConstantVector>(Args[1]); 225 bool Op1Sext = isa<SExtInst>(Args[0]) && 226 (Op1MinSize == 15 || (Op1MinSize < 15 && !ST->hasSSE41())); 227 bool Op2Sext = isa<SExtInst>(Args[1]) && 228 (Op2MinSize == 15 || (Op2MinSize < 15 && !ST->hasSSE41())); 229 230 bool IsZeroExtended = !Op1Signed || !Op2Signed; 231 bool IsConstant = Op1Constant || Op2Constant; 232 bool IsSext = Op1Sext || Op2Sext; 233 if (IsConstant || IsZeroExtended || IsSext) 234 LT.second = 235 MVT::getVectorVT(MVT::i16, 2 * LT.second.getVectorNumElements()); 236 } 237 } 238 239 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 240 ISD == ISD::UREM) && 241 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 242 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 243 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 244 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 245 // On X86, vector signed division by constants power-of-two are 246 // normally expanded to the sequence SRA + SRL + ADD + SRA. 247 // The OperandValue properties may not be the same as that of the previous 248 // operation; conservatively assume OP_None. 249 InstructionCost Cost = 250 2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Op1Info, 251 Op2Info, TargetTransformInfo::OP_None, 252 TargetTransformInfo::OP_None); 253 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 254 Op2Info, TargetTransformInfo::OP_None, 255 TargetTransformInfo::OP_None); 256 Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind, Op1Info, 257 Op2Info, TargetTransformInfo::OP_None, 258 TargetTransformInfo::OP_None); 259 260 if (ISD == ISD::SREM) { 261 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 262 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info, 263 Op2Info); 264 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info, 265 Op2Info); 266 } 267 268 return Cost; 269 } 270 271 // Vector unsigned division/remainder will be simplified to shifts/masks. 272 if (ISD == ISD::UDIV) 273 return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 274 Op2Info, TargetTransformInfo::OP_None, 275 TargetTransformInfo::OP_None); 276 // UREM 277 return getArithmeticInstrCost(Instruction::And, Ty, CostKind, Op1Info, 278 Op2Info, TargetTransformInfo::OP_None, 279 TargetTransformInfo::OP_None); 280 } 281 282 static const CostTblEntry GLMCostTable[] = { 283 { ISD::FDIV, MVT::f32, 18 }, // divss 284 { ISD::FDIV, MVT::v4f32, 35 }, // divps 285 { ISD::FDIV, MVT::f64, 33 }, // divsd 286 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 287 }; 288 289 if (ST->useGLMDivSqrtCosts()) 290 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 291 LT.second)) 292 return LT.first * Entry->Cost; 293 294 static const CostTblEntry SLMCostTable[] = { 295 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 296 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 297 { ISD::FMUL, MVT::f64, 2 }, // mulsd 298 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 299 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 300 { ISD::FDIV, MVT::f32, 17 }, // divss 301 { ISD::FDIV, MVT::v4f32, 39 }, // divps 302 { ISD::FDIV, MVT::f64, 32 }, // divsd 303 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 304 { ISD::FADD, MVT::v2f64, 2 }, // addpd 305 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 306 // v2i64/v4i64 mul is custom lowered as a series of long: 307 // multiplies(3), shifts(3) and adds(2) 308 // slm muldq version throughput is 2 and addq throughput 4 309 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 310 // 3X4 (addq throughput) = 17 311 { ISD::MUL, MVT::v2i64, 17 }, 312 // slm addq\subq throughput is 4 313 { ISD::ADD, MVT::v2i64, 4 }, 314 { ISD::SUB, MVT::v2i64, 4 }, 315 }; 316 317 if (ST->isSLM()) { 318 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 319 // Check if the operands can be shrinked into a smaller datatype. 320 // TODO: Merge this into generiic vXi32 MUL patterns above. 321 bool Op1Signed = false; 322 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 323 bool Op2Signed = false; 324 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 325 326 bool SignedMode = Op1Signed || Op2Signed; 327 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 328 329 if (OpMinSize <= 7) 330 return LT.first * 3; // pmullw/sext 331 if (!SignedMode && OpMinSize <= 8) 332 return LT.first * 3; // pmullw/zext 333 if (OpMinSize <= 15) 334 return LT.first * 5; // pmullw/pmulhw/pshuf 335 if (!SignedMode && OpMinSize <= 16) 336 return LT.first * 5; // pmullw/pmulhw/pshuf 337 } 338 339 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 340 LT.second)) { 341 return LT.first * Entry->Cost; 342 } 343 } 344 345 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 346 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 347 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 348 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 349 }; 350 351 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 352 ST->hasBWI()) { 353 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 354 LT.second)) 355 return LT.first * Entry->Cost; 356 } 357 358 static const CostTblEntry AVX512UniformConstCostTable[] = { 359 { ISD::SRA, MVT::v2i64, 1 }, 360 { ISD::SRA, MVT::v4i64, 1 }, 361 { ISD::SRA, MVT::v8i64, 1 }, 362 363 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 364 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 365 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 366 367 { ISD::SDIV, MVT::v16i32, 6 }, // pmuludq sequence 368 { ISD::SREM, MVT::v16i32, 8 }, // pmuludq+mul+sub sequence 369 { ISD::UDIV, MVT::v16i32, 5 }, // pmuludq sequence 370 { ISD::UREM, MVT::v16i32, 7 }, // pmuludq+mul+sub sequence 371 }; 372 373 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 374 ST->hasAVX512()) { 375 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 376 LT.second)) 377 return LT.first * Entry->Cost; 378 } 379 380 static const CostTblEntry AVX2UniformConstCostTable[] = { 381 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 382 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 383 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 384 385 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 386 387 { ISD::SDIV, MVT::v8i32, 6 }, // pmuludq sequence 388 { ISD::SREM, MVT::v8i32, 8 }, // pmuludq+mul+sub sequence 389 { ISD::UDIV, MVT::v8i32, 5 }, // pmuludq sequence 390 { ISD::UREM, MVT::v8i32, 7 }, // pmuludq+mul+sub sequence 391 }; 392 393 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 394 ST->hasAVX2()) { 395 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 396 LT.second)) 397 return LT.first * Entry->Cost; 398 } 399 400 static const CostTblEntry SSE2UniformConstCostTable[] = { 401 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 402 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 403 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 404 405 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 406 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 407 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 408 409 { ISD::SDIV, MVT::v8i32, 12+2 }, // 2*pmuludq sequence + split. 410 { ISD::SREM, MVT::v8i32, 16+2 }, // 2*pmuludq+mul+sub sequence + split. 411 { ISD::SDIV, MVT::v4i32, 6 }, // pmuludq sequence 412 { ISD::SREM, MVT::v4i32, 8 }, // pmuludq+mul+sub sequence 413 { ISD::UDIV, MVT::v8i32, 10+2 }, // 2*pmuludq sequence + split. 414 { ISD::UREM, MVT::v8i32, 14+2 }, // 2*pmuludq+mul+sub sequence + split. 415 { ISD::UDIV, MVT::v4i32, 5 }, // pmuludq sequence 416 { ISD::UREM, MVT::v4i32, 7 }, // pmuludq+mul+sub sequence 417 }; 418 419 // XOP has faster vXi8 shifts. 420 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 421 ST->hasSSE2() && !ST->hasXOP()) { 422 if (const auto *Entry = 423 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 424 return LT.first * Entry->Cost; 425 } 426 427 static const CostTblEntry AVX512BWConstCostTable[] = { 428 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 429 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 430 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 431 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 432 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 433 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 434 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 435 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 436 }; 437 438 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 439 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 440 ST->hasBWI()) { 441 if (const auto *Entry = 442 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 443 return LT.first * Entry->Cost; 444 } 445 446 static const CostTblEntry AVX512ConstCostTable[] = { 447 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 448 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 449 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 450 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 451 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 452 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 453 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 454 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 455 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 456 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 457 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 458 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 459 }; 460 461 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 462 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 463 ST->hasAVX512()) { 464 if (const auto *Entry = 465 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 466 return LT.first * Entry->Cost; 467 } 468 469 static const CostTblEntry AVX2ConstCostTable[] = { 470 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 471 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 472 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 473 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 474 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 475 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 476 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 477 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 478 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 479 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 480 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 481 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 482 }; 483 484 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 485 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 486 ST->hasAVX2()) { 487 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 488 return LT.first * Entry->Cost; 489 } 490 491 static const CostTblEntry SSE2ConstCostTable[] = { 492 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 493 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 494 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 495 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 496 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 497 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 498 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 499 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 500 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 501 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 502 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 503 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 504 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 505 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 506 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 507 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 508 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 509 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 510 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 511 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 512 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 513 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 514 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 515 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 516 }; 517 518 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 519 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 520 ST->hasSSE2()) { 521 // pmuldq sequence. 522 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 523 return LT.first * 32; 524 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 525 return LT.first * 38; 526 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 527 return LT.first * 15; 528 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 529 return LT.first * 20; 530 531 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 532 return LT.first * Entry->Cost; 533 } 534 535 static const CostTblEntry AVX512BWShiftCostTable[] = { 536 { ISD::SHL, MVT::v16i8, 4 }, // extend/vpsllvw/pack sequence. 537 { ISD::SRL, MVT::v16i8, 4 }, // extend/vpsrlvw/pack sequence. 538 { ISD::SRA, MVT::v16i8, 4 }, // extend/vpsravw/pack sequence. 539 { ISD::SHL, MVT::v32i8, 4 }, // extend/vpsllvw/pack sequence. 540 { ISD::SRL, MVT::v32i8, 4 }, // extend/vpsrlvw/pack sequence. 541 { ISD::SRA, MVT::v32i8, 6 }, // extend/vpsravw/pack sequence. 542 { ISD::SHL, MVT::v64i8, 6 }, // extend/vpsllvw/pack sequence. 543 { ISD::SRL, MVT::v64i8, 7 }, // extend/vpsrlvw/pack sequence. 544 { ISD::SRA, MVT::v64i8, 15 }, // extend/vpsravw/pack sequence. 545 546 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 547 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 548 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 549 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 550 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 551 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 552 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 553 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 554 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 555 }; 556 557 if (ST->hasBWI()) 558 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 559 return LT.first * Entry->Cost; 560 561 static const CostTblEntry AVX2UniformCostTable[] = { 562 // Uniform splats are cheaper for the following instructions. 563 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 564 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 565 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 566 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 567 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 568 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 569 570 { ISD::SHL, MVT::v8i32, 1 }, // pslld 571 { ISD::SRL, MVT::v8i32, 1 }, // psrld 572 { ISD::SRA, MVT::v8i32, 1 }, // psrad 573 { ISD::SHL, MVT::v4i64, 1 }, // psllq 574 { ISD::SRL, MVT::v4i64, 1 }, // psrlq 575 }; 576 577 if (ST->hasAVX2() && 578 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 579 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 580 if (const auto *Entry = 581 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 582 return LT.first * Entry->Cost; 583 } 584 585 static const CostTblEntry SSE2UniformCostTable[] = { 586 // Uniform splats are cheaper for the following instructions. 587 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 588 { ISD::SHL, MVT::v4i32, 1 }, // pslld 589 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 590 591 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 592 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 593 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 594 595 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 596 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 597 }; 598 599 if (ST->hasSSE2() && 600 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 601 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 602 if (const auto *Entry = 603 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 604 return LT.first * Entry->Cost; 605 } 606 607 static const CostTblEntry AVX512DQCostTable[] = { 608 { ISD::MUL, MVT::v2i64, 2 }, // pmullq 609 { ISD::MUL, MVT::v4i64, 2 }, // pmullq 610 { ISD::MUL, MVT::v8i64, 2 } // pmullq 611 }; 612 613 // Look for AVX512DQ lowering tricks for custom cases. 614 if (ST->hasDQI()) 615 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 616 return LT.first * Entry->Cost; 617 618 static const CostTblEntry AVX512BWCostTable[] = { 619 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 620 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 621 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 622 }; 623 624 // Look for AVX512BW lowering tricks for custom cases. 625 if (ST->hasBWI()) 626 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 627 return LT.first * Entry->Cost; 628 629 static const CostTblEntry AVX512CostTable[] = { 630 { ISD::SHL, MVT::v4i32, 1 }, 631 { ISD::SRL, MVT::v4i32, 1 }, 632 { ISD::SRA, MVT::v4i32, 1 }, 633 { ISD::SHL, MVT::v8i32, 1 }, 634 { ISD::SRL, MVT::v8i32, 1 }, 635 { ISD::SRA, MVT::v8i32, 1 }, 636 { ISD::SHL, MVT::v16i32, 1 }, 637 { ISD::SRL, MVT::v16i32, 1 }, 638 { ISD::SRA, MVT::v16i32, 1 }, 639 640 { ISD::SHL, MVT::v2i64, 1 }, 641 { ISD::SRL, MVT::v2i64, 1 }, 642 { ISD::SHL, MVT::v4i64, 1 }, 643 { ISD::SRL, MVT::v4i64, 1 }, 644 { ISD::SHL, MVT::v8i64, 1 }, 645 { ISD::SRL, MVT::v8i64, 1 }, 646 647 { ISD::SRA, MVT::v2i64, 1 }, 648 { ISD::SRA, MVT::v4i64, 1 }, 649 { ISD::SRA, MVT::v8i64, 1 }, 650 651 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 652 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 653 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 654 { ISD::MUL, MVT::v8i64, 6 }, // 3*pmuludq/3*shift/2*add 655 656 { ISD::FNEG, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 657 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 658 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 659 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 660 { ISD::FDIV, MVT::f64, 4 }, // Skylake from http://www.agner.org/ 661 { ISD::FDIV, MVT::v2f64, 4 }, // Skylake from http://www.agner.org/ 662 { ISD::FDIV, MVT::v4f64, 8 }, // Skylake from http://www.agner.org/ 663 { ISD::FDIV, MVT::v8f64, 16 }, // Skylake from http://www.agner.org/ 664 665 { ISD::FNEG, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 666 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 667 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 668 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 669 { ISD::FDIV, MVT::f32, 3 }, // Skylake from http://www.agner.org/ 670 { ISD::FDIV, MVT::v4f32, 3 }, // Skylake from http://www.agner.org/ 671 { ISD::FDIV, MVT::v8f32, 5 }, // Skylake from http://www.agner.org/ 672 { ISD::FDIV, MVT::v16f32, 10 }, // Skylake from http://www.agner.org/ 673 }; 674 675 if (ST->hasAVX512()) 676 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 677 return LT.first * Entry->Cost; 678 679 static const CostTblEntry AVX2ShiftCostTable[] = { 680 // Shifts on vXi64/vXi32 on AVX2 is legal even though we declare to 681 // customize them to detect the cases where shift amount is a scalar one. 682 { ISD::SHL, MVT::v4i32, 2 }, // vpsllvd (Haswell from agner.org) 683 { ISD::SRL, MVT::v4i32, 2 }, // vpsrlvd (Haswell from agner.org) 684 { ISD::SRA, MVT::v4i32, 2 }, // vpsravd (Haswell from agner.org) 685 { ISD::SHL, MVT::v8i32, 2 }, // vpsllvd (Haswell from agner.org) 686 { ISD::SRL, MVT::v8i32, 2 }, // vpsrlvd (Haswell from agner.org) 687 { ISD::SRA, MVT::v8i32, 2 }, // vpsravd (Haswell from agner.org) 688 { ISD::SHL, MVT::v2i64, 1 }, // vpsllvq (Haswell from agner.org) 689 { ISD::SRL, MVT::v2i64, 1 }, // vpsrlvq (Haswell from agner.org) 690 { ISD::SHL, MVT::v4i64, 1 }, // vpsllvq (Haswell from agner.org) 691 { ISD::SRL, MVT::v4i64, 1 }, // vpsrlvq (Haswell from agner.org) 692 }; 693 694 if (ST->hasAVX512()) { 695 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 696 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 697 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 698 // On AVX512, a packed v32i16 shift left by a constant build_vector 699 // is lowered into a vector multiply (vpmullw). 700 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 701 Op1Info, Op2Info, 702 TargetTransformInfo::OP_None, 703 TargetTransformInfo::OP_None); 704 } 705 706 // Look for AVX2 lowering tricks (XOP is always better at v4i32 shifts). 707 if (ST->hasAVX2() && !(ST->hasXOP() && LT.second == MVT::v4i32)) { 708 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 709 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 710 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 711 // On AVX2, a packed v16i16 shift left by a constant build_vector 712 // is lowered into a vector multiply (vpmullw). 713 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 714 Op1Info, Op2Info, 715 TargetTransformInfo::OP_None, 716 TargetTransformInfo::OP_None); 717 718 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 719 return LT.first * Entry->Cost; 720 } 721 722 static const CostTblEntry XOPShiftCostTable[] = { 723 // 128bit shifts take 1cy, but right shifts require negation beforehand. 724 { ISD::SHL, MVT::v16i8, 1 }, 725 { ISD::SRL, MVT::v16i8, 2 }, 726 { ISD::SRA, MVT::v16i8, 2 }, 727 { ISD::SHL, MVT::v8i16, 1 }, 728 { ISD::SRL, MVT::v8i16, 2 }, 729 { ISD::SRA, MVT::v8i16, 2 }, 730 { ISD::SHL, MVT::v4i32, 1 }, 731 { ISD::SRL, MVT::v4i32, 2 }, 732 { ISD::SRA, MVT::v4i32, 2 }, 733 { ISD::SHL, MVT::v2i64, 1 }, 734 { ISD::SRL, MVT::v2i64, 2 }, 735 { ISD::SRA, MVT::v2i64, 2 }, 736 // 256bit shifts require splitting if AVX2 didn't catch them above. 737 { ISD::SHL, MVT::v32i8, 2+2 }, 738 { ISD::SRL, MVT::v32i8, 4+2 }, 739 { ISD::SRA, MVT::v32i8, 4+2 }, 740 { ISD::SHL, MVT::v16i16, 2+2 }, 741 { ISD::SRL, MVT::v16i16, 4+2 }, 742 { ISD::SRA, MVT::v16i16, 4+2 }, 743 { ISD::SHL, MVT::v8i32, 2+2 }, 744 { ISD::SRL, MVT::v8i32, 4+2 }, 745 { ISD::SRA, MVT::v8i32, 4+2 }, 746 { ISD::SHL, MVT::v4i64, 2+2 }, 747 { ISD::SRL, MVT::v4i64, 4+2 }, 748 { ISD::SRA, MVT::v4i64, 4+2 }, 749 }; 750 751 // Look for XOP lowering tricks. 752 if (ST->hasXOP()) { 753 // If the right shift is constant then we'll fold the negation so 754 // it's as cheap as a left shift. 755 int ShiftISD = ISD; 756 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 757 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 758 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 759 ShiftISD = ISD::SHL; 760 if (const auto *Entry = 761 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 762 return LT.first * Entry->Cost; 763 } 764 765 static const CostTblEntry SSE2UniformShiftCostTable[] = { 766 // Uniform splats are cheaper for the following instructions. 767 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 768 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 769 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 770 771 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 772 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 773 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 774 775 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 776 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 777 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 778 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 779 }; 780 781 if (ST->hasSSE2() && 782 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 783 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 784 785 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 786 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 787 return LT.first * 4; // 2*psrad + shuffle. 788 789 if (const auto *Entry = 790 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 791 return LT.first * Entry->Cost; 792 } 793 794 if (ISD == ISD::SHL && 795 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 796 MVT VT = LT.second; 797 // Vector shift left by non uniform constant can be lowered 798 // into vector multiply. 799 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 800 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 801 ISD = ISD::MUL; 802 } 803 804 static const CostTblEntry AVX2CostTable[] = { 805 { ISD::SHL, MVT::v16i8, 6 }, // vpblendvb sequence. 806 { ISD::SHL, MVT::v32i8, 6 }, // vpblendvb sequence. 807 { ISD::SHL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 808 { ISD::SHL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 809 { ISD::SHL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 810 { ISD::SHL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 811 812 { ISD::SRL, MVT::v16i8, 6 }, // vpblendvb sequence. 813 { ISD::SRL, MVT::v32i8, 6 }, // vpblendvb sequence. 814 { ISD::SRL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 815 { ISD::SRL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 816 { ISD::SRL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 817 { ISD::SRL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 818 819 { ISD::SRA, MVT::v16i8, 17 }, // vpblendvb sequence. 820 { ISD::SRA, MVT::v32i8, 17 }, // vpblendvb sequence. 821 { ISD::SRA, MVT::v64i8, 34 }, // 2*vpblendvb sequence. 822 { ISD::SRA, MVT::v8i16, 5 }, // extend/vpsravd/pack sequence. 823 { ISD::SRA, MVT::v16i16, 7 }, // extend/vpsravd/pack sequence. 824 { ISD::SRA, MVT::v32i16, 14 }, // 2*extend/vpsravd/pack sequence. 825 { ISD::SRA, MVT::v2i64, 2 }, // srl/xor/sub sequence. 826 { ISD::SRA, MVT::v4i64, 2 }, // srl/xor/sub sequence. 827 828 { ISD::SUB, MVT::v32i8, 1 }, // psubb 829 { ISD::ADD, MVT::v32i8, 1 }, // paddb 830 { ISD::SUB, MVT::v16i16, 1 }, // psubw 831 { ISD::ADD, MVT::v16i16, 1 }, // paddw 832 { ISD::SUB, MVT::v8i32, 1 }, // psubd 833 { ISD::ADD, MVT::v8i32, 1 }, // paddd 834 { ISD::SUB, MVT::v4i64, 1 }, // psubq 835 { ISD::ADD, MVT::v4i64, 1 }, // paddq 836 837 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 838 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 839 { ISD::MUL, MVT::v4i64, 6 }, // 3*pmuludq/3*shift/2*add 840 841 { ISD::FNEG, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 842 { ISD::FNEG, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 843 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 844 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 845 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 846 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 847 { ISD::FMUL, MVT::f64, 1 }, // Haswell from http://www.agner.org/ 848 { ISD::FMUL, MVT::v2f64, 1 }, // Haswell from http://www.agner.org/ 849 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 850 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 851 852 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 853 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 854 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 855 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 856 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 857 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 858 }; 859 860 // Look for AVX2 lowering tricks for custom cases. 861 if (ST->hasAVX2()) 862 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 863 return LT.first * Entry->Cost; 864 865 static const CostTblEntry AVX1CostTable[] = { 866 // We don't have to scalarize unsupported ops. We can issue two half-sized 867 // operations and we only need to extract the upper YMM half. 868 // Two ops + 1 extract + 1 insert = 4. 869 { ISD::MUL, MVT::v16i16, 4 }, 870 { ISD::MUL, MVT::v8i32, 5 }, // BTVER2 from http://www.agner.org/ 871 { ISD::MUL, MVT::v4i64, 12 }, 872 873 { ISD::SUB, MVT::v32i8, 4 }, 874 { ISD::ADD, MVT::v32i8, 4 }, 875 { ISD::SUB, MVT::v16i16, 4 }, 876 { ISD::ADD, MVT::v16i16, 4 }, 877 { ISD::SUB, MVT::v8i32, 4 }, 878 { ISD::ADD, MVT::v8i32, 4 }, 879 { ISD::SUB, MVT::v4i64, 4 }, 880 { ISD::ADD, MVT::v4i64, 4 }, 881 882 { ISD::SHL, MVT::v32i8, 22 }, // pblendvb sequence + split. 883 { ISD::SHL, MVT::v8i16, 6 }, // pblendvb sequence. 884 { ISD::SHL, MVT::v16i16, 13 }, // pblendvb sequence + split. 885 { ISD::SHL, MVT::v4i32, 3 }, // pslld/paddd/cvttps2dq/pmulld 886 { ISD::SHL, MVT::v8i32, 9 }, // pslld/paddd/cvttps2dq/pmulld + split 887 { ISD::SHL, MVT::v2i64, 2 }, // Shift each lane + blend. 888 { ISD::SHL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 889 890 { ISD::SRL, MVT::v32i8, 23 }, // pblendvb sequence + split. 891 { ISD::SRL, MVT::v16i16, 28 }, // pblendvb sequence + split. 892 { ISD::SRL, MVT::v4i32, 6 }, // Shift each lane + blend. 893 { ISD::SRL, MVT::v8i32, 14 }, // Shift each lane + blend + split. 894 { ISD::SRL, MVT::v2i64, 2 }, // Shift each lane + blend. 895 { ISD::SRL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 896 897 { ISD::SRA, MVT::v32i8, 44 }, // pblendvb sequence + split. 898 { ISD::SRA, MVT::v16i16, 28 }, // pblendvb sequence + split. 899 { ISD::SRA, MVT::v4i32, 6 }, // Shift each lane + blend. 900 { ISD::SRA, MVT::v8i32, 14 }, // Shift each lane + blend + split. 901 { ISD::SRA, MVT::v2i64, 5 }, // Shift each lane + blend. 902 { ISD::SRA, MVT::v4i64, 12 }, // Shift each lane + blend + split. 903 904 { ISD::FNEG, MVT::v4f64, 2 }, // BTVER2 from http://www.agner.org/ 905 { ISD::FNEG, MVT::v8f32, 2 }, // BTVER2 from http://www.agner.org/ 906 907 { ISD::FMUL, MVT::f64, 2 }, // BTVER2 from http://www.agner.org/ 908 { ISD::FMUL, MVT::v2f64, 2 }, // BTVER2 from http://www.agner.org/ 909 { ISD::FMUL, MVT::v4f64, 4 }, // BTVER2 from http://www.agner.org/ 910 911 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 912 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 913 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 914 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 915 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 916 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 917 }; 918 919 if (ST->hasAVX()) 920 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 921 return LT.first * Entry->Cost; 922 923 static const CostTblEntry SSE42CostTable[] = { 924 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 925 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 926 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 927 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 928 929 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 930 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 931 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 932 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 933 934 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 935 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 936 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 937 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 938 939 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 940 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 941 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 942 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 943 944 { ISD::MUL, MVT::v2i64, 6 } // 3*pmuludq/3*shift/2*add 945 }; 946 947 if (ST->hasSSE42()) 948 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 949 return LT.first * Entry->Cost; 950 951 static const CostTblEntry SSE41CostTable[] = { 952 { ISD::SHL, MVT::v16i8, 10 }, // pblendvb sequence. 953 { ISD::SHL, MVT::v8i16, 11 }, // pblendvb sequence. 954 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 955 956 { ISD::SRL, MVT::v16i8, 11 }, // pblendvb sequence. 957 { ISD::SRL, MVT::v8i16, 13 }, // pblendvb sequence. 958 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 959 960 { ISD::SRA, MVT::v16i8, 21 }, // pblendvb sequence. 961 { ISD::SRA, MVT::v8i16, 13 }, // pblendvb sequence. 962 963 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 964 }; 965 966 if (ST->hasSSE41()) 967 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 968 return LT.first * Entry->Cost; 969 970 static const CostTblEntry SSE2CostTable[] = { 971 // We don't correctly identify costs of casts because they are marked as 972 // custom. 973 { ISD::SHL, MVT::v16i8, 13 }, // cmpgtb sequence. 974 { ISD::SHL, MVT::v8i16, 25 }, // cmpgtw sequence. 975 { ISD::SHL, MVT::v4i32, 16 }, // pslld/paddd/cvttps2dq/pmuludq. 976 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 977 978 { ISD::SRL, MVT::v16i8, 14 }, // cmpgtb sequence. 979 { ISD::SRL, MVT::v8i16, 16 }, // cmpgtw sequence. 980 { ISD::SRL, MVT::v4i32, 12 }, // Shift each lane + blend. 981 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 982 983 { ISD::SRA, MVT::v16i8, 27 }, // unpacked cmpgtb sequence. 984 { ISD::SRA, MVT::v8i16, 16 }, // cmpgtw sequence. 985 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 986 { ISD::SRA, MVT::v2i64, 8 }, // srl/xor/sub splat+shuffle sequence. 987 988 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 989 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 990 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 991 992 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 993 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 994 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 995 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 996 997 { ISD::FNEG, MVT::f32, 1 }, // Pentium IV from http://www.agner.org/ 998 { ISD::FNEG, MVT::f64, 1 }, // Pentium IV from http://www.agner.org/ 999 { ISD::FNEG, MVT::v4f32, 1 }, // Pentium IV from http://www.agner.org/ 1000 { ISD::FNEG, MVT::v2f64, 1 }, // Pentium IV from http://www.agner.org/ 1001 1002 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 1003 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 1004 1005 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 1006 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 1007 }; 1008 1009 if (ST->hasSSE2()) 1010 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 1011 return LT.first * Entry->Cost; 1012 1013 static const CostTblEntry SSE1CostTable[] = { 1014 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 1015 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 1016 1017 { ISD::FNEG, MVT::f32, 2 }, // Pentium III from http://www.agner.org/ 1018 { ISD::FNEG, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1019 1020 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1021 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1022 1023 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1024 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1025 }; 1026 1027 if (ST->hasSSE1()) 1028 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 1029 return LT.first * Entry->Cost; 1030 1031 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 1032 { ISD::ADD, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1033 { ISD::SUB, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1034 { ISD::MUL, MVT::i64, 2 }, // Nehalem from http://www.agner.org/ 1035 }; 1036 1037 if (ST->is64Bit()) 1038 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, LT.second)) 1039 return LT.first * Entry->Cost; 1040 1041 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 1042 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1043 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1044 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1045 1046 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1047 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1048 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1049 }; 1050 1051 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, LT.second)) 1052 return LT.first * Entry->Cost; 1053 1054 // It is not a good idea to vectorize division. We have to scalarize it and 1055 // in the process we will often end up having to spilling regular 1056 // registers. The overhead of division is going to dominate most kernels 1057 // anyways so try hard to prevent vectorization of division - it is 1058 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 1059 // to hide "20 cycles" for each lane. 1060 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 1061 ISD == ISD::UDIV || ISD == ISD::UREM)) { 1062 InstructionCost ScalarCost = getArithmeticInstrCost( 1063 Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info, 1064 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 1065 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 1066 } 1067 1068 // Fallback to the default implementation. 1069 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info); 1070 } 1071 1072 InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, 1073 VectorType *BaseTp, 1074 ArrayRef<int> Mask, int Index, 1075 VectorType *SubTp) { 1076 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 1077 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 1078 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 1079 1080 Kind = improveShuffleKindFromMask(Kind, Mask); 1081 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 1082 if (Kind == TTI::SK_Transpose) 1083 Kind = TTI::SK_PermuteTwoSrc; 1084 1085 // For Broadcasts we are splatting the first element from the first input 1086 // register, so only need to reference that input and all the output 1087 // registers are the same. 1088 if (Kind == TTI::SK_Broadcast) 1089 LT.first = 1; 1090 1091 // Subvector extractions are free if they start at the beginning of a 1092 // vector and cheap if the subvectors are aligned. 1093 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 1094 int NumElts = LT.second.getVectorNumElements(); 1095 if ((Index % NumElts) == 0) 1096 return 0; 1097 std::pair<InstructionCost, MVT> SubLT = 1098 TLI->getTypeLegalizationCost(DL, SubTp); 1099 if (SubLT.second.isVector()) { 1100 int NumSubElts = SubLT.second.getVectorNumElements(); 1101 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1102 return SubLT.first; 1103 // Handle some cases for widening legalization. For now we only handle 1104 // cases where the original subvector was naturally aligned and evenly 1105 // fit in its legalized subvector type. 1106 // FIXME: Remove some of the alignment restrictions. 1107 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 1108 // vectors. 1109 int OrigSubElts = cast<FixedVectorType>(SubTp)->getNumElements(); 1110 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 1111 (NumSubElts % OrigSubElts) == 0 && 1112 LT.second.getVectorElementType() == 1113 SubLT.second.getVectorElementType() && 1114 LT.second.getVectorElementType().getSizeInBits() == 1115 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 1116 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 1117 "Unexpected number of elements!"); 1118 auto *VecTy = FixedVectorType::get(BaseTp->getElementType(), 1119 LT.second.getVectorNumElements()); 1120 auto *SubTy = FixedVectorType::get(BaseTp->getElementType(), 1121 SubLT.second.getVectorNumElements()); 1122 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 1123 InstructionCost ExtractCost = getShuffleCost( 1124 TTI::SK_ExtractSubvector, VecTy, None, ExtractIndex, SubTy); 1125 1126 // If the original size is 32-bits or more, we can use pshufd. Otherwise 1127 // if we have SSSE3 we can use pshufb. 1128 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 1129 return ExtractCost + 1; // pshufd or pshufb 1130 1131 assert(SubTp->getPrimitiveSizeInBits() == 16 && 1132 "Unexpected vector size"); 1133 1134 return ExtractCost + 2; // worst case pshufhw + pshufd 1135 } 1136 } 1137 } 1138 1139 // Subvector insertions are cheap if the subvectors are aligned. 1140 // Note that in general, the insertion starting at the beginning of a vector 1141 // isn't free, because we need to preserve the rest of the wide vector. 1142 if (Kind == TTI::SK_InsertSubvector && LT.second.isVector()) { 1143 int NumElts = LT.second.getVectorNumElements(); 1144 std::pair<InstructionCost, MVT> SubLT = 1145 TLI->getTypeLegalizationCost(DL, SubTp); 1146 if (SubLT.second.isVector()) { 1147 int NumSubElts = SubLT.second.getVectorNumElements(); 1148 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1149 return SubLT.first; 1150 } 1151 1152 // If the insertion isn't aligned, treat it like a 2-op shuffle. 1153 Kind = TTI::SK_PermuteTwoSrc; 1154 } 1155 1156 // Handle some common (illegal) sub-vector types as they are often very cheap 1157 // to shuffle even on targets without PSHUFB. 1158 EVT VT = TLI->getValueType(DL, BaseTp); 1159 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 1160 !ST->hasSSSE3()) { 1161 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 1162 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 1163 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1164 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1165 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1166 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1167 1168 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1169 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1170 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1171 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1172 1173 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1174 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1175 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1176 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1177 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1178 1179 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1180 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1181 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1182 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1183 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1184 }; 1185 1186 if (ST->hasSSE2()) 1187 if (const auto *Entry = 1188 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1189 return Entry->Cost; 1190 } 1191 1192 // We are going to permute multiple sources and the result will be in multiple 1193 // destinations. Providing an accurate cost only for splits where the element 1194 // type remains the same. 1195 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1196 MVT LegalVT = LT.second; 1197 if (LegalVT.isVector() && 1198 LegalVT.getVectorElementType().getSizeInBits() == 1199 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1200 LegalVT.getVectorNumElements() < 1201 cast<FixedVectorType>(BaseTp)->getNumElements()) { 1202 1203 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1204 unsigned LegalVTSize = LegalVT.getStoreSize(); 1205 // Number of source vectors after legalization: 1206 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1207 // Number of destination vectors after legalization: 1208 InstructionCost NumOfDests = LT.first; 1209 1210 auto *SingleOpTy = FixedVectorType::get(BaseTp->getElementType(), 1211 LegalVT.getVectorNumElements()); 1212 1213 InstructionCost NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1214 return NumOfShuffles * getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 1215 None, 0, nullptr); 1216 } 1217 1218 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1219 } 1220 1221 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1222 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1223 // We assume that source and destination have the same vector type. 1224 InstructionCost NumOfDests = LT.first; 1225 InstructionCost NumOfShufflesPerDest = LT.first * 2 - 1; 1226 LT.first = NumOfDests * NumOfShufflesPerDest; 1227 } 1228 1229 static const CostTblEntry AVX512FP16ShuffleTbl[] = { 1230 {TTI::SK_Broadcast, MVT::v32f16, 1}, // vpbroadcastw 1231 {TTI::SK_Broadcast, MVT::v16f16, 1}, // vpbroadcastw 1232 {TTI::SK_Broadcast, MVT::v8f16, 1}, // vpbroadcastw 1233 1234 {TTI::SK_Reverse, MVT::v32f16, 2}, // vpermw 1235 {TTI::SK_Reverse, MVT::v16f16, 2}, // vpermw 1236 {TTI::SK_Reverse, MVT::v8f16, 1}, // vpshufb 1237 1238 {TTI::SK_PermuteSingleSrc, MVT::v32f16, 2}, // vpermw 1239 {TTI::SK_PermuteSingleSrc, MVT::v16f16, 2}, // vpermw 1240 {TTI::SK_PermuteSingleSrc, MVT::v8f16, 1}, // vpshufb 1241 1242 {TTI::SK_PermuteTwoSrc, MVT::v32f16, 2}, // vpermt2w 1243 {TTI::SK_PermuteTwoSrc, MVT::v16f16, 2}, // vpermt2w 1244 {TTI::SK_PermuteTwoSrc, MVT::v8f16, 2} // vpermt2w 1245 }; 1246 1247 if (!ST->useSoftFloat() && ST->hasFP16()) 1248 if (const auto *Entry = 1249 CostTableLookup(AVX512FP16ShuffleTbl, Kind, LT.second)) 1250 return LT.first * Entry->Cost; 1251 1252 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1253 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1254 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1255 1256 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1257 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1258 1259 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b 1260 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b 1261 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2} // vpermt2b 1262 }; 1263 1264 if (ST->hasVBMI()) 1265 if (const auto *Entry = 1266 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1267 return LT.first * Entry->Cost; 1268 1269 static const CostTblEntry AVX512BWShuffleTbl[] = { 1270 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1271 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1272 1273 {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw 1274 {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw 1275 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1276 1277 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw 1278 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw 1279 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1280 1281 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w 1282 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w 1283 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2}, // vpermt2w 1284 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1285 1286 {TTI::SK_Select, MVT::v32i16, 1}, // vblendmw 1287 {TTI::SK_Select, MVT::v64i8, 1}, // vblendmb 1288 }; 1289 1290 if (ST->hasBWI()) 1291 if (const auto *Entry = 1292 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1293 return LT.first * Entry->Cost; 1294 1295 static const CostTblEntry AVX512ShuffleTbl[] = { 1296 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1297 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1298 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1299 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1300 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1301 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1302 1303 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1304 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1305 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1306 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1307 {TTI::SK_Reverse, MVT::v32i16, 7}, // per mca 1308 {TTI::SK_Reverse, MVT::v64i8, 7}, // per mca 1309 1310 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1311 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1312 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1313 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1314 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1315 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1316 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1317 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1318 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1319 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1320 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1321 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1322 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1323 1324 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1325 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1326 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1327 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1328 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1329 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1330 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1331 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1332 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1333 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1334 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1335 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1336 1337 // FIXME: This just applies the type legalization cost rules above 1338 // assuming these completely split. 1339 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1340 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1341 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1342 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1343 1344 {TTI::SK_Select, MVT::v32i16, 1}, // vpternlogq 1345 {TTI::SK_Select, MVT::v64i8, 1}, // vpternlogq 1346 {TTI::SK_Select, MVT::v8f64, 1}, // vblendmpd 1347 {TTI::SK_Select, MVT::v16f32, 1}, // vblendmps 1348 {TTI::SK_Select, MVT::v8i64, 1}, // vblendmq 1349 {TTI::SK_Select, MVT::v16i32, 1}, // vblendmd 1350 }; 1351 1352 if (ST->hasAVX512()) 1353 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1354 return LT.first * Entry->Cost; 1355 1356 static const CostTblEntry AVX2ShuffleTbl[] = { 1357 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1358 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1359 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1360 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1361 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1362 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1363 1364 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1365 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1366 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1367 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1368 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1369 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1370 1371 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1372 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1373 1374 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1375 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1376 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1377 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1378 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1379 // + vpblendvb 1380 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1381 // + vpblendvb 1382 1383 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1384 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1385 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1386 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1387 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1388 // + vpblendvb 1389 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1390 // + vpblendvb 1391 }; 1392 1393 if (ST->hasAVX2()) 1394 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1395 return LT.first * Entry->Cost; 1396 1397 static const CostTblEntry XOPShuffleTbl[] = { 1398 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1399 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1400 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1401 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1402 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1403 // + vinsertf128 1404 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1405 // + vinsertf128 1406 1407 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1408 // + vinsertf128 1409 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1410 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1411 // + vinsertf128 1412 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1413 }; 1414 1415 if (ST->hasXOP()) 1416 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1417 return LT.first * Entry->Cost; 1418 1419 static const CostTblEntry AVX1ShuffleTbl[] = { 1420 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1421 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1422 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1423 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1424 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1425 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1426 1427 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1428 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1429 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1430 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1431 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1432 // + vinsertf128 1433 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1434 // + vinsertf128 1435 1436 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1437 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1438 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1439 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1440 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1441 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1442 1443 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1444 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1445 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1446 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1447 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1448 // + 2*por + vinsertf128 1449 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1450 // + 2*por + vinsertf128 1451 1452 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1453 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1454 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1455 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1456 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1457 // + 4*por + vinsertf128 1458 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1459 // + 4*por + vinsertf128 1460 }; 1461 1462 if (ST->hasAVX()) 1463 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1464 return LT.first * Entry->Cost; 1465 1466 static const CostTblEntry SSE41ShuffleTbl[] = { 1467 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1468 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1469 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1470 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1471 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1472 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1473 }; 1474 1475 if (ST->hasSSE41()) 1476 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1477 return LT.first * Entry->Cost; 1478 1479 static const CostTblEntry SSSE3ShuffleTbl[] = { 1480 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1481 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1482 1483 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1484 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1485 1486 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1487 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1488 1489 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1490 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1491 1492 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1493 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1494 }; 1495 1496 if (ST->hasSSSE3()) 1497 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1498 return LT.first * Entry->Cost; 1499 1500 static const CostTblEntry SSE2ShuffleTbl[] = { 1501 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1502 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1503 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1504 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1505 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1506 1507 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1508 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1509 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1510 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1511 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1512 // + 2*pshufd + 2*unpck + packus 1513 1514 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1515 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1516 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1517 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1518 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1519 1520 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1521 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1522 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1523 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1524 // + pshufd/unpck 1525 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1526 // + 2*pshufd + 2*unpck + 2*packus 1527 1528 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1529 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1530 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1531 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1532 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1533 }; 1534 1535 if (ST->hasSSE2()) 1536 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1537 return LT.first * Entry->Cost; 1538 1539 static const CostTblEntry SSE1ShuffleTbl[] = { 1540 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1541 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1542 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1543 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1544 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1545 }; 1546 1547 if (ST->hasSSE1()) 1548 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1549 return LT.first * Entry->Cost; 1550 1551 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1552 } 1553 1554 InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, 1555 Type *Src, 1556 TTI::CastContextHint CCH, 1557 TTI::TargetCostKind CostKind, 1558 const Instruction *I) { 1559 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1560 assert(ISD && "Invalid opcode"); 1561 1562 // TODO: Allow non-throughput costs that aren't binary. 1563 auto AdjustCost = [&CostKind](InstructionCost Cost) -> InstructionCost { 1564 if (CostKind != TTI::TCK_RecipThroughput) 1565 return Cost == 0 ? 0 : 1; 1566 return Cost; 1567 }; 1568 1569 // The cost tables include both specific, custom (non-legal) src/dst type 1570 // conversions and generic, legalized types. We test for customs first, before 1571 // falling back to legalization. 1572 // FIXME: Need a better design of the cost table to handle non-simple types of 1573 // potential massive combinations (elem_num x src_type x dst_type). 1574 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1575 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1576 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1577 1578 // Mask sign extend has an instruction. 1579 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1580 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1581 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1582 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1583 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1584 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1585 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1586 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1587 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1588 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1589 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1590 1591 // Mask zero extend is a sext + shift. 1592 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1593 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1594 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1595 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1596 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1597 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1598 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1599 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1600 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1601 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1602 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1603 1604 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, 1605 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm 1606 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // widen to zmm 1607 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // widen to zmm 1608 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // vpmovwb 1609 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // widen to zmm 1610 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // widen to zmm 1611 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // vpmovwb 1612 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // widen to zmm 1613 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // widen to zmm 1614 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // vpmovwb 1615 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // widen to zmm 1616 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // widen to zmm 1617 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // widen to zmm 1618 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, 1619 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, 1620 }; 1621 1622 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1623 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1624 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1625 1626 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1627 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1628 1629 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1630 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1631 1632 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1633 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1634 }; 1635 1636 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1637 // 256-bit wide vectors. 1638 1639 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1640 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1641 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1642 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1643 1644 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1645 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1646 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1647 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd 1648 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1649 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1650 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1651 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd 1652 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd 1653 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd 1654 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd 1655 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd 1656 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq 1657 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq 1658 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq 1659 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 2 }, // vpmovdb 1660 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 2 }, // vpmovdb 1661 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, // vpmovdb 1662 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, // vpmovdb 1663 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 2 }, // vpmovqb 1664 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 1 }, // vpshufb 1665 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, // vpmovqb 1666 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, // vpmovqw 1667 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, // vpmovqd 1668 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd 1669 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb 1670 1671 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32 1672 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, 1673 1674 // Sign extend is zmm vpternlogd+vptruncdb. 1675 // Zero extend is zmm broadcast load+vptruncdw. 1676 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 }, 1677 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 }, 1678 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, 1679 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, 1680 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, 1681 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, 1682 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 }, 1683 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 }, 1684 1685 // Sign extend is zmm vpternlogd+vptruncdw. 1686 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw. 1687 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 }, 1688 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1689 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 }, 1690 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1691 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 }, 1692 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1693 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 }, 1694 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1695 1696 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd 1697 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld 1698 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd 1699 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld 1700 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd 1701 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld 1702 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq 1703 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq 1704 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq 1705 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq 1706 1707 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd 1708 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld 1709 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq 1710 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq 1711 1712 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1713 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1714 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1715 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1716 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1717 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1718 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1719 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1720 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1721 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1722 1723 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1724 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1725 1726 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1727 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1728 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, 1729 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, 1730 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1731 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, 1732 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1733 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1734 1735 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1736 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1737 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, 1738 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, 1739 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1740 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, 1741 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1742 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1743 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1744 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1745 1746 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2 }, 1747 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f64, 7 }, 1748 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f64,15 }, 1749 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f32,11 }, 1750 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f64,31 }, 1751 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, 1752 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f64, 7 }, 1753 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f32, 5 }, 1754 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f64,15 }, 1755 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 1 }, 1756 { ISD::FP_TO_SINT, MVT::v16i32, MVT::v16f64, 3 }, 1757 1758 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1759 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, 1760 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, 1761 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1762 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, 1763 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, 1764 }; 1765 1766 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1767 // Mask sign extend has an instruction. 1768 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1769 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1770 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1771 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1772 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1773 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1774 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1775 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1776 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1777 1778 // Mask zero extend is a sext + shift. 1779 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1780 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1781 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1782 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1783 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1784 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1785 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1786 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1787 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1788 1789 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, 1790 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // vpsllw+vptestmb 1791 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // vpsllw+vptestmw 1792 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // vpsllw+vptestmb 1793 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // vpsllw+vptestmw 1794 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // vpsllw+vptestmb 1795 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // vpsllw+vptestmw 1796 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // vpsllw+vptestmb 1797 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // vpsllw+vptestmw 1798 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // vpsllw+vptestmb 1799 }; 1800 1801 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1802 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1803 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1804 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1805 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1806 1807 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1808 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1809 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1810 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1811 1812 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v4f32, 1 }, 1813 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1814 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1815 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1816 1817 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v4f32, 1 }, 1818 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1819 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1820 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1821 }; 1822 1823 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 1824 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1825 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1826 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1827 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 8 }, // split+2*v8i8 1828 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1829 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1830 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1831 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16 1832 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // vpslld+vptestmd 1833 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd 1834 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // vpslld+vptestmd 1835 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // vpsllq+vptestmq 1836 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // vpsllq+vptestmq 1837 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // vpmovqd 1838 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, // vpmovqb 1839 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, // vpmovqw 1840 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, // vpmovwb 1841 1842 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb 1843 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb 1844 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 }, 1845 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 }, 1846 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 }, 1847 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 }, 1848 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 }, 1849 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 }, 1850 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 }, 1851 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 }, 1852 1853 // sign extend is vpcmpeq+maskedmove+vpmovdw 1854 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw 1855 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1856 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 }, 1857 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1858 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 }, 1859 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1860 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 }, 1861 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 }, 1862 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 }, 1863 1864 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd 1865 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld 1866 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd 1867 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld 1868 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd 1869 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld 1870 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq 1871 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq 1872 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq 1873 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq 1874 1875 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 1 }, 1876 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 1 }, 1877 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 1 }, 1878 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 1 }, 1879 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1880 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1881 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 1 }, 1882 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 1 }, 1883 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1884 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1885 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1886 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1887 1888 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 1889 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 1 }, 1890 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 1891 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 1 }, 1892 1893 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 1894 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1895 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 1896 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 1 }, 1897 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 1898 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 1 }, 1899 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 1900 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1901 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1902 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1903 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1904 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1905 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1906 1907 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v8f32, 2 }, 1908 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2 }, 1909 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f32, 5 }, 1910 1911 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 1912 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 1913 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1914 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 1 }, 1915 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1916 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1917 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1918 }; 1919 1920 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1921 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1922 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1923 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1924 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1925 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1926 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1927 1928 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 2 }, 1929 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 2 }, 1930 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 2 }, 1931 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 2 }, 1932 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1933 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1934 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 2 }, 1935 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 2 }, 1936 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1937 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1938 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1939 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1940 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1941 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1942 1943 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1944 1945 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 4 }, 1946 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 4 }, 1947 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i16, 1 }, 1948 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 1 }, 1949 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 1 }, 1950 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i32, 4 }, 1951 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i64, 4 }, 1952 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 1 }, 1953 { ISD::TRUNCATE, MVT::v8i16, MVT::v2i64, 1 }, 1954 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i64, 5 }, 1955 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, 1956 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1957 1958 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1959 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1960 1961 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v8f32, 1 }, 1962 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 1 }, 1963 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 1 }, 1964 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 3 }, 1965 1966 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 3 }, 1967 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 3 }, 1968 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v8f32, 1 }, 1969 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 3 }, 1970 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 1971 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4 }, 1972 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 3 }, 1973 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v4f64, 4 }, 1974 1975 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 2 }, 1976 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 2 }, 1977 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 2 }, 1978 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1979 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1980 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1981 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 3 }, 1982 1983 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 2 }, 1984 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 2 }, 1985 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 2 }, 1986 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1987 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1988 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1989 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 2 }, 1990 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 1991 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 1992 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 }, 1993 }; 1994 1995 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1996 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1997 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1998 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1999 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 2000 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 2001 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 2002 2003 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 3 }, 2004 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 3 }, 2005 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 3 }, 2006 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 3 }, 2007 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 2008 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 2009 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 3 }, 2010 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 3 }, 2011 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 2012 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 2013 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 2014 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 2015 2016 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 4 }, 2017 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 5 }, 2018 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 4 }, 2019 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 9 }, 2020 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, 11 }, 2021 2022 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 2023 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, 2024 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // and+extract+packuswb 2025 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i32, 5 }, 2026 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2027 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i64, 5 }, 2028 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i64, 3 }, // and+extract+2*packusdw 2029 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 2030 2031 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 2032 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 2033 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 2034 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 4 }, 2035 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v16i8, 2 }, 2036 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 2037 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v8i16, 2 }, 2038 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2039 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 2040 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 }, 2041 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 5 }, 2042 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 8 }, 2043 2044 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 2045 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 2046 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 2047 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 4 }, 2048 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v16i8, 2 }, 2049 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 2050 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v8i16, 2 }, 2051 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 4 }, 2052 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 4 }, 2053 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 2054 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 2055 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 2056 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 10 }, 2057 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 10 }, 2058 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 18 }, 2059 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 2060 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 10 }, 2061 2062 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v8f32, 2 }, 2063 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f64, 2 }, 2064 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v8f32, 2 }, 2065 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v4f64, 2 }, 2066 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 2 }, 2067 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f64, 2 }, 2068 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v8f32, 2 }, 2069 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v4f64, 2 }, 2070 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 2 }, 2071 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 2 }, 2072 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 5 }, 2073 2074 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v8f32, 2 }, 2075 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f64, 2 }, 2076 { ISD::FP_TO_UINT, MVT::v32i8, MVT::v8f32, 2 }, 2077 { ISD::FP_TO_UINT, MVT::v32i8, MVT::v4f64, 2 }, 2078 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 2 }, 2079 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f64, 2 }, 2080 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v8f32, 2 }, 2081 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v4f64, 2 }, 2082 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 3 }, 2083 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 2084 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 6 }, 2085 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 7 }, 2086 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v4f64, 7 }, 2087 2088 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 2089 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 2090 }; 2091 2092 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 2093 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8, 1 }, 2094 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8, 1 }, 2095 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8, 1 }, 2096 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8, 1 }, 2097 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2098 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2099 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16, 1 }, 2100 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16, 1 }, 2101 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2102 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2103 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2104 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2105 2106 // These truncates end up widening elements. 2107 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 1 }, // PMOVXZBQ 2108 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 1 }, // PMOVXZWQ 2109 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 1 }, // PMOVXZBD 2110 2111 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 2 }, 2112 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 2 }, 2113 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 2 }, 2114 2115 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 1 }, 2116 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 1 }, 2117 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 1 }, 2118 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 1 }, 2119 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 1 }, 2120 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2121 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 1 }, 2122 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2123 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 2124 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 1 }, 2125 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2126 2127 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 1 }, 2128 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 1 }, 2129 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 2130 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 2131 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 1 }, 2132 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2133 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 1 }, 2134 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2135 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 3 }, 2136 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 3 }, 2137 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 2 }, 2138 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 12 }, 2139 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 22 }, 2140 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 4 }, 2141 2142 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 1 }, 2143 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 1 }, 2144 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 1 }, 2145 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 1 }, 2146 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f32, 2 }, 2147 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v2f64, 2 }, 2148 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f32, 1 }, 2149 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v2f64, 1 }, 2150 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, 2151 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v2f64, 1 }, 2152 2153 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 1 }, 2154 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 2155 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 1 }, 2156 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 2157 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f32, 2 }, 2158 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v2f64, 2 }, 2159 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f32, 1 }, 2160 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v2f64, 1 }, 2161 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 4 }, 2162 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 2163 }; 2164 2165 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 2166 // These are somewhat magic numbers justified by comparing the 2167 // output of llvm-mca for our various supported scheduler models 2168 // and basing it off the worst case scenario. 2169 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 3 }, 2170 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 3 }, 2171 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 3 }, 2172 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 3 }, 2173 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 3 }, 2174 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 4 }, 2175 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 3 }, 2176 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 4 }, 2177 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 3 }, 2178 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4 }, 2179 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 8 }, 2180 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 8 }, 2181 2182 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 3 }, 2183 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 3 }, 2184 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 8 }, 2185 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 9 }, 2186 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 4 }, 2187 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 4 }, 2188 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 4 }, 2189 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 4 }, 2190 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 7 }, 2191 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 7 }, 2192 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 2193 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 15 }, 2194 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 18 }, 2195 2196 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 4 }, 2197 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 4 }, 2198 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 4 }, 2199 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 4 }, 2200 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f32, 6 }, 2201 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v2f64, 6 }, 2202 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f32, 5 }, 2203 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v2f64, 5 }, 2204 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 4 }, 2205 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v2f64, 4 }, 2206 2207 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 4 }, 2208 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 2209 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 4 }, 2210 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 15 }, 2211 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f32, 6 }, 2212 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v2f64, 6 }, 2213 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f32, 5 }, 2214 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v2f64, 5 }, 2215 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 8 }, 2216 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 8 }, 2217 2218 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8, 4 }, 2219 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8, 4 }, 2220 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8, 2 }, 2221 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8, 3 }, 2222 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2223 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8, 2 }, 2224 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16, 2 }, 2225 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16, 3 }, 2226 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2227 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16, 2 }, 2228 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2229 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32, 2 }, 2230 2231 // These truncates are really widening elements. 2232 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 1 }, // PSHUFD 2233 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // PUNPCKLWD+DQ 2234 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // PUNPCKLBW+WD+PSHUFD 2235 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 1 }, // PUNPCKLWD 2236 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // PUNPCKLBW+WD 2237 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 1 }, // PUNPCKLBW 2238 2239 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i16, 2 }, // PAND+PACKUSWB 2240 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 2241 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 3 }, // PAND+2*PACKUSWB 2242 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 2243 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 2244 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 3 }, 2245 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2246 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32,10 }, 2247 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 2248 { ISD::TRUNCATE, MVT::v8i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 2249 { ISD::TRUNCATE, MVT::v4i32, MVT::v2i64, 1 }, // PSHUFD 2250 }; 2251 2252 // Attempt to map directly to (simple) MVT types to let us match custom entries. 2253 EVT SrcTy = TLI->getValueType(DL, Src); 2254 EVT DstTy = TLI->getValueType(DL, Dst); 2255 2256 // The function getSimpleVT only handles simple value types. 2257 if (SrcTy.isSimple() && DstTy.isSimple()) { 2258 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 2259 MVT SimpleDstTy = DstTy.getSimpleVT(); 2260 2261 if (ST->useAVX512Regs()) { 2262 if (ST->hasBWI()) 2263 if (const auto *Entry = ConvertCostTableLookup( 2264 AVX512BWConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2265 return AdjustCost(Entry->Cost); 2266 2267 if (ST->hasDQI()) 2268 if (const auto *Entry = ConvertCostTableLookup( 2269 AVX512DQConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2270 return AdjustCost(Entry->Cost); 2271 2272 if (ST->hasAVX512()) 2273 if (const auto *Entry = ConvertCostTableLookup( 2274 AVX512FConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2275 return AdjustCost(Entry->Cost); 2276 } 2277 2278 if (ST->hasBWI()) 2279 if (const auto *Entry = ConvertCostTableLookup( 2280 AVX512BWVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2281 return AdjustCost(Entry->Cost); 2282 2283 if (ST->hasDQI()) 2284 if (const auto *Entry = ConvertCostTableLookup( 2285 AVX512DQVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2286 return AdjustCost(Entry->Cost); 2287 2288 if (ST->hasAVX512()) 2289 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2290 SimpleDstTy, SimpleSrcTy)) 2291 return AdjustCost(Entry->Cost); 2292 2293 if (ST->hasAVX2()) { 2294 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2295 SimpleDstTy, SimpleSrcTy)) 2296 return AdjustCost(Entry->Cost); 2297 } 2298 2299 if (ST->hasAVX()) { 2300 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2301 SimpleDstTy, SimpleSrcTy)) 2302 return AdjustCost(Entry->Cost); 2303 } 2304 2305 if (ST->hasSSE41()) { 2306 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2307 SimpleDstTy, SimpleSrcTy)) 2308 return AdjustCost(Entry->Cost); 2309 } 2310 2311 if (ST->hasSSE2()) { 2312 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2313 SimpleDstTy, SimpleSrcTy)) 2314 return AdjustCost(Entry->Cost); 2315 } 2316 } 2317 2318 // Fall back to legalized types. 2319 std::pair<InstructionCost, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 2320 std::pair<InstructionCost, MVT> LTDest = 2321 TLI->getTypeLegalizationCost(DL, Dst); 2322 2323 if (ST->useAVX512Regs()) { 2324 if (ST->hasBWI()) 2325 if (const auto *Entry = ConvertCostTableLookup( 2326 AVX512BWConversionTbl, ISD, LTDest.second, LTSrc.second)) 2327 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2328 2329 if (ST->hasDQI()) 2330 if (const auto *Entry = ConvertCostTableLookup( 2331 AVX512DQConversionTbl, ISD, LTDest.second, LTSrc.second)) 2332 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2333 2334 if (ST->hasAVX512()) 2335 if (const auto *Entry = ConvertCostTableLookup( 2336 AVX512FConversionTbl, ISD, LTDest.second, LTSrc.second)) 2337 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2338 } 2339 2340 if (ST->hasBWI()) 2341 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 2342 LTDest.second, LTSrc.second)) 2343 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2344 2345 if (ST->hasDQI()) 2346 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 2347 LTDest.second, LTSrc.second)) 2348 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2349 2350 if (ST->hasAVX512()) 2351 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2352 LTDest.second, LTSrc.second)) 2353 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2354 2355 if (ST->hasAVX2()) 2356 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2357 LTDest.second, LTSrc.second)) 2358 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2359 2360 if (ST->hasAVX()) 2361 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2362 LTDest.second, LTSrc.second)) 2363 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2364 2365 if (ST->hasSSE41()) 2366 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2367 LTDest.second, LTSrc.second)) 2368 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2369 2370 if (ST->hasSSE2()) 2371 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2372 LTDest.second, LTSrc.second)) 2373 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2374 2375 // Fallback, for i8/i16 sitofp/uitofp cases we need to extend to i32 for 2376 // sitofp. 2377 if ((ISD == ISD::SINT_TO_FP || ISD == ISD::UINT_TO_FP) && 2378 1 < Src->getScalarSizeInBits() && Src->getScalarSizeInBits() < 32) { 2379 Type *ExtSrc = Src->getWithNewBitWidth(32); 2380 unsigned ExtOpc = 2381 (ISD == ISD::SINT_TO_FP) ? Instruction::SExt : Instruction::ZExt; 2382 2383 // For scalar loads the extend would be free. 2384 InstructionCost ExtCost = 0; 2385 if (!(Src->isIntegerTy() && I && isa<LoadInst>(I->getOperand(0)))) 2386 ExtCost = getCastInstrCost(ExtOpc, ExtSrc, Src, CCH, CostKind); 2387 2388 return ExtCost + getCastInstrCost(Instruction::SIToFP, Dst, ExtSrc, 2389 TTI::CastContextHint::None, CostKind); 2390 } 2391 2392 // Fallback for fptosi/fptoui i8/i16 cases we need to truncate from fptosi 2393 // i32. 2394 if ((ISD == ISD::FP_TO_SINT || ISD == ISD::FP_TO_UINT) && 2395 1 < Dst->getScalarSizeInBits() && Dst->getScalarSizeInBits() < 32) { 2396 Type *TruncDst = Dst->getWithNewBitWidth(32); 2397 return getCastInstrCost(Instruction::FPToSI, TruncDst, Src, CCH, CostKind) + 2398 getCastInstrCost(Instruction::Trunc, Dst, TruncDst, 2399 TTI::CastContextHint::None, CostKind); 2400 } 2401 2402 return AdjustCost( 2403 BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I)); 2404 } 2405 2406 InstructionCost X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 2407 Type *CondTy, 2408 CmpInst::Predicate VecPred, 2409 TTI::TargetCostKind CostKind, 2410 const Instruction *I) { 2411 // TODO: Handle other cost kinds. 2412 if (CostKind != TTI::TCK_RecipThroughput) 2413 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, 2414 I); 2415 2416 // Legalize the type. 2417 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2418 2419 MVT MTy = LT.second; 2420 2421 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2422 assert(ISD && "Invalid opcode"); 2423 2424 unsigned ExtraCost = 0; 2425 if (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp) { 2426 // Some vector comparison predicates cost extra instructions. 2427 // TODO: Should we invert this and assume worst case cmp costs 2428 // and reduce for particular predicates? 2429 if (MTy.isVector() && 2430 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 2431 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 2432 ST->hasBWI())) { 2433 // Fallback to I if a specific predicate wasn't specified. 2434 CmpInst::Predicate Pred = VecPred; 2435 if (I && (Pred == CmpInst::BAD_ICMP_PREDICATE || 2436 Pred == CmpInst::BAD_FCMP_PREDICATE)) 2437 Pred = cast<CmpInst>(I)->getPredicate(); 2438 2439 switch (Pred) { 2440 case CmpInst::Predicate::ICMP_NE: 2441 // xor(cmpeq(x,y),-1) 2442 ExtraCost = 1; 2443 break; 2444 case CmpInst::Predicate::ICMP_SGE: 2445 case CmpInst::Predicate::ICMP_SLE: 2446 // xor(cmpgt(x,y),-1) 2447 ExtraCost = 1; 2448 break; 2449 case CmpInst::Predicate::ICMP_ULT: 2450 case CmpInst::Predicate::ICMP_UGT: 2451 // cmpgt(xor(x,signbit),xor(y,signbit)) 2452 // xor(cmpeq(pmaxu(x,y),x),-1) 2453 ExtraCost = 2; 2454 break; 2455 case CmpInst::Predicate::ICMP_ULE: 2456 case CmpInst::Predicate::ICMP_UGE: 2457 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 2458 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 2459 // cmpeq(psubus(x,y),0) 2460 // cmpeq(pminu(x,y),x) 2461 ExtraCost = 1; 2462 } else { 2463 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 2464 ExtraCost = 3; 2465 } 2466 break; 2467 case CmpInst::Predicate::BAD_ICMP_PREDICATE: 2468 case CmpInst::Predicate::BAD_FCMP_PREDICATE: 2469 // Assume worst case scenario and add the maximum extra cost. 2470 ExtraCost = 3; 2471 break; 2472 default: 2473 break; 2474 } 2475 } 2476 } 2477 2478 static const CostTblEntry SLMCostTbl[] = { 2479 // slm pcmpeq/pcmpgt throughput is 2 2480 { ISD::SETCC, MVT::v2i64, 2 }, 2481 }; 2482 2483 static const CostTblEntry AVX512BWCostTbl[] = { 2484 { ISD::SETCC, MVT::v32i16, 1 }, 2485 { ISD::SETCC, MVT::v64i8, 1 }, 2486 2487 { ISD::SELECT, MVT::v32i16, 1 }, 2488 { ISD::SELECT, MVT::v64i8, 1 }, 2489 }; 2490 2491 static const CostTblEntry AVX512CostTbl[] = { 2492 { ISD::SETCC, MVT::v8i64, 1 }, 2493 { ISD::SETCC, MVT::v16i32, 1 }, 2494 { ISD::SETCC, MVT::v8f64, 1 }, 2495 { ISD::SETCC, MVT::v16f32, 1 }, 2496 2497 { ISD::SELECT, MVT::v8i64, 1 }, 2498 { ISD::SELECT, MVT::v16i32, 1 }, 2499 { ISD::SELECT, MVT::v8f64, 1 }, 2500 { ISD::SELECT, MVT::v16f32, 1 }, 2501 2502 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 2503 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 2504 2505 { ISD::SELECT, MVT::v32i16, 2 }, // FIXME: should be 3 2506 { ISD::SELECT, MVT::v64i8, 2 }, // FIXME: should be 3 2507 }; 2508 2509 static const CostTblEntry AVX2CostTbl[] = { 2510 { ISD::SETCC, MVT::v4i64, 1 }, 2511 { ISD::SETCC, MVT::v8i32, 1 }, 2512 { ISD::SETCC, MVT::v16i16, 1 }, 2513 { ISD::SETCC, MVT::v32i8, 1 }, 2514 2515 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 2516 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 2517 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 2518 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 2519 }; 2520 2521 static const CostTblEntry AVX1CostTbl[] = { 2522 { ISD::SETCC, MVT::v4f64, 1 }, 2523 { ISD::SETCC, MVT::v8f32, 1 }, 2524 // AVX1 does not support 8-wide integer compare. 2525 { ISD::SETCC, MVT::v4i64, 4 }, 2526 { ISD::SETCC, MVT::v8i32, 4 }, 2527 { ISD::SETCC, MVT::v16i16, 4 }, 2528 { ISD::SETCC, MVT::v32i8, 4 }, 2529 2530 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 2531 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 2532 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 2533 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 2534 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 2535 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 2536 }; 2537 2538 static const CostTblEntry SSE42CostTbl[] = { 2539 { ISD::SETCC, MVT::v2f64, 1 }, 2540 { ISD::SETCC, MVT::v4f32, 1 }, 2541 { ISD::SETCC, MVT::v2i64, 1 }, 2542 }; 2543 2544 static const CostTblEntry SSE41CostTbl[] = { 2545 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 2546 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 2547 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 2548 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 2549 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 2550 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 2551 }; 2552 2553 static const CostTblEntry SSE2CostTbl[] = { 2554 { ISD::SETCC, MVT::v2f64, 2 }, 2555 { ISD::SETCC, MVT::f64, 1 }, 2556 { ISD::SETCC, MVT::v2i64, 8 }, 2557 { ISD::SETCC, MVT::v4i32, 1 }, 2558 { ISD::SETCC, MVT::v8i16, 1 }, 2559 { ISD::SETCC, MVT::v16i8, 1 }, 2560 2561 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 2562 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 2563 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 2564 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 2565 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 2566 }; 2567 2568 static const CostTblEntry SSE1CostTbl[] = { 2569 { ISD::SETCC, MVT::v4f32, 2 }, 2570 { ISD::SETCC, MVT::f32, 1 }, 2571 2572 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 2573 }; 2574 2575 if (ST->isSLM()) 2576 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2577 return LT.first * (ExtraCost + Entry->Cost); 2578 2579 if (ST->hasBWI()) 2580 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2581 return LT.first * (ExtraCost + Entry->Cost); 2582 2583 if (ST->hasAVX512()) 2584 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2585 return LT.first * (ExtraCost + Entry->Cost); 2586 2587 if (ST->hasAVX2()) 2588 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2589 return LT.first * (ExtraCost + Entry->Cost); 2590 2591 if (ST->hasAVX()) 2592 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2593 return LT.first * (ExtraCost + Entry->Cost); 2594 2595 if (ST->hasSSE42()) 2596 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2597 return LT.first * (ExtraCost + Entry->Cost); 2598 2599 if (ST->hasSSE41()) 2600 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2601 return LT.first * (ExtraCost + Entry->Cost); 2602 2603 if (ST->hasSSE2()) 2604 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2605 return LT.first * (ExtraCost + Entry->Cost); 2606 2607 if (ST->hasSSE1()) 2608 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2609 return LT.first * (ExtraCost + Entry->Cost); 2610 2611 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I); 2612 } 2613 2614 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2615 2616 InstructionCost 2617 X86TTIImpl::getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 2618 TTI::TargetCostKind CostKind) { 2619 2620 // Costs should match the codegen from: 2621 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2622 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2623 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2624 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2625 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2626 2627 // TODO: Overflow intrinsics (*ADDO, *SUBO, *MULO) with vector types are not 2628 // specialized in these tables yet. 2629 static const CostTblEntry AVX512BITALGCostTbl[] = { 2630 { ISD::CTPOP, MVT::v32i16, 1 }, 2631 { ISD::CTPOP, MVT::v64i8, 1 }, 2632 { ISD::CTPOP, MVT::v16i16, 1 }, 2633 { ISD::CTPOP, MVT::v32i8, 1 }, 2634 { ISD::CTPOP, MVT::v8i16, 1 }, 2635 { ISD::CTPOP, MVT::v16i8, 1 }, 2636 }; 2637 static const CostTblEntry AVX512VPOPCNTDQCostTbl[] = { 2638 { ISD::CTPOP, MVT::v8i64, 1 }, 2639 { ISD::CTPOP, MVT::v16i32, 1 }, 2640 { ISD::CTPOP, MVT::v4i64, 1 }, 2641 { ISD::CTPOP, MVT::v8i32, 1 }, 2642 { ISD::CTPOP, MVT::v2i64, 1 }, 2643 { ISD::CTPOP, MVT::v4i32, 1 }, 2644 }; 2645 static const CostTblEntry AVX512CDCostTbl[] = { 2646 { ISD::CTLZ, MVT::v8i64, 1 }, 2647 { ISD::CTLZ, MVT::v16i32, 1 }, 2648 { ISD::CTLZ, MVT::v32i16, 8 }, 2649 { ISD::CTLZ, MVT::v64i8, 20 }, 2650 { ISD::CTLZ, MVT::v4i64, 1 }, 2651 { ISD::CTLZ, MVT::v8i32, 1 }, 2652 { ISD::CTLZ, MVT::v16i16, 4 }, 2653 { ISD::CTLZ, MVT::v32i8, 10 }, 2654 { ISD::CTLZ, MVT::v2i64, 1 }, 2655 { ISD::CTLZ, MVT::v4i32, 1 }, 2656 { ISD::CTLZ, MVT::v8i16, 4 }, 2657 { ISD::CTLZ, MVT::v16i8, 4 }, 2658 }; 2659 static const CostTblEntry AVX512BWCostTbl[] = { 2660 { ISD::ABS, MVT::v32i16, 1 }, 2661 { ISD::ABS, MVT::v64i8, 1 }, 2662 { ISD::BITREVERSE, MVT::v8i64, 3 }, 2663 { ISD::BITREVERSE, MVT::v16i32, 3 }, 2664 { ISD::BITREVERSE, MVT::v32i16, 3 }, 2665 { ISD::BITREVERSE, MVT::v64i8, 2 }, 2666 { ISD::BSWAP, MVT::v8i64, 1 }, 2667 { ISD::BSWAP, MVT::v16i32, 1 }, 2668 { ISD::BSWAP, MVT::v32i16, 1 }, 2669 { ISD::CTLZ, MVT::v8i64, 23 }, 2670 { ISD::CTLZ, MVT::v16i32, 22 }, 2671 { ISD::CTLZ, MVT::v32i16, 18 }, 2672 { ISD::CTLZ, MVT::v64i8, 17 }, 2673 { ISD::CTPOP, MVT::v8i64, 7 }, 2674 { ISD::CTPOP, MVT::v16i32, 11 }, 2675 { ISD::CTPOP, MVT::v32i16, 9 }, 2676 { ISD::CTPOP, MVT::v64i8, 6 }, 2677 { ISD::CTTZ, MVT::v8i64, 10 }, 2678 { ISD::CTTZ, MVT::v16i32, 14 }, 2679 { ISD::CTTZ, MVT::v32i16, 12 }, 2680 { ISD::CTTZ, MVT::v64i8, 9 }, 2681 { ISD::SADDSAT, MVT::v32i16, 1 }, 2682 { ISD::SADDSAT, MVT::v64i8, 1 }, 2683 { ISD::SMAX, MVT::v32i16, 1 }, 2684 { ISD::SMAX, MVT::v64i8, 1 }, 2685 { ISD::SMIN, MVT::v32i16, 1 }, 2686 { ISD::SMIN, MVT::v64i8, 1 }, 2687 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2688 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2689 { ISD::UADDSAT, MVT::v32i16, 1 }, 2690 { ISD::UADDSAT, MVT::v64i8, 1 }, 2691 { ISD::UMAX, MVT::v32i16, 1 }, 2692 { ISD::UMAX, MVT::v64i8, 1 }, 2693 { ISD::UMIN, MVT::v32i16, 1 }, 2694 { ISD::UMIN, MVT::v64i8, 1 }, 2695 { ISD::USUBSAT, MVT::v32i16, 1 }, 2696 { ISD::USUBSAT, MVT::v64i8, 1 }, 2697 }; 2698 static const CostTblEntry AVX512CostTbl[] = { 2699 { ISD::ABS, MVT::v8i64, 1 }, 2700 { ISD::ABS, MVT::v16i32, 1 }, 2701 { ISD::ABS, MVT::v32i16, 2 }, // FIXME: include split 2702 { ISD::ABS, MVT::v64i8, 2 }, // FIXME: include split 2703 { ISD::ABS, MVT::v4i64, 1 }, 2704 { ISD::ABS, MVT::v2i64, 1 }, 2705 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2706 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2707 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2708 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2709 { ISD::BSWAP, MVT::v8i64, 4 }, 2710 { ISD::BSWAP, MVT::v16i32, 4 }, 2711 { ISD::BSWAP, MVT::v32i16, 4 }, 2712 { ISD::CTLZ, MVT::v8i64, 29 }, 2713 { ISD::CTLZ, MVT::v16i32, 35 }, 2714 { ISD::CTLZ, MVT::v32i16, 28 }, 2715 { ISD::CTLZ, MVT::v64i8, 18 }, 2716 { ISD::CTPOP, MVT::v8i64, 16 }, 2717 { ISD::CTPOP, MVT::v16i32, 24 }, 2718 { ISD::CTPOP, MVT::v32i16, 18 }, 2719 { ISD::CTPOP, MVT::v64i8, 12 }, 2720 { ISD::CTTZ, MVT::v8i64, 20 }, 2721 { ISD::CTTZ, MVT::v16i32, 28 }, 2722 { ISD::CTTZ, MVT::v32i16, 24 }, 2723 { ISD::CTTZ, MVT::v64i8, 18 }, 2724 { ISD::SMAX, MVT::v8i64, 1 }, 2725 { ISD::SMAX, MVT::v16i32, 1 }, 2726 { ISD::SMAX, MVT::v32i16, 2 }, // FIXME: include split 2727 { ISD::SMAX, MVT::v64i8, 2 }, // FIXME: include split 2728 { ISD::SMAX, MVT::v4i64, 1 }, 2729 { ISD::SMAX, MVT::v2i64, 1 }, 2730 { ISD::SMIN, MVT::v8i64, 1 }, 2731 { ISD::SMIN, MVT::v16i32, 1 }, 2732 { ISD::SMIN, MVT::v32i16, 2 }, // FIXME: include split 2733 { ISD::SMIN, MVT::v64i8, 2 }, // FIXME: include split 2734 { ISD::SMIN, MVT::v4i64, 1 }, 2735 { ISD::SMIN, MVT::v2i64, 1 }, 2736 { ISD::UMAX, MVT::v8i64, 1 }, 2737 { ISD::UMAX, MVT::v16i32, 1 }, 2738 { ISD::UMAX, MVT::v32i16, 2 }, // FIXME: include split 2739 { ISD::UMAX, MVT::v64i8, 2 }, // FIXME: include split 2740 { ISD::UMAX, MVT::v4i64, 1 }, 2741 { ISD::UMAX, MVT::v2i64, 1 }, 2742 { ISD::UMIN, MVT::v8i64, 1 }, 2743 { ISD::UMIN, MVT::v16i32, 1 }, 2744 { ISD::UMIN, MVT::v32i16, 2 }, // FIXME: include split 2745 { ISD::UMIN, MVT::v64i8, 2 }, // FIXME: include split 2746 { ISD::UMIN, MVT::v4i64, 1 }, 2747 { ISD::UMIN, MVT::v2i64, 1 }, 2748 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2749 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2750 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2751 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2752 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2753 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2754 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2755 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2756 { ISD::SADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2757 { ISD::SADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2758 { ISD::SSUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2759 { ISD::SSUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2760 { ISD::UADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2761 { ISD::UADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2762 { ISD::USUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2763 { ISD::USUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2764 { ISD::FMAXNUM, MVT::f32, 2 }, 2765 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2766 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2767 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2768 { ISD::FMAXNUM, MVT::f64, 2 }, 2769 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2770 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2771 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2772 }; 2773 static const CostTblEntry XOPCostTbl[] = { 2774 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2775 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2776 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2777 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2778 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2779 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2780 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2781 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2782 { ISD::BITREVERSE, MVT::i64, 3 }, 2783 { ISD::BITREVERSE, MVT::i32, 3 }, 2784 { ISD::BITREVERSE, MVT::i16, 3 }, 2785 { ISD::BITREVERSE, MVT::i8, 3 } 2786 }; 2787 static const CostTblEntry AVX2CostTbl[] = { 2788 { ISD::ABS, MVT::v4i64, 2 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2789 { ISD::ABS, MVT::v8i32, 1 }, 2790 { ISD::ABS, MVT::v16i16, 1 }, 2791 { ISD::ABS, MVT::v32i8, 1 }, 2792 { ISD::BITREVERSE, MVT::v2i64, 3 }, 2793 { ISD::BITREVERSE, MVT::v4i64, 3 }, 2794 { ISD::BITREVERSE, MVT::v4i32, 3 }, 2795 { ISD::BITREVERSE, MVT::v8i32, 3 }, 2796 { ISD::BITREVERSE, MVT::v8i16, 3 }, 2797 { ISD::BITREVERSE, MVT::v16i16, 3 }, 2798 { ISD::BITREVERSE, MVT::v16i8, 3 }, 2799 { ISD::BITREVERSE, MVT::v32i8, 3 }, 2800 { ISD::BSWAP, MVT::v4i64, 1 }, 2801 { ISD::BSWAP, MVT::v8i32, 1 }, 2802 { ISD::BSWAP, MVT::v16i16, 1 }, 2803 { ISD::CTLZ, MVT::v2i64, 7 }, 2804 { ISD::CTLZ, MVT::v4i64, 7 }, 2805 { ISD::CTLZ, MVT::v4i32, 5 }, 2806 { ISD::CTLZ, MVT::v8i32, 5 }, 2807 { ISD::CTLZ, MVT::v8i16, 4 }, 2808 { ISD::CTLZ, MVT::v16i16, 4 }, 2809 { ISD::CTLZ, MVT::v16i8, 3 }, 2810 { ISD::CTLZ, MVT::v32i8, 3 }, 2811 { ISD::CTPOP, MVT::v2i64, 3 }, 2812 { ISD::CTPOP, MVT::v4i64, 3 }, 2813 { ISD::CTPOP, MVT::v4i32, 7 }, 2814 { ISD::CTPOP, MVT::v8i32, 7 }, 2815 { ISD::CTPOP, MVT::v8i16, 3 }, 2816 { ISD::CTPOP, MVT::v16i16, 3 }, 2817 { ISD::CTPOP, MVT::v16i8, 2 }, 2818 { ISD::CTPOP, MVT::v32i8, 2 }, 2819 { ISD::CTTZ, MVT::v2i64, 4 }, 2820 { ISD::CTTZ, MVT::v4i64, 4 }, 2821 { ISD::CTTZ, MVT::v4i32, 7 }, 2822 { ISD::CTTZ, MVT::v8i32, 7 }, 2823 { ISD::CTTZ, MVT::v8i16, 4 }, 2824 { ISD::CTTZ, MVT::v16i16, 4 }, 2825 { ISD::CTTZ, MVT::v16i8, 3 }, 2826 { ISD::CTTZ, MVT::v32i8, 3 }, 2827 { ISD::SADDSAT, MVT::v16i16, 1 }, 2828 { ISD::SADDSAT, MVT::v32i8, 1 }, 2829 { ISD::SMAX, MVT::v8i32, 1 }, 2830 { ISD::SMAX, MVT::v16i16, 1 }, 2831 { ISD::SMAX, MVT::v32i8, 1 }, 2832 { ISD::SMIN, MVT::v8i32, 1 }, 2833 { ISD::SMIN, MVT::v16i16, 1 }, 2834 { ISD::SMIN, MVT::v32i8, 1 }, 2835 { ISD::SSUBSAT, MVT::v16i16, 1 }, 2836 { ISD::SSUBSAT, MVT::v32i8, 1 }, 2837 { ISD::UADDSAT, MVT::v16i16, 1 }, 2838 { ISD::UADDSAT, MVT::v32i8, 1 }, 2839 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 2840 { ISD::UMAX, MVT::v8i32, 1 }, 2841 { ISD::UMAX, MVT::v16i16, 1 }, 2842 { ISD::UMAX, MVT::v32i8, 1 }, 2843 { ISD::UMIN, MVT::v8i32, 1 }, 2844 { ISD::UMIN, MVT::v16i16, 1 }, 2845 { ISD::UMIN, MVT::v32i8, 1 }, 2846 { ISD::USUBSAT, MVT::v16i16, 1 }, 2847 { ISD::USUBSAT, MVT::v32i8, 1 }, 2848 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2849 { ISD::FMAXNUM, MVT::v8f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2850 { ISD::FMAXNUM, MVT::v4f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2851 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2852 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2853 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2854 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2855 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2856 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2857 }; 2858 static const CostTblEntry AVX1CostTbl[] = { 2859 { ISD::ABS, MVT::v4i64, 5 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2860 { ISD::ABS, MVT::v8i32, 3 }, 2861 { ISD::ABS, MVT::v16i16, 3 }, 2862 { ISD::ABS, MVT::v32i8, 3 }, 2863 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 2864 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 2865 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 2866 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 2867 { ISD::BSWAP, MVT::v4i64, 4 }, 2868 { ISD::BSWAP, MVT::v8i32, 4 }, 2869 { ISD::BSWAP, MVT::v16i16, 4 }, 2870 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 2871 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 2872 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 2873 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2874 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 2875 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 2876 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 2877 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 2878 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 2879 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 2880 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 2881 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2882 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2883 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2884 { ISD::SMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2885 { ISD::SMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2886 { ISD::SMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2887 { ISD::SMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2888 { ISD::SMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2889 { ISD::SMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2890 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2891 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2892 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2893 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2894 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 2895 { ISD::UMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2896 { ISD::UMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2897 { ISD::UMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2898 { ISD::UMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2899 { ISD::UMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2900 { ISD::UMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2901 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2902 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2903 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 2904 { ISD::FMAXNUM, MVT::f32, 3 }, // MAXSS + CMPUNORDSS + BLENDVPS 2905 { ISD::FMAXNUM, MVT::v4f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2906 { ISD::FMAXNUM, MVT::v8f32, 5 }, // MAXPS + CMPUNORDPS + BLENDVPS + ? 2907 { ISD::FMAXNUM, MVT::f64, 3 }, // MAXSD + CMPUNORDSD + BLENDVPD 2908 { ISD::FMAXNUM, MVT::v2f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2909 { ISD::FMAXNUM, MVT::v4f64, 5 }, // MAXPD + CMPUNORDPD + BLENDVPD + ? 2910 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 2911 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 2912 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 2913 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 2914 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 2915 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 2916 }; 2917 static const CostTblEntry GLMCostTbl[] = { 2918 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 2919 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 2920 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 2921 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 2922 }; 2923 static const CostTblEntry SLMCostTbl[] = { 2924 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 2925 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 2926 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 2927 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 2928 }; 2929 static const CostTblEntry SSE42CostTbl[] = { 2930 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 2931 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 2932 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 2933 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 2934 }; 2935 static const CostTblEntry SSE41CostTbl[] = { 2936 { ISD::ABS, MVT::v2i64, 2 }, // BLENDVPD(X,PSUBQ(0,X),X) 2937 { ISD::SMAX, MVT::v4i32, 1 }, 2938 { ISD::SMAX, MVT::v16i8, 1 }, 2939 { ISD::SMIN, MVT::v4i32, 1 }, 2940 { ISD::SMIN, MVT::v16i8, 1 }, 2941 { ISD::UMAX, MVT::v4i32, 1 }, 2942 { ISD::UMAX, MVT::v8i16, 1 }, 2943 { ISD::UMIN, MVT::v4i32, 1 }, 2944 { ISD::UMIN, MVT::v8i16, 1 }, 2945 }; 2946 static const CostTblEntry SSSE3CostTbl[] = { 2947 { ISD::ABS, MVT::v4i32, 1 }, 2948 { ISD::ABS, MVT::v8i16, 1 }, 2949 { ISD::ABS, MVT::v16i8, 1 }, 2950 { ISD::BITREVERSE, MVT::v2i64, 5 }, 2951 { ISD::BITREVERSE, MVT::v4i32, 5 }, 2952 { ISD::BITREVERSE, MVT::v8i16, 5 }, 2953 { ISD::BITREVERSE, MVT::v16i8, 5 }, 2954 { ISD::BSWAP, MVT::v2i64, 1 }, 2955 { ISD::BSWAP, MVT::v4i32, 1 }, 2956 { ISD::BSWAP, MVT::v8i16, 1 }, 2957 { ISD::CTLZ, MVT::v2i64, 23 }, 2958 { ISD::CTLZ, MVT::v4i32, 18 }, 2959 { ISD::CTLZ, MVT::v8i16, 14 }, 2960 { ISD::CTLZ, MVT::v16i8, 9 }, 2961 { ISD::CTPOP, MVT::v2i64, 7 }, 2962 { ISD::CTPOP, MVT::v4i32, 11 }, 2963 { ISD::CTPOP, MVT::v8i16, 9 }, 2964 { ISD::CTPOP, MVT::v16i8, 6 }, 2965 { ISD::CTTZ, MVT::v2i64, 10 }, 2966 { ISD::CTTZ, MVT::v4i32, 14 }, 2967 { ISD::CTTZ, MVT::v8i16, 12 }, 2968 { ISD::CTTZ, MVT::v16i8, 9 } 2969 }; 2970 static const CostTblEntry SSE2CostTbl[] = { 2971 { ISD::ABS, MVT::v2i64, 4 }, 2972 { ISD::ABS, MVT::v4i32, 3 }, 2973 { ISD::ABS, MVT::v8i16, 2 }, 2974 { ISD::ABS, MVT::v16i8, 2 }, 2975 { ISD::BITREVERSE, MVT::v2i64, 29 }, 2976 { ISD::BITREVERSE, MVT::v4i32, 27 }, 2977 { ISD::BITREVERSE, MVT::v8i16, 27 }, 2978 { ISD::BITREVERSE, MVT::v16i8, 20 }, 2979 { ISD::BSWAP, MVT::v2i64, 7 }, 2980 { ISD::BSWAP, MVT::v4i32, 7 }, 2981 { ISD::BSWAP, MVT::v8i16, 7 }, 2982 { ISD::CTLZ, MVT::v2i64, 25 }, 2983 { ISD::CTLZ, MVT::v4i32, 26 }, 2984 { ISD::CTLZ, MVT::v8i16, 20 }, 2985 { ISD::CTLZ, MVT::v16i8, 17 }, 2986 { ISD::CTPOP, MVT::v2i64, 12 }, 2987 { ISD::CTPOP, MVT::v4i32, 15 }, 2988 { ISD::CTPOP, MVT::v8i16, 13 }, 2989 { ISD::CTPOP, MVT::v16i8, 10 }, 2990 { ISD::CTTZ, MVT::v2i64, 14 }, 2991 { ISD::CTTZ, MVT::v4i32, 18 }, 2992 { ISD::CTTZ, MVT::v8i16, 16 }, 2993 { ISD::CTTZ, MVT::v16i8, 13 }, 2994 { ISD::SADDSAT, MVT::v8i16, 1 }, 2995 { ISD::SADDSAT, MVT::v16i8, 1 }, 2996 { ISD::SMAX, MVT::v8i16, 1 }, 2997 { ISD::SMIN, MVT::v8i16, 1 }, 2998 { ISD::SSUBSAT, MVT::v8i16, 1 }, 2999 { ISD::SSUBSAT, MVT::v16i8, 1 }, 3000 { ISD::UADDSAT, MVT::v8i16, 1 }, 3001 { ISD::UADDSAT, MVT::v16i8, 1 }, 3002 { ISD::UMAX, MVT::v8i16, 2 }, 3003 { ISD::UMAX, MVT::v16i8, 1 }, 3004 { ISD::UMIN, MVT::v8i16, 2 }, 3005 { ISD::UMIN, MVT::v16i8, 1 }, 3006 { ISD::USUBSAT, MVT::v8i16, 1 }, 3007 { ISD::USUBSAT, MVT::v16i8, 1 }, 3008 { ISD::FMAXNUM, MVT::f64, 4 }, 3009 { ISD::FMAXNUM, MVT::v2f64, 4 }, 3010 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 3011 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 3012 }; 3013 static const CostTblEntry SSE1CostTbl[] = { 3014 { ISD::FMAXNUM, MVT::f32, 4 }, 3015 { ISD::FMAXNUM, MVT::v4f32, 4 }, 3016 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 3017 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 3018 }; 3019 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 3020 { ISD::CTTZ, MVT::i64, 1 }, 3021 }; 3022 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 3023 { ISD::CTTZ, MVT::i32, 1 }, 3024 { ISD::CTTZ, MVT::i16, 1 }, 3025 { ISD::CTTZ, MVT::i8, 1 }, 3026 }; 3027 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 3028 { ISD::CTLZ, MVT::i64, 1 }, 3029 }; 3030 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 3031 { ISD::CTLZ, MVT::i32, 1 }, 3032 { ISD::CTLZ, MVT::i16, 1 }, 3033 { ISD::CTLZ, MVT::i8, 1 }, 3034 }; 3035 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 3036 { ISD::CTPOP, MVT::i64, 1 }, 3037 }; 3038 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 3039 { ISD::CTPOP, MVT::i32, 1 }, 3040 { ISD::CTPOP, MVT::i16, 1 }, 3041 { ISD::CTPOP, MVT::i8, 1 }, 3042 }; 3043 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 3044 { ISD::ABS, MVT::i64, 2 }, // SUB+CMOV 3045 { ISD::BITREVERSE, MVT::i64, 14 }, 3046 { ISD::BSWAP, MVT::i64, 1 }, 3047 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 3048 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 3049 { ISD::CTPOP, MVT::i64, 10 }, 3050 { ISD::SADDO, MVT::i64, 1 }, 3051 { ISD::UADDO, MVT::i64, 1 }, 3052 { ISD::UMULO, MVT::i64, 2 }, // mulq + seto 3053 }; 3054 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 3055 { ISD::ABS, MVT::i32, 2 }, // SUB+CMOV 3056 { ISD::ABS, MVT::i16, 2 }, // SUB+CMOV 3057 { ISD::BITREVERSE, MVT::i32, 14 }, 3058 { ISD::BITREVERSE, MVT::i16, 14 }, 3059 { ISD::BITREVERSE, MVT::i8, 11 }, 3060 { ISD::BSWAP, MVT::i32, 1 }, 3061 { ISD::BSWAP, MVT::i16, 1 }, // ROL 3062 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 3063 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 3064 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 3065 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 3066 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 3067 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 3068 { ISD::CTPOP, MVT::i32, 8 }, 3069 { ISD::CTPOP, MVT::i16, 9 }, 3070 { ISD::CTPOP, MVT::i8, 7 }, 3071 { ISD::SADDO, MVT::i32, 1 }, 3072 { ISD::SADDO, MVT::i16, 1 }, 3073 { ISD::SADDO, MVT::i8, 1 }, 3074 { ISD::UADDO, MVT::i32, 1 }, 3075 { ISD::UADDO, MVT::i16, 1 }, 3076 { ISD::UADDO, MVT::i8, 1 }, 3077 { ISD::UMULO, MVT::i32, 2 }, // mul + seto 3078 { ISD::UMULO, MVT::i16, 2 }, 3079 { ISD::UMULO, MVT::i8, 2 }, 3080 }; 3081 3082 Type *RetTy = ICA.getReturnType(); 3083 Type *OpTy = RetTy; 3084 Intrinsic::ID IID = ICA.getID(); 3085 unsigned ISD = ISD::DELETED_NODE; 3086 switch (IID) { 3087 default: 3088 break; 3089 case Intrinsic::abs: 3090 ISD = ISD::ABS; 3091 break; 3092 case Intrinsic::bitreverse: 3093 ISD = ISD::BITREVERSE; 3094 break; 3095 case Intrinsic::bswap: 3096 ISD = ISD::BSWAP; 3097 break; 3098 case Intrinsic::ctlz: 3099 ISD = ISD::CTLZ; 3100 break; 3101 case Intrinsic::ctpop: 3102 ISD = ISD::CTPOP; 3103 break; 3104 case Intrinsic::cttz: 3105 ISD = ISD::CTTZ; 3106 break; 3107 case Intrinsic::maxnum: 3108 case Intrinsic::minnum: 3109 // FMINNUM has same costs so don't duplicate. 3110 ISD = ISD::FMAXNUM; 3111 break; 3112 case Intrinsic::sadd_sat: 3113 ISD = ISD::SADDSAT; 3114 break; 3115 case Intrinsic::smax: 3116 ISD = ISD::SMAX; 3117 break; 3118 case Intrinsic::smin: 3119 ISD = ISD::SMIN; 3120 break; 3121 case Intrinsic::ssub_sat: 3122 ISD = ISD::SSUBSAT; 3123 break; 3124 case Intrinsic::uadd_sat: 3125 ISD = ISD::UADDSAT; 3126 break; 3127 case Intrinsic::umax: 3128 ISD = ISD::UMAX; 3129 break; 3130 case Intrinsic::umin: 3131 ISD = ISD::UMIN; 3132 break; 3133 case Intrinsic::usub_sat: 3134 ISD = ISD::USUBSAT; 3135 break; 3136 case Intrinsic::sqrt: 3137 ISD = ISD::FSQRT; 3138 break; 3139 case Intrinsic::sadd_with_overflow: 3140 case Intrinsic::ssub_with_overflow: 3141 // SSUBO has same costs so don't duplicate. 3142 ISD = ISD::SADDO; 3143 OpTy = RetTy->getContainedType(0); 3144 break; 3145 case Intrinsic::uadd_with_overflow: 3146 case Intrinsic::usub_with_overflow: 3147 // USUBO has same costs so don't duplicate. 3148 ISD = ISD::UADDO; 3149 OpTy = RetTy->getContainedType(0); 3150 break; 3151 case Intrinsic::umul_with_overflow: 3152 case Intrinsic::smul_with_overflow: 3153 // SMULO has same costs so don't duplicate. 3154 ISD = ISD::UMULO; 3155 OpTy = RetTy->getContainedType(0); 3156 break; 3157 } 3158 3159 if (ISD != ISD::DELETED_NODE) { 3160 // Legalize the type. 3161 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 3162 MVT MTy = LT.second; 3163 3164 // Attempt to lookup cost. 3165 if (ISD == ISD::BITREVERSE && ST->hasGFNI() && ST->hasSSSE3() && 3166 MTy.isVector()) { 3167 // With PSHUFB the code is very similar for all types. If we have integer 3168 // byte operations, we just need a GF2P8AFFINEQB for vXi8. For other types 3169 // we also need a PSHUFB. 3170 unsigned Cost = MTy.getVectorElementType() == MVT::i8 ? 1 : 2; 3171 3172 // Without byte operations, we need twice as many GF2P8AFFINEQB and PSHUFB 3173 // instructions. We also need an extract and an insert. 3174 if (!(MTy.is128BitVector() || (ST->hasAVX2() && MTy.is256BitVector()) || 3175 (ST->hasBWI() && MTy.is512BitVector()))) 3176 Cost = Cost * 2 + 2; 3177 3178 return LT.first * Cost; 3179 } 3180 3181 auto adjustTableCost = [](const CostTblEntry &Entry, 3182 InstructionCost LegalizationCost, 3183 FastMathFlags FMF) { 3184 // If there are no NANs to deal with, then these are reduced to a 3185 // single MIN** or MAX** instruction instead of the MIN/CMP/SELECT that we 3186 // assume is used in the non-fast case. 3187 if (Entry.ISD == ISD::FMAXNUM || Entry.ISD == ISD::FMINNUM) { 3188 if (FMF.noNaNs()) 3189 return LegalizationCost * 1; 3190 } 3191 return LegalizationCost * (int)Entry.Cost; 3192 }; 3193 3194 if (ST->useGLMDivSqrtCosts()) 3195 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 3196 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3197 3198 if (ST->isSLM()) 3199 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 3200 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3201 3202 if (ST->hasBITALG()) 3203 if (const auto *Entry = CostTableLookup(AVX512BITALGCostTbl, ISD, MTy)) 3204 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3205 3206 if (ST->hasVPOPCNTDQ()) 3207 if (const auto *Entry = CostTableLookup(AVX512VPOPCNTDQCostTbl, ISD, MTy)) 3208 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3209 3210 if (ST->hasCDI()) 3211 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 3212 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3213 3214 if (ST->hasBWI()) 3215 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3216 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3217 3218 if (ST->hasAVX512()) 3219 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3220 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3221 3222 if (ST->hasXOP()) 3223 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3224 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3225 3226 if (ST->hasAVX2()) 3227 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3228 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3229 3230 if (ST->hasAVX()) 3231 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3232 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3233 3234 if (ST->hasSSE42()) 3235 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3236 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3237 3238 if (ST->hasSSE41()) 3239 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3240 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3241 3242 if (ST->hasSSSE3()) 3243 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 3244 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3245 3246 if (ST->hasSSE2()) 3247 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3248 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3249 3250 if (ST->hasSSE1()) 3251 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3252 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3253 3254 if (ST->hasBMI()) { 3255 if (ST->is64Bit()) 3256 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 3257 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3258 3259 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 3260 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3261 } 3262 3263 if (ST->hasLZCNT()) { 3264 if (ST->is64Bit()) 3265 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 3266 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3267 3268 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 3269 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3270 } 3271 3272 if (ST->hasPOPCNT()) { 3273 if (ST->is64Bit()) 3274 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 3275 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3276 3277 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 3278 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3279 } 3280 3281 if (ISD == ISD::BSWAP && ST->hasMOVBE() && ST->hasFastMOVBE()) { 3282 if (const Instruction *II = ICA.getInst()) { 3283 if (II->hasOneUse() && isa<StoreInst>(II->user_back())) 3284 return TTI::TCC_Free; 3285 if (auto *LI = dyn_cast<LoadInst>(II->getOperand(0))) { 3286 if (LI->hasOneUse()) 3287 return TTI::TCC_Free; 3288 } 3289 } 3290 } 3291 3292 // TODO - add BMI (TZCNT) scalar handling 3293 3294 if (ST->is64Bit()) 3295 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3296 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3297 3298 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3299 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3300 } 3301 3302 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3303 } 3304 3305 InstructionCost 3306 X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 3307 TTI::TargetCostKind CostKind) { 3308 if (ICA.isTypeBasedOnly()) 3309 return getTypeBasedIntrinsicInstrCost(ICA, CostKind); 3310 3311 static const CostTblEntry AVX512CostTbl[] = { 3312 { ISD::ROTL, MVT::v8i64, 1 }, 3313 { ISD::ROTL, MVT::v4i64, 1 }, 3314 { ISD::ROTL, MVT::v2i64, 1 }, 3315 { ISD::ROTL, MVT::v16i32, 1 }, 3316 { ISD::ROTL, MVT::v8i32, 1 }, 3317 { ISD::ROTL, MVT::v4i32, 1 }, 3318 { ISD::ROTR, MVT::v8i64, 1 }, 3319 { ISD::ROTR, MVT::v4i64, 1 }, 3320 { ISD::ROTR, MVT::v2i64, 1 }, 3321 { ISD::ROTR, MVT::v16i32, 1 }, 3322 { ISD::ROTR, MVT::v8i32, 1 }, 3323 { ISD::ROTR, MVT::v4i32, 1 } 3324 }; 3325 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 3326 static const CostTblEntry XOPCostTbl[] = { 3327 { ISD::ROTL, MVT::v4i64, 4 }, 3328 { ISD::ROTL, MVT::v8i32, 4 }, 3329 { ISD::ROTL, MVT::v16i16, 4 }, 3330 { ISD::ROTL, MVT::v32i8, 4 }, 3331 { ISD::ROTL, MVT::v2i64, 1 }, 3332 { ISD::ROTL, MVT::v4i32, 1 }, 3333 { ISD::ROTL, MVT::v8i16, 1 }, 3334 { ISD::ROTL, MVT::v16i8, 1 }, 3335 { ISD::ROTR, MVT::v4i64, 6 }, 3336 { ISD::ROTR, MVT::v8i32, 6 }, 3337 { ISD::ROTR, MVT::v16i16, 6 }, 3338 { ISD::ROTR, MVT::v32i8, 6 }, 3339 { ISD::ROTR, MVT::v2i64, 2 }, 3340 { ISD::ROTR, MVT::v4i32, 2 }, 3341 { ISD::ROTR, MVT::v8i16, 2 }, 3342 { ISD::ROTR, MVT::v16i8, 2 } 3343 }; 3344 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 3345 { ISD::ROTL, MVT::i64, 1 }, 3346 { ISD::ROTR, MVT::i64, 1 }, 3347 { ISD::FSHL, MVT::i64, 4 } 3348 }; 3349 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 3350 { ISD::ROTL, MVT::i32, 1 }, 3351 { ISD::ROTL, MVT::i16, 1 }, 3352 { ISD::ROTL, MVT::i8, 1 }, 3353 { ISD::ROTR, MVT::i32, 1 }, 3354 { ISD::ROTR, MVT::i16, 1 }, 3355 { ISD::ROTR, MVT::i8, 1 }, 3356 { ISD::FSHL, MVT::i32, 4 }, 3357 { ISD::FSHL, MVT::i16, 4 }, 3358 { ISD::FSHL, MVT::i8, 4 } 3359 }; 3360 3361 Intrinsic::ID IID = ICA.getID(); 3362 Type *RetTy = ICA.getReturnType(); 3363 const SmallVectorImpl<const Value *> &Args = ICA.getArgs(); 3364 unsigned ISD = ISD::DELETED_NODE; 3365 switch (IID) { 3366 default: 3367 break; 3368 case Intrinsic::fshl: 3369 ISD = ISD::FSHL; 3370 if (Args[0] == Args[1]) 3371 ISD = ISD::ROTL; 3372 break; 3373 case Intrinsic::fshr: 3374 // FSHR has same costs so don't duplicate. 3375 ISD = ISD::FSHL; 3376 if (Args[0] == Args[1]) 3377 ISD = ISD::ROTR; 3378 break; 3379 } 3380 3381 if (ISD != ISD::DELETED_NODE) { 3382 // Legalize the type. 3383 std::pair<InstructionCost, MVT> LT = 3384 TLI->getTypeLegalizationCost(DL, RetTy); 3385 MVT MTy = LT.second; 3386 3387 // Attempt to lookup cost. 3388 if (ST->hasAVX512()) 3389 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3390 return LT.first * Entry->Cost; 3391 3392 if (ST->hasXOP()) 3393 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3394 return LT.first * Entry->Cost; 3395 3396 if (ST->is64Bit()) 3397 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3398 return LT.first * Entry->Cost; 3399 3400 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3401 return LT.first * Entry->Cost; 3402 } 3403 3404 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3405 } 3406 3407 InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, 3408 unsigned Index) { 3409 static const CostTblEntry SLMCostTbl[] = { 3410 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 3411 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 3412 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 3413 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 3414 }; 3415 3416 assert(Val->isVectorTy() && "This must be a vector type"); 3417 Type *ScalarType = Val->getScalarType(); 3418 int RegisterFileMoveCost = 0; 3419 3420 // Non-immediate extraction/insertion can be handled as a sequence of 3421 // aliased loads+stores via the stack. 3422 if (Index == -1U && (Opcode == Instruction::ExtractElement || 3423 Opcode == Instruction::InsertElement)) { 3424 // TODO: On some SSE41+ targets, we expand to cmp+splat+select patterns: 3425 // inselt N0, N1, N2 --> select (SplatN2 == {0,1,2...}) ? SplatN1 : N0. 3426 3427 // TODO: Move this to BasicTTIImpl.h? We'd need better gep + index handling. 3428 assert(isa<FixedVectorType>(Val) && "Fixed vector type expected"); 3429 Align VecAlign = DL.getPrefTypeAlign(Val); 3430 Align SclAlign = DL.getPrefTypeAlign(ScalarType); 3431 3432 // Extract - store vector to stack, load scalar. 3433 if (Opcode == Instruction::ExtractElement) { 3434 return getMemoryOpCost(Instruction::Store, Val, VecAlign, 0, 3435 TTI::TargetCostKind::TCK_RecipThroughput) + 3436 getMemoryOpCost(Instruction::Load, ScalarType, SclAlign, 0, 3437 TTI::TargetCostKind::TCK_RecipThroughput); 3438 } 3439 // Insert - store vector to stack, store scalar, load vector. 3440 if (Opcode == Instruction::InsertElement) { 3441 return getMemoryOpCost(Instruction::Store, Val, VecAlign, 0, 3442 TTI::TargetCostKind::TCK_RecipThroughput) + 3443 getMemoryOpCost(Instruction::Store, ScalarType, SclAlign, 0, 3444 TTI::TargetCostKind::TCK_RecipThroughput) + 3445 getMemoryOpCost(Instruction::Load, Val, VecAlign, 0, 3446 TTI::TargetCostKind::TCK_RecipThroughput); 3447 } 3448 } 3449 3450 if (Index != -1U && (Opcode == Instruction::ExtractElement || 3451 Opcode == Instruction::InsertElement)) { 3452 // Legalize the type. 3453 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 3454 3455 // This type is legalized to a scalar type. 3456 if (!LT.second.isVector()) 3457 return 0; 3458 3459 // The type may be split. Normalize the index to the new type. 3460 unsigned NumElts = LT.second.getVectorNumElements(); 3461 unsigned SubNumElts = NumElts; 3462 Index = Index % NumElts; 3463 3464 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 3465 // For inserts, we also need to insert the subvector back. 3466 if (LT.second.getSizeInBits() > 128) { 3467 assert((LT.second.getSizeInBits() % 128) == 0 && "Illegal vector"); 3468 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 3469 SubNumElts = NumElts / NumSubVecs; 3470 if (SubNumElts <= Index) { 3471 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 3472 Index %= SubNumElts; 3473 } 3474 } 3475 3476 if (Index == 0) { 3477 // Floating point scalars are already located in index #0. 3478 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 3479 // true for all. 3480 if (ScalarType->isFloatingPointTy()) 3481 return RegisterFileMoveCost; 3482 3483 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 3484 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 3485 return 1 + RegisterFileMoveCost; 3486 } 3487 3488 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3489 assert(ISD && "Unexpected vector opcode"); 3490 MVT MScalarTy = LT.second.getScalarType(); 3491 if (ST->isSLM()) 3492 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 3493 return Entry->Cost + RegisterFileMoveCost; 3494 3495 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 3496 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3497 (MScalarTy.isInteger() && ST->hasSSE41())) 3498 return 1 + RegisterFileMoveCost; 3499 3500 // Assume insertps is relatively cheap on all targets. 3501 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 3502 Opcode == Instruction::InsertElement) 3503 return 1 + RegisterFileMoveCost; 3504 3505 // For extractions we just need to shuffle the element to index 0, which 3506 // should be very cheap (assume cost = 1). For insertions we need to shuffle 3507 // the elements to its destination. In both cases we must handle the 3508 // subvector move(s). 3509 // If the vector type is already less than 128-bits then don't reduce it. 3510 // TODO: Under what circumstances should we shuffle using the full width? 3511 InstructionCost ShuffleCost = 1; 3512 if (Opcode == Instruction::InsertElement) { 3513 auto *SubTy = cast<VectorType>(Val); 3514 EVT VT = TLI->getValueType(DL, Val); 3515 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 3516 SubTy = FixedVectorType::get(ScalarType, SubNumElts); 3517 ShuffleCost = 3518 getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, None, 0, SubTy); 3519 } 3520 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 3521 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 3522 } 3523 3524 // Add to the base cost if we know that the extracted element of a vector is 3525 // destined to be moved to and used in the integer register file. 3526 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 3527 RegisterFileMoveCost += 1; 3528 3529 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 3530 } 3531 3532 InstructionCost X86TTIImpl::getScalarizationOverhead(VectorType *Ty, 3533 const APInt &DemandedElts, 3534 bool Insert, 3535 bool Extract) { 3536 InstructionCost Cost = 0; 3537 3538 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much 3539 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT. 3540 if (Insert) { 3541 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3542 MVT MScalarTy = LT.second.getScalarType(); 3543 3544 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3545 (MScalarTy.isInteger() && ST->hasSSE41()) || 3546 (MScalarTy == MVT::f32 && ST->hasSSE41())) { 3547 // For types we can insert directly, insertion into 128-bit sub vectors is 3548 // cheap, followed by a cheap chain of concatenations. 3549 if (LT.second.getSizeInBits() <= 128) { 3550 Cost += 3551 BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, false); 3552 } else { 3553 // In each 128-lane, if at least one index is demanded but not all 3554 // indices are demanded and this 128-lane is not the first 128-lane of 3555 // the legalized-vector, then this 128-lane needs a extracti128; If in 3556 // each 128-lane, there is at least one demanded index, this 128-lane 3557 // needs a inserti128. 3558 3559 // The following cases will help you build a better understanding: 3560 // Assume we insert several elements into a v8i32 vector in avx2, 3561 // Case#1: inserting into 1th index needs vpinsrd + inserti128. 3562 // Case#2: inserting into 5th index needs extracti128 + vpinsrd + 3563 // inserti128. 3564 // Case#3: inserting into 4,5,6,7 index needs 4*vpinsrd + inserti128. 3565 const int CostValue = *LT.first.getValue(); 3566 assert(CostValue >= 0 && "Negative cost!"); 3567 unsigned Num128Lanes = LT.second.getSizeInBits() / 128 * CostValue; 3568 unsigned NumElts = LT.second.getVectorNumElements() * CostValue; 3569 APInt WidenedDemandedElts = DemandedElts.zextOrSelf(NumElts); 3570 unsigned Scale = NumElts / Num128Lanes; 3571 // We iterate each 128-lane, and check if we need a 3572 // extracti128/inserti128 for this 128-lane. 3573 for (unsigned I = 0; I < NumElts; I += Scale) { 3574 APInt Mask = WidenedDemandedElts.getBitsSet(NumElts, I, I + Scale); 3575 APInt MaskedDE = Mask & WidenedDemandedElts; 3576 unsigned Population = MaskedDE.countPopulation(); 3577 Cost += (Population > 0 && Population != Scale && 3578 I % LT.second.getVectorNumElements() != 0); 3579 Cost += Population > 0; 3580 } 3581 Cost += DemandedElts.countPopulation(); 3582 3583 // For vXf32 cases, insertion into the 0'th index in each v4f32 3584 // 128-bit vector is free. 3585 // NOTE: This assumes legalization widens vXf32 vectors. 3586 if (MScalarTy == MVT::f32) 3587 for (unsigned i = 0, e = cast<FixedVectorType>(Ty)->getNumElements(); 3588 i < e; i += 4) 3589 if (DemandedElts[i]) 3590 Cost--; 3591 } 3592 } else if (LT.second.isVector()) { 3593 // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded 3594 // integer element as a SCALAR_TO_VECTOR, then we build the vector as a 3595 // series of UNPCK followed by CONCAT_VECTORS - all of these can be 3596 // considered cheap. 3597 if (Ty->isIntOrIntVectorTy()) 3598 Cost += DemandedElts.countPopulation(); 3599 3600 // Get the smaller of the legalized or original pow2-extended number of 3601 // vector elements, which represents the number of unpacks we'll end up 3602 // performing. 3603 unsigned NumElts = LT.second.getVectorNumElements(); 3604 unsigned Pow2Elts = 3605 PowerOf2Ceil(cast<FixedVectorType>(Ty)->getNumElements()); 3606 Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first; 3607 } 3608 } 3609 3610 // TODO: Use default extraction for now, but we should investigate extending this 3611 // to handle repeated subvector extraction. 3612 if (Extract) 3613 Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, false, Extract); 3614 3615 return Cost; 3616 } 3617 3618 InstructionCost X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 3619 MaybeAlign Alignment, 3620 unsigned AddressSpace, 3621 TTI::TargetCostKind CostKind, 3622 const Instruction *I) { 3623 // TODO: Handle other cost kinds. 3624 if (CostKind != TTI::TCK_RecipThroughput) { 3625 if (auto *SI = dyn_cast_or_null<StoreInst>(I)) { 3626 // Store instruction with index and scale costs 2 Uops. 3627 // Check the preceding GEP to identify non-const indices. 3628 if (auto *GEP = dyn_cast<GetElementPtrInst>(SI->getPointerOperand())) { 3629 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3630 return TTI::TCC_Basic * 2; 3631 } 3632 } 3633 return TTI::TCC_Basic; 3634 } 3635 3636 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 3637 "Invalid Opcode"); 3638 // Type legalization can't handle structs 3639 if (TLI->getValueType(DL, Src, true) == MVT::Other) 3640 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3641 CostKind); 3642 3643 // Legalize the type. 3644 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 3645 3646 auto *VTy = dyn_cast<FixedVectorType>(Src); 3647 3648 // Handle the simple case of non-vectors. 3649 // NOTE: this assumes that legalization never creates vector from scalars! 3650 if (!VTy || !LT.second.isVector()) 3651 // Each load/store unit costs 1. 3652 return LT.first * 1; 3653 3654 bool IsLoad = Opcode == Instruction::Load; 3655 3656 Type *EltTy = VTy->getElementType(); 3657 3658 const int EltTyBits = DL.getTypeSizeInBits(EltTy); 3659 3660 InstructionCost Cost = 0; 3661 3662 // Source of truth: how many elements were there in the original IR vector? 3663 const unsigned SrcNumElt = VTy->getNumElements(); 3664 3665 // How far have we gotten? 3666 int NumEltRemaining = SrcNumElt; 3667 // Note that we intentionally capture by-reference, NumEltRemaining changes. 3668 auto NumEltDone = [&]() { return SrcNumElt - NumEltRemaining; }; 3669 3670 const int MaxLegalOpSizeBytes = divideCeil(LT.second.getSizeInBits(), 8); 3671 3672 // Note that even if we can store 64 bits of an XMM, we still operate on XMM. 3673 const unsigned XMMBits = 128; 3674 if (XMMBits % EltTyBits != 0) 3675 // Vector size must be a multiple of the element size. I.e. no padding. 3676 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3677 CostKind); 3678 const int NumEltPerXMM = XMMBits / EltTyBits; 3679 3680 auto *XMMVecTy = FixedVectorType::get(EltTy, NumEltPerXMM); 3681 3682 for (int CurrOpSizeBytes = MaxLegalOpSizeBytes, SubVecEltsLeft = 0; 3683 NumEltRemaining > 0; CurrOpSizeBytes /= 2) { 3684 // How many elements would a single op deal with at once? 3685 if ((8 * CurrOpSizeBytes) % EltTyBits != 0) 3686 // Vector size must be a multiple of the element size. I.e. no padding. 3687 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3688 CostKind); 3689 int CurrNumEltPerOp = (8 * CurrOpSizeBytes) / EltTyBits; 3690 3691 assert(CurrOpSizeBytes > 0 && CurrNumEltPerOp > 0 && "How'd we get here?"); 3692 assert((((NumEltRemaining * EltTyBits) < (2 * 8 * CurrOpSizeBytes)) || 3693 (CurrOpSizeBytes == MaxLegalOpSizeBytes)) && 3694 "Unless we haven't halved the op size yet, " 3695 "we have less than two op's sized units of work left."); 3696 3697 auto *CurrVecTy = CurrNumEltPerOp > NumEltPerXMM 3698 ? FixedVectorType::get(EltTy, CurrNumEltPerOp) 3699 : XMMVecTy; 3700 3701 assert(CurrVecTy->getNumElements() % CurrNumEltPerOp == 0 && 3702 "After halving sizes, the vector elt count is no longer a multiple " 3703 "of number of elements per operation?"); 3704 auto *CoalescedVecTy = 3705 CurrNumEltPerOp == 1 3706 ? CurrVecTy 3707 : FixedVectorType::get( 3708 IntegerType::get(Src->getContext(), 3709 EltTyBits * CurrNumEltPerOp), 3710 CurrVecTy->getNumElements() / CurrNumEltPerOp); 3711 assert(DL.getTypeSizeInBits(CoalescedVecTy) == 3712 DL.getTypeSizeInBits(CurrVecTy) && 3713 "coalesciing elements doesn't change vector width."); 3714 3715 while (NumEltRemaining > 0) { 3716 assert(SubVecEltsLeft >= 0 && "Subreg element count overconsumtion?"); 3717 3718 // Can we use this vector size, as per the remaining element count? 3719 // Iff the vector is naturally aligned, we can do a wide load regardless. 3720 if (NumEltRemaining < CurrNumEltPerOp && 3721 (!IsLoad || Alignment.valueOrOne() < CurrOpSizeBytes) && 3722 CurrOpSizeBytes != 1) 3723 break; // Try smalled vector size. 3724 3725 bool Is0thSubVec = (NumEltDone() % LT.second.getVectorNumElements()) == 0; 3726 3727 // If we have fully processed the previous reg, we need to replenish it. 3728 if (SubVecEltsLeft == 0) { 3729 SubVecEltsLeft += CurrVecTy->getNumElements(); 3730 // And that's free only for the 0'th subvector of a legalized vector. 3731 if (!Is0thSubVec) 3732 Cost += getShuffleCost(IsLoad ? TTI::ShuffleKind::SK_InsertSubvector 3733 : TTI::ShuffleKind::SK_ExtractSubvector, 3734 VTy, None, NumEltDone(), CurrVecTy); 3735 } 3736 3737 // While we can directly load/store ZMM, YMM, and 64-bit halves of XMM, 3738 // for smaller widths (32/16/8) we have to insert/extract them separately. 3739 // Again, it's free for the 0'th subreg (if op is 32/64 bit wide, 3740 // but let's pretend that it is also true for 16/8 bit wide ops...) 3741 if (CurrOpSizeBytes <= 32 / 8 && !Is0thSubVec) { 3742 int NumEltDoneInCurrXMM = NumEltDone() % NumEltPerXMM; 3743 assert(NumEltDoneInCurrXMM % CurrNumEltPerOp == 0 && ""); 3744 int CoalescedVecEltIdx = NumEltDoneInCurrXMM / CurrNumEltPerOp; 3745 APInt DemandedElts = 3746 APInt::getBitsSet(CoalescedVecTy->getNumElements(), 3747 CoalescedVecEltIdx, CoalescedVecEltIdx + 1); 3748 assert(DemandedElts.countPopulation() == 1 && "Inserting single value"); 3749 Cost += getScalarizationOverhead(CoalescedVecTy, DemandedElts, IsLoad, 3750 !IsLoad); 3751 } 3752 3753 // This isn't exactly right. We're using slow unaligned 32-byte accesses 3754 // as a proxy for a double-pumped AVX memory interface such as on 3755 // Sandybridge. 3756 if (CurrOpSizeBytes == 32 && ST->isUnalignedMem32Slow()) 3757 Cost += 2; 3758 else 3759 Cost += 1; 3760 3761 SubVecEltsLeft -= CurrNumEltPerOp; 3762 NumEltRemaining -= CurrNumEltPerOp; 3763 Alignment = commonAlignment(Alignment.valueOrOne(), CurrOpSizeBytes); 3764 } 3765 } 3766 3767 assert(NumEltRemaining <= 0 && "Should have processed all the elements."); 3768 3769 return Cost; 3770 } 3771 3772 InstructionCost 3773 X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, Align Alignment, 3774 unsigned AddressSpace, 3775 TTI::TargetCostKind CostKind) { 3776 bool IsLoad = (Instruction::Load == Opcode); 3777 bool IsStore = (Instruction::Store == Opcode); 3778 3779 auto *SrcVTy = dyn_cast<FixedVectorType>(SrcTy); 3780 if (!SrcVTy) 3781 // To calculate scalar take the regular cost, without mask 3782 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace, CostKind); 3783 3784 unsigned NumElem = SrcVTy->getNumElements(); 3785 auto *MaskTy = 3786 FixedVectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 3787 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, Alignment)) || 3788 (IsStore && !isLegalMaskedStore(SrcVTy, Alignment))) { 3789 // Scalarization 3790 APInt DemandedElts = APInt::getAllOnes(NumElem); 3791 InstructionCost MaskSplitCost = 3792 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 3793 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 3794 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr, 3795 CmpInst::BAD_ICMP_PREDICATE, CostKind); 3796 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 3797 InstructionCost MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 3798 InstructionCost ValueSplitCost = 3799 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore); 3800 InstructionCost MemopCost = 3801 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3802 Alignment, AddressSpace, CostKind); 3803 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 3804 } 3805 3806 // Legalize the type. 3807 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3808 auto VT = TLI->getValueType(DL, SrcVTy); 3809 InstructionCost Cost = 0; 3810 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 3811 LT.second.getVectorNumElements() == NumElem) 3812 // Promotion requires extend/truncate for data and a shuffle for mask. 3813 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, None, 0, nullptr) + 3814 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, None, 0, nullptr); 3815 3816 else if (LT.first * LT.second.getVectorNumElements() > NumElem) { 3817 auto *NewMaskTy = FixedVectorType::get(MaskTy->getElementType(), 3818 LT.second.getVectorNumElements()); 3819 // Expanding requires fill mask with zeroes 3820 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, None, 0, MaskTy); 3821 } 3822 3823 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 3824 if (!ST->hasAVX512()) 3825 return Cost + LT.first * (IsLoad ? 2 : 8); 3826 3827 // AVX-512 masked load/store is cheapper 3828 return Cost + LT.first; 3829 } 3830 3831 InstructionCost X86TTIImpl::getAddressComputationCost(Type *Ty, 3832 ScalarEvolution *SE, 3833 const SCEV *Ptr) { 3834 // Address computations in vectorized code with non-consecutive addresses will 3835 // likely result in more instructions compared to scalar code where the 3836 // computation can more often be merged into the index mode. The resulting 3837 // extra micro-ops can significantly decrease throughput. 3838 const unsigned NumVectorInstToHideOverhead = 10; 3839 3840 // Cost modeling of Strided Access Computation is hidden by the indexing 3841 // modes of X86 regardless of the stride value. We dont believe that there 3842 // is a difference between constant strided access in gerenal and constant 3843 // strided value which is less than or equal to 64. 3844 // Even in the case of (loop invariant) stride whose value is not known at 3845 // compile time, the address computation will not incur more than one extra 3846 // ADD instruction. 3847 if (Ty->isVectorTy() && SE) { 3848 if (!BaseT::isStridedAccess(Ptr)) 3849 return NumVectorInstToHideOverhead; 3850 if (!BaseT::getConstantStrideStep(SE, Ptr)) 3851 return 1; 3852 } 3853 3854 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 3855 } 3856 3857 InstructionCost 3858 X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 3859 Optional<FastMathFlags> FMF, 3860 TTI::TargetCostKind CostKind) { 3861 if (TTI::requiresOrderedReduction(FMF)) 3862 return BaseT::getArithmeticReductionCost(Opcode, ValTy, FMF, CostKind); 3863 3864 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3865 // and make it as the cost. 3866 3867 static const CostTblEntry SLMCostTblNoPairWise[] = { 3868 { ISD::FADD, MVT::v2f64, 3 }, 3869 { ISD::ADD, MVT::v2i64, 5 }, 3870 }; 3871 3872 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3873 { ISD::FADD, MVT::v2f64, 2 }, 3874 { ISD::FADD, MVT::v2f32, 2 }, 3875 { ISD::FADD, MVT::v4f32, 4 }, 3876 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 3877 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 3878 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 3879 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 3880 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 3881 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 3882 { ISD::ADD, MVT::v2i8, 2 }, 3883 { ISD::ADD, MVT::v4i8, 2 }, 3884 { ISD::ADD, MVT::v8i8, 2 }, 3885 { ISD::ADD, MVT::v16i8, 3 }, 3886 }; 3887 3888 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3889 { ISD::FADD, MVT::v4f64, 3 }, 3890 { ISD::FADD, MVT::v4f32, 3 }, 3891 { ISD::FADD, MVT::v8f32, 4 }, 3892 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 3893 { ISD::ADD, MVT::v4i64, 3 }, 3894 { ISD::ADD, MVT::v8i32, 5 }, 3895 { ISD::ADD, MVT::v16i16, 5 }, 3896 { ISD::ADD, MVT::v32i8, 4 }, 3897 }; 3898 3899 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3900 assert(ISD && "Invalid opcode"); 3901 3902 // Before legalizing the type, give a chance to look up illegal narrow types 3903 // in the table. 3904 // FIXME: Is there a better way to do this? 3905 EVT VT = TLI->getValueType(DL, ValTy); 3906 if (VT.isSimple()) { 3907 MVT MTy = VT.getSimpleVT(); 3908 if (ST->isSLM()) 3909 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3910 return Entry->Cost; 3911 3912 if (ST->hasAVX()) 3913 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3914 return Entry->Cost; 3915 3916 if (ST->hasSSE2()) 3917 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3918 return Entry->Cost; 3919 } 3920 3921 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3922 3923 MVT MTy = LT.second; 3924 3925 auto *ValVTy = cast<FixedVectorType>(ValTy); 3926 3927 // Special case: vXi8 mul reductions are performed as vXi16. 3928 if (ISD == ISD::MUL && MTy.getScalarType() == MVT::i8) { 3929 auto *WideSclTy = IntegerType::get(ValVTy->getContext(), 16); 3930 auto *WideVecTy = FixedVectorType::get(WideSclTy, ValVTy->getNumElements()); 3931 return getCastInstrCost(Instruction::ZExt, WideVecTy, ValTy, 3932 TargetTransformInfo::CastContextHint::None, 3933 CostKind) + 3934 getArithmeticReductionCost(Opcode, WideVecTy, FMF, CostKind); 3935 } 3936 3937 InstructionCost ArithmeticCost = 0; 3938 if (LT.first != 1 && MTy.isVector() && 3939 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3940 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3941 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3942 MTy.getVectorNumElements()); 3943 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3944 ArithmeticCost *= LT.first - 1; 3945 } 3946 3947 if (ST->isSLM()) 3948 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3949 return ArithmeticCost + Entry->Cost; 3950 3951 if (ST->hasAVX()) 3952 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3953 return ArithmeticCost + Entry->Cost; 3954 3955 if (ST->hasSSE2()) 3956 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3957 return ArithmeticCost + Entry->Cost; 3958 3959 // FIXME: These assume a naive kshift+binop lowering, which is probably 3960 // conservative in most cases. 3961 static const CostTblEntry AVX512BoolReduction[] = { 3962 { ISD::AND, MVT::v2i1, 3 }, 3963 { ISD::AND, MVT::v4i1, 5 }, 3964 { ISD::AND, MVT::v8i1, 7 }, 3965 { ISD::AND, MVT::v16i1, 9 }, 3966 { ISD::AND, MVT::v32i1, 11 }, 3967 { ISD::AND, MVT::v64i1, 13 }, 3968 { ISD::OR, MVT::v2i1, 3 }, 3969 { ISD::OR, MVT::v4i1, 5 }, 3970 { ISD::OR, MVT::v8i1, 7 }, 3971 { ISD::OR, MVT::v16i1, 9 }, 3972 { ISD::OR, MVT::v32i1, 11 }, 3973 { ISD::OR, MVT::v64i1, 13 }, 3974 }; 3975 3976 static const CostTblEntry AVX2BoolReduction[] = { 3977 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 3978 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 3979 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 3980 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 3981 }; 3982 3983 static const CostTblEntry AVX1BoolReduction[] = { 3984 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 3985 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 3986 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3987 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3988 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 3989 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 3990 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3991 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3992 }; 3993 3994 static const CostTblEntry SSE2BoolReduction[] = { 3995 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 3996 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 3997 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 3998 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 3999 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 4000 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 4001 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 4002 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 4003 }; 4004 4005 // Handle bool allof/anyof patterns. 4006 if (ValVTy->getElementType()->isIntegerTy(1)) { 4007 InstructionCost ArithmeticCost = 0; 4008 if (LT.first != 1 && MTy.isVector() && 4009 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4010 // Type needs to be split. We need LT.first - 1 arithmetic ops. 4011 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 4012 MTy.getVectorNumElements()); 4013 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 4014 ArithmeticCost *= LT.first - 1; 4015 } 4016 4017 if (ST->hasAVX512()) 4018 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 4019 return ArithmeticCost + Entry->Cost; 4020 if (ST->hasAVX2()) 4021 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 4022 return ArithmeticCost + Entry->Cost; 4023 if (ST->hasAVX()) 4024 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 4025 return ArithmeticCost + Entry->Cost; 4026 if (ST->hasSSE2()) 4027 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 4028 return ArithmeticCost + Entry->Cost; 4029 4030 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, FMF, CostKind); 4031 } 4032 4033 unsigned NumVecElts = ValVTy->getNumElements(); 4034 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 4035 4036 // Special case power of 2 reductions where the scalar type isn't changed 4037 // by type legalization. 4038 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 4039 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, FMF, CostKind); 4040 4041 InstructionCost ReductionCost = 0; 4042 4043 auto *Ty = ValVTy; 4044 if (LT.first != 1 && MTy.isVector() && 4045 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4046 // Type needs to be split. We need LT.first - 1 arithmetic ops. 4047 Ty = FixedVectorType::get(ValVTy->getElementType(), 4048 MTy.getVectorNumElements()); 4049 ReductionCost = getArithmeticInstrCost(Opcode, Ty, CostKind); 4050 ReductionCost *= LT.first - 1; 4051 NumVecElts = MTy.getVectorNumElements(); 4052 } 4053 4054 // Now handle reduction with the legal type, taking into account size changes 4055 // at each level. 4056 while (NumVecElts > 1) { 4057 // Determine the size of the remaining vector we need to reduce. 4058 unsigned Size = NumVecElts * ScalarSize; 4059 NumVecElts /= 2; 4060 // If we're reducing from 256/512 bits, use an extract_subvector. 4061 if (Size > 128) { 4062 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 4063 ReductionCost += 4064 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 4065 Ty = SubTy; 4066 } else if (Size == 128) { 4067 // Reducing from 128 bits is a permute of v2f64/v2i64. 4068 FixedVectorType *ShufTy; 4069 if (ValVTy->isFloatingPointTy()) 4070 ShufTy = 4071 FixedVectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 4072 else 4073 ShufTy = 4074 FixedVectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 4075 ReductionCost += 4076 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4077 } else if (Size == 64) { 4078 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 4079 FixedVectorType *ShufTy; 4080 if (ValVTy->isFloatingPointTy()) 4081 ShufTy = 4082 FixedVectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 4083 else 4084 ShufTy = 4085 FixedVectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 4086 ReductionCost += 4087 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4088 } else { 4089 // Reducing from smaller size is a shift by immediate. 4090 auto *ShiftTy = FixedVectorType::get( 4091 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 4092 ReductionCost += getArithmeticInstrCost( 4093 Instruction::LShr, ShiftTy, CostKind, 4094 TargetTransformInfo::OK_AnyValue, 4095 TargetTransformInfo::OK_UniformConstantValue, 4096 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 4097 } 4098 4099 // Add the arithmetic op for this level. 4100 ReductionCost += getArithmeticInstrCost(Opcode, Ty, CostKind); 4101 } 4102 4103 // Add the final extract element to the cost. 4104 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 4105 } 4106 4107 InstructionCost X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, 4108 bool IsUnsigned) { 4109 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 4110 4111 MVT MTy = LT.second; 4112 4113 int ISD; 4114 if (Ty->isIntOrIntVectorTy()) { 4115 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 4116 } else { 4117 assert(Ty->isFPOrFPVectorTy() && 4118 "Expected float point or integer vector type."); 4119 ISD = ISD::FMINNUM; 4120 } 4121 4122 static const CostTblEntry SSE1CostTbl[] = { 4123 {ISD::FMINNUM, MVT::v4f32, 1}, 4124 }; 4125 4126 static const CostTblEntry SSE2CostTbl[] = { 4127 {ISD::FMINNUM, MVT::v2f64, 1}, 4128 {ISD::SMIN, MVT::v8i16, 1}, 4129 {ISD::UMIN, MVT::v16i8, 1}, 4130 }; 4131 4132 static const CostTblEntry SSE41CostTbl[] = { 4133 {ISD::SMIN, MVT::v4i32, 1}, 4134 {ISD::UMIN, MVT::v4i32, 1}, 4135 {ISD::UMIN, MVT::v8i16, 1}, 4136 {ISD::SMIN, MVT::v16i8, 1}, 4137 }; 4138 4139 static const CostTblEntry SSE42CostTbl[] = { 4140 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 4141 }; 4142 4143 static const CostTblEntry AVX1CostTbl[] = { 4144 {ISD::FMINNUM, MVT::v8f32, 1}, 4145 {ISD::FMINNUM, MVT::v4f64, 1}, 4146 {ISD::SMIN, MVT::v8i32, 3}, 4147 {ISD::UMIN, MVT::v8i32, 3}, 4148 {ISD::SMIN, MVT::v16i16, 3}, 4149 {ISD::UMIN, MVT::v16i16, 3}, 4150 {ISD::SMIN, MVT::v32i8, 3}, 4151 {ISD::UMIN, MVT::v32i8, 3}, 4152 }; 4153 4154 static const CostTblEntry AVX2CostTbl[] = { 4155 {ISD::SMIN, MVT::v8i32, 1}, 4156 {ISD::UMIN, MVT::v8i32, 1}, 4157 {ISD::SMIN, MVT::v16i16, 1}, 4158 {ISD::UMIN, MVT::v16i16, 1}, 4159 {ISD::SMIN, MVT::v32i8, 1}, 4160 {ISD::UMIN, MVT::v32i8, 1}, 4161 }; 4162 4163 static const CostTblEntry AVX512CostTbl[] = { 4164 {ISD::FMINNUM, MVT::v16f32, 1}, 4165 {ISD::FMINNUM, MVT::v8f64, 1}, 4166 {ISD::SMIN, MVT::v2i64, 1}, 4167 {ISD::UMIN, MVT::v2i64, 1}, 4168 {ISD::SMIN, MVT::v4i64, 1}, 4169 {ISD::UMIN, MVT::v4i64, 1}, 4170 {ISD::SMIN, MVT::v8i64, 1}, 4171 {ISD::UMIN, MVT::v8i64, 1}, 4172 {ISD::SMIN, MVT::v16i32, 1}, 4173 {ISD::UMIN, MVT::v16i32, 1}, 4174 }; 4175 4176 static const CostTblEntry AVX512BWCostTbl[] = { 4177 {ISD::SMIN, MVT::v32i16, 1}, 4178 {ISD::UMIN, MVT::v32i16, 1}, 4179 {ISD::SMIN, MVT::v64i8, 1}, 4180 {ISD::UMIN, MVT::v64i8, 1}, 4181 }; 4182 4183 // If we have a native MIN/MAX instruction for this type, use it. 4184 if (ST->hasBWI()) 4185 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 4186 return LT.first * Entry->Cost; 4187 4188 if (ST->hasAVX512()) 4189 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 4190 return LT.first * Entry->Cost; 4191 4192 if (ST->hasAVX2()) 4193 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 4194 return LT.first * Entry->Cost; 4195 4196 if (ST->hasAVX()) 4197 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 4198 return LT.first * Entry->Cost; 4199 4200 if (ST->hasSSE42()) 4201 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 4202 return LT.first * Entry->Cost; 4203 4204 if (ST->hasSSE41()) 4205 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 4206 return LT.first * Entry->Cost; 4207 4208 if (ST->hasSSE2()) 4209 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 4210 return LT.first * Entry->Cost; 4211 4212 if (ST->hasSSE1()) 4213 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 4214 return LT.first * Entry->Cost; 4215 4216 unsigned CmpOpcode; 4217 if (Ty->isFPOrFPVectorTy()) { 4218 CmpOpcode = Instruction::FCmp; 4219 } else { 4220 assert(Ty->isIntOrIntVectorTy() && 4221 "expecting floating point or integer type for min/max reduction"); 4222 CmpOpcode = Instruction::ICmp; 4223 } 4224 4225 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4226 // Otherwise fall back to cmp+select. 4227 InstructionCost Result = 4228 getCmpSelInstrCost(CmpOpcode, Ty, CondTy, CmpInst::BAD_ICMP_PREDICATE, 4229 CostKind) + 4230 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, 4231 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4232 return Result; 4233 } 4234 4235 InstructionCost 4236 X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 4237 bool IsUnsigned, 4238 TTI::TargetCostKind CostKind) { 4239 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 4240 4241 MVT MTy = LT.second; 4242 4243 int ISD; 4244 if (ValTy->isIntOrIntVectorTy()) { 4245 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 4246 } else { 4247 assert(ValTy->isFPOrFPVectorTy() && 4248 "Expected float point or integer vector type."); 4249 ISD = ISD::FMINNUM; 4250 } 4251 4252 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 4253 // and make it as the cost. 4254 4255 static const CostTblEntry SSE2CostTblNoPairWise[] = { 4256 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 4257 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 4258 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 4259 }; 4260 4261 static const CostTblEntry SSE41CostTblNoPairWise[] = { 4262 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 4263 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 4264 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 4265 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 4266 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 4267 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 4268 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 4269 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 4270 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 4271 {ISD::SMIN, MVT::v16i8, 6}, 4272 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 4273 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 4274 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 4275 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 4276 }; 4277 4278 static const CostTblEntry AVX1CostTblNoPairWise[] = { 4279 {ISD::SMIN, MVT::v16i16, 6}, 4280 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 4281 {ISD::SMIN, MVT::v32i8, 8}, 4282 {ISD::UMIN, MVT::v32i8, 8}, 4283 }; 4284 4285 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 4286 {ISD::SMIN, MVT::v32i16, 8}, 4287 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 4288 {ISD::SMIN, MVT::v64i8, 10}, 4289 {ISD::UMIN, MVT::v64i8, 10}, 4290 }; 4291 4292 // Before legalizing the type, give a chance to look up illegal narrow types 4293 // in the table. 4294 // FIXME: Is there a better way to do this? 4295 EVT VT = TLI->getValueType(DL, ValTy); 4296 if (VT.isSimple()) { 4297 MVT MTy = VT.getSimpleVT(); 4298 if (ST->hasBWI()) 4299 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4300 return Entry->Cost; 4301 4302 if (ST->hasAVX()) 4303 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4304 return Entry->Cost; 4305 4306 if (ST->hasSSE41()) 4307 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4308 return Entry->Cost; 4309 4310 if (ST->hasSSE2()) 4311 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4312 return Entry->Cost; 4313 } 4314 4315 auto *ValVTy = cast<FixedVectorType>(ValTy); 4316 unsigned NumVecElts = ValVTy->getNumElements(); 4317 4318 auto *Ty = ValVTy; 4319 InstructionCost MinMaxCost = 0; 4320 if (LT.first != 1 && MTy.isVector() && 4321 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4322 // Type needs to be split. We need LT.first - 1 operations ops. 4323 Ty = FixedVectorType::get(ValVTy->getElementType(), 4324 MTy.getVectorNumElements()); 4325 auto *SubCondTy = FixedVectorType::get(CondTy->getElementType(), 4326 MTy.getVectorNumElements()); 4327 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4328 MinMaxCost *= LT.first - 1; 4329 NumVecElts = MTy.getVectorNumElements(); 4330 } 4331 4332 if (ST->hasBWI()) 4333 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4334 return MinMaxCost + Entry->Cost; 4335 4336 if (ST->hasAVX()) 4337 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4338 return MinMaxCost + Entry->Cost; 4339 4340 if (ST->hasSSE41()) 4341 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4342 return MinMaxCost + Entry->Cost; 4343 4344 if (ST->hasSSE2()) 4345 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4346 return MinMaxCost + Entry->Cost; 4347 4348 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 4349 4350 // Special case power of 2 reductions where the scalar type isn't changed 4351 // by type legalization. 4352 if (!isPowerOf2_32(ValVTy->getNumElements()) || 4353 ScalarSize != MTy.getScalarSizeInBits()) 4354 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsUnsigned, CostKind); 4355 4356 // Now handle reduction with the legal type, taking into account size changes 4357 // at each level. 4358 while (NumVecElts > 1) { 4359 // Determine the size of the remaining vector we need to reduce. 4360 unsigned Size = NumVecElts * ScalarSize; 4361 NumVecElts /= 2; 4362 // If we're reducing from 256/512 bits, use an extract_subvector. 4363 if (Size > 128) { 4364 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 4365 MinMaxCost += 4366 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 4367 Ty = SubTy; 4368 } else if (Size == 128) { 4369 // Reducing from 128 bits is a permute of v2f64/v2i64. 4370 VectorType *ShufTy; 4371 if (ValTy->isFloatingPointTy()) 4372 ShufTy = 4373 FixedVectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 4374 else 4375 ShufTy = FixedVectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 4376 MinMaxCost += 4377 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4378 } else if (Size == 64) { 4379 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 4380 FixedVectorType *ShufTy; 4381 if (ValTy->isFloatingPointTy()) 4382 ShufTy = FixedVectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 4383 else 4384 ShufTy = FixedVectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 4385 MinMaxCost += 4386 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4387 } else { 4388 // Reducing from smaller size is a shift by immediate. 4389 auto *ShiftTy = FixedVectorType::get( 4390 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 4391 MinMaxCost += getArithmeticInstrCost( 4392 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, 4393 TargetTransformInfo::OK_AnyValue, 4394 TargetTransformInfo::OK_UniformConstantValue, 4395 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 4396 } 4397 4398 // Add the arithmetic op for this level. 4399 auto *SubCondTy = 4400 FixedVectorType::get(CondTy->getElementType(), Ty->getNumElements()); 4401 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4402 } 4403 4404 // Add the final extract element to the cost. 4405 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 4406 } 4407 4408 /// Calculate the cost of materializing a 64-bit value. This helper 4409 /// method might only calculate a fraction of a larger immediate. Therefore it 4410 /// is valid to return a cost of ZERO. 4411 InstructionCost X86TTIImpl::getIntImmCost(int64_t Val) { 4412 if (Val == 0) 4413 return TTI::TCC_Free; 4414 4415 if (isInt<32>(Val)) 4416 return TTI::TCC_Basic; 4417 4418 return 2 * TTI::TCC_Basic; 4419 } 4420 4421 InstructionCost X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 4422 TTI::TargetCostKind CostKind) { 4423 assert(Ty->isIntegerTy()); 4424 4425 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4426 if (BitSize == 0) 4427 return ~0U; 4428 4429 // Never hoist constants larger than 128bit, because this might lead to 4430 // incorrect code generation or assertions in codegen. 4431 // Fixme: Create a cost model for types larger than i128 once the codegen 4432 // issues have been fixed. 4433 if (BitSize > 128) 4434 return TTI::TCC_Free; 4435 4436 if (Imm == 0) 4437 return TTI::TCC_Free; 4438 4439 // Sign-extend all constants to a multiple of 64-bit. 4440 APInt ImmVal = Imm; 4441 if (BitSize % 64 != 0) 4442 ImmVal = Imm.sext(alignTo(BitSize, 64)); 4443 4444 // Split the constant into 64-bit chunks and calculate the cost for each 4445 // chunk. 4446 InstructionCost Cost = 0; 4447 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 4448 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 4449 int64_t Val = Tmp.getSExtValue(); 4450 Cost += getIntImmCost(Val); 4451 } 4452 // We need at least one instruction to materialize the constant. 4453 return std::max<InstructionCost>(1, Cost); 4454 } 4455 4456 InstructionCost X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, 4457 const APInt &Imm, Type *Ty, 4458 TTI::TargetCostKind CostKind, 4459 Instruction *Inst) { 4460 assert(Ty->isIntegerTy()); 4461 4462 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4463 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4464 // here, so that constant hoisting will ignore this constant. 4465 if (BitSize == 0) 4466 return TTI::TCC_Free; 4467 4468 unsigned ImmIdx = ~0U; 4469 switch (Opcode) { 4470 default: 4471 return TTI::TCC_Free; 4472 case Instruction::GetElementPtr: 4473 // Always hoist the base address of a GetElementPtr. This prevents the 4474 // creation of new constants for every base constant that gets constant 4475 // folded with the offset. 4476 if (Idx == 0) 4477 return 2 * TTI::TCC_Basic; 4478 return TTI::TCC_Free; 4479 case Instruction::Store: 4480 ImmIdx = 0; 4481 break; 4482 case Instruction::ICmp: 4483 // This is an imperfect hack to prevent constant hoisting of 4484 // compares that might be trying to check if a 64-bit value fits in 4485 // 32-bits. The backend can optimize these cases using a right shift by 32. 4486 // Ideally we would check the compare predicate here. There also other 4487 // similar immediates the backend can use shifts for. 4488 if (Idx == 1 && Imm.getBitWidth() == 64) { 4489 uint64_t ImmVal = Imm.getZExtValue(); 4490 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 4491 return TTI::TCC_Free; 4492 } 4493 ImmIdx = 1; 4494 break; 4495 case Instruction::And: 4496 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 4497 // by using a 32-bit operation with implicit zero extension. Detect such 4498 // immediates here as the normal path expects bit 31 to be sign extended. 4499 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 4500 return TTI::TCC_Free; 4501 ImmIdx = 1; 4502 break; 4503 case Instruction::Add: 4504 case Instruction::Sub: 4505 // For add/sub, we can use the opposite instruction for INT32_MIN. 4506 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 4507 return TTI::TCC_Free; 4508 ImmIdx = 1; 4509 break; 4510 case Instruction::UDiv: 4511 case Instruction::SDiv: 4512 case Instruction::URem: 4513 case Instruction::SRem: 4514 // Division by constant is typically expanded later into a different 4515 // instruction sequence. This completely changes the constants. 4516 // Report them as "free" to stop ConstantHoist from marking them as opaque. 4517 return TTI::TCC_Free; 4518 case Instruction::Mul: 4519 case Instruction::Or: 4520 case Instruction::Xor: 4521 ImmIdx = 1; 4522 break; 4523 // Always return TCC_Free for the shift value of a shift instruction. 4524 case Instruction::Shl: 4525 case Instruction::LShr: 4526 case Instruction::AShr: 4527 if (Idx == 1) 4528 return TTI::TCC_Free; 4529 break; 4530 case Instruction::Trunc: 4531 case Instruction::ZExt: 4532 case Instruction::SExt: 4533 case Instruction::IntToPtr: 4534 case Instruction::PtrToInt: 4535 case Instruction::BitCast: 4536 case Instruction::PHI: 4537 case Instruction::Call: 4538 case Instruction::Select: 4539 case Instruction::Ret: 4540 case Instruction::Load: 4541 break; 4542 } 4543 4544 if (Idx == ImmIdx) { 4545 int NumConstants = divideCeil(BitSize, 64); 4546 InstructionCost Cost = X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4547 return (Cost <= NumConstants * TTI::TCC_Basic) 4548 ? static_cast<int>(TTI::TCC_Free) 4549 : Cost; 4550 } 4551 4552 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4553 } 4554 4555 InstructionCost X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 4556 const APInt &Imm, Type *Ty, 4557 TTI::TargetCostKind CostKind) { 4558 assert(Ty->isIntegerTy()); 4559 4560 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4561 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4562 // here, so that constant hoisting will ignore this constant. 4563 if (BitSize == 0) 4564 return TTI::TCC_Free; 4565 4566 switch (IID) { 4567 default: 4568 return TTI::TCC_Free; 4569 case Intrinsic::sadd_with_overflow: 4570 case Intrinsic::uadd_with_overflow: 4571 case Intrinsic::ssub_with_overflow: 4572 case Intrinsic::usub_with_overflow: 4573 case Intrinsic::smul_with_overflow: 4574 case Intrinsic::umul_with_overflow: 4575 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 4576 return TTI::TCC_Free; 4577 break; 4578 case Intrinsic::experimental_stackmap: 4579 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4580 return TTI::TCC_Free; 4581 break; 4582 case Intrinsic::experimental_patchpoint_void: 4583 case Intrinsic::experimental_patchpoint_i64: 4584 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4585 return TTI::TCC_Free; 4586 break; 4587 } 4588 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4589 } 4590 4591 InstructionCost X86TTIImpl::getCFInstrCost(unsigned Opcode, 4592 TTI::TargetCostKind CostKind, 4593 const Instruction *I) { 4594 if (CostKind != TTI::TCK_RecipThroughput) 4595 return Opcode == Instruction::PHI ? 0 : 1; 4596 // Branches are assumed to be predicted. 4597 return 0; 4598 } 4599 4600 int X86TTIImpl::getGatherOverhead() const { 4601 // Some CPUs have more overhead for gather. The specified overhead is relative 4602 // to the Load operation. "2" is the number provided by Intel architects. This 4603 // parameter is used for cost estimation of Gather Op and comparison with 4604 // other alternatives. 4605 // TODO: Remove the explicit hasAVX512()?, That would mean we would only 4606 // enable gather with a -march. 4607 if (ST->hasAVX512() || (ST->hasAVX2() && ST->hasFastGather())) 4608 return 2; 4609 4610 return 1024; 4611 } 4612 4613 int X86TTIImpl::getScatterOverhead() const { 4614 if (ST->hasAVX512()) 4615 return 2; 4616 4617 return 1024; 4618 } 4619 4620 // Return an average cost of Gather / Scatter instruction, maybe improved later. 4621 // FIXME: Add TargetCostKind support. 4622 InstructionCost X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, 4623 const Value *Ptr, Align Alignment, 4624 unsigned AddressSpace) { 4625 4626 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 4627 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4628 4629 // Try to reduce index size from 64 bit (default for GEP) 4630 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 4631 // operation will use 16 x 64 indices which do not fit in a zmm and needs 4632 // to split. Also check that the base pointer is the same for all lanes, 4633 // and that there's at most one variable index. 4634 auto getIndexSizeInBits = [](const Value *Ptr, const DataLayout &DL) { 4635 unsigned IndexSize = DL.getPointerSizeInBits(); 4636 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 4637 if (IndexSize < 64 || !GEP) 4638 return IndexSize; 4639 4640 unsigned NumOfVarIndices = 0; 4641 const Value *Ptrs = GEP->getPointerOperand(); 4642 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 4643 return IndexSize; 4644 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 4645 if (isa<Constant>(GEP->getOperand(i))) 4646 continue; 4647 Type *IndxTy = GEP->getOperand(i)->getType(); 4648 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 4649 IndxTy = IndexVTy->getElementType(); 4650 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 4651 !isa<SExtInst>(GEP->getOperand(i))) || 4652 ++NumOfVarIndices > 1) 4653 return IndexSize; // 64 4654 } 4655 return (unsigned)32; 4656 }; 4657 4658 // Trying to reduce IndexSize to 32 bits for vector 16. 4659 // By default the IndexSize is equal to pointer size. 4660 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 4661 ? getIndexSizeInBits(Ptr, DL) 4662 : DL.getPointerSizeInBits(); 4663 4664 auto *IndexVTy = FixedVectorType::get( 4665 IntegerType::get(SrcVTy->getContext(), IndexSize), VF); 4666 std::pair<InstructionCost, MVT> IdxsLT = 4667 TLI->getTypeLegalizationCost(DL, IndexVTy); 4668 std::pair<InstructionCost, MVT> SrcLT = 4669 TLI->getTypeLegalizationCost(DL, SrcVTy); 4670 InstructionCost::CostType SplitFactor = 4671 *std::max(IdxsLT.first, SrcLT.first).getValue(); 4672 if (SplitFactor > 1) { 4673 // Handle splitting of vector of pointers 4674 auto *SplitSrcTy = 4675 FixedVectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 4676 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 4677 AddressSpace); 4678 } 4679 4680 // The gather / scatter cost is given by Intel architects. It is a rough 4681 // number since we are looking at one instruction in a time. 4682 const int GSOverhead = (Opcode == Instruction::Load) 4683 ? getGatherOverhead() 4684 : getScatterOverhead(); 4685 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4686 MaybeAlign(Alignment), AddressSpace, 4687 TTI::TCK_RecipThroughput); 4688 } 4689 4690 /// Return the cost of full scalarization of gather / scatter operation. 4691 /// 4692 /// Opcode - Load or Store instruction. 4693 /// SrcVTy - The type of the data vector that should be gathered or scattered. 4694 /// VariableMask - The mask is non-constant at compile time. 4695 /// Alignment - Alignment for one element. 4696 /// AddressSpace - pointer[s] address space. 4697 /// 4698 /// FIXME: Add TargetCostKind support. 4699 InstructionCost X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 4700 bool VariableMask, Align Alignment, 4701 unsigned AddressSpace) { 4702 Type *ScalarTy = SrcVTy->getScalarType(); 4703 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4704 APInt DemandedElts = APInt::getAllOnes(VF); 4705 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4706 4707 InstructionCost MaskUnpackCost = 0; 4708 if (VariableMask) { 4709 auto *MaskTy = 4710 FixedVectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 4711 MaskUnpackCost = getScalarizationOverhead( 4712 MaskTy, DemandedElts, /*Insert=*/false, /*Extract=*/true); 4713 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 4714 Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), nullptr, 4715 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4716 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 4717 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 4718 } 4719 4720 InstructionCost AddressUnpackCost = getScalarizationOverhead( 4721 FixedVectorType::get(ScalarTy->getPointerTo(), VF), DemandedElts, 4722 /*Insert=*/false, /*Extract=*/true); 4723 4724 // The cost of the scalar loads/stores. 4725 InstructionCost MemoryOpCost = 4726 VF * getMemoryOpCost(Opcode, ScalarTy, MaybeAlign(Alignment), 4727 AddressSpace, CostKind); 4728 4729 // The cost of forming the vector from loaded scalars/ 4730 // scalarizing the vector to perform scalar stores. 4731 InstructionCost InsertExtractCost = 4732 getScalarizationOverhead(cast<FixedVectorType>(SrcVTy), DemandedElts, 4733 /*Insert=*/Opcode == Instruction::Load, 4734 /*Extract=*/Opcode == Instruction::Store); 4735 4736 return AddressUnpackCost + MemoryOpCost + MaskUnpackCost + InsertExtractCost; 4737 } 4738 4739 /// Calculate the cost of Gather / Scatter operation 4740 InstructionCost X86TTIImpl::getGatherScatterOpCost( 4741 unsigned Opcode, Type *SrcVTy, const Value *Ptr, bool VariableMask, 4742 Align Alignment, TTI::TargetCostKind CostKind, 4743 const Instruction *I = nullptr) { 4744 if (CostKind != TTI::TCK_RecipThroughput) { 4745 if ((Opcode == Instruction::Load && 4746 isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4747 (Opcode == Instruction::Store && 4748 isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4749 return 1; 4750 return BaseT::getGatherScatterOpCost(Opcode, SrcVTy, Ptr, VariableMask, 4751 Alignment, CostKind, I); 4752 } 4753 4754 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 4755 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 4756 if (!PtrTy && Ptr->getType()->isVectorTy()) 4757 PtrTy = dyn_cast<PointerType>( 4758 cast<VectorType>(Ptr->getType())->getElementType()); 4759 assert(PtrTy && "Unexpected type for Ptr argument"); 4760 unsigned AddressSpace = PtrTy->getAddressSpace(); 4761 4762 if ((Opcode == Instruction::Load && 4763 !isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4764 (Opcode == Instruction::Store && 4765 !isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4766 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 4767 AddressSpace); 4768 4769 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 4770 } 4771 4772 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 4773 TargetTransformInfo::LSRCost &C2) { 4774 // X86 specific here are "instruction number 1st priority". 4775 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 4776 C1.NumIVMuls, C1.NumBaseAdds, 4777 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 4778 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 4779 C2.NumIVMuls, C2.NumBaseAdds, 4780 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 4781 } 4782 4783 bool X86TTIImpl::canMacroFuseCmp() { 4784 return ST->hasMacroFusion() || ST->hasBranchFusion(); 4785 } 4786 4787 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, Align Alignment) { 4788 if (!ST->hasAVX()) 4789 return false; 4790 4791 // The backend can't handle a single element vector. 4792 if (isa<VectorType>(DataTy) && 4793 cast<FixedVectorType>(DataTy)->getNumElements() == 1) 4794 return false; 4795 Type *ScalarTy = DataTy->getScalarType(); 4796 4797 if (ScalarTy->isPointerTy()) 4798 return true; 4799 4800 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4801 return true; 4802 4803 if (ScalarTy->isHalfTy() && ST->hasBWI() && ST->hasFP16()) 4804 return true; 4805 4806 if (!ScalarTy->isIntegerTy()) 4807 return false; 4808 4809 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4810 return IntWidth == 32 || IntWidth == 64 || 4811 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 4812 } 4813 4814 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, Align Alignment) { 4815 return isLegalMaskedLoad(DataType, Alignment); 4816 } 4817 4818 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 4819 unsigned DataSize = DL.getTypeStoreSize(DataType); 4820 // The only supported nontemporal loads are for aligned vectors of 16 or 32 4821 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 4822 // (the equivalent stores only require AVX). 4823 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 4824 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 4825 4826 return false; 4827 } 4828 4829 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 4830 unsigned DataSize = DL.getTypeStoreSize(DataType); 4831 4832 // SSE4A supports nontemporal stores of float and double at arbitrary 4833 // alignment. 4834 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 4835 return true; 4836 4837 // Besides the SSE4A subtarget exception above, only aligned stores are 4838 // available nontemporaly on any other subtarget. And only stores with a size 4839 // of 4..32 bytes (powers of 2, only) are permitted. 4840 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 4841 !isPowerOf2_32(DataSize)) 4842 return false; 4843 4844 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 4845 // loads require AVX2). 4846 if (DataSize == 32) 4847 return ST->hasAVX(); 4848 if (DataSize == 16) 4849 return ST->hasSSE1(); 4850 return true; 4851 } 4852 4853 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 4854 if (!isa<VectorType>(DataTy)) 4855 return false; 4856 4857 if (!ST->hasAVX512()) 4858 return false; 4859 4860 // The backend can't handle a single element vector. 4861 if (cast<FixedVectorType>(DataTy)->getNumElements() == 1) 4862 return false; 4863 4864 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 4865 4866 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4867 return true; 4868 4869 if (!ScalarTy->isIntegerTy()) 4870 return false; 4871 4872 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4873 return IntWidth == 32 || IntWidth == 64 || 4874 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 4875 } 4876 4877 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 4878 return isLegalMaskedExpandLoad(DataTy); 4879 } 4880 4881 bool X86TTIImpl::supportsGather() const { 4882 // Some CPUs have better gather performance than others. 4883 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 4884 // enable gather with a -march. 4885 return ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()); 4886 } 4887 4888 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, Align Alignment) { 4889 if (!supportsGather()) 4890 return false; 4891 4892 // This function is called now in two cases: from the Loop Vectorizer 4893 // and from the Scalarizer. 4894 // When the Loop Vectorizer asks about legality of the feature, 4895 // the vectorization factor is not calculated yet. The Loop Vectorizer 4896 // sends a scalar type and the decision is based on the width of the 4897 // scalar element. 4898 // Later on, the cost model will estimate usage this intrinsic based on 4899 // the vector type. 4900 // The Scalarizer asks again about legality. It sends a vector type. 4901 // In this case we can reject non-power-of-2 vectors. 4902 // We also reject single element vectors as the type legalizer can't 4903 // scalarize it. 4904 if (auto *DataVTy = dyn_cast<FixedVectorType>(DataTy)) { 4905 unsigned NumElts = DataVTy->getNumElements(); 4906 if (NumElts == 1) 4907 return false; 4908 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 4909 // Vector-4 of gather/scatter instruction does not exist on KNL. 4910 // We can extend it to 8 elements, but zeroing upper bits of 4911 // the mask vector will add more instructions. Right now we give the scalar 4912 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter 4913 // instruction is better in the VariableMask case. 4914 if (ST->hasAVX512() && (NumElts == 2 || (NumElts == 4 && !ST->hasVLX()))) 4915 return false; 4916 } 4917 Type *ScalarTy = DataTy->getScalarType(); 4918 if (ScalarTy->isPointerTy()) 4919 return true; 4920 4921 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4922 return true; 4923 4924 if (!ScalarTy->isIntegerTy()) 4925 return false; 4926 4927 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4928 return IntWidth == 32 || IntWidth == 64; 4929 } 4930 4931 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, Align Alignment) { 4932 // AVX2 doesn't support scatter 4933 if (!ST->hasAVX512()) 4934 return false; 4935 return isLegalMaskedGather(DataType, Alignment); 4936 } 4937 4938 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 4939 EVT VT = TLI->getValueType(DL, DataType); 4940 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 4941 } 4942 4943 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 4944 return false; 4945 } 4946 4947 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 4948 const Function *Callee) const { 4949 const TargetMachine &TM = getTLI()->getTargetMachine(); 4950 4951 // Work this as a subsetting of subtarget features. 4952 const FeatureBitset &CallerBits = 4953 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 4954 const FeatureBitset &CalleeBits = 4955 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 4956 4957 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 4958 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 4959 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 4960 } 4961 4962 bool X86TTIImpl::areFunctionArgsABICompatible( 4963 const Function *Caller, const Function *Callee, 4964 SmallPtrSetImpl<Argument *> &Args) const { 4965 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args)) 4966 return false; 4967 4968 // If we get here, we know the target features match. If one function 4969 // considers 512-bit vectors legal and the other does not, consider them 4970 // incompatible. 4971 const TargetMachine &TM = getTLI()->getTargetMachine(); 4972 4973 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 4974 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs()) 4975 return true; 4976 4977 // Consider the arguments compatible if they aren't vectors or aggregates. 4978 // FIXME: Look at the size of vectors. 4979 // FIXME: Look at the element types of aggregates to see if there are vectors. 4980 // FIXME: The API of this function seems intended to allow arguments 4981 // to be removed from the set, but the caller doesn't check if the set 4982 // becomes empty so that may not work in practice. 4983 return llvm::none_of(Args, [](Argument *A) { 4984 auto *EltTy = cast<PointerType>(A->getType())->getElementType(); 4985 return EltTy->isVectorTy() || EltTy->isAggregateType(); 4986 }); 4987 } 4988 4989 X86TTIImpl::TTI::MemCmpExpansionOptions 4990 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 4991 TTI::MemCmpExpansionOptions Options; 4992 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 4993 Options.NumLoadsPerBlock = 2; 4994 // All GPR and vector loads can be unaligned. 4995 Options.AllowOverlappingLoads = true; 4996 if (IsZeroCmp) { 4997 // Only enable vector loads for equality comparison. Right now the vector 4998 // version is not as fast for three way compare (see #33329). 4999 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 5000 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 5001 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 5002 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 5003 } 5004 if (ST->is64Bit()) { 5005 Options.LoadSizes.push_back(8); 5006 } 5007 Options.LoadSizes.push_back(4); 5008 Options.LoadSizes.push_back(2); 5009 Options.LoadSizes.push_back(1); 5010 return Options; 5011 } 5012 5013 bool X86TTIImpl::prefersVectorizedAddressing() const { 5014 return supportsGather(); 5015 } 5016 5017 bool X86TTIImpl::supportsEfficientVectorElementLoadStore() const { 5018 return false; 5019 } 5020 5021 bool X86TTIImpl::enableInterleavedAccessVectorization() { 5022 // TODO: We expect this to be beneficial regardless of arch, 5023 // but there are currently some unexplained performance artifacts on Atom. 5024 // As a temporary solution, disable on Atom. 5025 return !(ST->isAtom()); 5026 } 5027 5028 // Get estimation for interleaved load/store operations and strided load. 5029 // \p Indices contains indices for strided load. 5030 // \p Factor - the factor of interleaving. 5031 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 5032 InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX512( 5033 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 5034 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 5035 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 5036 // VecTy for interleave memop is <VF*Factor x Elt>. 5037 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 5038 // VecTy = <12 x i32>. 5039 5040 // Calculate the number of memory operations (NumOfMemOps), required 5041 // for load/store the VecTy. 5042 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 5043 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 5044 unsigned LegalVTSize = LegalVT.getStoreSize(); 5045 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 5046 5047 // Get the cost of one memory operation. 5048 auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(), 5049 LegalVT.getVectorNumElements()); 5050 InstructionCost MemOpCost = getMemoryOpCost( 5051 Opcode, SingleMemOpTy, MaybeAlign(Alignment), AddressSpace, CostKind); 5052 5053 unsigned VF = VecTy->getNumElements() / Factor; 5054 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 5055 5056 if (Opcode == Instruction::Load) { 5057 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 5058 // contain the cost of the optimized shuffle sequence that the 5059 // X86InterleavedAccess pass will generate. 5060 // The cost of loads and stores are computed separately from the table. 5061 5062 // X86InterleavedAccess support only the following interleaved-access group. 5063 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 5064 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 5065 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 5066 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 5067 }; 5068 5069 if (const auto *Entry = 5070 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 5071 return NumOfMemOps * MemOpCost + Entry->Cost; 5072 //If an entry does not exist, fallback to the default implementation. 5073 5074 // Kind of shuffle depends on number of loaded values. 5075 // If we load the entire data in one register, we can use a 1-src shuffle. 5076 // Otherwise, we'll merge 2 sources in each operation. 5077 TTI::ShuffleKind ShuffleKind = 5078 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 5079 5080 InstructionCost ShuffleCost = 5081 getShuffleCost(ShuffleKind, SingleMemOpTy, None, 0, nullptr); 5082 5083 unsigned NumOfLoadsInInterleaveGrp = 5084 Indices.size() ? Indices.size() : Factor; 5085 auto *ResultTy = FixedVectorType::get(VecTy->getElementType(), 5086 VecTy->getNumElements() / Factor); 5087 InstructionCost NumOfResults = 5088 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 5089 NumOfLoadsInInterleaveGrp; 5090 5091 // About a half of the loads may be folded in shuffles when we have only 5092 // one result. If we have more than one result, we do not fold loads at all. 5093 unsigned NumOfUnfoldedLoads = 5094 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 5095 5096 // Get a number of shuffle operations per result. 5097 unsigned NumOfShufflesPerResult = 5098 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 5099 5100 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 5101 // When we have more than one destination, we need additional instructions 5102 // to keep sources. 5103 InstructionCost NumOfMoves = 0; 5104 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 5105 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 5106 5107 InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 5108 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 5109 5110 return Cost; 5111 } 5112 5113 // Store. 5114 assert(Opcode == Instruction::Store && 5115 "Expected Store Instruction at this point"); 5116 // X86InterleavedAccess support only the following interleaved-access group. 5117 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 5118 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 5119 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 5120 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 5121 5122 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 5123 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 5124 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 5125 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 5126 }; 5127 5128 if (const auto *Entry = 5129 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 5130 return NumOfMemOps * MemOpCost + Entry->Cost; 5131 //If an entry does not exist, fallback to the default implementation. 5132 5133 // There is no strided stores meanwhile. And store can't be folded in 5134 // shuffle. 5135 unsigned NumOfSources = Factor; // The number of values to be merged. 5136 InstructionCost ShuffleCost = 5137 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, None, 0, nullptr); 5138 unsigned NumOfShufflesPerStore = NumOfSources - 1; 5139 5140 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 5141 // We need additional instructions to keep sources. 5142 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 5143 InstructionCost Cost = 5144 NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 5145 NumOfMoves; 5146 return Cost; 5147 } 5148 5149 InstructionCost X86TTIImpl::getInterleavedMemoryOpCost( 5150 unsigned Opcode, Type *BaseTy, unsigned Factor, ArrayRef<unsigned> Indices, 5151 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, 5152 bool UseMaskForCond, bool UseMaskForGaps) { 5153 auto *VecTy = cast<FixedVectorType>(BaseTy); 5154 if (UseMaskForCond || UseMaskForGaps) 5155 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5156 Alignment, AddressSpace, CostKind, 5157 UseMaskForCond, UseMaskForGaps); 5158 5159 auto isSupportedOnAVX512 = [&](Type *VecTy, bool HasBW) { 5160 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 5161 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 5162 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 5163 return true; 5164 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8) || 5165 (!ST->useSoftFloat() && ST->hasFP16() && EltTy->isHalfTy())) 5166 return HasBW; 5167 return false; 5168 }; 5169 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 5170 return getInterleavedMemoryOpCostAVX512( 5171 Opcode, VecTy, Factor, Indices, Alignment, 5172 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 5173 5174 // Get estimation for interleaved load/store operations for SSE-AVX2. 5175 // As opposed to AVX-512, SSE-AVX2 do not have generic shuffles that allow 5176 // computing the cost using a generic formula as a function of generic 5177 // shuffles. We therefore use a lookup table instead, filled according to 5178 // the instruction sequences that codegen currently generates. 5179 5180 // VecTy for interleave memop is <VF*Factor x Elt>. 5181 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 5182 // VecTy = <12 x i32>. 5183 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 5184 5185 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 5186 // the VF=2, while v2i128 is an unsupported MVT vector type 5187 // (see MachineValueType.h::getVectorVT()). 5188 if (!LegalVT.isVector()) 5189 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5190 Alignment, AddressSpace, CostKind); 5191 5192 unsigned VF = VecTy->getNumElements() / Factor; 5193 Type *ScalarTy = VecTy->getElementType(); 5194 // Deduplicate entries, model floats/pointers as appropriately-sized integers. 5195 if (!ScalarTy->isIntegerTy()) 5196 ScalarTy = 5197 Type::getIntNTy(ScalarTy->getContext(), DL.getTypeSizeInBits(ScalarTy)); 5198 5199 // Get the cost of all the memory operations. 5200 InstructionCost MemOpCosts = getMemoryOpCost( 5201 Opcode, VecTy, MaybeAlign(Alignment), AddressSpace, CostKind); 5202 5203 auto *VT = FixedVectorType::get(ScalarTy, VF); 5204 EVT ETy = TLI->getValueType(DL, VT); 5205 if (!ETy.isSimple()) 5206 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5207 Alignment, AddressSpace, CostKind); 5208 5209 // TODO: Complete for other data-types and strides. 5210 // Each combination of Stride, element bit width and VF results in a different 5211 // sequence; The cost tables are therefore accessed with: 5212 // Factor (stride) and VectorType=VFxiN. 5213 // The Cost accounts only for the shuffle sequence; 5214 // The cost of the loads/stores is accounted for separately. 5215 // 5216 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 5217 {2, MVT::v2i8, 2}, // (load 4i8 and) deinterleave into 2 x 2i8 5218 {2, MVT::v4i8, 2}, // (load 8i8 and) deinterleave into 2 x 4i8 5219 {2, MVT::v8i8, 2}, // (load 16i8 and) deinterleave into 2 x 8i8 5220 {2, MVT::v16i8, 4}, // (load 32i8 and) deinterleave into 2 x 16i8 5221 {2, MVT::v32i8, 6}, // (load 64i8 and) deinterleave into 2 x 32i8 5222 5223 {2, MVT::v8i16, 6}, // (load 16i16 and) deinterleave into 2 x 8i16 5224 {2, MVT::v16i16, 9}, // (load 32i16 and) deinterleave into 2 x 16i16 5225 {2, MVT::v32i16, 18}, // (load 64i16 and) deinterleave into 2 x 32i16 5226 5227 {2, MVT::v8i32, 4}, // (load 16i32 and) deinterleave into 2 x 8i32 5228 {2, MVT::v16i32, 8}, // (load 32i32 and) deinterleave into 2 x 16i32 5229 {2, MVT::v32i32, 16}, // (load 64i32 and) deinterleave into 2 x 32i32 5230 5231 {2, MVT::v4i64, 4}, // (load 8i64 and) deinterleave into 2 x 4i64 5232 {2, MVT::v8i64, 8}, // (load 16i64 and) deinterleave into 2 x 8i64 5233 {2, MVT::v16i64, 16}, // (load 32i64 and) deinterleave into 2 x 16i64 5234 {2, MVT::v32i64, 32}, // (load 64i64 and) deinterleave into 2 x 32i64 5235 5236 {3, MVT::v2i8, 3}, // (load 6i8 and) deinterleave into 3 x 2i8 5237 {3, MVT::v4i8, 3}, // (load 12i8 and) deinterleave into 3 x 4i8 5238 {3, MVT::v8i8, 6}, // (load 24i8 and) deinterleave into 3 x 8i8 5239 {3, MVT::v16i8, 11}, // (load 48i8 and) deinterleave into 3 x 16i8 5240 {3, MVT::v32i8, 14}, // (load 96i8 and) deinterleave into 3 x 32i8 5241 5242 {3, MVT::v2i16, 5}, // (load 6i16 and) deinterleave into 3 x 2i16 5243 {3, MVT::v4i16, 7}, // (load 12i16 and) deinterleave into 3 x 4i16 5244 {3, MVT::v8i16, 9}, // (load 24i16 and) deinterleave into 3 x 8i16 5245 {3, MVT::v16i16, 28}, // (load 48i16 and) deinterleave into 3 x 16i16 5246 {3, MVT::v32i16, 56}, // (load 96i16 and) deinterleave into 3 x 32i16 5247 5248 {3, MVT::v2i32, 3}, // (load 6i32 and) deinterleave into 3 x 2i32 5249 {3, MVT::v4i32, 3}, // (load 12i32 and) deinterleave into 3 x 4i32 5250 {3, MVT::v8i32, 7}, // (load 24i32 and) deinterleave into 3 x 8i32 5251 {3, MVT::v16i32, 14}, // (load 48i32 and) deinterleave into 3 x 16i32 5252 {3, MVT::v32i32, 32}, // (load 96i32 and) deinterleave into 3 x 32i32 5253 5254 {3, MVT::v2i64, 1}, // (load 6i64 and) deinterleave into 3 x 2i64 5255 {3, MVT::v4i64, 5}, // (load 12i64 and) deinterleave into 3 x 4i64 5256 {3, MVT::v8i64, 10}, // (load 24i64 and) deinterleave into 3 x 8i64 5257 {3, MVT::v16i64, 20}, // (load 48i64 and) deinterleave into 3 x 16i64 5258 5259 {4, MVT::v2i8, 4}, // (load 8i8 and) deinterleave into 4 x 2i8 5260 {4, MVT::v4i8, 4}, // (load 16i8 and) deinterleave into 4 x 4i8 5261 {4, MVT::v8i8, 12}, // (load 32i8 and) deinterleave into 4 x 8i8 5262 {4, MVT::v16i8, 24}, // (load 64i8 and) deinterleave into 4 x 16i8 5263 {4, MVT::v32i8, 56}, // (load 128i8 and) deinterleave into 4 x 32i8 5264 5265 {4, MVT::v2i16, 6}, // (load 8i16 and) deinterleave into 4 x 2i16 5266 {4, MVT::v4i16, 17}, // (load 16i16 and) deinterleave into 4 x 4i16 5267 {4, MVT::v8i16, 33}, // (load 32i16 and) deinterleave into 4 x 8i16 5268 {4, MVT::v16i16, 75}, // (load 64i16 and) deinterleave into 4 x 16i16 5269 {4, MVT::v32i16, 150}, // (load 128i16 and) deinterleave into 4 x 32i16 5270 5271 {4, MVT::v2i32, 4}, // (load 8i32 and) deinterleave into 4 x 2i32 5272 {4, MVT::v4i32, 8}, // (load 16i32 and) deinterleave into 4 x 4i32 5273 {4, MVT::v8i32, 16}, // (load 32i32 and) deinterleave into 4 x 8i32 5274 {4, MVT::v16i32, 32}, // (load 64i32 and) deinterleave into 4 x 16i32 5275 {4, MVT::v32i32, 68}, // (load 128i32 and) deinterleave into 4 x 32i32 5276 5277 {4, MVT::v2i64, 6}, // (load 8i64 and) deinterleave into 4 x 2i64 5278 {4, MVT::v4i64, 8}, // (load 16i64 and) deinterleave into 4 x 4i64 5279 {4, MVT::v8i64, 20}, // (load 32i64 and) deinterleave into 4 x 8i64 5280 {4, MVT::v16i64, 40}, // (load 64i64 and) deinterleave into 4 x 16i64 5281 5282 {6, MVT::v2i8, 6}, // (load 12i8 and) deinterleave into 6 x 2i8 5283 {6, MVT::v4i8, 14}, // (load 24i8 and) deinterleave into 6 x 4i8 5284 {6, MVT::v8i8, 18}, // (load 48i8 and) deinterleave into 6 x 8i8 5285 {6, MVT::v16i8, 43}, // (load 96i8 and) deinterleave into 6 x 16i8 5286 {6, MVT::v32i8, 82}, // (load 192i8 and) deinterleave into 6 x 32i8 5287 5288 {6, MVT::v2i16, 13}, // (load 12i16 and) deinterleave into 6 x 2i16 5289 {6, MVT::v4i16, 9}, // (load 24i16 and) deinterleave into 6 x 4i16 5290 {6, MVT::v8i16, 39}, // (load 48i16 and) deinterleave into 6 x 8i16 5291 {6, MVT::v16i16, 106}, // (load 96i16 and) deinterleave into 6 x 16i16 5292 {6, MVT::v32i16, 212}, // (load 192i16 and) deinterleave into 6 x 32i16 5293 5294 {6, MVT::v2i32, 6}, // (load 12i32 and) deinterleave into 6 x 2i32 5295 {6, MVT::v4i32, 15}, // (load 24i32 and) deinterleave into 6 x 4i32 5296 {6, MVT::v8i32, 31}, // (load 48i32 and) deinterleave into 6 x 8i32 5297 {6, MVT::v16i32, 64}, // (load 96i32 and) deinterleave into 6 x 16i32 5298 5299 {6, MVT::v2i64, 6}, // (load 12i64 and) deinterleave into 6 x 2i64 5300 {6, MVT::v4i64, 18}, // (load 24i64 and) deinterleave into 6 x 4i64 5301 {6, MVT::v8i64, 36}, // (load 48i64 and) deinterleave into 6 x 8i64 5302 5303 {8, MVT::v8i32, 40} // (load 64i32 and) deinterleave into 8 x 8i32 5304 }; 5305 5306 static const CostTblEntry SSSE3InterleavedLoadTbl[] = { 5307 {2, MVT::v4i16, 2}, // (load 8i16 and) deinterleave into 2 x 4i16 5308 }; 5309 5310 static const CostTblEntry SSE2InterleavedLoadTbl[] = { 5311 {2, MVT::v2i16, 2}, // (load 4i16 and) deinterleave into 2 x 2i16 5312 {2, MVT::v4i16, 7}, // (load 8i16 and) deinterleave into 2 x 4i16 5313 5314 {2, MVT::v2i32, 2}, // (load 4i32 and) deinterleave into 2 x 2i32 5315 {2, MVT::v4i32, 2}, // (load 8i32 and) deinterleave into 2 x 4i32 5316 5317 {2, MVT::v2i64, 2}, // (load 4i64 and) deinterleave into 2 x 2i64 5318 }; 5319 5320 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 5321 {2, MVT::v16i8, 3}, // interleave 2 x 16i8 into 32i8 (and store) 5322 {2, MVT::v32i8, 4}, // interleave 2 x 32i8 into 64i8 (and store) 5323 5324 {2, MVT::v8i16, 3}, // interleave 2 x 8i16 into 16i16 (and store) 5325 {2, MVT::v16i16, 4}, // interleave 2 x 16i16 into 32i16 (and store) 5326 {2, MVT::v32i16, 8}, // interleave 2 x 32i16 into 64i16 (and store) 5327 5328 {2, MVT::v4i32, 2}, // interleave 2 x 4i32 into 8i32 (and store) 5329 {2, MVT::v8i32, 4}, // interleave 2 x 8i32 into 16i32 (and store) 5330 {2, MVT::v16i32, 8}, // interleave 2 x 16i32 into 32i32 (and store) 5331 {2, MVT::v32i32, 16}, // interleave 2 x 32i32 into 64i32 (and store) 5332 5333 {2, MVT::v2i64, 2}, // interleave 2 x 2i64 into 4i64 (and store) 5334 {2, MVT::v4i64, 4}, // interleave 2 x 4i64 into 8i64 (and store) 5335 {2, MVT::v8i64, 8}, // interleave 2 x 8i64 into 16i64 (and store) 5336 {2, MVT::v16i64, 16}, // interleave 2 x 16i64 into 32i64 (and store) 5337 {2, MVT::v32i64, 32}, // interleave 2 x 32i64 into 64i64 (and store) 5338 5339 {3, MVT::v2i8, 4}, // interleave 3 x 2i8 into 6i8 (and store) 5340 {3, MVT::v4i8, 4}, // interleave 3 x 4i8 into 12i8 (and store) 5341 {3, MVT::v8i8, 6}, // interleave 3 x 8i8 into 24i8 (and store) 5342 {3, MVT::v16i8, 11}, // interleave 3 x 16i8 into 48i8 (and store) 5343 {3, MVT::v32i8, 13}, // interleave 3 x 32i8 into 96i8 (and store) 5344 5345 {3, MVT::v2i16, 4}, // interleave 3 x 2i16 into 6i16 (and store) 5346 {3, MVT::v4i16, 6}, // interleave 3 x 4i16 into 12i16 (and store) 5347 {3, MVT::v8i16, 12}, // interleave 3 x 8i16 into 24i16 (and store) 5348 {3, MVT::v16i16, 27}, // interleave 3 x 16i16 into 48i16 (and store) 5349 {3, MVT::v32i16, 54}, // interleave 3 x 32i16 into 96i16 (and store) 5350 5351 {3, MVT::v2i32, 4}, // interleave 3 x 2i32 into 6i32 (and store) 5352 {3, MVT::v4i32, 5}, // interleave 3 x 4i32 into 12i32 (and store) 5353 {3, MVT::v8i32, 11}, // interleave 3 x 8i32 into 24i32 (and store) 5354 {3, MVT::v16i32, 22}, // interleave 3 x 16i32 into 48i32 (and store) 5355 {3, MVT::v32i32, 48}, // interleave 3 x 32i32 into 96i32 (and store) 5356 5357 {3, MVT::v2i64, 4}, // interleave 3 x 2i64 into 6i64 (and store) 5358 {3, MVT::v4i64, 6}, // interleave 3 x 4i64 into 12i64 (and store) 5359 {3, MVT::v8i64, 12}, // interleave 3 x 8i64 into 24i64 (and store) 5360 {3, MVT::v16i64, 24}, // interleave 3 x 16i64 into 48i64 (and store) 5361 5362 {4, MVT::v2i8, 4}, // interleave 4 x 2i8 into 8i8 (and store) 5363 {4, MVT::v4i8, 4}, // interleave 4 x 4i8 into 16i8 (and store) 5364 {4, MVT::v8i8, 4}, // interleave 4 x 8i8 into 32i8 (and store) 5365 {4, MVT::v16i8, 8}, // interleave 4 x 16i8 into 64i8 (and store) 5366 {4, MVT::v32i8, 12}, // interleave 4 x 32i8 into 128i8 (and store) 5367 5368 {4, MVT::v2i16, 2}, // interleave 4 x 2i16 into 8i16 (and store) 5369 {4, MVT::v4i16, 6}, // interleave 4 x 4i16 into 16i16 (and store) 5370 {4, MVT::v8i16, 10}, // interleave 4 x 8i16 into 32i16 (and store) 5371 {4, MVT::v16i16, 32}, // interleave 4 x 16i16 into 64i16 (and store) 5372 {4, MVT::v32i16, 64}, // interleave 4 x 32i16 into 128i16 (and store) 5373 5374 {4, MVT::v2i32, 5}, // interleave 4 x 2i32 into 8i32 (and store) 5375 {4, MVT::v4i32, 6}, // interleave 4 x 4i32 into 16i32 (and store) 5376 {4, MVT::v8i32, 16}, // interleave 4 x 8i32 into 32i32 (and store) 5377 {4, MVT::v16i32, 32}, // interleave 4 x 16i32 into 64i32 (and store) 5378 {4, MVT::v32i32, 64}, // interleave 4 x 32i32 into 128i32 (and store) 5379 5380 {4, MVT::v2i64, 6}, // interleave 4 x 2i64 into 8i64 (and store) 5381 {4, MVT::v4i64, 8}, // interleave 4 x 4i64 into 16i64 (and store) 5382 {4, MVT::v8i64, 20}, // interleave 4 x 8i64 into 32i64 (and store) 5383 {4, MVT::v16i64, 40}, // interleave 4 x 16i64 into 64i64 (and store) 5384 5385 {6, MVT::v2i8, 7}, // interleave 6 x 2i8 into 12i8 (and store) 5386 {6, MVT::v4i8, 9}, // interleave 6 x 4i8 into 24i8 (and store) 5387 {6, MVT::v8i8, 16}, // interleave 6 x 8i8 into 48i8 (and store) 5388 {6, MVT::v16i8, 27}, // interleave 6 x 16i8 into 96i8 (and store) 5389 {6, MVT::v32i8, 90}, // interleave 6 x 32i8 into 192i8 (and store) 5390 5391 {6, MVT::v2i16, 10}, // interleave 6 x 2i16 into 12i16 (and store) 5392 {6, MVT::v4i16, 15}, // interleave 6 x 4i16 into 24i16 (and store) 5393 {6, MVT::v8i16, 21}, // interleave 6 x 8i16 into 48i16 (and store) 5394 {6, MVT::v16i16, 58}, // interleave 6 x 16i16 into 96i16 (and store) 5395 {6, MVT::v32i16, 90}, // interleave 6 x 32i16 into 192i16 (and store) 5396 5397 {6, MVT::v2i32, 9}, // interleave 6 x 2i32 into 12i32 (and store) 5398 {6, MVT::v4i32, 12}, // interleave 6 x 4i32 into 24i32 (and store) 5399 {6, MVT::v8i32, 33}, // interleave 6 x 8i32 into 48i32 (and store) 5400 {6, MVT::v16i32, 66}, // interleave 6 x 16i32 into 96i32 (and store) 5401 5402 {6, MVT::v2i64, 8}, // interleave 6 x 2i64 into 12i64 (and store) 5403 {6, MVT::v4i64, 15}, // interleave 6 x 4i64 into 24i64 (and store) 5404 {6, MVT::v8i64, 30}, // interleave 6 x 8i64 into 48i64 (and store) 5405 }; 5406 5407 static const CostTblEntry SSE2InterleavedStoreTbl[] = { 5408 {2, MVT::v2i8, 1}, // interleave 2 x 2i8 into 4i8 (and store) 5409 {2, MVT::v4i8, 1}, // interleave 2 x 4i8 into 8i8 (and store) 5410 {2, MVT::v8i8, 1}, // interleave 2 x 8i8 into 16i8 (and store) 5411 5412 {2, MVT::v2i16, 1}, // interleave 2 x 2i16 into 4i16 (and store) 5413 {2, MVT::v4i16, 1}, // interleave 2 x 4i16 into 8i16 (and store) 5414 5415 {2, MVT::v2i32, 1}, // interleave 2 x 2i32 into 4i32 (and store) 5416 }; 5417 5418 if (Opcode == Instruction::Load) { 5419 // FIXME: if we have a partially-interleaved groups, with gaps, 5420 // should we discount the not-demanded indicies? 5421 if (ST->hasAVX2()) 5422 if (const auto *Entry = CostTableLookup(AVX2InterleavedLoadTbl, Factor, 5423 ETy.getSimpleVT())) 5424 return MemOpCosts + Entry->Cost; 5425 5426 if (ST->hasSSSE3()) 5427 if (const auto *Entry = CostTableLookup(SSSE3InterleavedLoadTbl, Factor, 5428 ETy.getSimpleVT())) 5429 return MemOpCosts + Entry->Cost; 5430 5431 if (ST->hasSSE2()) 5432 if (const auto *Entry = CostTableLookup(SSE2InterleavedLoadTbl, Factor, 5433 ETy.getSimpleVT())) 5434 return MemOpCosts + Entry->Cost; 5435 } else { 5436 assert(Opcode == Instruction::Store && 5437 "Expected Store Instruction at this point"); 5438 assert((!Indices.size() || Indices.size() == Factor) && 5439 "Interleaved store only supports fully-interleaved groups."); 5440 if (ST->hasAVX2()) 5441 if (const auto *Entry = CostTableLookup(AVX2InterleavedStoreTbl, Factor, 5442 ETy.getSimpleVT())) 5443 return MemOpCosts + Entry->Cost; 5444 5445 if (ST->hasSSE2()) 5446 if (const auto *Entry = CostTableLookup(SSE2InterleavedStoreTbl, Factor, 5447 ETy.getSimpleVT())) 5448 return MemOpCosts + Entry->Cost; 5449 } 5450 5451 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5452 Alignment, AddressSpace, CostKind, 5453 UseMaskForCond, UseMaskForGaps); 5454 } 5455