1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // X86 cost model. 56 // 57 //===----------------------------------------------------------------------===// 58 59 TargetTransformInfo::PopcntSupportKind 60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 61 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 62 // TODO: Currently the __builtin_popcount() implementation using SSE3 63 // instructions is inefficient. Once the problem is fixed, we should 64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 66 } 67 68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 69 TargetTransformInfo::CacheLevel Level) const { 70 switch (Level) { 71 case TargetTransformInfo::CacheLevel::L1D: 72 // - Penryn 73 // - Nehalem 74 // - Westmere 75 // - Sandy Bridge 76 // - Ivy Bridge 77 // - Haswell 78 // - Broadwell 79 // - Skylake 80 // - Kabylake 81 return 32 * 1024; // 32 KByte 82 case TargetTransformInfo::CacheLevel::L2D: 83 // - Penryn 84 // - Nehalem 85 // - Westmere 86 // - Sandy Bridge 87 // - Ivy Bridge 88 // - Haswell 89 // - Broadwell 90 // - Skylake 91 // - Kabylake 92 return 256 * 1024; // 256 KByte 93 } 94 95 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 96 } 97 98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 99 TargetTransformInfo::CacheLevel Level) const { 100 // - Penryn 101 // - Nehalem 102 // - Westmere 103 // - Sandy Bridge 104 // - Ivy Bridge 105 // - Haswell 106 // - Broadwell 107 // - Skylake 108 // - Kabylake 109 switch (Level) { 110 case TargetTransformInfo::CacheLevel::L1D: 111 LLVM_FALLTHROUGH; 112 case TargetTransformInfo::CacheLevel::L2D: 113 return 8; 114 } 115 116 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 117 } 118 119 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 120 bool Vector = (ClassID == 1); 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const { 133 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 134 if (Vector) { 135 if (ST->hasAVX512() && PreferVectorWidth >= 512) 136 return 512; 137 if (ST->hasAVX() && PreferVectorWidth >= 256) 138 return 256; 139 if (ST->hasSSE1() && PreferVectorWidth >= 128) 140 return 128; 141 return 0; 142 } 143 144 if (ST->is64Bit()) 145 return 64; 146 147 return 32; 148 } 149 150 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 151 return getRegisterBitWidth(true); 152 } 153 154 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 155 // If the loop will not be vectorized, don't interleave the loop. 156 // Let regular unroll to unroll the loop, which saves the overflow 157 // check and memory check cost. 158 if (VF == 1) 159 return 1; 160 161 if (ST->isAtom()) 162 return 1; 163 164 // Sandybridge and Haswell have multiple execution ports and pipelined 165 // vector units. 166 if (ST->hasAVX()) 167 return 4; 168 169 return 2; 170 } 171 172 int X86TTIImpl::getArithmeticInstrCost(unsigned Opcode, Type *Ty, 173 TTI::OperandValueKind Op1Info, 174 TTI::OperandValueKind Op2Info, 175 TTI::OperandValueProperties Opd1PropInfo, 176 TTI::OperandValueProperties Opd2PropInfo, 177 ArrayRef<const Value *> Args, 178 const Instruction *CxtI) { 179 // Legalize the type. 180 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 181 182 int ISD = TLI->InstructionOpcodeToISD(Opcode); 183 assert(ISD && "Invalid opcode"); 184 185 static const CostTblEntry GLMCostTable[] = { 186 { ISD::FDIV, MVT::f32, 18 }, // divss 187 { ISD::FDIV, MVT::v4f32, 35 }, // divps 188 { ISD::FDIV, MVT::f64, 33 }, // divsd 189 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 190 }; 191 192 if (ST->useGLMDivSqrtCosts()) 193 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 194 LT.second)) 195 return LT.first * Entry->Cost; 196 197 static const CostTblEntry SLMCostTable[] = { 198 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 199 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 200 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. 201 { ISD::FMUL, MVT::f64, 2 }, // mulsd 202 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 203 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 204 { ISD::FDIV, MVT::f32, 17 }, // divss 205 { ISD::FDIV, MVT::v4f32, 39 }, // divps 206 { ISD::FDIV, MVT::f64, 32 }, // divsd 207 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 208 { ISD::FADD, MVT::v2f64, 2 }, // addpd 209 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 210 // v2i64/v4i64 mul is custom lowered as a series of long: 211 // multiplies(3), shifts(3) and adds(2) 212 // slm muldq version throughput is 2 and addq throughput 4 213 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 214 // 3X4 (addq throughput) = 17 215 { ISD::MUL, MVT::v2i64, 17 }, 216 // slm addq\subq throughput is 4 217 { ISD::ADD, MVT::v2i64, 4 }, 218 { ISD::SUB, MVT::v2i64, 4 }, 219 }; 220 221 if (ST->isSLM()) { 222 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 223 // Check if the operands can be shrinked into a smaller datatype. 224 bool Op1Signed = false; 225 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 226 bool Op2Signed = false; 227 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 228 229 bool signedMode = Op1Signed | Op2Signed; 230 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 231 232 if (OpMinSize <= 7) 233 return LT.first * 3; // pmullw/sext 234 if (!signedMode && OpMinSize <= 8) 235 return LT.first * 3; // pmullw/zext 236 if (OpMinSize <= 15) 237 return LT.first * 5; // pmullw/pmulhw/pshuf 238 if (!signedMode && OpMinSize <= 16) 239 return LT.first * 5; // pmullw/pmulhw/pshuf 240 } 241 242 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 243 LT.second)) { 244 return LT.first * Entry->Cost; 245 } 246 } 247 248 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 249 ISD == ISD::UREM) && 250 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 251 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 252 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 253 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 254 // On X86, vector signed division by constants power-of-two are 255 // normally expanded to the sequence SRA + SRL + ADD + SRA. 256 // The OperandValue properties may not be the same as that of the previous 257 // operation; conservatively assume OP_None. 258 int Cost = 259 2 * getArithmeticInstrCost(Instruction::AShr, Ty, Op1Info, Op2Info, 260 TargetTransformInfo::OP_None, 261 TargetTransformInfo::OP_None); 262 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 263 TargetTransformInfo::OP_None, 264 TargetTransformInfo::OP_None); 265 Cost += getArithmeticInstrCost(Instruction::Add, Ty, Op1Info, Op2Info, 266 TargetTransformInfo::OP_None, 267 TargetTransformInfo::OP_None); 268 269 if (ISD == ISD::SREM) { 270 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 271 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info); 272 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, Op1Info, Op2Info); 273 } 274 275 return Cost; 276 } 277 278 // Vector unsigned division/remainder will be simplified to shifts/masks. 279 if (ISD == ISD::UDIV) 280 return getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 281 TargetTransformInfo::OP_None, 282 TargetTransformInfo::OP_None); 283 284 else // UREM 285 return getArithmeticInstrCost(Instruction::And, Ty, Op1Info, Op2Info, 286 TargetTransformInfo::OP_None, 287 TargetTransformInfo::OP_None); 288 } 289 290 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 291 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 292 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 293 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 294 }; 295 296 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 297 ST->hasBWI()) { 298 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 299 LT.second)) 300 return LT.first * Entry->Cost; 301 } 302 303 static const CostTblEntry AVX512UniformConstCostTable[] = { 304 { ISD::SRA, MVT::v2i64, 1 }, 305 { ISD::SRA, MVT::v4i64, 1 }, 306 { ISD::SRA, MVT::v8i64, 1 }, 307 308 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 309 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 310 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 311 }; 312 313 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 314 ST->hasAVX512()) { 315 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 316 LT.second)) 317 return LT.first * Entry->Cost; 318 } 319 320 static const CostTblEntry AVX2UniformConstCostTable[] = { 321 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 322 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 323 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 324 325 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 326 }; 327 328 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 329 ST->hasAVX2()) { 330 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 331 LT.second)) 332 return LT.first * Entry->Cost; 333 } 334 335 static const CostTblEntry SSE2UniformConstCostTable[] = { 336 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 337 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 338 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 339 340 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 341 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 342 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 343 }; 344 345 // XOP has faster vXi8 shifts. 346 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 347 ST->hasSSE2() && !ST->hasXOP()) { 348 if (const auto *Entry = 349 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 350 return LT.first * Entry->Cost; 351 } 352 353 static const CostTblEntry AVX512BWConstCostTable[] = { 354 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 355 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 356 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 357 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 358 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 359 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 360 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 361 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 362 }; 363 364 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 365 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 366 ST->hasBWI()) { 367 if (const auto *Entry = 368 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 369 return LT.first * Entry->Cost; 370 } 371 372 static const CostTblEntry AVX512ConstCostTable[] = { 373 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 374 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 375 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 376 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 377 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 378 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 379 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 380 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 381 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 382 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 383 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 384 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 385 }; 386 387 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 388 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 389 ST->hasAVX512()) { 390 if (const auto *Entry = 391 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 392 return LT.first * Entry->Cost; 393 } 394 395 static const CostTblEntry AVX2ConstCostTable[] = { 396 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 397 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 398 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 399 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 400 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 401 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 402 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 403 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 404 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 405 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 406 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 407 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 408 }; 409 410 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 411 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 412 ST->hasAVX2()) { 413 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 414 return LT.first * Entry->Cost; 415 } 416 417 static const CostTblEntry SSE2ConstCostTable[] = { 418 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 419 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 420 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 421 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 422 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 423 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 424 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 425 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 426 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 427 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 428 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 429 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 430 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 431 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 432 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 433 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 434 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 435 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 436 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 437 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 438 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 439 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 440 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 441 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 442 }; 443 444 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 445 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 446 ST->hasSSE2()) { 447 // pmuldq sequence. 448 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 449 return LT.first * 32; 450 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 451 return LT.first * 38; 452 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 453 return LT.first * 15; 454 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 455 return LT.first * 20; 456 457 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 458 return LT.first * Entry->Cost; 459 } 460 461 static const CostTblEntry AVX512BWShiftCostTable[] = { 462 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 463 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 464 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 465 466 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 467 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 468 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 469 470 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 471 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 472 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 473 }; 474 475 if (ST->hasBWI()) 476 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 477 return LT.first * Entry->Cost; 478 479 static const CostTblEntry AVX2UniformCostTable[] = { 480 // Uniform splats are cheaper for the following instructions. 481 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 482 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 483 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 484 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 485 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 486 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 487 }; 488 489 if (ST->hasAVX2() && 490 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 491 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 492 if (const auto *Entry = 493 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 494 return LT.first * Entry->Cost; 495 } 496 497 static const CostTblEntry SSE2UniformCostTable[] = { 498 // Uniform splats are cheaper for the following instructions. 499 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 500 { ISD::SHL, MVT::v4i32, 1 }, // pslld 501 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 502 503 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 504 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 505 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 506 507 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 508 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 509 }; 510 511 if (ST->hasSSE2() && 512 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 513 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 514 if (const auto *Entry = 515 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 516 return LT.first * Entry->Cost; 517 } 518 519 static const CostTblEntry AVX512DQCostTable[] = { 520 { ISD::MUL, MVT::v2i64, 1 }, 521 { ISD::MUL, MVT::v4i64, 1 }, 522 { ISD::MUL, MVT::v8i64, 1 } 523 }; 524 525 // Look for AVX512DQ lowering tricks for custom cases. 526 if (ST->hasDQI()) 527 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 528 return LT.first * Entry->Cost; 529 530 static const CostTblEntry AVX512BWCostTable[] = { 531 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 532 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 533 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 534 535 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence. 536 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence. 537 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence. 538 }; 539 540 // Look for AVX512BW lowering tricks for custom cases. 541 if (ST->hasBWI()) 542 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 543 return LT.first * Entry->Cost; 544 545 static const CostTblEntry AVX512CostTable[] = { 546 { ISD::SHL, MVT::v16i32, 1 }, 547 { ISD::SRL, MVT::v16i32, 1 }, 548 { ISD::SRA, MVT::v16i32, 1 }, 549 550 { ISD::SHL, MVT::v8i64, 1 }, 551 { ISD::SRL, MVT::v8i64, 1 }, 552 553 { ISD::SRA, MVT::v2i64, 1 }, 554 { ISD::SRA, MVT::v4i64, 1 }, 555 { ISD::SRA, MVT::v8i64, 1 }, 556 557 { ISD::MUL, MVT::v64i8, 26 }, // extend/pmullw/trunc sequence. 558 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence. 559 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence. 560 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 561 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 562 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 563 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add 564 565 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 566 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 567 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 568 569 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 570 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 571 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 572 }; 573 574 if (ST->hasAVX512()) 575 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 576 return LT.first * Entry->Cost; 577 578 static const CostTblEntry AVX2ShiftCostTable[] = { 579 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 580 // customize them to detect the cases where shift amount is a scalar one. 581 { ISD::SHL, MVT::v4i32, 1 }, 582 { ISD::SRL, MVT::v4i32, 1 }, 583 { ISD::SRA, MVT::v4i32, 1 }, 584 { ISD::SHL, MVT::v8i32, 1 }, 585 { ISD::SRL, MVT::v8i32, 1 }, 586 { ISD::SRA, MVT::v8i32, 1 }, 587 { ISD::SHL, MVT::v2i64, 1 }, 588 { ISD::SRL, MVT::v2i64, 1 }, 589 { ISD::SHL, MVT::v4i64, 1 }, 590 { ISD::SRL, MVT::v4i64, 1 }, 591 }; 592 593 if (ST->hasAVX512()) { 594 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 595 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 596 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 597 // On AVX512, a packed v32i16 shift left by a constant build_vector 598 // is lowered into a vector multiply (vpmullw). 599 return getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info, 600 TargetTransformInfo::OP_None, 601 TargetTransformInfo::OP_None); 602 } 603 604 // Look for AVX2 lowering tricks. 605 if (ST->hasAVX2()) { 606 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 607 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 608 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 609 // On AVX2, a packed v16i16 shift left by a constant build_vector 610 // is lowered into a vector multiply (vpmullw). 611 return getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info, 612 TargetTransformInfo::OP_None, 613 TargetTransformInfo::OP_None); 614 615 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 616 return LT.first * Entry->Cost; 617 } 618 619 static const CostTblEntry XOPShiftCostTable[] = { 620 // 128bit shifts take 1cy, but right shifts require negation beforehand. 621 { ISD::SHL, MVT::v16i8, 1 }, 622 { ISD::SRL, MVT::v16i8, 2 }, 623 { ISD::SRA, MVT::v16i8, 2 }, 624 { ISD::SHL, MVT::v8i16, 1 }, 625 { ISD::SRL, MVT::v8i16, 2 }, 626 { ISD::SRA, MVT::v8i16, 2 }, 627 { ISD::SHL, MVT::v4i32, 1 }, 628 { ISD::SRL, MVT::v4i32, 2 }, 629 { ISD::SRA, MVT::v4i32, 2 }, 630 { ISD::SHL, MVT::v2i64, 1 }, 631 { ISD::SRL, MVT::v2i64, 2 }, 632 { ISD::SRA, MVT::v2i64, 2 }, 633 // 256bit shifts require splitting if AVX2 didn't catch them above. 634 { ISD::SHL, MVT::v32i8, 2+2 }, 635 { ISD::SRL, MVT::v32i8, 4+2 }, 636 { ISD::SRA, MVT::v32i8, 4+2 }, 637 { ISD::SHL, MVT::v16i16, 2+2 }, 638 { ISD::SRL, MVT::v16i16, 4+2 }, 639 { ISD::SRA, MVT::v16i16, 4+2 }, 640 { ISD::SHL, MVT::v8i32, 2+2 }, 641 { ISD::SRL, MVT::v8i32, 4+2 }, 642 { ISD::SRA, MVT::v8i32, 4+2 }, 643 { ISD::SHL, MVT::v4i64, 2+2 }, 644 { ISD::SRL, MVT::v4i64, 4+2 }, 645 { ISD::SRA, MVT::v4i64, 4+2 }, 646 }; 647 648 // Look for XOP lowering tricks. 649 if (ST->hasXOP()) { 650 // If the right shift is constant then we'll fold the negation so 651 // it's as cheap as a left shift. 652 int ShiftISD = ISD; 653 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 654 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 655 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 656 ShiftISD = ISD::SHL; 657 if (const auto *Entry = 658 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 659 return LT.first * Entry->Cost; 660 } 661 662 static const CostTblEntry SSE2UniformShiftCostTable[] = { 663 // Uniform splats are cheaper for the following instructions. 664 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 665 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 666 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 667 668 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 669 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 670 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 671 672 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 673 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 674 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 675 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 676 }; 677 678 if (ST->hasSSE2() && 679 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 680 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 681 682 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 683 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 684 return LT.first * 4; // 2*psrad + shuffle. 685 686 if (const auto *Entry = 687 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 688 return LT.first * Entry->Cost; 689 } 690 691 if (ISD == ISD::SHL && 692 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 693 MVT VT = LT.second; 694 // Vector shift left by non uniform constant can be lowered 695 // into vector multiply. 696 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 697 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 698 ISD = ISD::MUL; 699 } 700 701 static const CostTblEntry AVX2CostTable[] = { 702 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. 703 { ISD::SHL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. 704 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 705 { ISD::SHL, MVT::v32i16, 20 }, // 2*extend/vpsrlvd/pack sequence. 706 707 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. 708 { ISD::SRL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. 709 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 710 { ISD::SRL, MVT::v32i16, 20 }, // 2*extend/vpsrlvd/pack sequence. 711 712 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. 713 { ISD::SRA, MVT::v64i8, 48 }, // 2*vpblendvb sequence. 714 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. 715 { ISD::SRA, MVT::v32i16, 20 }, // 2*extend/vpsravd/pack sequence. 716 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. 717 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 718 719 { ISD::SUB, MVT::v32i8, 1 }, // psubb 720 { ISD::ADD, MVT::v32i8, 1 }, // paddb 721 { ISD::SUB, MVT::v16i16, 1 }, // psubw 722 { ISD::ADD, MVT::v16i16, 1 }, // paddw 723 { ISD::SUB, MVT::v8i32, 1 }, // psubd 724 { ISD::ADD, MVT::v8i32, 1 }, // paddd 725 { ISD::SUB, MVT::v4i64, 1 }, // psubq 726 { ISD::ADD, MVT::v4i64, 1 }, // paddq 727 728 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence. 729 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence. 730 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 731 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 732 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add 733 734 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 735 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 736 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 737 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 738 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 739 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 740 741 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 742 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 743 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 744 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 745 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 746 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 747 }; 748 749 // Look for AVX2 lowering tricks for custom cases. 750 if (ST->hasAVX2()) 751 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 752 return LT.first * Entry->Cost; 753 754 static const CostTblEntry AVX1CostTable[] = { 755 // We don't have to scalarize unsupported ops. We can issue two half-sized 756 // operations and we only need to extract the upper YMM half. 757 // Two ops + 1 extract + 1 insert = 4. 758 { ISD::MUL, MVT::v16i16, 4 }, 759 { ISD::MUL, MVT::v8i32, 4 }, 760 { ISD::SUB, MVT::v32i8, 4 }, 761 { ISD::ADD, MVT::v32i8, 4 }, 762 { ISD::SUB, MVT::v16i16, 4 }, 763 { ISD::ADD, MVT::v16i16, 4 }, 764 { ISD::SUB, MVT::v8i32, 4 }, 765 { ISD::ADD, MVT::v8i32, 4 }, 766 { ISD::SUB, MVT::v4i64, 4 }, 767 { ISD::ADD, MVT::v4i64, 4 }, 768 769 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 770 // are lowered as a series of long multiplies(3), shifts(3) and adds(2) 771 // Because we believe v4i64 to be a legal type, we must also include the 772 // extract+insert in the cost table. Therefore, the cost here is 18 773 // instead of 8. 774 { ISD::MUL, MVT::v4i64, 18 }, 775 776 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence. 777 778 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 779 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 780 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 781 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 782 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 783 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 784 }; 785 786 if (ST->hasAVX()) 787 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 788 return LT.first * Entry->Cost; 789 790 static const CostTblEntry SSE42CostTable[] = { 791 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 792 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 793 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 794 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 795 796 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 797 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 798 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 799 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 800 801 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 802 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 803 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 804 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 805 806 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 807 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 808 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 809 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 810 }; 811 812 if (ST->hasSSE42()) 813 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 814 return LT.first * Entry->Cost; 815 816 static const CostTblEntry SSE41CostTable[] = { 817 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 818 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split. 819 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 820 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 821 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 822 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split 823 824 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 825 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split. 826 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 827 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 828 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 829 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split. 830 831 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 832 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split. 833 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 834 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 835 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 836 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split. 837 838 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 839 }; 840 841 if (ST->hasSSE41()) 842 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 843 return LT.first * Entry->Cost; 844 845 static const CostTblEntry SSE2CostTable[] = { 846 // We don't correctly identify costs of casts because they are marked as 847 // custom. 848 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 849 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 850 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 851 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 852 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 853 854 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 855 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 856 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 857 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 858 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 859 860 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 861 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 862 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 863 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 864 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split. 865 866 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence. 867 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 868 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 869 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 870 871 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 872 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 873 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 874 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 875 876 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 877 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 878 879 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 880 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 881 }; 882 883 if (ST->hasSSE2()) 884 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 885 return LT.first * Entry->Cost; 886 887 static const CostTblEntry SSE1CostTable[] = { 888 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 889 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 890 891 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 892 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 893 894 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 895 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 896 897 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 898 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 899 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 900 901 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 902 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 903 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 904 }; 905 906 if (ST->hasSSE1()) 907 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 908 return LT.first * Entry->Cost; 909 910 // It is not a good idea to vectorize division. We have to scalarize it and 911 // in the process we will often end up having to spilling regular 912 // registers. The overhead of division is going to dominate most kernels 913 // anyways so try hard to prevent vectorization of division - it is 914 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 915 // to hide "20 cycles" for each lane. 916 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 917 ISD == ISD::UDIV || ISD == ISD::UREM)) { 918 int ScalarCost = getArithmeticInstrCost( 919 Opcode, Ty->getScalarType(), Op1Info, Op2Info, 920 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 921 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 922 } 923 924 // Fallback to the default implementation. 925 return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info); 926 } 927 928 int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, VectorType *BaseTp, 929 int Index, VectorType *SubTp) { 930 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 931 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 932 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 933 934 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 935 if (Kind == TTI::SK_Transpose) 936 Kind = TTI::SK_PermuteTwoSrc; 937 938 // For Broadcasts we are splatting the first element from the first input 939 // register, so only need to reference that input and all the output 940 // registers are the same. 941 if (Kind == TTI::SK_Broadcast) 942 LT.first = 1; 943 944 // Subvector extractions are free if they start at the beginning of a 945 // vector and cheap if the subvectors are aligned. 946 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 947 int NumElts = LT.second.getVectorNumElements(); 948 if ((Index % NumElts) == 0) 949 return 0; 950 std::pair<int, MVT> SubLT = TLI->getTypeLegalizationCost(DL, SubTp); 951 if (SubLT.second.isVector()) { 952 int NumSubElts = SubLT.second.getVectorNumElements(); 953 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 954 return SubLT.first; 955 // Handle some cases for widening legalization. For now we only handle 956 // cases where the original subvector was naturally aligned and evenly 957 // fit in its legalized subvector type. 958 // FIXME: Remove some of the alignment restrictions. 959 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 960 // vectors. 961 int OrigSubElts = cast<VectorType>(SubTp)->getNumElements(); 962 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 963 (NumSubElts % OrigSubElts) == 0 && 964 LT.second.getVectorElementType() == 965 SubLT.second.getVectorElementType() && 966 LT.second.getVectorElementType().getSizeInBits() == 967 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 968 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 969 "Unexpected number of elements!"); 970 VectorType *VecTy = VectorType::get(BaseTp->getElementType(), 971 LT.second.getVectorNumElements()); 972 VectorType *SubTy = 973 VectorType::get(BaseTp->getElementType(), 974 SubLT.second.getVectorNumElements()); 975 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 976 int ExtractCost = getShuffleCost(TTI::SK_ExtractSubvector, VecTy, 977 ExtractIndex, SubTy); 978 979 // If the original size is 32-bits or more, we can use pshufd. Otherwise 980 // if we have SSSE3 we can use pshufb. 981 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 982 return ExtractCost + 1; // pshufd or pshufb 983 984 assert(SubTp->getPrimitiveSizeInBits() == 16 && 985 "Unexpected vector size"); 986 987 return ExtractCost + 2; // worst case pshufhw + pshufd 988 } 989 } 990 } 991 992 // Handle some common (illegal) sub-vector types as they are often very cheap 993 // to shuffle even on targets without PSHUFB. 994 EVT VT = TLI->getValueType(DL, BaseTp); 995 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 996 !ST->hasSSSE3()) { 997 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 998 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 999 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1000 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1001 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1002 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1003 1004 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1005 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1006 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1007 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1008 1009 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1010 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1011 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1012 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1013 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1014 1015 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1016 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1017 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1018 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1019 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1020 }; 1021 1022 if (ST->hasSSE2()) 1023 if (const auto *Entry = 1024 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1025 return Entry->Cost; 1026 } 1027 1028 // We are going to permute multiple sources and the result will be in multiple 1029 // destinations. Providing an accurate cost only for splits where the element 1030 // type remains the same. 1031 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1032 MVT LegalVT = LT.second; 1033 if (LegalVT.isVector() && 1034 LegalVT.getVectorElementType().getSizeInBits() == 1035 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1036 LegalVT.getVectorNumElements() < BaseTp->getNumElements()) { 1037 1038 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1039 unsigned LegalVTSize = LegalVT.getStoreSize(); 1040 // Number of source vectors after legalization: 1041 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1042 // Number of destination vectors after legalization: 1043 unsigned NumOfDests = LT.first; 1044 1045 VectorType *SingleOpTy = 1046 VectorType::get(BaseTp->getElementType(), 1047 LegalVT.getVectorNumElements()); 1048 1049 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1050 return NumOfShuffles * 1051 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 0, nullptr); 1052 } 1053 1054 return BaseT::getShuffleCost(Kind, BaseTp, Index, SubTp); 1055 } 1056 1057 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1058 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1059 // We assume that source and destination have the same vector type. 1060 int NumOfDests = LT.first; 1061 int NumOfShufflesPerDest = LT.first * 2 - 1; 1062 LT.first = NumOfDests * NumOfShufflesPerDest; 1063 } 1064 1065 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1066 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1067 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1068 1069 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1070 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1071 1072 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 1}, // vpermt2b 1073 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 1}, // vpermt2b 1074 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1} // vpermt2b 1075 }; 1076 1077 if (ST->hasVBMI()) 1078 if (const auto *Entry = 1079 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1080 return LT.first * Entry->Cost; 1081 1082 static const CostTblEntry AVX512BWShuffleTbl[] = { 1083 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1084 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1085 1086 {TTI::SK_Reverse, MVT::v32i16, 1}, // vpermw 1087 {TTI::SK_Reverse, MVT::v16i16, 1}, // vpermw 1088 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1089 1090 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 1}, // vpermw 1091 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 1}, // vpermw 1092 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // vpermw 1093 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1094 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 3}, // vpermw + zext/trunc 1095 1096 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 1}, // vpermt2w 1097 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 1}, // vpermt2w 1098 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpermt2w 1099 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 3}, // zext + vpermt2w + trunc 1100 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1101 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3} // zext + vpermt2w + trunc 1102 }; 1103 1104 if (ST->hasBWI()) 1105 if (const auto *Entry = 1106 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1107 return LT.first * Entry->Cost; 1108 1109 static const CostTblEntry AVX512ShuffleTbl[] = { 1110 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1111 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1112 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1113 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1114 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1115 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1116 1117 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1118 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1119 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1120 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1121 1122 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1123 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1124 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1125 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1126 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1127 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1128 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1129 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1130 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1131 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1132 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1133 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1134 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1135 1136 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1137 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1138 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1139 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1140 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1141 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1142 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1143 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1144 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1145 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1146 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1147 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1148 1149 // FIXME: This just applies the type legalization cost rules above 1150 // assuming these completely split. 1151 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1152 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1153 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1154 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1155 }; 1156 1157 if (ST->hasAVX512()) 1158 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1159 return LT.first * Entry->Cost; 1160 1161 static const CostTblEntry AVX2ShuffleTbl[] = { 1162 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1163 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1164 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1165 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1166 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1167 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1168 1169 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1170 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1171 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1172 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1173 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1174 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1175 1176 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1177 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1178 1179 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1180 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1181 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1182 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1183 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1184 // + vpblendvb 1185 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1186 // + vpblendvb 1187 1188 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1189 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1190 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1191 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1192 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1193 // + vpblendvb 1194 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1195 // + vpblendvb 1196 }; 1197 1198 if (ST->hasAVX2()) 1199 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1200 return LT.first * Entry->Cost; 1201 1202 static const CostTblEntry XOPShuffleTbl[] = { 1203 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1204 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1205 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1206 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1207 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1208 // + vinsertf128 1209 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1210 // + vinsertf128 1211 1212 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1213 // + vinsertf128 1214 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1215 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1216 // + vinsertf128 1217 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1218 }; 1219 1220 if (ST->hasXOP()) 1221 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1222 return LT.first * Entry->Cost; 1223 1224 static const CostTblEntry AVX1ShuffleTbl[] = { 1225 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1226 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1227 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1228 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1229 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1230 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1231 1232 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1233 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1234 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1235 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1236 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1237 // + vinsertf128 1238 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1239 // + vinsertf128 1240 1241 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1242 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1243 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1244 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1245 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1246 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1247 1248 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1249 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1250 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1251 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1252 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1253 // + 2*por + vinsertf128 1254 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1255 // + 2*por + vinsertf128 1256 1257 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1258 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1259 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1260 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1261 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1262 // + 4*por + vinsertf128 1263 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1264 // + 4*por + vinsertf128 1265 }; 1266 1267 if (ST->hasAVX()) 1268 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1269 return LT.first * Entry->Cost; 1270 1271 static const CostTblEntry SSE41ShuffleTbl[] = { 1272 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1273 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1274 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1275 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1276 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1277 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1278 }; 1279 1280 if (ST->hasSSE41()) 1281 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1282 return LT.first * Entry->Cost; 1283 1284 static const CostTblEntry SSSE3ShuffleTbl[] = { 1285 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1286 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1287 1288 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1289 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1290 1291 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1292 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1293 1294 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1295 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1296 1297 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1298 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1299 }; 1300 1301 if (ST->hasSSSE3()) 1302 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1303 return LT.first * Entry->Cost; 1304 1305 static const CostTblEntry SSE2ShuffleTbl[] = { 1306 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1307 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1308 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1309 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1310 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1311 1312 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1313 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1314 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1315 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1316 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1317 // + 2*pshufd + 2*unpck + packus 1318 1319 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1320 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1321 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1322 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1323 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1324 1325 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1326 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1327 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1328 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1329 // + pshufd/unpck 1330 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1331 // + 2*pshufd + 2*unpck + 2*packus 1332 1333 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1334 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1335 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1336 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1337 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1338 }; 1339 1340 if (ST->hasSSE2()) 1341 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1342 return LT.first * Entry->Cost; 1343 1344 static const CostTblEntry SSE1ShuffleTbl[] = { 1345 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1346 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1347 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1348 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1349 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1350 }; 1351 1352 if (ST->hasSSE1()) 1353 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1354 return LT.first * Entry->Cost; 1355 1356 return BaseT::getShuffleCost(Kind, BaseTp, Index, SubTp); 1357 } 1358 1359 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 1360 const Instruction *I) { 1361 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1362 assert(ISD && "Invalid opcode"); 1363 1364 // FIXME: Need a better design of the cost table to handle non-simple types of 1365 // potential massive combinations (elem_num x src_type x dst_type). 1366 1367 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1368 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1369 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1370 1371 // Mask sign extend has an instruction. 1372 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1373 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1374 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1375 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1376 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1377 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1378 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1379 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1380 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1381 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1382 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1383 1384 // Mask zero extend is a sext + shift. 1385 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1386 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1387 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1388 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1389 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1390 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1391 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1392 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1393 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1394 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1395 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1396 1397 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, 1398 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm 1399 }; 1400 1401 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1402 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1403 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1404 1405 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1406 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1407 1408 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1409 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1410 1411 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1412 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1413 }; 1414 1415 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1416 // 256-bit wide vectors. 1417 1418 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1419 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1420 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1421 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1422 1423 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, 1424 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, 1425 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, 1426 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, 1427 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 1428 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb 1429 1430 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32 1431 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, 1432 1433 // Sign extend is zmm vpternlogd+vptruncdb. 1434 // Zero extend is zmm broadcast load+vptruncdw. 1435 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 }, 1436 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 }, 1437 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, 1438 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, 1439 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, 1440 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, 1441 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 }, 1442 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 }, 1443 1444 // Sign extend is zmm vpternlogd+vptruncdw. 1445 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw. 1446 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 }, 1447 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1448 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 }, 1449 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1450 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 }, 1451 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1452 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 }, 1453 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1454 1455 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd 1456 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld 1457 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd 1458 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld 1459 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd 1460 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld 1461 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq 1462 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq 1463 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq 1464 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq 1465 1466 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd 1467 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld 1468 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq 1469 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq 1470 1471 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1472 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1473 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1474 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1475 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1476 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1477 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1478 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1479 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1480 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1481 1482 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1483 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1484 1485 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1486 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1487 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1488 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1489 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1490 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1491 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1492 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1493 1494 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1495 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1496 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1497 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1498 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1499 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1500 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1501 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1502 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1503 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1504 1505 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f64, 3 }, 1506 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, 1507 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 3 }, 1508 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 3 }, 1509 1510 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1511 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, 1512 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, 1513 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1514 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, 1515 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, 1516 }; 1517 1518 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1519 // Mask sign extend has an instruction. 1520 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1521 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1522 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1523 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1524 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1525 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1526 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1527 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1528 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1529 1530 // Mask zero extend is a sext + shift. 1531 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1532 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1533 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1534 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1535 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1536 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1537 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1538 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1539 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1540 1541 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, 1542 }; 1543 1544 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1545 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1546 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1547 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1548 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1549 1550 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1551 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1552 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1553 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1554 1555 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1556 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1557 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1558 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1559 1560 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1561 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1562 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1563 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1564 }; 1565 1566 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 1567 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb 1568 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb 1569 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 }, 1570 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 }, 1571 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 }, 1572 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 }, 1573 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 }, 1574 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 }, 1575 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 }, 1576 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 }, 1577 1578 // sign extend is vpcmpeq+maskedmove+vpmovdw 1579 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw 1580 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1581 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 }, 1582 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1583 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 }, 1584 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1585 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 }, 1586 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 }, 1587 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 }, 1588 1589 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd 1590 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld 1591 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd 1592 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld 1593 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd 1594 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld 1595 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq 1596 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq 1597 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq 1598 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq 1599 1600 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1601 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1602 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1603 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1604 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1605 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1606 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1607 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1608 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1609 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1610 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1611 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1612 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1613 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1614 1615 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 1616 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1617 1618 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 3 }, 1619 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 3 }, 1620 1621 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 1622 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 1623 1624 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1625 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1626 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 1 }, 1627 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1628 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1629 }; 1630 1631 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1632 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1633 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1634 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1635 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1636 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1637 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1638 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1639 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1640 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1641 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1642 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1643 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1644 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1645 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1646 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1647 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1648 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1649 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1650 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1651 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1652 1653 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 1654 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 1655 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1656 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 1657 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1658 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 }, 1659 1660 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1661 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1662 1663 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1664 }; 1665 1666 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1667 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1668 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1669 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1670 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1671 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1672 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1673 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1674 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1675 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1676 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1677 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1678 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1679 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 4 }, 1680 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1681 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1682 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1683 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1684 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1685 1686 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 1687 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1688 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1689 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1690 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 1691 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 }, 1692 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 11 }, 1693 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 9 }, 1694 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 }, 1695 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 11 }, 1696 1697 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1698 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1699 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1700 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1701 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1702 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1703 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1704 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1705 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1706 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1707 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1708 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1709 1710 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1711 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1712 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1713 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1714 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1715 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1716 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1717 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1718 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1719 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 }, 1720 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 1721 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1722 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 1723 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1724 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1725 // The generic code to compute the scalar overhead is currently broken. 1726 // Workaround this limitation by estimating the scalarization overhead 1727 // here. We have roughly 10 instructions per scalar element. 1728 // Multiply that by the vector width. 1729 // FIXME: remove that when PR19268 is fixed. 1730 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1731 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1732 1733 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 4 }, 1734 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f64, 3 }, 1735 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f64, 2 }, 1736 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 3 }, 1737 1738 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f64, 3 }, 1739 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f64, 2 }, 1740 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 4 }, 1741 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 3 }, 1742 // This node is expanded into scalarized operations but BasicTTI is overly 1743 // optimistic estimating its cost. It computes 3 per element (one 1744 // vector-extract, one scalar conversion and one vector-insert). The 1745 // problem is that the inserts form a read-modify-write chain so latency 1746 // should be factored in too. Inflating the cost per element by 1. 1747 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, 1748 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 1749 1750 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 1751 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 1752 }; 1753 1754 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 1755 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1756 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1757 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1758 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1759 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1760 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1761 1762 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1763 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 }, 1764 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1765 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1766 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1767 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1768 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1769 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1770 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1771 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1772 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1773 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1774 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1775 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1776 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1777 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1778 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1779 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1780 1781 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, 1782 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 1783 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 1784 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 1785 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 1786 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 1787 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 1788 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 1 }, // PSHUFB 1789 1790 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 1791 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 1792 1793 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 3 }, 1794 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 3 }, 1795 1796 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 3 }, 1797 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 3 }, 1798 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, 1799 }; 1800 1801 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 1802 // These are somewhat magic numbers justified by looking at the output of 1803 // Intel's IACA, running some kernels and making sure when we take 1804 // legalization into account the throughput will be overestimated. 1805 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1806 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1807 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1808 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1809 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1810 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 2*10 }, 1811 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2*10 }, 1812 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1813 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 1814 1815 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1816 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1817 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1818 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1819 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1820 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, 1821 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 }, 1822 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1823 1824 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 4 }, 1825 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 2 }, 1826 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, 1827 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, 1828 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, 1829 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 4 }, 1830 1831 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 1 }, 1832 1833 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 6 }, 1834 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 }, 1835 1836 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 1837 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 1838 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 4 }, 1839 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 4 }, 1840 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 }, 1841 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 2 }, 1842 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 }, 1843 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 4 }, 1844 1845 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1846 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 1847 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 1848 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 1849 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1850 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 1851 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1852 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 1853 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1854 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1855 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1856 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1857 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 1858 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 1859 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1860 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 1861 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1862 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 1863 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1864 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1865 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 1866 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 1867 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1868 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 1869 1870 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // PAND+PACKUSWB 1871 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 4 }, 1872 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, 1873 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 1874 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 3 }, // PAND+3*PACKUSWB 1875 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 1876 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 1877 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 1878 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1879 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 1880 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1881 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 1882 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 1883 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 1884 { ISD::TRUNCATE, MVT::v2i32, MVT::v2i64, 1 }, // PSHUFD 1885 }; 1886 1887 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 1888 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst); 1889 1890 if (ST->hasSSE2() && !ST->hasAVX()) { 1891 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1892 LTDest.second, LTSrc.second)) 1893 return LTSrc.first * Entry->Cost; 1894 } 1895 1896 EVT SrcTy = TLI->getValueType(DL, Src); 1897 EVT DstTy = TLI->getValueType(DL, Dst); 1898 1899 // The function getSimpleVT only handles simple value types. 1900 if (!SrcTy.isSimple() || !DstTy.isSimple()) 1901 return BaseT::getCastInstrCost(Opcode, Dst, Src); 1902 1903 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 1904 MVT SimpleDstTy = DstTy.getSimpleVT(); 1905 1906 if (ST->useAVX512Regs()) { 1907 if (ST->hasBWI()) 1908 if (const auto *Entry = ConvertCostTableLookup(AVX512BWConversionTbl, ISD, 1909 SimpleDstTy, SimpleSrcTy)) 1910 return Entry->Cost; 1911 1912 if (ST->hasDQI()) 1913 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 1914 SimpleDstTy, SimpleSrcTy)) 1915 return Entry->Cost; 1916 1917 if (ST->hasAVX512()) 1918 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 1919 SimpleDstTy, SimpleSrcTy)) 1920 return Entry->Cost; 1921 } 1922 1923 if (ST->hasBWI()) 1924 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 1925 SimpleDstTy, SimpleSrcTy)) 1926 return Entry->Cost; 1927 1928 if (ST->hasDQI()) 1929 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 1930 SimpleDstTy, SimpleSrcTy)) 1931 return Entry->Cost; 1932 1933 if (ST->hasAVX512()) 1934 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 1935 SimpleDstTy, SimpleSrcTy)) 1936 return Entry->Cost; 1937 1938 if (ST->hasAVX2()) { 1939 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 1940 SimpleDstTy, SimpleSrcTy)) 1941 return Entry->Cost; 1942 } 1943 1944 if (ST->hasAVX()) { 1945 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 1946 SimpleDstTy, SimpleSrcTy)) 1947 return Entry->Cost; 1948 } 1949 1950 if (ST->hasSSE41()) { 1951 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 1952 SimpleDstTy, SimpleSrcTy)) 1953 return Entry->Cost; 1954 } 1955 1956 if (ST->hasSSE2()) { 1957 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1958 SimpleDstTy, SimpleSrcTy)) 1959 return Entry->Cost; 1960 } 1961 1962 return BaseT::getCastInstrCost(Opcode, Dst, Src, I); 1963 } 1964 1965 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 1966 const Instruction *I) { 1967 // Legalize the type. 1968 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 1969 1970 MVT MTy = LT.second; 1971 1972 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1973 assert(ISD && "Invalid opcode"); 1974 1975 unsigned ExtraCost = 0; 1976 if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) { 1977 // Some vector comparison predicates cost extra instructions. 1978 if (MTy.isVector() && 1979 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 1980 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 1981 ST->hasBWI())) { 1982 switch (cast<CmpInst>(I)->getPredicate()) { 1983 case CmpInst::Predicate::ICMP_NE: 1984 // xor(cmpeq(x,y),-1) 1985 ExtraCost = 1; 1986 break; 1987 case CmpInst::Predicate::ICMP_SGE: 1988 case CmpInst::Predicate::ICMP_SLE: 1989 // xor(cmpgt(x,y),-1) 1990 ExtraCost = 1; 1991 break; 1992 case CmpInst::Predicate::ICMP_ULT: 1993 case CmpInst::Predicate::ICMP_UGT: 1994 // cmpgt(xor(x,signbit),xor(y,signbit)) 1995 // xor(cmpeq(pmaxu(x,y),x),-1) 1996 ExtraCost = 2; 1997 break; 1998 case CmpInst::Predicate::ICMP_ULE: 1999 case CmpInst::Predicate::ICMP_UGE: 2000 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 2001 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 2002 // cmpeq(psubus(x,y),0) 2003 // cmpeq(pminu(x,y),x) 2004 ExtraCost = 1; 2005 } else { 2006 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 2007 ExtraCost = 3; 2008 } 2009 break; 2010 default: 2011 break; 2012 } 2013 } 2014 } 2015 2016 static const CostTblEntry SLMCostTbl[] = { 2017 // slm pcmpeq/pcmpgt throughput is 2 2018 { ISD::SETCC, MVT::v2i64, 2 }, 2019 }; 2020 2021 static const CostTblEntry AVX512BWCostTbl[] = { 2022 { ISD::SETCC, MVT::v32i16, 1 }, 2023 { ISD::SETCC, MVT::v64i8, 1 }, 2024 2025 { ISD::SELECT, MVT::v32i16, 1 }, 2026 { ISD::SELECT, MVT::v64i8, 1 }, 2027 }; 2028 2029 static const CostTblEntry AVX512CostTbl[] = { 2030 { ISD::SETCC, MVT::v8i64, 1 }, 2031 { ISD::SETCC, MVT::v16i32, 1 }, 2032 { ISD::SETCC, MVT::v8f64, 1 }, 2033 { ISD::SETCC, MVT::v16f32, 1 }, 2034 2035 { ISD::SELECT, MVT::v8i64, 1 }, 2036 { ISD::SELECT, MVT::v16i32, 1 }, 2037 { ISD::SELECT, MVT::v8f64, 1 }, 2038 { ISD::SELECT, MVT::v16f32, 1 }, 2039 2040 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 2041 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 2042 2043 { ISD::SELECT, MVT::v32i16, 2 }, // FIXME: should be 3 2044 { ISD::SELECT, MVT::v64i8, 2 }, // FIXME: should be 3 2045 }; 2046 2047 static const CostTblEntry AVX2CostTbl[] = { 2048 { ISD::SETCC, MVT::v4i64, 1 }, 2049 { ISD::SETCC, MVT::v8i32, 1 }, 2050 { ISD::SETCC, MVT::v16i16, 1 }, 2051 { ISD::SETCC, MVT::v32i8, 1 }, 2052 2053 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 2054 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 2055 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 2056 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 2057 }; 2058 2059 static const CostTblEntry AVX1CostTbl[] = { 2060 { ISD::SETCC, MVT::v4f64, 1 }, 2061 { ISD::SETCC, MVT::v8f32, 1 }, 2062 // AVX1 does not support 8-wide integer compare. 2063 { ISD::SETCC, MVT::v4i64, 4 }, 2064 { ISD::SETCC, MVT::v8i32, 4 }, 2065 { ISD::SETCC, MVT::v16i16, 4 }, 2066 { ISD::SETCC, MVT::v32i8, 4 }, 2067 2068 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 2069 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 2070 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 2071 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 2072 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 2073 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 2074 }; 2075 2076 static const CostTblEntry SSE42CostTbl[] = { 2077 { ISD::SETCC, MVT::v2f64, 1 }, 2078 { ISD::SETCC, MVT::v4f32, 1 }, 2079 { ISD::SETCC, MVT::v2i64, 1 }, 2080 }; 2081 2082 static const CostTblEntry SSE41CostTbl[] = { 2083 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 2084 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 2085 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 2086 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 2087 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 2088 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 2089 }; 2090 2091 static const CostTblEntry SSE2CostTbl[] = { 2092 { ISD::SETCC, MVT::v2f64, 2 }, 2093 { ISD::SETCC, MVT::f64, 1 }, 2094 { ISD::SETCC, MVT::v2i64, 8 }, 2095 { ISD::SETCC, MVT::v4i32, 1 }, 2096 { ISD::SETCC, MVT::v8i16, 1 }, 2097 { ISD::SETCC, MVT::v16i8, 1 }, 2098 2099 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 2100 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 2101 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 2102 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 2103 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 2104 }; 2105 2106 static const CostTblEntry SSE1CostTbl[] = { 2107 { ISD::SETCC, MVT::v4f32, 2 }, 2108 { ISD::SETCC, MVT::f32, 1 }, 2109 2110 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 2111 }; 2112 2113 if (ST->isSLM()) 2114 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2115 return LT.first * (ExtraCost + Entry->Cost); 2116 2117 if (ST->hasBWI()) 2118 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2119 return LT.first * (ExtraCost + Entry->Cost); 2120 2121 if (ST->hasAVX512()) 2122 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2123 return LT.first * (ExtraCost + Entry->Cost); 2124 2125 if (ST->hasAVX2()) 2126 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2127 return LT.first * (ExtraCost + Entry->Cost); 2128 2129 if (ST->hasAVX()) 2130 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2131 return LT.first * (ExtraCost + Entry->Cost); 2132 2133 if (ST->hasSSE42()) 2134 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2135 return LT.first * (ExtraCost + Entry->Cost); 2136 2137 if (ST->hasSSE41()) 2138 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2139 return LT.first * (ExtraCost + Entry->Cost); 2140 2141 if (ST->hasSSE2()) 2142 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2143 return LT.first * (ExtraCost + Entry->Cost); 2144 2145 if (ST->hasSSE1()) 2146 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2147 return LT.first * (ExtraCost + Entry->Cost); 2148 2149 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I); 2150 } 2151 2152 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2153 2154 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 2155 ArrayRef<Type *> Tys, FastMathFlags FMF, 2156 unsigned ScalarizationCostPassed, 2157 const Instruction *I) { 2158 // Costs should match the codegen from: 2159 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2160 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2161 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2162 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2163 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2164 static const CostTblEntry AVX512CDCostTbl[] = { 2165 { ISD::CTLZ, MVT::v8i64, 1 }, 2166 { ISD::CTLZ, MVT::v16i32, 1 }, 2167 { ISD::CTLZ, MVT::v32i16, 8 }, 2168 { ISD::CTLZ, MVT::v64i8, 20 }, 2169 { ISD::CTLZ, MVT::v4i64, 1 }, 2170 { ISD::CTLZ, MVT::v8i32, 1 }, 2171 { ISD::CTLZ, MVT::v16i16, 4 }, 2172 { ISD::CTLZ, MVT::v32i8, 10 }, 2173 { ISD::CTLZ, MVT::v2i64, 1 }, 2174 { ISD::CTLZ, MVT::v4i32, 1 }, 2175 { ISD::CTLZ, MVT::v8i16, 4 }, 2176 { ISD::CTLZ, MVT::v16i8, 4 }, 2177 }; 2178 static const CostTblEntry AVX512BWCostTbl[] = { 2179 { ISD::BITREVERSE, MVT::v8i64, 5 }, 2180 { ISD::BITREVERSE, MVT::v16i32, 5 }, 2181 { ISD::BITREVERSE, MVT::v32i16, 5 }, 2182 { ISD::BITREVERSE, MVT::v64i8, 5 }, 2183 { ISD::CTLZ, MVT::v8i64, 23 }, 2184 { ISD::CTLZ, MVT::v16i32, 22 }, 2185 { ISD::CTLZ, MVT::v32i16, 18 }, 2186 { ISD::CTLZ, MVT::v64i8, 17 }, 2187 { ISD::CTPOP, MVT::v8i64, 7 }, 2188 { ISD::CTPOP, MVT::v16i32, 11 }, 2189 { ISD::CTPOP, MVT::v32i16, 9 }, 2190 { ISD::CTPOP, MVT::v64i8, 6 }, 2191 { ISD::CTTZ, MVT::v8i64, 10 }, 2192 { ISD::CTTZ, MVT::v16i32, 14 }, 2193 { ISD::CTTZ, MVT::v32i16, 12 }, 2194 { ISD::CTTZ, MVT::v64i8, 9 }, 2195 { ISD::SADDSAT, MVT::v32i16, 1 }, 2196 { ISD::SADDSAT, MVT::v64i8, 1 }, 2197 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2198 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2199 { ISD::UADDSAT, MVT::v32i16, 1 }, 2200 { ISD::UADDSAT, MVT::v64i8, 1 }, 2201 { ISD::USUBSAT, MVT::v32i16, 1 }, 2202 { ISD::USUBSAT, MVT::v64i8, 1 }, 2203 }; 2204 static const CostTblEntry AVX512CostTbl[] = { 2205 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2206 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2207 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2208 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2209 { ISD::CTLZ, MVT::v8i64, 29 }, 2210 { ISD::CTLZ, MVT::v16i32, 35 }, 2211 { ISD::CTLZ, MVT::v32i16, 28 }, 2212 { ISD::CTLZ, MVT::v64i8, 18 }, 2213 { ISD::CTPOP, MVT::v8i64, 16 }, 2214 { ISD::CTPOP, MVT::v16i32, 24 }, 2215 { ISD::CTPOP, MVT::v32i16, 18 }, 2216 { ISD::CTPOP, MVT::v64i8, 12 }, 2217 { ISD::CTTZ, MVT::v8i64, 20 }, 2218 { ISD::CTTZ, MVT::v16i32, 28 }, 2219 { ISD::CTTZ, MVT::v32i16, 24 }, 2220 { ISD::CTTZ, MVT::v64i8, 18 }, 2221 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2222 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2223 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2224 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2225 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2226 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2227 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2228 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2229 { ISD::SADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2230 { ISD::SADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2231 { ISD::SSUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2232 { ISD::SSUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2233 { ISD::UADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2234 { ISD::UADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2235 { ISD::USUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2236 { ISD::USUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2237 { ISD::FMAXNUM, MVT::f32, 2 }, 2238 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2239 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2240 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2241 { ISD::FMAXNUM, MVT::f64, 2 }, 2242 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2243 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2244 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2245 }; 2246 static const CostTblEntry XOPCostTbl[] = { 2247 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2248 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2249 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2250 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2251 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2252 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2253 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2254 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2255 { ISD::BITREVERSE, MVT::i64, 3 }, 2256 { ISD::BITREVERSE, MVT::i32, 3 }, 2257 { ISD::BITREVERSE, MVT::i16, 3 }, 2258 { ISD::BITREVERSE, MVT::i8, 3 } 2259 }; 2260 static const CostTblEntry AVX2CostTbl[] = { 2261 { ISD::BITREVERSE, MVT::v4i64, 5 }, 2262 { ISD::BITREVERSE, MVT::v8i32, 5 }, 2263 { ISD::BITREVERSE, MVT::v16i16, 5 }, 2264 { ISD::BITREVERSE, MVT::v32i8, 5 }, 2265 { ISD::BSWAP, MVT::v4i64, 1 }, 2266 { ISD::BSWAP, MVT::v8i32, 1 }, 2267 { ISD::BSWAP, MVT::v16i16, 1 }, 2268 { ISD::CTLZ, MVT::v4i64, 23 }, 2269 { ISD::CTLZ, MVT::v8i32, 18 }, 2270 { ISD::CTLZ, MVT::v16i16, 14 }, 2271 { ISD::CTLZ, MVT::v32i8, 9 }, 2272 { ISD::CTPOP, MVT::v4i64, 7 }, 2273 { ISD::CTPOP, MVT::v8i32, 11 }, 2274 { ISD::CTPOP, MVT::v16i16, 9 }, 2275 { ISD::CTPOP, MVT::v32i8, 6 }, 2276 { ISD::CTTZ, MVT::v4i64, 10 }, 2277 { ISD::CTTZ, MVT::v8i32, 14 }, 2278 { ISD::CTTZ, MVT::v16i16, 12 }, 2279 { ISD::CTTZ, MVT::v32i8, 9 }, 2280 { ISD::SADDSAT, MVT::v16i16, 1 }, 2281 { ISD::SADDSAT, MVT::v32i8, 1 }, 2282 { ISD::SSUBSAT, MVT::v16i16, 1 }, 2283 { ISD::SSUBSAT, MVT::v32i8, 1 }, 2284 { ISD::UADDSAT, MVT::v16i16, 1 }, 2285 { ISD::UADDSAT, MVT::v32i8, 1 }, 2286 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 2287 { ISD::USUBSAT, MVT::v16i16, 1 }, 2288 { ISD::USUBSAT, MVT::v32i8, 1 }, 2289 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2290 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2291 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2292 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2293 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2294 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2295 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2296 }; 2297 static const CostTblEntry AVX1CostTbl[] = { 2298 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 2299 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 2300 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 2301 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 2302 { ISD::BSWAP, MVT::v4i64, 4 }, 2303 { ISD::BSWAP, MVT::v8i32, 4 }, 2304 { ISD::BSWAP, MVT::v16i16, 4 }, 2305 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 2306 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 2307 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 2308 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2309 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 2310 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 2311 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 2312 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 2313 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 2314 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 2315 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 2316 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2317 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2318 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2319 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2320 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2321 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2322 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2323 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 2324 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2325 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2326 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 2327 { ISD::FMAXNUM, MVT::f32, 3 }, 2328 { ISD::FMAXNUM, MVT::v4f32, 3 }, 2329 { ISD::FMAXNUM, MVT::v8f32, 5 }, 2330 { ISD::FMAXNUM, MVT::f64, 3 }, 2331 { ISD::FMAXNUM, MVT::v2f64, 3 }, 2332 { ISD::FMAXNUM, MVT::v4f64, 5 }, 2333 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 2334 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 2335 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 2336 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 2337 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 2338 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 2339 }; 2340 static const CostTblEntry GLMCostTbl[] = { 2341 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 2342 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 2343 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 2344 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 2345 }; 2346 static const CostTblEntry SLMCostTbl[] = { 2347 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 2348 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 2349 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 2350 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 2351 }; 2352 static const CostTblEntry SSE42CostTbl[] = { 2353 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 2354 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 2355 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 2356 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 2357 }; 2358 static const CostTblEntry SSSE3CostTbl[] = { 2359 { ISD::BITREVERSE, MVT::v2i64, 5 }, 2360 { ISD::BITREVERSE, MVT::v4i32, 5 }, 2361 { ISD::BITREVERSE, MVT::v8i16, 5 }, 2362 { ISD::BITREVERSE, MVT::v16i8, 5 }, 2363 { ISD::BSWAP, MVT::v2i64, 1 }, 2364 { ISD::BSWAP, MVT::v4i32, 1 }, 2365 { ISD::BSWAP, MVT::v8i16, 1 }, 2366 { ISD::CTLZ, MVT::v2i64, 23 }, 2367 { ISD::CTLZ, MVT::v4i32, 18 }, 2368 { ISD::CTLZ, MVT::v8i16, 14 }, 2369 { ISD::CTLZ, MVT::v16i8, 9 }, 2370 { ISD::CTPOP, MVT::v2i64, 7 }, 2371 { ISD::CTPOP, MVT::v4i32, 11 }, 2372 { ISD::CTPOP, MVT::v8i16, 9 }, 2373 { ISD::CTPOP, MVT::v16i8, 6 }, 2374 { ISD::CTTZ, MVT::v2i64, 10 }, 2375 { ISD::CTTZ, MVT::v4i32, 14 }, 2376 { ISD::CTTZ, MVT::v8i16, 12 }, 2377 { ISD::CTTZ, MVT::v16i8, 9 } 2378 }; 2379 static const CostTblEntry SSE2CostTbl[] = { 2380 { ISD::BITREVERSE, MVT::v2i64, 29 }, 2381 { ISD::BITREVERSE, MVT::v4i32, 27 }, 2382 { ISD::BITREVERSE, MVT::v8i16, 27 }, 2383 { ISD::BITREVERSE, MVT::v16i8, 20 }, 2384 { ISD::BSWAP, MVT::v2i64, 7 }, 2385 { ISD::BSWAP, MVT::v4i32, 7 }, 2386 { ISD::BSWAP, MVT::v8i16, 7 }, 2387 { ISD::CTLZ, MVT::v2i64, 25 }, 2388 { ISD::CTLZ, MVT::v4i32, 26 }, 2389 { ISD::CTLZ, MVT::v8i16, 20 }, 2390 { ISD::CTLZ, MVT::v16i8, 17 }, 2391 { ISD::CTPOP, MVT::v2i64, 12 }, 2392 { ISD::CTPOP, MVT::v4i32, 15 }, 2393 { ISD::CTPOP, MVT::v8i16, 13 }, 2394 { ISD::CTPOP, MVT::v16i8, 10 }, 2395 { ISD::CTTZ, MVT::v2i64, 14 }, 2396 { ISD::CTTZ, MVT::v4i32, 18 }, 2397 { ISD::CTTZ, MVT::v8i16, 16 }, 2398 { ISD::CTTZ, MVT::v16i8, 13 }, 2399 { ISD::SADDSAT, MVT::v8i16, 1 }, 2400 { ISD::SADDSAT, MVT::v16i8, 1 }, 2401 { ISD::SSUBSAT, MVT::v8i16, 1 }, 2402 { ISD::SSUBSAT, MVT::v16i8, 1 }, 2403 { ISD::UADDSAT, MVT::v8i16, 1 }, 2404 { ISD::UADDSAT, MVT::v16i8, 1 }, 2405 { ISD::USUBSAT, MVT::v8i16, 1 }, 2406 { ISD::USUBSAT, MVT::v16i8, 1 }, 2407 { ISD::FMAXNUM, MVT::f64, 4 }, 2408 { ISD::FMAXNUM, MVT::v2f64, 4 }, 2409 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 2410 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 2411 }; 2412 static const CostTblEntry SSE1CostTbl[] = { 2413 { ISD::FMAXNUM, MVT::f32, 4 }, 2414 { ISD::FMAXNUM, MVT::v4f32, 4 }, 2415 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 2416 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 2417 }; 2418 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 2419 { ISD::CTTZ, MVT::i64, 1 }, 2420 }; 2421 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 2422 { ISD::CTTZ, MVT::i32, 1 }, 2423 { ISD::CTTZ, MVT::i16, 1 }, 2424 { ISD::CTTZ, MVT::i8, 1 }, 2425 }; 2426 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 2427 { ISD::CTLZ, MVT::i64, 1 }, 2428 }; 2429 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 2430 { ISD::CTLZ, MVT::i32, 1 }, 2431 { ISD::CTLZ, MVT::i16, 1 }, 2432 { ISD::CTLZ, MVT::i8, 1 }, 2433 }; 2434 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 2435 { ISD::CTPOP, MVT::i64, 1 }, 2436 }; 2437 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 2438 { ISD::CTPOP, MVT::i32, 1 }, 2439 { ISD::CTPOP, MVT::i16, 1 }, 2440 { ISD::CTPOP, MVT::i8, 1 }, 2441 }; 2442 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2443 { ISD::BITREVERSE, MVT::i64, 14 }, 2444 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 2445 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 2446 { ISD::CTPOP, MVT::i64, 10 }, 2447 { ISD::SADDO, MVT::i64, 1 }, 2448 { ISD::UADDO, MVT::i64, 1 }, 2449 }; 2450 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2451 { ISD::BITREVERSE, MVT::i32, 14 }, 2452 { ISD::BITREVERSE, MVT::i16, 14 }, 2453 { ISD::BITREVERSE, MVT::i8, 11 }, 2454 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 2455 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 2456 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 2457 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 2458 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 2459 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 2460 { ISD::CTPOP, MVT::i32, 8 }, 2461 { ISD::CTPOP, MVT::i16, 9 }, 2462 { ISD::CTPOP, MVT::i8, 7 }, 2463 { ISD::SADDO, MVT::i32, 1 }, 2464 { ISD::SADDO, MVT::i16, 1 }, 2465 { ISD::SADDO, MVT::i8, 1 }, 2466 { ISD::UADDO, MVT::i32, 1 }, 2467 { ISD::UADDO, MVT::i16, 1 }, 2468 { ISD::UADDO, MVT::i8, 1 }, 2469 }; 2470 2471 Type *OpTy = RetTy; 2472 unsigned ISD = ISD::DELETED_NODE; 2473 switch (IID) { 2474 default: 2475 break; 2476 case Intrinsic::bitreverse: 2477 ISD = ISD::BITREVERSE; 2478 break; 2479 case Intrinsic::bswap: 2480 ISD = ISD::BSWAP; 2481 break; 2482 case Intrinsic::ctlz: 2483 ISD = ISD::CTLZ; 2484 break; 2485 case Intrinsic::ctpop: 2486 ISD = ISD::CTPOP; 2487 break; 2488 case Intrinsic::cttz: 2489 ISD = ISD::CTTZ; 2490 break; 2491 case Intrinsic::maxnum: 2492 case Intrinsic::minnum: 2493 // FMINNUM has same costs so don't duplicate. 2494 ISD = ISD::FMAXNUM; 2495 break; 2496 case Intrinsic::sadd_sat: 2497 ISD = ISD::SADDSAT; 2498 break; 2499 case Intrinsic::ssub_sat: 2500 ISD = ISD::SSUBSAT; 2501 break; 2502 case Intrinsic::uadd_sat: 2503 ISD = ISD::UADDSAT; 2504 break; 2505 case Intrinsic::usub_sat: 2506 ISD = ISD::USUBSAT; 2507 break; 2508 case Intrinsic::sqrt: 2509 ISD = ISD::FSQRT; 2510 break; 2511 case Intrinsic::sadd_with_overflow: 2512 case Intrinsic::ssub_with_overflow: 2513 // SSUBO has same costs so don't duplicate. 2514 ISD = ISD::SADDO; 2515 OpTy = RetTy->getContainedType(0); 2516 break; 2517 case Intrinsic::uadd_with_overflow: 2518 case Intrinsic::usub_with_overflow: 2519 // USUBO has same costs so don't duplicate. 2520 ISD = ISD::UADDO; 2521 OpTy = RetTy->getContainedType(0); 2522 break; 2523 } 2524 2525 if (ISD != ISD::DELETED_NODE) { 2526 // Legalize the type. 2527 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 2528 MVT MTy = LT.second; 2529 2530 // Attempt to lookup cost. 2531 if (ST->useGLMDivSqrtCosts()) 2532 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 2533 return LT.first * Entry->Cost; 2534 2535 if (ST->isSLM()) 2536 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2537 return LT.first * Entry->Cost; 2538 2539 if (ST->hasCDI()) 2540 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 2541 return LT.first * Entry->Cost; 2542 2543 if (ST->hasBWI()) 2544 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2545 return LT.first * Entry->Cost; 2546 2547 if (ST->hasAVX512()) 2548 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2549 return LT.first * Entry->Cost; 2550 2551 if (ST->hasXOP()) 2552 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2553 return LT.first * Entry->Cost; 2554 2555 if (ST->hasAVX2()) 2556 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2557 return LT.first * Entry->Cost; 2558 2559 if (ST->hasAVX()) 2560 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2561 return LT.first * Entry->Cost; 2562 2563 if (ST->hasSSE42()) 2564 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2565 return LT.first * Entry->Cost; 2566 2567 if (ST->hasSSSE3()) 2568 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 2569 return LT.first * Entry->Cost; 2570 2571 if (ST->hasSSE2()) 2572 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2573 return LT.first * Entry->Cost; 2574 2575 if (ST->hasSSE1()) 2576 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2577 return LT.first * Entry->Cost; 2578 2579 if (ST->hasBMI()) { 2580 if (ST->is64Bit()) 2581 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 2582 return LT.first * Entry->Cost; 2583 2584 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 2585 return LT.first * Entry->Cost; 2586 } 2587 2588 if (ST->hasLZCNT()) { 2589 if (ST->is64Bit()) 2590 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 2591 return LT.first * Entry->Cost; 2592 2593 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 2594 return LT.first * Entry->Cost; 2595 } 2596 2597 if (ST->hasPOPCNT()) { 2598 if (ST->is64Bit()) 2599 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 2600 return LT.first * Entry->Cost; 2601 2602 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 2603 return LT.first * Entry->Cost; 2604 } 2605 2606 // TODO - add BMI (TZCNT) scalar handling 2607 2608 if (ST->is64Bit()) 2609 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2610 return LT.first * Entry->Cost; 2611 2612 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2613 return LT.first * Entry->Cost; 2614 } 2615 2616 return BaseT::getIntrinsicInstrCost(IID, RetTy, Tys, FMF, 2617 ScalarizationCostPassed, I); 2618 } 2619 2620 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 2621 ArrayRef<Value *> Args, FastMathFlags FMF, 2622 unsigned VF, const Instruction *I) { 2623 static const CostTblEntry AVX512CostTbl[] = { 2624 { ISD::ROTL, MVT::v8i64, 1 }, 2625 { ISD::ROTL, MVT::v4i64, 1 }, 2626 { ISD::ROTL, MVT::v2i64, 1 }, 2627 { ISD::ROTL, MVT::v16i32, 1 }, 2628 { ISD::ROTL, MVT::v8i32, 1 }, 2629 { ISD::ROTL, MVT::v4i32, 1 }, 2630 { ISD::ROTR, MVT::v8i64, 1 }, 2631 { ISD::ROTR, MVT::v4i64, 1 }, 2632 { ISD::ROTR, MVT::v2i64, 1 }, 2633 { ISD::ROTR, MVT::v16i32, 1 }, 2634 { ISD::ROTR, MVT::v8i32, 1 }, 2635 { ISD::ROTR, MVT::v4i32, 1 } 2636 }; 2637 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 2638 static const CostTblEntry XOPCostTbl[] = { 2639 { ISD::ROTL, MVT::v4i64, 4 }, 2640 { ISD::ROTL, MVT::v8i32, 4 }, 2641 { ISD::ROTL, MVT::v16i16, 4 }, 2642 { ISD::ROTL, MVT::v32i8, 4 }, 2643 { ISD::ROTL, MVT::v2i64, 1 }, 2644 { ISD::ROTL, MVT::v4i32, 1 }, 2645 { ISD::ROTL, MVT::v8i16, 1 }, 2646 { ISD::ROTL, MVT::v16i8, 1 }, 2647 { ISD::ROTR, MVT::v4i64, 6 }, 2648 { ISD::ROTR, MVT::v8i32, 6 }, 2649 { ISD::ROTR, MVT::v16i16, 6 }, 2650 { ISD::ROTR, MVT::v32i8, 6 }, 2651 { ISD::ROTR, MVT::v2i64, 2 }, 2652 { ISD::ROTR, MVT::v4i32, 2 }, 2653 { ISD::ROTR, MVT::v8i16, 2 }, 2654 { ISD::ROTR, MVT::v16i8, 2 } 2655 }; 2656 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2657 { ISD::ROTL, MVT::i64, 1 }, 2658 { ISD::ROTR, MVT::i64, 1 }, 2659 { ISD::FSHL, MVT::i64, 4 } 2660 }; 2661 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2662 { ISD::ROTL, MVT::i32, 1 }, 2663 { ISD::ROTL, MVT::i16, 1 }, 2664 { ISD::ROTL, MVT::i8, 1 }, 2665 { ISD::ROTR, MVT::i32, 1 }, 2666 { ISD::ROTR, MVT::i16, 1 }, 2667 { ISD::ROTR, MVT::i8, 1 }, 2668 { ISD::FSHL, MVT::i32, 4 }, 2669 { ISD::FSHL, MVT::i16, 4 }, 2670 { ISD::FSHL, MVT::i8, 4 } 2671 }; 2672 2673 unsigned ISD = ISD::DELETED_NODE; 2674 switch (IID) { 2675 default: 2676 break; 2677 case Intrinsic::fshl: 2678 ISD = ISD::FSHL; 2679 if (Args[0] == Args[1]) 2680 ISD = ISD::ROTL; 2681 break; 2682 case Intrinsic::fshr: 2683 // FSHR has same costs so don't duplicate. 2684 ISD = ISD::FSHL; 2685 if (Args[0] == Args[1]) 2686 ISD = ISD::ROTR; 2687 break; 2688 } 2689 2690 if (ISD != ISD::DELETED_NODE) { 2691 // Legalize the type. 2692 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 2693 MVT MTy = LT.second; 2694 2695 // Attempt to lookup cost. 2696 if (ST->hasAVX512()) 2697 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2698 return LT.first * Entry->Cost; 2699 2700 if (ST->hasXOP()) 2701 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2702 return LT.first * Entry->Cost; 2703 2704 if (ST->is64Bit()) 2705 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2706 return LT.first * Entry->Cost; 2707 2708 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2709 return LT.first * Entry->Cost; 2710 } 2711 2712 return BaseT::getIntrinsicInstrCost(IID, RetTy, Args, FMF, VF, I); 2713 } 2714 2715 int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { 2716 static const CostTblEntry SLMCostTbl[] = { 2717 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 2718 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 2719 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 2720 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 2721 }; 2722 2723 assert(Val->isVectorTy() && "This must be a vector type"); 2724 Type *ScalarType = Val->getScalarType(); 2725 int RegisterFileMoveCost = 0; 2726 2727 if (Index != -1U && (Opcode == Instruction::ExtractElement || 2728 Opcode == Instruction::InsertElement)) { 2729 // Legalize the type. 2730 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 2731 2732 // This type is legalized to a scalar type. 2733 if (!LT.second.isVector()) 2734 return 0; 2735 2736 // The type may be split. Normalize the index to the new type. 2737 unsigned NumElts = LT.second.getVectorNumElements(); 2738 unsigned SubNumElts = NumElts; 2739 Index = Index % NumElts; 2740 2741 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 2742 // For inserts, we also need to insert the subvector back. 2743 if (LT.second.getSizeInBits() > 128) { 2744 assert((LT.second.getSizeInBits() % 128) == 0 && "Illegal vector"); 2745 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 2746 SubNumElts = NumElts / NumSubVecs; 2747 if (SubNumElts <= Index) { 2748 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 2749 Index %= SubNumElts; 2750 } 2751 } 2752 2753 if (Index == 0) { 2754 // Floating point scalars are already located in index #0. 2755 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 2756 // true for all. 2757 if (ScalarType->isFloatingPointTy()) 2758 return RegisterFileMoveCost; 2759 2760 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 2761 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 2762 return 1 + RegisterFileMoveCost; 2763 } 2764 2765 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2766 assert(ISD && "Unexpected vector opcode"); 2767 MVT MScalarTy = LT.second.getScalarType(); 2768 if (ST->isSLM()) 2769 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 2770 return Entry->Cost + RegisterFileMoveCost; 2771 2772 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 2773 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 2774 (MScalarTy.isInteger() && ST->hasSSE41())) 2775 return 1 + RegisterFileMoveCost; 2776 2777 // Assume insertps is relatively cheap on all targets. 2778 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 2779 Opcode == Instruction::InsertElement) 2780 return 1 + RegisterFileMoveCost; 2781 2782 // For extractions we just need to shuffle the element to index 0, which 2783 // should be very cheap (assume cost = 1). For insertions we need to shuffle 2784 // the elements to its destination. In both cases we must handle the 2785 // subvector move(s). 2786 // If the vector type is already less than 128-bits then don't reduce it. 2787 // TODO: Under what circumstances should we shuffle using the full width? 2788 int ShuffleCost = 1; 2789 if (Opcode == Instruction::InsertElement) { 2790 auto *SubTy = cast<VectorType>(Val); 2791 EVT VT = TLI->getValueType(DL, Val); 2792 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 2793 SubTy = VectorType::get(ScalarType, SubNumElts); 2794 ShuffleCost = getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, 0, SubTy); 2795 } 2796 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 2797 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 2798 } 2799 2800 // Add to the base cost if we know that the extracted element of a vector is 2801 // destined to be moved to and used in the integer register file. 2802 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 2803 RegisterFileMoveCost += 1; 2804 2805 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 2806 } 2807 2808 unsigned X86TTIImpl::getScalarizationOverhead(Type *Ty, bool Insert, 2809 bool Extract) { 2810 return BaseT::getScalarizationOverhead(Ty, Insert, Extract); 2811 } 2812 2813 int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 2814 MaybeAlign Alignment, unsigned AddressSpace, 2815 const Instruction *I) { 2816 // Handle non-power-of-two vectors such as <3 x float> 2817 if (VectorType *VTy = dyn_cast<VectorType>(Src)) { 2818 unsigned NumElem = VTy->getNumElements(); 2819 2820 // Handle a few common cases: 2821 // <3 x float> 2822 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 2823 // Cost = 64 bit store + extract + 32 bit store. 2824 return 3; 2825 2826 // <3 x double> 2827 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 2828 // Cost = 128 bit store + unpack + 64 bit store. 2829 return 3; 2830 2831 // Assume that all other non-power-of-two numbers are scalarized. 2832 if (!isPowerOf2_32(NumElem)) { 2833 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment, 2834 AddressSpace); 2835 int SplitCost = getScalarizationOverhead(Src, Opcode == Instruction::Load, 2836 Opcode == Instruction::Store); 2837 return NumElem * Cost + SplitCost; 2838 } 2839 } 2840 2841 // Legalize the type. 2842 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 2843 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 2844 "Invalid Opcode"); 2845 2846 // Each load/store unit costs 1. 2847 int Cost = LT.first * 1; 2848 2849 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a 2850 // proxy for a double-pumped AVX memory interface such as on Sandybridge. 2851 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow()) 2852 Cost *= 2; 2853 2854 return Cost; 2855 } 2856 2857 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, 2858 unsigned Alignment, 2859 unsigned AddressSpace) { 2860 bool IsLoad = (Instruction::Load == Opcode); 2861 bool IsStore = (Instruction::Store == Opcode); 2862 2863 VectorType *SrcVTy = dyn_cast<VectorType>(SrcTy); 2864 if (!SrcVTy) 2865 // To calculate scalar take the regular cost, without mask 2866 return getMemoryOpCost(Opcode, SrcTy, MaybeAlign(Alignment), AddressSpace); 2867 2868 unsigned NumElem = SrcVTy->getNumElements(); 2869 VectorType *MaskTy = 2870 VectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 2871 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, MaybeAlign(Alignment))) || 2872 (IsStore && !isLegalMaskedStore(SrcVTy, MaybeAlign(Alignment))) || 2873 !isPowerOf2_32(NumElem)) { 2874 // Scalarization 2875 int MaskSplitCost = getScalarizationOverhead(MaskTy, false, true); 2876 int ScalarCompareCost = getCmpSelInstrCost( 2877 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr); 2878 int BranchCost = getCFInstrCost(Instruction::Br); 2879 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 2880 2881 int ValueSplitCost = getScalarizationOverhead(SrcVTy, IsLoad, IsStore); 2882 int MemopCost = 2883 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2884 MaybeAlign(Alignment), AddressSpace); 2885 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 2886 } 2887 2888 // Legalize the type. 2889 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 2890 auto VT = TLI->getValueType(DL, SrcVTy); 2891 int Cost = 0; 2892 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 2893 LT.second.getVectorNumElements() == NumElem) 2894 // Promotion requires expand/truncate for data and a shuffle for mask. 2895 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, 0, nullptr) + 2896 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, 0, nullptr); 2897 2898 else if (LT.second.getVectorNumElements() > NumElem) { 2899 VectorType *NewMaskTy = VectorType::get(MaskTy->getElementType(), 2900 LT.second.getVectorNumElements()); 2901 // Expanding requires fill mask with zeroes 2902 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, 0, MaskTy); 2903 } 2904 2905 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 2906 if (!ST->hasAVX512()) 2907 return Cost + LT.first * (IsLoad ? 2 : 8); 2908 2909 // AVX-512 masked load/store is cheapper 2910 return Cost + LT.first; 2911 } 2912 2913 int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE, 2914 const SCEV *Ptr) { 2915 // Address computations in vectorized code with non-consecutive addresses will 2916 // likely result in more instructions compared to scalar code where the 2917 // computation can more often be merged into the index mode. The resulting 2918 // extra micro-ops can significantly decrease throughput. 2919 const unsigned NumVectorInstToHideOverhead = 10; 2920 2921 // Cost modeling of Strided Access Computation is hidden by the indexing 2922 // modes of X86 regardless of the stride value. We dont believe that there 2923 // is a difference between constant strided access in gerenal and constant 2924 // strided value which is less than or equal to 64. 2925 // Even in the case of (loop invariant) stride whose value is not known at 2926 // compile time, the address computation will not incur more than one extra 2927 // ADD instruction. 2928 if (Ty->isVectorTy() && SE) { 2929 if (!BaseT::isStridedAccess(Ptr)) 2930 return NumVectorInstToHideOverhead; 2931 if (!BaseT::getConstantStrideStep(SE, Ptr)) 2932 return 1; 2933 } 2934 2935 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 2936 } 2937 2938 int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 2939 bool IsPairwise) { 2940 // Just use the default implementation for pair reductions. 2941 if (IsPairwise) 2942 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise); 2943 2944 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 2945 // and make it as the cost. 2946 2947 static const CostTblEntry SLMCostTblNoPairWise[] = { 2948 { ISD::FADD, MVT::v2f64, 3 }, 2949 { ISD::ADD, MVT::v2i64, 5 }, 2950 }; 2951 2952 static const CostTblEntry SSE2CostTblNoPairWise[] = { 2953 { ISD::FADD, MVT::v2f64, 2 }, 2954 { ISD::FADD, MVT::v4f32, 4 }, 2955 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 2956 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 2957 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 2958 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 2959 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 2960 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 2961 { ISD::ADD, MVT::v2i8, 2 }, 2962 { ISD::ADD, MVT::v4i8, 2 }, 2963 { ISD::ADD, MVT::v8i8, 2 }, 2964 { ISD::ADD, MVT::v16i8, 3 }, 2965 }; 2966 2967 static const CostTblEntry AVX1CostTblNoPairWise[] = { 2968 { ISD::FADD, MVT::v4f64, 3 }, 2969 { ISD::FADD, MVT::v4f32, 3 }, 2970 { ISD::FADD, MVT::v8f32, 4 }, 2971 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 2972 { ISD::ADD, MVT::v4i64, 3 }, 2973 { ISD::ADD, MVT::v8i32, 5 }, 2974 { ISD::ADD, MVT::v16i16, 5 }, 2975 { ISD::ADD, MVT::v32i8, 4 }, 2976 }; 2977 2978 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2979 assert(ISD && "Invalid opcode"); 2980 2981 // Before legalizing the type, give a chance to look up illegal narrow types 2982 // in the table. 2983 // FIXME: Is there a better way to do this? 2984 EVT VT = TLI->getValueType(DL, ValTy); 2985 if (VT.isSimple()) { 2986 MVT MTy = VT.getSimpleVT(); 2987 if (ST->isSLM()) 2988 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 2989 return Entry->Cost; 2990 2991 if (ST->hasAVX()) 2992 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 2993 return Entry->Cost; 2994 2995 if (ST->hasSSE2()) 2996 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 2997 return Entry->Cost; 2998 } 2999 3000 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3001 3002 MVT MTy = LT.second; 3003 3004 auto *ValVTy = cast<VectorType>(ValTy); 3005 3006 unsigned ArithmeticCost = 0; 3007 if (LT.first != 1 && MTy.isVector() && 3008 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3009 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3010 VectorType *SingleOpTy = 3011 VectorType::get(ValVTy->getElementType(), MTy.getVectorNumElements()); 3012 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy); 3013 ArithmeticCost *= LT.first - 1; 3014 } 3015 3016 if (ST->isSLM()) 3017 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3018 return ArithmeticCost + Entry->Cost; 3019 3020 if (ST->hasAVX()) 3021 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3022 return ArithmeticCost + Entry->Cost; 3023 3024 if (ST->hasSSE2()) 3025 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3026 return ArithmeticCost + Entry->Cost; 3027 3028 // FIXME: These assume a naive kshift+binop lowering, which is probably 3029 // conservative in most cases. 3030 static const CostTblEntry AVX512BoolReduction[] = { 3031 { ISD::AND, MVT::v2i1, 3 }, 3032 { ISD::AND, MVT::v4i1, 5 }, 3033 { ISD::AND, MVT::v8i1, 7 }, 3034 { ISD::AND, MVT::v16i1, 9 }, 3035 { ISD::AND, MVT::v32i1, 11 }, 3036 { ISD::AND, MVT::v64i1, 13 }, 3037 { ISD::OR, MVT::v2i1, 3 }, 3038 { ISD::OR, MVT::v4i1, 5 }, 3039 { ISD::OR, MVT::v8i1, 7 }, 3040 { ISD::OR, MVT::v16i1, 9 }, 3041 { ISD::OR, MVT::v32i1, 11 }, 3042 { ISD::OR, MVT::v64i1, 13 }, 3043 }; 3044 3045 static const CostTblEntry AVX2BoolReduction[] = { 3046 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 3047 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 3048 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 3049 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 3050 }; 3051 3052 static const CostTblEntry AVX1BoolReduction[] = { 3053 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 3054 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 3055 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3056 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3057 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 3058 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 3059 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3060 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3061 }; 3062 3063 static const CostTblEntry SSE2BoolReduction[] = { 3064 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 3065 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 3066 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 3067 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 3068 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 3069 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 3070 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 3071 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 3072 }; 3073 3074 // Handle bool allof/anyof patterns. 3075 if (ValVTy->getElementType()->isIntegerTy(1)) { 3076 unsigned ArithmeticCost = 0; 3077 if (LT.first != 1 && MTy.isVector() && 3078 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3079 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3080 Type *SingleOpTy = 3081 VectorType::get(ValVTy->getElementType(), MTy.getVectorNumElements()); 3082 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy); 3083 ArithmeticCost *= LT.first - 1; 3084 } 3085 3086 if (ST->hasAVX512()) 3087 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 3088 return ArithmeticCost + Entry->Cost; 3089 if (ST->hasAVX2()) 3090 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 3091 return ArithmeticCost + Entry->Cost; 3092 if (ST->hasAVX()) 3093 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 3094 return ArithmeticCost + Entry->Cost; 3095 if (ST->hasSSE2()) 3096 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 3097 return ArithmeticCost + Entry->Cost; 3098 3099 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise); 3100 } 3101 3102 unsigned NumVecElts = ValVTy->getNumElements(); 3103 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 3104 3105 // Special case power of 2 reductions where the scalar type isn't changed 3106 // by type legalization. 3107 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 3108 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise); 3109 3110 unsigned ReductionCost = 0; 3111 3112 auto *Ty = ValVTy; 3113 if (LT.first != 1 && MTy.isVector() && 3114 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3115 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3116 Ty = VectorType::get(ValVTy->getElementType(), MTy.getVectorNumElements()); 3117 ReductionCost = getArithmeticInstrCost(Opcode, Ty); 3118 ReductionCost *= LT.first - 1; 3119 NumVecElts = MTy.getVectorNumElements(); 3120 } 3121 3122 // Now handle reduction with the legal type, taking into account size changes 3123 // at each level. 3124 while (NumVecElts > 1) { 3125 // Determine the size of the remaining vector we need to reduce. 3126 unsigned Size = NumVecElts * ScalarSize; 3127 NumVecElts /= 2; 3128 // If we're reducing from 256/512 bits, use an extract_subvector. 3129 if (Size > 128) { 3130 auto *SubTy = VectorType::get(ValVTy->getElementType(), NumVecElts); 3131 ReductionCost += 3132 getShuffleCost(TTI::SK_ExtractSubvector, Ty, NumVecElts, SubTy); 3133 Ty = SubTy; 3134 } else if (Size == 128) { 3135 // Reducing from 128 bits is a permute of v2f64/v2i64. 3136 VectorType *ShufTy; 3137 if (ValVTy->isFloatingPointTy()) 3138 ShufTy = VectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 3139 else 3140 ShufTy = VectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 3141 ReductionCost += 3142 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3143 } else if (Size == 64) { 3144 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3145 VectorType *ShufTy; 3146 if (ValVTy->isFloatingPointTy()) 3147 ShufTy = VectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 3148 else 3149 ShufTy = VectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 3150 ReductionCost += 3151 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3152 } else { 3153 // Reducing from smaller size is a shift by immediate. 3154 auto *ShiftTy = VectorType::get( 3155 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 3156 ReductionCost += getArithmeticInstrCost( 3157 Instruction::LShr, ShiftTy, TargetTransformInfo::OK_AnyValue, 3158 TargetTransformInfo::OK_UniformConstantValue, 3159 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3160 } 3161 3162 // Add the arithmetic op for this level. 3163 ReductionCost += getArithmeticInstrCost(Opcode, Ty); 3164 } 3165 3166 // Add the final extract element to the cost. 3167 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3168 } 3169 3170 int X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, bool IsUnsigned) { 3171 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3172 3173 MVT MTy = LT.second; 3174 3175 int ISD; 3176 if (Ty->isIntOrIntVectorTy()) { 3177 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3178 } else { 3179 assert(Ty->isFPOrFPVectorTy() && 3180 "Expected float point or integer vector type."); 3181 ISD = ISD::FMINNUM; 3182 } 3183 3184 static const CostTblEntry SSE1CostTbl[] = { 3185 {ISD::FMINNUM, MVT::v4f32, 1}, 3186 }; 3187 3188 static const CostTblEntry SSE2CostTbl[] = { 3189 {ISD::FMINNUM, MVT::v2f64, 1}, 3190 {ISD::SMIN, MVT::v8i16, 1}, 3191 {ISD::UMIN, MVT::v16i8, 1}, 3192 }; 3193 3194 static const CostTblEntry SSE41CostTbl[] = { 3195 {ISD::SMIN, MVT::v4i32, 1}, 3196 {ISD::UMIN, MVT::v4i32, 1}, 3197 {ISD::UMIN, MVT::v8i16, 1}, 3198 {ISD::SMIN, MVT::v16i8, 1}, 3199 }; 3200 3201 static const CostTblEntry SSE42CostTbl[] = { 3202 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 3203 }; 3204 3205 static const CostTblEntry AVX1CostTbl[] = { 3206 {ISD::FMINNUM, MVT::v8f32, 1}, 3207 {ISD::FMINNUM, MVT::v4f64, 1}, 3208 {ISD::SMIN, MVT::v8i32, 3}, 3209 {ISD::UMIN, MVT::v8i32, 3}, 3210 {ISD::SMIN, MVT::v16i16, 3}, 3211 {ISD::UMIN, MVT::v16i16, 3}, 3212 {ISD::SMIN, MVT::v32i8, 3}, 3213 {ISD::UMIN, MVT::v32i8, 3}, 3214 }; 3215 3216 static const CostTblEntry AVX2CostTbl[] = { 3217 {ISD::SMIN, MVT::v8i32, 1}, 3218 {ISD::UMIN, MVT::v8i32, 1}, 3219 {ISD::SMIN, MVT::v16i16, 1}, 3220 {ISD::UMIN, MVT::v16i16, 1}, 3221 {ISD::SMIN, MVT::v32i8, 1}, 3222 {ISD::UMIN, MVT::v32i8, 1}, 3223 }; 3224 3225 static const CostTblEntry AVX512CostTbl[] = { 3226 {ISD::FMINNUM, MVT::v16f32, 1}, 3227 {ISD::FMINNUM, MVT::v8f64, 1}, 3228 {ISD::SMIN, MVT::v2i64, 1}, 3229 {ISD::UMIN, MVT::v2i64, 1}, 3230 {ISD::SMIN, MVT::v4i64, 1}, 3231 {ISD::UMIN, MVT::v4i64, 1}, 3232 {ISD::SMIN, MVT::v8i64, 1}, 3233 {ISD::UMIN, MVT::v8i64, 1}, 3234 {ISD::SMIN, MVT::v16i32, 1}, 3235 {ISD::UMIN, MVT::v16i32, 1}, 3236 }; 3237 3238 static const CostTblEntry AVX512BWCostTbl[] = { 3239 {ISD::SMIN, MVT::v32i16, 1}, 3240 {ISD::UMIN, MVT::v32i16, 1}, 3241 {ISD::SMIN, MVT::v64i8, 1}, 3242 {ISD::UMIN, MVT::v64i8, 1}, 3243 }; 3244 3245 // If we have a native MIN/MAX instruction for this type, use it. 3246 if (ST->hasBWI()) 3247 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3248 return LT.first * Entry->Cost; 3249 3250 if (ST->hasAVX512()) 3251 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3252 return LT.first * Entry->Cost; 3253 3254 if (ST->hasAVX2()) 3255 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3256 return LT.first * Entry->Cost; 3257 3258 if (ST->hasAVX()) 3259 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3260 return LT.first * Entry->Cost; 3261 3262 if (ST->hasSSE42()) 3263 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3264 return LT.first * Entry->Cost; 3265 3266 if (ST->hasSSE41()) 3267 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3268 return LT.first * Entry->Cost; 3269 3270 if (ST->hasSSE2()) 3271 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3272 return LT.first * Entry->Cost; 3273 3274 if (ST->hasSSE1()) 3275 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3276 return LT.first * Entry->Cost; 3277 3278 unsigned CmpOpcode; 3279 if (Ty->isFPOrFPVectorTy()) { 3280 CmpOpcode = Instruction::FCmp; 3281 } else { 3282 assert(Ty->isIntOrIntVectorTy() && 3283 "expecting floating point or integer type for min/max reduction"); 3284 CmpOpcode = Instruction::ICmp; 3285 } 3286 3287 // Otherwise fall back to cmp+select. 3288 return getCmpSelInstrCost(CmpOpcode, Ty, CondTy, nullptr) + 3289 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, nullptr); 3290 } 3291 3292 int X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 3293 bool IsPairwise, bool IsUnsigned) { 3294 // Just use the default implementation for pair reductions. 3295 if (IsPairwise) 3296 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned); 3297 3298 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3299 3300 MVT MTy = LT.second; 3301 3302 int ISD; 3303 if (ValTy->isIntOrIntVectorTy()) { 3304 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3305 } else { 3306 assert(ValTy->isFPOrFPVectorTy() && 3307 "Expected float point or integer vector type."); 3308 ISD = ISD::FMINNUM; 3309 } 3310 3311 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3312 // and make it as the cost. 3313 3314 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3315 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 3316 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 3317 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 3318 }; 3319 3320 static const CostTblEntry SSE41CostTblNoPairWise[] = { 3321 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 3322 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 3323 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 3324 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 3325 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 3326 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 3327 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 3328 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 3329 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 3330 {ISD::SMIN, MVT::v16i8, 6}, 3331 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 3332 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 3333 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 3334 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 3335 }; 3336 3337 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3338 {ISD::SMIN, MVT::v16i16, 6}, 3339 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 3340 {ISD::SMIN, MVT::v32i8, 8}, 3341 {ISD::UMIN, MVT::v32i8, 8}, 3342 }; 3343 3344 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 3345 {ISD::SMIN, MVT::v32i16, 8}, 3346 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 3347 {ISD::SMIN, MVT::v64i8, 10}, 3348 {ISD::UMIN, MVT::v64i8, 10}, 3349 }; 3350 3351 // Before legalizing the type, give a chance to look up illegal narrow types 3352 // in the table. 3353 // FIXME: Is there a better way to do this? 3354 EVT VT = TLI->getValueType(DL, ValTy); 3355 if (VT.isSimple()) { 3356 MVT MTy = VT.getSimpleVT(); 3357 if (ST->hasBWI()) 3358 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3359 return Entry->Cost; 3360 3361 if (ST->hasAVX()) 3362 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3363 return Entry->Cost; 3364 3365 if (ST->hasSSE41()) 3366 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3367 return Entry->Cost; 3368 3369 if (ST->hasSSE2()) 3370 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3371 return Entry->Cost; 3372 } 3373 3374 auto *ValVTy = cast<VectorType>(ValTy); 3375 unsigned NumVecElts = ValVTy->getNumElements(); 3376 3377 auto *Ty = ValVTy; 3378 unsigned MinMaxCost = 0; 3379 if (LT.first != 1 && MTy.isVector() && 3380 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3381 // Type needs to be split. We need LT.first - 1 operations ops. 3382 Ty = VectorType::get(ValVTy->getElementType(), MTy.getVectorNumElements()); 3383 auto *SubCondTy = VectorType::get( 3384 cast<VectorType>(CondTy)->getElementType(), MTy.getVectorNumElements()); 3385 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3386 MinMaxCost *= LT.first - 1; 3387 NumVecElts = MTy.getVectorNumElements(); 3388 } 3389 3390 if (ST->hasBWI()) 3391 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3392 return MinMaxCost + Entry->Cost; 3393 3394 if (ST->hasAVX()) 3395 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3396 return MinMaxCost + Entry->Cost; 3397 3398 if (ST->hasSSE41()) 3399 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3400 return MinMaxCost + Entry->Cost; 3401 3402 if (ST->hasSSE2()) 3403 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3404 return MinMaxCost + Entry->Cost; 3405 3406 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 3407 3408 // Special case power of 2 reductions where the scalar type isn't changed 3409 // by type legalization. 3410 if (!isPowerOf2_32(ValVTy->getNumElements()) || 3411 ScalarSize != MTy.getScalarSizeInBits()) 3412 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned); 3413 3414 // Now handle reduction with the legal type, taking into account size changes 3415 // at each level. 3416 while (NumVecElts > 1) { 3417 // Determine the size of the remaining vector we need to reduce. 3418 unsigned Size = NumVecElts * ScalarSize; 3419 NumVecElts /= 2; 3420 // If we're reducing from 256/512 bits, use an extract_subvector. 3421 if (Size > 128) { 3422 auto *SubTy = VectorType::get(ValVTy->getElementType(), NumVecElts); 3423 MinMaxCost += 3424 getShuffleCost(TTI::SK_ExtractSubvector, Ty, NumVecElts, SubTy); 3425 Ty = SubTy; 3426 } else if (Size == 128) { 3427 // Reducing from 128 bits is a permute of v2f64/v2i64. 3428 VectorType *ShufTy; 3429 if (ValTy->isFloatingPointTy()) 3430 ShufTy = VectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 3431 else 3432 ShufTy = VectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 3433 MinMaxCost += 3434 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3435 } else if (Size == 64) { 3436 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3437 VectorType *ShufTy; 3438 if (ValTy->isFloatingPointTy()) 3439 ShufTy = VectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 3440 else 3441 ShufTy = VectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 3442 MinMaxCost += 3443 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3444 } else { 3445 // Reducing from smaller size is a shift by immediate. 3446 VectorType *ShiftTy = VectorType::get( 3447 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 3448 MinMaxCost += getArithmeticInstrCost( 3449 Instruction::LShr, ShiftTy, TargetTransformInfo::OK_AnyValue, 3450 TargetTransformInfo::OK_UniformConstantValue, 3451 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3452 } 3453 3454 // Add the arithmetic op for this level. 3455 auto *SubCondTy = VectorType::get(CondTy->getElementType(), 3456 Ty->getNumElements()); 3457 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3458 } 3459 3460 // Add the final extract element to the cost. 3461 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3462 } 3463 3464 /// Calculate the cost of materializing a 64-bit value. This helper 3465 /// method might only calculate a fraction of a larger immediate. Therefore it 3466 /// is valid to return a cost of ZERO. 3467 int X86TTIImpl::getIntImmCost(int64_t Val) { 3468 if (Val == 0) 3469 return TTI::TCC_Free; 3470 3471 if (isInt<32>(Val)) 3472 return TTI::TCC_Basic; 3473 3474 return 2 * TTI::TCC_Basic; 3475 } 3476 3477 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { 3478 assert(Ty->isIntegerTy()); 3479 3480 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3481 if (BitSize == 0) 3482 return ~0U; 3483 3484 // Never hoist constants larger than 128bit, because this might lead to 3485 // incorrect code generation or assertions in codegen. 3486 // Fixme: Create a cost model for types larger than i128 once the codegen 3487 // issues have been fixed. 3488 if (BitSize > 128) 3489 return TTI::TCC_Free; 3490 3491 if (Imm == 0) 3492 return TTI::TCC_Free; 3493 3494 // Sign-extend all constants to a multiple of 64-bit. 3495 APInt ImmVal = Imm; 3496 if (BitSize % 64 != 0) 3497 ImmVal = Imm.sext(alignTo(BitSize, 64)); 3498 3499 // Split the constant into 64-bit chunks and calculate the cost for each 3500 // chunk. 3501 int Cost = 0; 3502 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 3503 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 3504 int64_t Val = Tmp.getSExtValue(); 3505 Cost += getIntImmCost(Val); 3506 } 3507 // We need at least one instruction to materialize the constant. 3508 return std::max(1, Cost); 3509 } 3510 3511 int X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, 3512 Type *Ty) { 3513 assert(Ty->isIntegerTy()); 3514 3515 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3516 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3517 // here, so that constant hoisting will ignore this constant. 3518 if (BitSize == 0) 3519 return TTI::TCC_Free; 3520 3521 unsigned ImmIdx = ~0U; 3522 switch (Opcode) { 3523 default: 3524 return TTI::TCC_Free; 3525 case Instruction::GetElementPtr: 3526 // Always hoist the base address of a GetElementPtr. This prevents the 3527 // creation of new constants for every base constant that gets constant 3528 // folded with the offset. 3529 if (Idx == 0) 3530 return 2 * TTI::TCC_Basic; 3531 return TTI::TCC_Free; 3532 case Instruction::Store: 3533 ImmIdx = 0; 3534 break; 3535 case Instruction::ICmp: 3536 // This is an imperfect hack to prevent constant hoisting of 3537 // compares that might be trying to check if a 64-bit value fits in 3538 // 32-bits. The backend can optimize these cases using a right shift by 32. 3539 // Ideally we would check the compare predicate here. There also other 3540 // similar immediates the backend can use shifts for. 3541 if (Idx == 1 && Imm.getBitWidth() == 64) { 3542 uint64_t ImmVal = Imm.getZExtValue(); 3543 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 3544 return TTI::TCC_Free; 3545 } 3546 ImmIdx = 1; 3547 break; 3548 case Instruction::And: 3549 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 3550 // by using a 32-bit operation with implicit zero extension. Detect such 3551 // immediates here as the normal path expects bit 31 to be sign extended. 3552 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 3553 return TTI::TCC_Free; 3554 ImmIdx = 1; 3555 break; 3556 case Instruction::Add: 3557 case Instruction::Sub: 3558 // For add/sub, we can use the opposite instruction for INT32_MIN. 3559 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 3560 return TTI::TCC_Free; 3561 ImmIdx = 1; 3562 break; 3563 case Instruction::UDiv: 3564 case Instruction::SDiv: 3565 case Instruction::URem: 3566 case Instruction::SRem: 3567 // Division by constant is typically expanded later into a different 3568 // instruction sequence. This completely changes the constants. 3569 // Report them as "free" to stop ConstantHoist from marking them as opaque. 3570 return TTI::TCC_Free; 3571 case Instruction::Mul: 3572 case Instruction::Or: 3573 case Instruction::Xor: 3574 ImmIdx = 1; 3575 break; 3576 // Always return TCC_Free for the shift value of a shift instruction. 3577 case Instruction::Shl: 3578 case Instruction::LShr: 3579 case Instruction::AShr: 3580 if (Idx == 1) 3581 return TTI::TCC_Free; 3582 break; 3583 case Instruction::Trunc: 3584 case Instruction::ZExt: 3585 case Instruction::SExt: 3586 case Instruction::IntToPtr: 3587 case Instruction::PtrToInt: 3588 case Instruction::BitCast: 3589 case Instruction::PHI: 3590 case Instruction::Call: 3591 case Instruction::Select: 3592 case Instruction::Ret: 3593 case Instruction::Load: 3594 break; 3595 } 3596 3597 if (Idx == ImmIdx) { 3598 int NumConstants = divideCeil(BitSize, 64); 3599 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty); 3600 return (Cost <= NumConstants * TTI::TCC_Basic) 3601 ? static_cast<int>(TTI::TCC_Free) 3602 : Cost; 3603 } 3604 3605 return X86TTIImpl::getIntImmCost(Imm, Ty); 3606 } 3607 3608 int X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 3609 const APInt &Imm, Type *Ty) { 3610 assert(Ty->isIntegerTy()); 3611 3612 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3613 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3614 // here, so that constant hoisting will ignore this constant. 3615 if (BitSize == 0) 3616 return TTI::TCC_Free; 3617 3618 switch (IID) { 3619 default: 3620 return TTI::TCC_Free; 3621 case Intrinsic::sadd_with_overflow: 3622 case Intrinsic::uadd_with_overflow: 3623 case Intrinsic::ssub_with_overflow: 3624 case Intrinsic::usub_with_overflow: 3625 case Intrinsic::smul_with_overflow: 3626 case Intrinsic::umul_with_overflow: 3627 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 3628 return TTI::TCC_Free; 3629 break; 3630 case Intrinsic::experimental_stackmap: 3631 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 3632 return TTI::TCC_Free; 3633 break; 3634 case Intrinsic::experimental_patchpoint_void: 3635 case Intrinsic::experimental_patchpoint_i64: 3636 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 3637 return TTI::TCC_Free; 3638 break; 3639 } 3640 return X86TTIImpl::getIntImmCost(Imm, Ty); 3641 } 3642 3643 unsigned X86TTIImpl::getUserCost(const User *U, 3644 ArrayRef<const Value *> Operands) { 3645 if (isa<StoreInst>(U)) { 3646 Value *Ptr = U->getOperand(1); 3647 // Store instruction with index and scale costs 2 Uops. 3648 // Check the preceding GEP to identify non-const indices. 3649 if (auto GEP = dyn_cast<GetElementPtrInst>(Ptr)) { 3650 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3651 return TTI::TCC_Basic * 2; 3652 } 3653 return TTI::TCC_Basic; 3654 } 3655 return BaseT::getUserCost(U, Operands); 3656 } 3657 3658 // Return an average cost of Gather / Scatter instruction, maybe improved later 3659 int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, Value *Ptr, 3660 unsigned Alignment, unsigned AddressSpace) { 3661 3662 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 3663 unsigned VF = cast<VectorType>(SrcVTy)->getNumElements(); 3664 3665 // Try to reduce index size from 64 bit (default for GEP) 3666 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 3667 // operation will use 16 x 64 indices which do not fit in a zmm and needs 3668 // to split. Also check that the base pointer is the same for all lanes, 3669 // and that there's at most one variable index. 3670 auto getIndexSizeInBits = [](Value *Ptr, const DataLayout& DL) { 3671 unsigned IndexSize = DL.getPointerSizeInBits(); 3672 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 3673 if (IndexSize < 64 || !GEP) 3674 return IndexSize; 3675 3676 unsigned NumOfVarIndices = 0; 3677 Value *Ptrs = GEP->getPointerOperand(); 3678 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 3679 return IndexSize; 3680 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 3681 if (isa<Constant>(GEP->getOperand(i))) 3682 continue; 3683 Type *IndxTy = GEP->getOperand(i)->getType(); 3684 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 3685 IndxTy = IndexVTy->getElementType(); 3686 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 3687 !isa<SExtInst>(GEP->getOperand(i))) || 3688 ++NumOfVarIndices > 1) 3689 return IndexSize; // 64 3690 } 3691 return (unsigned)32; 3692 }; 3693 3694 3695 // Trying to reduce IndexSize to 32 bits for vector 16. 3696 // By default the IndexSize is equal to pointer size. 3697 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 3698 ? getIndexSizeInBits(Ptr, DL) 3699 : DL.getPointerSizeInBits(); 3700 3701 Type *IndexVTy = VectorType::get(IntegerType::get(SrcVTy->getContext(), 3702 IndexSize), VF); 3703 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy); 3704 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3705 int SplitFactor = std::max(IdxsLT.first, SrcLT.first); 3706 if (SplitFactor > 1) { 3707 // Handle splitting of vector of pointers 3708 Type *SplitSrcTy = VectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 3709 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 3710 AddressSpace); 3711 } 3712 3713 // The gather / scatter cost is given by Intel architects. It is a rough 3714 // number since we are looking at one instruction in a time. 3715 const int GSOverhead = (Opcode == Instruction::Load) 3716 ? ST->getGatherOverhead() 3717 : ST->getScatterOverhead(); 3718 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3719 MaybeAlign(Alignment), AddressSpace); 3720 } 3721 3722 /// Return the cost of full scalarization of gather / scatter operation. 3723 /// 3724 /// Opcode - Load or Store instruction. 3725 /// SrcVTy - The type of the data vector that should be gathered or scattered. 3726 /// VariableMask - The mask is non-constant at compile time. 3727 /// Alignment - Alignment for one element. 3728 /// AddressSpace - pointer[s] address space. 3729 /// 3730 int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 3731 bool VariableMask, unsigned Alignment, 3732 unsigned AddressSpace) { 3733 unsigned VF = cast<VectorType>(SrcVTy)->getNumElements(); 3734 3735 int MaskUnpackCost = 0; 3736 if (VariableMask) { 3737 VectorType *MaskTy = 3738 VectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 3739 MaskUnpackCost = getScalarizationOverhead(MaskTy, false, true); 3740 int ScalarCompareCost = 3741 getCmpSelInstrCost(Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), 3742 nullptr); 3743 int BranchCost = getCFInstrCost(Instruction::Br); 3744 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 3745 } 3746 3747 // The cost of the scalar loads/stores. 3748 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3749 MaybeAlign(Alignment), AddressSpace); 3750 3751 int InsertExtractCost = 0; 3752 if (Opcode == Instruction::Load) 3753 for (unsigned i = 0; i < VF; ++i) 3754 // Add the cost of inserting each scalar load into the vector 3755 InsertExtractCost += 3756 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 3757 else 3758 for (unsigned i = 0; i < VF; ++i) 3759 // Add the cost of extracting each element out of the data vector 3760 InsertExtractCost += 3761 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 3762 3763 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 3764 } 3765 3766 /// Calculate the cost of Gather / Scatter operation 3767 int X86TTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *SrcVTy, 3768 Value *Ptr, bool VariableMask, 3769 unsigned Alignment, 3770 const Instruction *I = nullptr) { 3771 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 3772 unsigned VF = cast<VectorType>(SrcVTy)->getNumElements(); 3773 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 3774 if (!PtrTy && Ptr->getType()->isVectorTy()) 3775 PtrTy = dyn_cast<PointerType>( 3776 cast<VectorType>(Ptr->getType())->getElementType()); 3777 assert(PtrTy && "Unexpected type for Ptr argument"); 3778 unsigned AddressSpace = PtrTy->getAddressSpace(); 3779 3780 bool Scalarize = false; 3781 if ((Opcode == Instruction::Load && 3782 !isLegalMaskedGather(SrcVTy, MaybeAlign(Alignment))) || 3783 (Opcode == Instruction::Store && 3784 !isLegalMaskedScatter(SrcVTy, MaybeAlign(Alignment)))) 3785 Scalarize = true; 3786 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 3787 // Vector-4 of gather/scatter instruction does not exist on KNL. 3788 // We can extend it to 8 elements, but zeroing upper bits of 3789 // the mask vector will add more instructions. Right now we give the scalar 3790 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 3791 // is better in the VariableMask case. 3792 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 3793 Scalarize = true; 3794 3795 if (Scalarize) 3796 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 3797 AddressSpace); 3798 3799 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 3800 } 3801 3802 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 3803 TargetTransformInfo::LSRCost &C2) { 3804 // X86 specific here are "instruction number 1st priority". 3805 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 3806 C1.NumIVMuls, C1.NumBaseAdds, 3807 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 3808 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 3809 C2.NumIVMuls, C2.NumBaseAdds, 3810 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 3811 } 3812 3813 bool X86TTIImpl::canMacroFuseCmp() { 3814 return ST->hasMacroFusion() || ST->hasBranchFusion(); 3815 } 3816 3817 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, MaybeAlign Alignment) { 3818 if (!ST->hasAVX()) 3819 return false; 3820 3821 // The backend can't handle a single element vector. 3822 if (isa<VectorType>(DataTy) && 3823 cast<VectorType>(DataTy)->getNumElements() == 1) 3824 return false; 3825 Type *ScalarTy = DataTy->getScalarType(); 3826 3827 if (ScalarTy->isPointerTy()) 3828 return true; 3829 3830 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 3831 return true; 3832 3833 if (!ScalarTy->isIntegerTy()) 3834 return false; 3835 3836 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 3837 return IntWidth == 32 || IntWidth == 64 || 3838 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 3839 } 3840 3841 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, MaybeAlign Alignment) { 3842 return isLegalMaskedLoad(DataType, Alignment); 3843 } 3844 3845 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 3846 unsigned DataSize = DL.getTypeStoreSize(DataType); 3847 // The only supported nontemporal loads are for aligned vectors of 16 or 32 3848 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 3849 // (the equivalent stores only require AVX). 3850 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 3851 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 3852 3853 return false; 3854 } 3855 3856 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 3857 unsigned DataSize = DL.getTypeStoreSize(DataType); 3858 3859 // SSE4A supports nontemporal stores of float and double at arbitrary 3860 // alignment. 3861 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 3862 return true; 3863 3864 // Besides the SSE4A subtarget exception above, only aligned stores are 3865 // available nontemporaly on any other subtarget. And only stores with a size 3866 // of 4..32 bytes (powers of 2, only) are permitted. 3867 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 3868 !isPowerOf2_32(DataSize)) 3869 return false; 3870 3871 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 3872 // loads require AVX2). 3873 if (DataSize == 32) 3874 return ST->hasAVX(); 3875 else if (DataSize == 16) 3876 return ST->hasSSE1(); 3877 return true; 3878 } 3879 3880 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 3881 if (!isa<VectorType>(DataTy)) 3882 return false; 3883 3884 if (!ST->hasAVX512()) 3885 return false; 3886 3887 // The backend can't handle a single element vector. 3888 if (cast<VectorType>(DataTy)->getNumElements() == 1) 3889 return false; 3890 3891 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 3892 3893 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 3894 return true; 3895 3896 if (!ScalarTy->isIntegerTy()) 3897 return false; 3898 3899 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 3900 return IntWidth == 32 || IntWidth == 64 || 3901 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 3902 } 3903 3904 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 3905 return isLegalMaskedExpandLoad(DataTy); 3906 } 3907 3908 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, MaybeAlign Alignment) { 3909 // Some CPUs have better gather performance than others. 3910 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 3911 // enable gather with a -march. 3912 if (!(ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()))) 3913 return false; 3914 3915 // This function is called now in two cases: from the Loop Vectorizer 3916 // and from the Scalarizer. 3917 // When the Loop Vectorizer asks about legality of the feature, 3918 // the vectorization factor is not calculated yet. The Loop Vectorizer 3919 // sends a scalar type and the decision is based on the width of the 3920 // scalar element. 3921 // Later on, the cost model will estimate usage this intrinsic based on 3922 // the vector type. 3923 // The Scalarizer asks again about legality. It sends a vector type. 3924 // In this case we can reject non-power-of-2 vectors. 3925 // We also reject single element vectors as the type legalizer can't 3926 // scalarize it. 3927 if (auto *DataVTy = dyn_cast<VectorType>(DataTy)) { 3928 unsigned NumElts = DataVTy->getNumElements(); 3929 if (NumElts == 1 || !isPowerOf2_32(NumElts)) 3930 return false; 3931 } 3932 Type *ScalarTy = DataTy->getScalarType(); 3933 if (ScalarTy->isPointerTy()) 3934 return true; 3935 3936 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 3937 return true; 3938 3939 if (!ScalarTy->isIntegerTy()) 3940 return false; 3941 3942 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 3943 return IntWidth == 32 || IntWidth == 64; 3944 } 3945 3946 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, MaybeAlign Alignment) { 3947 // AVX2 doesn't support scatter 3948 if (!ST->hasAVX512()) 3949 return false; 3950 return isLegalMaskedGather(DataType, Alignment); 3951 } 3952 3953 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 3954 EVT VT = TLI->getValueType(DL, DataType); 3955 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 3956 } 3957 3958 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 3959 return false; 3960 } 3961 3962 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 3963 const Function *Callee) const { 3964 const TargetMachine &TM = getTLI()->getTargetMachine(); 3965 3966 // Work this as a subsetting of subtarget features. 3967 const FeatureBitset &CallerBits = 3968 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 3969 const FeatureBitset &CalleeBits = 3970 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 3971 3972 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 3973 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 3974 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 3975 } 3976 3977 bool X86TTIImpl::areFunctionArgsABICompatible( 3978 const Function *Caller, const Function *Callee, 3979 SmallPtrSetImpl<Argument *> &Args) const { 3980 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args)) 3981 return false; 3982 3983 // If we get here, we know the target features match. If one function 3984 // considers 512-bit vectors legal and the other does not, consider them 3985 // incompatible. 3986 const TargetMachine &TM = getTLI()->getTargetMachine(); 3987 3988 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 3989 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs()) 3990 return true; 3991 3992 // Consider the arguments compatible if they aren't vectors or aggregates. 3993 // FIXME: Look at the size of vectors. 3994 // FIXME: Look at the element types of aggregates to see if there are vectors. 3995 // FIXME: The API of this function seems intended to allow arguments 3996 // to be removed from the set, but the caller doesn't check if the set 3997 // becomes empty so that may not work in practice. 3998 return llvm::none_of(Args, [](Argument *A) { 3999 auto *EltTy = cast<PointerType>(A->getType())->getElementType(); 4000 return EltTy->isVectorTy() || EltTy->isAggregateType(); 4001 }); 4002 } 4003 4004 X86TTIImpl::TTI::MemCmpExpansionOptions 4005 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 4006 TTI::MemCmpExpansionOptions Options; 4007 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 4008 Options.NumLoadsPerBlock = 2; 4009 // All GPR and vector loads can be unaligned. 4010 Options.AllowOverlappingLoads = true; 4011 if (IsZeroCmp) { 4012 // Only enable vector loads for equality comparison. Right now the vector 4013 // version is not as fast for three way compare (see #33329). 4014 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 4015 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 4016 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 4017 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 4018 } 4019 if (ST->is64Bit()) { 4020 Options.LoadSizes.push_back(8); 4021 } 4022 Options.LoadSizes.push_back(4); 4023 Options.LoadSizes.push_back(2); 4024 Options.LoadSizes.push_back(1); 4025 return Options; 4026 } 4027 4028 bool X86TTIImpl::enableInterleavedAccessVectorization() { 4029 // TODO: We expect this to be beneficial regardless of arch, 4030 // but there are currently some unexplained performance artifacts on Atom. 4031 // As a temporary solution, disable on Atom. 4032 return !(ST->isAtom()); 4033 } 4034 4035 // Get estimation for interleaved load/store operations for AVX2. 4036 // \p Factor is the interleaved-access factor (stride) - number of 4037 // (interleaved) elements in the group. 4038 // \p Indices contains the indices for a strided load: when the 4039 // interleaved load has gaps they indicate which elements are used. 4040 // If Indices is empty (or if the number of indices is equal to the size 4041 // of the interleaved-access as given in \p Factor) the access has no gaps. 4042 // 4043 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 4044 // computing the cost using a generic formula as a function of generic 4045 // shuffles. We therefore use a lookup table instead, filled according to 4046 // the instruction sequences that codegen currently generates. 4047 int X86TTIImpl::getInterleavedMemoryOpCostAVX2(unsigned Opcode, Type *VecTy, 4048 unsigned Factor, 4049 ArrayRef<unsigned> Indices, 4050 unsigned Alignment, 4051 unsigned AddressSpace, 4052 bool UseMaskForCond, 4053 bool UseMaskForGaps) { 4054 4055 if (UseMaskForCond || UseMaskForGaps) 4056 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4057 Alignment, AddressSpace, 4058 UseMaskForCond, UseMaskForGaps); 4059 4060 // We currently Support only fully-interleaved groups, with no gaps. 4061 // TODO: Support also strided loads (interleaved-groups with gaps). 4062 if (Indices.size() && Indices.size() != Factor) 4063 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4064 Alignment, AddressSpace); 4065 4066 // VecTy for interleave memop is <VF*Factor x Elt>. 4067 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4068 // VecTy = <12 x i32>. 4069 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4070 4071 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 4072 // the VF=2, while v2i128 is an unsupported MVT vector type 4073 // (see MachineValueType.h::getVectorVT()). 4074 if (!LegalVT.isVector()) 4075 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4076 Alignment, AddressSpace); 4077 4078 unsigned VF = cast<VectorType>(VecTy)->getNumElements() / Factor; 4079 Type *ScalarTy = cast<VectorType>(VecTy)->getElementType(); 4080 4081 // Calculate the number of memory operations (NumOfMemOps), required 4082 // for load/store the VecTy. 4083 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4084 unsigned LegalVTSize = LegalVT.getStoreSize(); 4085 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4086 4087 // Get the cost of one memory operation. 4088 Type *SingleMemOpTy = 4089 VectorType::get(cast<VectorType>(VecTy)->getElementType(), 4090 LegalVT.getVectorNumElements()); 4091 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 4092 MaybeAlign(Alignment), AddressSpace); 4093 4094 VectorType *VT = VectorType::get(ScalarTy, VF); 4095 EVT ETy = TLI->getValueType(DL, VT); 4096 if (!ETy.isSimple()) 4097 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4098 Alignment, AddressSpace); 4099 4100 // TODO: Complete for other data-types and strides. 4101 // Each combination of Stride, ElementTy and VF results in a different 4102 // sequence; The cost tables are therefore accessed with: 4103 // Factor (stride) and VectorType=VFxElemType. 4104 // The Cost accounts only for the shuffle sequence; 4105 // The cost of the loads/stores is accounted for separately. 4106 // 4107 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 4108 { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64 4109 { 2, MVT::v4f64, 6 }, //(load 8f64 and) deinterleave into 2 x 4f64 4110 4111 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8 4112 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8 4113 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8 4114 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8 4115 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8 4116 { 3, MVT::v8f32, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32 4117 4118 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8 4119 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8 4120 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8 4121 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8 4122 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8 4123 4124 { 8, MVT::v8f32, 40 } //(load 64f32 and)deinterleave into 8 x 8f32 4125 }; 4126 4127 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 4128 { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store) 4129 { 2, MVT::v4f64, 6 }, //interleave into 2 x 4f64 into 8f64 (and store) 4130 4131 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store) 4132 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store) 4133 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store) 4134 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store) 4135 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store) 4136 4137 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store) 4138 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store) 4139 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store) 4140 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store) 4141 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store) 4142 }; 4143 4144 if (Opcode == Instruction::Load) { 4145 if (const auto *Entry = 4146 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 4147 return NumOfMemOps * MemOpCost + Entry->Cost; 4148 } else { 4149 assert(Opcode == Instruction::Store && 4150 "Expected Store Instruction at this point"); 4151 if (const auto *Entry = 4152 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 4153 return NumOfMemOps * MemOpCost + Entry->Cost; 4154 } 4155 4156 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4157 Alignment, AddressSpace); 4158 } 4159 4160 // Get estimation for interleaved load/store operations and strided load. 4161 // \p Indices contains indices for strided load. 4162 // \p Factor - the factor of interleaving. 4163 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 4164 int X86TTIImpl::getInterleavedMemoryOpCostAVX512(unsigned Opcode, Type *VecTy, 4165 unsigned Factor, 4166 ArrayRef<unsigned> Indices, 4167 unsigned Alignment, 4168 unsigned AddressSpace, 4169 bool UseMaskForCond, 4170 bool UseMaskForGaps) { 4171 4172 if (UseMaskForCond || UseMaskForGaps) 4173 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4174 Alignment, AddressSpace, 4175 UseMaskForCond, UseMaskForGaps); 4176 4177 // VecTy for interleave memop is <VF*Factor x Elt>. 4178 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4179 // VecTy = <12 x i32>. 4180 4181 // Calculate the number of memory operations (NumOfMemOps), required 4182 // for load/store the VecTy. 4183 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4184 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4185 unsigned LegalVTSize = LegalVT.getStoreSize(); 4186 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4187 4188 // Get the cost of one memory operation. 4189 auto *SingleMemOpTy = 4190 VectorType::get(cast<VectorType>(VecTy)->getElementType(), 4191 LegalVT.getVectorNumElements()); 4192 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 4193 MaybeAlign(Alignment), AddressSpace); 4194 4195 unsigned VF = cast<VectorType>(VecTy)->getNumElements() / Factor; 4196 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 4197 4198 if (Opcode == Instruction::Load) { 4199 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 4200 // contain the cost of the optimized shuffle sequence that the 4201 // X86InterleavedAccess pass will generate. 4202 // The cost of loads and stores are computed separately from the table. 4203 4204 // X86InterleavedAccess support only the following interleaved-access group. 4205 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 4206 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 4207 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 4208 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 4209 }; 4210 4211 if (const auto *Entry = 4212 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 4213 return NumOfMemOps * MemOpCost + Entry->Cost; 4214 //If an entry does not exist, fallback to the default implementation. 4215 4216 // Kind of shuffle depends on number of loaded values. 4217 // If we load the entire data in one register, we can use a 1-src shuffle. 4218 // Otherwise, we'll merge 2 sources in each operation. 4219 TTI::ShuffleKind ShuffleKind = 4220 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 4221 4222 unsigned ShuffleCost = 4223 getShuffleCost(ShuffleKind, SingleMemOpTy, 0, nullptr); 4224 4225 unsigned NumOfLoadsInInterleaveGrp = 4226 Indices.size() ? Indices.size() : Factor; 4227 Type *ResultTy = 4228 VectorType::get(cast<VectorType>(VecTy)->getElementType(), 4229 cast<VectorType>(VecTy)->getNumElements() / Factor); 4230 unsigned NumOfResults = 4231 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 4232 NumOfLoadsInInterleaveGrp; 4233 4234 // About a half of the loads may be folded in shuffles when we have only 4235 // one result. If we have more than one result, we do not fold loads at all. 4236 unsigned NumOfUnfoldedLoads = 4237 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 4238 4239 // Get a number of shuffle operations per result. 4240 unsigned NumOfShufflesPerResult = 4241 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 4242 4243 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4244 // When we have more than one destination, we need additional instructions 4245 // to keep sources. 4246 unsigned NumOfMoves = 0; 4247 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 4248 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 4249 4250 int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 4251 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 4252 4253 return Cost; 4254 } 4255 4256 // Store. 4257 assert(Opcode == Instruction::Store && 4258 "Expected Store Instruction at this point"); 4259 // X86InterleavedAccess support only the following interleaved-access group. 4260 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 4261 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 4262 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 4263 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 4264 4265 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 4266 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 4267 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 4268 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 4269 }; 4270 4271 if (const auto *Entry = 4272 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 4273 return NumOfMemOps * MemOpCost + Entry->Cost; 4274 //If an entry does not exist, fallback to the default implementation. 4275 4276 // There is no strided stores meanwhile. And store can't be folded in 4277 // shuffle. 4278 unsigned NumOfSources = Factor; // The number of values to be merged. 4279 unsigned ShuffleCost = 4280 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, 0, nullptr); 4281 unsigned NumOfShufflesPerStore = NumOfSources - 1; 4282 4283 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4284 // We need additional instructions to keep sources. 4285 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 4286 int Cost = NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 4287 NumOfMoves; 4288 return Cost; 4289 } 4290 4291 int X86TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, 4292 unsigned Factor, 4293 ArrayRef<unsigned> Indices, 4294 unsigned Alignment, 4295 unsigned AddressSpace, 4296 bool UseMaskForCond, 4297 bool UseMaskForGaps) { 4298 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 4299 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 4300 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 4301 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 4302 return true; 4303 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 4304 return HasBW; 4305 return false; 4306 }; 4307 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 4308 return getInterleavedMemoryOpCostAVX512(Opcode, VecTy, Factor, Indices, 4309 Alignment, AddressSpace, 4310 UseMaskForCond, UseMaskForGaps); 4311 if (ST->hasAVX2()) 4312 return getInterleavedMemoryOpCostAVX2(Opcode, VecTy, Factor, Indices, 4313 Alignment, AddressSpace, 4314 UseMaskForCond, UseMaskForGaps); 4315 4316 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4317 Alignment, AddressSpace, 4318 UseMaskForCond, UseMaskForGaps); 4319 } 4320