1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// \file 10 /// This file implements a TargetTransformInfo analysis pass specific to the 11 /// X86 target machine. It uses the target's detailed information to provide 12 /// more precise answers to certain TTI queries, while letting the target 13 /// independent and default TTI implementations handle the rest. 14 /// 15 //===----------------------------------------------------------------------===// 16 /// About Cost Model numbers used below it's necessary to say the following: 17 /// the numbers correspond to some "generic" X86 CPU instead of usage of 18 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 19 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 20 /// the lookups below the cost is based on Nehalem as that was the first CPU 21 /// to support that feature level and thus has most likely the worst case cost. 22 /// Some examples of other technologies/CPUs: 23 /// SSE 3 - Pentium4 / Athlon64 24 /// SSE 4.1 - Penryn 25 /// SSE 4.2 - Nehalem 26 /// AVX - Sandy Bridge 27 /// AVX2 - Haswell 28 /// AVX-512 - Xeon Phi / Skylake 29 /// And some examples of instruction target dependent costs (latency) 30 /// divss sqrtss rsqrtss 31 /// AMD K7 11-16 19 3 32 /// Piledriver 9-24 13-15 5 33 /// Jaguar 14 16 2 34 /// Pentium II,III 18 30 2 35 /// Nehalem 7-14 7-18 3 36 /// Haswell 10-13 11 5 37 /// TODO: Develop and implement the target dependent cost model and 38 /// specialize cost numbers for different Cost Model Targets such as throughput, 39 /// code size, latency and uop count. 40 //===----------------------------------------------------------------------===// 41 42 #include "X86TargetTransformInfo.h" 43 #include "llvm/Analysis/TargetTransformInfo.h" 44 #include "llvm/CodeGen/BasicTTIImpl.h" 45 #include "llvm/CodeGen/CostTable.h" 46 #include "llvm/CodeGen/TargetLowering.h" 47 #include "llvm/IR/IntrinsicInst.h" 48 #include "llvm/Support/Debug.h" 49 50 using namespace llvm; 51 52 #define DEBUG_TYPE "x86tti" 53 54 //===----------------------------------------------------------------------===// 55 // 56 // X86 cost model. 57 // 58 //===----------------------------------------------------------------------===// 59 60 TargetTransformInfo::PopcntSupportKind 61 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 62 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 63 // TODO: Currently the __builtin_popcount() implementation using SSE3 64 // instructions is inefficient. Once the problem is fixed, we should 65 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 66 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 67 } 68 69 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 70 TargetTransformInfo::CacheLevel Level) const { 71 switch (Level) { 72 case TargetTransformInfo::CacheLevel::L1D: 73 // - Penryn 74 // - Nehalem 75 // - Westmere 76 // - Sandy Bridge 77 // - Ivy Bridge 78 // - Haswell 79 // - Broadwell 80 // - Skylake 81 // - Kabylake 82 return 32 * 1024; // 32 KByte 83 case TargetTransformInfo::CacheLevel::L2D: 84 // - Penryn 85 // - Nehalem 86 // - Westmere 87 // - Sandy Bridge 88 // - Ivy Bridge 89 // - Haswell 90 // - Broadwell 91 // - Skylake 92 // - Kabylake 93 return 256 * 1024; // 256 KByte 94 } 95 96 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 97 } 98 99 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 100 TargetTransformInfo::CacheLevel Level) const { 101 // - Penryn 102 // - Nehalem 103 // - Westmere 104 // - Sandy Bridge 105 // - Ivy Bridge 106 // - Haswell 107 // - Broadwell 108 // - Skylake 109 // - Kabylake 110 switch (Level) { 111 case TargetTransformInfo::CacheLevel::L1D: 112 LLVM_FALLTHROUGH; 113 case TargetTransformInfo::CacheLevel::L2D: 114 return 8; 115 } 116 117 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 118 } 119 120 unsigned X86TTIImpl::getNumberOfRegisters(bool Vector) { 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const { 133 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 134 if (Vector) { 135 if (ST->hasAVX512() && PreferVectorWidth >= 512) 136 return 512; 137 if (ST->hasAVX() && PreferVectorWidth >= 256) 138 return 256; 139 if (ST->hasSSE1() && PreferVectorWidth >= 128) 140 return 128; 141 return 0; 142 } 143 144 if (ST->is64Bit()) 145 return 64; 146 147 return 32; 148 } 149 150 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 151 return getRegisterBitWidth(true); 152 } 153 154 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 155 // If the loop will not be vectorized, don't interleave the loop. 156 // Let regular unroll to unroll the loop, which saves the overflow 157 // check and memory check cost. 158 if (VF == 1) 159 return 1; 160 161 if (ST->isAtom()) 162 return 1; 163 164 // Sandybridge and Haswell have multiple execution ports and pipelined 165 // vector units. 166 if (ST->hasAVX()) 167 return 4; 168 169 return 2; 170 } 171 172 int X86TTIImpl::getArithmeticInstrCost( 173 unsigned Opcode, Type *Ty, 174 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 175 TTI::OperandValueProperties Opd1PropInfo, 176 TTI::OperandValueProperties Opd2PropInfo, 177 ArrayRef<const Value *> Args) { 178 // Legalize the type. 179 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 180 181 int ISD = TLI->InstructionOpcodeToISD(Opcode); 182 assert(ISD && "Invalid opcode"); 183 184 static const CostTblEntry GLMCostTable[] = { 185 { ISD::FDIV, MVT::f32, 18 }, // divss 186 { ISD::FDIV, MVT::v4f32, 35 }, // divps 187 { ISD::FDIV, MVT::f64, 33 }, // divsd 188 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 189 }; 190 191 if (ST->isGLM()) 192 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 193 LT.second)) 194 return LT.first * Entry->Cost; 195 196 static const CostTblEntry SLMCostTable[] = { 197 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 198 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 199 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. 200 { ISD::FMUL, MVT::f64, 2 }, // mulsd 201 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 202 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 203 { ISD::FDIV, MVT::f32, 17 }, // divss 204 { ISD::FDIV, MVT::v4f32, 39 }, // divps 205 { ISD::FDIV, MVT::f64, 32 }, // divsd 206 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 207 { ISD::FADD, MVT::v2f64, 2 }, // addpd 208 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 209 // v2i64/v4i64 mul is custom lowered as a series of long: 210 // multiplies(3), shifts(3) and adds(2) 211 // slm muldq version throughput is 2 and addq throughput 4 212 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 213 // 3X4 (addq throughput) = 17 214 { ISD::MUL, MVT::v2i64, 17 }, 215 // slm addq\subq throughput is 4 216 { ISD::ADD, MVT::v2i64, 4 }, 217 { ISD::SUB, MVT::v2i64, 4 }, 218 }; 219 220 if (ST->isSLM()) { 221 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 222 // Check if the operands can be shrinked into a smaller datatype. 223 bool Op1Signed = false; 224 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 225 bool Op2Signed = false; 226 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 227 228 bool signedMode = Op1Signed | Op2Signed; 229 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 230 231 if (OpMinSize <= 7) 232 return LT.first * 3; // pmullw/sext 233 if (!signedMode && OpMinSize <= 8) 234 return LT.first * 3; // pmullw/zext 235 if (OpMinSize <= 15) 236 return LT.first * 5; // pmullw/pmulhw/pshuf 237 if (!signedMode && OpMinSize <= 16) 238 return LT.first * 5; // pmullw/pmulhw/pshuf 239 } 240 241 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 242 LT.second)) { 243 return LT.first * Entry->Cost; 244 } 245 } 246 247 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 248 ISD == ISD::UREM) && 249 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 250 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 251 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 252 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 253 // On X86, vector signed division by constants power-of-two are 254 // normally expanded to the sequence SRA + SRL + ADD + SRA. 255 // The OperandValue properties may not be the same as that of the previous 256 // operation; conservatively assume OP_None. 257 int Cost = 258 2 * getArithmeticInstrCost(Instruction::AShr, Ty, Op1Info, Op2Info, 259 TargetTransformInfo::OP_None, 260 TargetTransformInfo::OP_None); 261 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 262 TargetTransformInfo::OP_None, 263 TargetTransformInfo::OP_None); 264 Cost += getArithmeticInstrCost(Instruction::Add, Ty, Op1Info, Op2Info, 265 TargetTransformInfo::OP_None, 266 TargetTransformInfo::OP_None); 267 268 if (ISD == ISD::SREM) { 269 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 270 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info); 271 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, Op1Info, Op2Info); 272 } 273 274 return Cost; 275 } 276 277 // Vector unsigned division/remainder will be simplified to shifts/masks. 278 if (ISD == ISD::UDIV) 279 return getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 280 TargetTransformInfo::OP_None, 281 TargetTransformInfo::OP_None); 282 283 if (ISD == ISD::UREM) 284 return getArithmeticInstrCost(Instruction::And, Ty, Op1Info, Op2Info, 285 TargetTransformInfo::OP_None, 286 TargetTransformInfo::OP_None); 287 } 288 289 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 290 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 291 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 292 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 293 }; 294 295 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 296 ST->hasBWI()) { 297 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 298 LT.second)) 299 return LT.first * Entry->Cost; 300 } 301 302 static const CostTblEntry AVX512UniformConstCostTable[] = { 303 { ISD::SRA, MVT::v2i64, 1 }, 304 { ISD::SRA, MVT::v4i64, 1 }, 305 { ISD::SRA, MVT::v8i64, 1 }, 306 }; 307 308 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 309 ST->hasAVX512()) { 310 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 311 LT.second)) 312 return LT.first * Entry->Cost; 313 } 314 315 static const CostTblEntry AVX2UniformConstCostTable[] = { 316 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 317 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 318 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 319 320 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 321 }; 322 323 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 324 ST->hasAVX2()) { 325 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 326 LT.second)) 327 return LT.first * Entry->Cost; 328 } 329 330 static const CostTblEntry SSE2UniformConstCostTable[] = { 331 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 332 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 333 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 334 335 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 336 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 337 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 338 }; 339 340 // XOP has faster vXi8 shifts. 341 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 342 ST->hasSSE2() && !ST->hasXOP()) { 343 if (const auto *Entry = 344 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 345 return LT.first * Entry->Cost; 346 } 347 348 static const CostTblEntry AVX512BWConstCostTable[] = { 349 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 350 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 351 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 352 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 353 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 354 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 355 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 356 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 357 }; 358 359 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 360 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 361 ST->hasBWI()) { 362 if (const auto *Entry = 363 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 364 return LT.first * Entry->Cost; 365 } 366 367 static const CostTblEntry AVX512ConstCostTable[] = { 368 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 369 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 370 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 371 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 372 }; 373 374 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 375 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 376 ST->hasAVX512()) { 377 if (const auto *Entry = 378 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 379 return LT.first * Entry->Cost; 380 } 381 382 static const CostTblEntry AVX2ConstCostTable[] = { 383 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 384 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 385 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 386 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 387 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 388 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 389 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 390 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 391 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 392 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 393 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 394 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 395 }; 396 397 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 398 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 399 ST->hasAVX2()) { 400 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 401 return LT.first * Entry->Cost; 402 } 403 404 static const CostTblEntry SSE2ConstCostTable[] = { 405 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 406 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 407 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 408 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 409 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 410 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 411 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 412 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 413 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 414 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 415 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 416 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 417 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 418 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 419 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 420 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 421 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 422 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 423 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 424 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 425 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 426 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 427 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 428 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 429 }; 430 431 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 432 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 433 ST->hasSSE2()) { 434 // pmuldq sequence. 435 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 436 return LT.first * 32; 437 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 438 return LT.first * 38; 439 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 440 return LT.first * 15; 441 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 442 return LT.first * 20; 443 444 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 445 return LT.first * Entry->Cost; 446 } 447 448 static const CostTblEntry AVX2UniformCostTable[] = { 449 // Uniform splats are cheaper for the following instructions. 450 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 451 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 452 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 453 }; 454 455 if (ST->hasAVX2() && 456 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 457 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 458 if (const auto *Entry = 459 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 460 return LT.first * Entry->Cost; 461 } 462 463 static const CostTblEntry SSE2UniformCostTable[] = { 464 // Uniform splats are cheaper for the following instructions. 465 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 466 { ISD::SHL, MVT::v4i32, 1 }, // pslld 467 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 468 469 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 470 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 471 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 472 473 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 474 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 475 }; 476 477 if (ST->hasSSE2() && 478 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 479 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 480 if (const auto *Entry = 481 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 482 return LT.first * Entry->Cost; 483 } 484 485 static const CostTblEntry AVX512DQCostTable[] = { 486 { ISD::MUL, MVT::v2i64, 1 }, 487 { ISD::MUL, MVT::v4i64, 1 }, 488 { ISD::MUL, MVT::v8i64, 1 } 489 }; 490 491 // Look for AVX512DQ lowering tricks for custom cases. 492 if (ST->hasDQI()) 493 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 494 return LT.first * Entry->Cost; 495 496 static const CostTblEntry AVX512BWCostTable[] = { 497 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 498 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 499 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 500 501 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 502 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 503 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 504 505 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 506 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 507 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 508 509 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 510 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 511 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 512 513 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence. 514 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence. 515 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence. 516 }; 517 518 // Look for AVX512BW lowering tricks for custom cases. 519 if (ST->hasBWI()) 520 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 521 return LT.first * Entry->Cost; 522 523 static const CostTblEntry AVX512CostTable[] = { 524 { ISD::SHL, MVT::v16i32, 1 }, 525 { ISD::SRL, MVT::v16i32, 1 }, 526 { ISD::SRA, MVT::v16i32, 1 }, 527 528 { ISD::SHL, MVT::v8i64, 1 }, 529 { ISD::SRL, MVT::v8i64, 1 }, 530 531 { ISD::SRA, MVT::v2i64, 1 }, 532 { ISD::SRA, MVT::v4i64, 1 }, 533 { ISD::SRA, MVT::v8i64, 1 }, 534 535 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence. 536 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence. 537 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 538 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 539 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 540 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add 541 542 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 543 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 544 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 545 546 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 547 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 548 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 549 }; 550 551 if (ST->hasAVX512()) 552 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 553 return LT.first * Entry->Cost; 554 555 static const CostTblEntry AVX2ShiftCostTable[] = { 556 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 557 // customize them to detect the cases where shift amount is a scalar one. 558 { ISD::SHL, MVT::v4i32, 1 }, 559 { ISD::SRL, MVT::v4i32, 1 }, 560 { ISD::SRA, MVT::v4i32, 1 }, 561 { ISD::SHL, MVT::v8i32, 1 }, 562 { ISD::SRL, MVT::v8i32, 1 }, 563 { ISD::SRA, MVT::v8i32, 1 }, 564 { ISD::SHL, MVT::v2i64, 1 }, 565 { ISD::SRL, MVT::v2i64, 1 }, 566 { ISD::SHL, MVT::v4i64, 1 }, 567 { ISD::SRL, MVT::v4i64, 1 }, 568 }; 569 570 // Look for AVX2 lowering tricks. 571 if (ST->hasAVX2()) { 572 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 573 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 574 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 575 // On AVX2, a packed v16i16 shift left by a constant build_vector 576 // is lowered into a vector multiply (vpmullw). 577 return getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info, 578 TargetTransformInfo::OP_None, 579 TargetTransformInfo::OP_None); 580 581 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 582 return LT.first * Entry->Cost; 583 } 584 585 static const CostTblEntry XOPShiftCostTable[] = { 586 // 128bit shifts take 1cy, but right shifts require negation beforehand. 587 { ISD::SHL, MVT::v16i8, 1 }, 588 { ISD::SRL, MVT::v16i8, 2 }, 589 { ISD::SRA, MVT::v16i8, 2 }, 590 { ISD::SHL, MVT::v8i16, 1 }, 591 { ISD::SRL, MVT::v8i16, 2 }, 592 { ISD::SRA, MVT::v8i16, 2 }, 593 { ISD::SHL, MVT::v4i32, 1 }, 594 { ISD::SRL, MVT::v4i32, 2 }, 595 { ISD::SRA, MVT::v4i32, 2 }, 596 { ISD::SHL, MVT::v2i64, 1 }, 597 { ISD::SRL, MVT::v2i64, 2 }, 598 { ISD::SRA, MVT::v2i64, 2 }, 599 // 256bit shifts require splitting if AVX2 didn't catch them above. 600 { ISD::SHL, MVT::v32i8, 2+2 }, 601 { ISD::SRL, MVT::v32i8, 4+2 }, 602 { ISD::SRA, MVT::v32i8, 4+2 }, 603 { ISD::SHL, MVT::v16i16, 2+2 }, 604 { ISD::SRL, MVT::v16i16, 4+2 }, 605 { ISD::SRA, MVT::v16i16, 4+2 }, 606 { ISD::SHL, MVT::v8i32, 2+2 }, 607 { ISD::SRL, MVT::v8i32, 4+2 }, 608 { ISD::SRA, MVT::v8i32, 4+2 }, 609 { ISD::SHL, MVT::v4i64, 2+2 }, 610 { ISD::SRL, MVT::v4i64, 4+2 }, 611 { ISD::SRA, MVT::v4i64, 4+2 }, 612 }; 613 614 // Look for XOP lowering tricks. 615 if (ST->hasXOP()) { 616 // If the right shift is constant then we'll fold the negation so 617 // it's as cheap as a left shift. 618 int ShiftISD = ISD; 619 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 620 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 621 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 622 ShiftISD = ISD::SHL; 623 if (const auto *Entry = 624 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 625 return LT.first * Entry->Cost; 626 } 627 628 static const CostTblEntry SSE2UniformShiftCostTable[] = { 629 // Uniform splats are cheaper for the following instructions. 630 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 631 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 632 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 633 634 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 635 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 636 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 637 638 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 639 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 640 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 641 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 642 }; 643 644 if (ST->hasSSE2() && 645 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 646 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 647 648 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 649 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 650 return LT.first * 4; // 2*psrad + shuffle. 651 652 if (const auto *Entry = 653 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 654 return LT.first * Entry->Cost; 655 } 656 657 if (ISD == ISD::SHL && 658 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 659 MVT VT = LT.second; 660 // Vector shift left by non uniform constant can be lowered 661 // into vector multiply. 662 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 663 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 664 ISD = ISD::MUL; 665 } 666 667 static const CostTblEntry AVX2CostTable[] = { 668 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. 669 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 670 671 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. 672 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 673 674 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. 675 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. 676 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. 677 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 678 679 { ISD::SUB, MVT::v32i8, 1 }, // psubb 680 { ISD::ADD, MVT::v32i8, 1 }, // paddb 681 { ISD::SUB, MVT::v16i16, 1 }, // psubw 682 { ISD::ADD, MVT::v16i16, 1 }, // paddw 683 { ISD::SUB, MVT::v8i32, 1 }, // psubd 684 { ISD::ADD, MVT::v8i32, 1 }, // paddd 685 { ISD::SUB, MVT::v4i64, 1 }, // psubq 686 { ISD::ADD, MVT::v4i64, 1 }, // paddq 687 688 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence. 689 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence. 690 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 691 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 692 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add 693 694 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 695 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 696 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 697 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 698 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 699 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 700 701 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 702 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 703 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 704 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 705 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 706 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 707 }; 708 709 // Look for AVX2 lowering tricks for custom cases. 710 if (ST->hasAVX2()) 711 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 712 return LT.first * Entry->Cost; 713 714 static const CostTblEntry AVX1CostTable[] = { 715 // We don't have to scalarize unsupported ops. We can issue two half-sized 716 // operations and we only need to extract the upper YMM half. 717 // Two ops + 1 extract + 1 insert = 4. 718 { ISD::MUL, MVT::v16i16, 4 }, 719 { ISD::MUL, MVT::v8i32, 4 }, 720 { ISD::SUB, MVT::v32i8, 4 }, 721 { ISD::ADD, MVT::v32i8, 4 }, 722 { ISD::SUB, MVT::v16i16, 4 }, 723 { ISD::ADD, MVT::v16i16, 4 }, 724 { ISD::SUB, MVT::v8i32, 4 }, 725 { ISD::ADD, MVT::v8i32, 4 }, 726 { ISD::SUB, MVT::v4i64, 4 }, 727 { ISD::ADD, MVT::v4i64, 4 }, 728 729 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 730 // are lowered as a series of long multiplies(3), shifts(3) and adds(2) 731 // Because we believe v4i64 to be a legal type, we must also include the 732 // extract+insert in the cost table. Therefore, the cost here is 18 733 // instead of 8. 734 { ISD::MUL, MVT::v4i64, 18 }, 735 736 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence. 737 738 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 739 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 740 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 741 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 742 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 743 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 744 }; 745 746 if (ST->hasAVX()) 747 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 748 return LT.first * Entry->Cost; 749 750 static const CostTblEntry SSE42CostTable[] = { 751 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 752 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 753 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 754 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 755 756 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 757 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 758 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 759 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 760 761 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 762 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 763 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 764 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 765 766 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 767 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 768 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 769 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 770 }; 771 772 if (ST->hasSSE42()) 773 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 774 return LT.first * Entry->Cost; 775 776 static const CostTblEntry SSE41CostTable[] = { 777 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 778 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split. 779 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 780 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 781 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 782 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split 783 784 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 785 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split. 786 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 787 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 788 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 789 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split. 790 791 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 792 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split. 793 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 794 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 795 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 796 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split. 797 798 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 799 }; 800 801 if (ST->hasSSE41()) 802 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 803 return LT.first * Entry->Cost; 804 805 static const CostTblEntry SSE2CostTable[] = { 806 // We don't correctly identify costs of casts because they are marked as 807 // custom. 808 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 809 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 810 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 811 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 812 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 813 814 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 815 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 816 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 817 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 818 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 819 820 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 821 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 822 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 823 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 824 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split. 825 826 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence. 827 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 828 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 829 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 830 831 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 832 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 833 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 834 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 835 836 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 837 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 838 839 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 840 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 841 }; 842 843 if (ST->hasSSE2()) 844 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 845 return LT.first * Entry->Cost; 846 847 static const CostTblEntry SSE1CostTable[] = { 848 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 849 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 850 851 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 852 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 853 854 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 855 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 856 857 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 858 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 859 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 860 861 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 862 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 863 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 864 }; 865 866 if (ST->hasSSE1()) 867 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 868 return LT.first * Entry->Cost; 869 870 // It is not a good idea to vectorize division. We have to scalarize it and 871 // in the process we will often end up having to spilling regular 872 // registers. The overhead of division is going to dominate most kernels 873 // anyways so try hard to prevent vectorization of division - it is 874 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 875 // to hide "20 cycles" for each lane. 876 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 877 ISD == ISD::UDIV || ISD == ISD::UREM)) { 878 int ScalarCost = getArithmeticInstrCost( 879 Opcode, Ty->getScalarType(), Op1Info, Op2Info, 880 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 881 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 882 } 883 884 // Fallback to the default implementation. 885 return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info); 886 } 887 888 int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, 889 Type *SubTp) { 890 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 891 // 64-bit packed integer vectors (v2i32) are promoted to type v2i64. 892 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp); 893 894 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 895 if (Kind == TTI::SK_Transpose) 896 Kind = TTI::SK_PermuteTwoSrc; 897 898 // For Broadcasts we are splatting the first element from the first input 899 // register, so only need to reference that input and all the output 900 // registers are the same. 901 if (Kind == TTI::SK_Broadcast) 902 LT.first = 1; 903 904 // Subvector extractions are free if they start at the beginning of a 905 // vector and cheap if the subvectors are aligned. 906 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 907 int NumElts = LT.second.getVectorNumElements(); 908 if ((Index % NumElts) == 0) 909 return 0; 910 std::pair<int, MVT> SubLT = TLI->getTypeLegalizationCost(DL, SubTp); 911 if (SubLT.second.isVector()) { 912 int NumSubElts = SubLT.second.getVectorNumElements(); 913 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 914 return SubLT.first; 915 } 916 } 917 918 // We are going to permute multiple sources and the result will be in multiple 919 // destinations. Providing an accurate cost only for splits where the element 920 // type remains the same. 921 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 922 MVT LegalVT = LT.second; 923 if (LegalVT.isVector() && 924 LegalVT.getVectorElementType().getSizeInBits() == 925 Tp->getVectorElementType()->getPrimitiveSizeInBits() && 926 LegalVT.getVectorNumElements() < Tp->getVectorNumElements()) { 927 928 unsigned VecTySize = DL.getTypeStoreSize(Tp); 929 unsigned LegalVTSize = LegalVT.getStoreSize(); 930 // Number of source vectors after legalization: 931 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 932 // Number of destination vectors after legalization: 933 unsigned NumOfDests = LT.first; 934 935 Type *SingleOpTy = VectorType::get(Tp->getVectorElementType(), 936 LegalVT.getVectorNumElements()); 937 938 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 939 return NumOfShuffles * 940 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 0, nullptr); 941 } 942 943 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 944 } 945 946 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 947 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 948 // We assume that source and destination have the same vector type. 949 int NumOfDests = LT.first; 950 int NumOfShufflesPerDest = LT.first * 2 - 1; 951 LT.first = NumOfDests * NumOfShufflesPerDest; 952 } 953 954 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 955 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 956 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 957 958 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 959 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 960 961 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 1}, // vpermt2b 962 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 1}, // vpermt2b 963 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1} // vpermt2b 964 }; 965 966 if (ST->hasVBMI()) 967 if (const auto *Entry = 968 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 969 return LT.first * Entry->Cost; 970 971 static const CostTblEntry AVX512BWShuffleTbl[] = { 972 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 973 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 974 975 {TTI::SK_Reverse, MVT::v32i16, 1}, // vpermw 976 {TTI::SK_Reverse, MVT::v16i16, 1}, // vpermw 977 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 978 979 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 1}, // vpermw 980 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 1}, // vpermw 981 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // vpermw 982 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 983 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 3}, // vpermw + zext/trunc 984 985 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 1}, // vpermt2w 986 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 1}, // vpermt2w 987 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpermt2w 988 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 3}, // zext + vpermt2w + trunc 989 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 990 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3} // zext + vpermt2w + trunc 991 }; 992 993 if (ST->hasBWI()) 994 if (const auto *Entry = 995 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 996 return LT.first * Entry->Cost; 997 998 static const CostTblEntry AVX512ShuffleTbl[] = { 999 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1000 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1001 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1002 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1003 1004 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1005 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1006 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1007 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1008 1009 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1010 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1011 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1012 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1013 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1014 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1015 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1016 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1017 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1018 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1019 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1020 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1021 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1022 1023 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1024 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1025 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1026 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1027 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1028 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1029 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1030 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1031 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1032 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1033 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1034 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1} // vpermt2d 1035 }; 1036 1037 if (ST->hasAVX512()) 1038 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1039 return LT.first * Entry->Cost; 1040 1041 static const CostTblEntry AVX2ShuffleTbl[] = { 1042 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1043 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1044 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1045 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1046 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1047 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1048 1049 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1050 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1051 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1052 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1053 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1054 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1055 1056 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1057 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1058 1059 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1060 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1061 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1062 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1063 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1064 // + vpblendvb 1065 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1066 // + vpblendvb 1067 1068 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1069 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1070 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1071 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1072 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1073 // + vpblendvb 1074 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1075 // + vpblendvb 1076 }; 1077 1078 if (ST->hasAVX2()) 1079 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1080 return LT.first * Entry->Cost; 1081 1082 static const CostTblEntry XOPShuffleTbl[] = { 1083 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1084 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1085 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1086 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1087 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1088 // + vinsertf128 1089 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1090 // + vinsertf128 1091 1092 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1093 // + vinsertf128 1094 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1095 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1096 // + vinsertf128 1097 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1098 }; 1099 1100 if (ST->hasXOP()) 1101 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1102 return LT.first * Entry->Cost; 1103 1104 static const CostTblEntry AVX1ShuffleTbl[] = { 1105 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1106 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1107 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1108 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1109 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1110 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1111 1112 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1113 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1114 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1115 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1116 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1117 // + vinsertf128 1118 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1119 // + vinsertf128 1120 1121 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1122 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1123 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1124 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1125 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1126 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1127 1128 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1129 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1130 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1131 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1132 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1133 // + 2*por + vinsertf128 1134 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1135 // + 2*por + vinsertf128 1136 1137 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1138 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1139 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1140 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1141 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1142 // + 4*por + vinsertf128 1143 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1144 // + 4*por + vinsertf128 1145 }; 1146 1147 if (ST->hasAVX()) 1148 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1149 return LT.first * Entry->Cost; 1150 1151 static const CostTblEntry SSE41ShuffleTbl[] = { 1152 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1153 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1154 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1155 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1156 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1157 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1158 }; 1159 1160 if (ST->hasSSE41()) 1161 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1162 return LT.first * Entry->Cost; 1163 1164 static const CostTblEntry SSSE3ShuffleTbl[] = { 1165 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1166 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1167 1168 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1169 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1170 1171 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1172 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1173 1174 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1175 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1176 1177 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1178 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1179 }; 1180 1181 if (ST->hasSSSE3()) 1182 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1183 return LT.first * Entry->Cost; 1184 1185 static const CostTblEntry SSE2ShuffleTbl[] = { 1186 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1187 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1188 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1189 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1190 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1191 1192 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1193 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1194 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1195 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1196 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1197 // + 2*pshufd + 2*unpck + packus 1198 1199 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1200 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1201 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1202 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1203 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1204 1205 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1206 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1207 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1208 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1209 // + pshufd/unpck 1210 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1211 // + 2*pshufd + 2*unpck + 2*packus 1212 1213 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1214 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1215 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1216 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1217 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1218 }; 1219 1220 if (ST->hasSSE2()) 1221 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1222 return LT.first * Entry->Cost; 1223 1224 static const CostTblEntry SSE1ShuffleTbl[] = { 1225 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1226 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1227 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1228 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1229 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1230 }; 1231 1232 if (ST->hasSSE1()) 1233 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1234 return LT.first * Entry->Cost; 1235 1236 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 1237 } 1238 1239 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 1240 const Instruction *I) { 1241 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1242 assert(ISD && "Invalid opcode"); 1243 1244 // FIXME: Need a better design of the cost table to handle non-simple types of 1245 // potential massive combinations (elem_num x src_type x dst_type). 1246 1247 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1248 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1249 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1250 1251 // Mask sign extend has an instruction. 1252 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1253 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1254 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1255 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1256 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1257 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1258 1259 // Mask zero extend is a load + broadcast. 1260 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1261 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1262 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1263 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1264 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1265 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1266 }; 1267 1268 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1269 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1270 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1271 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1272 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1273 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1274 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1275 1276 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1277 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1278 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1279 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1280 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1281 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1282 1283 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1284 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1285 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1286 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1287 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1288 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1289 1290 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1291 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1292 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1293 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1294 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1295 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1296 }; 1297 1298 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1299 // 256-bit wide vectors. 1300 1301 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1302 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1303 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1304 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1305 1306 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 }, 1307 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 }, 1308 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 }, 1309 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 1310 1311 // v16i1 -> v16i32 - load + broadcast 1312 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1313 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1314 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1315 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1316 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1317 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1318 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1319 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1320 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1321 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1322 1323 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1324 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1325 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1326 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1327 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1328 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1329 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1330 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1331 1332 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1333 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1334 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1335 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1336 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1337 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1338 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1339 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1340 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1341 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1342 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1343 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1344 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1345 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1346 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1347 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1348 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1349 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1350 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1351 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1352 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1353 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1354 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1355 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1356 1357 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1358 1359 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1360 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1361 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1362 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1363 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 2 }, 1364 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 2 }, 1365 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1366 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 2 }, 1367 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 2 }, 1368 }; 1369 1370 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1371 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1372 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1373 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1374 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1375 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 1376 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 1377 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 1378 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 1379 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1380 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1381 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1382 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1383 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1384 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1385 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1386 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1387 1388 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 1389 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 1390 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1391 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 1392 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1393 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 }, 1394 1395 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1396 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1397 1398 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1399 }; 1400 1401 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1402 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1403 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1404 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1405 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1406 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 }, 1407 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1408 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 7 }, 1409 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1410 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1411 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1412 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 }, 1413 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1414 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1415 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1416 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1417 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1418 1419 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 1420 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1421 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1422 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1423 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 1424 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 }, 1425 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 }, 1426 1427 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1428 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1429 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1430 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1431 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1432 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1433 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1434 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1435 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1436 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1437 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1438 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1439 1440 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1441 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1442 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1443 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1444 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1445 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1446 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1447 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1448 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1449 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 }, 1450 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 1451 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1452 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 1453 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1454 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1455 // The generic code to compute the scalar overhead is currently broken. 1456 // Workaround this limitation by estimating the scalarization overhead 1457 // here. We have roughly 10 instructions per scalar element. 1458 // Multiply that by the vector width. 1459 // FIXME: remove that when PR19268 is fixed. 1460 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1461 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1462 1463 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 }, 1464 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 }, 1465 // This node is expanded into scalarized operations but BasicTTI is overly 1466 // optimistic estimating its cost. It computes 3 per element (one 1467 // vector-extract, one scalar conversion and one vector-insert). The 1468 // problem is that the inserts form a read-modify-write chain so latency 1469 // should be factored in too. Inflating the cost per element by 1. 1470 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, 1471 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 1472 1473 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 1474 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 1475 }; 1476 1477 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 1478 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1479 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1480 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1481 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1482 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1483 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1484 1485 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1486 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 }, 1487 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1488 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1489 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1490 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1491 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1492 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1493 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1494 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1495 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1496 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1497 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1498 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1499 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1500 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1501 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1502 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1503 1504 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, 1505 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 1506 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 1507 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 1508 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 1509 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 1510 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 1511 1512 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 1513 }; 1514 1515 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 1516 // These are somewhat magic numbers justified by looking at the output of 1517 // Intel's IACA, running some kernels and making sure when we take 1518 // legalization into account the throughput will be overestimated. 1519 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1520 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1521 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1522 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1523 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1524 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1525 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1526 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 1527 1528 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1529 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1530 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1531 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1532 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1533 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, 1534 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 }, 1535 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1536 1537 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 3 }, 1538 1539 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 }, 1540 1541 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1542 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 1543 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 1544 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 1545 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1546 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 1547 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1548 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 1549 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1550 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1551 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1552 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1553 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 1554 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 1555 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1556 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 1557 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1558 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 1559 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1560 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1561 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 1562 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 1563 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1564 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 1565 1566 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 4 }, 1567 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, 1568 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 1569 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 1570 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 1571 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1572 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 1573 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1574 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 1575 }; 1576 1577 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 1578 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst); 1579 1580 if (ST->hasSSE2() && !ST->hasAVX()) { 1581 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1582 LTDest.second, LTSrc.second)) 1583 return LTSrc.first * Entry->Cost; 1584 } 1585 1586 EVT SrcTy = TLI->getValueType(DL, Src); 1587 EVT DstTy = TLI->getValueType(DL, Dst); 1588 1589 // The function getSimpleVT only handles simple value types. 1590 if (!SrcTy.isSimple() || !DstTy.isSimple()) 1591 return BaseT::getCastInstrCost(Opcode, Dst, Src); 1592 1593 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 1594 MVT SimpleDstTy = DstTy.getSimpleVT(); 1595 1596 // Make sure that neither type is going to be split before using the 1597 // AVX512 tables. This handles -mprefer-vector-width=256 1598 // with -min-legal-vector-width<=256 1599 if (TLI->getTypeAction(SimpleSrcTy) != TargetLowering::TypeSplitVector && 1600 TLI->getTypeAction(SimpleDstTy) != TargetLowering::TypeSplitVector) { 1601 if (ST->hasBWI()) 1602 if (const auto *Entry = ConvertCostTableLookup(AVX512BWConversionTbl, ISD, 1603 SimpleDstTy, SimpleSrcTy)) 1604 return Entry->Cost; 1605 1606 if (ST->hasDQI()) 1607 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 1608 SimpleDstTy, SimpleSrcTy)) 1609 return Entry->Cost; 1610 1611 if (ST->hasAVX512()) 1612 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 1613 SimpleDstTy, SimpleSrcTy)) 1614 return Entry->Cost; 1615 } 1616 1617 if (ST->hasAVX2()) { 1618 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 1619 SimpleDstTy, SimpleSrcTy)) 1620 return Entry->Cost; 1621 } 1622 1623 if (ST->hasAVX()) { 1624 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 1625 SimpleDstTy, SimpleSrcTy)) 1626 return Entry->Cost; 1627 } 1628 1629 if (ST->hasSSE41()) { 1630 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 1631 SimpleDstTy, SimpleSrcTy)) 1632 return Entry->Cost; 1633 } 1634 1635 if (ST->hasSSE2()) { 1636 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1637 SimpleDstTy, SimpleSrcTy)) 1638 return Entry->Cost; 1639 } 1640 1641 return BaseT::getCastInstrCost(Opcode, Dst, Src, I); 1642 } 1643 1644 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 1645 const Instruction *I) { 1646 // Legalize the type. 1647 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 1648 1649 MVT MTy = LT.second; 1650 1651 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1652 assert(ISD && "Invalid opcode"); 1653 1654 static const CostTblEntry SSE2CostTbl[] = { 1655 { ISD::SETCC, MVT::v2i64, 8 }, 1656 { ISD::SETCC, MVT::v4i32, 1 }, 1657 { ISD::SETCC, MVT::v8i16, 1 }, 1658 { ISD::SETCC, MVT::v16i8, 1 }, 1659 }; 1660 1661 static const CostTblEntry SSE42CostTbl[] = { 1662 { ISD::SETCC, MVT::v2f64, 1 }, 1663 { ISD::SETCC, MVT::v4f32, 1 }, 1664 { ISD::SETCC, MVT::v2i64, 1 }, 1665 }; 1666 1667 static const CostTblEntry AVX1CostTbl[] = { 1668 { ISD::SETCC, MVT::v4f64, 1 }, 1669 { ISD::SETCC, MVT::v8f32, 1 }, 1670 // AVX1 does not support 8-wide integer compare. 1671 { ISD::SETCC, MVT::v4i64, 4 }, 1672 { ISD::SETCC, MVT::v8i32, 4 }, 1673 { ISD::SETCC, MVT::v16i16, 4 }, 1674 { ISD::SETCC, MVT::v32i8, 4 }, 1675 }; 1676 1677 static const CostTblEntry AVX2CostTbl[] = { 1678 { ISD::SETCC, MVT::v4i64, 1 }, 1679 { ISD::SETCC, MVT::v8i32, 1 }, 1680 { ISD::SETCC, MVT::v16i16, 1 }, 1681 { ISD::SETCC, MVT::v32i8, 1 }, 1682 }; 1683 1684 static const CostTblEntry AVX512CostTbl[] = { 1685 { ISD::SETCC, MVT::v8i64, 1 }, 1686 { ISD::SETCC, MVT::v16i32, 1 }, 1687 { ISD::SETCC, MVT::v8f64, 1 }, 1688 { ISD::SETCC, MVT::v16f32, 1 }, 1689 }; 1690 1691 static const CostTblEntry AVX512BWCostTbl[] = { 1692 { ISD::SETCC, MVT::v32i16, 1 }, 1693 { ISD::SETCC, MVT::v64i8, 1 }, 1694 }; 1695 1696 if (ST->hasBWI()) 1697 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 1698 return LT.first * Entry->Cost; 1699 1700 if (ST->hasAVX512()) 1701 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 1702 return LT.first * Entry->Cost; 1703 1704 if (ST->hasAVX2()) 1705 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 1706 return LT.first * Entry->Cost; 1707 1708 if (ST->hasAVX()) 1709 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 1710 return LT.first * Entry->Cost; 1711 1712 if (ST->hasSSE42()) 1713 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 1714 return LT.first * Entry->Cost; 1715 1716 if (ST->hasSSE2()) 1717 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 1718 return LT.first * Entry->Cost; 1719 1720 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I); 1721 } 1722 1723 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 1724 1725 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 1726 ArrayRef<Type *> Tys, FastMathFlags FMF, 1727 unsigned ScalarizationCostPassed) { 1728 // Costs should match the codegen from: 1729 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 1730 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 1731 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 1732 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 1733 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 1734 static const CostTblEntry AVX512CDCostTbl[] = { 1735 { ISD::CTLZ, MVT::v8i64, 1 }, 1736 { ISD::CTLZ, MVT::v16i32, 1 }, 1737 { ISD::CTLZ, MVT::v32i16, 8 }, 1738 { ISD::CTLZ, MVT::v64i8, 20 }, 1739 { ISD::CTLZ, MVT::v4i64, 1 }, 1740 { ISD::CTLZ, MVT::v8i32, 1 }, 1741 { ISD::CTLZ, MVT::v16i16, 4 }, 1742 { ISD::CTLZ, MVT::v32i8, 10 }, 1743 { ISD::CTLZ, MVT::v2i64, 1 }, 1744 { ISD::CTLZ, MVT::v4i32, 1 }, 1745 { ISD::CTLZ, MVT::v8i16, 4 }, 1746 { ISD::CTLZ, MVT::v16i8, 4 }, 1747 }; 1748 static const CostTblEntry AVX512BWCostTbl[] = { 1749 { ISD::BITREVERSE, MVT::v8i64, 5 }, 1750 { ISD::BITREVERSE, MVT::v16i32, 5 }, 1751 { ISD::BITREVERSE, MVT::v32i16, 5 }, 1752 { ISD::BITREVERSE, MVT::v64i8, 5 }, 1753 { ISD::CTLZ, MVT::v8i64, 23 }, 1754 { ISD::CTLZ, MVT::v16i32, 22 }, 1755 { ISD::CTLZ, MVT::v32i16, 18 }, 1756 { ISD::CTLZ, MVT::v64i8, 17 }, 1757 { ISD::CTPOP, MVT::v8i64, 7 }, 1758 { ISD::CTPOP, MVT::v16i32, 11 }, 1759 { ISD::CTPOP, MVT::v32i16, 9 }, 1760 { ISD::CTPOP, MVT::v64i8, 6 }, 1761 { ISD::CTTZ, MVT::v8i64, 10 }, 1762 { ISD::CTTZ, MVT::v16i32, 14 }, 1763 { ISD::CTTZ, MVT::v32i16, 12 }, 1764 { ISD::CTTZ, MVT::v64i8, 9 }, 1765 { ISD::SADDSAT, MVT::v32i16, 1 }, 1766 { ISD::SADDSAT, MVT::v64i8, 1 }, 1767 { ISD::SSUBSAT, MVT::v32i16, 1 }, 1768 { ISD::SSUBSAT, MVT::v64i8, 1 }, 1769 { ISD::UADDSAT, MVT::v32i16, 1 }, 1770 { ISD::UADDSAT, MVT::v64i8, 1 }, 1771 { ISD::USUBSAT, MVT::v32i16, 1 }, 1772 { ISD::USUBSAT, MVT::v64i8, 1 }, 1773 }; 1774 static const CostTblEntry AVX512CostTbl[] = { 1775 { ISD::BITREVERSE, MVT::v8i64, 36 }, 1776 { ISD::BITREVERSE, MVT::v16i32, 24 }, 1777 { ISD::CTLZ, MVT::v8i64, 29 }, 1778 { ISD::CTLZ, MVT::v16i32, 35 }, 1779 { ISD::CTPOP, MVT::v8i64, 16 }, 1780 { ISD::CTPOP, MVT::v16i32, 24 }, 1781 { ISD::CTTZ, MVT::v8i64, 20 }, 1782 { ISD::CTTZ, MVT::v16i32, 28 }, 1783 }; 1784 static const CostTblEntry XOPCostTbl[] = { 1785 { ISD::BITREVERSE, MVT::v4i64, 4 }, 1786 { ISD::BITREVERSE, MVT::v8i32, 4 }, 1787 { ISD::BITREVERSE, MVT::v16i16, 4 }, 1788 { ISD::BITREVERSE, MVT::v32i8, 4 }, 1789 { ISD::BITREVERSE, MVT::v2i64, 1 }, 1790 { ISD::BITREVERSE, MVT::v4i32, 1 }, 1791 { ISD::BITREVERSE, MVT::v8i16, 1 }, 1792 { ISD::BITREVERSE, MVT::v16i8, 1 }, 1793 { ISD::BITREVERSE, MVT::i64, 3 }, 1794 { ISD::BITREVERSE, MVT::i32, 3 }, 1795 { ISD::BITREVERSE, MVT::i16, 3 }, 1796 { ISD::BITREVERSE, MVT::i8, 3 } 1797 }; 1798 static const CostTblEntry AVX2CostTbl[] = { 1799 { ISD::BITREVERSE, MVT::v4i64, 5 }, 1800 { ISD::BITREVERSE, MVT::v8i32, 5 }, 1801 { ISD::BITREVERSE, MVT::v16i16, 5 }, 1802 { ISD::BITREVERSE, MVT::v32i8, 5 }, 1803 { ISD::BSWAP, MVT::v4i64, 1 }, 1804 { ISD::BSWAP, MVT::v8i32, 1 }, 1805 { ISD::BSWAP, MVT::v16i16, 1 }, 1806 { ISD::CTLZ, MVT::v4i64, 23 }, 1807 { ISD::CTLZ, MVT::v8i32, 18 }, 1808 { ISD::CTLZ, MVT::v16i16, 14 }, 1809 { ISD::CTLZ, MVT::v32i8, 9 }, 1810 { ISD::CTPOP, MVT::v4i64, 7 }, 1811 { ISD::CTPOP, MVT::v8i32, 11 }, 1812 { ISD::CTPOP, MVT::v16i16, 9 }, 1813 { ISD::CTPOP, MVT::v32i8, 6 }, 1814 { ISD::CTTZ, MVT::v4i64, 10 }, 1815 { ISD::CTTZ, MVT::v8i32, 14 }, 1816 { ISD::CTTZ, MVT::v16i16, 12 }, 1817 { ISD::CTTZ, MVT::v32i8, 9 }, 1818 { ISD::SADDSAT, MVT::v16i16, 1 }, 1819 { ISD::SADDSAT, MVT::v32i8, 1 }, 1820 { ISD::SSUBSAT, MVT::v16i16, 1 }, 1821 { ISD::SSUBSAT, MVT::v32i8, 1 }, 1822 { ISD::UADDSAT, MVT::v16i16, 1 }, 1823 { ISD::UADDSAT, MVT::v32i8, 1 }, 1824 { ISD::USUBSAT, MVT::v16i16, 1 }, 1825 { ISD::USUBSAT, MVT::v32i8, 1 }, 1826 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 1827 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 1828 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 1829 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 1830 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 1831 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 1832 }; 1833 static const CostTblEntry AVX1CostTbl[] = { 1834 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 1835 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 1836 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 1837 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 1838 { ISD::BSWAP, MVT::v4i64, 4 }, 1839 { ISD::BSWAP, MVT::v8i32, 4 }, 1840 { ISD::BSWAP, MVT::v16i16, 4 }, 1841 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 1842 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 1843 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 1844 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 1845 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 1846 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 1847 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 1848 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 1849 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 1850 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 1851 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 1852 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 1853 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 1854 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 1855 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 1856 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 1857 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 1858 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 1859 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 1860 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 1861 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 1862 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 1863 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 1864 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 1865 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 1866 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 1867 }; 1868 static const CostTblEntry GLMCostTbl[] = { 1869 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 1870 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 1871 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 1872 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 1873 }; 1874 static const CostTblEntry SLMCostTbl[] = { 1875 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 1876 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 1877 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 1878 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 1879 }; 1880 static const CostTblEntry SSE42CostTbl[] = { 1881 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 1882 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 1883 }; 1884 static const CostTblEntry SSSE3CostTbl[] = { 1885 { ISD::BITREVERSE, MVT::v2i64, 5 }, 1886 { ISD::BITREVERSE, MVT::v4i32, 5 }, 1887 { ISD::BITREVERSE, MVT::v8i16, 5 }, 1888 { ISD::BITREVERSE, MVT::v16i8, 5 }, 1889 { ISD::BSWAP, MVT::v2i64, 1 }, 1890 { ISD::BSWAP, MVT::v4i32, 1 }, 1891 { ISD::BSWAP, MVT::v8i16, 1 }, 1892 { ISD::CTLZ, MVT::v2i64, 23 }, 1893 { ISD::CTLZ, MVT::v4i32, 18 }, 1894 { ISD::CTLZ, MVT::v8i16, 14 }, 1895 { ISD::CTLZ, MVT::v16i8, 9 }, 1896 { ISD::CTPOP, MVT::v2i64, 7 }, 1897 { ISD::CTPOP, MVT::v4i32, 11 }, 1898 { ISD::CTPOP, MVT::v8i16, 9 }, 1899 { ISD::CTPOP, MVT::v16i8, 6 }, 1900 { ISD::CTTZ, MVT::v2i64, 10 }, 1901 { ISD::CTTZ, MVT::v4i32, 14 }, 1902 { ISD::CTTZ, MVT::v8i16, 12 }, 1903 { ISD::CTTZ, MVT::v16i8, 9 } 1904 }; 1905 static const CostTblEntry SSE2CostTbl[] = { 1906 { ISD::BITREVERSE, MVT::v2i64, 29 }, 1907 { ISD::BITREVERSE, MVT::v4i32, 27 }, 1908 { ISD::BITREVERSE, MVT::v8i16, 27 }, 1909 { ISD::BITREVERSE, MVT::v16i8, 20 }, 1910 { ISD::BSWAP, MVT::v2i64, 7 }, 1911 { ISD::BSWAP, MVT::v4i32, 7 }, 1912 { ISD::BSWAP, MVT::v8i16, 7 }, 1913 { ISD::CTLZ, MVT::v2i64, 25 }, 1914 { ISD::CTLZ, MVT::v4i32, 26 }, 1915 { ISD::CTLZ, MVT::v8i16, 20 }, 1916 { ISD::CTLZ, MVT::v16i8, 17 }, 1917 { ISD::CTPOP, MVT::v2i64, 12 }, 1918 { ISD::CTPOP, MVT::v4i32, 15 }, 1919 { ISD::CTPOP, MVT::v8i16, 13 }, 1920 { ISD::CTPOP, MVT::v16i8, 10 }, 1921 { ISD::CTTZ, MVT::v2i64, 14 }, 1922 { ISD::CTTZ, MVT::v4i32, 18 }, 1923 { ISD::CTTZ, MVT::v8i16, 16 }, 1924 { ISD::CTTZ, MVT::v16i8, 13 }, 1925 { ISD::SADDSAT, MVT::v8i16, 1 }, 1926 { ISD::SADDSAT, MVT::v16i8, 1 }, 1927 { ISD::SSUBSAT, MVT::v8i16, 1 }, 1928 { ISD::SSUBSAT, MVT::v16i8, 1 }, 1929 { ISD::UADDSAT, MVT::v8i16, 1 }, 1930 { ISD::UADDSAT, MVT::v16i8, 1 }, 1931 { ISD::USUBSAT, MVT::v8i16, 1 }, 1932 { ISD::USUBSAT, MVT::v16i8, 1 }, 1933 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 1934 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 1935 }; 1936 static const CostTblEntry SSE1CostTbl[] = { 1937 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 1938 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 1939 }; 1940 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 1941 { ISD::BITREVERSE, MVT::i64, 14 } 1942 }; 1943 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 1944 { ISD::BITREVERSE, MVT::i32, 14 }, 1945 { ISD::BITREVERSE, MVT::i16, 14 }, 1946 { ISD::BITREVERSE, MVT::i8, 11 } 1947 }; 1948 1949 unsigned ISD = ISD::DELETED_NODE; 1950 switch (IID) { 1951 default: 1952 break; 1953 case Intrinsic::bitreverse: 1954 ISD = ISD::BITREVERSE; 1955 break; 1956 case Intrinsic::bswap: 1957 ISD = ISD::BSWAP; 1958 break; 1959 case Intrinsic::ctlz: 1960 ISD = ISD::CTLZ; 1961 break; 1962 case Intrinsic::ctpop: 1963 ISD = ISD::CTPOP; 1964 break; 1965 case Intrinsic::cttz: 1966 ISD = ISD::CTTZ; 1967 break; 1968 case Intrinsic::sadd_sat: 1969 ISD = ISD::SADDSAT; 1970 break; 1971 case Intrinsic::ssub_sat: 1972 ISD = ISD::SSUBSAT; 1973 break; 1974 case Intrinsic::uadd_sat: 1975 ISD = ISD::UADDSAT; 1976 break; 1977 case Intrinsic::usub_sat: 1978 ISD = ISD::USUBSAT; 1979 break; 1980 case Intrinsic::sqrt: 1981 ISD = ISD::FSQRT; 1982 break; 1983 } 1984 1985 if (ISD != ISD::DELETED_NODE) { 1986 // Legalize the type. 1987 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 1988 MVT MTy = LT.second; 1989 1990 // Attempt to lookup cost. 1991 if (ST->isGLM()) 1992 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 1993 return LT.first * Entry->Cost; 1994 1995 if (ST->isSLM()) 1996 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 1997 return LT.first * Entry->Cost; 1998 1999 if (ST->hasCDI()) 2000 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 2001 return LT.first * Entry->Cost; 2002 2003 if (ST->hasBWI()) 2004 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2005 return LT.first * Entry->Cost; 2006 2007 if (ST->hasAVX512()) 2008 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2009 return LT.first * Entry->Cost; 2010 2011 if (ST->hasXOP()) 2012 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2013 return LT.first * Entry->Cost; 2014 2015 if (ST->hasAVX2()) 2016 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2017 return LT.first * Entry->Cost; 2018 2019 if (ST->hasAVX()) 2020 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2021 return LT.first * Entry->Cost; 2022 2023 if (ST->hasSSE42()) 2024 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2025 return LT.first * Entry->Cost; 2026 2027 if (ST->hasSSSE3()) 2028 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 2029 return LT.first * Entry->Cost; 2030 2031 if (ST->hasSSE2()) 2032 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2033 return LT.first * Entry->Cost; 2034 2035 if (ST->hasSSE1()) 2036 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2037 return LT.first * Entry->Cost; 2038 2039 if (ST->is64Bit()) 2040 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2041 return LT.first * Entry->Cost; 2042 2043 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2044 return LT.first * Entry->Cost; 2045 } 2046 2047 return BaseT::getIntrinsicInstrCost(IID, RetTy, Tys, FMF, ScalarizationCostPassed); 2048 } 2049 2050 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 2051 ArrayRef<Value *> Args, FastMathFlags FMF, 2052 unsigned VF) { 2053 static const CostTblEntry AVX512CostTbl[] = { 2054 { ISD::ROTL, MVT::v8i64, 1 }, 2055 { ISD::ROTL, MVT::v4i64, 1 }, 2056 { ISD::ROTL, MVT::v2i64, 1 }, 2057 { ISD::ROTL, MVT::v16i32, 1 }, 2058 { ISD::ROTL, MVT::v8i32, 1 }, 2059 { ISD::ROTL, MVT::v4i32, 1 }, 2060 { ISD::ROTR, MVT::v8i64, 1 }, 2061 { ISD::ROTR, MVT::v4i64, 1 }, 2062 { ISD::ROTR, MVT::v2i64, 1 }, 2063 { ISD::ROTR, MVT::v16i32, 1 }, 2064 { ISD::ROTR, MVT::v8i32, 1 }, 2065 { ISD::ROTR, MVT::v4i32, 1 } 2066 }; 2067 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 2068 static const CostTblEntry XOPCostTbl[] = { 2069 { ISD::ROTL, MVT::v4i64, 4 }, 2070 { ISD::ROTL, MVT::v8i32, 4 }, 2071 { ISD::ROTL, MVT::v16i16, 4 }, 2072 { ISD::ROTL, MVT::v32i8, 4 }, 2073 { ISD::ROTL, MVT::v2i64, 1 }, 2074 { ISD::ROTL, MVT::v4i32, 1 }, 2075 { ISD::ROTL, MVT::v8i16, 1 }, 2076 { ISD::ROTL, MVT::v16i8, 1 }, 2077 { ISD::ROTR, MVT::v4i64, 6 }, 2078 { ISD::ROTR, MVT::v8i32, 6 }, 2079 { ISD::ROTR, MVT::v16i16, 6 }, 2080 { ISD::ROTR, MVT::v32i8, 6 }, 2081 { ISD::ROTR, MVT::v2i64, 2 }, 2082 { ISD::ROTR, MVT::v4i32, 2 }, 2083 { ISD::ROTR, MVT::v8i16, 2 }, 2084 { ISD::ROTR, MVT::v16i8, 2 } 2085 }; 2086 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2087 { ISD::ROTL, MVT::i64, 1 }, 2088 { ISD::ROTR, MVT::i64, 1 }, 2089 { ISD::FSHL, MVT::i64, 4 } 2090 }; 2091 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2092 { ISD::ROTL, MVT::i32, 1 }, 2093 { ISD::ROTL, MVT::i16, 1 }, 2094 { ISD::ROTL, MVT::i8, 1 }, 2095 { ISD::ROTR, MVT::i32, 1 }, 2096 { ISD::ROTR, MVT::i16, 1 }, 2097 { ISD::ROTR, MVT::i8, 1 }, 2098 { ISD::FSHL, MVT::i32, 4 }, 2099 { ISD::FSHL, MVT::i16, 4 }, 2100 { ISD::FSHL, MVT::i8, 4 } 2101 }; 2102 2103 unsigned ISD = ISD::DELETED_NODE; 2104 switch (IID) { 2105 default: 2106 break; 2107 case Intrinsic::fshl: 2108 ISD = ISD::FSHL; 2109 if (Args[0] == Args[1]) 2110 ISD = ISD::ROTL; 2111 break; 2112 case Intrinsic::fshr: 2113 // FSHR has same costs so don't duplicate. 2114 ISD = ISD::FSHL; 2115 if (Args[0] == Args[1]) 2116 ISD = ISD::ROTR; 2117 break; 2118 } 2119 2120 if (ISD != ISD::DELETED_NODE) { 2121 // Legalize the type. 2122 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 2123 MVT MTy = LT.second; 2124 2125 // Attempt to lookup cost. 2126 if (ST->hasAVX512()) 2127 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2128 return LT.first * Entry->Cost; 2129 2130 if (ST->hasXOP()) 2131 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2132 return LT.first * Entry->Cost; 2133 2134 if (ST->is64Bit()) 2135 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2136 return LT.first * Entry->Cost; 2137 2138 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2139 return LT.first * Entry->Cost; 2140 } 2141 2142 return BaseT::getIntrinsicInstrCost(IID, RetTy, Args, FMF, VF); 2143 } 2144 2145 int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { 2146 assert(Val->isVectorTy() && "This must be a vector type"); 2147 2148 Type *ScalarType = Val->getScalarType(); 2149 2150 if (Index != -1U) { 2151 // Legalize the type. 2152 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 2153 2154 // This type is legalized to a scalar type. 2155 if (!LT.second.isVector()) 2156 return 0; 2157 2158 // The type may be split. Normalize the index to the new type. 2159 unsigned Width = LT.second.getVectorNumElements(); 2160 Index = Index % Width; 2161 2162 // Floating point scalars are already located in index #0. 2163 if (ScalarType->isFloatingPointTy() && Index == 0) 2164 return 0; 2165 } 2166 2167 // Add to the base cost if we know that the extracted element of a vector is 2168 // destined to be moved to and used in the integer register file. 2169 int RegisterFileMoveCost = 0; 2170 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 2171 RegisterFileMoveCost = 1; 2172 2173 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 2174 } 2175 2176 int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, 2177 unsigned AddressSpace, const Instruction *I) { 2178 // Handle non-power-of-two vectors such as <3 x float> 2179 if (VectorType *VTy = dyn_cast<VectorType>(Src)) { 2180 unsigned NumElem = VTy->getVectorNumElements(); 2181 2182 // Handle a few common cases: 2183 // <3 x float> 2184 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 2185 // Cost = 64 bit store + extract + 32 bit store. 2186 return 3; 2187 2188 // <3 x double> 2189 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 2190 // Cost = 128 bit store + unpack + 64 bit store. 2191 return 3; 2192 2193 // Assume that all other non-power-of-two numbers are scalarized. 2194 if (!isPowerOf2_32(NumElem)) { 2195 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment, 2196 AddressSpace); 2197 int SplitCost = getScalarizationOverhead(Src, Opcode == Instruction::Load, 2198 Opcode == Instruction::Store); 2199 return NumElem * Cost + SplitCost; 2200 } 2201 } 2202 2203 // Legalize the type. 2204 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 2205 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 2206 "Invalid Opcode"); 2207 2208 // Each load/store unit costs 1. 2209 int Cost = LT.first * 1; 2210 2211 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a 2212 // proxy for a double-pumped AVX memory interface such as on Sandybridge. 2213 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow()) 2214 Cost *= 2; 2215 2216 return Cost; 2217 } 2218 2219 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, 2220 unsigned Alignment, 2221 unsigned AddressSpace) { 2222 VectorType *SrcVTy = dyn_cast<VectorType>(SrcTy); 2223 if (!SrcVTy) 2224 // To calculate scalar take the regular cost, without mask 2225 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace); 2226 2227 unsigned NumElem = SrcVTy->getVectorNumElements(); 2228 VectorType *MaskTy = 2229 VectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 2230 if ((Opcode == Instruction::Load && !isLegalMaskedLoad(SrcVTy)) || 2231 (Opcode == Instruction::Store && !isLegalMaskedStore(SrcVTy)) || 2232 !isPowerOf2_32(NumElem)) { 2233 // Scalarization 2234 int MaskSplitCost = getScalarizationOverhead(MaskTy, false, true); 2235 int ScalarCompareCost = getCmpSelInstrCost( 2236 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr); 2237 int BranchCost = getCFInstrCost(Instruction::Br); 2238 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 2239 2240 int ValueSplitCost = getScalarizationOverhead( 2241 SrcVTy, Opcode == Instruction::Load, Opcode == Instruction::Store); 2242 int MemopCost = 2243 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2244 Alignment, AddressSpace); 2245 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 2246 } 2247 2248 // Legalize the type. 2249 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 2250 auto VT = TLI->getValueType(DL, SrcVTy); 2251 int Cost = 0; 2252 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 2253 LT.second.getVectorNumElements() == NumElem) 2254 // Promotion requires expand/truncate for data and a shuffle for mask. 2255 Cost += getShuffleCost(TTI::SK_Select, SrcVTy, 0, nullptr) + 2256 getShuffleCost(TTI::SK_Select, MaskTy, 0, nullptr); 2257 2258 else if (LT.second.getVectorNumElements() > NumElem) { 2259 VectorType *NewMaskTy = VectorType::get(MaskTy->getVectorElementType(), 2260 LT.second.getVectorNumElements()); 2261 // Expanding requires fill mask with zeroes 2262 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, 0, MaskTy); 2263 } 2264 if (!ST->hasAVX512()) 2265 return Cost + LT.first*4; // Each maskmov costs 4 2266 2267 // AVX-512 masked load/store is cheapper 2268 return Cost+LT.first; 2269 } 2270 2271 int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE, 2272 const SCEV *Ptr) { 2273 // Address computations in vectorized code with non-consecutive addresses will 2274 // likely result in more instructions compared to scalar code where the 2275 // computation can more often be merged into the index mode. The resulting 2276 // extra micro-ops can significantly decrease throughput. 2277 unsigned NumVectorInstToHideOverhead = 10; 2278 2279 // Cost modeling of Strided Access Computation is hidden by the indexing 2280 // modes of X86 regardless of the stride value. We dont believe that there 2281 // is a difference between constant strided access in gerenal and constant 2282 // strided value which is less than or equal to 64. 2283 // Even in the case of (loop invariant) stride whose value is not known at 2284 // compile time, the address computation will not incur more than one extra 2285 // ADD instruction. 2286 if (Ty->isVectorTy() && SE) { 2287 if (!BaseT::isStridedAccess(Ptr)) 2288 return NumVectorInstToHideOverhead; 2289 if (!BaseT::getConstantStrideStep(SE, Ptr)) 2290 return 1; 2291 } 2292 2293 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 2294 } 2295 2296 int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, Type *ValTy, 2297 bool IsPairwise) { 2298 2299 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2300 2301 MVT MTy = LT.second; 2302 2303 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2304 assert(ISD && "Invalid opcode"); 2305 2306 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 2307 // and make it as the cost. 2308 2309 static const CostTblEntry SSE42CostTblPairWise[] = { 2310 { ISD::FADD, MVT::v2f64, 2 }, 2311 { ISD::FADD, MVT::v4f32, 4 }, 2312 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 2313 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5". 2314 { ISD::ADD, MVT::v8i16, 5 }, 2315 }; 2316 2317 static const CostTblEntry AVX1CostTblPairWise[] = { 2318 { ISD::FADD, MVT::v4f32, 4 }, 2319 { ISD::FADD, MVT::v4f64, 5 }, 2320 { ISD::FADD, MVT::v8f32, 7 }, 2321 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 2322 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5". 2323 { ISD::ADD, MVT::v4i64, 5 }, // The data reported by the IACA tool is "4.8". 2324 { ISD::ADD, MVT::v8i16, 5 }, 2325 { ISD::ADD, MVT::v8i32, 5 }, 2326 }; 2327 2328 static const CostTblEntry SSE42CostTblNoPairWise[] = { 2329 { ISD::FADD, MVT::v2f64, 2 }, 2330 { ISD::FADD, MVT::v4f32, 4 }, 2331 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 2332 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 2333 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 2334 }; 2335 2336 static const CostTblEntry AVX1CostTblNoPairWise[] = { 2337 { ISD::FADD, MVT::v4f32, 3 }, 2338 { ISD::FADD, MVT::v4f64, 3 }, 2339 { ISD::FADD, MVT::v8f32, 4 }, 2340 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 2341 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "2.8". 2342 { ISD::ADD, MVT::v4i64, 3 }, 2343 { ISD::ADD, MVT::v8i16, 4 }, 2344 { ISD::ADD, MVT::v8i32, 5 }, 2345 }; 2346 2347 if (IsPairwise) { 2348 if (ST->hasAVX()) 2349 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy)) 2350 return LT.first * Entry->Cost; 2351 2352 if (ST->hasSSE42()) 2353 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy)) 2354 return LT.first * Entry->Cost; 2355 } else { 2356 if (ST->hasAVX()) 2357 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 2358 return LT.first * Entry->Cost; 2359 2360 if (ST->hasSSE42()) 2361 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy)) 2362 return LT.first * Entry->Cost; 2363 } 2364 2365 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise); 2366 } 2367 2368 int X86TTIImpl::getMinMaxReductionCost(Type *ValTy, Type *CondTy, 2369 bool IsPairwise, bool IsUnsigned) { 2370 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2371 2372 MVT MTy = LT.second; 2373 2374 int ISD; 2375 if (ValTy->isIntOrIntVectorTy()) { 2376 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 2377 } else { 2378 assert(ValTy->isFPOrFPVectorTy() && 2379 "Expected float point or integer vector type."); 2380 ISD = ISD::FMINNUM; 2381 } 2382 2383 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 2384 // and make it as the cost. 2385 2386 static const CostTblEntry SSE42CostTblPairWise[] = { 2387 {ISD::FMINNUM, MVT::v2f64, 3}, 2388 {ISD::FMINNUM, MVT::v4f32, 2}, 2389 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8" 2390 {ISD::UMIN, MVT::v2i64, 8}, // The data reported by the IACA is "8.6" 2391 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5" 2392 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8" 2393 {ISD::SMIN, MVT::v8i16, 2}, 2394 {ISD::UMIN, MVT::v8i16, 2}, 2395 }; 2396 2397 static const CostTblEntry AVX1CostTblPairWise[] = { 2398 {ISD::FMINNUM, MVT::v4f32, 1}, 2399 {ISD::FMINNUM, MVT::v4f64, 1}, 2400 {ISD::FMINNUM, MVT::v8f32, 2}, 2401 {ISD::SMIN, MVT::v2i64, 3}, 2402 {ISD::UMIN, MVT::v2i64, 3}, 2403 {ISD::SMIN, MVT::v4i32, 1}, 2404 {ISD::UMIN, MVT::v4i32, 1}, 2405 {ISD::SMIN, MVT::v8i16, 1}, 2406 {ISD::UMIN, MVT::v8i16, 1}, 2407 {ISD::SMIN, MVT::v8i32, 3}, 2408 {ISD::UMIN, MVT::v8i32, 3}, 2409 }; 2410 2411 static const CostTblEntry AVX2CostTblPairWise[] = { 2412 {ISD::SMIN, MVT::v4i64, 2}, 2413 {ISD::UMIN, MVT::v4i64, 2}, 2414 {ISD::SMIN, MVT::v8i32, 1}, 2415 {ISD::UMIN, MVT::v8i32, 1}, 2416 {ISD::SMIN, MVT::v16i16, 1}, 2417 {ISD::UMIN, MVT::v16i16, 1}, 2418 {ISD::SMIN, MVT::v32i8, 2}, 2419 {ISD::UMIN, MVT::v32i8, 2}, 2420 }; 2421 2422 static const CostTblEntry AVX512CostTblPairWise[] = { 2423 {ISD::FMINNUM, MVT::v8f64, 1}, 2424 {ISD::FMINNUM, MVT::v16f32, 2}, 2425 {ISD::SMIN, MVT::v8i64, 2}, 2426 {ISD::UMIN, MVT::v8i64, 2}, 2427 {ISD::SMIN, MVT::v16i32, 1}, 2428 {ISD::UMIN, MVT::v16i32, 1}, 2429 }; 2430 2431 static const CostTblEntry SSE42CostTblNoPairWise[] = { 2432 {ISD::FMINNUM, MVT::v2f64, 3}, 2433 {ISD::FMINNUM, MVT::v4f32, 3}, 2434 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8" 2435 {ISD::UMIN, MVT::v2i64, 9}, // The data reported by the IACA is "8.6" 2436 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5" 2437 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8" 2438 {ISD::SMIN, MVT::v8i16, 1}, // The data reported by the IACA is "1.5" 2439 {ISD::UMIN, MVT::v8i16, 2}, // The data reported by the IACA is "1.8" 2440 }; 2441 2442 static const CostTblEntry AVX1CostTblNoPairWise[] = { 2443 {ISD::FMINNUM, MVT::v4f32, 1}, 2444 {ISD::FMINNUM, MVT::v4f64, 1}, 2445 {ISD::FMINNUM, MVT::v8f32, 1}, 2446 {ISD::SMIN, MVT::v2i64, 3}, 2447 {ISD::UMIN, MVT::v2i64, 3}, 2448 {ISD::SMIN, MVT::v4i32, 1}, 2449 {ISD::UMIN, MVT::v4i32, 1}, 2450 {ISD::SMIN, MVT::v8i16, 1}, 2451 {ISD::UMIN, MVT::v8i16, 1}, 2452 {ISD::SMIN, MVT::v8i32, 2}, 2453 {ISD::UMIN, MVT::v8i32, 2}, 2454 }; 2455 2456 static const CostTblEntry AVX2CostTblNoPairWise[] = { 2457 {ISD::SMIN, MVT::v4i64, 1}, 2458 {ISD::UMIN, MVT::v4i64, 1}, 2459 {ISD::SMIN, MVT::v8i32, 1}, 2460 {ISD::UMIN, MVT::v8i32, 1}, 2461 {ISD::SMIN, MVT::v16i16, 1}, 2462 {ISD::UMIN, MVT::v16i16, 1}, 2463 {ISD::SMIN, MVT::v32i8, 1}, 2464 {ISD::UMIN, MVT::v32i8, 1}, 2465 }; 2466 2467 static const CostTblEntry AVX512CostTblNoPairWise[] = { 2468 {ISD::FMINNUM, MVT::v8f64, 1}, 2469 {ISD::FMINNUM, MVT::v16f32, 2}, 2470 {ISD::SMIN, MVT::v8i64, 1}, 2471 {ISD::UMIN, MVT::v8i64, 1}, 2472 {ISD::SMIN, MVT::v16i32, 1}, 2473 {ISD::UMIN, MVT::v16i32, 1}, 2474 }; 2475 2476 if (IsPairwise) { 2477 if (ST->hasAVX512()) 2478 if (const auto *Entry = CostTableLookup(AVX512CostTblPairWise, ISD, MTy)) 2479 return LT.first * Entry->Cost; 2480 2481 if (ST->hasAVX2()) 2482 if (const auto *Entry = CostTableLookup(AVX2CostTblPairWise, ISD, MTy)) 2483 return LT.first * Entry->Cost; 2484 2485 if (ST->hasAVX()) 2486 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy)) 2487 return LT.first * Entry->Cost; 2488 2489 if (ST->hasSSE42()) 2490 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy)) 2491 return LT.first * Entry->Cost; 2492 } else { 2493 if (ST->hasAVX512()) 2494 if (const auto *Entry = 2495 CostTableLookup(AVX512CostTblNoPairWise, ISD, MTy)) 2496 return LT.first * Entry->Cost; 2497 2498 if (ST->hasAVX2()) 2499 if (const auto *Entry = CostTableLookup(AVX2CostTblNoPairWise, ISD, MTy)) 2500 return LT.first * Entry->Cost; 2501 2502 if (ST->hasAVX()) 2503 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 2504 return LT.first * Entry->Cost; 2505 2506 if (ST->hasSSE42()) 2507 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy)) 2508 return LT.first * Entry->Cost; 2509 } 2510 2511 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned); 2512 } 2513 2514 /// Calculate the cost of materializing a 64-bit value. This helper 2515 /// method might only calculate a fraction of a larger immediate. Therefore it 2516 /// is valid to return a cost of ZERO. 2517 int X86TTIImpl::getIntImmCost(int64_t Val) { 2518 if (Val == 0) 2519 return TTI::TCC_Free; 2520 2521 if (isInt<32>(Val)) 2522 return TTI::TCC_Basic; 2523 2524 return 2 * TTI::TCC_Basic; 2525 } 2526 2527 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { 2528 assert(Ty->isIntegerTy()); 2529 2530 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 2531 if (BitSize == 0) 2532 return ~0U; 2533 2534 // Never hoist constants larger than 128bit, because this might lead to 2535 // incorrect code generation or assertions in codegen. 2536 // Fixme: Create a cost model for types larger than i128 once the codegen 2537 // issues have been fixed. 2538 if (BitSize > 128) 2539 return TTI::TCC_Free; 2540 2541 if (Imm == 0) 2542 return TTI::TCC_Free; 2543 2544 // Sign-extend all constants to a multiple of 64-bit. 2545 APInt ImmVal = Imm; 2546 if (BitSize % 64 != 0) 2547 ImmVal = Imm.sext(alignTo(BitSize, 64)); 2548 2549 // Split the constant into 64-bit chunks and calculate the cost for each 2550 // chunk. 2551 int Cost = 0; 2552 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 2553 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 2554 int64_t Val = Tmp.getSExtValue(); 2555 Cost += getIntImmCost(Val); 2556 } 2557 // We need at least one instruction to materialize the constant. 2558 return std::max(1, Cost); 2559 } 2560 2561 int X86TTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, 2562 Type *Ty) { 2563 assert(Ty->isIntegerTy()); 2564 2565 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 2566 // There is no cost model for constants with a bit size of 0. Return TCC_Free 2567 // here, so that constant hoisting will ignore this constant. 2568 if (BitSize == 0) 2569 return TTI::TCC_Free; 2570 2571 unsigned ImmIdx = ~0U; 2572 switch (Opcode) { 2573 default: 2574 return TTI::TCC_Free; 2575 case Instruction::GetElementPtr: 2576 // Always hoist the base address of a GetElementPtr. This prevents the 2577 // creation of new constants for every base constant that gets constant 2578 // folded with the offset. 2579 if (Idx == 0) 2580 return 2 * TTI::TCC_Basic; 2581 return TTI::TCC_Free; 2582 case Instruction::Store: 2583 ImmIdx = 0; 2584 break; 2585 case Instruction::ICmp: 2586 // This is an imperfect hack to prevent constant hoisting of 2587 // compares that might be trying to check if a 64-bit value fits in 2588 // 32-bits. The backend can optimize these cases using a right shift by 32. 2589 // Ideally we would check the compare predicate here. There also other 2590 // similar immediates the backend can use shifts for. 2591 if (Idx == 1 && Imm.getBitWidth() == 64) { 2592 uint64_t ImmVal = Imm.getZExtValue(); 2593 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 2594 return TTI::TCC_Free; 2595 } 2596 ImmIdx = 1; 2597 break; 2598 case Instruction::And: 2599 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 2600 // by using a 32-bit operation with implicit zero extension. Detect such 2601 // immediates here as the normal path expects bit 31 to be sign extended. 2602 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 2603 return TTI::TCC_Free; 2604 ImmIdx = 1; 2605 break; 2606 case Instruction::Add: 2607 case Instruction::Sub: 2608 // For add/sub, we can use the opposite instruction for INT32_MIN. 2609 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 2610 return TTI::TCC_Free; 2611 ImmIdx = 1; 2612 break; 2613 case Instruction::UDiv: 2614 case Instruction::SDiv: 2615 case Instruction::URem: 2616 case Instruction::SRem: 2617 // Division by constant is typically expanded later into a different 2618 // instruction sequence. This completely changes the constants. 2619 // Report them as "free" to stop ConstantHoist from marking them as opaque. 2620 return TTI::TCC_Free; 2621 case Instruction::Mul: 2622 case Instruction::Or: 2623 case Instruction::Xor: 2624 ImmIdx = 1; 2625 break; 2626 // Always return TCC_Free for the shift value of a shift instruction. 2627 case Instruction::Shl: 2628 case Instruction::LShr: 2629 case Instruction::AShr: 2630 if (Idx == 1) 2631 return TTI::TCC_Free; 2632 break; 2633 case Instruction::Trunc: 2634 case Instruction::ZExt: 2635 case Instruction::SExt: 2636 case Instruction::IntToPtr: 2637 case Instruction::PtrToInt: 2638 case Instruction::BitCast: 2639 case Instruction::PHI: 2640 case Instruction::Call: 2641 case Instruction::Select: 2642 case Instruction::Ret: 2643 case Instruction::Load: 2644 break; 2645 } 2646 2647 if (Idx == ImmIdx) { 2648 int NumConstants = divideCeil(BitSize, 64); 2649 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty); 2650 return (Cost <= NumConstants * TTI::TCC_Basic) 2651 ? static_cast<int>(TTI::TCC_Free) 2652 : Cost; 2653 } 2654 2655 return X86TTIImpl::getIntImmCost(Imm, Ty); 2656 } 2657 2658 int X86TTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, 2659 Type *Ty) { 2660 assert(Ty->isIntegerTy()); 2661 2662 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 2663 // There is no cost model for constants with a bit size of 0. Return TCC_Free 2664 // here, so that constant hoisting will ignore this constant. 2665 if (BitSize == 0) 2666 return TTI::TCC_Free; 2667 2668 switch (IID) { 2669 default: 2670 return TTI::TCC_Free; 2671 case Intrinsic::sadd_with_overflow: 2672 case Intrinsic::uadd_with_overflow: 2673 case Intrinsic::ssub_with_overflow: 2674 case Intrinsic::usub_with_overflow: 2675 case Intrinsic::smul_with_overflow: 2676 case Intrinsic::umul_with_overflow: 2677 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 2678 return TTI::TCC_Free; 2679 break; 2680 case Intrinsic::experimental_stackmap: 2681 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 2682 return TTI::TCC_Free; 2683 break; 2684 case Intrinsic::experimental_patchpoint_void: 2685 case Intrinsic::experimental_patchpoint_i64: 2686 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 2687 return TTI::TCC_Free; 2688 break; 2689 } 2690 return X86TTIImpl::getIntImmCost(Imm, Ty); 2691 } 2692 2693 unsigned X86TTIImpl::getUserCost(const User *U, 2694 ArrayRef<const Value *> Operands) { 2695 if (isa<StoreInst>(U)) { 2696 Value *Ptr = U->getOperand(1); 2697 // Store instruction with index and scale costs 2 Uops. 2698 // Check the preceding GEP to identify non-const indices. 2699 if (auto GEP = dyn_cast<GetElementPtrInst>(Ptr)) { 2700 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 2701 return TTI::TCC_Basic * 2; 2702 } 2703 return TTI::TCC_Basic; 2704 } 2705 return BaseT::getUserCost(U, Operands); 2706 } 2707 2708 // Return an average cost of Gather / Scatter instruction, maybe improved later 2709 int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, Value *Ptr, 2710 unsigned Alignment, unsigned AddressSpace) { 2711 2712 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 2713 unsigned VF = SrcVTy->getVectorNumElements(); 2714 2715 // Try to reduce index size from 64 bit (default for GEP) 2716 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 2717 // operation will use 16 x 64 indices which do not fit in a zmm and needs 2718 // to split. Also check that the base pointer is the same for all lanes, 2719 // and that there's at most one variable index. 2720 auto getIndexSizeInBits = [](Value *Ptr, const DataLayout& DL) { 2721 unsigned IndexSize = DL.getPointerSizeInBits(); 2722 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 2723 if (IndexSize < 64 || !GEP) 2724 return IndexSize; 2725 2726 unsigned NumOfVarIndices = 0; 2727 Value *Ptrs = GEP->getPointerOperand(); 2728 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 2729 return IndexSize; 2730 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 2731 if (isa<Constant>(GEP->getOperand(i))) 2732 continue; 2733 Type *IndxTy = GEP->getOperand(i)->getType(); 2734 if (IndxTy->isVectorTy()) 2735 IndxTy = IndxTy->getVectorElementType(); 2736 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 2737 !isa<SExtInst>(GEP->getOperand(i))) || 2738 ++NumOfVarIndices > 1) 2739 return IndexSize; // 64 2740 } 2741 return (unsigned)32; 2742 }; 2743 2744 2745 // Trying to reduce IndexSize to 32 bits for vector 16. 2746 // By default the IndexSize is equal to pointer size. 2747 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 2748 ? getIndexSizeInBits(Ptr, DL) 2749 : DL.getPointerSizeInBits(); 2750 2751 Type *IndexVTy = VectorType::get(IntegerType::get(SrcVTy->getContext(), 2752 IndexSize), VF); 2753 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy); 2754 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy); 2755 int SplitFactor = std::max(IdxsLT.first, SrcLT.first); 2756 if (SplitFactor > 1) { 2757 // Handle splitting of vector of pointers 2758 Type *SplitSrcTy = VectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 2759 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 2760 AddressSpace); 2761 } 2762 2763 // The gather / scatter cost is given by Intel architects. It is a rough 2764 // number since we are looking at one instruction in a time. 2765 const int GSOverhead = (Opcode == Instruction::Load) 2766 ? ST->getGatherOverhead() 2767 : ST->getScatterOverhead(); 2768 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2769 Alignment, AddressSpace); 2770 } 2771 2772 /// Return the cost of full scalarization of gather / scatter operation. 2773 /// 2774 /// Opcode - Load or Store instruction. 2775 /// SrcVTy - The type of the data vector that should be gathered or scattered. 2776 /// VariableMask - The mask is non-constant at compile time. 2777 /// Alignment - Alignment for one element. 2778 /// AddressSpace - pointer[s] address space. 2779 /// 2780 int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 2781 bool VariableMask, unsigned Alignment, 2782 unsigned AddressSpace) { 2783 unsigned VF = SrcVTy->getVectorNumElements(); 2784 2785 int MaskUnpackCost = 0; 2786 if (VariableMask) { 2787 VectorType *MaskTy = 2788 VectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 2789 MaskUnpackCost = getScalarizationOverhead(MaskTy, false, true); 2790 int ScalarCompareCost = 2791 getCmpSelInstrCost(Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), 2792 nullptr); 2793 int BranchCost = getCFInstrCost(Instruction::Br); 2794 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 2795 } 2796 2797 // The cost of the scalar loads/stores. 2798 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2799 Alignment, AddressSpace); 2800 2801 int InsertExtractCost = 0; 2802 if (Opcode == Instruction::Load) 2803 for (unsigned i = 0; i < VF; ++i) 2804 // Add the cost of inserting each scalar load into the vector 2805 InsertExtractCost += 2806 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 2807 else 2808 for (unsigned i = 0; i < VF; ++i) 2809 // Add the cost of extracting each element out of the data vector 2810 InsertExtractCost += 2811 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 2812 2813 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 2814 } 2815 2816 /// Calculate the cost of Gather / Scatter operation 2817 int X86TTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *SrcVTy, 2818 Value *Ptr, bool VariableMask, 2819 unsigned Alignment) { 2820 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 2821 unsigned VF = SrcVTy->getVectorNumElements(); 2822 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 2823 if (!PtrTy && Ptr->getType()->isVectorTy()) 2824 PtrTy = dyn_cast<PointerType>(Ptr->getType()->getVectorElementType()); 2825 assert(PtrTy && "Unexpected type for Ptr argument"); 2826 unsigned AddressSpace = PtrTy->getAddressSpace(); 2827 2828 bool Scalarize = false; 2829 if ((Opcode == Instruction::Load && !isLegalMaskedGather(SrcVTy)) || 2830 (Opcode == Instruction::Store && !isLegalMaskedScatter(SrcVTy))) 2831 Scalarize = true; 2832 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 2833 // Vector-4 of gather/scatter instruction does not exist on KNL. 2834 // We can extend it to 8 elements, but zeroing upper bits of 2835 // the mask vector will add more instructions. Right now we give the scalar 2836 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 2837 // is better in the VariableMask case. 2838 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 2839 Scalarize = true; 2840 2841 if (Scalarize) 2842 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 2843 AddressSpace); 2844 2845 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 2846 } 2847 2848 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 2849 TargetTransformInfo::LSRCost &C2) { 2850 // X86 specific here are "instruction number 1st priority". 2851 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 2852 C1.NumIVMuls, C1.NumBaseAdds, 2853 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 2854 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 2855 C2.NumIVMuls, C2.NumBaseAdds, 2856 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 2857 } 2858 2859 bool X86TTIImpl::canMacroFuseCmp() { 2860 return ST->hasMacroFusion(); 2861 } 2862 2863 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy) { 2864 // The backend can't handle a single element vector. 2865 if (isa<VectorType>(DataTy) && DataTy->getVectorNumElements() == 1) 2866 return false; 2867 Type *ScalarTy = DataTy->getScalarType(); 2868 int DataWidth = isa<PointerType>(ScalarTy) ? 2869 DL.getPointerSizeInBits() : ScalarTy->getPrimitiveSizeInBits(); 2870 2871 return ((DataWidth == 32 || DataWidth == 64) && ST->hasAVX()) || 2872 ((DataWidth == 8 || DataWidth == 16) && ST->hasBWI()); 2873 } 2874 2875 bool X86TTIImpl::isLegalMaskedStore(Type *DataType) { 2876 return isLegalMaskedLoad(DataType); 2877 } 2878 2879 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy) { 2880 // This function is called now in two cases: from the Loop Vectorizer 2881 // and from the Scalarizer. 2882 // When the Loop Vectorizer asks about legality of the feature, 2883 // the vectorization factor is not calculated yet. The Loop Vectorizer 2884 // sends a scalar type and the decision is based on the width of the 2885 // scalar element. 2886 // Later on, the cost model will estimate usage this intrinsic based on 2887 // the vector type. 2888 // The Scalarizer asks again about legality. It sends a vector type. 2889 // In this case we can reject non-power-of-2 vectors. 2890 // We also reject single element vectors as the type legalizer can't 2891 // scalarize it. 2892 if (isa<VectorType>(DataTy)) { 2893 unsigned NumElts = DataTy->getVectorNumElements(); 2894 if (NumElts == 1 || !isPowerOf2_32(NumElts)) 2895 return false; 2896 } 2897 Type *ScalarTy = DataTy->getScalarType(); 2898 int DataWidth = isa<PointerType>(ScalarTy) ? 2899 DL.getPointerSizeInBits() : ScalarTy->getPrimitiveSizeInBits(); 2900 2901 // Some CPUs have better gather performance than others. 2902 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 2903 // enable gather with a -march. 2904 return (DataWidth == 32 || DataWidth == 64) && 2905 (ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2())); 2906 } 2907 2908 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType) { 2909 // AVX2 doesn't support scatter 2910 if (!ST->hasAVX512()) 2911 return false; 2912 return isLegalMaskedGather(DataType); 2913 } 2914 2915 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 2916 EVT VT = TLI->getValueType(DL, DataType); 2917 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 2918 } 2919 2920 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 2921 return false; 2922 } 2923 2924 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 2925 const Function *Callee) const { 2926 const TargetMachine &TM = getTLI()->getTargetMachine(); 2927 2928 // Work this as a subsetting of subtarget features. 2929 const FeatureBitset &CallerBits = 2930 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 2931 const FeatureBitset &CalleeBits = 2932 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 2933 2934 // FIXME: This is likely too limiting as it will include subtarget features 2935 // that we might not care about for inlining, but it is conservatively 2936 // correct. 2937 return (CallerBits & CalleeBits) == CalleeBits; 2938 } 2939 2940 const X86TTIImpl::TTI::MemCmpExpansionOptions * 2941 X86TTIImpl::enableMemCmpExpansion(bool IsZeroCmp) const { 2942 // Only enable vector loads for equality comparison. 2943 // Right now the vector version is not as fast, see #33329. 2944 static const auto ThreeWayOptions = [this]() { 2945 TTI::MemCmpExpansionOptions Options; 2946 if (ST->is64Bit()) { 2947 Options.LoadSizes.push_back(8); 2948 } 2949 Options.LoadSizes.push_back(4); 2950 Options.LoadSizes.push_back(2); 2951 Options.LoadSizes.push_back(1); 2952 return Options; 2953 }(); 2954 static const auto EqZeroOptions = [this]() { 2955 TTI::MemCmpExpansionOptions Options; 2956 // TODO: enable AVX512 when the DAG is ready. 2957 // if (ST->hasAVX512()) Options.LoadSizes.push_back(64); 2958 if (ST->hasAVX2()) Options.LoadSizes.push_back(32); 2959 if (ST->hasSSE2()) Options.LoadSizes.push_back(16); 2960 if (ST->is64Bit()) { 2961 Options.LoadSizes.push_back(8); 2962 } 2963 Options.LoadSizes.push_back(4); 2964 Options.LoadSizes.push_back(2); 2965 Options.LoadSizes.push_back(1); 2966 // All GPR and vector loads can be unaligned. SIMD compare requires integer 2967 // vectors (SSE2/AVX2). 2968 Options.AllowOverlappingLoads = true; 2969 return Options; 2970 }(); 2971 return IsZeroCmp ? &EqZeroOptions : &ThreeWayOptions; 2972 } 2973 2974 bool X86TTIImpl::enableInterleavedAccessVectorization() { 2975 // TODO: We expect this to be beneficial regardless of arch, 2976 // but there are currently some unexplained performance artifacts on Atom. 2977 // As a temporary solution, disable on Atom. 2978 return !(ST->isAtom()); 2979 } 2980 2981 // Get estimation for interleaved load/store operations for AVX2. 2982 // \p Factor is the interleaved-access factor (stride) - number of 2983 // (interleaved) elements in the group. 2984 // \p Indices contains the indices for a strided load: when the 2985 // interleaved load has gaps they indicate which elements are used. 2986 // If Indices is empty (or if the number of indices is equal to the size 2987 // of the interleaved-access as given in \p Factor) the access has no gaps. 2988 // 2989 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 2990 // computing the cost using a generic formula as a function of generic 2991 // shuffles. We therefore use a lookup table instead, filled according to 2992 // the instruction sequences that codegen currently generates. 2993 int X86TTIImpl::getInterleavedMemoryOpCostAVX2(unsigned Opcode, Type *VecTy, 2994 unsigned Factor, 2995 ArrayRef<unsigned> Indices, 2996 unsigned Alignment, 2997 unsigned AddressSpace, 2998 bool UseMaskForCond, 2999 bool UseMaskForGaps) { 3000 3001 if (UseMaskForCond || UseMaskForGaps) 3002 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3003 Alignment, AddressSpace, 3004 UseMaskForCond, UseMaskForGaps); 3005 3006 // We currently Support only fully-interleaved groups, with no gaps. 3007 // TODO: Support also strided loads (interleaved-groups with gaps). 3008 if (Indices.size() && Indices.size() != Factor) 3009 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3010 Alignment, AddressSpace); 3011 3012 // VecTy for interleave memop is <VF*Factor x Elt>. 3013 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 3014 // VecTy = <12 x i32>. 3015 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 3016 3017 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 3018 // the VF=2, while v2i128 is an unsupported MVT vector type 3019 // (see MachineValueType.h::getVectorVT()). 3020 if (!LegalVT.isVector()) 3021 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3022 Alignment, AddressSpace); 3023 3024 unsigned VF = VecTy->getVectorNumElements() / Factor; 3025 Type *ScalarTy = VecTy->getVectorElementType(); 3026 3027 // Calculate the number of memory operations (NumOfMemOps), required 3028 // for load/store the VecTy. 3029 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 3030 unsigned LegalVTSize = LegalVT.getStoreSize(); 3031 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 3032 3033 // Get the cost of one memory operation. 3034 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(), 3035 LegalVT.getVectorNumElements()); 3036 unsigned MemOpCost = 3037 getMemoryOpCost(Opcode, SingleMemOpTy, Alignment, AddressSpace); 3038 3039 VectorType *VT = VectorType::get(ScalarTy, VF); 3040 EVT ETy = TLI->getValueType(DL, VT); 3041 if (!ETy.isSimple()) 3042 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3043 Alignment, AddressSpace); 3044 3045 // TODO: Complete for other data-types and strides. 3046 // Each combination of Stride, ElementTy and VF results in a different 3047 // sequence; The cost tables are therefore accessed with: 3048 // Factor (stride) and VectorType=VFxElemType. 3049 // The Cost accounts only for the shuffle sequence; 3050 // The cost of the loads/stores is accounted for separately. 3051 // 3052 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 3053 { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64 3054 { 2, MVT::v4f64, 6 }, //(load 8f64 and) deinterleave into 2 x 4f64 3055 3056 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8 3057 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8 3058 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8 3059 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8 3060 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8 3061 { 3, MVT::v8f32, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32 3062 3063 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8 3064 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8 3065 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8 3066 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8 3067 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8 3068 3069 { 8, MVT::v8f32, 40 } //(load 64f32 and)deinterleave into 8 x 8f32 3070 }; 3071 3072 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 3073 { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store) 3074 { 2, MVT::v4f64, 6 }, //interleave into 2 x 4f64 into 8f64 (and store) 3075 3076 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store) 3077 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store) 3078 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store) 3079 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store) 3080 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store) 3081 3082 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store) 3083 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store) 3084 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store) 3085 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store) 3086 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store) 3087 }; 3088 3089 if (Opcode == Instruction::Load) { 3090 if (const auto *Entry = 3091 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 3092 return NumOfMemOps * MemOpCost + Entry->Cost; 3093 } else { 3094 assert(Opcode == Instruction::Store && 3095 "Expected Store Instruction at this point"); 3096 if (const auto *Entry = 3097 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 3098 return NumOfMemOps * MemOpCost + Entry->Cost; 3099 } 3100 3101 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3102 Alignment, AddressSpace); 3103 } 3104 3105 // Get estimation for interleaved load/store operations and strided load. 3106 // \p Indices contains indices for strided load. 3107 // \p Factor - the factor of interleaving. 3108 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 3109 int X86TTIImpl::getInterleavedMemoryOpCostAVX512(unsigned Opcode, Type *VecTy, 3110 unsigned Factor, 3111 ArrayRef<unsigned> Indices, 3112 unsigned Alignment, 3113 unsigned AddressSpace, 3114 bool UseMaskForCond, 3115 bool UseMaskForGaps) { 3116 3117 if (UseMaskForCond || UseMaskForGaps) 3118 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3119 Alignment, AddressSpace, 3120 UseMaskForCond, UseMaskForGaps); 3121 3122 // VecTy for interleave memop is <VF*Factor x Elt>. 3123 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 3124 // VecTy = <12 x i32>. 3125 3126 // Calculate the number of memory operations (NumOfMemOps), required 3127 // for load/store the VecTy. 3128 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 3129 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 3130 unsigned LegalVTSize = LegalVT.getStoreSize(); 3131 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 3132 3133 // Get the cost of one memory operation. 3134 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(), 3135 LegalVT.getVectorNumElements()); 3136 unsigned MemOpCost = 3137 getMemoryOpCost(Opcode, SingleMemOpTy, Alignment, AddressSpace); 3138 3139 unsigned VF = VecTy->getVectorNumElements() / Factor; 3140 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 3141 3142 if (Opcode == Instruction::Load) { 3143 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 3144 // contain the cost of the optimized shuffle sequence that the 3145 // X86InterleavedAccess pass will generate. 3146 // The cost of loads and stores are computed separately from the table. 3147 3148 // X86InterleavedAccess support only the following interleaved-access group. 3149 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 3150 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 3151 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 3152 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 3153 }; 3154 3155 if (const auto *Entry = 3156 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 3157 return NumOfMemOps * MemOpCost + Entry->Cost; 3158 //If an entry does not exist, fallback to the default implementation. 3159 3160 // Kind of shuffle depends on number of loaded values. 3161 // If we load the entire data in one register, we can use a 1-src shuffle. 3162 // Otherwise, we'll merge 2 sources in each operation. 3163 TTI::ShuffleKind ShuffleKind = 3164 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 3165 3166 unsigned ShuffleCost = 3167 getShuffleCost(ShuffleKind, SingleMemOpTy, 0, nullptr); 3168 3169 unsigned NumOfLoadsInInterleaveGrp = 3170 Indices.size() ? Indices.size() : Factor; 3171 Type *ResultTy = VectorType::get(VecTy->getVectorElementType(), 3172 VecTy->getVectorNumElements() / Factor); 3173 unsigned NumOfResults = 3174 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 3175 NumOfLoadsInInterleaveGrp; 3176 3177 // About a half of the loads may be folded in shuffles when we have only 3178 // one result. If we have more than one result, we do not fold loads at all. 3179 unsigned NumOfUnfoldedLoads = 3180 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 3181 3182 // Get a number of shuffle operations per result. 3183 unsigned NumOfShufflesPerResult = 3184 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 3185 3186 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 3187 // When we have more than one destination, we need additional instructions 3188 // to keep sources. 3189 unsigned NumOfMoves = 0; 3190 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 3191 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 3192 3193 int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 3194 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 3195 3196 return Cost; 3197 } 3198 3199 // Store. 3200 assert(Opcode == Instruction::Store && 3201 "Expected Store Instruction at this point"); 3202 // X86InterleavedAccess support only the following interleaved-access group. 3203 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 3204 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 3205 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 3206 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 3207 3208 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 3209 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 3210 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 3211 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 3212 }; 3213 3214 if (const auto *Entry = 3215 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 3216 return NumOfMemOps * MemOpCost + Entry->Cost; 3217 //If an entry does not exist, fallback to the default implementation. 3218 3219 // There is no strided stores meanwhile. And store can't be folded in 3220 // shuffle. 3221 unsigned NumOfSources = Factor; // The number of values to be merged. 3222 unsigned ShuffleCost = 3223 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, 0, nullptr); 3224 unsigned NumOfShufflesPerStore = NumOfSources - 1; 3225 3226 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 3227 // We need additional instructions to keep sources. 3228 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 3229 int Cost = NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 3230 NumOfMoves; 3231 return Cost; 3232 } 3233 3234 int X86TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, 3235 unsigned Factor, 3236 ArrayRef<unsigned> Indices, 3237 unsigned Alignment, 3238 unsigned AddressSpace, 3239 bool UseMaskForCond, 3240 bool UseMaskForGaps) { 3241 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 3242 Type *EltTy = VecTy->getVectorElementType(); 3243 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 3244 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 3245 return true; 3246 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 3247 return HasBW; 3248 return false; 3249 }; 3250 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 3251 return getInterleavedMemoryOpCostAVX512(Opcode, VecTy, Factor, Indices, 3252 Alignment, AddressSpace, 3253 UseMaskForCond, UseMaskForGaps); 3254 if (ST->hasAVX2()) 3255 return getInterleavedMemoryOpCostAVX2(Opcode, VecTy, Factor, Indices, 3256 Alignment, AddressSpace, 3257 UseMaskForCond, UseMaskForGaps); 3258 3259 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3260 Alignment, AddressSpace, 3261 UseMaskForCond, UseMaskForGaps); 3262 } 3263