1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // X86 cost model. 56 // 57 //===----------------------------------------------------------------------===// 58 59 TargetTransformInfo::PopcntSupportKind 60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 61 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 62 // TODO: Currently the __builtin_popcount() implementation using SSE3 63 // instructions is inefficient. Once the problem is fixed, we should 64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 66 } 67 68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 69 TargetTransformInfo::CacheLevel Level) const { 70 switch (Level) { 71 case TargetTransformInfo::CacheLevel::L1D: 72 // - Penryn 73 // - Nehalem 74 // - Westmere 75 // - Sandy Bridge 76 // - Ivy Bridge 77 // - Haswell 78 // - Broadwell 79 // - Skylake 80 // - Kabylake 81 return 32 * 1024; // 32 KByte 82 case TargetTransformInfo::CacheLevel::L2D: 83 // - Penryn 84 // - Nehalem 85 // - Westmere 86 // - Sandy Bridge 87 // - Ivy Bridge 88 // - Haswell 89 // - Broadwell 90 // - Skylake 91 // - Kabylake 92 return 256 * 1024; // 256 KByte 93 } 94 95 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 96 } 97 98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 99 TargetTransformInfo::CacheLevel Level) const { 100 // - Penryn 101 // - Nehalem 102 // - Westmere 103 // - Sandy Bridge 104 // - Ivy Bridge 105 // - Haswell 106 // - Broadwell 107 // - Skylake 108 // - Kabylake 109 switch (Level) { 110 case TargetTransformInfo::CacheLevel::L1D: 111 LLVM_FALLTHROUGH; 112 case TargetTransformInfo::CacheLevel::L2D: 113 return 8; 114 } 115 116 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 117 } 118 119 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 120 bool Vector = (ClassID == 1); 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 TypeSize 133 X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { 134 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 135 switch (K) { 136 case TargetTransformInfo::RGK_Scalar: 137 return TypeSize::getFixed(ST->is64Bit() ? 64 : 32); 138 case TargetTransformInfo::RGK_FixedWidthVector: 139 if (ST->hasAVX512() && PreferVectorWidth >= 512) 140 return TypeSize::getFixed(512); 141 if (ST->hasAVX() && PreferVectorWidth >= 256) 142 return TypeSize::getFixed(256); 143 if (ST->hasSSE1() && PreferVectorWidth >= 128) 144 return TypeSize::getFixed(128); 145 return TypeSize::getFixed(0); 146 case TargetTransformInfo::RGK_ScalableVector: 147 return TypeSize::getScalable(0); 148 } 149 150 llvm_unreachable("Unsupported register kind"); 151 } 152 153 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 154 return getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector) 155 .getFixedSize(); 156 } 157 158 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 159 // If the loop will not be vectorized, don't interleave the loop. 160 // Let regular unroll to unroll the loop, which saves the overflow 161 // check and memory check cost. 162 if (VF == 1) 163 return 1; 164 165 if (ST->isAtom()) 166 return 1; 167 168 // Sandybridge and Haswell have multiple execution ports and pipelined 169 // vector units. 170 if (ST->hasAVX()) 171 return 4; 172 173 return 2; 174 } 175 176 InstructionCost X86TTIImpl::getArithmeticInstrCost( 177 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, 178 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 179 TTI::OperandValueProperties Opd1PropInfo, 180 TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, 181 const Instruction *CxtI) { 182 // TODO: Handle more cost kinds. 183 if (CostKind != TTI::TCK_RecipThroughput) 184 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, 185 Op2Info, Opd1PropInfo, 186 Opd2PropInfo, Args, CxtI); 187 188 // vXi8 multiplications are always promoted to vXi16. 189 if (Opcode == Instruction::Mul && Ty->isVectorTy() && 190 Ty->getScalarSizeInBits() == 8) { 191 Type *WideVecTy = 192 VectorType::getExtendedElementVectorType(cast<VectorType>(Ty)); 193 return getCastInstrCost(Instruction::ZExt, WideVecTy, Ty, 194 TargetTransformInfo::CastContextHint::None, 195 CostKind) + 196 getCastInstrCost(Instruction::Trunc, Ty, WideVecTy, 197 TargetTransformInfo::CastContextHint::None, 198 CostKind) + 199 getArithmeticInstrCost(Opcode, WideVecTy, CostKind, Op1Info, Op2Info, 200 Opd1PropInfo, Opd2PropInfo); 201 } 202 203 // Legalize the type. 204 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 205 206 int ISD = TLI->InstructionOpcodeToISD(Opcode); 207 assert(ISD && "Invalid opcode"); 208 209 if (ISD == ISD::MUL && Args.size() == 2 && LT.second.isVector() && 210 LT.second.getScalarType() == MVT::i32) { 211 // Check if the operands can be represented as a smaller datatype. 212 bool Op1Signed = false, Op2Signed = false; 213 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 214 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 215 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 216 217 // If both are representable as i15 and at least one is zero-extended, 218 // then we can treat this as PMADDWD which has the same costs 219 // as a vXi16 multiply.. 220 if (OpMinSize <= 15 && (!Op1Signed || !Op2Signed) && !ST->isPMADDWDSlow()) 221 LT.second = 222 MVT::getVectorVT(MVT::i16, 2 * LT.second.getVectorNumElements()); 223 } 224 225 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 226 ISD == ISD::UREM) && 227 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 228 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 229 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 230 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 231 // On X86, vector signed division by constants power-of-two are 232 // normally expanded to the sequence SRA + SRL + ADD + SRA. 233 // The OperandValue properties may not be the same as that of the previous 234 // operation; conservatively assume OP_None. 235 InstructionCost Cost = 236 2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Op1Info, 237 Op2Info, TargetTransformInfo::OP_None, 238 TargetTransformInfo::OP_None); 239 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 240 Op2Info, TargetTransformInfo::OP_None, 241 TargetTransformInfo::OP_None); 242 Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind, Op1Info, 243 Op2Info, TargetTransformInfo::OP_None, 244 TargetTransformInfo::OP_None); 245 246 if (ISD == ISD::SREM) { 247 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 248 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info, 249 Op2Info); 250 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info, 251 Op2Info); 252 } 253 254 return Cost; 255 } 256 257 // Vector unsigned division/remainder will be simplified to shifts/masks. 258 if (ISD == ISD::UDIV) 259 return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 260 Op2Info, TargetTransformInfo::OP_None, 261 TargetTransformInfo::OP_None); 262 // UREM 263 return getArithmeticInstrCost(Instruction::And, Ty, CostKind, Op1Info, 264 Op2Info, TargetTransformInfo::OP_None, 265 TargetTransformInfo::OP_None); 266 } 267 268 static const CostTblEntry GLMCostTable[] = { 269 { ISD::FDIV, MVT::f32, 18 }, // divss 270 { ISD::FDIV, MVT::v4f32, 35 }, // divps 271 { ISD::FDIV, MVT::f64, 33 }, // divsd 272 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 273 }; 274 275 if (ST->useGLMDivSqrtCosts()) 276 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 277 LT.second)) 278 return LT.first * Entry->Cost; 279 280 static const CostTblEntry SLMCostTable[] = { 281 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 282 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 283 { ISD::FMUL, MVT::f64, 2 }, // mulsd 284 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 285 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 286 { ISD::FDIV, MVT::f32, 17 }, // divss 287 { ISD::FDIV, MVT::v4f32, 39 }, // divps 288 { ISD::FDIV, MVT::f64, 32 }, // divsd 289 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 290 { ISD::FADD, MVT::v2f64, 2 }, // addpd 291 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 292 // v2i64/v4i64 mul is custom lowered as a series of long: 293 // multiplies(3), shifts(3) and adds(2) 294 // slm muldq version throughput is 2 and addq throughput 4 295 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 296 // 3X4 (addq throughput) = 17 297 { ISD::MUL, MVT::v2i64, 17 }, 298 // slm addq\subq throughput is 4 299 { ISD::ADD, MVT::v2i64, 4 }, 300 { ISD::SUB, MVT::v2i64, 4 }, 301 }; 302 303 if (ST->isSLM()) { 304 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 305 // Check if the operands can be shrinked into a smaller datatype. 306 // TODO: Merge this into generiic vXi32 MUL patterns above. 307 bool Op1Signed = false; 308 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 309 bool Op2Signed = false; 310 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 311 312 bool SignedMode = Op1Signed || Op2Signed; 313 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 314 315 if (OpMinSize <= 7) 316 return LT.first * 3; // pmullw/sext 317 if (!SignedMode && OpMinSize <= 8) 318 return LT.first * 3; // pmullw/zext 319 if (OpMinSize <= 15) 320 return LT.first * 5; // pmullw/pmulhw/pshuf 321 if (!SignedMode && OpMinSize <= 16) 322 return LT.first * 5; // pmullw/pmulhw/pshuf 323 } 324 325 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 326 LT.second)) { 327 return LT.first * Entry->Cost; 328 } 329 } 330 331 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 332 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 333 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 334 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 335 }; 336 337 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 338 ST->hasBWI()) { 339 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 340 LT.second)) 341 return LT.first * Entry->Cost; 342 } 343 344 static const CostTblEntry AVX512UniformConstCostTable[] = { 345 { ISD::SRA, MVT::v2i64, 1 }, 346 { ISD::SRA, MVT::v4i64, 1 }, 347 { ISD::SRA, MVT::v8i64, 1 }, 348 349 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 350 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 351 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 352 353 { ISD::SDIV, MVT::v16i32, 6 }, // pmuludq sequence 354 { ISD::SREM, MVT::v16i32, 8 }, // pmuludq+mul+sub sequence 355 { ISD::UDIV, MVT::v16i32, 5 }, // pmuludq sequence 356 { ISD::UREM, MVT::v16i32, 7 }, // pmuludq+mul+sub sequence 357 }; 358 359 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 360 ST->hasAVX512()) { 361 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 362 LT.second)) 363 return LT.first * Entry->Cost; 364 } 365 366 static const CostTblEntry AVX2UniformConstCostTable[] = { 367 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 368 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 369 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 370 371 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 372 373 { ISD::SDIV, MVT::v8i32, 6 }, // pmuludq sequence 374 { ISD::SREM, MVT::v8i32, 8 }, // pmuludq+mul+sub sequence 375 { ISD::UDIV, MVT::v8i32, 5 }, // pmuludq sequence 376 { ISD::UREM, MVT::v8i32, 7 }, // pmuludq+mul+sub sequence 377 }; 378 379 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 380 ST->hasAVX2()) { 381 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 382 LT.second)) 383 return LT.first * Entry->Cost; 384 } 385 386 static const CostTblEntry SSE2UniformConstCostTable[] = { 387 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 388 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 389 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 390 391 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 392 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 393 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 394 395 { ISD::SDIV, MVT::v8i32, 12+2 }, // 2*pmuludq sequence + split. 396 { ISD::SREM, MVT::v8i32, 16+2 }, // 2*pmuludq+mul+sub sequence + split. 397 { ISD::SDIV, MVT::v4i32, 6 }, // pmuludq sequence 398 { ISD::SREM, MVT::v4i32, 8 }, // pmuludq+mul+sub sequence 399 { ISD::UDIV, MVT::v8i32, 10+2 }, // 2*pmuludq sequence + split. 400 { ISD::UREM, MVT::v8i32, 14+2 }, // 2*pmuludq+mul+sub sequence + split. 401 { ISD::UDIV, MVT::v4i32, 5 }, // pmuludq sequence 402 { ISD::UREM, MVT::v4i32, 7 }, // pmuludq+mul+sub sequence 403 }; 404 405 // XOP has faster vXi8 shifts. 406 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 407 ST->hasSSE2() && !ST->hasXOP()) { 408 if (const auto *Entry = 409 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 410 return LT.first * Entry->Cost; 411 } 412 413 static const CostTblEntry AVX512BWConstCostTable[] = { 414 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 415 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 416 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 417 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 418 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 419 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 420 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 421 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 422 }; 423 424 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 425 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 426 ST->hasBWI()) { 427 if (const auto *Entry = 428 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 429 return LT.first * Entry->Cost; 430 } 431 432 static const CostTblEntry AVX512ConstCostTable[] = { 433 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 434 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 435 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 436 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 437 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 438 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 439 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 440 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 441 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 442 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 443 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 444 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 445 }; 446 447 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 448 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 449 ST->hasAVX512()) { 450 if (const auto *Entry = 451 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 452 return LT.first * Entry->Cost; 453 } 454 455 static const CostTblEntry AVX2ConstCostTable[] = { 456 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 457 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 458 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 459 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 460 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 461 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 462 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 463 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 464 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 465 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 466 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 467 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 468 }; 469 470 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 471 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 472 ST->hasAVX2()) { 473 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 474 return LT.first * Entry->Cost; 475 } 476 477 static const CostTblEntry SSE2ConstCostTable[] = { 478 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 479 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 480 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 481 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 482 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 483 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 484 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 485 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 486 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 487 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 488 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 489 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 490 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 491 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 492 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 493 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 494 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 495 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 496 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 497 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 498 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 499 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 500 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 501 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 502 }; 503 504 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 505 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 506 ST->hasSSE2()) { 507 // pmuldq sequence. 508 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 509 return LT.first * 32; 510 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 511 return LT.first * 38; 512 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 513 return LT.first * 15; 514 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 515 return LT.first * 20; 516 517 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 518 return LT.first * Entry->Cost; 519 } 520 521 static const CostTblEntry AVX512BWShiftCostTable[] = { 522 { ISD::SHL, MVT::v16i8, 4 }, // extend/vpsllvw/pack sequence. 523 { ISD::SRL, MVT::v16i8, 4 }, // extend/vpsrlvw/pack sequence. 524 { ISD::SRA, MVT::v16i8, 4 }, // extend/vpsravw/pack sequence. 525 { ISD::SHL, MVT::v32i8, 4 }, // extend/vpsllvw/pack sequence. 526 { ISD::SRL, MVT::v32i8, 4 }, // extend/vpsrlvw/pack sequence. 527 { ISD::SRA, MVT::v32i8, 6 }, // extend/vpsravw/pack sequence. 528 { ISD::SHL, MVT::v64i8, 6 }, // extend/vpsllvw/pack sequence. 529 { ISD::SRL, MVT::v64i8, 7 }, // extend/vpsrlvw/pack sequence. 530 { ISD::SRA, MVT::v64i8, 15 }, // extend/vpsravw/pack sequence. 531 532 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 533 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 534 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 535 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 536 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 537 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 538 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 539 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 540 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 541 }; 542 543 if (ST->hasBWI()) 544 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 545 return LT.first * Entry->Cost; 546 547 static const CostTblEntry AVX2UniformCostTable[] = { 548 // Uniform splats are cheaper for the following instructions. 549 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 550 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 551 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 552 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 553 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 554 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 555 556 { ISD::SHL, MVT::v8i32, 1 }, // pslld 557 { ISD::SRL, MVT::v8i32, 1 }, // psrld 558 { ISD::SRA, MVT::v8i32, 1 }, // psrad 559 { ISD::SHL, MVT::v4i64, 1 }, // psllq 560 { ISD::SRL, MVT::v4i64, 1 }, // psrlq 561 }; 562 563 if (ST->hasAVX2() && 564 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 565 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 566 if (const auto *Entry = 567 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 568 return LT.first * Entry->Cost; 569 } 570 571 static const CostTblEntry SSE2UniformCostTable[] = { 572 // Uniform splats are cheaper for the following instructions. 573 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 574 { ISD::SHL, MVT::v4i32, 1 }, // pslld 575 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 576 577 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 578 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 579 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 580 581 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 582 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 583 }; 584 585 if (ST->hasSSE2() && 586 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 587 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 588 if (const auto *Entry = 589 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 590 return LT.first * Entry->Cost; 591 } 592 593 static const CostTblEntry AVX512DQCostTable[] = { 594 { ISD::MUL, MVT::v2i64, 2 }, // pmullq 595 { ISD::MUL, MVT::v4i64, 2 }, // pmullq 596 { ISD::MUL, MVT::v8i64, 2 } // pmullq 597 }; 598 599 // Look for AVX512DQ lowering tricks for custom cases. 600 if (ST->hasDQI()) 601 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 602 return LT.first * Entry->Cost; 603 604 static const CostTblEntry AVX512BWCostTable[] = { 605 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 606 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 607 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 608 }; 609 610 // Look for AVX512BW lowering tricks for custom cases. 611 if (ST->hasBWI()) 612 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 613 return LT.first * Entry->Cost; 614 615 static const CostTblEntry AVX512CostTable[] = { 616 { ISD::SHL, MVT::v4i32, 1 }, 617 { ISD::SRL, MVT::v4i32, 1 }, 618 { ISD::SRA, MVT::v4i32, 1 }, 619 { ISD::SHL, MVT::v8i32, 1 }, 620 { ISD::SRL, MVT::v8i32, 1 }, 621 { ISD::SRA, MVT::v8i32, 1 }, 622 { ISD::SHL, MVT::v16i32, 1 }, 623 { ISD::SRL, MVT::v16i32, 1 }, 624 { ISD::SRA, MVT::v16i32, 1 }, 625 626 { ISD::SHL, MVT::v2i64, 1 }, 627 { ISD::SRL, MVT::v2i64, 1 }, 628 { ISD::SHL, MVT::v4i64, 1 }, 629 { ISD::SRL, MVT::v4i64, 1 }, 630 { ISD::SHL, MVT::v8i64, 1 }, 631 { ISD::SRL, MVT::v8i64, 1 }, 632 633 { ISD::SRA, MVT::v2i64, 1 }, 634 { ISD::SRA, MVT::v4i64, 1 }, 635 { ISD::SRA, MVT::v8i64, 1 }, 636 637 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 638 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 639 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 640 { ISD::MUL, MVT::v8i64, 6 }, // 3*pmuludq/3*shift/2*add 641 642 { ISD::FNEG, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 643 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 644 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 645 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 646 { ISD::FDIV, MVT::f64, 4 }, // Skylake from http://www.agner.org/ 647 { ISD::FDIV, MVT::v2f64, 4 }, // Skylake from http://www.agner.org/ 648 { ISD::FDIV, MVT::v4f64, 8 }, // Skylake from http://www.agner.org/ 649 { ISD::FDIV, MVT::v8f64, 16 }, // Skylake from http://www.agner.org/ 650 651 { ISD::FNEG, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 652 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 653 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 654 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 655 { ISD::FDIV, MVT::f32, 3 }, // Skylake from http://www.agner.org/ 656 { ISD::FDIV, MVT::v4f32, 3 }, // Skylake from http://www.agner.org/ 657 { ISD::FDIV, MVT::v8f32, 5 }, // Skylake from http://www.agner.org/ 658 { ISD::FDIV, MVT::v16f32, 10 }, // Skylake from http://www.agner.org/ 659 }; 660 661 if (ST->hasAVX512()) 662 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 663 return LT.first * Entry->Cost; 664 665 static const CostTblEntry AVX2ShiftCostTable[] = { 666 // Shifts on vXi64/vXi32 on AVX2 is legal even though we declare to 667 // customize them to detect the cases where shift amount is a scalar one. 668 { ISD::SHL, MVT::v4i32, 2 }, // vpsllvd (Haswell from agner.org) 669 { ISD::SRL, MVT::v4i32, 2 }, // vpsrlvd (Haswell from agner.org) 670 { ISD::SRA, MVT::v4i32, 2 }, // vpsravd (Haswell from agner.org) 671 { ISD::SHL, MVT::v8i32, 2 }, // vpsllvd (Haswell from agner.org) 672 { ISD::SRL, MVT::v8i32, 2 }, // vpsrlvd (Haswell from agner.org) 673 { ISD::SRA, MVT::v8i32, 2 }, // vpsravd (Haswell from agner.org) 674 { ISD::SHL, MVT::v2i64, 1 }, // vpsllvq (Haswell from agner.org) 675 { ISD::SRL, MVT::v2i64, 1 }, // vpsrlvq (Haswell from agner.org) 676 { ISD::SHL, MVT::v4i64, 1 }, // vpsllvq (Haswell from agner.org) 677 { ISD::SRL, MVT::v4i64, 1 }, // vpsrlvq (Haswell from agner.org) 678 }; 679 680 if (ST->hasAVX512()) { 681 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 682 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 683 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 684 // On AVX512, a packed v32i16 shift left by a constant build_vector 685 // is lowered into a vector multiply (vpmullw). 686 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 687 Op1Info, Op2Info, 688 TargetTransformInfo::OP_None, 689 TargetTransformInfo::OP_None); 690 } 691 692 // Look for AVX2 lowering tricks (XOP is always better at v4i32 shifts). 693 if (ST->hasAVX2() && !(ST->hasXOP() && LT.second == MVT::v4i32)) { 694 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 695 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 696 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 697 // On AVX2, a packed v16i16 shift left by a constant build_vector 698 // is lowered into a vector multiply (vpmullw). 699 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 700 Op1Info, Op2Info, 701 TargetTransformInfo::OP_None, 702 TargetTransformInfo::OP_None); 703 704 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 705 return LT.first * Entry->Cost; 706 } 707 708 static const CostTblEntry XOPShiftCostTable[] = { 709 // 128bit shifts take 1cy, but right shifts require negation beforehand. 710 { ISD::SHL, MVT::v16i8, 1 }, 711 { ISD::SRL, MVT::v16i8, 2 }, 712 { ISD::SRA, MVT::v16i8, 2 }, 713 { ISD::SHL, MVT::v8i16, 1 }, 714 { ISD::SRL, MVT::v8i16, 2 }, 715 { ISD::SRA, MVT::v8i16, 2 }, 716 { ISD::SHL, MVT::v4i32, 1 }, 717 { ISD::SRL, MVT::v4i32, 2 }, 718 { ISD::SRA, MVT::v4i32, 2 }, 719 { ISD::SHL, MVT::v2i64, 1 }, 720 { ISD::SRL, MVT::v2i64, 2 }, 721 { ISD::SRA, MVT::v2i64, 2 }, 722 // 256bit shifts require splitting if AVX2 didn't catch them above. 723 { ISD::SHL, MVT::v32i8, 2+2 }, 724 { ISD::SRL, MVT::v32i8, 4+2 }, 725 { ISD::SRA, MVT::v32i8, 4+2 }, 726 { ISD::SHL, MVT::v16i16, 2+2 }, 727 { ISD::SRL, MVT::v16i16, 4+2 }, 728 { ISD::SRA, MVT::v16i16, 4+2 }, 729 { ISD::SHL, MVT::v8i32, 2+2 }, 730 { ISD::SRL, MVT::v8i32, 4+2 }, 731 { ISD::SRA, MVT::v8i32, 4+2 }, 732 { ISD::SHL, MVT::v4i64, 2+2 }, 733 { ISD::SRL, MVT::v4i64, 4+2 }, 734 { ISD::SRA, MVT::v4i64, 4+2 }, 735 }; 736 737 // Look for XOP lowering tricks. 738 if (ST->hasXOP()) { 739 // If the right shift is constant then we'll fold the negation so 740 // it's as cheap as a left shift. 741 int ShiftISD = ISD; 742 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 743 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 744 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 745 ShiftISD = ISD::SHL; 746 if (const auto *Entry = 747 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 748 return LT.first * Entry->Cost; 749 } 750 751 static const CostTblEntry SSE2UniformShiftCostTable[] = { 752 // Uniform splats are cheaper for the following instructions. 753 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 754 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 755 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 756 757 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 758 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 759 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 760 761 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 762 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 763 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 764 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 765 }; 766 767 if (ST->hasSSE2() && 768 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 769 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 770 771 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 772 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 773 return LT.first * 4; // 2*psrad + shuffle. 774 775 if (const auto *Entry = 776 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 777 return LT.first * Entry->Cost; 778 } 779 780 if (ISD == ISD::SHL && 781 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 782 MVT VT = LT.second; 783 // Vector shift left by non uniform constant can be lowered 784 // into vector multiply. 785 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 786 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 787 ISD = ISD::MUL; 788 } 789 790 static const CostTblEntry AVX2CostTable[] = { 791 { ISD::SHL, MVT::v16i8, 6 }, // vpblendvb sequence. 792 { ISD::SHL, MVT::v32i8, 6 }, // vpblendvb sequence. 793 { ISD::SHL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 794 { ISD::SHL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 795 { ISD::SHL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 796 { ISD::SHL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 797 798 { ISD::SRL, MVT::v16i8, 6 }, // vpblendvb sequence. 799 { ISD::SRL, MVT::v32i8, 6 }, // vpblendvb sequence. 800 { ISD::SRL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 801 { ISD::SRL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 802 { ISD::SRL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 803 { ISD::SRL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 804 805 { ISD::SRA, MVT::v16i8, 17 }, // vpblendvb sequence. 806 { ISD::SRA, MVT::v32i8, 17 }, // vpblendvb sequence. 807 { ISD::SRA, MVT::v64i8, 34 }, // 2*vpblendvb sequence. 808 { ISD::SRA, MVT::v8i16, 5 }, // extend/vpsravd/pack sequence. 809 { ISD::SRA, MVT::v16i16, 7 }, // extend/vpsravd/pack sequence. 810 { ISD::SRA, MVT::v32i16, 14 }, // 2*extend/vpsravd/pack sequence. 811 { ISD::SRA, MVT::v2i64, 2 }, // srl/xor/sub sequence. 812 { ISD::SRA, MVT::v4i64, 2 }, // srl/xor/sub sequence. 813 814 { ISD::SUB, MVT::v32i8, 1 }, // psubb 815 { ISD::ADD, MVT::v32i8, 1 }, // paddb 816 { ISD::SUB, MVT::v16i16, 1 }, // psubw 817 { ISD::ADD, MVT::v16i16, 1 }, // paddw 818 { ISD::SUB, MVT::v8i32, 1 }, // psubd 819 { ISD::ADD, MVT::v8i32, 1 }, // paddd 820 { ISD::SUB, MVT::v4i64, 1 }, // psubq 821 { ISD::ADD, MVT::v4i64, 1 }, // paddq 822 823 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 824 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 825 { ISD::MUL, MVT::v4i64, 6 }, // 3*pmuludq/3*shift/2*add 826 827 { ISD::FNEG, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 828 { ISD::FNEG, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 829 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 830 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 831 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 832 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 833 { ISD::FMUL, MVT::f64, 1 }, // Haswell from http://www.agner.org/ 834 { ISD::FMUL, MVT::v2f64, 1 }, // Haswell from http://www.agner.org/ 835 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 836 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 837 838 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 839 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 840 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 841 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 842 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 843 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 844 }; 845 846 // Look for AVX2 lowering tricks for custom cases. 847 if (ST->hasAVX2()) 848 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 849 return LT.first * Entry->Cost; 850 851 static const CostTblEntry AVX1CostTable[] = { 852 // We don't have to scalarize unsupported ops. We can issue two half-sized 853 // operations and we only need to extract the upper YMM half. 854 // Two ops + 1 extract + 1 insert = 4. 855 { ISD::MUL, MVT::v16i16, 4 }, 856 { ISD::MUL, MVT::v8i32, 5 }, // BTVER2 from http://www.agner.org/ 857 { ISD::MUL, MVT::v4i64, 12 }, 858 859 { ISD::SUB, MVT::v32i8, 4 }, 860 { ISD::ADD, MVT::v32i8, 4 }, 861 { ISD::SUB, MVT::v16i16, 4 }, 862 { ISD::ADD, MVT::v16i16, 4 }, 863 { ISD::SUB, MVT::v8i32, 4 }, 864 { ISD::ADD, MVT::v8i32, 4 }, 865 { ISD::SUB, MVT::v4i64, 4 }, 866 { ISD::ADD, MVT::v4i64, 4 }, 867 868 { ISD::SHL, MVT::v32i8, 22 }, // pblendvb sequence + split. 869 { ISD::SHL, MVT::v8i16, 6 }, // pblendvb sequence. 870 { ISD::SHL, MVT::v16i16, 13 }, // pblendvb sequence + split. 871 { ISD::SHL, MVT::v4i32, 3 }, // pslld/paddd/cvttps2dq/pmulld 872 { ISD::SHL, MVT::v8i32, 9 }, // pslld/paddd/cvttps2dq/pmulld + split 873 { ISD::SHL, MVT::v2i64, 2 }, // Shift each lane + blend. 874 { ISD::SHL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 875 876 { ISD::SRL, MVT::v32i8, 23 }, // pblendvb sequence + split. 877 { ISD::SRL, MVT::v16i16, 28 }, // pblendvb sequence + split. 878 { ISD::SRL, MVT::v4i32, 6 }, // Shift each lane + blend. 879 { ISD::SRL, MVT::v8i32, 14 }, // Shift each lane + blend + split. 880 { ISD::SRL, MVT::v2i64, 2 }, // Shift each lane + blend. 881 { ISD::SRL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 882 883 { ISD::SRA, MVT::v32i8, 44 }, // pblendvb sequence + split. 884 { ISD::SRA, MVT::v16i16, 28 }, // pblendvb sequence + split. 885 { ISD::SRA, MVT::v4i32, 6 }, // Shift each lane + blend. 886 { ISD::SRA, MVT::v8i32, 14 }, // Shift each lane + blend + split. 887 { ISD::SRA, MVT::v2i64, 5 }, // Shift each lane + blend. 888 { ISD::SRA, MVT::v4i64, 12 }, // Shift each lane + blend + split. 889 890 { ISD::FNEG, MVT::v4f64, 2 }, // BTVER2 from http://www.agner.org/ 891 { ISD::FNEG, MVT::v8f32, 2 }, // BTVER2 from http://www.agner.org/ 892 893 { ISD::FMUL, MVT::f64, 2 }, // BTVER2 from http://www.agner.org/ 894 { ISD::FMUL, MVT::v2f64, 2 }, // BTVER2 from http://www.agner.org/ 895 { ISD::FMUL, MVT::v4f64, 4 }, // BTVER2 from http://www.agner.org/ 896 897 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 898 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 899 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 900 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 901 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 902 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 903 }; 904 905 if (ST->hasAVX()) 906 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 907 return LT.first * Entry->Cost; 908 909 static const CostTblEntry SSE42CostTable[] = { 910 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 911 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 912 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 913 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 914 915 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 916 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 917 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 918 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 919 920 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 921 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 922 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 923 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 924 925 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 926 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 927 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 928 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 929 930 { ISD::MUL, MVT::v2i64, 6 } // 3*pmuludq/3*shift/2*add 931 }; 932 933 if (ST->hasSSE42()) 934 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 935 return LT.first * Entry->Cost; 936 937 static const CostTblEntry SSE41CostTable[] = { 938 { ISD::SHL, MVT::v16i8, 10 }, // pblendvb sequence. 939 { ISD::SHL, MVT::v8i16, 11 }, // pblendvb sequence. 940 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 941 942 { ISD::SRL, MVT::v16i8, 11 }, // pblendvb sequence. 943 { ISD::SRL, MVT::v8i16, 13 }, // pblendvb sequence. 944 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 945 946 { ISD::SRA, MVT::v16i8, 21 }, // pblendvb sequence. 947 { ISD::SRA, MVT::v8i16, 13 }, // pblendvb sequence. 948 949 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 950 }; 951 952 if (ST->hasSSE41()) 953 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 954 return LT.first * Entry->Cost; 955 956 static const CostTblEntry SSE2CostTable[] = { 957 // We don't correctly identify costs of casts because they are marked as 958 // custom. 959 { ISD::SHL, MVT::v16i8, 13 }, // cmpgtb sequence. 960 { ISD::SHL, MVT::v8i16, 25 }, // cmpgtw sequence. 961 { ISD::SHL, MVT::v4i32, 16 }, // pslld/paddd/cvttps2dq/pmuludq. 962 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 963 964 { ISD::SRL, MVT::v16i8, 14 }, // cmpgtb sequence. 965 { ISD::SRL, MVT::v8i16, 16 }, // cmpgtw sequence. 966 { ISD::SRL, MVT::v4i32, 12 }, // Shift each lane + blend. 967 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 968 969 { ISD::SRA, MVT::v16i8, 27 }, // unpacked cmpgtb sequence. 970 { ISD::SRA, MVT::v8i16, 16 }, // cmpgtw sequence. 971 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 972 { ISD::SRA, MVT::v2i64, 8 }, // srl/xor/sub splat+shuffle sequence. 973 974 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 975 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 976 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 977 978 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 979 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 980 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 981 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 982 983 { ISD::FNEG, MVT::f32, 1 }, // Pentium IV from http://www.agner.org/ 984 { ISD::FNEG, MVT::f64, 1 }, // Pentium IV from http://www.agner.org/ 985 { ISD::FNEG, MVT::v4f32, 1 }, // Pentium IV from http://www.agner.org/ 986 { ISD::FNEG, MVT::v2f64, 1 }, // Pentium IV from http://www.agner.org/ 987 988 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 989 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 990 991 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 992 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 993 }; 994 995 if (ST->hasSSE2()) 996 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 997 return LT.first * Entry->Cost; 998 999 static const CostTblEntry SSE1CostTable[] = { 1000 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 1001 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 1002 1003 { ISD::FNEG, MVT::f32, 2 }, // Pentium III from http://www.agner.org/ 1004 { ISD::FNEG, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1005 1006 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1007 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1008 1009 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1010 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1011 }; 1012 1013 if (ST->hasSSE1()) 1014 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 1015 return LT.first * Entry->Cost; 1016 1017 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 1018 { ISD::ADD, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1019 { ISD::SUB, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1020 }; 1021 1022 if (ST->is64Bit()) 1023 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, LT.second)) 1024 return LT.first * Entry->Cost; 1025 1026 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 1027 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1028 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1029 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1030 1031 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1032 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1033 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1034 }; 1035 1036 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, LT.second)) 1037 return LT.first * Entry->Cost; 1038 1039 // It is not a good idea to vectorize division. We have to scalarize it and 1040 // in the process we will often end up having to spilling regular 1041 // registers. The overhead of division is going to dominate most kernels 1042 // anyways so try hard to prevent vectorization of division - it is 1043 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 1044 // to hide "20 cycles" for each lane. 1045 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 1046 ISD == ISD::UDIV || ISD == ISD::UREM)) { 1047 InstructionCost ScalarCost = getArithmeticInstrCost( 1048 Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info, 1049 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 1050 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 1051 } 1052 1053 // Fallback to the default implementation. 1054 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info); 1055 } 1056 1057 InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, 1058 VectorType *BaseTp, 1059 ArrayRef<int> Mask, int Index, 1060 VectorType *SubTp) { 1061 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 1062 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 1063 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 1064 1065 Kind = improveShuffleKindFromMask(Kind, Mask); 1066 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 1067 if (Kind == TTI::SK_Transpose) 1068 Kind = TTI::SK_PermuteTwoSrc; 1069 1070 // For Broadcasts we are splatting the first element from the first input 1071 // register, so only need to reference that input and all the output 1072 // registers are the same. 1073 if (Kind == TTI::SK_Broadcast) 1074 LT.first = 1; 1075 1076 // Subvector extractions are free if they start at the beginning of a 1077 // vector and cheap if the subvectors are aligned. 1078 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 1079 int NumElts = LT.second.getVectorNumElements(); 1080 if ((Index % NumElts) == 0) 1081 return 0; 1082 std::pair<InstructionCost, MVT> SubLT = 1083 TLI->getTypeLegalizationCost(DL, SubTp); 1084 if (SubLT.second.isVector()) { 1085 int NumSubElts = SubLT.second.getVectorNumElements(); 1086 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1087 return SubLT.first; 1088 // Handle some cases for widening legalization. For now we only handle 1089 // cases where the original subvector was naturally aligned and evenly 1090 // fit in its legalized subvector type. 1091 // FIXME: Remove some of the alignment restrictions. 1092 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 1093 // vectors. 1094 int OrigSubElts = cast<FixedVectorType>(SubTp)->getNumElements(); 1095 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 1096 (NumSubElts % OrigSubElts) == 0 && 1097 LT.second.getVectorElementType() == 1098 SubLT.second.getVectorElementType() && 1099 LT.second.getVectorElementType().getSizeInBits() == 1100 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 1101 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 1102 "Unexpected number of elements!"); 1103 auto *VecTy = FixedVectorType::get(BaseTp->getElementType(), 1104 LT.second.getVectorNumElements()); 1105 auto *SubTy = FixedVectorType::get(BaseTp->getElementType(), 1106 SubLT.second.getVectorNumElements()); 1107 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 1108 InstructionCost ExtractCost = getShuffleCost( 1109 TTI::SK_ExtractSubvector, VecTy, None, ExtractIndex, SubTy); 1110 1111 // If the original size is 32-bits or more, we can use pshufd. Otherwise 1112 // if we have SSSE3 we can use pshufb. 1113 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 1114 return ExtractCost + 1; // pshufd or pshufb 1115 1116 assert(SubTp->getPrimitiveSizeInBits() == 16 && 1117 "Unexpected vector size"); 1118 1119 return ExtractCost + 2; // worst case pshufhw + pshufd 1120 } 1121 } 1122 } 1123 1124 // Subvector insertions are cheap if the subvectors are aligned. 1125 // Note that in general, the insertion starting at the beginning of a vector 1126 // isn't free, because we need to preserve the rest of the wide vector. 1127 if (Kind == TTI::SK_InsertSubvector && LT.second.isVector()) { 1128 int NumElts = LT.second.getVectorNumElements(); 1129 std::pair<InstructionCost, MVT> SubLT = 1130 TLI->getTypeLegalizationCost(DL, SubTp); 1131 if (SubLT.second.isVector()) { 1132 int NumSubElts = SubLT.second.getVectorNumElements(); 1133 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1134 return SubLT.first; 1135 } 1136 1137 // If the insertion isn't aligned, treat it like a 2-op shuffle. 1138 Kind = TTI::SK_PermuteTwoSrc; 1139 } 1140 1141 // Handle some common (illegal) sub-vector types as they are often very cheap 1142 // to shuffle even on targets without PSHUFB. 1143 EVT VT = TLI->getValueType(DL, BaseTp); 1144 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 1145 !ST->hasSSSE3()) { 1146 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 1147 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 1148 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1149 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1150 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1151 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1152 1153 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1154 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1155 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1156 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1157 1158 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1159 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1160 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1161 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1162 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1163 1164 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1165 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1166 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1167 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1168 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1169 }; 1170 1171 if (ST->hasSSE2()) 1172 if (const auto *Entry = 1173 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1174 return Entry->Cost; 1175 } 1176 1177 // We are going to permute multiple sources and the result will be in multiple 1178 // destinations. Providing an accurate cost only for splits where the element 1179 // type remains the same. 1180 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1181 MVT LegalVT = LT.second; 1182 if (LegalVT.isVector() && 1183 LegalVT.getVectorElementType().getSizeInBits() == 1184 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1185 LegalVT.getVectorNumElements() < 1186 cast<FixedVectorType>(BaseTp)->getNumElements()) { 1187 1188 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1189 unsigned LegalVTSize = LegalVT.getStoreSize(); 1190 // Number of source vectors after legalization: 1191 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1192 // Number of destination vectors after legalization: 1193 InstructionCost NumOfDests = LT.first; 1194 1195 auto *SingleOpTy = FixedVectorType::get(BaseTp->getElementType(), 1196 LegalVT.getVectorNumElements()); 1197 1198 InstructionCost NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1199 return NumOfShuffles * getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 1200 None, 0, nullptr); 1201 } 1202 1203 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1204 } 1205 1206 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1207 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1208 // We assume that source and destination have the same vector type. 1209 InstructionCost NumOfDests = LT.first; 1210 InstructionCost NumOfShufflesPerDest = LT.first * 2 - 1; 1211 LT.first = NumOfDests * NumOfShufflesPerDest; 1212 } 1213 1214 static const CostTblEntry AVX512FP16ShuffleTbl[] = { 1215 {TTI::SK_Broadcast, MVT::v32f16, 1}, // vpbroadcastw 1216 {TTI::SK_Broadcast, MVT::v16f16, 1}, // vpbroadcastw 1217 {TTI::SK_Broadcast, MVT::v8f16, 1}, // vpbroadcastw 1218 1219 {TTI::SK_Reverse, MVT::v32f16, 2}, // vpermw 1220 {TTI::SK_Reverse, MVT::v16f16, 2}, // vpermw 1221 {TTI::SK_Reverse, MVT::v8f16, 1}, // vpshufb 1222 1223 {TTI::SK_PermuteSingleSrc, MVT::v32f16, 2}, // vpermw 1224 {TTI::SK_PermuteSingleSrc, MVT::v16f16, 2}, // vpermw 1225 {TTI::SK_PermuteSingleSrc, MVT::v8f16, 1}, // vpshufb 1226 1227 {TTI::SK_PermuteTwoSrc, MVT::v32f16, 2}, // vpermt2w 1228 {TTI::SK_PermuteTwoSrc, MVT::v16f16, 2}, // vpermt2w 1229 {TTI::SK_PermuteTwoSrc, MVT::v8f16, 2} // vpermt2w 1230 }; 1231 1232 if (!ST->useSoftFloat() && ST->hasFP16()) 1233 if (const auto *Entry = 1234 CostTableLookup(AVX512FP16ShuffleTbl, Kind, LT.second)) 1235 return LT.first * Entry->Cost; 1236 1237 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1238 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1239 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1240 1241 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1242 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1243 1244 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b 1245 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b 1246 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2} // vpermt2b 1247 }; 1248 1249 if (ST->hasVBMI()) 1250 if (const auto *Entry = 1251 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1252 return LT.first * Entry->Cost; 1253 1254 static const CostTblEntry AVX512BWShuffleTbl[] = { 1255 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1256 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1257 1258 {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw 1259 {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw 1260 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1261 1262 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw 1263 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw 1264 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1265 1266 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w 1267 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w 1268 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2}, // vpermt2w 1269 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1270 1271 {TTI::SK_Select, MVT::v32i16, 1}, // vblendmw 1272 {TTI::SK_Select, MVT::v64i8, 1}, // vblendmb 1273 }; 1274 1275 if (ST->hasBWI()) 1276 if (const auto *Entry = 1277 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1278 return LT.first * Entry->Cost; 1279 1280 static const CostTblEntry AVX512ShuffleTbl[] = { 1281 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1282 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1283 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1284 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1285 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1286 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1287 1288 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1289 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1290 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1291 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1292 {TTI::SK_Reverse, MVT::v32i16, 7}, // per mca 1293 {TTI::SK_Reverse, MVT::v64i8, 7}, // per mca 1294 1295 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1296 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1297 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1298 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1299 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1300 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1301 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1302 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1303 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1304 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1305 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1306 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1307 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1308 1309 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1310 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1311 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1312 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1313 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1314 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1315 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1316 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1317 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1318 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1319 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1320 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1321 1322 // FIXME: This just applies the type legalization cost rules above 1323 // assuming these completely split. 1324 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1325 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1326 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1327 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1328 1329 {TTI::SK_Select, MVT::v32i16, 1}, // vpternlogq 1330 {TTI::SK_Select, MVT::v64i8, 1}, // vpternlogq 1331 {TTI::SK_Select, MVT::v8f64, 1}, // vblendmpd 1332 {TTI::SK_Select, MVT::v16f32, 1}, // vblendmps 1333 {TTI::SK_Select, MVT::v8i64, 1}, // vblendmq 1334 {TTI::SK_Select, MVT::v16i32, 1}, // vblendmd 1335 }; 1336 1337 if (ST->hasAVX512()) 1338 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1339 return LT.first * Entry->Cost; 1340 1341 static const CostTblEntry AVX2ShuffleTbl[] = { 1342 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1343 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1344 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1345 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1346 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1347 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1348 1349 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1350 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1351 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1352 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1353 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1354 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1355 1356 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1357 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1358 1359 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1360 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1361 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1362 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1363 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1364 // + vpblendvb 1365 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1366 // + vpblendvb 1367 1368 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1369 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1370 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1371 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1372 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1373 // + vpblendvb 1374 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1375 // + vpblendvb 1376 }; 1377 1378 if (ST->hasAVX2()) 1379 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1380 return LT.first * Entry->Cost; 1381 1382 static const CostTblEntry XOPShuffleTbl[] = { 1383 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1384 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1385 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1386 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1387 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1388 // + vinsertf128 1389 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1390 // + vinsertf128 1391 1392 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1393 // + vinsertf128 1394 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1395 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1396 // + vinsertf128 1397 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1398 }; 1399 1400 if (ST->hasXOP()) 1401 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1402 return LT.first * Entry->Cost; 1403 1404 static const CostTblEntry AVX1ShuffleTbl[] = { 1405 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1406 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1407 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1408 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1409 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1410 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1411 1412 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1413 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1414 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1415 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1416 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1417 // + vinsertf128 1418 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1419 // + vinsertf128 1420 1421 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1422 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1423 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1424 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1425 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1426 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1427 1428 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1429 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1430 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1431 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1432 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1433 // + 2*por + vinsertf128 1434 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1435 // + 2*por + vinsertf128 1436 1437 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1438 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1439 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1440 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1441 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1442 // + 4*por + vinsertf128 1443 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1444 // + 4*por + vinsertf128 1445 }; 1446 1447 if (ST->hasAVX()) 1448 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1449 return LT.first * Entry->Cost; 1450 1451 static const CostTblEntry SSE41ShuffleTbl[] = { 1452 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1453 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1454 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1455 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1456 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1457 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1458 }; 1459 1460 if (ST->hasSSE41()) 1461 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1462 return LT.first * Entry->Cost; 1463 1464 static const CostTblEntry SSSE3ShuffleTbl[] = { 1465 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1466 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1467 1468 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1469 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1470 1471 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1472 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1473 1474 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1475 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1476 1477 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1478 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1479 }; 1480 1481 if (ST->hasSSSE3()) 1482 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1483 return LT.first * Entry->Cost; 1484 1485 static const CostTblEntry SSE2ShuffleTbl[] = { 1486 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1487 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1488 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1489 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1490 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1491 1492 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1493 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1494 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1495 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1496 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1497 // + 2*pshufd + 2*unpck + packus 1498 1499 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1500 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1501 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1502 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1503 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1504 1505 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1506 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1507 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1508 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1509 // + pshufd/unpck 1510 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1511 // + 2*pshufd + 2*unpck + 2*packus 1512 1513 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1514 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1515 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1516 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1517 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1518 }; 1519 1520 if (ST->hasSSE2()) 1521 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1522 return LT.first * Entry->Cost; 1523 1524 static const CostTblEntry SSE1ShuffleTbl[] = { 1525 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1526 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1527 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1528 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1529 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1530 }; 1531 1532 if (ST->hasSSE1()) 1533 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1534 return LT.first * Entry->Cost; 1535 1536 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1537 } 1538 1539 InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, 1540 Type *Src, 1541 TTI::CastContextHint CCH, 1542 TTI::TargetCostKind CostKind, 1543 const Instruction *I) { 1544 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1545 assert(ISD && "Invalid opcode"); 1546 1547 // TODO: Allow non-throughput costs that aren't binary. 1548 auto AdjustCost = [&CostKind](InstructionCost Cost) -> InstructionCost { 1549 if (CostKind != TTI::TCK_RecipThroughput) 1550 return Cost == 0 ? 0 : 1; 1551 return Cost; 1552 }; 1553 1554 // The cost tables include both specific, custom (non-legal) src/dst type 1555 // conversions and generic, legalized types. We test for customs first, before 1556 // falling back to legalization. 1557 // FIXME: Need a better design of the cost table to handle non-simple types of 1558 // potential massive combinations (elem_num x src_type x dst_type). 1559 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1560 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1561 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1562 1563 // Mask sign extend has an instruction. 1564 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1565 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1566 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1567 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1568 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1569 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1570 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1571 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1572 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1573 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1574 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1575 1576 // Mask zero extend is a sext + shift. 1577 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1578 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1579 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1580 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1581 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1582 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1583 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1584 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1585 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1586 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1587 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1588 1589 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, 1590 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm 1591 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // widen to zmm 1592 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // widen to zmm 1593 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // vpmovwb 1594 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // widen to zmm 1595 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // widen to zmm 1596 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // vpmovwb 1597 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // widen to zmm 1598 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // widen to zmm 1599 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // vpmovwb 1600 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // widen to zmm 1601 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // widen to zmm 1602 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // widen to zmm 1603 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, 1604 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, 1605 }; 1606 1607 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1608 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1609 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1610 1611 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1612 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1613 1614 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1615 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1616 1617 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1618 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1619 }; 1620 1621 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1622 // 256-bit wide vectors. 1623 1624 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1625 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1626 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1627 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1628 1629 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1630 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1631 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1632 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd 1633 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1634 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1635 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1636 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd 1637 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd 1638 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd 1639 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd 1640 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd 1641 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq 1642 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq 1643 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq 1644 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 2 }, // vpmovdb 1645 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 2 }, // vpmovdb 1646 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, // vpmovdb 1647 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, // vpmovdb 1648 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 2 }, // vpmovqb 1649 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 1 }, // vpshufb 1650 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, // vpmovqb 1651 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, // vpmovqw 1652 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, // vpmovqd 1653 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd 1654 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb 1655 1656 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32 1657 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, 1658 1659 // Sign extend is zmm vpternlogd+vptruncdb. 1660 // Zero extend is zmm broadcast load+vptruncdw. 1661 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 }, 1662 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 }, 1663 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, 1664 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, 1665 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, 1666 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, 1667 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 }, 1668 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 }, 1669 1670 // Sign extend is zmm vpternlogd+vptruncdw. 1671 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw. 1672 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 }, 1673 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1674 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 }, 1675 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1676 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 }, 1677 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1678 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 }, 1679 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1680 1681 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd 1682 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld 1683 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd 1684 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld 1685 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd 1686 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld 1687 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq 1688 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq 1689 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq 1690 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq 1691 1692 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd 1693 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld 1694 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq 1695 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq 1696 1697 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1698 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1699 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1700 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1701 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1702 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1703 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1704 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1705 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1706 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1707 1708 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1709 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1710 1711 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1712 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1713 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, 1714 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, 1715 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1716 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, 1717 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1718 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1719 1720 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1721 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1722 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, 1723 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, 1724 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1725 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, 1726 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1727 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1728 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1729 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1730 1731 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2 }, 1732 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f64, 7 }, 1733 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f64,15 }, 1734 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f32,11 }, 1735 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f64,31 }, 1736 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, 1737 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f64, 7 }, 1738 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f32, 5 }, 1739 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f64,15 }, 1740 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 1 }, 1741 { ISD::FP_TO_SINT, MVT::v16i32, MVT::v16f64, 3 }, 1742 1743 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1744 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, 1745 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, 1746 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1747 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, 1748 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, 1749 }; 1750 1751 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1752 // Mask sign extend has an instruction. 1753 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1754 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1755 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1756 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1757 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1758 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1759 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1760 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1761 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1762 1763 // Mask zero extend is a sext + shift. 1764 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1765 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1766 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1767 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1768 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1769 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1770 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1771 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1772 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1773 1774 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, 1775 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // vpsllw+vptestmb 1776 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // vpsllw+vptestmw 1777 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // vpsllw+vptestmb 1778 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // vpsllw+vptestmw 1779 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // vpsllw+vptestmb 1780 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // vpsllw+vptestmw 1781 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // vpsllw+vptestmb 1782 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // vpsllw+vptestmw 1783 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // vpsllw+vptestmb 1784 }; 1785 1786 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1787 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1788 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1789 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1790 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1791 1792 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1793 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1794 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1795 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1796 1797 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v4f32, 1 }, 1798 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1799 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1800 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1801 1802 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v4f32, 1 }, 1803 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1804 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1805 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1806 }; 1807 1808 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 1809 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1810 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1811 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1812 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 8 }, // split+2*v8i8 1813 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1814 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1815 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1816 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16 1817 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // vpslld+vptestmd 1818 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd 1819 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // vpslld+vptestmd 1820 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // vpsllq+vptestmq 1821 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // vpsllq+vptestmq 1822 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // vpmovqd 1823 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, // vpmovqb 1824 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, // vpmovqw 1825 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, // vpmovwb 1826 1827 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb 1828 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb 1829 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 }, 1830 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 }, 1831 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 }, 1832 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 }, 1833 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 }, 1834 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 }, 1835 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 }, 1836 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 }, 1837 1838 // sign extend is vpcmpeq+maskedmove+vpmovdw 1839 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw 1840 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1841 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 }, 1842 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1843 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 }, 1844 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1845 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 }, 1846 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 }, 1847 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 }, 1848 1849 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd 1850 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld 1851 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd 1852 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld 1853 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd 1854 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld 1855 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq 1856 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq 1857 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq 1858 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq 1859 1860 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 1 }, 1861 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 1 }, 1862 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 1 }, 1863 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 1 }, 1864 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1865 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1866 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 1 }, 1867 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 1 }, 1868 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1869 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1870 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1871 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1872 1873 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 1874 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 1 }, 1875 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 1876 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 1 }, 1877 1878 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 1879 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1880 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 1881 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 1 }, 1882 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 1883 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 1 }, 1884 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 1885 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1886 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1887 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1888 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1889 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1890 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1891 1892 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v8f32, 2 }, 1893 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2 }, 1894 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f32, 5 }, 1895 1896 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 1897 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 1898 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1899 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 1 }, 1900 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1901 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1902 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1903 }; 1904 1905 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1906 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1907 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1908 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1909 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1910 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1911 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1912 1913 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 2 }, 1914 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 2 }, 1915 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 2 }, 1916 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 2 }, 1917 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1918 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1919 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 2 }, 1920 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 2 }, 1921 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1922 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1923 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1924 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1925 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1926 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1927 1928 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1929 1930 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i16, 1 }, 1931 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 1 }, 1932 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 1 }, 1933 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i32, 4 }, 1934 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i64, 4 }, 1935 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 1 }, 1936 { ISD::TRUNCATE, MVT::v8i16, MVT::v2i64, 1 }, 1937 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i64, 5 }, 1938 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, 1939 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1940 1941 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1942 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1943 1944 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v8f32, 1 }, 1945 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 1 }, 1946 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 1 }, 1947 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 3 }, 1948 1949 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 3 }, 1950 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 3 }, 1951 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v8f32, 1 }, 1952 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 3 }, 1953 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 1954 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4 }, 1955 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 3 }, 1956 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v4f64, 4 }, 1957 1958 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 2 }, 1959 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 2 }, 1960 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 2 }, 1961 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1962 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1963 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1964 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 3 }, 1965 1966 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 2 }, 1967 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 2 }, 1968 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 2 }, 1969 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1970 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1971 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1972 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 2 }, 1973 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 1974 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 1975 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 }, 1976 }; 1977 1978 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1979 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1980 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1981 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1982 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1983 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1984 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1985 1986 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 3 }, 1987 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 3 }, 1988 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 3 }, 1989 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 3 }, 1990 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1991 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1992 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 3 }, 1993 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 3 }, 1994 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1995 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1996 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1997 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1998 1999 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 4 }, 2000 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 5 }, 2001 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 4 }, 2002 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 9 }, 2003 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, 11 }, 2004 2005 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // and+extract+packuswb 2006 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i32, 5 }, 2007 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2008 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i64, 5 }, 2009 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i64, 3 }, // and+extract+2*packusdw 2010 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 2011 2012 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 2013 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 2014 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 2015 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 4 }, 2016 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v16i8, 2 }, 2017 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 2018 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v8i16, 2 }, 2019 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2020 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 2021 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 }, 2022 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 5 }, 2023 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 8 }, 2024 2025 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 2026 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 2027 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 2028 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 4 }, 2029 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v16i8, 2 }, 2030 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 2031 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v8i16, 2 }, 2032 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 4 }, 2033 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 4 }, 2034 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 2035 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 2036 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 2037 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 10 }, 2038 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 10 }, 2039 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 18 }, 2040 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 2041 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 10 }, 2042 2043 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v8f32, 2 }, 2044 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f64, 2 }, 2045 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v8f32, 2 }, 2046 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v4f64, 2 }, 2047 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 2 }, 2048 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f64, 2 }, 2049 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v8f32, 2 }, 2050 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v4f64, 2 }, 2051 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 2 }, 2052 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 2 }, 2053 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 5 }, 2054 2055 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v8f32, 2 }, 2056 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f64, 2 }, 2057 { ISD::FP_TO_UINT, MVT::v32i8, MVT::v8f32, 2 }, 2058 { ISD::FP_TO_UINT, MVT::v32i8, MVT::v4f64, 2 }, 2059 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 2 }, 2060 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f64, 2 }, 2061 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v8f32, 2 }, 2062 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v4f64, 2 }, 2063 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 3 }, 2064 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 2065 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 6 }, 2066 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 7 }, 2067 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v4f64, 7 }, 2068 2069 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 2070 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 2071 }; 2072 2073 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 2074 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8, 1 }, 2075 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8, 1 }, 2076 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8, 1 }, 2077 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8, 1 }, 2078 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2079 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2080 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16, 1 }, 2081 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16, 1 }, 2082 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2083 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2084 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2085 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2086 2087 // These truncates end up widening elements. 2088 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 1 }, // PMOVXZBQ 2089 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 1 }, // PMOVXZWQ 2090 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 1 }, // PMOVXZBD 2091 2092 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 2 }, 2093 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 2 }, 2094 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 2 }, 2095 2096 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 1 }, 2097 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 1 }, 2098 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 1 }, 2099 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 1 }, 2100 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 1 }, 2101 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2102 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 1 }, 2103 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2104 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 2105 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 1 }, 2106 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2107 2108 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 1 }, 2109 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 1 }, 2110 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 2111 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 2112 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 1 }, 2113 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2114 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 1 }, 2115 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2116 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 3 }, 2117 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 3 }, 2118 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 2 }, 2119 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 12 }, 2120 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 22 }, 2121 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 4 }, 2122 2123 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 1 }, 2124 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 1 }, 2125 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 1 }, 2126 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 1 }, 2127 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f32, 2 }, 2128 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v2f64, 2 }, 2129 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f32, 1 }, 2130 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v2f64, 1 }, 2131 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, 2132 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v2f64, 1 }, 2133 2134 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 1 }, 2135 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 2136 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 1 }, 2137 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 2138 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f32, 2 }, 2139 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v2f64, 2 }, 2140 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f32, 1 }, 2141 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v2f64, 1 }, 2142 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 4 }, 2143 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 2144 }; 2145 2146 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 2147 // These are somewhat magic numbers justified by comparing the 2148 // output of llvm-mca for our various supported scheduler models 2149 // and basing it off the worst case scenario. 2150 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 3 }, 2151 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 3 }, 2152 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 3 }, 2153 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 3 }, 2154 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 3 }, 2155 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 4 }, 2156 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 3 }, 2157 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 4 }, 2158 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 3 }, 2159 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4 }, 2160 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 8 }, 2161 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 8 }, 2162 2163 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 3 }, 2164 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 3 }, 2165 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 8 }, 2166 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 9 }, 2167 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 4 }, 2168 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 4 }, 2169 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 4 }, 2170 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 4 }, 2171 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 7 }, 2172 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 7 }, 2173 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 2174 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 15 }, 2175 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 18 }, 2176 2177 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 4 }, 2178 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 4 }, 2179 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 4 }, 2180 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 4 }, 2181 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f32, 6 }, 2182 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v2f64, 6 }, 2183 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f32, 5 }, 2184 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v2f64, 5 }, 2185 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 4 }, 2186 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v2f64, 4 }, 2187 2188 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 4 }, 2189 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 2190 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 4 }, 2191 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 15 }, 2192 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f32, 6 }, 2193 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v2f64, 6 }, 2194 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f32, 5 }, 2195 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v2f64, 5 }, 2196 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 8 }, 2197 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 8 }, 2198 2199 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8, 4 }, 2200 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8, 4 }, 2201 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8, 2 }, 2202 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8, 3 }, 2203 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2204 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8, 2 }, 2205 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16, 2 }, 2206 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16, 3 }, 2207 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2208 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16, 2 }, 2209 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2210 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32, 2 }, 2211 2212 // These truncates are really widening elements. 2213 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 1 }, // PSHUFD 2214 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // PUNPCKLWD+DQ 2215 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // PUNPCKLBW+WD+PSHUFD 2216 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 1 }, // PUNPCKLWD 2217 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // PUNPCKLBW+WD 2218 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 1 }, // PUNPCKLBW 2219 2220 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i16, 2 }, // PAND+PACKUSWB 2221 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 2222 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 3 }, // PAND+2*PACKUSWB 2223 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 2224 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 2225 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 3 }, 2226 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2227 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32,10 }, 2228 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 2229 { ISD::TRUNCATE, MVT::v8i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 2230 { ISD::TRUNCATE, MVT::v4i32, MVT::v2i64, 1 }, // PSHUFD 2231 }; 2232 2233 // Attempt to map directly to (simple) MVT types to let us match custom entries. 2234 EVT SrcTy = TLI->getValueType(DL, Src); 2235 EVT DstTy = TLI->getValueType(DL, Dst); 2236 2237 // The function getSimpleVT only handles simple value types. 2238 if (SrcTy.isSimple() && DstTy.isSimple()) { 2239 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 2240 MVT SimpleDstTy = DstTy.getSimpleVT(); 2241 2242 if (ST->useAVX512Regs()) { 2243 if (ST->hasBWI()) 2244 if (const auto *Entry = ConvertCostTableLookup( 2245 AVX512BWConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2246 return AdjustCost(Entry->Cost); 2247 2248 if (ST->hasDQI()) 2249 if (const auto *Entry = ConvertCostTableLookup( 2250 AVX512DQConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2251 return AdjustCost(Entry->Cost); 2252 2253 if (ST->hasAVX512()) 2254 if (const auto *Entry = ConvertCostTableLookup( 2255 AVX512FConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2256 return AdjustCost(Entry->Cost); 2257 } 2258 2259 if (ST->hasBWI()) 2260 if (const auto *Entry = ConvertCostTableLookup( 2261 AVX512BWVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2262 return AdjustCost(Entry->Cost); 2263 2264 if (ST->hasDQI()) 2265 if (const auto *Entry = ConvertCostTableLookup( 2266 AVX512DQVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2267 return AdjustCost(Entry->Cost); 2268 2269 if (ST->hasAVX512()) 2270 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2271 SimpleDstTy, SimpleSrcTy)) 2272 return AdjustCost(Entry->Cost); 2273 2274 if (ST->hasAVX2()) { 2275 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2276 SimpleDstTy, SimpleSrcTy)) 2277 return AdjustCost(Entry->Cost); 2278 } 2279 2280 if (ST->hasAVX()) { 2281 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2282 SimpleDstTy, SimpleSrcTy)) 2283 return AdjustCost(Entry->Cost); 2284 } 2285 2286 if (ST->hasSSE41()) { 2287 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2288 SimpleDstTy, SimpleSrcTy)) 2289 return AdjustCost(Entry->Cost); 2290 } 2291 2292 if (ST->hasSSE2()) { 2293 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2294 SimpleDstTy, SimpleSrcTy)) 2295 return AdjustCost(Entry->Cost); 2296 } 2297 } 2298 2299 // Fall back to legalized types. 2300 std::pair<InstructionCost, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 2301 std::pair<InstructionCost, MVT> LTDest = 2302 TLI->getTypeLegalizationCost(DL, Dst); 2303 2304 if (ST->useAVX512Regs()) { 2305 if (ST->hasBWI()) 2306 if (const auto *Entry = ConvertCostTableLookup( 2307 AVX512BWConversionTbl, ISD, LTDest.second, LTSrc.second)) 2308 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2309 2310 if (ST->hasDQI()) 2311 if (const auto *Entry = ConvertCostTableLookup( 2312 AVX512DQConversionTbl, ISD, LTDest.second, LTSrc.second)) 2313 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2314 2315 if (ST->hasAVX512()) 2316 if (const auto *Entry = ConvertCostTableLookup( 2317 AVX512FConversionTbl, ISD, LTDest.second, LTSrc.second)) 2318 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2319 } 2320 2321 if (ST->hasBWI()) 2322 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 2323 LTDest.second, LTSrc.second)) 2324 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2325 2326 if (ST->hasDQI()) 2327 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 2328 LTDest.second, LTSrc.second)) 2329 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2330 2331 if (ST->hasAVX512()) 2332 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2333 LTDest.second, LTSrc.second)) 2334 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2335 2336 if (ST->hasAVX2()) 2337 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2338 LTDest.second, LTSrc.second)) 2339 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2340 2341 if (ST->hasAVX()) 2342 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2343 LTDest.second, LTSrc.second)) 2344 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2345 2346 if (ST->hasSSE41()) 2347 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2348 LTDest.second, LTSrc.second)) 2349 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2350 2351 if (ST->hasSSE2()) 2352 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2353 LTDest.second, LTSrc.second)) 2354 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2355 2356 // Fallback, for i8/i16 sitofp/uitofp cases we need to extend to i32 for 2357 // sitofp. 2358 if ((ISD == ISD::SINT_TO_FP || ISD == ISD::UINT_TO_FP) && 2359 1 < Src->getScalarSizeInBits() && Src->getScalarSizeInBits() < 32) { 2360 Type *ExtSrc = Src->getWithNewBitWidth(32); 2361 unsigned ExtOpc = 2362 (ISD == ISD::SINT_TO_FP) ? Instruction::SExt : Instruction::ZExt; 2363 2364 // For scalar loads the extend would be free. 2365 InstructionCost ExtCost = 0; 2366 if (!(Src->isIntegerTy() && I && isa<LoadInst>(I->getOperand(0)))) 2367 ExtCost = getCastInstrCost(ExtOpc, ExtSrc, Src, CCH, CostKind); 2368 2369 return ExtCost + getCastInstrCost(Instruction::SIToFP, Dst, ExtSrc, 2370 TTI::CastContextHint::None, CostKind); 2371 } 2372 2373 // Fallback for fptosi/fptoui i8/i16 cases we need to truncate from fptosi 2374 // i32. 2375 if ((ISD == ISD::FP_TO_SINT || ISD == ISD::FP_TO_UINT) && 2376 1 < Dst->getScalarSizeInBits() && Dst->getScalarSizeInBits() < 32) { 2377 Type *TruncDst = Dst->getWithNewBitWidth(32); 2378 return getCastInstrCost(Instruction::FPToSI, TruncDst, Src, CCH, CostKind) + 2379 getCastInstrCost(Instruction::Trunc, Dst, TruncDst, 2380 TTI::CastContextHint::None, CostKind); 2381 } 2382 2383 return AdjustCost( 2384 BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I)); 2385 } 2386 2387 InstructionCost X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 2388 Type *CondTy, 2389 CmpInst::Predicate VecPred, 2390 TTI::TargetCostKind CostKind, 2391 const Instruction *I) { 2392 // TODO: Handle other cost kinds. 2393 if (CostKind != TTI::TCK_RecipThroughput) 2394 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, 2395 I); 2396 2397 // Legalize the type. 2398 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2399 2400 MVT MTy = LT.second; 2401 2402 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2403 assert(ISD && "Invalid opcode"); 2404 2405 unsigned ExtraCost = 0; 2406 if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) { 2407 // Some vector comparison predicates cost extra instructions. 2408 if (MTy.isVector() && 2409 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 2410 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 2411 ST->hasBWI())) { 2412 switch (cast<CmpInst>(I)->getPredicate()) { 2413 case CmpInst::Predicate::ICMP_NE: 2414 // xor(cmpeq(x,y),-1) 2415 ExtraCost = 1; 2416 break; 2417 case CmpInst::Predicate::ICMP_SGE: 2418 case CmpInst::Predicate::ICMP_SLE: 2419 // xor(cmpgt(x,y),-1) 2420 ExtraCost = 1; 2421 break; 2422 case CmpInst::Predicate::ICMP_ULT: 2423 case CmpInst::Predicate::ICMP_UGT: 2424 // cmpgt(xor(x,signbit),xor(y,signbit)) 2425 // xor(cmpeq(pmaxu(x,y),x),-1) 2426 ExtraCost = 2; 2427 break; 2428 case CmpInst::Predicate::ICMP_ULE: 2429 case CmpInst::Predicate::ICMP_UGE: 2430 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 2431 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 2432 // cmpeq(psubus(x,y),0) 2433 // cmpeq(pminu(x,y),x) 2434 ExtraCost = 1; 2435 } else { 2436 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 2437 ExtraCost = 3; 2438 } 2439 break; 2440 default: 2441 break; 2442 } 2443 } 2444 } 2445 2446 static const CostTblEntry SLMCostTbl[] = { 2447 // slm pcmpeq/pcmpgt throughput is 2 2448 { ISD::SETCC, MVT::v2i64, 2 }, 2449 }; 2450 2451 static const CostTblEntry AVX512BWCostTbl[] = { 2452 { ISD::SETCC, MVT::v32i16, 1 }, 2453 { ISD::SETCC, MVT::v64i8, 1 }, 2454 2455 { ISD::SELECT, MVT::v32i16, 1 }, 2456 { ISD::SELECT, MVT::v64i8, 1 }, 2457 }; 2458 2459 static const CostTblEntry AVX512CostTbl[] = { 2460 { ISD::SETCC, MVT::v8i64, 1 }, 2461 { ISD::SETCC, MVT::v16i32, 1 }, 2462 { ISD::SETCC, MVT::v8f64, 1 }, 2463 { ISD::SETCC, MVT::v16f32, 1 }, 2464 2465 { ISD::SELECT, MVT::v8i64, 1 }, 2466 { ISD::SELECT, MVT::v16i32, 1 }, 2467 { ISD::SELECT, MVT::v8f64, 1 }, 2468 { ISD::SELECT, MVT::v16f32, 1 }, 2469 2470 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 2471 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 2472 2473 { ISD::SELECT, MVT::v32i16, 2 }, // FIXME: should be 3 2474 { ISD::SELECT, MVT::v64i8, 2 }, // FIXME: should be 3 2475 }; 2476 2477 static const CostTblEntry AVX2CostTbl[] = { 2478 { ISD::SETCC, MVT::v4i64, 1 }, 2479 { ISD::SETCC, MVT::v8i32, 1 }, 2480 { ISD::SETCC, MVT::v16i16, 1 }, 2481 { ISD::SETCC, MVT::v32i8, 1 }, 2482 2483 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 2484 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 2485 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 2486 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 2487 }; 2488 2489 static const CostTblEntry AVX1CostTbl[] = { 2490 { ISD::SETCC, MVT::v4f64, 1 }, 2491 { ISD::SETCC, MVT::v8f32, 1 }, 2492 // AVX1 does not support 8-wide integer compare. 2493 { ISD::SETCC, MVT::v4i64, 4 }, 2494 { ISD::SETCC, MVT::v8i32, 4 }, 2495 { ISD::SETCC, MVT::v16i16, 4 }, 2496 { ISD::SETCC, MVT::v32i8, 4 }, 2497 2498 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 2499 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 2500 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 2501 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 2502 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 2503 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 2504 }; 2505 2506 static const CostTblEntry SSE42CostTbl[] = { 2507 { ISD::SETCC, MVT::v2f64, 1 }, 2508 { ISD::SETCC, MVT::v4f32, 1 }, 2509 { ISD::SETCC, MVT::v2i64, 1 }, 2510 }; 2511 2512 static const CostTblEntry SSE41CostTbl[] = { 2513 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 2514 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 2515 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 2516 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 2517 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 2518 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 2519 }; 2520 2521 static const CostTblEntry SSE2CostTbl[] = { 2522 { ISD::SETCC, MVT::v2f64, 2 }, 2523 { ISD::SETCC, MVT::f64, 1 }, 2524 { ISD::SETCC, MVT::v2i64, 8 }, 2525 { ISD::SETCC, MVT::v4i32, 1 }, 2526 { ISD::SETCC, MVT::v8i16, 1 }, 2527 { ISD::SETCC, MVT::v16i8, 1 }, 2528 2529 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 2530 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 2531 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 2532 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 2533 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 2534 }; 2535 2536 static const CostTblEntry SSE1CostTbl[] = { 2537 { ISD::SETCC, MVT::v4f32, 2 }, 2538 { ISD::SETCC, MVT::f32, 1 }, 2539 2540 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 2541 }; 2542 2543 if (ST->isSLM()) 2544 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2545 return LT.first * (ExtraCost + Entry->Cost); 2546 2547 if (ST->hasBWI()) 2548 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2549 return LT.first * (ExtraCost + Entry->Cost); 2550 2551 if (ST->hasAVX512()) 2552 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2553 return LT.first * (ExtraCost + Entry->Cost); 2554 2555 if (ST->hasAVX2()) 2556 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2557 return LT.first * (ExtraCost + Entry->Cost); 2558 2559 if (ST->hasAVX()) 2560 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2561 return LT.first * (ExtraCost + Entry->Cost); 2562 2563 if (ST->hasSSE42()) 2564 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2565 return LT.first * (ExtraCost + Entry->Cost); 2566 2567 if (ST->hasSSE41()) 2568 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2569 return LT.first * (ExtraCost + Entry->Cost); 2570 2571 if (ST->hasSSE2()) 2572 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2573 return LT.first * (ExtraCost + Entry->Cost); 2574 2575 if (ST->hasSSE1()) 2576 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2577 return LT.first * (ExtraCost + Entry->Cost); 2578 2579 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I); 2580 } 2581 2582 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2583 2584 InstructionCost 2585 X86TTIImpl::getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 2586 TTI::TargetCostKind CostKind) { 2587 2588 // Costs should match the codegen from: 2589 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2590 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2591 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2592 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2593 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2594 2595 // TODO: Overflow intrinsics (*ADDO, *SUBO, *MULO) with vector types are not 2596 // specialized in these tables yet. 2597 static const CostTblEntry AVX512BITALGCostTbl[] = { 2598 { ISD::CTPOP, MVT::v32i16, 1 }, 2599 { ISD::CTPOP, MVT::v64i8, 1 }, 2600 { ISD::CTPOP, MVT::v16i16, 1 }, 2601 { ISD::CTPOP, MVT::v32i8, 1 }, 2602 { ISD::CTPOP, MVT::v8i16, 1 }, 2603 { ISD::CTPOP, MVT::v16i8, 1 }, 2604 }; 2605 static const CostTblEntry AVX512VPOPCNTDQCostTbl[] = { 2606 { ISD::CTPOP, MVT::v8i64, 1 }, 2607 { ISD::CTPOP, MVT::v16i32, 1 }, 2608 { ISD::CTPOP, MVT::v4i64, 1 }, 2609 { ISD::CTPOP, MVT::v8i32, 1 }, 2610 { ISD::CTPOP, MVT::v2i64, 1 }, 2611 { ISD::CTPOP, MVT::v4i32, 1 }, 2612 }; 2613 static const CostTblEntry AVX512CDCostTbl[] = { 2614 { ISD::CTLZ, MVT::v8i64, 1 }, 2615 { ISD::CTLZ, MVT::v16i32, 1 }, 2616 { ISD::CTLZ, MVT::v32i16, 8 }, 2617 { ISD::CTLZ, MVT::v64i8, 20 }, 2618 { ISD::CTLZ, MVT::v4i64, 1 }, 2619 { ISD::CTLZ, MVT::v8i32, 1 }, 2620 { ISD::CTLZ, MVT::v16i16, 4 }, 2621 { ISD::CTLZ, MVT::v32i8, 10 }, 2622 { ISD::CTLZ, MVT::v2i64, 1 }, 2623 { ISD::CTLZ, MVT::v4i32, 1 }, 2624 { ISD::CTLZ, MVT::v8i16, 4 }, 2625 { ISD::CTLZ, MVT::v16i8, 4 }, 2626 }; 2627 static const CostTblEntry AVX512BWCostTbl[] = { 2628 { ISD::ABS, MVT::v32i16, 1 }, 2629 { ISD::ABS, MVT::v64i8, 1 }, 2630 { ISD::BITREVERSE, MVT::v8i64, 3 }, 2631 { ISD::BITREVERSE, MVT::v16i32, 3 }, 2632 { ISD::BITREVERSE, MVT::v32i16, 3 }, 2633 { ISD::BITREVERSE, MVT::v64i8, 2 }, 2634 { ISD::BSWAP, MVT::v8i64, 1 }, 2635 { ISD::BSWAP, MVT::v16i32, 1 }, 2636 { ISD::BSWAP, MVT::v32i16, 1 }, 2637 { ISD::CTLZ, MVT::v8i64, 23 }, 2638 { ISD::CTLZ, MVT::v16i32, 22 }, 2639 { ISD::CTLZ, MVT::v32i16, 18 }, 2640 { ISD::CTLZ, MVT::v64i8, 17 }, 2641 { ISD::CTPOP, MVT::v8i64, 7 }, 2642 { ISD::CTPOP, MVT::v16i32, 11 }, 2643 { ISD::CTPOP, MVT::v32i16, 9 }, 2644 { ISD::CTPOP, MVT::v64i8, 6 }, 2645 { ISD::CTTZ, MVT::v8i64, 10 }, 2646 { ISD::CTTZ, MVT::v16i32, 14 }, 2647 { ISD::CTTZ, MVT::v32i16, 12 }, 2648 { ISD::CTTZ, MVT::v64i8, 9 }, 2649 { ISD::SADDSAT, MVT::v32i16, 1 }, 2650 { ISD::SADDSAT, MVT::v64i8, 1 }, 2651 { ISD::SMAX, MVT::v32i16, 1 }, 2652 { ISD::SMAX, MVT::v64i8, 1 }, 2653 { ISD::SMIN, MVT::v32i16, 1 }, 2654 { ISD::SMIN, MVT::v64i8, 1 }, 2655 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2656 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2657 { ISD::UADDSAT, MVT::v32i16, 1 }, 2658 { ISD::UADDSAT, MVT::v64i8, 1 }, 2659 { ISD::UMAX, MVT::v32i16, 1 }, 2660 { ISD::UMAX, MVT::v64i8, 1 }, 2661 { ISD::UMIN, MVT::v32i16, 1 }, 2662 { ISD::UMIN, MVT::v64i8, 1 }, 2663 { ISD::USUBSAT, MVT::v32i16, 1 }, 2664 { ISD::USUBSAT, MVT::v64i8, 1 }, 2665 }; 2666 static const CostTblEntry AVX512CostTbl[] = { 2667 { ISD::ABS, MVT::v8i64, 1 }, 2668 { ISD::ABS, MVT::v16i32, 1 }, 2669 { ISD::ABS, MVT::v32i16, 2 }, // FIXME: include split 2670 { ISD::ABS, MVT::v64i8, 2 }, // FIXME: include split 2671 { ISD::ABS, MVT::v4i64, 1 }, 2672 { ISD::ABS, MVT::v2i64, 1 }, 2673 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2674 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2675 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2676 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2677 { ISD::BSWAP, MVT::v8i64, 4 }, 2678 { ISD::BSWAP, MVT::v16i32, 4 }, 2679 { ISD::BSWAP, MVT::v32i16, 4 }, 2680 { ISD::CTLZ, MVT::v8i64, 29 }, 2681 { ISD::CTLZ, MVT::v16i32, 35 }, 2682 { ISD::CTLZ, MVT::v32i16, 28 }, 2683 { ISD::CTLZ, MVT::v64i8, 18 }, 2684 { ISD::CTPOP, MVT::v8i64, 16 }, 2685 { ISD::CTPOP, MVT::v16i32, 24 }, 2686 { ISD::CTPOP, MVT::v32i16, 18 }, 2687 { ISD::CTPOP, MVT::v64i8, 12 }, 2688 { ISD::CTTZ, MVT::v8i64, 20 }, 2689 { ISD::CTTZ, MVT::v16i32, 28 }, 2690 { ISD::CTTZ, MVT::v32i16, 24 }, 2691 { ISD::CTTZ, MVT::v64i8, 18 }, 2692 { ISD::SMAX, MVT::v8i64, 1 }, 2693 { ISD::SMAX, MVT::v16i32, 1 }, 2694 { ISD::SMAX, MVT::v32i16, 2 }, // FIXME: include split 2695 { ISD::SMAX, MVT::v64i8, 2 }, // FIXME: include split 2696 { ISD::SMAX, MVT::v4i64, 1 }, 2697 { ISD::SMAX, MVT::v2i64, 1 }, 2698 { ISD::SMIN, MVT::v8i64, 1 }, 2699 { ISD::SMIN, MVT::v16i32, 1 }, 2700 { ISD::SMIN, MVT::v32i16, 2 }, // FIXME: include split 2701 { ISD::SMIN, MVT::v64i8, 2 }, // FIXME: include split 2702 { ISD::SMIN, MVT::v4i64, 1 }, 2703 { ISD::SMIN, MVT::v2i64, 1 }, 2704 { ISD::UMAX, MVT::v8i64, 1 }, 2705 { ISD::UMAX, MVT::v16i32, 1 }, 2706 { ISD::UMAX, MVT::v32i16, 2 }, // FIXME: include split 2707 { ISD::UMAX, MVT::v64i8, 2 }, // FIXME: include split 2708 { ISD::UMAX, MVT::v4i64, 1 }, 2709 { ISD::UMAX, MVT::v2i64, 1 }, 2710 { ISD::UMIN, MVT::v8i64, 1 }, 2711 { ISD::UMIN, MVT::v16i32, 1 }, 2712 { ISD::UMIN, MVT::v32i16, 2 }, // FIXME: include split 2713 { ISD::UMIN, MVT::v64i8, 2 }, // FIXME: include split 2714 { ISD::UMIN, MVT::v4i64, 1 }, 2715 { ISD::UMIN, MVT::v2i64, 1 }, 2716 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2717 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2718 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2719 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2720 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2721 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2722 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2723 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2724 { ISD::SADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2725 { ISD::SADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2726 { ISD::SSUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2727 { ISD::SSUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2728 { ISD::UADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2729 { ISD::UADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2730 { ISD::USUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2731 { ISD::USUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2732 { ISD::FMAXNUM, MVT::f32, 2 }, 2733 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2734 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2735 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2736 { ISD::FMAXNUM, MVT::f64, 2 }, 2737 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2738 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2739 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2740 }; 2741 static const CostTblEntry XOPCostTbl[] = { 2742 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2743 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2744 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2745 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2746 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2747 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2748 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2749 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2750 { ISD::BITREVERSE, MVT::i64, 3 }, 2751 { ISD::BITREVERSE, MVT::i32, 3 }, 2752 { ISD::BITREVERSE, MVT::i16, 3 }, 2753 { ISD::BITREVERSE, MVT::i8, 3 } 2754 }; 2755 static const CostTblEntry AVX2CostTbl[] = { 2756 { ISD::ABS, MVT::v4i64, 2 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2757 { ISD::ABS, MVT::v8i32, 1 }, 2758 { ISD::ABS, MVT::v16i16, 1 }, 2759 { ISD::ABS, MVT::v32i8, 1 }, 2760 { ISD::BITREVERSE, MVT::v2i64, 3 }, 2761 { ISD::BITREVERSE, MVT::v4i64, 3 }, 2762 { ISD::BITREVERSE, MVT::v4i32, 3 }, 2763 { ISD::BITREVERSE, MVT::v8i32, 3 }, 2764 { ISD::BITREVERSE, MVT::v8i16, 3 }, 2765 { ISD::BITREVERSE, MVT::v16i16, 3 }, 2766 { ISD::BITREVERSE, MVT::v16i8, 3 }, 2767 { ISD::BITREVERSE, MVT::v32i8, 3 }, 2768 { ISD::BSWAP, MVT::v4i64, 1 }, 2769 { ISD::BSWAP, MVT::v8i32, 1 }, 2770 { ISD::BSWAP, MVT::v16i16, 1 }, 2771 { ISD::CTLZ, MVT::v2i64, 7 }, 2772 { ISD::CTLZ, MVT::v4i64, 7 }, 2773 { ISD::CTLZ, MVT::v4i32, 5 }, 2774 { ISD::CTLZ, MVT::v8i32, 5 }, 2775 { ISD::CTLZ, MVT::v8i16, 4 }, 2776 { ISD::CTLZ, MVT::v16i16, 4 }, 2777 { ISD::CTLZ, MVT::v16i8, 3 }, 2778 { ISD::CTLZ, MVT::v32i8, 3 }, 2779 { ISD::CTPOP, MVT::v2i64, 3 }, 2780 { ISD::CTPOP, MVT::v4i64, 3 }, 2781 { ISD::CTPOP, MVT::v4i32, 7 }, 2782 { ISD::CTPOP, MVT::v8i32, 7 }, 2783 { ISD::CTPOP, MVT::v8i16, 3 }, 2784 { ISD::CTPOP, MVT::v16i16, 3 }, 2785 { ISD::CTPOP, MVT::v16i8, 2 }, 2786 { ISD::CTPOP, MVT::v32i8, 2 }, 2787 { ISD::CTTZ, MVT::v2i64, 4 }, 2788 { ISD::CTTZ, MVT::v4i64, 4 }, 2789 { ISD::CTTZ, MVT::v4i32, 7 }, 2790 { ISD::CTTZ, MVT::v8i32, 7 }, 2791 { ISD::CTTZ, MVT::v8i16, 4 }, 2792 { ISD::CTTZ, MVT::v16i16, 4 }, 2793 { ISD::CTTZ, MVT::v16i8, 3 }, 2794 { ISD::CTTZ, MVT::v32i8, 3 }, 2795 { ISD::SADDSAT, MVT::v16i16, 1 }, 2796 { ISD::SADDSAT, MVT::v32i8, 1 }, 2797 { ISD::SMAX, MVT::v8i32, 1 }, 2798 { ISD::SMAX, MVT::v16i16, 1 }, 2799 { ISD::SMAX, MVT::v32i8, 1 }, 2800 { ISD::SMIN, MVT::v8i32, 1 }, 2801 { ISD::SMIN, MVT::v16i16, 1 }, 2802 { ISD::SMIN, MVT::v32i8, 1 }, 2803 { ISD::SSUBSAT, MVT::v16i16, 1 }, 2804 { ISD::SSUBSAT, MVT::v32i8, 1 }, 2805 { ISD::UADDSAT, MVT::v16i16, 1 }, 2806 { ISD::UADDSAT, MVT::v32i8, 1 }, 2807 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 2808 { ISD::UMAX, MVT::v8i32, 1 }, 2809 { ISD::UMAX, MVT::v16i16, 1 }, 2810 { ISD::UMAX, MVT::v32i8, 1 }, 2811 { ISD::UMIN, MVT::v8i32, 1 }, 2812 { ISD::UMIN, MVT::v16i16, 1 }, 2813 { ISD::UMIN, MVT::v32i8, 1 }, 2814 { ISD::USUBSAT, MVT::v16i16, 1 }, 2815 { ISD::USUBSAT, MVT::v32i8, 1 }, 2816 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2817 { ISD::FMAXNUM, MVT::v8f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2818 { ISD::FMAXNUM, MVT::v4f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2819 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2820 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2821 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2822 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2823 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2824 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2825 }; 2826 static const CostTblEntry AVX1CostTbl[] = { 2827 { ISD::ABS, MVT::v4i64, 5 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2828 { ISD::ABS, MVT::v8i32, 3 }, 2829 { ISD::ABS, MVT::v16i16, 3 }, 2830 { ISD::ABS, MVT::v32i8, 3 }, 2831 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 2832 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 2833 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 2834 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 2835 { ISD::BSWAP, MVT::v4i64, 4 }, 2836 { ISD::BSWAP, MVT::v8i32, 4 }, 2837 { ISD::BSWAP, MVT::v16i16, 4 }, 2838 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 2839 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 2840 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 2841 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2842 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 2843 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 2844 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 2845 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 2846 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 2847 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 2848 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 2849 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2850 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2851 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2852 { ISD::SMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2853 { ISD::SMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2854 { ISD::SMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2855 { ISD::SMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2856 { ISD::SMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2857 { ISD::SMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2858 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2859 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2860 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2861 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2862 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 2863 { ISD::UMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2864 { ISD::UMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2865 { ISD::UMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2866 { ISD::UMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2867 { ISD::UMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2868 { ISD::UMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2869 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2870 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2871 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 2872 { ISD::FMAXNUM, MVT::f32, 3 }, // MAXSS + CMPUNORDSS + BLENDVPS 2873 { ISD::FMAXNUM, MVT::v4f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2874 { ISD::FMAXNUM, MVT::v8f32, 5 }, // MAXPS + CMPUNORDPS + BLENDVPS + ? 2875 { ISD::FMAXNUM, MVT::f64, 3 }, // MAXSD + CMPUNORDSD + BLENDVPD 2876 { ISD::FMAXNUM, MVT::v2f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2877 { ISD::FMAXNUM, MVT::v4f64, 5 }, // MAXPD + CMPUNORDPD + BLENDVPD + ? 2878 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 2879 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 2880 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 2881 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 2882 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 2883 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 2884 }; 2885 static const CostTblEntry GLMCostTbl[] = { 2886 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 2887 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 2888 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 2889 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 2890 }; 2891 static const CostTblEntry SLMCostTbl[] = { 2892 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 2893 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 2894 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 2895 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 2896 }; 2897 static const CostTblEntry SSE42CostTbl[] = { 2898 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 2899 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 2900 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 2901 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 2902 }; 2903 static const CostTblEntry SSE41CostTbl[] = { 2904 { ISD::ABS, MVT::v2i64, 2 }, // BLENDVPD(X,PSUBQ(0,X),X) 2905 { ISD::SMAX, MVT::v4i32, 1 }, 2906 { ISD::SMAX, MVT::v16i8, 1 }, 2907 { ISD::SMIN, MVT::v4i32, 1 }, 2908 { ISD::SMIN, MVT::v16i8, 1 }, 2909 { ISD::UMAX, MVT::v4i32, 1 }, 2910 { ISD::UMAX, MVT::v8i16, 1 }, 2911 { ISD::UMIN, MVT::v4i32, 1 }, 2912 { ISD::UMIN, MVT::v8i16, 1 }, 2913 }; 2914 static const CostTblEntry SSSE3CostTbl[] = { 2915 { ISD::ABS, MVT::v4i32, 1 }, 2916 { ISD::ABS, MVT::v8i16, 1 }, 2917 { ISD::ABS, MVT::v16i8, 1 }, 2918 { ISD::BITREVERSE, MVT::v2i64, 5 }, 2919 { ISD::BITREVERSE, MVT::v4i32, 5 }, 2920 { ISD::BITREVERSE, MVT::v8i16, 5 }, 2921 { ISD::BITREVERSE, MVT::v16i8, 5 }, 2922 { ISD::BSWAP, MVT::v2i64, 1 }, 2923 { ISD::BSWAP, MVT::v4i32, 1 }, 2924 { ISD::BSWAP, MVT::v8i16, 1 }, 2925 { ISD::CTLZ, MVT::v2i64, 23 }, 2926 { ISD::CTLZ, MVT::v4i32, 18 }, 2927 { ISD::CTLZ, MVT::v8i16, 14 }, 2928 { ISD::CTLZ, MVT::v16i8, 9 }, 2929 { ISD::CTPOP, MVT::v2i64, 7 }, 2930 { ISD::CTPOP, MVT::v4i32, 11 }, 2931 { ISD::CTPOP, MVT::v8i16, 9 }, 2932 { ISD::CTPOP, MVT::v16i8, 6 }, 2933 { ISD::CTTZ, MVT::v2i64, 10 }, 2934 { ISD::CTTZ, MVT::v4i32, 14 }, 2935 { ISD::CTTZ, MVT::v8i16, 12 }, 2936 { ISD::CTTZ, MVT::v16i8, 9 } 2937 }; 2938 static const CostTblEntry SSE2CostTbl[] = { 2939 { ISD::ABS, MVT::v2i64, 4 }, 2940 { ISD::ABS, MVT::v4i32, 3 }, 2941 { ISD::ABS, MVT::v8i16, 2 }, 2942 { ISD::ABS, MVT::v16i8, 2 }, 2943 { ISD::BITREVERSE, MVT::v2i64, 29 }, 2944 { ISD::BITREVERSE, MVT::v4i32, 27 }, 2945 { ISD::BITREVERSE, MVT::v8i16, 27 }, 2946 { ISD::BITREVERSE, MVT::v16i8, 20 }, 2947 { ISD::BSWAP, MVT::v2i64, 7 }, 2948 { ISD::BSWAP, MVT::v4i32, 7 }, 2949 { ISD::BSWAP, MVT::v8i16, 7 }, 2950 { ISD::CTLZ, MVT::v2i64, 25 }, 2951 { ISD::CTLZ, MVT::v4i32, 26 }, 2952 { ISD::CTLZ, MVT::v8i16, 20 }, 2953 { ISD::CTLZ, MVT::v16i8, 17 }, 2954 { ISD::CTPOP, MVT::v2i64, 12 }, 2955 { ISD::CTPOP, MVT::v4i32, 15 }, 2956 { ISD::CTPOP, MVT::v8i16, 13 }, 2957 { ISD::CTPOP, MVT::v16i8, 10 }, 2958 { ISD::CTTZ, MVT::v2i64, 14 }, 2959 { ISD::CTTZ, MVT::v4i32, 18 }, 2960 { ISD::CTTZ, MVT::v8i16, 16 }, 2961 { ISD::CTTZ, MVT::v16i8, 13 }, 2962 { ISD::SADDSAT, MVT::v8i16, 1 }, 2963 { ISD::SADDSAT, MVT::v16i8, 1 }, 2964 { ISD::SMAX, MVT::v8i16, 1 }, 2965 { ISD::SMIN, MVT::v8i16, 1 }, 2966 { ISD::SSUBSAT, MVT::v8i16, 1 }, 2967 { ISD::SSUBSAT, MVT::v16i8, 1 }, 2968 { ISD::UADDSAT, MVT::v8i16, 1 }, 2969 { ISD::UADDSAT, MVT::v16i8, 1 }, 2970 { ISD::UMAX, MVT::v8i16, 2 }, 2971 { ISD::UMAX, MVT::v16i8, 1 }, 2972 { ISD::UMIN, MVT::v8i16, 2 }, 2973 { ISD::UMIN, MVT::v16i8, 1 }, 2974 { ISD::USUBSAT, MVT::v8i16, 1 }, 2975 { ISD::USUBSAT, MVT::v16i8, 1 }, 2976 { ISD::FMAXNUM, MVT::f64, 4 }, 2977 { ISD::FMAXNUM, MVT::v2f64, 4 }, 2978 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 2979 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 2980 }; 2981 static const CostTblEntry SSE1CostTbl[] = { 2982 { ISD::FMAXNUM, MVT::f32, 4 }, 2983 { ISD::FMAXNUM, MVT::v4f32, 4 }, 2984 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 2985 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 2986 }; 2987 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 2988 { ISD::CTTZ, MVT::i64, 1 }, 2989 }; 2990 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 2991 { ISD::CTTZ, MVT::i32, 1 }, 2992 { ISD::CTTZ, MVT::i16, 1 }, 2993 { ISD::CTTZ, MVT::i8, 1 }, 2994 }; 2995 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 2996 { ISD::CTLZ, MVT::i64, 1 }, 2997 }; 2998 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 2999 { ISD::CTLZ, MVT::i32, 1 }, 3000 { ISD::CTLZ, MVT::i16, 1 }, 3001 { ISD::CTLZ, MVT::i8, 1 }, 3002 }; 3003 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 3004 { ISD::CTPOP, MVT::i64, 1 }, 3005 }; 3006 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 3007 { ISD::CTPOP, MVT::i32, 1 }, 3008 { ISD::CTPOP, MVT::i16, 1 }, 3009 { ISD::CTPOP, MVT::i8, 1 }, 3010 }; 3011 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 3012 { ISD::ABS, MVT::i64, 2 }, // SUB+CMOV 3013 { ISD::BITREVERSE, MVT::i64, 14 }, 3014 { ISD::BSWAP, MVT::i64, 1 }, 3015 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 3016 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 3017 { ISD::CTPOP, MVT::i64, 10 }, 3018 { ISD::SADDO, MVT::i64, 1 }, 3019 { ISD::UADDO, MVT::i64, 1 }, 3020 { ISD::UMULO, MVT::i64, 2 }, // mulq + seto 3021 }; 3022 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 3023 { ISD::ABS, MVT::i32, 2 }, // SUB+CMOV 3024 { ISD::ABS, MVT::i16, 2 }, // SUB+CMOV 3025 { ISD::BITREVERSE, MVT::i32, 14 }, 3026 { ISD::BITREVERSE, MVT::i16, 14 }, 3027 { ISD::BITREVERSE, MVT::i8, 11 }, 3028 { ISD::BSWAP, MVT::i32, 1 }, 3029 { ISD::BSWAP, MVT::i16, 1 }, // ROL 3030 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 3031 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 3032 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 3033 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 3034 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 3035 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 3036 { ISD::CTPOP, MVT::i32, 8 }, 3037 { ISD::CTPOP, MVT::i16, 9 }, 3038 { ISD::CTPOP, MVT::i8, 7 }, 3039 { ISD::SADDO, MVT::i32, 1 }, 3040 { ISD::SADDO, MVT::i16, 1 }, 3041 { ISD::SADDO, MVT::i8, 1 }, 3042 { ISD::UADDO, MVT::i32, 1 }, 3043 { ISD::UADDO, MVT::i16, 1 }, 3044 { ISD::UADDO, MVT::i8, 1 }, 3045 { ISD::UMULO, MVT::i32, 2 }, // mul + seto 3046 { ISD::UMULO, MVT::i16, 2 }, 3047 { ISD::UMULO, MVT::i8, 2 }, 3048 }; 3049 3050 Type *RetTy = ICA.getReturnType(); 3051 Type *OpTy = RetTy; 3052 Intrinsic::ID IID = ICA.getID(); 3053 unsigned ISD = ISD::DELETED_NODE; 3054 switch (IID) { 3055 default: 3056 break; 3057 case Intrinsic::abs: 3058 ISD = ISD::ABS; 3059 break; 3060 case Intrinsic::bitreverse: 3061 ISD = ISD::BITREVERSE; 3062 break; 3063 case Intrinsic::bswap: 3064 ISD = ISD::BSWAP; 3065 break; 3066 case Intrinsic::ctlz: 3067 ISD = ISD::CTLZ; 3068 break; 3069 case Intrinsic::ctpop: 3070 ISD = ISD::CTPOP; 3071 break; 3072 case Intrinsic::cttz: 3073 ISD = ISD::CTTZ; 3074 break; 3075 case Intrinsic::maxnum: 3076 case Intrinsic::minnum: 3077 // FMINNUM has same costs so don't duplicate. 3078 ISD = ISD::FMAXNUM; 3079 break; 3080 case Intrinsic::sadd_sat: 3081 ISD = ISD::SADDSAT; 3082 break; 3083 case Intrinsic::smax: 3084 ISD = ISD::SMAX; 3085 break; 3086 case Intrinsic::smin: 3087 ISD = ISD::SMIN; 3088 break; 3089 case Intrinsic::ssub_sat: 3090 ISD = ISD::SSUBSAT; 3091 break; 3092 case Intrinsic::uadd_sat: 3093 ISD = ISD::UADDSAT; 3094 break; 3095 case Intrinsic::umax: 3096 ISD = ISD::UMAX; 3097 break; 3098 case Intrinsic::umin: 3099 ISD = ISD::UMIN; 3100 break; 3101 case Intrinsic::usub_sat: 3102 ISD = ISD::USUBSAT; 3103 break; 3104 case Intrinsic::sqrt: 3105 ISD = ISD::FSQRT; 3106 break; 3107 case Intrinsic::sadd_with_overflow: 3108 case Intrinsic::ssub_with_overflow: 3109 // SSUBO has same costs so don't duplicate. 3110 ISD = ISD::SADDO; 3111 OpTy = RetTy->getContainedType(0); 3112 break; 3113 case Intrinsic::uadd_with_overflow: 3114 case Intrinsic::usub_with_overflow: 3115 // USUBO has same costs so don't duplicate. 3116 ISD = ISD::UADDO; 3117 OpTy = RetTy->getContainedType(0); 3118 break; 3119 case Intrinsic::umul_with_overflow: 3120 case Intrinsic::smul_with_overflow: 3121 // SMULO has same costs so don't duplicate. 3122 ISD = ISD::UMULO; 3123 OpTy = RetTy->getContainedType(0); 3124 break; 3125 } 3126 3127 if (ISD != ISD::DELETED_NODE) { 3128 // Legalize the type. 3129 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 3130 MVT MTy = LT.second; 3131 3132 // Attempt to lookup cost. 3133 if (ISD == ISD::BITREVERSE && ST->hasGFNI() && ST->hasSSSE3() && 3134 MTy.isVector()) { 3135 // With PSHUFB the code is very similar for all types. If we have integer 3136 // byte operations, we just need a GF2P8AFFINEQB for vXi8. For other types 3137 // we also need a PSHUFB. 3138 unsigned Cost = MTy.getVectorElementType() == MVT::i8 ? 1 : 2; 3139 3140 // Without byte operations, we need twice as many GF2P8AFFINEQB and PSHUFB 3141 // instructions. We also need an extract and an insert. 3142 if (!(MTy.is128BitVector() || (ST->hasAVX2() && MTy.is256BitVector()) || 3143 (ST->hasBWI() && MTy.is512BitVector()))) 3144 Cost = Cost * 2 + 2; 3145 3146 return LT.first * Cost; 3147 } 3148 3149 auto adjustTableCost = [](const CostTblEntry &Entry, 3150 InstructionCost LegalizationCost, 3151 FastMathFlags FMF) { 3152 // If there are no NANs to deal with, then these are reduced to a 3153 // single MIN** or MAX** instruction instead of the MIN/CMP/SELECT that we 3154 // assume is used in the non-fast case. 3155 if (Entry.ISD == ISD::FMAXNUM || Entry.ISD == ISD::FMINNUM) { 3156 if (FMF.noNaNs()) 3157 return LegalizationCost * 1; 3158 } 3159 return LegalizationCost * (int)Entry.Cost; 3160 }; 3161 3162 if (ST->useGLMDivSqrtCosts()) 3163 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 3164 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3165 3166 if (ST->isSLM()) 3167 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 3168 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3169 3170 if (ST->hasBITALG()) 3171 if (const auto *Entry = CostTableLookup(AVX512BITALGCostTbl, ISD, MTy)) 3172 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3173 3174 if (ST->hasVPOPCNTDQ()) 3175 if (const auto *Entry = CostTableLookup(AVX512VPOPCNTDQCostTbl, ISD, MTy)) 3176 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3177 3178 if (ST->hasCDI()) 3179 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 3180 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3181 3182 if (ST->hasBWI()) 3183 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3184 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3185 3186 if (ST->hasAVX512()) 3187 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3188 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3189 3190 if (ST->hasXOP()) 3191 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3192 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3193 3194 if (ST->hasAVX2()) 3195 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3196 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3197 3198 if (ST->hasAVX()) 3199 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3200 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3201 3202 if (ST->hasSSE42()) 3203 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3204 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3205 3206 if (ST->hasSSE41()) 3207 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3208 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3209 3210 if (ST->hasSSSE3()) 3211 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 3212 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3213 3214 if (ST->hasSSE2()) 3215 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3216 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3217 3218 if (ST->hasSSE1()) 3219 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3220 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3221 3222 if (ST->hasBMI()) { 3223 if (ST->is64Bit()) 3224 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 3225 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3226 3227 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 3228 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3229 } 3230 3231 if (ST->hasLZCNT()) { 3232 if (ST->is64Bit()) 3233 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 3234 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3235 3236 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 3237 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3238 } 3239 3240 if (ST->hasPOPCNT()) { 3241 if (ST->is64Bit()) 3242 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 3243 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3244 3245 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 3246 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3247 } 3248 3249 if (ISD == ISD::BSWAP && ST->hasMOVBE() && ST->hasFastMOVBE()) { 3250 if (const Instruction *II = ICA.getInst()) { 3251 if (II->hasOneUse() && isa<StoreInst>(II->user_back())) 3252 return TTI::TCC_Free; 3253 if (auto *LI = dyn_cast<LoadInst>(II->getOperand(0))) { 3254 if (LI->hasOneUse()) 3255 return TTI::TCC_Free; 3256 } 3257 } 3258 } 3259 3260 // TODO - add BMI (TZCNT) scalar handling 3261 3262 if (ST->is64Bit()) 3263 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3264 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3265 3266 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3267 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3268 } 3269 3270 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3271 } 3272 3273 InstructionCost 3274 X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 3275 TTI::TargetCostKind CostKind) { 3276 if (ICA.isTypeBasedOnly()) 3277 return getTypeBasedIntrinsicInstrCost(ICA, CostKind); 3278 3279 static const CostTblEntry AVX512CostTbl[] = { 3280 { ISD::ROTL, MVT::v8i64, 1 }, 3281 { ISD::ROTL, MVT::v4i64, 1 }, 3282 { ISD::ROTL, MVT::v2i64, 1 }, 3283 { ISD::ROTL, MVT::v16i32, 1 }, 3284 { ISD::ROTL, MVT::v8i32, 1 }, 3285 { ISD::ROTL, MVT::v4i32, 1 }, 3286 { ISD::ROTR, MVT::v8i64, 1 }, 3287 { ISD::ROTR, MVT::v4i64, 1 }, 3288 { ISD::ROTR, MVT::v2i64, 1 }, 3289 { ISD::ROTR, MVT::v16i32, 1 }, 3290 { ISD::ROTR, MVT::v8i32, 1 }, 3291 { ISD::ROTR, MVT::v4i32, 1 } 3292 }; 3293 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 3294 static const CostTblEntry XOPCostTbl[] = { 3295 { ISD::ROTL, MVT::v4i64, 4 }, 3296 { ISD::ROTL, MVT::v8i32, 4 }, 3297 { ISD::ROTL, MVT::v16i16, 4 }, 3298 { ISD::ROTL, MVT::v32i8, 4 }, 3299 { ISD::ROTL, MVT::v2i64, 1 }, 3300 { ISD::ROTL, MVT::v4i32, 1 }, 3301 { ISD::ROTL, MVT::v8i16, 1 }, 3302 { ISD::ROTL, MVT::v16i8, 1 }, 3303 { ISD::ROTR, MVT::v4i64, 6 }, 3304 { ISD::ROTR, MVT::v8i32, 6 }, 3305 { ISD::ROTR, MVT::v16i16, 6 }, 3306 { ISD::ROTR, MVT::v32i8, 6 }, 3307 { ISD::ROTR, MVT::v2i64, 2 }, 3308 { ISD::ROTR, MVT::v4i32, 2 }, 3309 { ISD::ROTR, MVT::v8i16, 2 }, 3310 { ISD::ROTR, MVT::v16i8, 2 } 3311 }; 3312 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 3313 { ISD::ROTL, MVT::i64, 1 }, 3314 { ISD::ROTR, MVT::i64, 1 }, 3315 { ISD::FSHL, MVT::i64, 4 } 3316 }; 3317 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 3318 { ISD::ROTL, MVT::i32, 1 }, 3319 { ISD::ROTL, MVT::i16, 1 }, 3320 { ISD::ROTL, MVT::i8, 1 }, 3321 { ISD::ROTR, MVT::i32, 1 }, 3322 { ISD::ROTR, MVT::i16, 1 }, 3323 { ISD::ROTR, MVT::i8, 1 }, 3324 { ISD::FSHL, MVT::i32, 4 }, 3325 { ISD::FSHL, MVT::i16, 4 }, 3326 { ISD::FSHL, MVT::i8, 4 } 3327 }; 3328 3329 Intrinsic::ID IID = ICA.getID(); 3330 Type *RetTy = ICA.getReturnType(); 3331 const SmallVectorImpl<const Value *> &Args = ICA.getArgs(); 3332 unsigned ISD = ISD::DELETED_NODE; 3333 switch (IID) { 3334 default: 3335 break; 3336 case Intrinsic::fshl: 3337 ISD = ISD::FSHL; 3338 if (Args[0] == Args[1]) 3339 ISD = ISD::ROTL; 3340 break; 3341 case Intrinsic::fshr: 3342 // FSHR has same costs so don't duplicate. 3343 ISD = ISD::FSHL; 3344 if (Args[0] == Args[1]) 3345 ISD = ISD::ROTR; 3346 break; 3347 } 3348 3349 if (ISD != ISD::DELETED_NODE) { 3350 // Legalize the type. 3351 std::pair<InstructionCost, MVT> LT = 3352 TLI->getTypeLegalizationCost(DL, RetTy); 3353 MVT MTy = LT.second; 3354 3355 // Attempt to lookup cost. 3356 if (ST->hasAVX512()) 3357 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3358 return LT.first * Entry->Cost; 3359 3360 if (ST->hasXOP()) 3361 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3362 return LT.first * Entry->Cost; 3363 3364 if (ST->is64Bit()) 3365 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3366 return LT.first * Entry->Cost; 3367 3368 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3369 return LT.first * Entry->Cost; 3370 } 3371 3372 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3373 } 3374 3375 InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, 3376 unsigned Index) { 3377 static const CostTblEntry SLMCostTbl[] = { 3378 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 3379 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 3380 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 3381 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 3382 }; 3383 3384 assert(Val->isVectorTy() && "This must be a vector type"); 3385 Type *ScalarType = Val->getScalarType(); 3386 int RegisterFileMoveCost = 0; 3387 3388 // Non-immediate extraction/insertion can be handled as a sequence of 3389 // aliased loads+stores via the stack. 3390 if (Index == -1U && (Opcode == Instruction::ExtractElement || 3391 Opcode == Instruction::InsertElement)) { 3392 // TODO: On some SSE41+ targets, we expand to cmp+splat+select patterns: 3393 // inselt N0, N1, N2 --> select (SplatN2 == {0,1,2...}) ? SplatN1 : N0. 3394 3395 // TODO: Move this to BasicTTIImpl.h? We'd need better gep + index handling. 3396 assert(isa<FixedVectorType>(Val) && "Fixed vector type expected"); 3397 Align VecAlign = DL.getPrefTypeAlign(Val); 3398 Align SclAlign = DL.getPrefTypeAlign(ScalarType); 3399 3400 // Extract - store vector to stack, load scalar. 3401 if (Opcode == Instruction::ExtractElement) { 3402 return getMemoryOpCost(Instruction::Store, Val, VecAlign, 0, 3403 TTI::TargetCostKind::TCK_RecipThroughput) + 3404 getMemoryOpCost(Instruction::Load, ScalarType, SclAlign, 0, 3405 TTI::TargetCostKind::TCK_RecipThroughput); 3406 } 3407 // Insert - store vector to stack, store scalar, load vector. 3408 if (Opcode == Instruction::InsertElement) { 3409 return getMemoryOpCost(Instruction::Store, Val, VecAlign, 0, 3410 TTI::TargetCostKind::TCK_RecipThroughput) + 3411 getMemoryOpCost(Instruction::Store, ScalarType, SclAlign, 0, 3412 TTI::TargetCostKind::TCK_RecipThroughput) + 3413 getMemoryOpCost(Instruction::Load, Val, VecAlign, 0, 3414 TTI::TargetCostKind::TCK_RecipThroughput); 3415 } 3416 } 3417 3418 if (Index != -1U && (Opcode == Instruction::ExtractElement || 3419 Opcode == Instruction::InsertElement)) { 3420 // Legalize the type. 3421 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 3422 3423 // This type is legalized to a scalar type. 3424 if (!LT.second.isVector()) 3425 return 0; 3426 3427 // The type may be split. Normalize the index to the new type. 3428 unsigned NumElts = LT.second.getVectorNumElements(); 3429 unsigned SubNumElts = NumElts; 3430 Index = Index % NumElts; 3431 3432 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 3433 // For inserts, we also need to insert the subvector back. 3434 if (LT.second.getSizeInBits() > 128) { 3435 assert((LT.second.getSizeInBits() % 128) == 0 && "Illegal vector"); 3436 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 3437 SubNumElts = NumElts / NumSubVecs; 3438 if (SubNumElts <= Index) { 3439 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 3440 Index %= SubNumElts; 3441 } 3442 } 3443 3444 if (Index == 0) { 3445 // Floating point scalars are already located in index #0. 3446 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 3447 // true for all. 3448 if (ScalarType->isFloatingPointTy()) 3449 return RegisterFileMoveCost; 3450 3451 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 3452 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 3453 return 1 + RegisterFileMoveCost; 3454 } 3455 3456 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3457 assert(ISD && "Unexpected vector opcode"); 3458 MVT MScalarTy = LT.second.getScalarType(); 3459 if (ST->isSLM()) 3460 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 3461 return Entry->Cost + RegisterFileMoveCost; 3462 3463 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 3464 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3465 (MScalarTy.isInteger() && ST->hasSSE41())) 3466 return 1 + RegisterFileMoveCost; 3467 3468 // Assume insertps is relatively cheap on all targets. 3469 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 3470 Opcode == Instruction::InsertElement) 3471 return 1 + RegisterFileMoveCost; 3472 3473 // For extractions we just need to shuffle the element to index 0, which 3474 // should be very cheap (assume cost = 1). For insertions we need to shuffle 3475 // the elements to its destination. In both cases we must handle the 3476 // subvector move(s). 3477 // If the vector type is already less than 128-bits then don't reduce it. 3478 // TODO: Under what circumstances should we shuffle using the full width? 3479 InstructionCost ShuffleCost = 1; 3480 if (Opcode == Instruction::InsertElement) { 3481 auto *SubTy = cast<VectorType>(Val); 3482 EVT VT = TLI->getValueType(DL, Val); 3483 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 3484 SubTy = FixedVectorType::get(ScalarType, SubNumElts); 3485 ShuffleCost = 3486 getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, None, 0, SubTy); 3487 } 3488 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 3489 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 3490 } 3491 3492 // Add to the base cost if we know that the extracted element of a vector is 3493 // destined to be moved to and used in the integer register file. 3494 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 3495 RegisterFileMoveCost += 1; 3496 3497 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 3498 } 3499 3500 InstructionCost X86TTIImpl::getScalarizationOverhead(VectorType *Ty, 3501 const APInt &DemandedElts, 3502 bool Insert, 3503 bool Extract) { 3504 InstructionCost Cost = 0; 3505 3506 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much 3507 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT. 3508 if (Insert) { 3509 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3510 MVT MScalarTy = LT.second.getScalarType(); 3511 3512 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3513 (MScalarTy.isInteger() && ST->hasSSE41()) || 3514 (MScalarTy == MVT::f32 && ST->hasSSE41())) { 3515 // For types we can insert directly, insertion into 128-bit sub vectors is 3516 // cheap, followed by a cheap chain of concatenations. 3517 if (LT.second.getSizeInBits() <= 128) { 3518 Cost += 3519 BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, false); 3520 } else { 3521 // In each 128-lane, if at least one index is demanded but not all 3522 // indices are demanded and this 128-lane is not the first 128-lane of 3523 // the legalized-vector, then this 128-lane needs a extracti128; If in 3524 // each 128-lane, there is at least one demanded index, this 128-lane 3525 // needs a inserti128. 3526 3527 // The following cases will help you build a better understanding: 3528 // Assume we insert several elements into a v8i32 vector in avx2, 3529 // Case#1: inserting into 1th index needs vpinsrd + inserti128. 3530 // Case#2: inserting into 5th index needs extracti128 + vpinsrd + 3531 // inserti128. 3532 // Case#3: inserting into 4,5,6,7 index needs 4*vpinsrd + inserti128. 3533 const int CostValue = *LT.first.getValue(); 3534 assert(CostValue >= 0 && "Negative cost!"); 3535 unsigned Num128Lanes = LT.second.getSizeInBits() / 128 * CostValue; 3536 unsigned NumElts = LT.second.getVectorNumElements() * CostValue; 3537 APInt WidenedDemandedElts = DemandedElts.zextOrSelf(NumElts); 3538 unsigned Scale = NumElts / Num128Lanes; 3539 // We iterate each 128-lane, and check if we need a 3540 // extracti128/inserti128 for this 128-lane. 3541 for (unsigned I = 0; I < NumElts; I += Scale) { 3542 APInt Mask = WidenedDemandedElts.getBitsSet(NumElts, I, I + Scale); 3543 APInt MaskedDE = Mask & WidenedDemandedElts; 3544 unsigned Population = MaskedDE.countPopulation(); 3545 Cost += (Population > 0 && Population != Scale && 3546 I % LT.second.getVectorNumElements() != 0); 3547 Cost += Population > 0; 3548 } 3549 Cost += DemandedElts.countPopulation(); 3550 3551 // For vXf32 cases, insertion into the 0'th index in each v4f32 3552 // 128-bit vector is free. 3553 // NOTE: This assumes legalization widens vXf32 vectors. 3554 if (MScalarTy == MVT::f32) 3555 for (unsigned i = 0, e = cast<FixedVectorType>(Ty)->getNumElements(); 3556 i < e; i += 4) 3557 if (DemandedElts[i]) 3558 Cost--; 3559 } 3560 } else if (LT.second.isVector()) { 3561 // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded 3562 // integer element as a SCALAR_TO_VECTOR, then we build the vector as a 3563 // series of UNPCK followed by CONCAT_VECTORS - all of these can be 3564 // considered cheap. 3565 if (Ty->isIntOrIntVectorTy()) 3566 Cost += DemandedElts.countPopulation(); 3567 3568 // Get the smaller of the legalized or original pow2-extended number of 3569 // vector elements, which represents the number of unpacks we'll end up 3570 // performing. 3571 unsigned NumElts = LT.second.getVectorNumElements(); 3572 unsigned Pow2Elts = 3573 PowerOf2Ceil(cast<FixedVectorType>(Ty)->getNumElements()); 3574 Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first; 3575 } 3576 } 3577 3578 // TODO: Use default extraction for now, but we should investigate extending this 3579 // to handle repeated subvector extraction. 3580 if (Extract) 3581 Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, false, Extract); 3582 3583 return Cost; 3584 } 3585 3586 InstructionCost X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 3587 MaybeAlign Alignment, 3588 unsigned AddressSpace, 3589 TTI::TargetCostKind CostKind, 3590 const Instruction *I) { 3591 // TODO: Handle other cost kinds. 3592 if (CostKind != TTI::TCK_RecipThroughput) { 3593 if (auto *SI = dyn_cast_or_null<StoreInst>(I)) { 3594 // Store instruction with index and scale costs 2 Uops. 3595 // Check the preceding GEP to identify non-const indices. 3596 if (auto *GEP = dyn_cast<GetElementPtrInst>(SI->getPointerOperand())) { 3597 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3598 return TTI::TCC_Basic * 2; 3599 } 3600 } 3601 return TTI::TCC_Basic; 3602 } 3603 3604 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 3605 "Invalid Opcode"); 3606 // Type legalization can't handle structs 3607 if (TLI->getValueType(DL, Src, true) == MVT::Other) 3608 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3609 CostKind); 3610 3611 // Legalize the type. 3612 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 3613 3614 auto *VTy = dyn_cast<FixedVectorType>(Src); 3615 3616 // Handle the simple case of non-vectors. 3617 // NOTE: this assumes that legalization never creates vector from scalars! 3618 if (!VTy || !LT.second.isVector()) 3619 // Each load/store unit costs 1. 3620 return LT.first * 1; 3621 3622 bool IsLoad = Opcode == Instruction::Load; 3623 3624 Type *EltTy = VTy->getElementType(); 3625 3626 const int EltTyBits = DL.getTypeSizeInBits(EltTy); 3627 3628 InstructionCost Cost = 0; 3629 3630 // Source of truth: how many elements were there in the original IR vector? 3631 const unsigned SrcNumElt = VTy->getNumElements(); 3632 3633 // How far have we gotten? 3634 int NumEltRemaining = SrcNumElt; 3635 // Note that we intentionally capture by-reference, NumEltRemaining changes. 3636 auto NumEltDone = [&]() { return SrcNumElt - NumEltRemaining; }; 3637 3638 const int MaxLegalOpSizeBytes = divideCeil(LT.second.getSizeInBits(), 8); 3639 3640 // Note that even if we can store 64 bits of an XMM, we still operate on XMM. 3641 const unsigned XMMBits = 128; 3642 if (XMMBits % EltTyBits != 0) 3643 // Vector size must be a multiple of the element size. I.e. no padding. 3644 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3645 CostKind); 3646 const int NumEltPerXMM = XMMBits / EltTyBits; 3647 3648 auto *XMMVecTy = FixedVectorType::get(EltTy, NumEltPerXMM); 3649 3650 for (int CurrOpSizeBytes = MaxLegalOpSizeBytes, SubVecEltsLeft = 0; 3651 NumEltRemaining > 0; CurrOpSizeBytes /= 2) { 3652 // How many elements would a single op deal with at once? 3653 if ((8 * CurrOpSizeBytes) % EltTyBits != 0) 3654 // Vector size must be a multiple of the element size. I.e. no padding. 3655 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3656 CostKind); 3657 int CurrNumEltPerOp = (8 * CurrOpSizeBytes) / EltTyBits; 3658 3659 assert(CurrOpSizeBytes > 0 && CurrNumEltPerOp > 0 && "How'd we get here?"); 3660 assert((((NumEltRemaining * EltTyBits) < (2 * 8 * CurrOpSizeBytes)) || 3661 (CurrOpSizeBytes == MaxLegalOpSizeBytes)) && 3662 "Unless we haven't halved the op size yet, " 3663 "we have less than two op's sized units of work left."); 3664 3665 auto *CurrVecTy = CurrNumEltPerOp > NumEltPerXMM 3666 ? FixedVectorType::get(EltTy, CurrNumEltPerOp) 3667 : XMMVecTy; 3668 3669 assert(CurrVecTy->getNumElements() % CurrNumEltPerOp == 0 && 3670 "After halving sizes, the vector elt count is no longer a multiple " 3671 "of number of elements per operation?"); 3672 auto *CoalescedVecTy = 3673 CurrNumEltPerOp == 1 3674 ? CurrVecTy 3675 : FixedVectorType::get( 3676 IntegerType::get(Src->getContext(), 3677 EltTyBits * CurrNumEltPerOp), 3678 CurrVecTy->getNumElements() / CurrNumEltPerOp); 3679 assert(DL.getTypeSizeInBits(CoalescedVecTy) == 3680 DL.getTypeSizeInBits(CurrVecTy) && 3681 "coalesciing elements doesn't change vector width."); 3682 3683 while (NumEltRemaining > 0) { 3684 assert(SubVecEltsLeft >= 0 && "Subreg element count overconsumtion?"); 3685 3686 // Can we use this vector size, as per the remaining element count? 3687 // Iff the vector is naturally aligned, we can do a wide load regardless. 3688 if (NumEltRemaining < CurrNumEltPerOp && 3689 (!IsLoad || Alignment.valueOrOne() < CurrOpSizeBytes) && 3690 CurrOpSizeBytes != 1) 3691 break; // Try smalled vector size. 3692 3693 bool Is0thSubVec = (NumEltDone() % LT.second.getVectorNumElements()) == 0; 3694 3695 // If we have fully processed the previous reg, we need to replenish it. 3696 if (SubVecEltsLeft == 0) { 3697 SubVecEltsLeft += CurrVecTy->getNumElements(); 3698 // And that's free only for the 0'th subvector of a legalized vector. 3699 if (!Is0thSubVec) 3700 Cost += getShuffleCost(IsLoad ? TTI::ShuffleKind::SK_InsertSubvector 3701 : TTI::ShuffleKind::SK_ExtractSubvector, 3702 VTy, None, NumEltDone(), CurrVecTy); 3703 } 3704 3705 // While we can directly load/store ZMM, YMM, and 64-bit halves of XMM, 3706 // for smaller widths (32/16/8) we have to insert/extract them separately. 3707 // Again, it's free for the 0'th subreg (if op is 32/64 bit wide, 3708 // but let's pretend that it is also true for 16/8 bit wide ops...) 3709 if (CurrOpSizeBytes <= 32 / 8 && !Is0thSubVec) { 3710 int NumEltDoneInCurrXMM = NumEltDone() % NumEltPerXMM; 3711 assert(NumEltDoneInCurrXMM % CurrNumEltPerOp == 0 && ""); 3712 int CoalescedVecEltIdx = NumEltDoneInCurrXMM / CurrNumEltPerOp; 3713 APInt DemandedElts = 3714 APInt::getBitsSet(CoalescedVecTy->getNumElements(), 3715 CoalescedVecEltIdx, CoalescedVecEltIdx + 1); 3716 assert(DemandedElts.countPopulation() == 1 && "Inserting single value"); 3717 Cost += getScalarizationOverhead(CoalescedVecTy, DemandedElts, IsLoad, 3718 !IsLoad); 3719 } 3720 3721 // This isn't exactly right. We're using slow unaligned 32-byte accesses 3722 // as a proxy for a double-pumped AVX memory interface such as on 3723 // Sandybridge. 3724 if (CurrOpSizeBytes == 32 && ST->isUnalignedMem32Slow()) 3725 Cost += 2; 3726 else 3727 Cost += 1; 3728 3729 SubVecEltsLeft -= CurrNumEltPerOp; 3730 NumEltRemaining -= CurrNumEltPerOp; 3731 Alignment = commonAlignment(Alignment.valueOrOne(), CurrOpSizeBytes); 3732 } 3733 } 3734 3735 assert(NumEltRemaining <= 0 && "Should have processed all the elements."); 3736 3737 return Cost; 3738 } 3739 3740 InstructionCost 3741 X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, Align Alignment, 3742 unsigned AddressSpace, 3743 TTI::TargetCostKind CostKind) { 3744 bool IsLoad = (Instruction::Load == Opcode); 3745 bool IsStore = (Instruction::Store == Opcode); 3746 3747 auto *SrcVTy = dyn_cast<FixedVectorType>(SrcTy); 3748 if (!SrcVTy) 3749 // To calculate scalar take the regular cost, without mask 3750 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace, CostKind); 3751 3752 unsigned NumElem = SrcVTy->getNumElements(); 3753 auto *MaskTy = 3754 FixedVectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 3755 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, Alignment)) || 3756 (IsStore && !isLegalMaskedStore(SrcVTy, Alignment))) { 3757 // Scalarization 3758 APInt DemandedElts = APInt::getAllOnes(NumElem); 3759 InstructionCost MaskSplitCost = 3760 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 3761 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 3762 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr, 3763 CmpInst::BAD_ICMP_PREDICATE, CostKind); 3764 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 3765 InstructionCost MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 3766 InstructionCost ValueSplitCost = 3767 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore); 3768 InstructionCost MemopCost = 3769 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3770 Alignment, AddressSpace, CostKind); 3771 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 3772 } 3773 3774 // Legalize the type. 3775 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3776 auto VT = TLI->getValueType(DL, SrcVTy); 3777 InstructionCost Cost = 0; 3778 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 3779 LT.second.getVectorNumElements() == NumElem) 3780 // Promotion requires extend/truncate for data and a shuffle for mask. 3781 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, None, 0, nullptr) + 3782 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, None, 0, nullptr); 3783 3784 else if (LT.first * LT.second.getVectorNumElements() > NumElem) { 3785 auto *NewMaskTy = FixedVectorType::get(MaskTy->getElementType(), 3786 LT.second.getVectorNumElements()); 3787 // Expanding requires fill mask with zeroes 3788 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, None, 0, MaskTy); 3789 } 3790 3791 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 3792 if (!ST->hasAVX512()) 3793 return Cost + LT.first * (IsLoad ? 2 : 8); 3794 3795 // AVX-512 masked load/store is cheapper 3796 return Cost + LT.first; 3797 } 3798 3799 InstructionCost X86TTIImpl::getAddressComputationCost(Type *Ty, 3800 ScalarEvolution *SE, 3801 const SCEV *Ptr) { 3802 // Address computations in vectorized code with non-consecutive addresses will 3803 // likely result in more instructions compared to scalar code where the 3804 // computation can more often be merged into the index mode. The resulting 3805 // extra micro-ops can significantly decrease throughput. 3806 const unsigned NumVectorInstToHideOverhead = 10; 3807 3808 // Cost modeling of Strided Access Computation is hidden by the indexing 3809 // modes of X86 regardless of the stride value. We dont believe that there 3810 // is a difference between constant strided access in gerenal and constant 3811 // strided value which is less than or equal to 64. 3812 // Even in the case of (loop invariant) stride whose value is not known at 3813 // compile time, the address computation will not incur more than one extra 3814 // ADD instruction. 3815 if (Ty->isVectorTy() && SE) { 3816 if (!BaseT::isStridedAccess(Ptr)) 3817 return NumVectorInstToHideOverhead; 3818 if (!BaseT::getConstantStrideStep(SE, Ptr)) 3819 return 1; 3820 } 3821 3822 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 3823 } 3824 3825 InstructionCost 3826 X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 3827 Optional<FastMathFlags> FMF, 3828 TTI::TargetCostKind CostKind) { 3829 if (TTI::requiresOrderedReduction(FMF)) 3830 return BaseT::getArithmeticReductionCost(Opcode, ValTy, FMF, CostKind); 3831 3832 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3833 // and make it as the cost. 3834 3835 static const CostTblEntry SLMCostTblNoPairWise[] = { 3836 { ISD::FADD, MVT::v2f64, 3 }, 3837 { ISD::ADD, MVT::v2i64, 5 }, 3838 }; 3839 3840 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3841 { ISD::FADD, MVT::v2f64, 2 }, 3842 { ISD::FADD, MVT::v2f32, 2 }, 3843 { ISD::FADD, MVT::v4f32, 4 }, 3844 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 3845 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 3846 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 3847 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 3848 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 3849 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 3850 { ISD::ADD, MVT::v2i8, 2 }, 3851 { ISD::ADD, MVT::v4i8, 2 }, 3852 { ISD::ADD, MVT::v8i8, 2 }, 3853 { ISD::ADD, MVT::v16i8, 3 }, 3854 }; 3855 3856 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3857 { ISD::FADD, MVT::v4f64, 3 }, 3858 { ISD::FADD, MVT::v4f32, 3 }, 3859 { ISD::FADD, MVT::v8f32, 4 }, 3860 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 3861 { ISD::ADD, MVT::v4i64, 3 }, 3862 { ISD::ADD, MVT::v8i32, 5 }, 3863 { ISD::ADD, MVT::v16i16, 5 }, 3864 { ISD::ADD, MVT::v32i8, 4 }, 3865 }; 3866 3867 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3868 assert(ISD && "Invalid opcode"); 3869 3870 // Before legalizing the type, give a chance to look up illegal narrow types 3871 // in the table. 3872 // FIXME: Is there a better way to do this? 3873 EVT VT = TLI->getValueType(DL, ValTy); 3874 if (VT.isSimple()) { 3875 MVT MTy = VT.getSimpleVT(); 3876 if (ST->isSLM()) 3877 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3878 return Entry->Cost; 3879 3880 if (ST->hasAVX()) 3881 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3882 return Entry->Cost; 3883 3884 if (ST->hasSSE2()) 3885 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3886 return Entry->Cost; 3887 } 3888 3889 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3890 3891 MVT MTy = LT.second; 3892 3893 auto *ValVTy = cast<FixedVectorType>(ValTy); 3894 3895 // Special case: vXi8 mul reductions are performed as vXi16. 3896 if (ISD == ISD::MUL && MTy.getScalarType() == MVT::i8) { 3897 auto *WideSclTy = IntegerType::get(ValVTy->getContext(), 16); 3898 auto *WideVecTy = FixedVectorType::get(WideSclTy, ValVTy->getNumElements()); 3899 return getCastInstrCost(Instruction::ZExt, WideVecTy, ValTy, 3900 TargetTransformInfo::CastContextHint::None, 3901 CostKind) + 3902 getArithmeticReductionCost(Opcode, WideVecTy, FMF, CostKind); 3903 } 3904 3905 InstructionCost ArithmeticCost = 0; 3906 if (LT.first != 1 && MTy.isVector() && 3907 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3908 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3909 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3910 MTy.getVectorNumElements()); 3911 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3912 ArithmeticCost *= LT.first - 1; 3913 } 3914 3915 if (ST->isSLM()) 3916 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3917 return ArithmeticCost + Entry->Cost; 3918 3919 if (ST->hasAVX()) 3920 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3921 return ArithmeticCost + Entry->Cost; 3922 3923 if (ST->hasSSE2()) 3924 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3925 return ArithmeticCost + Entry->Cost; 3926 3927 // FIXME: These assume a naive kshift+binop lowering, which is probably 3928 // conservative in most cases. 3929 static const CostTblEntry AVX512BoolReduction[] = { 3930 { ISD::AND, MVT::v2i1, 3 }, 3931 { ISD::AND, MVT::v4i1, 5 }, 3932 { ISD::AND, MVT::v8i1, 7 }, 3933 { ISD::AND, MVT::v16i1, 9 }, 3934 { ISD::AND, MVT::v32i1, 11 }, 3935 { ISD::AND, MVT::v64i1, 13 }, 3936 { ISD::OR, MVT::v2i1, 3 }, 3937 { ISD::OR, MVT::v4i1, 5 }, 3938 { ISD::OR, MVT::v8i1, 7 }, 3939 { ISD::OR, MVT::v16i1, 9 }, 3940 { ISD::OR, MVT::v32i1, 11 }, 3941 { ISD::OR, MVT::v64i1, 13 }, 3942 }; 3943 3944 static const CostTblEntry AVX2BoolReduction[] = { 3945 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 3946 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 3947 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 3948 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 3949 }; 3950 3951 static const CostTblEntry AVX1BoolReduction[] = { 3952 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 3953 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 3954 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3955 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3956 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 3957 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 3958 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3959 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3960 }; 3961 3962 static const CostTblEntry SSE2BoolReduction[] = { 3963 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 3964 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 3965 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 3966 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 3967 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 3968 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 3969 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 3970 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 3971 }; 3972 3973 // Handle bool allof/anyof patterns. 3974 if (ValVTy->getElementType()->isIntegerTy(1)) { 3975 InstructionCost ArithmeticCost = 0; 3976 if (LT.first != 1 && MTy.isVector() && 3977 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3978 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3979 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3980 MTy.getVectorNumElements()); 3981 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3982 ArithmeticCost *= LT.first - 1; 3983 } 3984 3985 if (ST->hasAVX512()) 3986 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 3987 return ArithmeticCost + Entry->Cost; 3988 if (ST->hasAVX2()) 3989 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 3990 return ArithmeticCost + Entry->Cost; 3991 if (ST->hasAVX()) 3992 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 3993 return ArithmeticCost + Entry->Cost; 3994 if (ST->hasSSE2()) 3995 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 3996 return ArithmeticCost + Entry->Cost; 3997 3998 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, FMF, CostKind); 3999 } 4000 4001 unsigned NumVecElts = ValVTy->getNumElements(); 4002 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 4003 4004 // Special case power of 2 reductions where the scalar type isn't changed 4005 // by type legalization. 4006 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 4007 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, FMF, CostKind); 4008 4009 InstructionCost ReductionCost = 0; 4010 4011 auto *Ty = ValVTy; 4012 if (LT.first != 1 && MTy.isVector() && 4013 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4014 // Type needs to be split. We need LT.first - 1 arithmetic ops. 4015 Ty = FixedVectorType::get(ValVTy->getElementType(), 4016 MTy.getVectorNumElements()); 4017 ReductionCost = getArithmeticInstrCost(Opcode, Ty, CostKind); 4018 ReductionCost *= LT.first - 1; 4019 NumVecElts = MTy.getVectorNumElements(); 4020 } 4021 4022 // Now handle reduction with the legal type, taking into account size changes 4023 // at each level. 4024 while (NumVecElts > 1) { 4025 // Determine the size of the remaining vector we need to reduce. 4026 unsigned Size = NumVecElts * ScalarSize; 4027 NumVecElts /= 2; 4028 // If we're reducing from 256/512 bits, use an extract_subvector. 4029 if (Size > 128) { 4030 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 4031 ReductionCost += 4032 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 4033 Ty = SubTy; 4034 } else if (Size == 128) { 4035 // Reducing from 128 bits is a permute of v2f64/v2i64. 4036 FixedVectorType *ShufTy; 4037 if (ValVTy->isFloatingPointTy()) 4038 ShufTy = 4039 FixedVectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 4040 else 4041 ShufTy = 4042 FixedVectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 4043 ReductionCost += 4044 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4045 } else if (Size == 64) { 4046 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 4047 FixedVectorType *ShufTy; 4048 if (ValVTy->isFloatingPointTy()) 4049 ShufTy = 4050 FixedVectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 4051 else 4052 ShufTy = 4053 FixedVectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 4054 ReductionCost += 4055 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4056 } else { 4057 // Reducing from smaller size is a shift by immediate. 4058 auto *ShiftTy = FixedVectorType::get( 4059 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 4060 ReductionCost += getArithmeticInstrCost( 4061 Instruction::LShr, ShiftTy, CostKind, 4062 TargetTransformInfo::OK_AnyValue, 4063 TargetTransformInfo::OK_UniformConstantValue, 4064 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 4065 } 4066 4067 // Add the arithmetic op for this level. 4068 ReductionCost += getArithmeticInstrCost(Opcode, Ty, CostKind); 4069 } 4070 4071 // Add the final extract element to the cost. 4072 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 4073 } 4074 4075 InstructionCost X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, 4076 bool IsUnsigned) { 4077 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 4078 4079 MVT MTy = LT.second; 4080 4081 int ISD; 4082 if (Ty->isIntOrIntVectorTy()) { 4083 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 4084 } else { 4085 assert(Ty->isFPOrFPVectorTy() && 4086 "Expected float point or integer vector type."); 4087 ISD = ISD::FMINNUM; 4088 } 4089 4090 static const CostTblEntry SSE1CostTbl[] = { 4091 {ISD::FMINNUM, MVT::v4f32, 1}, 4092 }; 4093 4094 static const CostTblEntry SSE2CostTbl[] = { 4095 {ISD::FMINNUM, MVT::v2f64, 1}, 4096 {ISD::SMIN, MVT::v8i16, 1}, 4097 {ISD::UMIN, MVT::v16i8, 1}, 4098 }; 4099 4100 static const CostTblEntry SSE41CostTbl[] = { 4101 {ISD::SMIN, MVT::v4i32, 1}, 4102 {ISD::UMIN, MVT::v4i32, 1}, 4103 {ISD::UMIN, MVT::v8i16, 1}, 4104 {ISD::SMIN, MVT::v16i8, 1}, 4105 }; 4106 4107 static const CostTblEntry SSE42CostTbl[] = { 4108 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 4109 }; 4110 4111 static const CostTblEntry AVX1CostTbl[] = { 4112 {ISD::FMINNUM, MVT::v8f32, 1}, 4113 {ISD::FMINNUM, MVT::v4f64, 1}, 4114 {ISD::SMIN, MVT::v8i32, 3}, 4115 {ISD::UMIN, MVT::v8i32, 3}, 4116 {ISD::SMIN, MVT::v16i16, 3}, 4117 {ISD::UMIN, MVT::v16i16, 3}, 4118 {ISD::SMIN, MVT::v32i8, 3}, 4119 {ISD::UMIN, MVT::v32i8, 3}, 4120 }; 4121 4122 static const CostTblEntry AVX2CostTbl[] = { 4123 {ISD::SMIN, MVT::v8i32, 1}, 4124 {ISD::UMIN, MVT::v8i32, 1}, 4125 {ISD::SMIN, MVT::v16i16, 1}, 4126 {ISD::UMIN, MVT::v16i16, 1}, 4127 {ISD::SMIN, MVT::v32i8, 1}, 4128 {ISD::UMIN, MVT::v32i8, 1}, 4129 }; 4130 4131 static const CostTblEntry AVX512CostTbl[] = { 4132 {ISD::FMINNUM, MVT::v16f32, 1}, 4133 {ISD::FMINNUM, MVT::v8f64, 1}, 4134 {ISD::SMIN, MVT::v2i64, 1}, 4135 {ISD::UMIN, MVT::v2i64, 1}, 4136 {ISD::SMIN, MVT::v4i64, 1}, 4137 {ISD::UMIN, MVT::v4i64, 1}, 4138 {ISD::SMIN, MVT::v8i64, 1}, 4139 {ISD::UMIN, MVT::v8i64, 1}, 4140 {ISD::SMIN, MVT::v16i32, 1}, 4141 {ISD::UMIN, MVT::v16i32, 1}, 4142 }; 4143 4144 static const CostTblEntry AVX512BWCostTbl[] = { 4145 {ISD::SMIN, MVT::v32i16, 1}, 4146 {ISD::UMIN, MVT::v32i16, 1}, 4147 {ISD::SMIN, MVT::v64i8, 1}, 4148 {ISD::UMIN, MVT::v64i8, 1}, 4149 }; 4150 4151 // If we have a native MIN/MAX instruction for this type, use it. 4152 if (ST->hasBWI()) 4153 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 4154 return LT.first * Entry->Cost; 4155 4156 if (ST->hasAVX512()) 4157 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 4158 return LT.first * Entry->Cost; 4159 4160 if (ST->hasAVX2()) 4161 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 4162 return LT.first * Entry->Cost; 4163 4164 if (ST->hasAVX()) 4165 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 4166 return LT.first * Entry->Cost; 4167 4168 if (ST->hasSSE42()) 4169 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 4170 return LT.first * Entry->Cost; 4171 4172 if (ST->hasSSE41()) 4173 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 4174 return LT.first * Entry->Cost; 4175 4176 if (ST->hasSSE2()) 4177 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 4178 return LT.first * Entry->Cost; 4179 4180 if (ST->hasSSE1()) 4181 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 4182 return LT.first * Entry->Cost; 4183 4184 unsigned CmpOpcode; 4185 if (Ty->isFPOrFPVectorTy()) { 4186 CmpOpcode = Instruction::FCmp; 4187 } else { 4188 assert(Ty->isIntOrIntVectorTy() && 4189 "expecting floating point or integer type for min/max reduction"); 4190 CmpOpcode = Instruction::ICmp; 4191 } 4192 4193 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4194 // Otherwise fall back to cmp+select. 4195 InstructionCost Result = 4196 getCmpSelInstrCost(CmpOpcode, Ty, CondTy, CmpInst::BAD_ICMP_PREDICATE, 4197 CostKind) + 4198 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, 4199 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4200 return Result; 4201 } 4202 4203 InstructionCost 4204 X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 4205 bool IsUnsigned, 4206 TTI::TargetCostKind CostKind) { 4207 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 4208 4209 MVT MTy = LT.second; 4210 4211 int ISD; 4212 if (ValTy->isIntOrIntVectorTy()) { 4213 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 4214 } else { 4215 assert(ValTy->isFPOrFPVectorTy() && 4216 "Expected float point or integer vector type."); 4217 ISD = ISD::FMINNUM; 4218 } 4219 4220 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 4221 // and make it as the cost. 4222 4223 static const CostTblEntry SSE2CostTblNoPairWise[] = { 4224 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 4225 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 4226 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 4227 }; 4228 4229 static const CostTblEntry SSE41CostTblNoPairWise[] = { 4230 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 4231 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 4232 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 4233 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 4234 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 4235 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 4236 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 4237 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 4238 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 4239 {ISD::SMIN, MVT::v16i8, 6}, 4240 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 4241 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 4242 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 4243 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 4244 }; 4245 4246 static const CostTblEntry AVX1CostTblNoPairWise[] = { 4247 {ISD::SMIN, MVT::v16i16, 6}, 4248 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 4249 {ISD::SMIN, MVT::v32i8, 8}, 4250 {ISD::UMIN, MVT::v32i8, 8}, 4251 }; 4252 4253 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 4254 {ISD::SMIN, MVT::v32i16, 8}, 4255 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 4256 {ISD::SMIN, MVT::v64i8, 10}, 4257 {ISD::UMIN, MVT::v64i8, 10}, 4258 }; 4259 4260 // Before legalizing the type, give a chance to look up illegal narrow types 4261 // in the table. 4262 // FIXME: Is there a better way to do this? 4263 EVT VT = TLI->getValueType(DL, ValTy); 4264 if (VT.isSimple()) { 4265 MVT MTy = VT.getSimpleVT(); 4266 if (ST->hasBWI()) 4267 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4268 return Entry->Cost; 4269 4270 if (ST->hasAVX()) 4271 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4272 return Entry->Cost; 4273 4274 if (ST->hasSSE41()) 4275 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4276 return Entry->Cost; 4277 4278 if (ST->hasSSE2()) 4279 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4280 return Entry->Cost; 4281 } 4282 4283 auto *ValVTy = cast<FixedVectorType>(ValTy); 4284 unsigned NumVecElts = ValVTy->getNumElements(); 4285 4286 auto *Ty = ValVTy; 4287 InstructionCost MinMaxCost = 0; 4288 if (LT.first != 1 && MTy.isVector() && 4289 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4290 // Type needs to be split. We need LT.first - 1 operations ops. 4291 Ty = FixedVectorType::get(ValVTy->getElementType(), 4292 MTy.getVectorNumElements()); 4293 auto *SubCondTy = FixedVectorType::get(CondTy->getElementType(), 4294 MTy.getVectorNumElements()); 4295 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4296 MinMaxCost *= LT.first - 1; 4297 NumVecElts = MTy.getVectorNumElements(); 4298 } 4299 4300 if (ST->hasBWI()) 4301 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4302 return MinMaxCost + Entry->Cost; 4303 4304 if (ST->hasAVX()) 4305 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4306 return MinMaxCost + Entry->Cost; 4307 4308 if (ST->hasSSE41()) 4309 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4310 return MinMaxCost + Entry->Cost; 4311 4312 if (ST->hasSSE2()) 4313 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4314 return MinMaxCost + Entry->Cost; 4315 4316 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 4317 4318 // Special case power of 2 reductions where the scalar type isn't changed 4319 // by type legalization. 4320 if (!isPowerOf2_32(ValVTy->getNumElements()) || 4321 ScalarSize != MTy.getScalarSizeInBits()) 4322 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsUnsigned, CostKind); 4323 4324 // Now handle reduction with the legal type, taking into account size changes 4325 // at each level. 4326 while (NumVecElts > 1) { 4327 // Determine the size of the remaining vector we need to reduce. 4328 unsigned Size = NumVecElts * ScalarSize; 4329 NumVecElts /= 2; 4330 // If we're reducing from 256/512 bits, use an extract_subvector. 4331 if (Size > 128) { 4332 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 4333 MinMaxCost += 4334 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 4335 Ty = SubTy; 4336 } else if (Size == 128) { 4337 // Reducing from 128 bits is a permute of v2f64/v2i64. 4338 VectorType *ShufTy; 4339 if (ValTy->isFloatingPointTy()) 4340 ShufTy = 4341 FixedVectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 4342 else 4343 ShufTy = FixedVectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 4344 MinMaxCost += 4345 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4346 } else if (Size == 64) { 4347 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 4348 FixedVectorType *ShufTy; 4349 if (ValTy->isFloatingPointTy()) 4350 ShufTy = FixedVectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 4351 else 4352 ShufTy = FixedVectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 4353 MinMaxCost += 4354 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4355 } else { 4356 // Reducing from smaller size is a shift by immediate. 4357 auto *ShiftTy = FixedVectorType::get( 4358 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 4359 MinMaxCost += getArithmeticInstrCost( 4360 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, 4361 TargetTransformInfo::OK_AnyValue, 4362 TargetTransformInfo::OK_UniformConstantValue, 4363 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 4364 } 4365 4366 // Add the arithmetic op for this level. 4367 auto *SubCondTy = 4368 FixedVectorType::get(CondTy->getElementType(), Ty->getNumElements()); 4369 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4370 } 4371 4372 // Add the final extract element to the cost. 4373 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 4374 } 4375 4376 /// Calculate the cost of materializing a 64-bit value. This helper 4377 /// method might only calculate a fraction of a larger immediate. Therefore it 4378 /// is valid to return a cost of ZERO. 4379 InstructionCost X86TTIImpl::getIntImmCost(int64_t Val) { 4380 if (Val == 0) 4381 return TTI::TCC_Free; 4382 4383 if (isInt<32>(Val)) 4384 return TTI::TCC_Basic; 4385 4386 return 2 * TTI::TCC_Basic; 4387 } 4388 4389 InstructionCost X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 4390 TTI::TargetCostKind CostKind) { 4391 assert(Ty->isIntegerTy()); 4392 4393 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4394 if (BitSize == 0) 4395 return ~0U; 4396 4397 // Never hoist constants larger than 128bit, because this might lead to 4398 // incorrect code generation or assertions in codegen. 4399 // Fixme: Create a cost model for types larger than i128 once the codegen 4400 // issues have been fixed. 4401 if (BitSize > 128) 4402 return TTI::TCC_Free; 4403 4404 if (Imm == 0) 4405 return TTI::TCC_Free; 4406 4407 // Sign-extend all constants to a multiple of 64-bit. 4408 APInt ImmVal = Imm; 4409 if (BitSize % 64 != 0) 4410 ImmVal = Imm.sext(alignTo(BitSize, 64)); 4411 4412 // Split the constant into 64-bit chunks and calculate the cost for each 4413 // chunk. 4414 InstructionCost Cost = 0; 4415 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 4416 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 4417 int64_t Val = Tmp.getSExtValue(); 4418 Cost += getIntImmCost(Val); 4419 } 4420 // We need at least one instruction to materialize the constant. 4421 return std::max<InstructionCost>(1, Cost); 4422 } 4423 4424 InstructionCost X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, 4425 const APInt &Imm, Type *Ty, 4426 TTI::TargetCostKind CostKind, 4427 Instruction *Inst) { 4428 assert(Ty->isIntegerTy()); 4429 4430 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4431 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4432 // here, so that constant hoisting will ignore this constant. 4433 if (BitSize == 0) 4434 return TTI::TCC_Free; 4435 4436 unsigned ImmIdx = ~0U; 4437 switch (Opcode) { 4438 default: 4439 return TTI::TCC_Free; 4440 case Instruction::GetElementPtr: 4441 // Always hoist the base address of a GetElementPtr. This prevents the 4442 // creation of new constants for every base constant that gets constant 4443 // folded with the offset. 4444 if (Idx == 0) 4445 return 2 * TTI::TCC_Basic; 4446 return TTI::TCC_Free; 4447 case Instruction::Store: 4448 ImmIdx = 0; 4449 break; 4450 case Instruction::ICmp: 4451 // This is an imperfect hack to prevent constant hoisting of 4452 // compares that might be trying to check if a 64-bit value fits in 4453 // 32-bits. The backend can optimize these cases using a right shift by 32. 4454 // Ideally we would check the compare predicate here. There also other 4455 // similar immediates the backend can use shifts for. 4456 if (Idx == 1 && Imm.getBitWidth() == 64) { 4457 uint64_t ImmVal = Imm.getZExtValue(); 4458 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 4459 return TTI::TCC_Free; 4460 } 4461 ImmIdx = 1; 4462 break; 4463 case Instruction::And: 4464 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 4465 // by using a 32-bit operation with implicit zero extension. Detect such 4466 // immediates here as the normal path expects bit 31 to be sign extended. 4467 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 4468 return TTI::TCC_Free; 4469 ImmIdx = 1; 4470 break; 4471 case Instruction::Add: 4472 case Instruction::Sub: 4473 // For add/sub, we can use the opposite instruction for INT32_MIN. 4474 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 4475 return TTI::TCC_Free; 4476 ImmIdx = 1; 4477 break; 4478 case Instruction::UDiv: 4479 case Instruction::SDiv: 4480 case Instruction::URem: 4481 case Instruction::SRem: 4482 // Division by constant is typically expanded later into a different 4483 // instruction sequence. This completely changes the constants. 4484 // Report them as "free" to stop ConstantHoist from marking them as opaque. 4485 return TTI::TCC_Free; 4486 case Instruction::Mul: 4487 case Instruction::Or: 4488 case Instruction::Xor: 4489 ImmIdx = 1; 4490 break; 4491 // Always return TCC_Free for the shift value of a shift instruction. 4492 case Instruction::Shl: 4493 case Instruction::LShr: 4494 case Instruction::AShr: 4495 if (Idx == 1) 4496 return TTI::TCC_Free; 4497 break; 4498 case Instruction::Trunc: 4499 case Instruction::ZExt: 4500 case Instruction::SExt: 4501 case Instruction::IntToPtr: 4502 case Instruction::PtrToInt: 4503 case Instruction::BitCast: 4504 case Instruction::PHI: 4505 case Instruction::Call: 4506 case Instruction::Select: 4507 case Instruction::Ret: 4508 case Instruction::Load: 4509 break; 4510 } 4511 4512 if (Idx == ImmIdx) { 4513 int NumConstants = divideCeil(BitSize, 64); 4514 InstructionCost Cost = X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4515 return (Cost <= NumConstants * TTI::TCC_Basic) 4516 ? static_cast<int>(TTI::TCC_Free) 4517 : Cost; 4518 } 4519 4520 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4521 } 4522 4523 InstructionCost X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 4524 const APInt &Imm, Type *Ty, 4525 TTI::TargetCostKind CostKind) { 4526 assert(Ty->isIntegerTy()); 4527 4528 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4529 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4530 // here, so that constant hoisting will ignore this constant. 4531 if (BitSize == 0) 4532 return TTI::TCC_Free; 4533 4534 switch (IID) { 4535 default: 4536 return TTI::TCC_Free; 4537 case Intrinsic::sadd_with_overflow: 4538 case Intrinsic::uadd_with_overflow: 4539 case Intrinsic::ssub_with_overflow: 4540 case Intrinsic::usub_with_overflow: 4541 case Intrinsic::smul_with_overflow: 4542 case Intrinsic::umul_with_overflow: 4543 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 4544 return TTI::TCC_Free; 4545 break; 4546 case Intrinsic::experimental_stackmap: 4547 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4548 return TTI::TCC_Free; 4549 break; 4550 case Intrinsic::experimental_patchpoint_void: 4551 case Intrinsic::experimental_patchpoint_i64: 4552 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4553 return TTI::TCC_Free; 4554 break; 4555 } 4556 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4557 } 4558 4559 InstructionCost X86TTIImpl::getCFInstrCost(unsigned Opcode, 4560 TTI::TargetCostKind CostKind, 4561 const Instruction *I) { 4562 if (CostKind != TTI::TCK_RecipThroughput) 4563 return Opcode == Instruction::PHI ? 0 : 1; 4564 // Branches are assumed to be predicted. 4565 return 0; 4566 } 4567 4568 int X86TTIImpl::getGatherOverhead() const { 4569 // Some CPUs have more overhead for gather. The specified overhead is relative 4570 // to the Load operation. "2" is the number provided by Intel architects. This 4571 // parameter is used for cost estimation of Gather Op and comparison with 4572 // other alternatives. 4573 // TODO: Remove the explicit hasAVX512()?, That would mean we would only 4574 // enable gather with a -march. 4575 if (ST->hasAVX512() || (ST->hasAVX2() && ST->hasFastGather())) 4576 return 2; 4577 4578 return 1024; 4579 } 4580 4581 int X86TTIImpl::getScatterOverhead() const { 4582 if (ST->hasAVX512()) 4583 return 2; 4584 4585 return 1024; 4586 } 4587 4588 // Return an average cost of Gather / Scatter instruction, maybe improved later. 4589 // FIXME: Add TargetCostKind support. 4590 InstructionCost X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, 4591 const Value *Ptr, Align Alignment, 4592 unsigned AddressSpace) { 4593 4594 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 4595 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4596 4597 // Try to reduce index size from 64 bit (default for GEP) 4598 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 4599 // operation will use 16 x 64 indices which do not fit in a zmm and needs 4600 // to split. Also check that the base pointer is the same for all lanes, 4601 // and that there's at most one variable index. 4602 auto getIndexSizeInBits = [](const Value *Ptr, const DataLayout &DL) { 4603 unsigned IndexSize = DL.getPointerSizeInBits(); 4604 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 4605 if (IndexSize < 64 || !GEP) 4606 return IndexSize; 4607 4608 unsigned NumOfVarIndices = 0; 4609 const Value *Ptrs = GEP->getPointerOperand(); 4610 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 4611 return IndexSize; 4612 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 4613 if (isa<Constant>(GEP->getOperand(i))) 4614 continue; 4615 Type *IndxTy = GEP->getOperand(i)->getType(); 4616 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 4617 IndxTy = IndexVTy->getElementType(); 4618 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 4619 !isa<SExtInst>(GEP->getOperand(i))) || 4620 ++NumOfVarIndices > 1) 4621 return IndexSize; // 64 4622 } 4623 return (unsigned)32; 4624 }; 4625 4626 // Trying to reduce IndexSize to 32 bits for vector 16. 4627 // By default the IndexSize is equal to pointer size. 4628 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 4629 ? getIndexSizeInBits(Ptr, DL) 4630 : DL.getPointerSizeInBits(); 4631 4632 auto *IndexVTy = FixedVectorType::get( 4633 IntegerType::get(SrcVTy->getContext(), IndexSize), VF); 4634 std::pair<InstructionCost, MVT> IdxsLT = 4635 TLI->getTypeLegalizationCost(DL, IndexVTy); 4636 std::pair<InstructionCost, MVT> SrcLT = 4637 TLI->getTypeLegalizationCost(DL, SrcVTy); 4638 InstructionCost::CostType SplitFactor = 4639 *std::max(IdxsLT.first, SrcLT.first).getValue(); 4640 if (SplitFactor > 1) { 4641 // Handle splitting of vector of pointers 4642 auto *SplitSrcTy = 4643 FixedVectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 4644 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 4645 AddressSpace); 4646 } 4647 4648 // The gather / scatter cost is given by Intel architects. It is a rough 4649 // number since we are looking at one instruction in a time. 4650 const int GSOverhead = (Opcode == Instruction::Load) 4651 ? getGatherOverhead() 4652 : getScatterOverhead(); 4653 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4654 MaybeAlign(Alignment), AddressSpace, 4655 TTI::TCK_RecipThroughput); 4656 } 4657 4658 /// Return the cost of full scalarization of gather / scatter operation. 4659 /// 4660 /// Opcode - Load or Store instruction. 4661 /// SrcVTy - The type of the data vector that should be gathered or scattered. 4662 /// VariableMask - The mask is non-constant at compile time. 4663 /// Alignment - Alignment for one element. 4664 /// AddressSpace - pointer[s] address space. 4665 /// 4666 /// FIXME: Add TargetCostKind support. 4667 InstructionCost X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 4668 bool VariableMask, Align Alignment, 4669 unsigned AddressSpace) { 4670 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4671 APInt DemandedElts = APInt::getAllOnes(VF); 4672 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4673 4674 InstructionCost MaskUnpackCost = 0; 4675 if (VariableMask) { 4676 auto *MaskTy = 4677 FixedVectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 4678 MaskUnpackCost = 4679 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 4680 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 4681 Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), nullptr, 4682 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4683 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 4684 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 4685 } 4686 4687 // The cost of the scalar loads/stores. 4688 InstructionCost MemoryOpCost = 4689 VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4690 MaybeAlign(Alignment), AddressSpace, CostKind); 4691 4692 InstructionCost InsertExtractCost = 0; 4693 if (Opcode == Instruction::Load) 4694 for (unsigned i = 0; i < VF; ++i) 4695 // Add the cost of inserting each scalar load into the vector 4696 InsertExtractCost += 4697 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 4698 else 4699 for (unsigned i = 0; i < VF; ++i) 4700 // Add the cost of extracting each element out of the data vector 4701 InsertExtractCost += 4702 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 4703 4704 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 4705 } 4706 4707 /// Calculate the cost of Gather / Scatter operation 4708 InstructionCost X86TTIImpl::getGatherScatterOpCost( 4709 unsigned Opcode, Type *SrcVTy, const Value *Ptr, bool VariableMask, 4710 Align Alignment, TTI::TargetCostKind CostKind, 4711 const Instruction *I = nullptr) { 4712 if (CostKind != TTI::TCK_RecipThroughput) { 4713 if ((Opcode == Instruction::Load && 4714 isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4715 (Opcode == Instruction::Store && 4716 isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4717 return 1; 4718 return BaseT::getGatherScatterOpCost(Opcode, SrcVTy, Ptr, VariableMask, 4719 Alignment, CostKind, I); 4720 } 4721 4722 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 4723 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 4724 if (!PtrTy && Ptr->getType()->isVectorTy()) 4725 PtrTy = dyn_cast<PointerType>( 4726 cast<VectorType>(Ptr->getType())->getElementType()); 4727 assert(PtrTy && "Unexpected type for Ptr argument"); 4728 unsigned AddressSpace = PtrTy->getAddressSpace(); 4729 4730 if ((Opcode == Instruction::Load && 4731 !isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4732 (Opcode == Instruction::Store && 4733 !isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4734 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 4735 AddressSpace); 4736 4737 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 4738 } 4739 4740 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 4741 TargetTransformInfo::LSRCost &C2) { 4742 // X86 specific here are "instruction number 1st priority". 4743 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 4744 C1.NumIVMuls, C1.NumBaseAdds, 4745 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 4746 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 4747 C2.NumIVMuls, C2.NumBaseAdds, 4748 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 4749 } 4750 4751 bool X86TTIImpl::canMacroFuseCmp() { 4752 return ST->hasMacroFusion() || ST->hasBranchFusion(); 4753 } 4754 4755 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, Align Alignment) { 4756 if (!ST->hasAVX()) 4757 return false; 4758 4759 // The backend can't handle a single element vector. 4760 if (isa<VectorType>(DataTy) && 4761 cast<FixedVectorType>(DataTy)->getNumElements() == 1) 4762 return false; 4763 Type *ScalarTy = DataTy->getScalarType(); 4764 4765 if (ScalarTy->isPointerTy()) 4766 return true; 4767 4768 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4769 return true; 4770 4771 if (ScalarTy->isHalfTy() && ST->hasBWI() && ST->hasFP16()) 4772 return true; 4773 4774 if (!ScalarTy->isIntegerTy()) 4775 return false; 4776 4777 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4778 return IntWidth == 32 || IntWidth == 64 || 4779 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 4780 } 4781 4782 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, Align Alignment) { 4783 return isLegalMaskedLoad(DataType, Alignment); 4784 } 4785 4786 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 4787 unsigned DataSize = DL.getTypeStoreSize(DataType); 4788 // The only supported nontemporal loads are for aligned vectors of 16 or 32 4789 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 4790 // (the equivalent stores only require AVX). 4791 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 4792 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 4793 4794 return false; 4795 } 4796 4797 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 4798 unsigned DataSize = DL.getTypeStoreSize(DataType); 4799 4800 // SSE4A supports nontemporal stores of float and double at arbitrary 4801 // alignment. 4802 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 4803 return true; 4804 4805 // Besides the SSE4A subtarget exception above, only aligned stores are 4806 // available nontemporaly on any other subtarget. And only stores with a size 4807 // of 4..32 bytes (powers of 2, only) are permitted. 4808 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 4809 !isPowerOf2_32(DataSize)) 4810 return false; 4811 4812 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 4813 // loads require AVX2). 4814 if (DataSize == 32) 4815 return ST->hasAVX(); 4816 if (DataSize == 16) 4817 return ST->hasSSE1(); 4818 return true; 4819 } 4820 4821 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 4822 if (!isa<VectorType>(DataTy)) 4823 return false; 4824 4825 if (!ST->hasAVX512()) 4826 return false; 4827 4828 // The backend can't handle a single element vector. 4829 if (cast<FixedVectorType>(DataTy)->getNumElements() == 1) 4830 return false; 4831 4832 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 4833 4834 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4835 return true; 4836 4837 if (!ScalarTy->isIntegerTy()) 4838 return false; 4839 4840 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4841 return IntWidth == 32 || IntWidth == 64 || 4842 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 4843 } 4844 4845 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 4846 return isLegalMaskedExpandLoad(DataTy); 4847 } 4848 4849 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, Align Alignment) { 4850 // Some CPUs have better gather performance than others. 4851 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 4852 // enable gather with a -march. 4853 if (!(ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()))) 4854 return false; 4855 4856 // This function is called now in two cases: from the Loop Vectorizer 4857 // and from the Scalarizer. 4858 // When the Loop Vectorizer asks about legality of the feature, 4859 // the vectorization factor is not calculated yet. The Loop Vectorizer 4860 // sends a scalar type and the decision is based on the width of the 4861 // scalar element. 4862 // Later on, the cost model will estimate usage this intrinsic based on 4863 // the vector type. 4864 // The Scalarizer asks again about legality. It sends a vector type. 4865 // In this case we can reject non-power-of-2 vectors. 4866 // We also reject single element vectors as the type legalizer can't 4867 // scalarize it. 4868 if (auto *DataVTy = dyn_cast<FixedVectorType>(DataTy)) { 4869 unsigned NumElts = DataVTy->getNumElements(); 4870 if (NumElts == 1) 4871 return false; 4872 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 4873 // Vector-4 of gather/scatter instruction does not exist on KNL. 4874 // We can extend it to 8 elements, but zeroing upper bits of 4875 // the mask vector will add more instructions. Right now we give the scalar 4876 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter 4877 // instruction is better in the VariableMask case. 4878 if (ST->hasAVX512() && (NumElts == 2 || (NumElts == 4 && !ST->hasVLX()))) 4879 return false; 4880 } 4881 Type *ScalarTy = DataTy->getScalarType(); 4882 if (ScalarTy->isPointerTy()) 4883 return true; 4884 4885 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4886 return true; 4887 4888 if (!ScalarTy->isIntegerTy()) 4889 return false; 4890 4891 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4892 return IntWidth == 32 || IntWidth == 64; 4893 } 4894 4895 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, Align Alignment) { 4896 // AVX2 doesn't support scatter 4897 if (!ST->hasAVX512()) 4898 return false; 4899 return isLegalMaskedGather(DataType, Alignment); 4900 } 4901 4902 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 4903 EVT VT = TLI->getValueType(DL, DataType); 4904 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 4905 } 4906 4907 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 4908 return false; 4909 } 4910 4911 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 4912 const Function *Callee) const { 4913 const TargetMachine &TM = getTLI()->getTargetMachine(); 4914 4915 // Work this as a subsetting of subtarget features. 4916 const FeatureBitset &CallerBits = 4917 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 4918 const FeatureBitset &CalleeBits = 4919 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 4920 4921 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 4922 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 4923 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 4924 } 4925 4926 bool X86TTIImpl::areFunctionArgsABICompatible( 4927 const Function *Caller, const Function *Callee, 4928 SmallPtrSetImpl<Argument *> &Args) const { 4929 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args)) 4930 return false; 4931 4932 // If we get here, we know the target features match. If one function 4933 // considers 512-bit vectors legal and the other does not, consider them 4934 // incompatible. 4935 const TargetMachine &TM = getTLI()->getTargetMachine(); 4936 4937 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 4938 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs()) 4939 return true; 4940 4941 // Consider the arguments compatible if they aren't vectors or aggregates. 4942 // FIXME: Look at the size of vectors. 4943 // FIXME: Look at the element types of aggregates to see if there are vectors. 4944 // FIXME: The API of this function seems intended to allow arguments 4945 // to be removed from the set, but the caller doesn't check if the set 4946 // becomes empty so that may not work in practice. 4947 return llvm::none_of(Args, [](Argument *A) { 4948 auto *EltTy = cast<PointerType>(A->getType())->getElementType(); 4949 return EltTy->isVectorTy() || EltTy->isAggregateType(); 4950 }); 4951 } 4952 4953 X86TTIImpl::TTI::MemCmpExpansionOptions 4954 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 4955 TTI::MemCmpExpansionOptions Options; 4956 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 4957 Options.NumLoadsPerBlock = 2; 4958 // All GPR and vector loads can be unaligned. 4959 Options.AllowOverlappingLoads = true; 4960 if (IsZeroCmp) { 4961 // Only enable vector loads for equality comparison. Right now the vector 4962 // version is not as fast for three way compare (see #33329). 4963 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 4964 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 4965 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 4966 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 4967 } 4968 if (ST->is64Bit()) { 4969 Options.LoadSizes.push_back(8); 4970 } 4971 Options.LoadSizes.push_back(4); 4972 Options.LoadSizes.push_back(2); 4973 Options.LoadSizes.push_back(1); 4974 return Options; 4975 } 4976 4977 bool X86TTIImpl::enableInterleavedAccessVectorization() { 4978 // TODO: We expect this to be beneficial regardless of arch, 4979 // but there are currently some unexplained performance artifacts on Atom. 4980 // As a temporary solution, disable on Atom. 4981 return !(ST->isAtom()); 4982 } 4983 4984 // Get estimation for interleaved load/store operations for AVX2. 4985 // \p Factor is the interleaved-access factor (stride) - number of 4986 // (interleaved) elements in the group. 4987 // \p Indices contains the indices for a strided load: when the 4988 // interleaved load has gaps they indicate which elements are used. 4989 // If Indices is empty (or if the number of indices is equal to the size 4990 // of the interleaved-access as given in \p Factor) the access has no gaps. 4991 // 4992 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 4993 // computing the cost using a generic formula as a function of generic 4994 // shuffles. We therefore use a lookup table instead, filled according to 4995 // the instruction sequences that codegen currently generates. 4996 InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2( 4997 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 4998 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 4999 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 5000 5001 if (UseMaskForCond || UseMaskForGaps) 5002 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5003 Alignment, AddressSpace, CostKind, 5004 UseMaskForCond, UseMaskForGaps); 5005 5006 // We currently Support only fully-interleaved groups, with no gaps. 5007 // TODO: Support also strided loads (interleaved-groups with gaps). 5008 if (Indices.size() && Indices.size() != Factor) 5009 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5010 Alignment, AddressSpace, CostKind); 5011 5012 // VecTy for interleave memop is <VF*Factor x Elt>. 5013 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 5014 // VecTy = <12 x i32>. 5015 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 5016 5017 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 5018 // the VF=2, while v2i128 is an unsupported MVT vector type 5019 // (see MachineValueType.h::getVectorVT()). 5020 if (!LegalVT.isVector()) 5021 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5022 Alignment, AddressSpace, CostKind); 5023 5024 unsigned VF = VecTy->getNumElements() / Factor; 5025 Type *ScalarTy = VecTy->getElementType(); 5026 // Deduplicate entries, model floats/pointers as appropriately-sized integers. 5027 if (!ScalarTy->isIntegerTy()) 5028 ScalarTy = 5029 Type::getIntNTy(ScalarTy->getContext(), DL.getTypeSizeInBits(ScalarTy)); 5030 5031 // Get the cost of all the memory operations. 5032 InstructionCost MemOpCosts = getMemoryOpCost( 5033 Opcode, VecTy, MaybeAlign(Alignment), AddressSpace, CostKind); 5034 5035 auto *VT = FixedVectorType::get(ScalarTy, VF); 5036 EVT ETy = TLI->getValueType(DL, VT); 5037 if (!ETy.isSimple()) 5038 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5039 Alignment, AddressSpace, CostKind); 5040 5041 // TODO: Complete for other data-types and strides. 5042 // Each combination of Stride, element bit width and VF results in a different 5043 // sequence; The cost tables are therefore accessed with: 5044 // Factor (stride) and VectorType=VFxiN. 5045 // The Cost accounts only for the shuffle sequence; 5046 // The cost of the loads/stores is accounted for separately. 5047 // 5048 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 5049 {2, MVT::v4i64, 6}, // (load 8i64 and) deinterleave into 2 x 4i64 5050 5051 {3, MVT::v2i8, 10}, // (load 6i8 and) deinterleave into 3 x 2i8 5052 {3, MVT::v4i8, 4}, // (load 12i8 and) deinterleave into 3 x 4i8 5053 {3, MVT::v8i8, 9}, // (load 24i8 and) deinterleave into 3 x 8i8 5054 {3, MVT::v16i8, 11}, // (load 48i8 and) deinterleave into 3 x 16i8 5055 {3, MVT::v32i8, 13}, // (load 96i8 and) deinterleave into 3 x 32i8 5056 5057 {3, MVT::v8i32, 17}, // (load 24i32 and) deinterleave into 3 x 8i32 5058 5059 {4, MVT::v2i8, 12}, // (load 8i8 and) deinterleave into 4 x 2i8 5060 {4, MVT::v4i8, 4}, // (load 16i8 and) deinterleave into 4 x 4i8 5061 {4, MVT::v8i8, 20}, // (load 32i8 and) deinterleave into 4 x 8i8 5062 {4, MVT::v16i8, 39}, // (load 64i8 and) deinterleave into 4 x 16i8 5063 {4, MVT::v32i8, 80}, // (load 128i8 and) deinterleave into 4 x 32i8 5064 5065 {8, MVT::v8i32, 40} // (load 64i32 and) deinterleave into 8 x 8i32 5066 }; 5067 5068 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 5069 {2, MVT::v4i64, 6}, // interleave 2 x 4i64 into 8i64 (and store) 5070 5071 {3, MVT::v2i8, 7}, // interleave 3 x 2i8 into 6i8 (and store) 5072 {3, MVT::v4i8, 8}, // interleave 3 x 4i8 into 12i8 (and store) 5073 {3, MVT::v8i8, 11}, // interleave 3 x 8i8 into 24i8 (and store) 5074 {3, MVT::v16i8, 11}, // interleave 3 x 16i8 into 48i8 (and store) 5075 {3, MVT::v32i8, 13}, // interleave 3 x 32i8 into 96i8 (and store) 5076 5077 {4, MVT::v2i8, 12}, // interleave 4 x 2i8 into 8i8 (and store) 5078 {4, MVT::v4i8, 9}, // interleave 4 x 4i8 into 16i8 (and store) 5079 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 5080 {4, MVT::v16i8, 10}, // interleave 4 x 16i8 into 64i8 (and store) 5081 {4, MVT::v32i8, 12} // interleave 4 x 32i8 into 128i8 (and store) 5082 }; 5083 5084 if (Opcode == Instruction::Load) { 5085 if (const auto *Entry = 5086 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 5087 return MemOpCosts + Entry->Cost; 5088 } else { 5089 assert(Opcode == Instruction::Store && 5090 "Expected Store Instruction at this point"); 5091 if (const auto *Entry = 5092 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 5093 return MemOpCosts + Entry->Cost; 5094 } 5095 5096 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5097 Alignment, AddressSpace, CostKind); 5098 } 5099 5100 // Get estimation for interleaved load/store operations and strided load. 5101 // \p Indices contains indices for strided load. 5102 // \p Factor - the factor of interleaving. 5103 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 5104 InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX512( 5105 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 5106 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 5107 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 5108 5109 if (UseMaskForCond || UseMaskForGaps) 5110 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5111 Alignment, AddressSpace, CostKind, 5112 UseMaskForCond, UseMaskForGaps); 5113 5114 // VecTy for interleave memop is <VF*Factor x Elt>. 5115 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 5116 // VecTy = <12 x i32>. 5117 5118 // Calculate the number of memory operations (NumOfMemOps), required 5119 // for load/store the VecTy. 5120 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 5121 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 5122 unsigned LegalVTSize = LegalVT.getStoreSize(); 5123 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 5124 5125 // Get the cost of one memory operation. 5126 auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(), 5127 LegalVT.getVectorNumElements()); 5128 InstructionCost MemOpCost = getMemoryOpCost( 5129 Opcode, SingleMemOpTy, MaybeAlign(Alignment), AddressSpace, CostKind); 5130 5131 unsigned VF = VecTy->getNumElements() / Factor; 5132 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 5133 5134 if (Opcode == Instruction::Load) { 5135 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 5136 // contain the cost of the optimized shuffle sequence that the 5137 // X86InterleavedAccess pass will generate. 5138 // The cost of loads and stores are computed separately from the table. 5139 5140 // X86InterleavedAccess support only the following interleaved-access group. 5141 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 5142 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 5143 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 5144 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 5145 }; 5146 5147 if (const auto *Entry = 5148 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 5149 return NumOfMemOps * MemOpCost + Entry->Cost; 5150 //If an entry does not exist, fallback to the default implementation. 5151 5152 // Kind of shuffle depends on number of loaded values. 5153 // If we load the entire data in one register, we can use a 1-src shuffle. 5154 // Otherwise, we'll merge 2 sources in each operation. 5155 TTI::ShuffleKind ShuffleKind = 5156 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 5157 5158 InstructionCost ShuffleCost = 5159 getShuffleCost(ShuffleKind, SingleMemOpTy, None, 0, nullptr); 5160 5161 unsigned NumOfLoadsInInterleaveGrp = 5162 Indices.size() ? Indices.size() : Factor; 5163 auto *ResultTy = FixedVectorType::get(VecTy->getElementType(), 5164 VecTy->getNumElements() / Factor); 5165 InstructionCost NumOfResults = 5166 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 5167 NumOfLoadsInInterleaveGrp; 5168 5169 // About a half of the loads may be folded in shuffles when we have only 5170 // one result. If we have more than one result, we do not fold loads at all. 5171 unsigned NumOfUnfoldedLoads = 5172 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 5173 5174 // Get a number of shuffle operations per result. 5175 unsigned NumOfShufflesPerResult = 5176 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 5177 5178 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 5179 // When we have more than one destination, we need additional instructions 5180 // to keep sources. 5181 InstructionCost NumOfMoves = 0; 5182 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 5183 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 5184 5185 InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 5186 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 5187 5188 return Cost; 5189 } 5190 5191 // Store. 5192 assert(Opcode == Instruction::Store && 5193 "Expected Store Instruction at this point"); 5194 // X86InterleavedAccess support only the following interleaved-access group. 5195 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 5196 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 5197 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 5198 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 5199 5200 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 5201 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 5202 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 5203 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 5204 }; 5205 5206 if (const auto *Entry = 5207 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 5208 return NumOfMemOps * MemOpCost + Entry->Cost; 5209 //If an entry does not exist, fallback to the default implementation. 5210 5211 // There is no strided stores meanwhile. And store can't be folded in 5212 // shuffle. 5213 unsigned NumOfSources = Factor; // The number of values to be merged. 5214 InstructionCost ShuffleCost = 5215 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, None, 0, nullptr); 5216 unsigned NumOfShufflesPerStore = NumOfSources - 1; 5217 5218 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 5219 // We need additional instructions to keep sources. 5220 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 5221 InstructionCost Cost = 5222 NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 5223 NumOfMoves; 5224 return Cost; 5225 } 5226 5227 InstructionCost X86TTIImpl::getInterleavedMemoryOpCost( 5228 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, 5229 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, 5230 bool UseMaskForCond, bool UseMaskForGaps) { 5231 auto isSupportedOnAVX512 = [&](Type *VecTy, bool HasBW) { 5232 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 5233 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 5234 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 5235 return true; 5236 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8) || 5237 (!ST->useSoftFloat() && ST->hasFP16() && EltTy->isHalfTy())) 5238 return HasBW; 5239 return false; 5240 }; 5241 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 5242 return getInterleavedMemoryOpCostAVX512( 5243 Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment, 5244 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 5245 if (ST->hasAVX2()) 5246 return getInterleavedMemoryOpCostAVX2( 5247 Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment, 5248 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 5249 5250 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5251 Alignment, AddressSpace, CostKind, 5252 UseMaskForCond, UseMaskForGaps); 5253 } 5254