1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // X86 cost model. 56 // 57 //===----------------------------------------------------------------------===// 58 59 TargetTransformInfo::PopcntSupportKind 60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 61 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 62 // TODO: Currently the __builtin_popcount() implementation using SSE3 63 // instructions is inefficient. Once the problem is fixed, we should 64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 66 } 67 68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 69 TargetTransformInfo::CacheLevel Level) const { 70 switch (Level) { 71 case TargetTransformInfo::CacheLevel::L1D: 72 // - Penryn 73 // - Nehalem 74 // - Westmere 75 // - Sandy Bridge 76 // - Ivy Bridge 77 // - Haswell 78 // - Broadwell 79 // - Skylake 80 // - Kabylake 81 return 32 * 1024; // 32 KByte 82 case TargetTransformInfo::CacheLevel::L2D: 83 // - Penryn 84 // - Nehalem 85 // - Westmere 86 // - Sandy Bridge 87 // - Ivy Bridge 88 // - Haswell 89 // - Broadwell 90 // - Skylake 91 // - Kabylake 92 return 256 * 1024; // 256 KByte 93 } 94 95 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 96 } 97 98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 99 TargetTransformInfo::CacheLevel Level) const { 100 // - Penryn 101 // - Nehalem 102 // - Westmere 103 // - Sandy Bridge 104 // - Ivy Bridge 105 // - Haswell 106 // - Broadwell 107 // - Skylake 108 // - Kabylake 109 switch (Level) { 110 case TargetTransformInfo::CacheLevel::L1D: 111 LLVM_FALLTHROUGH; 112 case TargetTransformInfo::CacheLevel::L2D: 113 return 8; 114 } 115 116 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 117 } 118 119 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 120 bool Vector = (ClassID == 1); 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 TypeSize 133 X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { 134 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 135 switch (K) { 136 case TargetTransformInfo::RGK_Scalar: 137 return TypeSize::getFixed(ST->is64Bit() ? 64 : 32); 138 case TargetTransformInfo::RGK_FixedWidthVector: 139 if (ST->hasAVX512() && PreferVectorWidth >= 512) 140 return TypeSize::getFixed(512); 141 if (ST->hasAVX() && PreferVectorWidth >= 256) 142 return TypeSize::getFixed(256); 143 if (ST->hasSSE1() && PreferVectorWidth >= 128) 144 return TypeSize::getFixed(128); 145 return TypeSize::getFixed(0); 146 case TargetTransformInfo::RGK_ScalableVector: 147 return TypeSize::getScalable(0); 148 } 149 150 llvm_unreachable("Unsupported register kind"); 151 } 152 153 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 154 return getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector) 155 .getFixedSize(); 156 } 157 158 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 159 // If the loop will not be vectorized, don't interleave the loop. 160 // Let regular unroll to unroll the loop, which saves the overflow 161 // check and memory check cost. 162 if (VF == 1) 163 return 1; 164 165 if (ST->isAtom()) 166 return 1; 167 168 // Sandybridge and Haswell have multiple execution ports and pipelined 169 // vector units. 170 if (ST->hasAVX()) 171 return 4; 172 173 return 2; 174 } 175 176 InstructionCost X86TTIImpl::getArithmeticInstrCost( 177 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, 178 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 179 TTI::OperandValueProperties Opd1PropInfo, 180 TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, 181 const Instruction *CxtI) { 182 // TODO: Handle more cost kinds. 183 if (CostKind != TTI::TCK_RecipThroughput) 184 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, 185 Op2Info, Opd1PropInfo, 186 Opd2PropInfo, Args, CxtI); 187 188 // vXi8 multiplications are always promoted to vXi16. 189 if (Opcode == Instruction::Mul && Ty->isVectorTy() && 190 Ty->getScalarSizeInBits() == 8) { 191 Type *WideVecTy = 192 VectorType::getExtendedElementVectorType(cast<VectorType>(Ty)); 193 return getCastInstrCost(Instruction::ZExt, WideVecTy, Ty, 194 TargetTransformInfo::CastContextHint::None, 195 CostKind) + 196 getCastInstrCost(Instruction::Trunc, Ty, WideVecTy, 197 TargetTransformInfo::CastContextHint::None, 198 CostKind) + 199 getArithmeticInstrCost(Opcode, WideVecTy, CostKind, Op1Info, Op2Info, 200 Opd1PropInfo, Opd2PropInfo); 201 } 202 203 // Legalize the type. 204 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 205 206 int ISD = TLI->InstructionOpcodeToISD(Opcode); 207 assert(ISD && "Invalid opcode"); 208 209 static const CostTblEntry GLMCostTable[] = { 210 { ISD::FDIV, MVT::f32, 18 }, // divss 211 { ISD::FDIV, MVT::v4f32, 35 }, // divps 212 { ISD::FDIV, MVT::f64, 33 }, // divsd 213 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 214 }; 215 216 if (ST->useGLMDivSqrtCosts()) 217 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 218 LT.second)) 219 return LT.first * Entry->Cost; 220 221 static const CostTblEntry SLMCostTable[] = { 222 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 223 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 224 { ISD::FMUL, MVT::f64, 2 }, // mulsd 225 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 226 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 227 { ISD::FDIV, MVT::f32, 17 }, // divss 228 { ISD::FDIV, MVT::v4f32, 39 }, // divps 229 { ISD::FDIV, MVT::f64, 32 }, // divsd 230 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 231 { ISD::FADD, MVT::v2f64, 2 }, // addpd 232 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 233 // v2i64/v4i64 mul is custom lowered as a series of long: 234 // multiplies(3), shifts(3) and adds(2) 235 // slm muldq version throughput is 2 and addq throughput 4 236 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 237 // 3X4 (addq throughput) = 17 238 { ISD::MUL, MVT::v2i64, 17 }, 239 // slm addq\subq throughput is 4 240 { ISD::ADD, MVT::v2i64, 4 }, 241 { ISD::SUB, MVT::v2i64, 4 }, 242 }; 243 244 if (ST->isSLM()) { 245 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 246 // Check if the operands can be shrinked into a smaller datatype. 247 bool Op1Signed = false; 248 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 249 bool Op2Signed = false; 250 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 251 252 bool SignedMode = Op1Signed || Op2Signed; 253 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 254 255 if (OpMinSize <= 7) 256 return LT.first * 3; // pmullw/sext 257 if (!SignedMode && OpMinSize <= 8) 258 return LT.first * 3; // pmullw/zext 259 if (OpMinSize <= 15) 260 return LT.first * 5; // pmullw/pmulhw/pshuf 261 if (!SignedMode && OpMinSize <= 16) 262 return LT.first * 5; // pmullw/pmulhw/pshuf 263 } 264 265 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 266 LT.second)) { 267 return LT.first * Entry->Cost; 268 } 269 } 270 271 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 272 ISD == ISD::UREM) && 273 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 274 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 275 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 276 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 277 // On X86, vector signed division by constants power-of-two are 278 // normally expanded to the sequence SRA + SRL + ADD + SRA. 279 // The OperandValue properties may not be the same as that of the previous 280 // operation; conservatively assume OP_None. 281 InstructionCost Cost = 282 2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Op1Info, 283 Op2Info, TargetTransformInfo::OP_None, 284 TargetTransformInfo::OP_None); 285 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 286 Op2Info, 287 TargetTransformInfo::OP_None, 288 TargetTransformInfo::OP_None); 289 Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind, Op1Info, 290 Op2Info, 291 TargetTransformInfo::OP_None, 292 TargetTransformInfo::OP_None); 293 294 if (ISD == ISD::SREM) { 295 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 296 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info, 297 Op2Info); 298 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info, 299 Op2Info); 300 } 301 302 return Cost; 303 } 304 305 // Vector unsigned division/remainder will be simplified to shifts/masks. 306 if (ISD == ISD::UDIV) 307 return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, 308 Op1Info, Op2Info, 309 TargetTransformInfo::OP_None, 310 TargetTransformInfo::OP_None); 311 312 else // UREM 313 return getArithmeticInstrCost(Instruction::And, Ty, CostKind, 314 Op1Info, Op2Info, 315 TargetTransformInfo::OP_None, 316 TargetTransformInfo::OP_None); 317 } 318 319 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 320 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 321 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 322 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 323 }; 324 325 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 326 ST->hasBWI()) { 327 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 328 LT.second)) 329 return LT.first * Entry->Cost; 330 } 331 332 static const CostTblEntry AVX512UniformConstCostTable[] = { 333 { ISD::SRA, MVT::v2i64, 1 }, 334 { ISD::SRA, MVT::v4i64, 1 }, 335 { ISD::SRA, MVT::v8i64, 1 }, 336 337 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 338 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 339 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 340 341 { ISD::SDIV, MVT::v16i32, 6 }, // pmuludq sequence 342 { ISD::SREM, MVT::v16i32, 8 }, // pmuludq+mul+sub sequence 343 { ISD::UDIV, MVT::v16i32, 5 }, // pmuludq sequence 344 { ISD::UREM, MVT::v16i32, 7 }, // pmuludq+mul+sub sequence 345 }; 346 347 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 348 ST->hasAVX512()) { 349 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 350 LT.second)) 351 return LT.first * Entry->Cost; 352 } 353 354 static const CostTblEntry AVX2UniformConstCostTable[] = { 355 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 356 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 357 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 358 359 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 360 361 { ISD::SDIV, MVT::v8i32, 6 }, // pmuludq sequence 362 { ISD::SREM, MVT::v8i32, 8 }, // pmuludq+mul+sub sequence 363 { ISD::UDIV, MVT::v8i32, 5 }, // pmuludq sequence 364 { ISD::UREM, MVT::v8i32, 7 }, // pmuludq+mul+sub sequence 365 }; 366 367 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 368 ST->hasAVX2()) { 369 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 370 LT.second)) 371 return LT.first * Entry->Cost; 372 } 373 374 static const CostTblEntry SSE2UniformConstCostTable[] = { 375 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 376 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 377 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 378 379 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 380 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 381 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 382 383 { ISD::SDIV, MVT::v8i32, 12+2 }, // 2*pmuludq sequence + split. 384 { ISD::SREM, MVT::v8i32, 16+2 }, // 2*pmuludq+mul+sub sequence + split. 385 { ISD::SDIV, MVT::v4i32, 6 }, // pmuludq sequence 386 { ISD::SREM, MVT::v4i32, 8 }, // pmuludq+mul+sub sequence 387 { ISD::UDIV, MVT::v8i32, 10+2 }, // 2*pmuludq sequence + split. 388 { ISD::UREM, MVT::v8i32, 14+2 }, // 2*pmuludq+mul+sub sequence + split. 389 { ISD::UDIV, MVT::v4i32, 5 }, // pmuludq sequence 390 { ISD::UREM, MVT::v4i32, 7 }, // pmuludq+mul+sub sequence 391 }; 392 393 // XOP has faster vXi8 shifts. 394 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 395 ST->hasSSE2() && !ST->hasXOP()) { 396 if (const auto *Entry = 397 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 398 return LT.first * Entry->Cost; 399 } 400 401 static const CostTblEntry AVX512BWConstCostTable[] = { 402 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 403 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 404 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 405 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 406 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 407 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 408 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 409 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 410 }; 411 412 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 413 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 414 ST->hasBWI()) { 415 if (const auto *Entry = 416 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 417 return LT.first * Entry->Cost; 418 } 419 420 static const CostTblEntry AVX512ConstCostTable[] = { 421 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 422 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 423 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 424 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 425 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 426 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 427 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 428 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 429 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 430 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 431 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 432 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 433 }; 434 435 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 436 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 437 ST->hasAVX512()) { 438 if (const auto *Entry = 439 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 440 return LT.first * Entry->Cost; 441 } 442 443 static const CostTblEntry AVX2ConstCostTable[] = { 444 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 445 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 446 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 447 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 448 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 449 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 450 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 451 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 452 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 453 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 454 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 455 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 456 }; 457 458 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 459 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 460 ST->hasAVX2()) { 461 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 462 return LT.first * Entry->Cost; 463 } 464 465 static const CostTblEntry SSE2ConstCostTable[] = { 466 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 467 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 468 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 469 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 470 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 471 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 472 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 473 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 474 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 475 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 476 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 477 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 478 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 479 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 480 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 481 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 482 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 483 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 484 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 485 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 486 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 487 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 488 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 489 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 490 }; 491 492 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 493 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 494 ST->hasSSE2()) { 495 // pmuldq sequence. 496 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 497 return LT.first * 32; 498 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 499 return LT.first * 38; 500 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 501 return LT.first * 15; 502 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 503 return LT.first * 20; 504 505 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 506 return LT.first * Entry->Cost; 507 } 508 509 static const CostTblEntry AVX512BWShiftCostTable[] = { 510 { ISD::SHL, MVT::v16i8, 4 }, // extend/vpsllvw/pack sequence. 511 { ISD::SRL, MVT::v16i8, 4 }, // extend/vpsrlvw/pack sequence. 512 { ISD::SRA, MVT::v16i8, 4 }, // extend/vpsravw/pack sequence. 513 { ISD::SHL, MVT::v32i8, 4 }, // extend/vpsllvw/pack sequence. 514 { ISD::SRL, MVT::v32i8, 4 }, // extend/vpsrlvw/pack sequence. 515 { ISD::SRA, MVT::v32i8, 6 }, // extend/vpsravw/pack sequence. 516 { ISD::SHL, MVT::v64i8, 6 }, // extend/vpsllvw/pack sequence. 517 { ISD::SRL, MVT::v64i8, 7 }, // extend/vpsrlvw/pack sequence. 518 { ISD::SRA, MVT::v64i8, 15 }, // extend/vpsravw/pack sequence. 519 520 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 521 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 522 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 523 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 524 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 525 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 526 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 527 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 528 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 529 }; 530 531 if (ST->hasBWI()) 532 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 533 return LT.first * Entry->Cost; 534 535 static const CostTblEntry AVX2UniformCostTable[] = { 536 // Uniform splats are cheaper for the following instructions. 537 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 538 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 539 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 540 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 541 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 542 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 543 544 { ISD::SHL, MVT::v8i32, 1 }, // pslld 545 { ISD::SRL, MVT::v8i32, 1 }, // psrld 546 { ISD::SRA, MVT::v8i32, 1 }, // psrad 547 { ISD::SHL, MVT::v4i64, 1 }, // psllq 548 { ISD::SRL, MVT::v4i64, 1 }, // psrlq 549 }; 550 551 if (ST->hasAVX2() && 552 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 553 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 554 if (const auto *Entry = 555 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 556 return LT.first * Entry->Cost; 557 } 558 559 static const CostTblEntry SSE2UniformCostTable[] = { 560 // Uniform splats are cheaper for the following instructions. 561 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 562 { ISD::SHL, MVT::v4i32, 1 }, // pslld 563 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 564 565 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 566 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 567 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 568 569 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 570 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 571 }; 572 573 if (ST->hasSSE2() && 574 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 575 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 576 if (const auto *Entry = 577 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 578 return LT.first * Entry->Cost; 579 } 580 581 static const CostTblEntry AVX512DQCostTable[] = { 582 { ISD::MUL, MVT::v2i64, 2 }, // pmullq 583 { ISD::MUL, MVT::v4i64, 2 }, // pmullq 584 { ISD::MUL, MVT::v8i64, 2 } // pmullq 585 }; 586 587 // Look for AVX512DQ lowering tricks for custom cases. 588 if (ST->hasDQI()) 589 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 590 return LT.first * Entry->Cost; 591 592 static const CostTblEntry AVX512BWCostTable[] = { 593 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 594 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 595 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 596 }; 597 598 // Look for AVX512BW lowering tricks for custom cases. 599 if (ST->hasBWI()) 600 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 601 return LT.first * Entry->Cost; 602 603 static const CostTblEntry AVX512CostTable[] = { 604 { ISD::SHL, MVT::v4i32, 1 }, 605 { ISD::SRL, MVT::v4i32, 1 }, 606 { ISD::SRA, MVT::v4i32, 1 }, 607 { ISD::SHL, MVT::v8i32, 1 }, 608 { ISD::SRL, MVT::v8i32, 1 }, 609 { ISD::SRA, MVT::v8i32, 1 }, 610 { ISD::SHL, MVT::v16i32, 1 }, 611 { ISD::SRL, MVT::v16i32, 1 }, 612 { ISD::SRA, MVT::v16i32, 1 }, 613 614 { ISD::SHL, MVT::v2i64, 1 }, 615 { ISD::SRL, MVT::v2i64, 1 }, 616 { ISD::SHL, MVT::v4i64, 1 }, 617 { ISD::SRL, MVT::v4i64, 1 }, 618 { ISD::SHL, MVT::v8i64, 1 }, 619 { ISD::SRL, MVT::v8i64, 1 }, 620 621 { ISD::SRA, MVT::v2i64, 1 }, 622 { ISD::SRA, MVT::v4i64, 1 }, 623 { ISD::SRA, MVT::v8i64, 1 }, 624 625 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 626 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 627 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 628 { ISD::MUL, MVT::v8i64, 6 }, // 3*pmuludq/3*shift/2*add 629 630 { ISD::FNEG, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 631 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 632 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 633 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 634 { ISD::FDIV, MVT::f64, 4 }, // Skylake from http://www.agner.org/ 635 { ISD::FDIV, MVT::v2f64, 4 }, // Skylake from http://www.agner.org/ 636 { ISD::FDIV, MVT::v4f64, 8 }, // Skylake from http://www.agner.org/ 637 { ISD::FDIV, MVT::v8f64, 16 }, // Skylake from http://www.agner.org/ 638 639 { ISD::FNEG, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 640 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 641 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 642 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 643 { ISD::FDIV, MVT::f32, 3 }, // Skylake from http://www.agner.org/ 644 { ISD::FDIV, MVT::v4f32, 3 }, // Skylake from http://www.agner.org/ 645 { ISD::FDIV, MVT::v8f32, 5 }, // Skylake from http://www.agner.org/ 646 { ISD::FDIV, MVT::v16f32, 10 }, // Skylake from http://www.agner.org/ 647 }; 648 649 if (ST->hasAVX512()) 650 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 651 return LT.first * Entry->Cost; 652 653 static const CostTblEntry AVX2ShiftCostTable[] = { 654 // Shifts on vXi64/vXi32 on AVX2 is legal even though we declare to 655 // customize them to detect the cases where shift amount is a scalar one. 656 { ISD::SHL, MVT::v4i32, 2 }, // vpsllvd (Haswell from agner.org) 657 { ISD::SRL, MVT::v4i32, 2 }, // vpsrlvd (Haswell from agner.org) 658 { ISD::SRA, MVT::v4i32, 2 }, // vpsravd (Haswell from agner.org) 659 { ISD::SHL, MVT::v8i32, 2 }, // vpsllvd (Haswell from agner.org) 660 { ISD::SRL, MVT::v8i32, 2 }, // vpsrlvd (Haswell from agner.org) 661 { ISD::SRA, MVT::v8i32, 2 }, // vpsravd (Haswell from agner.org) 662 { ISD::SHL, MVT::v2i64, 1 }, // vpsllvq (Haswell from agner.org) 663 { ISD::SRL, MVT::v2i64, 1 }, // vpsrlvq (Haswell from agner.org) 664 { ISD::SHL, MVT::v4i64, 1 }, // vpsllvq (Haswell from agner.org) 665 { ISD::SRL, MVT::v4i64, 1 }, // vpsrlvq (Haswell from agner.org) 666 }; 667 668 if (ST->hasAVX512()) { 669 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 670 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 671 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 672 // On AVX512, a packed v32i16 shift left by a constant build_vector 673 // is lowered into a vector multiply (vpmullw). 674 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 675 Op1Info, Op2Info, 676 TargetTransformInfo::OP_None, 677 TargetTransformInfo::OP_None); 678 } 679 680 // Look for AVX2 lowering tricks (XOP is always better at v4i32 shifts). 681 if (ST->hasAVX2() && !(ST->hasXOP() && LT.second == MVT::v4i32)) { 682 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 683 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 684 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 685 // On AVX2, a packed v16i16 shift left by a constant build_vector 686 // is lowered into a vector multiply (vpmullw). 687 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 688 Op1Info, Op2Info, 689 TargetTransformInfo::OP_None, 690 TargetTransformInfo::OP_None); 691 692 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 693 return LT.first * Entry->Cost; 694 } 695 696 static const CostTblEntry XOPShiftCostTable[] = { 697 // 128bit shifts take 1cy, but right shifts require negation beforehand. 698 { ISD::SHL, MVT::v16i8, 1 }, 699 { ISD::SRL, MVT::v16i8, 2 }, 700 { ISD::SRA, MVT::v16i8, 2 }, 701 { ISD::SHL, MVT::v8i16, 1 }, 702 { ISD::SRL, MVT::v8i16, 2 }, 703 { ISD::SRA, MVT::v8i16, 2 }, 704 { ISD::SHL, MVT::v4i32, 1 }, 705 { ISD::SRL, MVT::v4i32, 2 }, 706 { ISD::SRA, MVT::v4i32, 2 }, 707 { ISD::SHL, MVT::v2i64, 1 }, 708 { ISD::SRL, MVT::v2i64, 2 }, 709 { ISD::SRA, MVT::v2i64, 2 }, 710 // 256bit shifts require splitting if AVX2 didn't catch them above. 711 { ISD::SHL, MVT::v32i8, 2+2 }, 712 { ISD::SRL, MVT::v32i8, 4+2 }, 713 { ISD::SRA, MVT::v32i8, 4+2 }, 714 { ISD::SHL, MVT::v16i16, 2+2 }, 715 { ISD::SRL, MVT::v16i16, 4+2 }, 716 { ISD::SRA, MVT::v16i16, 4+2 }, 717 { ISD::SHL, MVT::v8i32, 2+2 }, 718 { ISD::SRL, MVT::v8i32, 4+2 }, 719 { ISD::SRA, MVT::v8i32, 4+2 }, 720 { ISD::SHL, MVT::v4i64, 2+2 }, 721 { ISD::SRL, MVT::v4i64, 4+2 }, 722 { ISD::SRA, MVT::v4i64, 4+2 }, 723 }; 724 725 // Look for XOP lowering tricks. 726 if (ST->hasXOP()) { 727 // If the right shift is constant then we'll fold the negation so 728 // it's as cheap as a left shift. 729 int ShiftISD = ISD; 730 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 731 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 732 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 733 ShiftISD = ISD::SHL; 734 if (const auto *Entry = 735 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 736 return LT.first * Entry->Cost; 737 } 738 739 static const CostTblEntry SSE2UniformShiftCostTable[] = { 740 // Uniform splats are cheaper for the following instructions. 741 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 742 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 743 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 744 745 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 746 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 747 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 748 749 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 750 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 751 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 752 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 753 }; 754 755 if (ST->hasSSE2() && 756 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 757 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 758 759 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 760 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 761 return LT.first * 4; // 2*psrad + shuffle. 762 763 if (const auto *Entry = 764 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 765 return LT.first * Entry->Cost; 766 } 767 768 if (ISD == ISD::SHL && 769 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 770 MVT VT = LT.second; 771 // Vector shift left by non uniform constant can be lowered 772 // into vector multiply. 773 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 774 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 775 ISD = ISD::MUL; 776 } 777 778 static const CostTblEntry AVX2CostTable[] = { 779 { ISD::SHL, MVT::v16i8, 6 }, // vpblendvb sequence. 780 { ISD::SHL, MVT::v32i8, 6 }, // vpblendvb sequence. 781 { ISD::SHL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 782 { ISD::SHL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 783 { ISD::SHL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 784 { ISD::SHL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 785 786 { ISD::SRL, MVT::v16i8, 6 }, // vpblendvb sequence. 787 { ISD::SRL, MVT::v32i8, 6 }, // vpblendvb sequence. 788 { ISD::SRL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 789 { ISD::SRL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 790 { ISD::SRL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 791 { ISD::SRL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 792 793 { ISD::SRA, MVT::v16i8, 17 }, // vpblendvb sequence. 794 { ISD::SRA, MVT::v32i8, 17 }, // vpblendvb sequence. 795 { ISD::SRA, MVT::v64i8, 34 }, // 2*vpblendvb sequence. 796 { ISD::SRA, MVT::v8i16, 5 }, // extend/vpsravd/pack sequence. 797 { ISD::SRA, MVT::v16i16, 7 }, // extend/vpsravd/pack sequence. 798 { ISD::SRA, MVT::v32i16, 14 }, // 2*extend/vpsravd/pack sequence. 799 { ISD::SRA, MVT::v2i64, 2 }, // srl/xor/sub sequence. 800 { ISD::SRA, MVT::v4i64, 2 }, // srl/xor/sub sequence. 801 802 { ISD::SUB, MVT::v32i8, 1 }, // psubb 803 { ISD::ADD, MVT::v32i8, 1 }, // paddb 804 { ISD::SUB, MVT::v16i16, 1 }, // psubw 805 { ISD::ADD, MVT::v16i16, 1 }, // paddw 806 { ISD::SUB, MVT::v8i32, 1 }, // psubd 807 { ISD::ADD, MVT::v8i32, 1 }, // paddd 808 { ISD::SUB, MVT::v4i64, 1 }, // psubq 809 { ISD::ADD, MVT::v4i64, 1 }, // paddq 810 811 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 812 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 813 { ISD::MUL, MVT::v4i64, 6 }, // 3*pmuludq/3*shift/2*add 814 815 { ISD::FNEG, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 816 { ISD::FNEG, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 817 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 818 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 819 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 820 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 821 { ISD::FMUL, MVT::f64, 1 }, // Haswell from http://www.agner.org/ 822 { ISD::FMUL, MVT::v2f64, 1 }, // Haswell from http://www.agner.org/ 823 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 824 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 825 826 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 827 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 828 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 829 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 830 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 831 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 832 }; 833 834 // Look for AVX2 lowering tricks for custom cases. 835 if (ST->hasAVX2()) 836 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 837 return LT.first * Entry->Cost; 838 839 static const CostTblEntry AVX1CostTable[] = { 840 // We don't have to scalarize unsupported ops. We can issue two half-sized 841 // operations and we only need to extract the upper YMM half. 842 // Two ops + 1 extract + 1 insert = 4. 843 { ISD::MUL, MVT::v16i16, 4 }, 844 { ISD::MUL, MVT::v8i32, 5 }, // BTVER2 from http://www.agner.org/ 845 { ISD::MUL, MVT::v4i64, 12 }, 846 847 { ISD::SUB, MVT::v32i8, 4 }, 848 { ISD::ADD, MVT::v32i8, 4 }, 849 { ISD::SUB, MVT::v16i16, 4 }, 850 { ISD::ADD, MVT::v16i16, 4 }, 851 { ISD::SUB, MVT::v8i32, 4 }, 852 { ISD::ADD, MVT::v8i32, 4 }, 853 { ISD::SUB, MVT::v4i64, 4 }, 854 { ISD::ADD, MVT::v4i64, 4 }, 855 856 { ISD::SHL, MVT::v16i8, 10 }, // pblendvb sequence . 857 { ISD::SHL, MVT::v32i8, 22 }, // pblendvb sequence + split. 858 { ISD::SHL, MVT::v8i16, 6 }, // pblendvb sequence. 859 { ISD::SHL, MVT::v16i16, 13 }, // pblendvb sequence + split. 860 { ISD::SHL, MVT::v4i32, 3 }, // pslld/paddd/cvttps2dq/pmulld 861 { ISD::SHL, MVT::v8i32, 9 }, // pslld/paddd/cvttps2dq/pmulld + split 862 { ISD::SHL, MVT::v2i64, 2 }, // Shift each lane + blend. 863 { ISD::SHL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 864 865 { ISD::SRL, MVT::v16i8, 11 }, // pblendvb sequence. 866 { ISD::SRL, MVT::v32i8, 23 }, // pblendvb sequence + split. 867 { ISD::SRL, MVT::v8i16, 13 }, // pblendvb sequence. 868 { ISD::SRL, MVT::v16i16, 28 }, // pblendvb sequence + split. 869 { ISD::SRL, MVT::v4i32, 6 }, // Shift each lane + blend. 870 { ISD::SRL, MVT::v8i32, 14 }, // Shift each lane + blend + split. 871 { ISD::SRL, MVT::v2i64, 2 }, // Shift each lane + blend. 872 { ISD::SRL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 873 874 { ISD::SRA, MVT::v16i8, 21 }, // pblendvb sequence. 875 { ISD::SRA, MVT::v32i8, 44 }, // pblendvb sequence + split. 876 { ISD::SRA, MVT::v8i16, 13 }, // pblendvb sequence. 877 { ISD::SRA, MVT::v16i16, 28 }, // pblendvb sequence + split. 878 { ISD::SRA, MVT::v4i32, 6 }, // Shift each lane + blend. 879 { ISD::SRA, MVT::v8i32, 14 }, // Shift each lane + blend + split. 880 { ISD::SRA, MVT::v2i64, 5 }, // Shift each lane + blend. 881 { ISD::SRA, MVT::v4i64, 12 }, // Shift each lane + blend + split. 882 883 { ISD::FNEG, MVT::v4f64, 2 }, // BTVER2 from http://www.agner.org/ 884 { ISD::FNEG, MVT::v8f32, 2 }, // BTVER2 from http://www.agner.org/ 885 886 { ISD::FMUL, MVT::f64, 2 }, // BTVER2 from http://www.agner.org/ 887 { ISD::FMUL, MVT::v2f64, 2 }, // BTVER2 from http://www.agner.org/ 888 { ISD::FMUL, MVT::v4f64, 4 }, // BTVER2 from http://www.agner.org/ 889 890 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 891 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 892 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 893 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 894 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 895 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 896 }; 897 898 if (ST->hasAVX()) 899 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 900 return LT.first * Entry->Cost; 901 902 static const CostTblEntry SSE42CostTable[] = { 903 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 904 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 905 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 906 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 907 908 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 909 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 910 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 911 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 912 913 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 914 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 915 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 916 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 917 918 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 919 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 920 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 921 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 922 923 { ISD::MUL, MVT::v2i64, 6 } // 3*pmuludq/3*shift/2*add 924 }; 925 926 if (ST->hasSSE42()) 927 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 928 return LT.first * Entry->Cost; 929 930 static const CostTblEntry SSE41CostTable[] = { 931 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 932 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 933 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 934 935 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 936 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 937 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 938 939 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 940 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 941 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 942 943 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 944 }; 945 946 if (ST->hasSSE41()) 947 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 948 return LT.first * Entry->Cost; 949 950 static const CostTblEntry SSE2CostTable[] = { 951 // We don't correctly identify costs of casts because they are marked as 952 // custom. 953 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 954 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 955 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 956 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 957 958 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 959 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 960 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 961 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 962 963 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 964 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 965 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 966 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 967 968 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 969 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 970 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 971 972 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 973 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 974 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 975 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 976 977 { ISD::FNEG, MVT::f32, 1 }, // Pentium IV from http://www.agner.org/ 978 { ISD::FNEG, MVT::f64, 1 }, // Pentium IV from http://www.agner.org/ 979 { ISD::FNEG, MVT::v4f32, 1 }, // Pentium IV from http://www.agner.org/ 980 { ISD::FNEG, MVT::v2f64, 1 }, // Pentium IV from http://www.agner.org/ 981 982 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 983 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 984 985 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 986 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 987 }; 988 989 if (ST->hasSSE2()) 990 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 991 return LT.first * Entry->Cost; 992 993 static const CostTblEntry SSE1CostTable[] = { 994 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 995 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 996 997 { ISD::FNEG, MVT::f32, 2 }, // Pentium III from http://www.agner.org/ 998 { ISD::FNEG, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 999 1000 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1001 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1002 1003 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1004 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1005 }; 1006 1007 if (ST->hasSSE1()) 1008 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 1009 return LT.first * Entry->Cost; 1010 1011 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 1012 { ISD::ADD, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1013 { ISD::SUB, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1014 }; 1015 1016 if (ST->is64Bit()) 1017 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, LT.second)) 1018 return LT.first * Entry->Cost; 1019 1020 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 1021 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1022 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1023 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1024 1025 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1026 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1027 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1028 }; 1029 1030 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, LT.second)) 1031 return LT.first * Entry->Cost; 1032 1033 // It is not a good idea to vectorize division. We have to scalarize it and 1034 // in the process we will often end up having to spilling regular 1035 // registers. The overhead of division is going to dominate most kernels 1036 // anyways so try hard to prevent vectorization of division - it is 1037 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 1038 // to hide "20 cycles" for each lane. 1039 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 1040 ISD == ISD::UDIV || ISD == ISD::UREM)) { 1041 InstructionCost ScalarCost = getArithmeticInstrCost( 1042 Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info, 1043 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 1044 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 1045 } 1046 1047 // Fallback to the default implementation. 1048 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info); 1049 } 1050 1051 InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, 1052 VectorType *BaseTp, 1053 ArrayRef<int> Mask, int Index, 1054 VectorType *SubTp) { 1055 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 1056 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 1057 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 1058 1059 Kind = improveShuffleKindFromMask(Kind, Mask); 1060 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 1061 if (Kind == TTI::SK_Transpose) 1062 Kind = TTI::SK_PermuteTwoSrc; 1063 1064 // For Broadcasts we are splatting the first element from the first input 1065 // register, so only need to reference that input and all the output 1066 // registers are the same. 1067 if (Kind == TTI::SK_Broadcast) 1068 LT.first = 1; 1069 1070 // Subvector extractions are free if they start at the beginning of a 1071 // vector and cheap if the subvectors are aligned. 1072 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 1073 int NumElts = LT.second.getVectorNumElements(); 1074 if ((Index % NumElts) == 0) 1075 return 0; 1076 std::pair<InstructionCost, MVT> SubLT = 1077 TLI->getTypeLegalizationCost(DL, SubTp); 1078 if (SubLT.second.isVector()) { 1079 int NumSubElts = SubLT.second.getVectorNumElements(); 1080 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1081 return SubLT.first; 1082 // Handle some cases for widening legalization. For now we only handle 1083 // cases where the original subvector was naturally aligned and evenly 1084 // fit in its legalized subvector type. 1085 // FIXME: Remove some of the alignment restrictions. 1086 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 1087 // vectors. 1088 int OrigSubElts = cast<FixedVectorType>(SubTp)->getNumElements(); 1089 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 1090 (NumSubElts % OrigSubElts) == 0 && 1091 LT.second.getVectorElementType() == 1092 SubLT.second.getVectorElementType() && 1093 LT.second.getVectorElementType().getSizeInBits() == 1094 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 1095 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 1096 "Unexpected number of elements!"); 1097 auto *VecTy = FixedVectorType::get(BaseTp->getElementType(), 1098 LT.second.getVectorNumElements()); 1099 auto *SubTy = FixedVectorType::get(BaseTp->getElementType(), 1100 SubLT.second.getVectorNumElements()); 1101 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 1102 InstructionCost ExtractCost = getShuffleCost( 1103 TTI::SK_ExtractSubvector, VecTy, None, ExtractIndex, SubTy); 1104 1105 // If the original size is 32-bits or more, we can use pshufd. Otherwise 1106 // if we have SSSE3 we can use pshufb. 1107 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 1108 return ExtractCost + 1; // pshufd or pshufb 1109 1110 assert(SubTp->getPrimitiveSizeInBits() == 16 && 1111 "Unexpected vector size"); 1112 1113 return ExtractCost + 2; // worst case pshufhw + pshufd 1114 } 1115 } 1116 } 1117 1118 // Subvector insertions are cheap if the subvectors are aligned. 1119 // Note that in general, the insertion starting at the beginning of a vector 1120 // isn't free, because we need to preserve the rest of the wide vector. 1121 if (Kind == TTI::SK_InsertSubvector && LT.second.isVector()) { 1122 int NumElts = LT.second.getVectorNumElements(); 1123 std::pair<InstructionCost, MVT> SubLT = 1124 TLI->getTypeLegalizationCost(DL, SubTp); 1125 if (SubLT.second.isVector()) { 1126 int NumSubElts = SubLT.second.getVectorNumElements(); 1127 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1128 return SubLT.first; 1129 } 1130 } 1131 1132 // Handle some common (illegal) sub-vector types as they are often very cheap 1133 // to shuffle even on targets without PSHUFB. 1134 EVT VT = TLI->getValueType(DL, BaseTp); 1135 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 1136 !ST->hasSSSE3()) { 1137 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 1138 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 1139 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1140 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1141 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1142 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1143 1144 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1145 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1146 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1147 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1148 1149 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1150 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1151 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1152 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1153 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1154 1155 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1156 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1157 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1158 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1159 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1160 }; 1161 1162 if (ST->hasSSE2()) 1163 if (const auto *Entry = 1164 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1165 return Entry->Cost; 1166 } 1167 1168 // We are going to permute multiple sources and the result will be in multiple 1169 // destinations. Providing an accurate cost only for splits where the element 1170 // type remains the same. 1171 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1172 MVT LegalVT = LT.second; 1173 if (LegalVT.isVector() && 1174 LegalVT.getVectorElementType().getSizeInBits() == 1175 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1176 LegalVT.getVectorNumElements() < 1177 cast<FixedVectorType>(BaseTp)->getNumElements()) { 1178 1179 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1180 unsigned LegalVTSize = LegalVT.getStoreSize(); 1181 // Number of source vectors after legalization: 1182 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1183 // Number of destination vectors after legalization: 1184 InstructionCost NumOfDests = LT.first; 1185 1186 auto *SingleOpTy = FixedVectorType::get(BaseTp->getElementType(), 1187 LegalVT.getVectorNumElements()); 1188 1189 InstructionCost NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1190 return NumOfShuffles * getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 1191 None, 0, nullptr); 1192 } 1193 1194 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1195 } 1196 1197 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1198 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1199 // We assume that source and destination have the same vector type. 1200 InstructionCost NumOfDests = LT.first; 1201 InstructionCost NumOfShufflesPerDest = LT.first * 2 - 1; 1202 LT.first = NumOfDests * NumOfShufflesPerDest; 1203 } 1204 1205 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1206 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1207 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1208 1209 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1210 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1211 1212 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b 1213 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b 1214 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2} // vpermt2b 1215 }; 1216 1217 if (ST->hasVBMI()) 1218 if (const auto *Entry = 1219 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1220 return LT.first * Entry->Cost; 1221 1222 static const CostTblEntry AVX512BWShuffleTbl[] = { 1223 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1224 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1225 1226 {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw 1227 {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw 1228 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1229 1230 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw 1231 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw 1232 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1233 1234 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w 1235 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w 1236 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2}, // vpermt2w 1237 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1238 1239 {TTI::SK_Select, MVT::v32i16, 1}, // vblendmw 1240 {TTI::SK_Select, MVT::v64i8, 1}, // vblendmb 1241 }; 1242 1243 if (ST->hasBWI()) 1244 if (const auto *Entry = 1245 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1246 return LT.first * Entry->Cost; 1247 1248 static const CostTblEntry AVX512ShuffleTbl[] = { 1249 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1250 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1251 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1252 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1253 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1254 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1255 1256 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1257 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1258 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1259 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1260 {TTI::SK_Reverse, MVT::v32i16, 7}, // per mca 1261 {TTI::SK_Reverse, MVT::v64i8, 7}, // per mca 1262 1263 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1264 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1265 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1266 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1267 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1268 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1269 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1270 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1271 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1272 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1273 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1274 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1275 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1276 1277 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1278 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1279 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1280 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1281 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1282 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1283 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1284 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1285 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1286 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1287 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1288 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1289 1290 // FIXME: This just applies the type legalization cost rules above 1291 // assuming these completely split. 1292 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1293 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1294 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1295 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1296 1297 {TTI::SK_Select, MVT::v32i16, 1}, // vpternlogq 1298 {TTI::SK_Select, MVT::v64i8, 1}, // vpternlogq 1299 {TTI::SK_Select, MVT::v8f64, 1}, // vblendmpd 1300 {TTI::SK_Select, MVT::v16f32, 1}, // vblendmps 1301 {TTI::SK_Select, MVT::v8i64, 1}, // vblendmq 1302 {TTI::SK_Select, MVT::v16i32, 1}, // vblendmd 1303 }; 1304 1305 if (ST->hasAVX512()) 1306 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1307 return LT.first * Entry->Cost; 1308 1309 static const CostTblEntry AVX2ShuffleTbl[] = { 1310 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1311 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1312 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1313 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1314 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1315 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1316 1317 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1318 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1319 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1320 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1321 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1322 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1323 1324 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1325 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1326 1327 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1328 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1329 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1330 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1331 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1332 // + vpblendvb 1333 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1334 // + vpblendvb 1335 1336 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1337 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1338 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1339 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1340 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1341 // + vpblendvb 1342 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1343 // + vpblendvb 1344 }; 1345 1346 if (ST->hasAVX2()) 1347 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1348 return LT.first * Entry->Cost; 1349 1350 static const CostTblEntry XOPShuffleTbl[] = { 1351 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1352 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1353 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1354 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1355 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1356 // + vinsertf128 1357 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1358 // + vinsertf128 1359 1360 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1361 // + vinsertf128 1362 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1363 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1364 // + vinsertf128 1365 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1366 }; 1367 1368 if (ST->hasXOP()) 1369 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1370 return LT.first * Entry->Cost; 1371 1372 static const CostTblEntry AVX1ShuffleTbl[] = { 1373 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1374 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1375 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1376 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1377 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1378 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1379 1380 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1381 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1382 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1383 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1384 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1385 // + vinsertf128 1386 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1387 // + vinsertf128 1388 1389 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1390 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1391 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1392 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1393 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1394 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1395 1396 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1397 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1398 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1399 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1400 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1401 // + 2*por + vinsertf128 1402 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1403 // + 2*por + vinsertf128 1404 1405 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1406 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1407 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1408 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1409 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1410 // + 4*por + vinsertf128 1411 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1412 // + 4*por + vinsertf128 1413 }; 1414 1415 if (ST->hasAVX()) 1416 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1417 return LT.first * Entry->Cost; 1418 1419 static const CostTblEntry SSE41ShuffleTbl[] = { 1420 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1421 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1422 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1423 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1424 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1425 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1426 }; 1427 1428 if (ST->hasSSE41()) 1429 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1430 return LT.first * Entry->Cost; 1431 1432 static const CostTblEntry SSSE3ShuffleTbl[] = { 1433 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1434 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1435 1436 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1437 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1438 1439 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1440 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1441 1442 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1443 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1444 1445 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1446 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1447 }; 1448 1449 if (ST->hasSSSE3()) 1450 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1451 return LT.first * Entry->Cost; 1452 1453 static const CostTblEntry SSE2ShuffleTbl[] = { 1454 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1455 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1456 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1457 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1458 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1459 1460 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1461 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1462 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1463 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1464 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1465 // + 2*pshufd + 2*unpck + packus 1466 1467 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1468 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1469 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1470 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1471 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1472 1473 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1474 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1475 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1476 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1477 // + pshufd/unpck 1478 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1479 // + 2*pshufd + 2*unpck + 2*packus 1480 1481 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1482 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1483 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1484 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1485 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1486 }; 1487 1488 if (ST->hasSSE2()) 1489 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1490 return LT.first * Entry->Cost; 1491 1492 static const CostTblEntry SSE1ShuffleTbl[] = { 1493 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1494 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1495 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1496 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1497 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1498 }; 1499 1500 if (ST->hasSSE1()) 1501 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1502 return LT.first * Entry->Cost; 1503 1504 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1505 } 1506 1507 InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, 1508 Type *Src, 1509 TTI::CastContextHint CCH, 1510 TTI::TargetCostKind CostKind, 1511 const Instruction *I) { 1512 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1513 assert(ISD && "Invalid opcode"); 1514 1515 // TODO: Allow non-throughput costs that aren't binary. 1516 auto AdjustCost = [&CostKind](InstructionCost Cost) -> InstructionCost { 1517 if (CostKind != TTI::TCK_RecipThroughput) 1518 return Cost == 0 ? 0 : 1; 1519 return Cost; 1520 }; 1521 1522 // FIXME: Need a better design of the cost table to handle non-simple types of 1523 // potential massive combinations (elem_num x src_type x dst_type). 1524 1525 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1526 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1527 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1528 1529 // Mask sign extend has an instruction. 1530 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1531 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1532 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1533 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1534 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1535 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1536 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1537 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1538 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1539 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1540 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1541 1542 // Mask zero extend is a sext + shift. 1543 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1544 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1545 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1546 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1547 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1548 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1549 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1550 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1551 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1552 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1553 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1554 1555 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, 1556 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm 1557 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // widen to zmm 1558 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // widen to zmm 1559 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // vpmovwb 1560 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // widen to zmm 1561 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // widen to zmm 1562 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // vpmovwb 1563 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // widen to zmm 1564 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // widen to zmm 1565 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // vpmovwb 1566 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // widen to zmm 1567 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // widen to zmm 1568 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // widen to zmm 1569 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, 1570 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, 1571 }; 1572 1573 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1574 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1575 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1576 1577 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1578 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1579 1580 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1581 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1582 1583 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1584 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1585 }; 1586 1587 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1588 // 256-bit wide vectors. 1589 1590 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1591 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1592 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1593 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1594 1595 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1596 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1597 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1598 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd 1599 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1600 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1601 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1602 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd 1603 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd 1604 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd 1605 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd 1606 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd 1607 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq 1608 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq 1609 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq 1610 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 2 }, // vpmovdb 1611 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 2 }, // vpmovdb 1612 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, // vpmovdb 1613 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, // vpmovdb 1614 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 2 }, // vpmovqb 1615 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 1 }, // vpshufb 1616 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, // vpmovqb 1617 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, // vpmovqw 1618 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, // vpmovqd 1619 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd 1620 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb 1621 1622 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32 1623 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, 1624 1625 // Sign extend is zmm vpternlogd+vptruncdb. 1626 // Zero extend is zmm broadcast load+vptruncdw. 1627 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 }, 1628 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 }, 1629 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, 1630 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, 1631 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, 1632 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, 1633 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 }, 1634 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 }, 1635 1636 // Sign extend is zmm vpternlogd+vptruncdw. 1637 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw. 1638 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 }, 1639 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1640 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 }, 1641 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1642 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 }, 1643 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1644 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 }, 1645 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1646 1647 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd 1648 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld 1649 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd 1650 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld 1651 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd 1652 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld 1653 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq 1654 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq 1655 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq 1656 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq 1657 1658 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd 1659 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld 1660 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq 1661 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq 1662 1663 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1664 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1665 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1666 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1667 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1668 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1669 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1670 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1671 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1672 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1673 1674 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1675 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1676 1677 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1678 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1679 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1680 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1681 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1682 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1683 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1684 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1685 1686 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1687 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1688 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1689 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1690 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1691 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1692 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1693 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1694 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1695 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1696 1697 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f64, 3 }, 1698 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, 1699 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 1 }, 1700 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 3 }, 1701 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 3 }, 1702 { ISD::FP_TO_SINT, MVT::v16i32, MVT::v16f64, 3 }, 1703 1704 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1705 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, 1706 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, 1707 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1708 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, 1709 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, 1710 }; 1711 1712 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1713 // Mask sign extend has an instruction. 1714 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1715 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1716 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1717 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1718 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1719 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1720 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1721 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1722 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1723 1724 // Mask zero extend is a sext + shift. 1725 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1726 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1727 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1728 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1729 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1730 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1731 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1732 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1733 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1734 1735 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, 1736 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // vpsllw+vptestmb 1737 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // vpsllw+vptestmw 1738 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // vpsllw+vptestmb 1739 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // vpsllw+vptestmw 1740 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // vpsllw+vptestmb 1741 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // vpsllw+vptestmw 1742 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // vpsllw+vptestmb 1743 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // vpsllw+vptestmw 1744 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // vpsllw+vptestmb 1745 }; 1746 1747 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1748 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1749 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1750 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1751 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1752 1753 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1754 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1755 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1756 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1757 1758 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1759 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1760 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1761 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1762 1763 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1764 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1765 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1766 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1767 }; 1768 1769 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 1770 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1771 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1772 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1773 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 8 }, // split+2*v8i8 1774 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1775 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1776 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1777 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16 1778 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // vpslld+vptestmd 1779 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd 1780 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // vpslld+vptestmd 1781 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // vpsllq+vptestmq 1782 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // vpsllq+vptestmq 1783 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // vpmovqd 1784 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, // vpmovqb 1785 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, // vpmovqw 1786 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, // vpmovwb 1787 1788 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb 1789 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb 1790 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 }, 1791 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 }, 1792 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 }, 1793 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 }, 1794 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 }, 1795 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 }, 1796 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 }, 1797 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 }, 1798 1799 // sign extend is vpcmpeq+maskedmove+vpmovdw 1800 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw 1801 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1802 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 }, 1803 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1804 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 }, 1805 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1806 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 }, 1807 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 }, 1808 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 }, 1809 1810 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd 1811 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld 1812 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd 1813 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld 1814 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd 1815 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld 1816 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq 1817 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq 1818 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq 1819 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq 1820 1821 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1822 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1823 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1824 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1825 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1826 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1827 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 1828 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1829 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1830 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1831 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1832 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1833 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1834 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1835 1836 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 1837 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1838 1839 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 3 }, 1840 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 3 }, 1841 1842 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 1843 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 1844 1845 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1846 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1847 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 1 }, 1848 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1849 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1850 }; 1851 1852 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1853 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1854 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1855 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1856 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1857 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1858 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1859 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1860 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1861 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1862 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1863 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1864 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1865 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1866 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1867 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1868 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1869 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1870 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1871 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1872 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1873 1874 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 1 }, 1875 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 1 }, 1876 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, 1877 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1878 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1879 1880 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1881 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1882 1883 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 1 }, 1884 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 1 }, 1885 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 3 }, 1886 1887 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 4 }, 1888 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 7 }, 1889 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 4 }, 1890 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 7 }, 1891 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 4 }, 1892 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 15 }, 1893 1894 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1895 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1896 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 3 }, 1897 1898 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1899 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1900 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 2 }, 1901 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 1902 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 1903 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 }, 1904 }; 1905 1906 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1907 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1908 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1909 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1910 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1911 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 1912 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 1913 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 1914 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 1915 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1916 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1917 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1918 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1919 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1920 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1921 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1922 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1923 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1924 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1925 1926 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 4 }, 1927 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 5 }, 1928 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 4 }, 1929 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 9 }, 1930 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, 11 }, 1931 1932 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // and+extract+packuswb 1933 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 2 }, // and+packusdw+packuswb 1934 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1935 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1936 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1937 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 3 }, // and+extract+2*packusdw 1938 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1939 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 11 }, 1940 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 9 }, 1941 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 }, 1942 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 11 }, 1943 1944 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1945 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1946 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1947 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1948 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1949 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1950 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1951 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1952 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1953 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 1954 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 1955 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 }, 1956 1957 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1958 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1959 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1960 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1961 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1962 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1963 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1964 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1965 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1966 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 4 }, 1967 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1968 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1969 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1970 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 10 }, 1971 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1972 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1973 // The generic code to compute the scalar overhead is currently broken. 1974 // Workaround this limitation by estimating the scalarization overhead 1975 // here. We have roughly 10 instructions per scalar element. 1976 // Multiply that by the vector width. 1977 // FIXME: remove that when PR19268 is fixed. 1978 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1979 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1980 1981 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 4 }, 1982 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f64, 3 }, 1983 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f64, 2 }, 1984 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 2 }, 1985 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 3 }, 1986 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 2 }, 1987 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 5 }, 1988 1989 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 5 }, 1990 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 9 }, 1991 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 5 }, 1992 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f64, 3 }, 1993 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f64, 2 }, 1994 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 9 }, 1995 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 4 }, 1996 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 3 }, 1997 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 9 }, 1998 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 19 }, 1999 // This node is expanded into scalarized operations but BasicTTI is overly 2000 // optimistic estimating its cost. It computes 3 per element (one 2001 // vector-extract, one scalar conversion and one vector-insert). The 2002 // problem is that the inserts form a read-modify-write chain so latency 2003 // should be factored in too. Inflating the cost per element by 1. 2004 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 2005 2006 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 2007 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 2008 }; 2009 2010 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 2011 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 2012 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 2013 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 2014 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 2015 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 2016 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 2017 2018 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i8, 1 }, 2019 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i8, 1 }, 2020 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i8, 1 }, 2021 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i8, 1 }, 2022 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i8, 1 }, 2023 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i8, 1 }, 2024 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 2025 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 2026 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 2027 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 2028 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 2029 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 2030 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 2031 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 2032 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 2033 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 2034 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 2035 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 2036 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i16, 1 }, 2037 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i16, 1 }, 2038 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i16, 1 }, 2039 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i16, 1 }, 2040 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 2041 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 2042 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 2043 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 2044 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 2045 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 2046 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, 2047 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, 2048 2049 // These truncates end up widening elements. 2050 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 1 }, // PMOVXZBQ 2051 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 1 }, // PMOVXZWQ 2052 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 1 }, // PMOVXZBD 2053 2054 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 1 }, 2055 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 1 }, 2056 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 2057 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 2058 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 2059 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 2060 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 2061 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 2062 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 1 }, // PSHUFB 2063 2064 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 2065 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 2066 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 2067 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 1 }, 2068 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2069 2070 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 2071 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 2072 2073 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 3 }, 2074 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 3 }, 2075 2076 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 3 }, 2077 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 3 }, 2078 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, 2079 }; 2080 2081 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 2082 // These are somewhat magic numbers justified by looking at the output of 2083 // Intel's IACA, running some kernels and making sure when we take 2084 // legalization into account the throughput will be overestimated. 2085 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 2086 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 2087 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 2088 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 2089 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 2090 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 2*10 }, 2091 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2*10 }, 2092 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 2093 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 2094 2095 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 2096 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 2097 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 2098 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 2099 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 2100 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 2101 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 }, 2102 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 2103 2104 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 4 }, 2105 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 2 }, 2106 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, 2107 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, 2108 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, 2109 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 4 }, 2110 2111 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 1 }, 2112 2113 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 6 }, 2114 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 }, 2115 2116 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 2117 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 2118 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 4 }, 2119 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 4 }, 2120 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 }, 2121 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 2 }, 2122 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 }, 2123 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 4 }, 2124 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 8 }, 2125 2126 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 2127 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 2128 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 2129 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 2130 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 2131 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 2132 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 2133 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 2134 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 2135 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 2136 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 2137 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 2138 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 2139 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 2140 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 2141 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 2142 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 2143 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 2144 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 2145 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 2146 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 2147 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 2148 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 2149 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 2150 2151 // These truncates are really widening elements. 2152 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 1 }, // PSHUFD 2153 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // PUNPCKLWD+DQ 2154 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // PUNPCKLBW+WD+PSHUFD 2155 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 1 }, // PUNPCKLWD 2156 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // PUNPCKLBW+WD 2157 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 1 }, // PUNPCKLBW 2158 2159 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // PAND+PACKUSWB 2160 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // PAND+PACKUSWB 2161 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // PAND+PACKUSWB 2162 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 2163 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 3 }, // PAND+2*PACKUSWB 2164 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 2165 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 2166 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 2167 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 2168 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 2169 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2170 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 2171 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 2172 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 2173 { ISD::TRUNCATE, MVT::v2i32, MVT::v2i64, 1 }, // PSHUFD 2174 }; 2175 2176 std::pair<InstructionCost, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 2177 std::pair<InstructionCost, MVT> LTDest = 2178 TLI->getTypeLegalizationCost(DL, Dst); 2179 2180 if (ST->hasSSE41() && !ST->hasAVX()) 2181 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2182 LTDest.second, LTSrc.second)) 2183 return AdjustCost(LTSrc.first * Entry->Cost); 2184 2185 if (ST->hasSSE2() && !ST->hasAVX()) 2186 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2187 LTDest.second, LTSrc.second)) 2188 return AdjustCost(LTSrc.first * Entry->Cost); 2189 2190 EVT SrcTy = TLI->getValueType(DL, Src); 2191 EVT DstTy = TLI->getValueType(DL, Dst); 2192 2193 // The function getSimpleVT only handles simple value types. 2194 if (!SrcTy.isSimple() || !DstTy.isSimple()) 2195 return AdjustCost(BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind)); 2196 2197 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 2198 MVT SimpleDstTy = DstTy.getSimpleVT(); 2199 2200 if (ST->useAVX512Regs()) { 2201 if (ST->hasBWI()) 2202 if (const auto *Entry = ConvertCostTableLookup(AVX512BWConversionTbl, ISD, 2203 SimpleDstTy, SimpleSrcTy)) 2204 return AdjustCost(Entry->Cost); 2205 2206 if (ST->hasDQI()) 2207 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 2208 SimpleDstTy, SimpleSrcTy)) 2209 return AdjustCost(Entry->Cost); 2210 2211 if (ST->hasAVX512()) 2212 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 2213 SimpleDstTy, SimpleSrcTy)) 2214 return AdjustCost(Entry->Cost); 2215 } 2216 2217 if (ST->hasBWI()) 2218 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 2219 SimpleDstTy, SimpleSrcTy)) 2220 return AdjustCost(Entry->Cost); 2221 2222 if (ST->hasDQI()) 2223 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 2224 SimpleDstTy, SimpleSrcTy)) 2225 return AdjustCost(Entry->Cost); 2226 2227 if (ST->hasAVX512()) 2228 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2229 SimpleDstTy, SimpleSrcTy)) 2230 return AdjustCost(Entry->Cost); 2231 2232 if (ST->hasAVX2()) { 2233 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2234 SimpleDstTy, SimpleSrcTy)) 2235 return AdjustCost(Entry->Cost); 2236 } 2237 2238 if (ST->hasAVX()) { 2239 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2240 SimpleDstTy, SimpleSrcTy)) 2241 return AdjustCost(Entry->Cost); 2242 } 2243 2244 if (ST->hasSSE41()) { 2245 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2246 SimpleDstTy, SimpleSrcTy)) 2247 return AdjustCost(Entry->Cost); 2248 } 2249 2250 if (ST->hasSSE2()) { 2251 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2252 SimpleDstTy, SimpleSrcTy)) 2253 return AdjustCost(Entry->Cost); 2254 } 2255 2256 return AdjustCost( 2257 BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I)); 2258 } 2259 2260 InstructionCost X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 2261 Type *CondTy, 2262 CmpInst::Predicate VecPred, 2263 TTI::TargetCostKind CostKind, 2264 const Instruction *I) { 2265 // TODO: Handle other cost kinds. 2266 if (CostKind != TTI::TCK_RecipThroughput) 2267 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, 2268 I); 2269 2270 // Legalize the type. 2271 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2272 2273 MVT MTy = LT.second; 2274 2275 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2276 assert(ISD && "Invalid opcode"); 2277 2278 unsigned ExtraCost = 0; 2279 if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) { 2280 // Some vector comparison predicates cost extra instructions. 2281 if (MTy.isVector() && 2282 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 2283 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 2284 ST->hasBWI())) { 2285 switch (cast<CmpInst>(I)->getPredicate()) { 2286 case CmpInst::Predicate::ICMP_NE: 2287 // xor(cmpeq(x,y),-1) 2288 ExtraCost = 1; 2289 break; 2290 case CmpInst::Predicate::ICMP_SGE: 2291 case CmpInst::Predicate::ICMP_SLE: 2292 // xor(cmpgt(x,y),-1) 2293 ExtraCost = 1; 2294 break; 2295 case CmpInst::Predicate::ICMP_ULT: 2296 case CmpInst::Predicate::ICMP_UGT: 2297 // cmpgt(xor(x,signbit),xor(y,signbit)) 2298 // xor(cmpeq(pmaxu(x,y),x),-1) 2299 ExtraCost = 2; 2300 break; 2301 case CmpInst::Predicate::ICMP_ULE: 2302 case CmpInst::Predicate::ICMP_UGE: 2303 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 2304 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 2305 // cmpeq(psubus(x,y),0) 2306 // cmpeq(pminu(x,y),x) 2307 ExtraCost = 1; 2308 } else { 2309 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 2310 ExtraCost = 3; 2311 } 2312 break; 2313 default: 2314 break; 2315 } 2316 } 2317 } 2318 2319 static const CostTblEntry SLMCostTbl[] = { 2320 // slm pcmpeq/pcmpgt throughput is 2 2321 { ISD::SETCC, MVT::v2i64, 2 }, 2322 }; 2323 2324 static const CostTblEntry AVX512BWCostTbl[] = { 2325 { ISD::SETCC, MVT::v32i16, 1 }, 2326 { ISD::SETCC, MVT::v64i8, 1 }, 2327 2328 { ISD::SELECT, MVT::v32i16, 1 }, 2329 { ISD::SELECT, MVT::v64i8, 1 }, 2330 }; 2331 2332 static const CostTblEntry AVX512CostTbl[] = { 2333 { ISD::SETCC, MVT::v8i64, 1 }, 2334 { ISD::SETCC, MVT::v16i32, 1 }, 2335 { ISD::SETCC, MVT::v8f64, 1 }, 2336 { ISD::SETCC, MVT::v16f32, 1 }, 2337 2338 { ISD::SELECT, MVT::v8i64, 1 }, 2339 { ISD::SELECT, MVT::v16i32, 1 }, 2340 { ISD::SELECT, MVT::v8f64, 1 }, 2341 { ISD::SELECT, MVT::v16f32, 1 }, 2342 2343 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 2344 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 2345 2346 { ISD::SELECT, MVT::v32i16, 2 }, // FIXME: should be 3 2347 { ISD::SELECT, MVT::v64i8, 2 }, // FIXME: should be 3 2348 }; 2349 2350 static const CostTblEntry AVX2CostTbl[] = { 2351 { ISD::SETCC, MVT::v4i64, 1 }, 2352 { ISD::SETCC, MVT::v8i32, 1 }, 2353 { ISD::SETCC, MVT::v16i16, 1 }, 2354 { ISD::SETCC, MVT::v32i8, 1 }, 2355 2356 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 2357 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 2358 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 2359 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 2360 }; 2361 2362 static const CostTblEntry AVX1CostTbl[] = { 2363 { ISD::SETCC, MVT::v4f64, 1 }, 2364 { ISD::SETCC, MVT::v8f32, 1 }, 2365 // AVX1 does not support 8-wide integer compare. 2366 { ISD::SETCC, MVT::v4i64, 4 }, 2367 { ISD::SETCC, MVT::v8i32, 4 }, 2368 { ISD::SETCC, MVT::v16i16, 4 }, 2369 { ISD::SETCC, MVT::v32i8, 4 }, 2370 2371 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 2372 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 2373 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 2374 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 2375 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 2376 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 2377 }; 2378 2379 static const CostTblEntry SSE42CostTbl[] = { 2380 { ISD::SETCC, MVT::v2f64, 1 }, 2381 { ISD::SETCC, MVT::v4f32, 1 }, 2382 { ISD::SETCC, MVT::v2i64, 1 }, 2383 }; 2384 2385 static const CostTblEntry SSE41CostTbl[] = { 2386 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 2387 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 2388 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 2389 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 2390 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 2391 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 2392 }; 2393 2394 static const CostTblEntry SSE2CostTbl[] = { 2395 { ISD::SETCC, MVT::v2f64, 2 }, 2396 { ISD::SETCC, MVT::f64, 1 }, 2397 { ISD::SETCC, MVT::v2i64, 8 }, 2398 { ISD::SETCC, MVT::v4i32, 1 }, 2399 { ISD::SETCC, MVT::v8i16, 1 }, 2400 { ISD::SETCC, MVT::v16i8, 1 }, 2401 2402 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 2403 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 2404 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 2405 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 2406 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 2407 }; 2408 2409 static const CostTblEntry SSE1CostTbl[] = { 2410 { ISD::SETCC, MVT::v4f32, 2 }, 2411 { ISD::SETCC, MVT::f32, 1 }, 2412 2413 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 2414 }; 2415 2416 if (ST->isSLM()) 2417 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2418 return LT.first * (ExtraCost + Entry->Cost); 2419 2420 if (ST->hasBWI()) 2421 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2422 return LT.first * (ExtraCost + Entry->Cost); 2423 2424 if (ST->hasAVX512()) 2425 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2426 return LT.first * (ExtraCost + Entry->Cost); 2427 2428 if (ST->hasAVX2()) 2429 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2430 return LT.first * (ExtraCost + Entry->Cost); 2431 2432 if (ST->hasAVX()) 2433 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2434 return LT.first * (ExtraCost + Entry->Cost); 2435 2436 if (ST->hasSSE42()) 2437 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2438 return LT.first * (ExtraCost + Entry->Cost); 2439 2440 if (ST->hasSSE41()) 2441 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2442 return LT.first * (ExtraCost + Entry->Cost); 2443 2444 if (ST->hasSSE2()) 2445 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2446 return LT.first * (ExtraCost + Entry->Cost); 2447 2448 if (ST->hasSSE1()) 2449 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2450 return LT.first * (ExtraCost + Entry->Cost); 2451 2452 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I); 2453 } 2454 2455 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2456 2457 InstructionCost 2458 X86TTIImpl::getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 2459 TTI::TargetCostKind CostKind) { 2460 2461 // Costs should match the codegen from: 2462 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2463 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2464 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2465 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2466 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2467 2468 // TODO: Overflow intrinsics (*ADDO, *SUBO, *MULO) with vector types are not 2469 // specialized in these tables yet. 2470 static const CostTblEntry AVX512CDCostTbl[] = { 2471 { ISD::CTLZ, MVT::v8i64, 1 }, 2472 { ISD::CTLZ, MVT::v16i32, 1 }, 2473 { ISD::CTLZ, MVT::v32i16, 8 }, 2474 { ISD::CTLZ, MVT::v64i8, 20 }, 2475 { ISD::CTLZ, MVT::v4i64, 1 }, 2476 { ISD::CTLZ, MVT::v8i32, 1 }, 2477 { ISD::CTLZ, MVT::v16i16, 4 }, 2478 { ISD::CTLZ, MVT::v32i8, 10 }, 2479 { ISD::CTLZ, MVT::v2i64, 1 }, 2480 { ISD::CTLZ, MVT::v4i32, 1 }, 2481 { ISD::CTLZ, MVT::v8i16, 4 }, 2482 { ISD::CTLZ, MVT::v16i8, 4 }, 2483 }; 2484 static const CostTblEntry AVX512BWCostTbl[] = { 2485 { ISD::ABS, MVT::v32i16, 1 }, 2486 { ISD::ABS, MVT::v64i8, 1 }, 2487 { ISD::BITREVERSE, MVT::v8i64, 5 }, 2488 { ISD::BITREVERSE, MVT::v16i32, 5 }, 2489 { ISD::BITREVERSE, MVT::v32i16, 5 }, 2490 { ISD::BITREVERSE, MVT::v64i8, 5 }, 2491 { ISD::BSWAP, MVT::v8i64, 1 }, 2492 { ISD::BSWAP, MVT::v16i32, 1 }, 2493 { ISD::BSWAP, MVT::v32i16, 1 }, 2494 { ISD::CTLZ, MVT::v8i64, 23 }, 2495 { ISD::CTLZ, MVT::v16i32, 22 }, 2496 { ISD::CTLZ, MVT::v32i16, 18 }, 2497 { ISD::CTLZ, MVT::v64i8, 17 }, 2498 { ISD::CTPOP, MVT::v8i64, 7 }, 2499 { ISD::CTPOP, MVT::v16i32, 11 }, 2500 { ISD::CTPOP, MVT::v32i16, 9 }, 2501 { ISD::CTPOP, MVT::v64i8, 6 }, 2502 { ISD::CTTZ, MVT::v8i64, 10 }, 2503 { ISD::CTTZ, MVT::v16i32, 14 }, 2504 { ISD::CTTZ, MVT::v32i16, 12 }, 2505 { ISD::CTTZ, MVT::v64i8, 9 }, 2506 { ISD::SADDSAT, MVT::v32i16, 1 }, 2507 { ISD::SADDSAT, MVT::v64i8, 1 }, 2508 { ISD::SMAX, MVT::v32i16, 1 }, 2509 { ISD::SMAX, MVT::v64i8, 1 }, 2510 { ISD::SMIN, MVT::v32i16, 1 }, 2511 { ISD::SMIN, MVT::v64i8, 1 }, 2512 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2513 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2514 { ISD::UADDSAT, MVT::v32i16, 1 }, 2515 { ISD::UADDSAT, MVT::v64i8, 1 }, 2516 { ISD::UMAX, MVT::v32i16, 1 }, 2517 { ISD::UMAX, MVT::v64i8, 1 }, 2518 { ISD::UMIN, MVT::v32i16, 1 }, 2519 { ISD::UMIN, MVT::v64i8, 1 }, 2520 { ISD::USUBSAT, MVT::v32i16, 1 }, 2521 { ISD::USUBSAT, MVT::v64i8, 1 }, 2522 }; 2523 static const CostTblEntry AVX512CostTbl[] = { 2524 { ISD::ABS, MVT::v8i64, 1 }, 2525 { ISD::ABS, MVT::v16i32, 1 }, 2526 { ISD::ABS, MVT::v32i16, 2 }, // FIXME: include split 2527 { ISD::ABS, MVT::v64i8, 2 }, // FIXME: include split 2528 { ISD::ABS, MVT::v4i64, 1 }, 2529 { ISD::ABS, MVT::v2i64, 1 }, 2530 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2531 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2532 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2533 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2534 { ISD::BSWAP, MVT::v8i64, 4 }, 2535 { ISD::BSWAP, MVT::v16i32, 4 }, 2536 { ISD::BSWAP, MVT::v32i16, 4 }, 2537 { ISD::CTLZ, MVT::v8i64, 29 }, 2538 { ISD::CTLZ, MVT::v16i32, 35 }, 2539 { ISD::CTLZ, MVT::v32i16, 28 }, 2540 { ISD::CTLZ, MVT::v64i8, 18 }, 2541 { ISD::CTPOP, MVT::v8i64, 16 }, 2542 { ISD::CTPOP, MVT::v16i32, 24 }, 2543 { ISD::CTPOP, MVT::v32i16, 18 }, 2544 { ISD::CTPOP, MVT::v64i8, 12 }, 2545 { ISD::CTTZ, MVT::v8i64, 20 }, 2546 { ISD::CTTZ, MVT::v16i32, 28 }, 2547 { ISD::CTTZ, MVT::v32i16, 24 }, 2548 { ISD::CTTZ, MVT::v64i8, 18 }, 2549 { ISD::SMAX, MVT::v8i64, 1 }, 2550 { ISD::SMAX, MVT::v16i32, 1 }, 2551 { ISD::SMAX, MVT::v32i16, 2 }, // FIXME: include split 2552 { ISD::SMAX, MVT::v64i8, 2 }, // FIXME: include split 2553 { ISD::SMAX, MVT::v4i64, 1 }, 2554 { ISD::SMAX, MVT::v2i64, 1 }, 2555 { ISD::SMIN, MVT::v8i64, 1 }, 2556 { ISD::SMIN, MVT::v16i32, 1 }, 2557 { ISD::SMIN, MVT::v32i16, 2 }, // FIXME: include split 2558 { ISD::SMIN, MVT::v64i8, 2 }, // FIXME: include split 2559 { ISD::SMIN, MVT::v4i64, 1 }, 2560 { ISD::SMIN, MVT::v2i64, 1 }, 2561 { ISD::UMAX, MVT::v8i64, 1 }, 2562 { ISD::UMAX, MVT::v16i32, 1 }, 2563 { ISD::UMAX, MVT::v32i16, 2 }, // FIXME: include split 2564 { ISD::UMAX, MVT::v64i8, 2 }, // FIXME: include split 2565 { ISD::UMAX, MVT::v4i64, 1 }, 2566 { ISD::UMAX, MVT::v2i64, 1 }, 2567 { ISD::UMIN, MVT::v8i64, 1 }, 2568 { ISD::UMIN, MVT::v16i32, 1 }, 2569 { ISD::UMIN, MVT::v32i16, 2 }, // FIXME: include split 2570 { ISD::UMIN, MVT::v64i8, 2 }, // FIXME: include split 2571 { ISD::UMIN, MVT::v4i64, 1 }, 2572 { ISD::UMIN, MVT::v2i64, 1 }, 2573 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2574 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2575 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2576 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2577 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2578 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2579 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2580 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2581 { ISD::SADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2582 { ISD::SADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2583 { ISD::SSUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2584 { ISD::SSUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2585 { ISD::UADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2586 { ISD::UADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2587 { ISD::USUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2588 { ISD::USUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2589 { ISD::FMAXNUM, MVT::f32, 2 }, 2590 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2591 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2592 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2593 { ISD::FMAXNUM, MVT::f64, 2 }, 2594 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2595 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2596 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2597 }; 2598 static const CostTblEntry XOPCostTbl[] = { 2599 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2600 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2601 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2602 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2603 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2604 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2605 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2606 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2607 { ISD::BITREVERSE, MVT::i64, 3 }, 2608 { ISD::BITREVERSE, MVT::i32, 3 }, 2609 { ISD::BITREVERSE, MVT::i16, 3 }, 2610 { ISD::BITREVERSE, MVT::i8, 3 } 2611 }; 2612 static const CostTblEntry AVX2CostTbl[] = { 2613 { ISD::ABS, MVT::v4i64, 2 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2614 { ISD::ABS, MVT::v8i32, 1 }, 2615 { ISD::ABS, MVT::v16i16, 1 }, 2616 { ISD::ABS, MVT::v32i8, 1 }, 2617 { ISD::BITREVERSE, MVT::v4i64, 5 }, 2618 { ISD::BITREVERSE, MVT::v8i32, 5 }, 2619 { ISD::BITREVERSE, MVT::v16i16, 5 }, 2620 { ISD::BITREVERSE, MVT::v32i8, 5 }, 2621 { ISD::BSWAP, MVT::v4i64, 1 }, 2622 { ISD::BSWAP, MVT::v8i32, 1 }, 2623 { ISD::BSWAP, MVT::v16i16, 1 }, 2624 { ISD::CTLZ, MVT::v4i64, 23 }, 2625 { ISD::CTLZ, MVT::v8i32, 18 }, 2626 { ISD::CTLZ, MVT::v16i16, 14 }, 2627 { ISD::CTLZ, MVT::v32i8, 9 }, 2628 { ISD::CTPOP, MVT::v4i64, 7 }, 2629 { ISD::CTPOP, MVT::v8i32, 11 }, 2630 { ISD::CTPOP, MVT::v16i16, 9 }, 2631 { ISD::CTPOP, MVT::v32i8, 6 }, 2632 { ISD::CTTZ, MVT::v4i64, 10 }, 2633 { ISD::CTTZ, MVT::v8i32, 14 }, 2634 { ISD::CTTZ, MVT::v16i16, 12 }, 2635 { ISD::CTTZ, MVT::v32i8, 9 }, 2636 { ISD::SADDSAT, MVT::v16i16, 1 }, 2637 { ISD::SADDSAT, MVT::v32i8, 1 }, 2638 { ISD::SMAX, MVT::v8i32, 1 }, 2639 { ISD::SMAX, MVT::v16i16, 1 }, 2640 { ISD::SMAX, MVT::v32i8, 1 }, 2641 { ISD::SMIN, MVT::v8i32, 1 }, 2642 { ISD::SMIN, MVT::v16i16, 1 }, 2643 { ISD::SMIN, MVT::v32i8, 1 }, 2644 { ISD::SSUBSAT, MVT::v16i16, 1 }, 2645 { ISD::SSUBSAT, MVT::v32i8, 1 }, 2646 { ISD::UADDSAT, MVT::v16i16, 1 }, 2647 { ISD::UADDSAT, MVT::v32i8, 1 }, 2648 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 2649 { ISD::UMAX, MVT::v8i32, 1 }, 2650 { ISD::UMAX, MVT::v16i16, 1 }, 2651 { ISD::UMAX, MVT::v32i8, 1 }, 2652 { ISD::UMIN, MVT::v8i32, 1 }, 2653 { ISD::UMIN, MVT::v16i16, 1 }, 2654 { ISD::UMIN, MVT::v32i8, 1 }, 2655 { ISD::USUBSAT, MVT::v16i16, 1 }, 2656 { ISD::USUBSAT, MVT::v32i8, 1 }, 2657 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2658 { ISD::FMAXNUM, MVT::v8f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2659 { ISD::FMAXNUM, MVT::v4f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2660 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2661 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2662 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2663 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2664 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2665 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2666 }; 2667 static const CostTblEntry AVX1CostTbl[] = { 2668 { ISD::ABS, MVT::v4i64, 5 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2669 { ISD::ABS, MVT::v8i32, 3 }, 2670 { ISD::ABS, MVT::v16i16, 3 }, 2671 { ISD::ABS, MVT::v32i8, 3 }, 2672 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 2673 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 2674 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 2675 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 2676 { ISD::BSWAP, MVT::v4i64, 4 }, 2677 { ISD::BSWAP, MVT::v8i32, 4 }, 2678 { ISD::BSWAP, MVT::v16i16, 4 }, 2679 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 2680 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 2681 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 2682 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2683 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 2684 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 2685 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 2686 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 2687 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 2688 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 2689 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 2690 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2691 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2692 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2693 { ISD::SMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2694 { ISD::SMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2695 { ISD::SMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2696 { ISD::SMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2697 { ISD::SMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2698 { ISD::SMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2699 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2700 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2701 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2702 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2703 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 2704 { ISD::UMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2705 { ISD::UMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2706 { ISD::UMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2707 { ISD::UMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2708 { ISD::UMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2709 { ISD::UMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2710 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2711 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2712 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 2713 { ISD::FMAXNUM, MVT::f32, 3 }, // MAXSS + CMPUNORDSS + BLENDVPS 2714 { ISD::FMAXNUM, MVT::v4f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2715 { ISD::FMAXNUM, MVT::v8f32, 5 }, // MAXPS + CMPUNORDPS + BLENDVPS + ? 2716 { ISD::FMAXNUM, MVT::f64, 3 }, // MAXSD + CMPUNORDSD + BLENDVPD 2717 { ISD::FMAXNUM, MVT::v2f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2718 { ISD::FMAXNUM, MVT::v4f64, 5 }, // MAXPD + CMPUNORDPD + BLENDVPD + ? 2719 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 2720 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 2721 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 2722 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 2723 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 2724 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 2725 }; 2726 static const CostTblEntry GLMCostTbl[] = { 2727 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 2728 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 2729 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 2730 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 2731 }; 2732 static const CostTblEntry SLMCostTbl[] = { 2733 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 2734 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 2735 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 2736 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 2737 }; 2738 static const CostTblEntry SSE42CostTbl[] = { 2739 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 2740 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 2741 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 2742 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 2743 }; 2744 static const CostTblEntry SSE41CostTbl[] = { 2745 { ISD::ABS, MVT::v2i64, 2 }, // BLENDVPD(X,PSUBQ(0,X),X) 2746 { ISD::SMAX, MVT::v4i32, 1 }, 2747 { ISD::SMAX, MVT::v16i8, 1 }, 2748 { ISD::SMIN, MVT::v4i32, 1 }, 2749 { ISD::SMIN, MVT::v16i8, 1 }, 2750 { ISD::UMAX, MVT::v4i32, 1 }, 2751 { ISD::UMAX, MVT::v8i16, 1 }, 2752 { ISD::UMIN, MVT::v4i32, 1 }, 2753 { ISD::UMIN, MVT::v8i16, 1 }, 2754 }; 2755 static const CostTblEntry SSSE3CostTbl[] = { 2756 { ISD::ABS, MVT::v4i32, 1 }, 2757 { ISD::ABS, MVT::v8i16, 1 }, 2758 { ISD::ABS, MVT::v16i8, 1 }, 2759 { ISD::BITREVERSE, MVT::v2i64, 5 }, 2760 { ISD::BITREVERSE, MVT::v4i32, 5 }, 2761 { ISD::BITREVERSE, MVT::v8i16, 5 }, 2762 { ISD::BITREVERSE, MVT::v16i8, 5 }, 2763 { ISD::BSWAP, MVT::v2i64, 1 }, 2764 { ISD::BSWAP, MVT::v4i32, 1 }, 2765 { ISD::BSWAP, MVT::v8i16, 1 }, 2766 { ISD::CTLZ, MVT::v2i64, 23 }, 2767 { ISD::CTLZ, MVT::v4i32, 18 }, 2768 { ISD::CTLZ, MVT::v8i16, 14 }, 2769 { ISD::CTLZ, MVT::v16i8, 9 }, 2770 { ISD::CTPOP, MVT::v2i64, 7 }, 2771 { ISD::CTPOP, MVT::v4i32, 11 }, 2772 { ISD::CTPOP, MVT::v8i16, 9 }, 2773 { ISD::CTPOP, MVT::v16i8, 6 }, 2774 { ISD::CTTZ, MVT::v2i64, 10 }, 2775 { ISD::CTTZ, MVT::v4i32, 14 }, 2776 { ISD::CTTZ, MVT::v8i16, 12 }, 2777 { ISD::CTTZ, MVT::v16i8, 9 } 2778 }; 2779 static const CostTblEntry SSE2CostTbl[] = { 2780 { ISD::ABS, MVT::v2i64, 4 }, 2781 { ISD::ABS, MVT::v4i32, 3 }, 2782 { ISD::ABS, MVT::v8i16, 2 }, 2783 { ISD::ABS, MVT::v16i8, 2 }, 2784 { ISD::BITREVERSE, MVT::v2i64, 29 }, 2785 { ISD::BITREVERSE, MVT::v4i32, 27 }, 2786 { ISD::BITREVERSE, MVT::v8i16, 27 }, 2787 { ISD::BITREVERSE, MVT::v16i8, 20 }, 2788 { ISD::BSWAP, MVT::v2i64, 7 }, 2789 { ISD::BSWAP, MVT::v4i32, 7 }, 2790 { ISD::BSWAP, MVT::v8i16, 7 }, 2791 { ISD::CTLZ, MVT::v2i64, 25 }, 2792 { ISD::CTLZ, MVT::v4i32, 26 }, 2793 { ISD::CTLZ, MVT::v8i16, 20 }, 2794 { ISD::CTLZ, MVT::v16i8, 17 }, 2795 { ISD::CTPOP, MVT::v2i64, 12 }, 2796 { ISD::CTPOP, MVT::v4i32, 15 }, 2797 { ISD::CTPOP, MVT::v8i16, 13 }, 2798 { ISD::CTPOP, MVT::v16i8, 10 }, 2799 { ISD::CTTZ, MVT::v2i64, 14 }, 2800 { ISD::CTTZ, MVT::v4i32, 18 }, 2801 { ISD::CTTZ, MVT::v8i16, 16 }, 2802 { ISD::CTTZ, MVT::v16i8, 13 }, 2803 { ISD::SADDSAT, MVT::v8i16, 1 }, 2804 { ISD::SADDSAT, MVT::v16i8, 1 }, 2805 { ISD::SMAX, MVT::v8i16, 1 }, 2806 { ISD::SMIN, MVT::v8i16, 1 }, 2807 { ISD::SSUBSAT, MVT::v8i16, 1 }, 2808 { ISD::SSUBSAT, MVT::v16i8, 1 }, 2809 { ISD::UADDSAT, MVT::v8i16, 1 }, 2810 { ISD::UADDSAT, MVT::v16i8, 1 }, 2811 { ISD::UMAX, MVT::v8i16, 2 }, 2812 { ISD::UMAX, MVT::v16i8, 1 }, 2813 { ISD::UMIN, MVT::v8i16, 2 }, 2814 { ISD::UMIN, MVT::v16i8, 1 }, 2815 { ISD::USUBSAT, MVT::v8i16, 1 }, 2816 { ISD::USUBSAT, MVT::v16i8, 1 }, 2817 { ISD::FMAXNUM, MVT::f64, 4 }, 2818 { ISD::FMAXNUM, MVT::v2f64, 4 }, 2819 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 2820 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 2821 }; 2822 static const CostTblEntry SSE1CostTbl[] = { 2823 { ISD::FMAXNUM, MVT::f32, 4 }, 2824 { ISD::FMAXNUM, MVT::v4f32, 4 }, 2825 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 2826 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 2827 }; 2828 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 2829 { ISD::CTTZ, MVT::i64, 1 }, 2830 }; 2831 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 2832 { ISD::CTTZ, MVT::i32, 1 }, 2833 { ISD::CTTZ, MVT::i16, 1 }, 2834 { ISD::CTTZ, MVT::i8, 1 }, 2835 }; 2836 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 2837 { ISD::CTLZ, MVT::i64, 1 }, 2838 }; 2839 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 2840 { ISD::CTLZ, MVT::i32, 1 }, 2841 { ISD::CTLZ, MVT::i16, 1 }, 2842 { ISD::CTLZ, MVT::i8, 1 }, 2843 }; 2844 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 2845 { ISD::CTPOP, MVT::i64, 1 }, 2846 }; 2847 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 2848 { ISD::CTPOP, MVT::i32, 1 }, 2849 { ISD::CTPOP, MVT::i16, 1 }, 2850 { ISD::CTPOP, MVT::i8, 1 }, 2851 }; 2852 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2853 { ISD::ABS, MVT::i64, 2 }, // SUB+CMOV 2854 { ISD::BITREVERSE, MVT::i64, 14 }, 2855 { ISD::BSWAP, MVT::i64, 1 }, 2856 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 2857 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 2858 { ISD::CTPOP, MVT::i64, 10 }, 2859 { ISD::SADDO, MVT::i64, 1 }, 2860 { ISD::UADDO, MVT::i64, 1 }, 2861 { ISD::UMULO, MVT::i64, 2 }, // mulq + seto 2862 }; 2863 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2864 { ISD::ABS, MVT::i32, 2 }, // SUB+CMOV 2865 { ISD::ABS, MVT::i16, 2 }, // SUB+CMOV 2866 { ISD::BITREVERSE, MVT::i32, 14 }, 2867 { ISD::BITREVERSE, MVT::i16, 14 }, 2868 { ISD::BITREVERSE, MVT::i8, 11 }, 2869 { ISD::BSWAP, MVT::i32, 1 }, 2870 { ISD::BSWAP, MVT::i16, 1 }, // ROL 2871 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 2872 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 2873 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 2874 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 2875 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 2876 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 2877 { ISD::CTPOP, MVT::i32, 8 }, 2878 { ISD::CTPOP, MVT::i16, 9 }, 2879 { ISD::CTPOP, MVT::i8, 7 }, 2880 { ISD::SADDO, MVT::i32, 1 }, 2881 { ISD::SADDO, MVT::i16, 1 }, 2882 { ISD::SADDO, MVT::i8, 1 }, 2883 { ISD::UADDO, MVT::i32, 1 }, 2884 { ISD::UADDO, MVT::i16, 1 }, 2885 { ISD::UADDO, MVT::i8, 1 }, 2886 { ISD::UMULO, MVT::i32, 2 }, // mul + seto 2887 { ISD::UMULO, MVT::i16, 2 }, 2888 { ISD::UMULO, MVT::i8, 2 }, 2889 }; 2890 2891 Type *RetTy = ICA.getReturnType(); 2892 Type *OpTy = RetTy; 2893 Intrinsic::ID IID = ICA.getID(); 2894 unsigned ISD = ISD::DELETED_NODE; 2895 switch (IID) { 2896 default: 2897 break; 2898 case Intrinsic::abs: 2899 ISD = ISD::ABS; 2900 break; 2901 case Intrinsic::bitreverse: 2902 ISD = ISD::BITREVERSE; 2903 break; 2904 case Intrinsic::bswap: 2905 ISD = ISD::BSWAP; 2906 break; 2907 case Intrinsic::ctlz: 2908 ISD = ISD::CTLZ; 2909 break; 2910 case Intrinsic::ctpop: 2911 ISD = ISD::CTPOP; 2912 break; 2913 case Intrinsic::cttz: 2914 ISD = ISD::CTTZ; 2915 break; 2916 case Intrinsic::maxnum: 2917 case Intrinsic::minnum: 2918 // FMINNUM has same costs so don't duplicate. 2919 ISD = ISD::FMAXNUM; 2920 break; 2921 case Intrinsic::sadd_sat: 2922 ISD = ISD::SADDSAT; 2923 break; 2924 case Intrinsic::smax: 2925 ISD = ISD::SMAX; 2926 break; 2927 case Intrinsic::smin: 2928 ISD = ISD::SMIN; 2929 break; 2930 case Intrinsic::ssub_sat: 2931 ISD = ISD::SSUBSAT; 2932 break; 2933 case Intrinsic::uadd_sat: 2934 ISD = ISD::UADDSAT; 2935 break; 2936 case Intrinsic::umax: 2937 ISD = ISD::UMAX; 2938 break; 2939 case Intrinsic::umin: 2940 ISD = ISD::UMIN; 2941 break; 2942 case Intrinsic::usub_sat: 2943 ISD = ISD::USUBSAT; 2944 break; 2945 case Intrinsic::sqrt: 2946 ISD = ISD::FSQRT; 2947 break; 2948 case Intrinsic::sadd_with_overflow: 2949 case Intrinsic::ssub_with_overflow: 2950 // SSUBO has same costs so don't duplicate. 2951 ISD = ISD::SADDO; 2952 OpTy = RetTy->getContainedType(0); 2953 break; 2954 case Intrinsic::uadd_with_overflow: 2955 case Intrinsic::usub_with_overflow: 2956 // USUBO has same costs so don't duplicate. 2957 ISD = ISD::UADDO; 2958 OpTy = RetTy->getContainedType(0); 2959 break; 2960 case Intrinsic::umul_with_overflow: 2961 case Intrinsic::smul_with_overflow: 2962 // SMULO has same costs so don't duplicate. 2963 ISD = ISD::UMULO; 2964 OpTy = RetTy->getContainedType(0); 2965 break; 2966 } 2967 2968 if (ISD != ISD::DELETED_NODE) { 2969 // Legalize the type. 2970 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 2971 MVT MTy = LT.second; 2972 2973 // Attempt to lookup cost. 2974 if (ISD == ISD::BITREVERSE && ST->hasGFNI() && ST->hasSSSE3() && 2975 MTy.isVector()) { 2976 // With PSHUFB the code is very similar for all types. If we have integer 2977 // byte operations, we just need a GF2P8AFFINEQB for vXi8. For other types 2978 // we also need a PSHUFB. 2979 unsigned Cost = MTy.getVectorElementType() == MVT::i8 ? 1 : 2; 2980 2981 // Without byte operations, we need twice as many GF2P8AFFINEQB and PSHUFB 2982 // instructions. We also need an extract and an insert. 2983 if (!(MTy.is128BitVector() || (ST->hasAVX2() && MTy.is256BitVector()) || 2984 (ST->hasBWI() && MTy.is512BitVector()))) 2985 Cost = Cost * 2 + 2; 2986 2987 return LT.first * Cost; 2988 } 2989 2990 auto adjustTableCost = [](const CostTblEntry &Entry, 2991 InstructionCost LegalizationCost, 2992 FastMathFlags FMF) { 2993 // If there are no NANs to deal with, then these are reduced to a 2994 // single MIN** or MAX** instruction instead of the MIN/CMP/SELECT that we 2995 // assume is used in the non-fast case. 2996 if (Entry.ISD == ISD::FMAXNUM || Entry.ISD == ISD::FMINNUM) { 2997 if (FMF.noNaNs()) 2998 return LegalizationCost * 1; 2999 } 3000 return LegalizationCost * (int)Entry.Cost; 3001 }; 3002 3003 if (ST->useGLMDivSqrtCosts()) 3004 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 3005 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3006 3007 if (ST->isSLM()) 3008 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 3009 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3010 3011 if (ST->hasCDI()) 3012 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 3013 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3014 3015 if (ST->hasBWI()) 3016 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3017 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3018 3019 if (ST->hasAVX512()) 3020 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3021 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3022 3023 if (ST->hasXOP()) 3024 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3025 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3026 3027 if (ST->hasAVX2()) 3028 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3029 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3030 3031 if (ST->hasAVX()) 3032 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3033 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3034 3035 if (ST->hasSSE42()) 3036 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3037 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3038 3039 if (ST->hasSSE41()) 3040 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3041 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3042 3043 if (ST->hasSSSE3()) 3044 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 3045 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3046 3047 if (ST->hasSSE2()) 3048 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3049 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3050 3051 if (ST->hasSSE1()) 3052 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3053 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3054 3055 if (ST->hasBMI()) { 3056 if (ST->is64Bit()) 3057 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 3058 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3059 3060 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 3061 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3062 } 3063 3064 if (ST->hasLZCNT()) { 3065 if (ST->is64Bit()) 3066 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 3067 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3068 3069 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 3070 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3071 } 3072 3073 if (ST->hasPOPCNT()) { 3074 if (ST->is64Bit()) 3075 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 3076 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3077 3078 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 3079 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3080 } 3081 3082 if (ISD == ISD::BSWAP && ST->hasMOVBE() && ST->hasFastMOVBE()) { 3083 if (const Instruction *II = ICA.getInst()) { 3084 if (II->hasOneUse() && isa<StoreInst>(II->user_back())) 3085 return TTI::TCC_Free; 3086 if (auto *LI = dyn_cast<LoadInst>(II->getOperand(0))) { 3087 if (LI->hasOneUse()) 3088 return TTI::TCC_Free; 3089 } 3090 } 3091 } 3092 3093 // TODO - add BMI (TZCNT) scalar handling 3094 3095 if (ST->is64Bit()) 3096 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3097 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3098 3099 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3100 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3101 } 3102 3103 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3104 } 3105 3106 InstructionCost 3107 X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 3108 TTI::TargetCostKind CostKind) { 3109 if (ICA.isTypeBasedOnly()) 3110 return getTypeBasedIntrinsicInstrCost(ICA, CostKind); 3111 3112 static const CostTblEntry AVX512CostTbl[] = { 3113 { ISD::ROTL, MVT::v8i64, 1 }, 3114 { ISD::ROTL, MVT::v4i64, 1 }, 3115 { ISD::ROTL, MVT::v2i64, 1 }, 3116 { ISD::ROTL, MVT::v16i32, 1 }, 3117 { ISD::ROTL, MVT::v8i32, 1 }, 3118 { ISD::ROTL, MVT::v4i32, 1 }, 3119 { ISD::ROTR, MVT::v8i64, 1 }, 3120 { ISD::ROTR, MVT::v4i64, 1 }, 3121 { ISD::ROTR, MVT::v2i64, 1 }, 3122 { ISD::ROTR, MVT::v16i32, 1 }, 3123 { ISD::ROTR, MVT::v8i32, 1 }, 3124 { ISD::ROTR, MVT::v4i32, 1 } 3125 }; 3126 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 3127 static const CostTblEntry XOPCostTbl[] = { 3128 { ISD::ROTL, MVT::v4i64, 4 }, 3129 { ISD::ROTL, MVT::v8i32, 4 }, 3130 { ISD::ROTL, MVT::v16i16, 4 }, 3131 { ISD::ROTL, MVT::v32i8, 4 }, 3132 { ISD::ROTL, MVT::v2i64, 1 }, 3133 { ISD::ROTL, MVT::v4i32, 1 }, 3134 { ISD::ROTL, MVT::v8i16, 1 }, 3135 { ISD::ROTL, MVT::v16i8, 1 }, 3136 { ISD::ROTR, MVT::v4i64, 6 }, 3137 { ISD::ROTR, MVT::v8i32, 6 }, 3138 { ISD::ROTR, MVT::v16i16, 6 }, 3139 { ISD::ROTR, MVT::v32i8, 6 }, 3140 { ISD::ROTR, MVT::v2i64, 2 }, 3141 { ISD::ROTR, MVT::v4i32, 2 }, 3142 { ISD::ROTR, MVT::v8i16, 2 }, 3143 { ISD::ROTR, MVT::v16i8, 2 } 3144 }; 3145 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 3146 { ISD::ROTL, MVT::i64, 1 }, 3147 { ISD::ROTR, MVT::i64, 1 }, 3148 { ISD::FSHL, MVT::i64, 4 } 3149 }; 3150 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 3151 { ISD::ROTL, MVT::i32, 1 }, 3152 { ISD::ROTL, MVT::i16, 1 }, 3153 { ISD::ROTL, MVT::i8, 1 }, 3154 { ISD::ROTR, MVT::i32, 1 }, 3155 { ISD::ROTR, MVT::i16, 1 }, 3156 { ISD::ROTR, MVT::i8, 1 }, 3157 { ISD::FSHL, MVT::i32, 4 }, 3158 { ISD::FSHL, MVT::i16, 4 }, 3159 { ISD::FSHL, MVT::i8, 4 } 3160 }; 3161 3162 Intrinsic::ID IID = ICA.getID(); 3163 Type *RetTy = ICA.getReturnType(); 3164 const SmallVectorImpl<const Value *> &Args = ICA.getArgs(); 3165 unsigned ISD = ISD::DELETED_NODE; 3166 switch (IID) { 3167 default: 3168 break; 3169 case Intrinsic::fshl: 3170 ISD = ISD::FSHL; 3171 if (Args[0] == Args[1]) 3172 ISD = ISD::ROTL; 3173 break; 3174 case Intrinsic::fshr: 3175 // FSHR has same costs so don't duplicate. 3176 ISD = ISD::FSHL; 3177 if (Args[0] == Args[1]) 3178 ISD = ISD::ROTR; 3179 break; 3180 } 3181 3182 if (ISD != ISD::DELETED_NODE) { 3183 // Legalize the type. 3184 std::pair<InstructionCost, MVT> LT = 3185 TLI->getTypeLegalizationCost(DL, RetTy); 3186 MVT MTy = LT.second; 3187 3188 // Attempt to lookup cost. 3189 if (ST->hasAVX512()) 3190 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3191 return LT.first * Entry->Cost; 3192 3193 if (ST->hasXOP()) 3194 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3195 return LT.first * Entry->Cost; 3196 3197 if (ST->is64Bit()) 3198 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3199 return LT.first * Entry->Cost; 3200 3201 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3202 return LT.first * Entry->Cost; 3203 } 3204 3205 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3206 } 3207 3208 InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, 3209 unsigned Index) { 3210 static const CostTblEntry SLMCostTbl[] = { 3211 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 3212 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 3213 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 3214 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 3215 }; 3216 3217 assert(Val->isVectorTy() && "This must be a vector type"); 3218 Type *ScalarType = Val->getScalarType(); 3219 int RegisterFileMoveCost = 0; 3220 3221 if (Index != -1U && (Opcode == Instruction::ExtractElement || 3222 Opcode == Instruction::InsertElement)) { 3223 // Legalize the type. 3224 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 3225 3226 // This type is legalized to a scalar type. 3227 if (!LT.second.isVector()) 3228 return 0; 3229 3230 // The type may be split. Normalize the index to the new type. 3231 unsigned NumElts = LT.second.getVectorNumElements(); 3232 unsigned SubNumElts = NumElts; 3233 Index = Index % NumElts; 3234 3235 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 3236 // For inserts, we also need to insert the subvector back. 3237 if (LT.second.getSizeInBits() > 128) { 3238 assert((LT.second.getSizeInBits() % 128) == 0 && "Illegal vector"); 3239 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 3240 SubNumElts = NumElts / NumSubVecs; 3241 if (SubNumElts <= Index) { 3242 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 3243 Index %= SubNumElts; 3244 } 3245 } 3246 3247 if (Index == 0) { 3248 // Floating point scalars are already located in index #0. 3249 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 3250 // true for all. 3251 if (ScalarType->isFloatingPointTy()) 3252 return RegisterFileMoveCost; 3253 3254 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 3255 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 3256 return 1 + RegisterFileMoveCost; 3257 } 3258 3259 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3260 assert(ISD && "Unexpected vector opcode"); 3261 MVT MScalarTy = LT.second.getScalarType(); 3262 if (ST->isSLM()) 3263 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 3264 return Entry->Cost + RegisterFileMoveCost; 3265 3266 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 3267 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3268 (MScalarTy.isInteger() && ST->hasSSE41())) 3269 return 1 + RegisterFileMoveCost; 3270 3271 // Assume insertps is relatively cheap on all targets. 3272 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 3273 Opcode == Instruction::InsertElement) 3274 return 1 + RegisterFileMoveCost; 3275 3276 // For extractions we just need to shuffle the element to index 0, which 3277 // should be very cheap (assume cost = 1). For insertions we need to shuffle 3278 // the elements to its destination. In both cases we must handle the 3279 // subvector move(s). 3280 // If the vector type is already less than 128-bits then don't reduce it. 3281 // TODO: Under what circumstances should we shuffle using the full width? 3282 InstructionCost ShuffleCost = 1; 3283 if (Opcode == Instruction::InsertElement) { 3284 auto *SubTy = cast<VectorType>(Val); 3285 EVT VT = TLI->getValueType(DL, Val); 3286 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 3287 SubTy = FixedVectorType::get(ScalarType, SubNumElts); 3288 ShuffleCost = 3289 getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, None, 0, SubTy); 3290 } 3291 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 3292 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 3293 } 3294 3295 // Add to the base cost if we know that the extracted element of a vector is 3296 // destined to be moved to and used in the integer register file. 3297 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 3298 RegisterFileMoveCost += 1; 3299 3300 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 3301 } 3302 3303 InstructionCost X86TTIImpl::getScalarizationOverhead(VectorType *Ty, 3304 const APInt &DemandedElts, 3305 bool Insert, 3306 bool Extract) { 3307 InstructionCost Cost = 0; 3308 3309 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much 3310 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT. 3311 if (Insert) { 3312 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3313 MVT MScalarTy = LT.second.getScalarType(); 3314 3315 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3316 (MScalarTy.isInteger() && ST->hasSSE41()) || 3317 (MScalarTy == MVT::f32 && ST->hasSSE41())) { 3318 // For types we can insert directly, insertion into 128-bit sub vectors is 3319 // cheap, followed by a cheap chain of concatenations. 3320 if (LT.second.getSizeInBits() <= 128) { 3321 Cost += 3322 BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, false); 3323 } else { 3324 // In each 128-lane, if at least one index is demanded but not all 3325 // indices are demanded and this 128-lane is not the first 128-lane of 3326 // the legalized-vector, then this 128-lane needs a extracti128; If in 3327 // each 128-lane, there is at least one demanded index, this 128-lane 3328 // needs a inserti128. 3329 3330 // The following cases will help you build a better understanding: 3331 // Assume we insert several elements into a v8i32 vector in avx2, 3332 // Case#1: inserting into 1th index needs vpinsrd + inserti128. 3333 // Case#2: inserting into 5th index needs extracti128 + vpinsrd + 3334 // inserti128. 3335 // Case#3: inserting into 4,5,6,7 index needs 4*vpinsrd + inserti128. 3336 const int CostValue = *LT.first.getValue(); 3337 assert(CostValue >= 0 && "Negative cost!"); 3338 unsigned Num128Lanes = LT.second.getSizeInBits() / 128 * CostValue; 3339 unsigned NumElts = LT.second.getVectorNumElements() * CostValue; 3340 APInt WidenedDemandedElts = DemandedElts.zextOrSelf(NumElts); 3341 unsigned Scale = NumElts / Num128Lanes; 3342 // We iterate each 128-lane, and check if we need a 3343 // extracti128/inserti128 for this 128-lane. 3344 for (unsigned I = 0; I < NumElts; I += Scale) { 3345 APInt Mask = WidenedDemandedElts.getBitsSet(NumElts, I, I + Scale); 3346 APInt MaskedDE = Mask & WidenedDemandedElts; 3347 unsigned Population = MaskedDE.countPopulation(); 3348 Cost += (Population > 0 && Population != Scale && 3349 I % LT.second.getVectorNumElements() != 0); 3350 Cost += Population > 0; 3351 } 3352 Cost += DemandedElts.countPopulation(); 3353 3354 // For vXf32 cases, insertion into the 0'th index in each v4f32 3355 // 128-bit vector is free. 3356 // NOTE: This assumes legalization widens vXf32 vectors. 3357 if (MScalarTy == MVT::f32) 3358 for (unsigned i = 0, e = cast<FixedVectorType>(Ty)->getNumElements(); 3359 i < e; i += 4) 3360 if (DemandedElts[i]) 3361 Cost--; 3362 } 3363 } else if (LT.second.isVector()) { 3364 // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded 3365 // integer element as a SCALAR_TO_VECTOR, then we build the vector as a 3366 // series of UNPCK followed by CONCAT_VECTORS - all of these can be 3367 // considered cheap. 3368 if (Ty->isIntOrIntVectorTy()) 3369 Cost += DemandedElts.countPopulation(); 3370 3371 // Get the smaller of the legalized or original pow2-extended number of 3372 // vector elements, which represents the number of unpacks we'll end up 3373 // performing. 3374 unsigned NumElts = LT.second.getVectorNumElements(); 3375 unsigned Pow2Elts = 3376 PowerOf2Ceil(cast<FixedVectorType>(Ty)->getNumElements()); 3377 Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first; 3378 } 3379 } 3380 3381 // TODO: Use default extraction for now, but we should investigate extending this 3382 // to handle repeated subvector extraction. 3383 if (Extract) 3384 Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, false, Extract); 3385 3386 return Cost; 3387 } 3388 3389 InstructionCost X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 3390 MaybeAlign Alignment, 3391 unsigned AddressSpace, 3392 TTI::TargetCostKind CostKind, 3393 const Instruction *I) { 3394 // TODO: Handle other cost kinds. 3395 if (CostKind != TTI::TCK_RecipThroughput) { 3396 if (auto *SI = dyn_cast_or_null<StoreInst>(I)) { 3397 // Store instruction with index and scale costs 2 Uops. 3398 // Check the preceding GEP to identify non-const indices. 3399 if (auto *GEP = dyn_cast<GetElementPtrInst>(SI->getPointerOperand())) { 3400 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3401 return TTI::TCC_Basic * 2; 3402 } 3403 } 3404 return TTI::TCC_Basic; 3405 } 3406 3407 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 3408 "Invalid Opcode"); 3409 // Type legalization can't handle structs 3410 if (TLI->getValueType(DL, Src, true) == MVT::Other) 3411 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3412 CostKind); 3413 3414 // Legalize the type. 3415 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 3416 3417 auto *VTy = dyn_cast<FixedVectorType>(Src); 3418 3419 // Handle the simple case of non-vectors. 3420 // NOTE: this assumes that legalization never creates vector from scalars! 3421 if (!VTy || !LT.second.isVector()) 3422 // Each load/store unit costs 1. 3423 return LT.first * 1; 3424 3425 bool IsLoad = Opcode == Instruction::Load; 3426 3427 Type *EltTy = VTy->getElementType(); 3428 3429 const int EltTyBits = DL.getTypeSizeInBits(EltTy); 3430 3431 InstructionCost Cost = 0; 3432 3433 // Source of truth: how many elements were there in the original IR vector? 3434 const unsigned SrcNumElt = VTy->getNumElements(); 3435 3436 // How far have we gotten? 3437 int NumEltRemaining = SrcNumElt; 3438 // Note that we intentionally capture by-reference, NumEltRemaining changes. 3439 auto NumEltDone = [&]() { return SrcNumElt - NumEltRemaining; }; 3440 3441 const int MaxLegalOpSizeBytes = divideCeil(LT.second.getSizeInBits(), 8); 3442 3443 // Note that even if we can store 64 bits of an XMM, we still operate on XMM. 3444 const unsigned XMMBits = 128; 3445 if (XMMBits % EltTyBits != 0) 3446 // Vector size must be a multiple of the element size. I.e. no padding. 3447 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3448 CostKind); 3449 const int NumEltPerXMM = XMMBits / EltTyBits; 3450 3451 auto *XMMVecTy = FixedVectorType::get(EltTy, NumEltPerXMM); 3452 3453 for (int CurrOpSizeBytes = MaxLegalOpSizeBytes, SubVecEltsLeft = 0; 3454 NumEltRemaining > 0; CurrOpSizeBytes /= 2) { 3455 // How many elements would a single op deal with at once? 3456 if ((8 * CurrOpSizeBytes) % EltTyBits != 0) 3457 // Vector size must be a multiple of the element size. I.e. no padding. 3458 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3459 CostKind); 3460 int CurrNumEltPerOp = (8 * CurrOpSizeBytes) / EltTyBits; 3461 3462 assert(CurrOpSizeBytes > 0 && CurrNumEltPerOp > 0 && "How'd we get here?"); 3463 assert((((NumEltRemaining * EltTyBits) < (2 * 8 * CurrOpSizeBytes)) || 3464 (CurrOpSizeBytes == MaxLegalOpSizeBytes)) && 3465 "Unless we haven't halved the op size yet, " 3466 "we have less than two op's sized units of work left."); 3467 3468 auto *CurrVecTy = CurrNumEltPerOp > NumEltPerXMM 3469 ? FixedVectorType::get(EltTy, CurrNumEltPerOp) 3470 : XMMVecTy; 3471 3472 assert(CurrVecTy->getNumElements() % CurrNumEltPerOp == 0 && 3473 "After halving sizes, the vector elt count is no longer a multiple " 3474 "of number of elements per operation?"); 3475 auto *CoalescedVecTy = 3476 CurrNumEltPerOp == 1 3477 ? CurrVecTy 3478 : FixedVectorType::get( 3479 IntegerType::get(Src->getContext(), 3480 EltTyBits * CurrNumEltPerOp), 3481 CurrVecTy->getNumElements() / CurrNumEltPerOp); 3482 assert(DL.getTypeSizeInBits(CoalescedVecTy) == 3483 DL.getTypeSizeInBits(CurrVecTy) && 3484 "coalesciing elements doesn't change vector width."); 3485 3486 while (NumEltRemaining > 0) { 3487 assert(SubVecEltsLeft >= 0 && "Subreg element count overconsumtion?"); 3488 3489 // Can we use this vector size, as per the remaining element count? 3490 // Iff the vector is naturally aligned, we can do a wide load regardless. 3491 if (NumEltRemaining < CurrNumEltPerOp && 3492 (!IsLoad || Alignment.valueOrOne() < CurrOpSizeBytes) && 3493 CurrOpSizeBytes != 1) 3494 break; // Try smalled vector size. 3495 3496 bool Is0thSubVec = (NumEltDone() % LT.second.getVectorNumElements()) == 0; 3497 3498 // If we have fully processed the previous reg, we need to replenish it. 3499 if (SubVecEltsLeft == 0) { 3500 SubVecEltsLeft += CurrVecTy->getNumElements(); 3501 // And that's free only for the 0'th subvector of a legalized vector. 3502 if (!Is0thSubVec) 3503 Cost += getShuffleCost(IsLoad ? TTI::ShuffleKind::SK_InsertSubvector 3504 : TTI::ShuffleKind::SK_ExtractSubvector, 3505 VTy, None, NumEltDone(), CurrVecTy); 3506 } 3507 3508 // While we can directly load/store ZMM, YMM, and 64-bit halves of XMM, 3509 // for smaller widths (32/16/8) we have to insert/extract them separately. 3510 // Again, it's free for the 0'th subreg (if op is 32/64 bit wide, 3511 // but let's pretend that it is also true for 16/8 bit wide ops...) 3512 if (CurrOpSizeBytes <= 32 / 8 && !Is0thSubVec) { 3513 int NumEltDoneInCurrXMM = NumEltDone() % NumEltPerXMM; 3514 assert(NumEltDoneInCurrXMM % CurrNumEltPerOp == 0 && ""); 3515 int CoalescedVecEltIdx = NumEltDoneInCurrXMM / CurrNumEltPerOp; 3516 APInt DemandedElts = 3517 APInt::getBitsSet(CoalescedVecTy->getNumElements(), 3518 CoalescedVecEltIdx, CoalescedVecEltIdx + 1); 3519 assert(DemandedElts.countPopulation() == 1 && "Inserting single value"); 3520 Cost += getScalarizationOverhead(CoalescedVecTy, DemandedElts, IsLoad, 3521 !IsLoad); 3522 } 3523 3524 // This isn't exactly right. We're using slow unaligned 32-byte accesses 3525 // as a proxy for a double-pumped AVX memory interface such as on 3526 // Sandybridge. 3527 if (CurrOpSizeBytes == 32 && ST->isUnalignedMem32Slow()) 3528 Cost += 2; 3529 else 3530 Cost += 1; 3531 3532 SubVecEltsLeft -= CurrNumEltPerOp; 3533 NumEltRemaining -= CurrNumEltPerOp; 3534 Alignment = commonAlignment(Alignment.valueOrOne(), CurrOpSizeBytes); 3535 } 3536 } 3537 3538 assert(NumEltRemaining <= 0 && "Should have processed all the elements."); 3539 3540 return Cost; 3541 } 3542 3543 InstructionCost 3544 X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, Align Alignment, 3545 unsigned AddressSpace, 3546 TTI::TargetCostKind CostKind) { 3547 bool IsLoad = (Instruction::Load == Opcode); 3548 bool IsStore = (Instruction::Store == Opcode); 3549 3550 auto *SrcVTy = dyn_cast<FixedVectorType>(SrcTy); 3551 if (!SrcVTy) 3552 // To calculate scalar take the regular cost, without mask 3553 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace, CostKind); 3554 3555 unsigned NumElem = SrcVTy->getNumElements(); 3556 auto *MaskTy = 3557 FixedVectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 3558 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, Alignment)) || 3559 (IsStore && !isLegalMaskedStore(SrcVTy, Alignment))) { 3560 // Scalarization 3561 APInt DemandedElts = APInt::getAllOnesValue(NumElem); 3562 InstructionCost MaskSplitCost = 3563 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 3564 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 3565 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr, 3566 CmpInst::BAD_ICMP_PREDICATE, CostKind); 3567 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 3568 InstructionCost MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 3569 InstructionCost ValueSplitCost = 3570 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore); 3571 InstructionCost MemopCost = 3572 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3573 Alignment, AddressSpace, CostKind); 3574 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 3575 } 3576 3577 // Legalize the type. 3578 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3579 auto VT = TLI->getValueType(DL, SrcVTy); 3580 InstructionCost Cost = 0; 3581 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 3582 LT.second.getVectorNumElements() == NumElem) 3583 // Promotion requires extend/truncate for data and a shuffle for mask. 3584 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, None, 0, nullptr) + 3585 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, None, 0, nullptr); 3586 3587 else if (LT.first * LT.second.getVectorNumElements() > NumElem) { 3588 auto *NewMaskTy = FixedVectorType::get(MaskTy->getElementType(), 3589 LT.second.getVectorNumElements()); 3590 // Expanding requires fill mask with zeroes 3591 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, None, 0, MaskTy); 3592 } 3593 3594 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 3595 if (!ST->hasAVX512()) 3596 return Cost + LT.first * (IsLoad ? 2 : 8); 3597 3598 // AVX-512 masked load/store is cheapper 3599 return Cost + LT.first; 3600 } 3601 3602 InstructionCost X86TTIImpl::getAddressComputationCost(Type *Ty, 3603 ScalarEvolution *SE, 3604 const SCEV *Ptr) { 3605 // Address computations in vectorized code with non-consecutive addresses will 3606 // likely result in more instructions compared to scalar code where the 3607 // computation can more often be merged into the index mode. The resulting 3608 // extra micro-ops can significantly decrease throughput. 3609 const unsigned NumVectorInstToHideOverhead = 10; 3610 3611 // Cost modeling of Strided Access Computation is hidden by the indexing 3612 // modes of X86 regardless of the stride value. We dont believe that there 3613 // is a difference between constant strided access in gerenal and constant 3614 // strided value which is less than or equal to 64. 3615 // Even in the case of (loop invariant) stride whose value is not known at 3616 // compile time, the address computation will not incur more than one extra 3617 // ADD instruction. 3618 if (Ty->isVectorTy() && SE) { 3619 if (!BaseT::isStridedAccess(Ptr)) 3620 return NumVectorInstToHideOverhead; 3621 if (!BaseT::getConstantStrideStep(SE, Ptr)) 3622 return 1; 3623 } 3624 3625 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 3626 } 3627 3628 InstructionCost 3629 X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 3630 bool IsPairwise, 3631 TTI::TargetCostKind CostKind) { 3632 // Just use the default implementation for pair reductions. 3633 if (IsPairwise) 3634 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise, CostKind); 3635 3636 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3637 // and make it as the cost. 3638 3639 static const CostTblEntry SLMCostTblNoPairWise[] = { 3640 { ISD::FADD, MVT::v2f64, 3 }, 3641 { ISD::ADD, MVT::v2i64, 5 }, 3642 }; 3643 3644 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3645 { ISD::FADD, MVT::v2f64, 2 }, 3646 { ISD::FADD, MVT::v2f32, 2 }, 3647 { ISD::FADD, MVT::v4f32, 4 }, 3648 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 3649 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 3650 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 3651 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 3652 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 3653 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 3654 { ISD::ADD, MVT::v2i8, 2 }, 3655 { ISD::ADD, MVT::v4i8, 2 }, 3656 { ISD::ADD, MVT::v8i8, 2 }, 3657 { ISD::ADD, MVT::v16i8, 3 }, 3658 }; 3659 3660 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3661 { ISD::FADD, MVT::v4f64, 3 }, 3662 { ISD::FADD, MVT::v4f32, 3 }, 3663 { ISD::FADD, MVT::v8f32, 4 }, 3664 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 3665 { ISD::ADD, MVT::v4i64, 3 }, 3666 { ISD::ADD, MVT::v8i32, 5 }, 3667 { ISD::ADD, MVT::v16i16, 5 }, 3668 { ISD::ADD, MVT::v32i8, 4 }, 3669 }; 3670 3671 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3672 assert(ISD && "Invalid opcode"); 3673 3674 // Before legalizing the type, give a chance to look up illegal narrow types 3675 // in the table. 3676 // FIXME: Is there a better way to do this? 3677 EVT VT = TLI->getValueType(DL, ValTy); 3678 if (VT.isSimple()) { 3679 MVT MTy = VT.getSimpleVT(); 3680 if (ST->isSLM()) 3681 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3682 return Entry->Cost; 3683 3684 if (ST->hasAVX()) 3685 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3686 return Entry->Cost; 3687 3688 if (ST->hasSSE2()) 3689 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3690 return Entry->Cost; 3691 } 3692 3693 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3694 3695 MVT MTy = LT.second; 3696 3697 auto *ValVTy = cast<FixedVectorType>(ValTy); 3698 3699 // Special case: vXi8 mul reductions are performed as vXi16. 3700 if (ISD == ISD::MUL && MTy.getScalarType() == MVT::i8) { 3701 auto *WideSclTy = IntegerType::get(ValVTy->getContext(), 16); 3702 auto *WideVecTy = FixedVectorType::get(WideSclTy, ValVTy->getNumElements()); 3703 return getCastInstrCost(Instruction::ZExt, WideVecTy, ValTy, 3704 TargetTransformInfo::CastContextHint::None, 3705 CostKind) + 3706 getArithmeticReductionCost(Opcode, WideVecTy, IsPairwise, CostKind); 3707 } 3708 3709 InstructionCost ArithmeticCost = 0; 3710 if (LT.first != 1 && MTy.isVector() && 3711 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3712 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3713 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3714 MTy.getVectorNumElements()); 3715 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3716 ArithmeticCost *= LT.first - 1; 3717 } 3718 3719 if (ST->isSLM()) 3720 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3721 return ArithmeticCost + Entry->Cost; 3722 3723 if (ST->hasAVX()) 3724 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3725 return ArithmeticCost + Entry->Cost; 3726 3727 if (ST->hasSSE2()) 3728 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3729 return ArithmeticCost + Entry->Cost; 3730 3731 // FIXME: These assume a naive kshift+binop lowering, which is probably 3732 // conservative in most cases. 3733 static const CostTblEntry AVX512BoolReduction[] = { 3734 { ISD::AND, MVT::v2i1, 3 }, 3735 { ISD::AND, MVT::v4i1, 5 }, 3736 { ISD::AND, MVT::v8i1, 7 }, 3737 { ISD::AND, MVT::v16i1, 9 }, 3738 { ISD::AND, MVT::v32i1, 11 }, 3739 { ISD::AND, MVT::v64i1, 13 }, 3740 { ISD::OR, MVT::v2i1, 3 }, 3741 { ISD::OR, MVT::v4i1, 5 }, 3742 { ISD::OR, MVT::v8i1, 7 }, 3743 { ISD::OR, MVT::v16i1, 9 }, 3744 { ISD::OR, MVT::v32i1, 11 }, 3745 { ISD::OR, MVT::v64i1, 13 }, 3746 }; 3747 3748 static const CostTblEntry AVX2BoolReduction[] = { 3749 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 3750 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 3751 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 3752 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 3753 }; 3754 3755 static const CostTblEntry AVX1BoolReduction[] = { 3756 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 3757 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 3758 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3759 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3760 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 3761 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 3762 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3763 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3764 }; 3765 3766 static const CostTblEntry SSE2BoolReduction[] = { 3767 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 3768 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 3769 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 3770 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 3771 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 3772 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 3773 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 3774 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 3775 }; 3776 3777 // Handle bool allof/anyof patterns. 3778 if (ValVTy->getElementType()->isIntegerTy(1)) { 3779 InstructionCost ArithmeticCost = 0; 3780 if (LT.first != 1 && MTy.isVector() && 3781 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3782 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3783 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3784 MTy.getVectorNumElements()); 3785 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3786 ArithmeticCost *= LT.first - 1; 3787 } 3788 3789 if (ST->hasAVX512()) 3790 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 3791 return ArithmeticCost + Entry->Cost; 3792 if (ST->hasAVX2()) 3793 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 3794 return ArithmeticCost + Entry->Cost; 3795 if (ST->hasAVX()) 3796 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 3797 return ArithmeticCost + Entry->Cost; 3798 if (ST->hasSSE2()) 3799 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 3800 return ArithmeticCost + Entry->Cost; 3801 3802 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise, 3803 CostKind); 3804 } 3805 3806 unsigned NumVecElts = ValVTy->getNumElements(); 3807 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 3808 3809 // Special case power of 2 reductions where the scalar type isn't changed 3810 // by type legalization. 3811 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 3812 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise, 3813 CostKind); 3814 3815 InstructionCost ReductionCost = 0; 3816 3817 auto *Ty = ValVTy; 3818 if (LT.first != 1 && MTy.isVector() && 3819 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3820 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3821 Ty = FixedVectorType::get(ValVTy->getElementType(), 3822 MTy.getVectorNumElements()); 3823 ReductionCost = getArithmeticInstrCost(Opcode, Ty, CostKind); 3824 ReductionCost *= LT.first - 1; 3825 NumVecElts = MTy.getVectorNumElements(); 3826 } 3827 3828 // Now handle reduction with the legal type, taking into account size changes 3829 // at each level. 3830 while (NumVecElts > 1) { 3831 // Determine the size of the remaining vector we need to reduce. 3832 unsigned Size = NumVecElts * ScalarSize; 3833 NumVecElts /= 2; 3834 // If we're reducing from 256/512 bits, use an extract_subvector. 3835 if (Size > 128) { 3836 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 3837 ReductionCost += 3838 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 3839 Ty = SubTy; 3840 } else if (Size == 128) { 3841 // Reducing from 128 bits is a permute of v2f64/v2i64. 3842 FixedVectorType *ShufTy; 3843 if (ValVTy->isFloatingPointTy()) 3844 ShufTy = 3845 FixedVectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 3846 else 3847 ShufTy = 3848 FixedVectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 3849 ReductionCost += 3850 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3851 } else if (Size == 64) { 3852 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3853 FixedVectorType *ShufTy; 3854 if (ValVTy->isFloatingPointTy()) 3855 ShufTy = 3856 FixedVectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 3857 else 3858 ShufTy = 3859 FixedVectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 3860 ReductionCost += 3861 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3862 } else { 3863 // Reducing from smaller size is a shift by immediate. 3864 auto *ShiftTy = FixedVectorType::get( 3865 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 3866 ReductionCost += getArithmeticInstrCost( 3867 Instruction::LShr, ShiftTy, CostKind, 3868 TargetTransformInfo::OK_AnyValue, 3869 TargetTransformInfo::OK_UniformConstantValue, 3870 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3871 } 3872 3873 // Add the arithmetic op for this level. 3874 ReductionCost += getArithmeticInstrCost(Opcode, Ty, CostKind); 3875 } 3876 3877 // Add the final extract element to the cost. 3878 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3879 } 3880 3881 InstructionCost X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, 3882 bool IsUnsigned) { 3883 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3884 3885 MVT MTy = LT.second; 3886 3887 int ISD; 3888 if (Ty->isIntOrIntVectorTy()) { 3889 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3890 } else { 3891 assert(Ty->isFPOrFPVectorTy() && 3892 "Expected float point or integer vector type."); 3893 ISD = ISD::FMINNUM; 3894 } 3895 3896 static const CostTblEntry SSE1CostTbl[] = { 3897 {ISD::FMINNUM, MVT::v4f32, 1}, 3898 }; 3899 3900 static const CostTblEntry SSE2CostTbl[] = { 3901 {ISD::FMINNUM, MVT::v2f64, 1}, 3902 {ISD::SMIN, MVT::v8i16, 1}, 3903 {ISD::UMIN, MVT::v16i8, 1}, 3904 }; 3905 3906 static const CostTblEntry SSE41CostTbl[] = { 3907 {ISD::SMIN, MVT::v4i32, 1}, 3908 {ISD::UMIN, MVT::v4i32, 1}, 3909 {ISD::UMIN, MVT::v8i16, 1}, 3910 {ISD::SMIN, MVT::v16i8, 1}, 3911 }; 3912 3913 static const CostTblEntry SSE42CostTbl[] = { 3914 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 3915 }; 3916 3917 static const CostTblEntry AVX1CostTbl[] = { 3918 {ISD::FMINNUM, MVT::v8f32, 1}, 3919 {ISD::FMINNUM, MVT::v4f64, 1}, 3920 {ISD::SMIN, MVT::v8i32, 3}, 3921 {ISD::UMIN, MVT::v8i32, 3}, 3922 {ISD::SMIN, MVT::v16i16, 3}, 3923 {ISD::UMIN, MVT::v16i16, 3}, 3924 {ISD::SMIN, MVT::v32i8, 3}, 3925 {ISD::UMIN, MVT::v32i8, 3}, 3926 }; 3927 3928 static const CostTblEntry AVX2CostTbl[] = { 3929 {ISD::SMIN, MVT::v8i32, 1}, 3930 {ISD::UMIN, MVT::v8i32, 1}, 3931 {ISD::SMIN, MVT::v16i16, 1}, 3932 {ISD::UMIN, MVT::v16i16, 1}, 3933 {ISD::SMIN, MVT::v32i8, 1}, 3934 {ISD::UMIN, MVT::v32i8, 1}, 3935 }; 3936 3937 static const CostTblEntry AVX512CostTbl[] = { 3938 {ISD::FMINNUM, MVT::v16f32, 1}, 3939 {ISD::FMINNUM, MVT::v8f64, 1}, 3940 {ISD::SMIN, MVT::v2i64, 1}, 3941 {ISD::UMIN, MVT::v2i64, 1}, 3942 {ISD::SMIN, MVT::v4i64, 1}, 3943 {ISD::UMIN, MVT::v4i64, 1}, 3944 {ISD::SMIN, MVT::v8i64, 1}, 3945 {ISD::UMIN, MVT::v8i64, 1}, 3946 {ISD::SMIN, MVT::v16i32, 1}, 3947 {ISD::UMIN, MVT::v16i32, 1}, 3948 }; 3949 3950 static const CostTblEntry AVX512BWCostTbl[] = { 3951 {ISD::SMIN, MVT::v32i16, 1}, 3952 {ISD::UMIN, MVT::v32i16, 1}, 3953 {ISD::SMIN, MVT::v64i8, 1}, 3954 {ISD::UMIN, MVT::v64i8, 1}, 3955 }; 3956 3957 // If we have a native MIN/MAX instruction for this type, use it. 3958 if (ST->hasBWI()) 3959 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3960 return LT.first * Entry->Cost; 3961 3962 if (ST->hasAVX512()) 3963 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3964 return LT.first * Entry->Cost; 3965 3966 if (ST->hasAVX2()) 3967 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3968 return LT.first * Entry->Cost; 3969 3970 if (ST->hasAVX()) 3971 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3972 return LT.first * Entry->Cost; 3973 3974 if (ST->hasSSE42()) 3975 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3976 return LT.first * Entry->Cost; 3977 3978 if (ST->hasSSE41()) 3979 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3980 return LT.first * Entry->Cost; 3981 3982 if (ST->hasSSE2()) 3983 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3984 return LT.first * Entry->Cost; 3985 3986 if (ST->hasSSE1()) 3987 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3988 return LT.first * Entry->Cost; 3989 3990 unsigned CmpOpcode; 3991 if (Ty->isFPOrFPVectorTy()) { 3992 CmpOpcode = Instruction::FCmp; 3993 } else { 3994 assert(Ty->isIntOrIntVectorTy() && 3995 "expecting floating point or integer type for min/max reduction"); 3996 CmpOpcode = Instruction::ICmp; 3997 } 3998 3999 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4000 // Otherwise fall back to cmp+select. 4001 InstructionCost Result = 4002 getCmpSelInstrCost(CmpOpcode, Ty, CondTy, CmpInst::BAD_ICMP_PREDICATE, 4003 CostKind) + 4004 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, 4005 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4006 return Result; 4007 } 4008 4009 InstructionCost 4010 X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 4011 bool IsPairwise, bool IsUnsigned, 4012 TTI::TargetCostKind CostKind) { 4013 // Just use the default implementation for pair reductions. 4014 if (IsPairwise) 4015 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned, 4016 CostKind); 4017 4018 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 4019 4020 MVT MTy = LT.second; 4021 4022 int ISD; 4023 if (ValTy->isIntOrIntVectorTy()) { 4024 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 4025 } else { 4026 assert(ValTy->isFPOrFPVectorTy() && 4027 "Expected float point or integer vector type."); 4028 ISD = ISD::FMINNUM; 4029 } 4030 4031 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 4032 // and make it as the cost. 4033 4034 static const CostTblEntry SSE2CostTblNoPairWise[] = { 4035 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 4036 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 4037 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 4038 }; 4039 4040 static const CostTblEntry SSE41CostTblNoPairWise[] = { 4041 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 4042 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 4043 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 4044 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 4045 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 4046 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 4047 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 4048 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 4049 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 4050 {ISD::SMIN, MVT::v16i8, 6}, 4051 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 4052 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 4053 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 4054 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 4055 }; 4056 4057 static const CostTblEntry AVX1CostTblNoPairWise[] = { 4058 {ISD::SMIN, MVT::v16i16, 6}, 4059 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 4060 {ISD::SMIN, MVT::v32i8, 8}, 4061 {ISD::UMIN, MVT::v32i8, 8}, 4062 }; 4063 4064 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 4065 {ISD::SMIN, MVT::v32i16, 8}, 4066 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 4067 {ISD::SMIN, MVT::v64i8, 10}, 4068 {ISD::UMIN, MVT::v64i8, 10}, 4069 }; 4070 4071 // Before legalizing the type, give a chance to look up illegal narrow types 4072 // in the table. 4073 // FIXME: Is there a better way to do this? 4074 EVT VT = TLI->getValueType(DL, ValTy); 4075 if (VT.isSimple()) { 4076 MVT MTy = VT.getSimpleVT(); 4077 if (ST->hasBWI()) 4078 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4079 return Entry->Cost; 4080 4081 if (ST->hasAVX()) 4082 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4083 return Entry->Cost; 4084 4085 if (ST->hasSSE41()) 4086 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4087 return Entry->Cost; 4088 4089 if (ST->hasSSE2()) 4090 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4091 return Entry->Cost; 4092 } 4093 4094 auto *ValVTy = cast<FixedVectorType>(ValTy); 4095 unsigned NumVecElts = ValVTy->getNumElements(); 4096 4097 auto *Ty = ValVTy; 4098 InstructionCost MinMaxCost = 0; 4099 if (LT.first != 1 && MTy.isVector() && 4100 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4101 // Type needs to be split. We need LT.first - 1 operations ops. 4102 Ty = FixedVectorType::get(ValVTy->getElementType(), 4103 MTy.getVectorNumElements()); 4104 auto *SubCondTy = FixedVectorType::get(CondTy->getElementType(), 4105 MTy.getVectorNumElements()); 4106 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4107 MinMaxCost *= LT.first - 1; 4108 NumVecElts = MTy.getVectorNumElements(); 4109 } 4110 4111 if (ST->hasBWI()) 4112 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4113 return MinMaxCost + Entry->Cost; 4114 4115 if (ST->hasAVX()) 4116 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4117 return MinMaxCost + Entry->Cost; 4118 4119 if (ST->hasSSE41()) 4120 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4121 return MinMaxCost + Entry->Cost; 4122 4123 if (ST->hasSSE2()) 4124 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4125 return MinMaxCost + Entry->Cost; 4126 4127 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 4128 4129 // Special case power of 2 reductions where the scalar type isn't changed 4130 // by type legalization. 4131 if (!isPowerOf2_32(ValVTy->getNumElements()) || 4132 ScalarSize != MTy.getScalarSizeInBits()) 4133 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned, 4134 CostKind); 4135 4136 // Now handle reduction with the legal type, taking into account size changes 4137 // at each level. 4138 while (NumVecElts > 1) { 4139 // Determine the size of the remaining vector we need to reduce. 4140 unsigned Size = NumVecElts * ScalarSize; 4141 NumVecElts /= 2; 4142 // If we're reducing from 256/512 bits, use an extract_subvector. 4143 if (Size > 128) { 4144 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 4145 MinMaxCost += 4146 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 4147 Ty = SubTy; 4148 } else if (Size == 128) { 4149 // Reducing from 128 bits is a permute of v2f64/v2i64. 4150 VectorType *ShufTy; 4151 if (ValTy->isFloatingPointTy()) 4152 ShufTy = 4153 FixedVectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 4154 else 4155 ShufTy = FixedVectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 4156 MinMaxCost += 4157 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4158 } else if (Size == 64) { 4159 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 4160 FixedVectorType *ShufTy; 4161 if (ValTy->isFloatingPointTy()) 4162 ShufTy = FixedVectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 4163 else 4164 ShufTy = FixedVectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 4165 MinMaxCost += 4166 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4167 } else { 4168 // Reducing from smaller size is a shift by immediate. 4169 auto *ShiftTy = FixedVectorType::get( 4170 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 4171 MinMaxCost += getArithmeticInstrCost( 4172 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, 4173 TargetTransformInfo::OK_AnyValue, 4174 TargetTransformInfo::OK_UniformConstantValue, 4175 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 4176 } 4177 4178 // Add the arithmetic op for this level. 4179 auto *SubCondTy = 4180 FixedVectorType::get(CondTy->getElementType(), Ty->getNumElements()); 4181 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4182 } 4183 4184 // Add the final extract element to the cost. 4185 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 4186 } 4187 4188 /// Calculate the cost of materializing a 64-bit value. This helper 4189 /// method might only calculate a fraction of a larger immediate. Therefore it 4190 /// is valid to return a cost of ZERO. 4191 InstructionCost X86TTIImpl::getIntImmCost(int64_t Val) { 4192 if (Val == 0) 4193 return TTI::TCC_Free; 4194 4195 if (isInt<32>(Val)) 4196 return TTI::TCC_Basic; 4197 4198 return 2 * TTI::TCC_Basic; 4199 } 4200 4201 InstructionCost X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 4202 TTI::TargetCostKind CostKind) { 4203 assert(Ty->isIntegerTy()); 4204 4205 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4206 if (BitSize == 0) 4207 return ~0U; 4208 4209 // Never hoist constants larger than 128bit, because this might lead to 4210 // incorrect code generation or assertions in codegen. 4211 // Fixme: Create a cost model for types larger than i128 once the codegen 4212 // issues have been fixed. 4213 if (BitSize > 128) 4214 return TTI::TCC_Free; 4215 4216 if (Imm == 0) 4217 return TTI::TCC_Free; 4218 4219 // Sign-extend all constants to a multiple of 64-bit. 4220 APInt ImmVal = Imm; 4221 if (BitSize % 64 != 0) 4222 ImmVal = Imm.sext(alignTo(BitSize, 64)); 4223 4224 // Split the constant into 64-bit chunks and calculate the cost for each 4225 // chunk. 4226 InstructionCost Cost = 0; 4227 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 4228 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 4229 int64_t Val = Tmp.getSExtValue(); 4230 Cost += getIntImmCost(Val); 4231 } 4232 // We need at least one instruction to materialize the constant. 4233 return std::max<InstructionCost>(1, Cost); 4234 } 4235 4236 InstructionCost X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, 4237 const APInt &Imm, Type *Ty, 4238 TTI::TargetCostKind CostKind, 4239 Instruction *Inst) { 4240 assert(Ty->isIntegerTy()); 4241 4242 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4243 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4244 // here, so that constant hoisting will ignore this constant. 4245 if (BitSize == 0) 4246 return TTI::TCC_Free; 4247 4248 unsigned ImmIdx = ~0U; 4249 switch (Opcode) { 4250 default: 4251 return TTI::TCC_Free; 4252 case Instruction::GetElementPtr: 4253 // Always hoist the base address of a GetElementPtr. This prevents the 4254 // creation of new constants for every base constant that gets constant 4255 // folded with the offset. 4256 if (Idx == 0) 4257 return 2 * TTI::TCC_Basic; 4258 return TTI::TCC_Free; 4259 case Instruction::Store: 4260 ImmIdx = 0; 4261 break; 4262 case Instruction::ICmp: 4263 // This is an imperfect hack to prevent constant hoisting of 4264 // compares that might be trying to check if a 64-bit value fits in 4265 // 32-bits. The backend can optimize these cases using a right shift by 32. 4266 // Ideally we would check the compare predicate here. There also other 4267 // similar immediates the backend can use shifts for. 4268 if (Idx == 1 && Imm.getBitWidth() == 64) { 4269 uint64_t ImmVal = Imm.getZExtValue(); 4270 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 4271 return TTI::TCC_Free; 4272 } 4273 ImmIdx = 1; 4274 break; 4275 case Instruction::And: 4276 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 4277 // by using a 32-bit operation with implicit zero extension. Detect such 4278 // immediates here as the normal path expects bit 31 to be sign extended. 4279 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 4280 return TTI::TCC_Free; 4281 ImmIdx = 1; 4282 break; 4283 case Instruction::Add: 4284 case Instruction::Sub: 4285 // For add/sub, we can use the opposite instruction for INT32_MIN. 4286 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 4287 return TTI::TCC_Free; 4288 ImmIdx = 1; 4289 break; 4290 case Instruction::UDiv: 4291 case Instruction::SDiv: 4292 case Instruction::URem: 4293 case Instruction::SRem: 4294 // Division by constant is typically expanded later into a different 4295 // instruction sequence. This completely changes the constants. 4296 // Report them as "free" to stop ConstantHoist from marking them as opaque. 4297 return TTI::TCC_Free; 4298 case Instruction::Mul: 4299 case Instruction::Or: 4300 case Instruction::Xor: 4301 ImmIdx = 1; 4302 break; 4303 // Always return TCC_Free for the shift value of a shift instruction. 4304 case Instruction::Shl: 4305 case Instruction::LShr: 4306 case Instruction::AShr: 4307 if (Idx == 1) 4308 return TTI::TCC_Free; 4309 break; 4310 case Instruction::Trunc: 4311 case Instruction::ZExt: 4312 case Instruction::SExt: 4313 case Instruction::IntToPtr: 4314 case Instruction::PtrToInt: 4315 case Instruction::BitCast: 4316 case Instruction::PHI: 4317 case Instruction::Call: 4318 case Instruction::Select: 4319 case Instruction::Ret: 4320 case Instruction::Load: 4321 break; 4322 } 4323 4324 if (Idx == ImmIdx) { 4325 int NumConstants = divideCeil(BitSize, 64); 4326 InstructionCost Cost = X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4327 return (Cost <= NumConstants * TTI::TCC_Basic) 4328 ? static_cast<int>(TTI::TCC_Free) 4329 : Cost; 4330 } 4331 4332 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4333 } 4334 4335 InstructionCost X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 4336 const APInt &Imm, Type *Ty, 4337 TTI::TargetCostKind CostKind) { 4338 assert(Ty->isIntegerTy()); 4339 4340 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4341 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4342 // here, so that constant hoisting will ignore this constant. 4343 if (BitSize == 0) 4344 return TTI::TCC_Free; 4345 4346 switch (IID) { 4347 default: 4348 return TTI::TCC_Free; 4349 case Intrinsic::sadd_with_overflow: 4350 case Intrinsic::uadd_with_overflow: 4351 case Intrinsic::ssub_with_overflow: 4352 case Intrinsic::usub_with_overflow: 4353 case Intrinsic::smul_with_overflow: 4354 case Intrinsic::umul_with_overflow: 4355 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 4356 return TTI::TCC_Free; 4357 break; 4358 case Intrinsic::experimental_stackmap: 4359 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4360 return TTI::TCC_Free; 4361 break; 4362 case Intrinsic::experimental_patchpoint_void: 4363 case Intrinsic::experimental_patchpoint_i64: 4364 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4365 return TTI::TCC_Free; 4366 break; 4367 } 4368 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4369 } 4370 4371 InstructionCost X86TTIImpl::getCFInstrCost(unsigned Opcode, 4372 TTI::TargetCostKind CostKind, 4373 const Instruction *I) { 4374 if (CostKind != TTI::TCK_RecipThroughput) 4375 return Opcode == Instruction::PHI ? 0 : 1; 4376 // Branches are assumed to be predicted. 4377 return 0; 4378 } 4379 4380 int X86TTIImpl::getGatherOverhead() const { 4381 // Some CPUs have more overhead for gather. The specified overhead is relative 4382 // to the Load operation. "2" is the number provided by Intel architects. This 4383 // parameter is used for cost estimation of Gather Op and comparison with 4384 // other alternatives. 4385 // TODO: Remove the explicit hasAVX512()?, That would mean we would only 4386 // enable gather with a -march. 4387 if (ST->hasAVX512() || (ST->hasAVX2() && ST->hasFastGather())) 4388 return 2; 4389 4390 return 1024; 4391 } 4392 4393 int X86TTIImpl::getScatterOverhead() const { 4394 if (ST->hasAVX512()) 4395 return 2; 4396 4397 return 1024; 4398 } 4399 4400 // Return an average cost of Gather / Scatter instruction, maybe improved later. 4401 // FIXME: Add TargetCostKind support. 4402 InstructionCost X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, 4403 const Value *Ptr, Align Alignment, 4404 unsigned AddressSpace) { 4405 4406 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 4407 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4408 4409 // Try to reduce index size from 64 bit (default for GEP) 4410 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 4411 // operation will use 16 x 64 indices which do not fit in a zmm and needs 4412 // to split. Also check that the base pointer is the same for all lanes, 4413 // and that there's at most one variable index. 4414 auto getIndexSizeInBits = [](const Value *Ptr, const DataLayout &DL) { 4415 unsigned IndexSize = DL.getPointerSizeInBits(); 4416 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 4417 if (IndexSize < 64 || !GEP) 4418 return IndexSize; 4419 4420 unsigned NumOfVarIndices = 0; 4421 const Value *Ptrs = GEP->getPointerOperand(); 4422 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 4423 return IndexSize; 4424 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 4425 if (isa<Constant>(GEP->getOperand(i))) 4426 continue; 4427 Type *IndxTy = GEP->getOperand(i)->getType(); 4428 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 4429 IndxTy = IndexVTy->getElementType(); 4430 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 4431 !isa<SExtInst>(GEP->getOperand(i))) || 4432 ++NumOfVarIndices > 1) 4433 return IndexSize; // 64 4434 } 4435 return (unsigned)32; 4436 }; 4437 4438 // Trying to reduce IndexSize to 32 bits for vector 16. 4439 // By default the IndexSize is equal to pointer size. 4440 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 4441 ? getIndexSizeInBits(Ptr, DL) 4442 : DL.getPointerSizeInBits(); 4443 4444 auto *IndexVTy = FixedVectorType::get( 4445 IntegerType::get(SrcVTy->getContext(), IndexSize), VF); 4446 std::pair<InstructionCost, MVT> IdxsLT = 4447 TLI->getTypeLegalizationCost(DL, IndexVTy); 4448 std::pair<InstructionCost, MVT> SrcLT = 4449 TLI->getTypeLegalizationCost(DL, SrcVTy); 4450 InstructionCost::CostType SplitFactor = 4451 *std::max(IdxsLT.first, SrcLT.first).getValue(); 4452 if (SplitFactor > 1) { 4453 // Handle splitting of vector of pointers 4454 auto *SplitSrcTy = 4455 FixedVectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 4456 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 4457 AddressSpace); 4458 } 4459 4460 // The gather / scatter cost is given by Intel architects. It is a rough 4461 // number since we are looking at one instruction in a time. 4462 const int GSOverhead = (Opcode == Instruction::Load) 4463 ? getGatherOverhead() 4464 : getScatterOverhead(); 4465 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4466 MaybeAlign(Alignment), AddressSpace, 4467 TTI::TCK_RecipThroughput); 4468 } 4469 4470 /// Return the cost of full scalarization of gather / scatter operation. 4471 /// 4472 /// Opcode - Load or Store instruction. 4473 /// SrcVTy - The type of the data vector that should be gathered or scattered. 4474 /// VariableMask - The mask is non-constant at compile time. 4475 /// Alignment - Alignment for one element. 4476 /// AddressSpace - pointer[s] address space. 4477 /// 4478 /// FIXME: Add TargetCostKind support. 4479 InstructionCost X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 4480 bool VariableMask, Align Alignment, 4481 unsigned AddressSpace) { 4482 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4483 APInt DemandedElts = APInt::getAllOnesValue(VF); 4484 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4485 4486 InstructionCost MaskUnpackCost = 0; 4487 if (VariableMask) { 4488 auto *MaskTy = 4489 FixedVectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 4490 MaskUnpackCost = 4491 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 4492 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 4493 Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), nullptr, 4494 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4495 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 4496 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 4497 } 4498 4499 // The cost of the scalar loads/stores. 4500 InstructionCost MemoryOpCost = 4501 VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4502 MaybeAlign(Alignment), AddressSpace, CostKind); 4503 4504 InstructionCost InsertExtractCost = 0; 4505 if (Opcode == Instruction::Load) 4506 for (unsigned i = 0; i < VF; ++i) 4507 // Add the cost of inserting each scalar load into the vector 4508 InsertExtractCost += 4509 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 4510 else 4511 for (unsigned i = 0; i < VF; ++i) 4512 // Add the cost of extracting each element out of the data vector 4513 InsertExtractCost += 4514 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 4515 4516 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 4517 } 4518 4519 /// Calculate the cost of Gather / Scatter operation 4520 InstructionCost X86TTIImpl::getGatherScatterOpCost( 4521 unsigned Opcode, Type *SrcVTy, const Value *Ptr, bool VariableMask, 4522 Align Alignment, TTI::TargetCostKind CostKind, 4523 const Instruction *I = nullptr) { 4524 if (CostKind != TTI::TCK_RecipThroughput) { 4525 if ((Opcode == Instruction::Load && 4526 isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4527 (Opcode == Instruction::Store && 4528 isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4529 return 1; 4530 return BaseT::getGatherScatterOpCost(Opcode, SrcVTy, Ptr, VariableMask, 4531 Alignment, CostKind, I); 4532 } 4533 4534 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 4535 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4536 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 4537 if (!PtrTy && Ptr->getType()->isVectorTy()) 4538 PtrTy = dyn_cast<PointerType>( 4539 cast<VectorType>(Ptr->getType())->getElementType()); 4540 assert(PtrTy && "Unexpected type for Ptr argument"); 4541 unsigned AddressSpace = PtrTy->getAddressSpace(); 4542 4543 bool Scalarize = false; 4544 if ((Opcode == Instruction::Load && 4545 !isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4546 (Opcode == Instruction::Store && 4547 !isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4548 Scalarize = true; 4549 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 4550 // Vector-4 of gather/scatter instruction does not exist on KNL. 4551 // We can extend it to 8 elements, but zeroing upper bits of 4552 // the mask vector will add more instructions. Right now we give the scalar 4553 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 4554 // is better in the VariableMask case. 4555 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 4556 Scalarize = true; 4557 4558 if (Scalarize) 4559 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 4560 AddressSpace); 4561 4562 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 4563 } 4564 4565 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 4566 TargetTransformInfo::LSRCost &C2) { 4567 // X86 specific here are "instruction number 1st priority". 4568 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 4569 C1.NumIVMuls, C1.NumBaseAdds, 4570 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 4571 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 4572 C2.NumIVMuls, C2.NumBaseAdds, 4573 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 4574 } 4575 4576 bool X86TTIImpl::canMacroFuseCmp() { 4577 return ST->hasMacroFusion() || ST->hasBranchFusion(); 4578 } 4579 4580 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, Align Alignment) { 4581 if (!ST->hasAVX()) 4582 return false; 4583 4584 // The backend can't handle a single element vector. 4585 if (isa<VectorType>(DataTy) && 4586 cast<FixedVectorType>(DataTy)->getNumElements() == 1) 4587 return false; 4588 Type *ScalarTy = DataTy->getScalarType(); 4589 4590 if (ScalarTy->isPointerTy()) 4591 return true; 4592 4593 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4594 return true; 4595 4596 if (!ScalarTy->isIntegerTy()) 4597 return false; 4598 4599 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4600 return IntWidth == 32 || IntWidth == 64 || 4601 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 4602 } 4603 4604 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, Align Alignment) { 4605 return isLegalMaskedLoad(DataType, Alignment); 4606 } 4607 4608 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 4609 unsigned DataSize = DL.getTypeStoreSize(DataType); 4610 // The only supported nontemporal loads are for aligned vectors of 16 or 32 4611 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 4612 // (the equivalent stores only require AVX). 4613 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 4614 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 4615 4616 return false; 4617 } 4618 4619 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 4620 unsigned DataSize = DL.getTypeStoreSize(DataType); 4621 4622 // SSE4A supports nontemporal stores of float and double at arbitrary 4623 // alignment. 4624 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 4625 return true; 4626 4627 // Besides the SSE4A subtarget exception above, only aligned stores are 4628 // available nontemporaly on any other subtarget. And only stores with a size 4629 // of 4..32 bytes (powers of 2, only) are permitted. 4630 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 4631 !isPowerOf2_32(DataSize)) 4632 return false; 4633 4634 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 4635 // loads require AVX2). 4636 if (DataSize == 32) 4637 return ST->hasAVX(); 4638 else if (DataSize == 16) 4639 return ST->hasSSE1(); 4640 return true; 4641 } 4642 4643 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 4644 if (!isa<VectorType>(DataTy)) 4645 return false; 4646 4647 if (!ST->hasAVX512()) 4648 return false; 4649 4650 // The backend can't handle a single element vector. 4651 if (cast<FixedVectorType>(DataTy)->getNumElements() == 1) 4652 return false; 4653 4654 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 4655 4656 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4657 return true; 4658 4659 if (!ScalarTy->isIntegerTy()) 4660 return false; 4661 4662 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4663 return IntWidth == 32 || IntWidth == 64 || 4664 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 4665 } 4666 4667 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 4668 return isLegalMaskedExpandLoad(DataTy); 4669 } 4670 4671 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, Align Alignment) { 4672 // Some CPUs have better gather performance than others. 4673 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 4674 // enable gather with a -march. 4675 if (!(ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()))) 4676 return false; 4677 4678 // This function is called now in two cases: from the Loop Vectorizer 4679 // and from the Scalarizer. 4680 // When the Loop Vectorizer asks about legality of the feature, 4681 // the vectorization factor is not calculated yet. The Loop Vectorizer 4682 // sends a scalar type and the decision is based on the width of the 4683 // scalar element. 4684 // Later on, the cost model will estimate usage this intrinsic based on 4685 // the vector type. 4686 // The Scalarizer asks again about legality. It sends a vector type. 4687 // In this case we can reject non-power-of-2 vectors. 4688 // We also reject single element vectors as the type legalizer can't 4689 // scalarize it. 4690 if (auto *DataVTy = dyn_cast<FixedVectorType>(DataTy)) { 4691 unsigned NumElts = DataVTy->getNumElements(); 4692 if (NumElts == 1) 4693 return false; 4694 } 4695 Type *ScalarTy = DataTy->getScalarType(); 4696 if (ScalarTy->isPointerTy()) 4697 return true; 4698 4699 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4700 return true; 4701 4702 if (!ScalarTy->isIntegerTy()) 4703 return false; 4704 4705 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4706 return IntWidth == 32 || IntWidth == 64; 4707 } 4708 4709 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, Align Alignment) { 4710 // AVX2 doesn't support scatter 4711 if (!ST->hasAVX512()) 4712 return false; 4713 return isLegalMaskedGather(DataType, Alignment); 4714 } 4715 4716 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 4717 EVT VT = TLI->getValueType(DL, DataType); 4718 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 4719 } 4720 4721 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 4722 return false; 4723 } 4724 4725 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 4726 const Function *Callee) const { 4727 const TargetMachine &TM = getTLI()->getTargetMachine(); 4728 4729 // Work this as a subsetting of subtarget features. 4730 const FeatureBitset &CallerBits = 4731 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 4732 const FeatureBitset &CalleeBits = 4733 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 4734 4735 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 4736 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 4737 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 4738 } 4739 4740 bool X86TTIImpl::areFunctionArgsABICompatible( 4741 const Function *Caller, const Function *Callee, 4742 SmallPtrSetImpl<Argument *> &Args) const { 4743 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args)) 4744 return false; 4745 4746 // If we get here, we know the target features match. If one function 4747 // considers 512-bit vectors legal and the other does not, consider them 4748 // incompatible. 4749 const TargetMachine &TM = getTLI()->getTargetMachine(); 4750 4751 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 4752 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs()) 4753 return true; 4754 4755 // Consider the arguments compatible if they aren't vectors or aggregates. 4756 // FIXME: Look at the size of vectors. 4757 // FIXME: Look at the element types of aggregates to see if there are vectors. 4758 // FIXME: The API of this function seems intended to allow arguments 4759 // to be removed from the set, but the caller doesn't check if the set 4760 // becomes empty so that may not work in practice. 4761 return llvm::none_of(Args, [](Argument *A) { 4762 auto *EltTy = cast<PointerType>(A->getType())->getElementType(); 4763 return EltTy->isVectorTy() || EltTy->isAggregateType(); 4764 }); 4765 } 4766 4767 X86TTIImpl::TTI::MemCmpExpansionOptions 4768 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 4769 TTI::MemCmpExpansionOptions Options; 4770 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 4771 Options.NumLoadsPerBlock = 2; 4772 // All GPR and vector loads can be unaligned. 4773 Options.AllowOverlappingLoads = true; 4774 if (IsZeroCmp) { 4775 // Only enable vector loads for equality comparison. Right now the vector 4776 // version is not as fast for three way compare (see #33329). 4777 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 4778 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 4779 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 4780 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 4781 } 4782 if (ST->is64Bit()) { 4783 Options.LoadSizes.push_back(8); 4784 } 4785 Options.LoadSizes.push_back(4); 4786 Options.LoadSizes.push_back(2); 4787 Options.LoadSizes.push_back(1); 4788 return Options; 4789 } 4790 4791 bool X86TTIImpl::enableInterleavedAccessVectorization() { 4792 // TODO: We expect this to be beneficial regardless of arch, 4793 // but there are currently some unexplained performance artifacts on Atom. 4794 // As a temporary solution, disable on Atom. 4795 return !(ST->isAtom()); 4796 } 4797 4798 // Get estimation for interleaved load/store operations for AVX2. 4799 // \p Factor is the interleaved-access factor (stride) - number of 4800 // (interleaved) elements in the group. 4801 // \p Indices contains the indices for a strided load: when the 4802 // interleaved load has gaps they indicate which elements are used. 4803 // If Indices is empty (or if the number of indices is equal to the size 4804 // of the interleaved-access as given in \p Factor) the access has no gaps. 4805 // 4806 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 4807 // computing the cost using a generic formula as a function of generic 4808 // shuffles. We therefore use a lookup table instead, filled according to 4809 // the instruction sequences that codegen currently generates. 4810 InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2( 4811 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 4812 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 4813 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 4814 4815 if (UseMaskForCond || UseMaskForGaps) 4816 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4817 Alignment, AddressSpace, CostKind, 4818 UseMaskForCond, UseMaskForGaps); 4819 4820 // We currently Support only fully-interleaved groups, with no gaps. 4821 // TODO: Support also strided loads (interleaved-groups with gaps). 4822 if (Indices.size() && Indices.size() != Factor) 4823 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4824 Alignment, AddressSpace, CostKind); 4825 4826 // VecTy for interleave memop is <VF*Factor x Elt>. 4827 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4828 // VecTy = <12 x i32>. 4829 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4830 4831 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 4832 // the VF=2, while v2i128 is an unsupported MVT vector type 4833 // (see MachineValueType.h::getVectorVT()). 4834 if (!LegalVT.isVector()) 4835 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4836 Alignment, AddressSpace, CostKind); 4837 4838 unsigned VF = VecTy->getNumElements() / Factor; 4839 Type *ScalarTy = VecTy->getElementType(); 4840 // Deduplicate entries, model floats/pointers as appropriately-sized integers. 4841 if (!ScalarTy->isIntegerTy()) 4842 ScalarTy = 4843 Type::getIntNTy(ScalarTy->getContext(), DL.getTypeSizeInBits(ScalarTy)); 4844 4845 // Get the cost of all the memory operations. 4846 InstructionCost MemOpCosts = getMemoryOpCost( 4847 Opcode, VecTy, MaybeAlign(Alignment), AddressSpace, CostKind); 4848 4849 auto *VT = FixedVectorType::get(ScalarTy, VF); 4850 EVT ETy = TLI->getValueType(DL, VT); 4851 if (!ETy.isSimple()) 4852 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4853 Alignment, AddressSpace, CostKind); 4854 4855 // TODO: Complete for other data-types and strides. 4856 // Each combination of Stride, element bit width and VF results in a different 4857 // sequence; The cost tables are therefore accessed with: 4858 // Factor (stride) and VectorType=VFxiN. 4859 // The Cost accounts only for the shuffle sequence; 4860 // The cost of the loads/stores is accounted for separately. 4861 // 4862 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 4863 {2, MVT::v4i64, 6}, // (load 8i64 and) deinterleave into 2 x 4i64 4864 4865 {3, MVT::v2i8, 10}, // (load 6i8 and) deinterleave into 3 x 2i8 4866 {3, MVT::v4i8, 4}, // (load 12i8 and) deinterleave into 3 x 4i8 4867 {3, MVT::v8i8, 9}, // (load 24i8 and) deinterleave into 3 x 8i8 4868 {3, MVT::v16i8, 11}, // (load 48i8 and) deinterleave into 3 x 16i8 4869 {3, MVT::v32i8, 13}, // (load 96i8 and) deinterleave into 3 x 32i8 4870 4871 {3, MVT::v8i32, 17}, // (load 24i32 and) deinterleave into 3 x 8i32 4872 4873 {4, MVT::v2i8, 12}, // (load 8i8 and) deinterleave into 4 x 2i8 4874 {4, MVT::v4i8, 4}, // (load 16i8 and) deinterleave into 4 x 4i8 4875 {4, MVT::v8i8, 20}, // (load 32i8 and) deinterleave into 4 x 8i8 4876 {4, MVT::v16i8, 39}, // (load 64i8 and) deinterleave into 4 x 16i8 4877 {4, MVT::v32i8, 80}, // (load 128i8 and) deinterleave into 4 x 32i8 4878 4879 {8, MVT::v8i32, 40} // (load 64i32 and) deinterleave into 8 x 8i32 4880 }; 4881 4882 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 4883 {2, MVT::v4i64, 6}, // interleave 2 x 4i64 into 8i64 (and store) 4884 4885 {3, MVT::v2i8, 7}, // interleave 3 x 2i8 into 6i8 (and store) 4886 {3, MVT::v4i8, 8}, // interleave 3 x 4i8 into 12i8 (and store) 4887 {3, MVT::v8i8, 11}, // interleave 3 x 8i8 into 24i8 (and store) 4888 {3, MVT::v16i8, 11}, // interleave 3 x 16i8 into 48i8 (and store) 4889 {3, MVT::v32i8, 13}, // interleave 3 x 32i8 into 96i8 (and store) 4890 4891 {4, MVT::v2i8, 12}, // interleave 4 x 2i8 into 8i8 (and store) 4892 {4, MVT::v4i8, 9}, // interleave 4 x 4i8 into 16i8 (and store) 4893 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 4894 {4, MVT::v16i8, 10}, // interleave 4 x 16i8 into 64i8 (and store) 4895 {4, MVT::v32i8, 12} // interleave 4 x 32i8 into 128i8 (and store) 4896 }; 4897 4898 if (Opcode == Instruction::Load) { 4899 if (const auto *Entry = 4900 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 4901 return MemOpCosts + Entry->Cost; 4902 } else { 4903 assert(Opcode == Instruction::Store && 4904 "Expected Store Instruction at this point"); 4905 if (const auto *Entry = 4906 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 4907 return MemOpCosts + Entry->Cost; 4908 } 4909 4910 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4911 Alignment, AddressSpace, CostKind); 4912 } 4913 4914 // Get estimation for interleaved load/store operations and strided load. 4915 // \p Indices contains indices for strided load. 4916 // \p Factor - the factor of interleaving. 4917 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 4918 InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX512( 4919 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 4920 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 4921 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 4922 4923 if (UseMaskForCond || UseMaskForGaps) 4924 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4925 Alignment, AddressSpace, CostKind, 4926 UseMaskForCond, UseMaskForGaps); 4927 4928 // VecTy for interleave memop is <VF*Factor x Elt>. 4929 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4930 // VecTy = <12 x i32>. 4931 4932 // Calculate the number of memory operations (NumOfMemOps), required 4933 // for load/store the VecTy. 4934 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4935 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4936 unsigned LegalVTSize = LegalVT.getStoreSize(); 4937 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4938 4939 // Get the cost of one memory operation. 4940 auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(), 4941 LegalVT.getVectorNumElements()); 4942 InstructionCost MemOpCost = getMemoryOpCost( 4943 Opcode, SingleMemOpTy, MaybeAlign(Alignment), AddressSpace, CostKind); 4944 4945 unsigned VF = VecTy->getNumElements() / Factor; 4946 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 4947 4948 if (Opcode == Instruction::Load) { 4949 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 4950 // contain the cost of the optimized shuffle sequence that the 4951 // X86InterleavedAccess pass will generate. 4952 // The cost of loads and stores are computed separately from the table. 4953 4954 // X86InterleavedAccess support only the following interleaved-access group. 4955 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 4956 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 4957 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 4958 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 4959 }; 4960 4961 if (const auto *Entry = 4962 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 4963 return NumOfMemOps * MemOpCost + Entry->Cost; 4964 //If an entry does not exist, fallback to the default implementation. 4965 4966 // Kind of shuffle depends on number of loaded values. 4967 // If we load the entire data in one register, we can use a 1-src shuffle. 4968 // Otherwise, we'll merge 2 sources in each operation. 4969 TTI::ShuffleKind ShuffleKind = 4970 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 4971 4972 InstructionCost ShuffleCost = 4973 getShuffleCost(ShuffleKind, SingleMemOpTy, None, 0, nullptr); 4974 4975 unsigned NumOfLoadsInInterleaveGrp = 4976 Indices.size() ? Indices.size() : Factor; 4977 auto *ResultTy = FixedVectorType::get(VecTy->getElementType(), 4978 VecTy->getNumElements() / Factor); 4979 InstructionCost NumOfResults = 4980 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 4981 NumOfLoadsInInterleaveGrp; 4982 4983 // About a half of the loads may be folded in shuffles when we have only 4984 // one result. If we have more than one result, we do not fold loads at all. 4985 unsigned NumOfUnfoldedLoads = 4986 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 4987 4988 // Get a number of shuffle operations per result. 4989 unsigned NumOfShufflesPerResult = 4990 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 4991 4992 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4993 // When we have more than one destination, we need additional instructions 4994 // to keep sources. 4995 InstructionCost NumOfMoves = 0; 4996 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 4997 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 4998 4999 InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 5000 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 5001 5002 return Cost; 5003 } 5004 5005 // Store. 5006 assert(Opcode == Instruction::Store && 5007 "Expected Store Instruction at this point"); 5008 // X86InterleavedAccess support only the following interleaved-access group. 5009 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 5010 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 5011 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 5012 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 5013 5014 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 5015 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 5016 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 5017 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 5018 }; 5019 5020 if (const auto *Entry = 5021 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 5022 return NumOfMemOps * MemOpCost + Entry->Cost; 5023 //If an entry does not exist, fallback to the default implementation. 5024 5025 // There is no strided stores meanwhile. And store can't be folded in 5026 // shuffle. 5027 unsigned NumOfSources = Factor; // The number of values to be merged. 5028 InstructionCost ShuffleCost = 5029 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, None, 0, nullptr); 5030 unsigned NumOfShufflesPerStore = NumOfSources - 1; 5031 5032 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 5033 // We need additional instructions to keep sources. 5034 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 5035 InstructionCost Cost = 5036 NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 5037 NumOfMoves; 5038 return Cost; 5039 } 5040 5041 InstructionCost X86TTIImpl::getInterleavedMemoryOpCost( 5042 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, 5043 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, 5044 bool UseMaskForCond, bool UseMaskForGaps) { 5045 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 5046 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 5047 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 5048 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 5049 return true; 5050 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 5051 return HasBW; 5052 return false; 5053 }; 5054 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 5055 return getInterleavedMemoryOpCostAVX512( 5056 Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment, 5057 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 5058 if (ST->hasAVX2()) 5059 return getInterleavedMemoryOpCostAVX2( 5060 Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment, 5061 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 5062 5063 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5064 Alignment, AddressSpace, CostKind, 5065 UseMaskForCond, UseMaskForGaps); 5066 } 5067