1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // X86 cost model. 56 // 57 //===----------------------------------------------------------------------===// 58 59 TargetTransformInfo::PopcntSupportKind 60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 61 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 62 // TODO: Currently the __builtin_popcount() implementation using SSE3 63 // instructions is inefficient. Once the problem is fixed, we should 64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 66 } 67 68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 69 TargetTransformInfo::CacheLevel Level) const { 70 switch (Level) { 71 case TargetTransformInfo::CacheLevel::L1D: 72 // - Penryn 73 // - Nehalem 74 // - Westmere 75 // - Sandy Bridge 76 // - Ivy Bridge 77 // - Haswell 78 // - Broadwell 79 // - Skylake 80 // - Kabylake 81 return 32 * 1024; // 32 KByte 82 case TargetTransformInfo::CacheLevel::L2D: 83 // - Penryn 84 // - Nehalem 85 // - Westmere 86 // - Sandy Bridge 87 // - Ivy Bridge 88 // - Haswell 89 // - Broadwell 90 // - Skylake 91 // - Kabylake 92 return 256 * 1024; // 256 KByte 93 } 94 95 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 96 } 97 98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 99 TargetTransformInfo::CacheLevel Level) const { 100 // - Penryn 101 // - Nehalem 102 // - Westmere 103 // - Sandy Bridge 104 // - Ivy Bridge 105 // - Haswell 106 // - Broadwell 107 // - Skylake 108 // - Kabylake 109 switch (Level) { 110 case TargetTransformInfo::CacheLevel::L1D: 111 LLVM_FALLTHROUGH; 112 case TargetTransformInfo::CacheLevel::L2D: 113 return 8; 114 } 115 116 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 117 } 118 119 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 120 bool Vector = (ClassID == 1); 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 TypeSize 133 X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { 134 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 135 switch (K) { 136 case TargetTransformInfo::RGK_Scalar: 137 return TypeSize::getFixed(ST->is64Bit() ? 64 : 32); 138 case TargetTransformInfo::RGK_FixedWidthVector: 139 if (ST->hasAVX512() && PreferVectorWidth >= 512) 140 return TypeSize::getFixed(512); 141 if (ST->hasAVX() && PreferVectorWidth >= 256) 142 return TypeSize::getFixed(256); 143 if (ST->hasSSE1() && PreferVectorWidth >= 128) 144 return TypeSize::getFixed(128); 145 return TypeSize::getFixed(0); 146 case TargetTransformInfo::RGK_ScalableVector: 147 return TypeSize::getScalable(0); 148 } 149 150 llvm_unreachable("Unsupported register kind"); 151 } 152 153 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 154 return getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector) 155 .getFixedSize(); 156 } 157 158 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 159 // If the loop will not be vectorized, don't interleave the loop. 160 // Let regular unroll to unroll the loop, which saves the overflow 161 // check and memory check cost. 162 if (VF == 1) 163 return 1; 164 165 if (ST->isAtom()) 166 return 1; 167 168 // Sandybridge and Haswell have multiple execution ports and pipelined 169 // vector units. 170 if (ST->hasAVX()) 171 return 4; 172 173 return 2; 174 } 175 176 InstructionCost X86TTIImpl::getArithmeticInstrCost( 177 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, 178 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 179 TTI::OperandValueProperties Opd1PropInfo, 180 TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, 181 const Instruction *CxtI) { 182 // TODO: Handle more cost kinds. 183 if (CostKind != TTI::TCK_RecipThroughput) 184 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, 185 Op2Info, Opd1PropInfo, 186 Opd2PropInfo, Args, CxtI); 187 188 // vXi8 multiplications are always promoted to vXi16. 189 if (Opcode == Instruction::Mul && Ty->isVectorTy() && 190 Ty->getScalarSizeInBits() == 8) { 191 Type *WideVecTy = 192 VectorType::getExtendedElementVectorType(cast<VectorType>(Ty)); 193 return getCastInstrCost(Instruction::ZExt, WideVecTy, Ty, 194 TargetTransformInfo::CastContextHint::None, 195 CostKind) + 196 getCastInstrCost(Instruction::Trunc, Ty, WideVecTy, 197 TargetTransformInfo::CastContextHint::None, 198 CostKind) + 199 getArithmeticInstrCost(Opcode, WideVecTy, CostKind, Op1Info, Op2Info, 200 Opd1PropInfo, Opd2PropInfo); 201 } 202 203 // Legalize the type. 204 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 205 206 int ISD = TLI->InstructionOpcodeToISD(Opcode); 207 assert(ISD && "Invalid opcode"); 208 209 static const CostTblEntry GLMCostTable[] = { 210 { ISD::FDIV, MVT::f32, 18 }, // divss 211 { ISD::FDIV, MVT::v4f32, 35 }, // divps 212 { ISD::FDIV, MVT::f64, 33 }, // divsd 213 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 214 }; 215 216 if (ST->useGLMDivSqrtCosts()) 217 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 218 LT.second)) 219 return LT.first * Entry->Cost; 220 221 static const CostTblEntry SLMCostTable[] = { 222 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 223 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 224 { ISD::FMUL, MVT::f64, 2 }, // mulsd 225 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 226 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 227 { ISD::FDIV, MVT::f32, 17 }, // divss 228 { ISD::FDIV, MVT::v4f32, 39 }, // divps 229 { ISD::FDIV, MVT::f64, 32 }, // divsd 230 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 231 { ISD::FADD, MVT::v2f64, 2 }, // addpd 232 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 233 // v2i64/v4i64 mul is custom lowered as a series of long: 234 // multiplies(3), shifts(3) and adds(2) 235 // slm muldq version throughput is 2 and addq throughput 4 236 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 237 // 3X4 (addq throughput) = 17 238 { ISD::MUL, MVT::v2i64, 17 }, 239 // slm addq\subq throughput is 4 240 { ISD::ADD, MVT::v2i64, 4 }, 241 { ISD::SUB, MVT::v2i64, 4 }, 242 }; 243 244 if (ST->isSLM()) { 245 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 246 // Check if the operands can be shrinked into a smaller datatype. 247 bool Op1Signed = false; 248 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 249 bool Op2Signed = false; 250 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 251 252 bool SignedMode = Op1Signed || Op2Signed; 253 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 254 255 if (OpMinSize <= 7) 256 return LT.first * 3; // pmullw/sext 257 if (!SignedMode && OpMinSize <= 8) 258 return LT.first * 3; // pmullw/zext 259 if (OpMinSize <= 15) 260 return LT.first * 5; // pmullw/pmulhw/pshuf 261 if (!SignedMode && OpMinSize <= 16) 262 return LT.first * 5; // pmullw/pmulhw/pshuf 263 } 264 265 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 266 LT.second)) { 267 return LT.first * Entry->Cost; 268 } 269 } 270 271 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 272 ISD == ISD::UREM) && 273 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 274 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 275 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 276 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 277 // On X86, vector signed division by constants power-of-two are 278 // normally expanded to the sequence SRA + SRL + ADD + SRA. 279 // The OperandValue properties may not be the same as that of the previous 280 // operation; conservatively assume OP_None. 281 InstructionCost Cost = 282 2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Op1Info, 283 Op2Info, TargetTransformInfo::OP_None, 284 TargetTransformInfo::OP_None); 285 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 286 Op2Info, 287 TargetTransformInfo::OP_None, 288 TargetTransformInfo::OP_None); 289 Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind, Op1Info, 290 Op2Info, 291 TargetTransformInfo::OP_None, 292 TargetTransformInfo::OP_None); 293 294 if (ISD == ISD::SREM) { 295 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 296 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info, 297 Op2Info); 298 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info, 299 Op2Info); 300 } 301 302 return Cost; 303 } 304 305 // Vector unsigned division/remainder will be simplified to shifts/masks. 306 if (ISD == ISD::UDIV) 307 return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, 308 Op1Info, Op2Info, 309 TargetTransformInfo::OP_None, 310 TargetTransformInfo::OP_None); 311 312 else // UREM 313 return getArithmeticInstrCost(Instruction::And, Ty, CostKind, 314 Op1Info, Op2Info, 315 TargetTransformInfo::OP_None, 316 TargetTransformInfo::OP_None); 317 } 318 319 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 320 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 321 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 322 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 323 }; 324 325 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 326 ST->hasBWI()) { 327 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 328 LT.second)) 329 return LT.first * Entry->Cost; 330 } 331 332 static const CostTblEntry AVX512UniformConstCostTable[] = { 333 { ISD::SRA, MVT::v2i64, 1 }, 334 { ISD::SRA, MVT::v4i64, 1 }, 335 { ISD::SRA, MVT::v8i64, 1 }, 336 337 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 338 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 339 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 340 341 { ISD::SDIV, MVT::v16i32, 6 }, // pmuludq sequence 342 { ISD::SREM, MVT::v16i32, 8 }, // pmuludq+mul+sub sequence 343 { ISD::UDIV, MVT::v16i32, 5 }, // pmuludq sequence 344 { ISD::UREM, MVT::v16i32, 7 }, // pmuludq+mul+sub sequence 345 }; 346 347 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 348 ST->hasAVX512()) { 349 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 350 LT.second)) 351 return LT.first * Entry->Cost; 352 } 353 354 static const CostTblEntry AVX2UniformConstCostTable[] = { 355 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 356 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 357 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 358 359 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 360 361 { ISD::SDIV, MVT::v8i32, 6 }, // pmuludq sequence 362 { ISD::SREM, MVT::v8i32, 8 }, // pmuludq+mul+sub sequence 363 { ISD::UDIV, MVT::v8i32, 5 }, // pmuludq sequence 364 { ISD::UREM, MVT::v8i32, 7 }, // pmuludq+mul+sub sequence 365 }; 366 367 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 368 ST->hasAVX2()) { 369 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 370 LT.second)) 371 return LT.first * Entry->Cost; 372 } 373 374 static const CostTblEntry SSE2UniformConstCostTable[] = { 375 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 376 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 377 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 378 379 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 380 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 381 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 382 383 { ISD::SDIV, MVT::v8i32, 12+2 }, // 2*pmuludq sequence + split. 384 { ISD::SREM, MVT::v8i32, 16+2 }, // 2*pmuludq+mul+sub sequence + split. 385 { ISD::SDIV, MVT::v4i32, 6 }, // pmuludq sequence 386 { ISD::SREM, MVT::v4i32, 8 }, // pmuludq+mul+sub sequence 387 { ISD::UDIV, MVT::v8i32, 10+2 }, // 2*pmuludq sequence + split. 388 { ISD::UREM, MVT::v8i32, 14+2 }, // 2*pmuludq+mul+sub sequence + split. 389 { ISD::UDIV, MVT::v4i32, 5 }, // pmuludq sequence 390 { ISD::UREM, MVT::v4i32, 7 }, // pmuludq+mul+sub sequence 391 }; 392 393 // XOP has faster vXi8 shifts. 394 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 395 ST->hasSSE2() && !ST->hasXOP()) { 396 if (const auto *Entry = 397 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 398 return LT.first * Entry->Cost; 399 } 400 401 static const CostTblEntry AVX512BWConstCostTable[] = { 402 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 403 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 404 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 405 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 406 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 407 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 408 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 409 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 410 }; 411 412 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 413 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 414 ST->hasBWI()) { 415 if (const auto *Entry = 416 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 417 return LT.first * Entry->Cost; 418 } 419 420 static const CostTblEntry AVX512ConstCostTable[] = { 421 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 422 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 423 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 424 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 425 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 426 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 427 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 428 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 429 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 430 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 431 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 432 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 433 }; 434 435 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 436 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 437 ST->hasAVX512()) { 438 if (const auto *Entry = 439 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 440 return LT.first * Entry->Cost; 441 } 442 443 static const CostTblEntry AVX2ConstCostTable[] = { 444 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 445 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 446 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 447 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 448 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 449 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 450 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 451 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 452 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 453 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 454 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 455 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 456 }; 457 458 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 459 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 460 ST->hasAVX2()) { 461 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 462 return LT.first * Entry->Cost; 463 } 464 465 static const CostTblEntry SSE2ConstCostTable[] = { 466 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 467 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 468 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 469 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 470 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 471 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 472 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 473 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 474 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 475 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 476 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 477 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 478 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 479 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 480 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 481 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 482 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 483 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 484 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 485 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 486 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 487 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 488 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 489 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 490 }; 491 492 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 493 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 494 ST->hasSSE2()) { 495 // pmuldq sequence. 496 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 497 return LT.first * 32; 498 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 499 return LT.first * 38; 500 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 501 return LT.first * 15; 502 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 503 return LT.first * 20; 504 505 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 506 return LT.first * Entry->Cost; 507 } 508 509 static const CostTblEntry AVX512BWShiftCostTable[] = { 510 { ISD::SHL, MVT::v16i8, 4 }, // extend/vpsllvw/pack sequence. 511 { ISD::SRL, MVT::v16i8, 4 }, // extend/vpsrlvw/pack sequence. 512 { ISD::SRA, MVT::v16i8, 4 }, // extend/vpsravw/pack sequence. 513 { ISD::SHL, MVT::v32i8, 4 }, // extend/vpsllvw/pack sequence. 514 { ISD::SRL, MVT::v32i8, 4 }, // extend/vpsrlvw/pack sequence. 515 { ISD::SRA, MVT::v32i8, 6 }, // extend/vpsravw/pack sequence. 516 { ISD::SHL, MVT::v64i8, 6 }, // extend/vpsllvw/pack sequence. 517 { ISD::SRL, MVT::v64i8, 7 }, // extend/vpsrlvw/pack sequence. 518 { ISD::SRA, MVT::v64i8, 15 }, // extend/vpsravw/pack sequence. 519 520 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 521 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 522 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 523 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 524 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 525 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 526 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 527 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 528 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 529 }; 530 531 if (ST->hasBWI()) 532 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 533 return LT.first * Entry->Cost; 534 535 static const CostTblEntry AVX2UniformCostTable[] = { 536 // Uniform splats are cheaper for the following instructions. 537 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 538 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 539 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 540 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 541 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 542 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 543 544 { ISD::SHL, MVT::v8i32, 1 }, // pslld 545 { ISD::SRL, MVT::v8i32, 1 }, // psrld 546 { ISD::SRA, MVT::v8i32, 1 }, // psrad 547 { ISD::SHL, MVT::v4i64, 1 }, // psllq 548 { ISD::SRL, MVT::v4i64, 1 }, // psrlq 549 }; 550 551 if (ST->hasAVX2() && 552 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 553 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 554 if (const auto *Entry = 555 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 556 return LT.first * Entry->Cost; 557 } 558 559 static const CostTblEntry SSE2UniformCostTable[] = { 560 // Uniform splats are cheaper for the following instructions. 561 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 562 { ISD::SHL, MVT::v4i32, 1 }, // pslld 563 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 564 565 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 566 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 567 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 568 569 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 570 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 571 }; 572 573 if (ST->hasSSE2() && 574 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 575 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 576 if (const auto *Entry = 577 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 578 return LT.first * Entry->Cost; 579 } 580 581 static const CostTblEntry AVX512DQCostTable[] = { 582 { ISD::MUL, MVT::v2i64, 2 }, // pmullq 583 { ISD::MUL, MVT::v4i64, 2 }, // pmullq 584 { ISD::MUL, MVT::v8i64, 2 } // pmullq 585 }; 586 587 // Look for AVX512DQ lowering tricks for custom cases. 588 if (ST->hasDQI()) 589 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 590 return LT.first * Entry->Cost; 591 592 static const CostTblEntry AVX512BWCostTable[] = { 593 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 594 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 595 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 596 }; 597 598 // Look for AVX512BW lowering tricks for custom cases. 599 if (ST->hasBWI()) 600 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 601 return LT.first * Entry->Cost; 602 603 static const CostTblEntry AVX512CostTable[] = { 604 { ISD::SHL, MVT::v4i32, 1 }, 605 { ISD::SRL, MVT::v4i32, 1 }, 606 { ISD::SRA, MVT::v4i32, 1 }, 607 { ISD::SHL, MVT::v8i32, 1 }, 608 { ISD::SRL, MVT::v8i32, 1 }, 609 { ISD::SRA, MVT::v8i32, 1 }, 610 { ISD::SHL, MVT::v16i32, 1 }, 611 { ISD::SRL, MVT::v16i32, 1 }, 612 { ISD::SRA, MVT::v16i32, 1 }, 613 614 { ISD::SHL, MVT::v2i64, 1 }, 615 { ISD::SRL, MVT::v2i64, 1 }, 616 { ISD::SHL, MVT::v4i64, 1 }, 617 { ISD::SRL, MVT::v4i64, 1 }, 618 { ISD::SHL, MVT::v8i64, 1 }, 619 { ISD::SRL, MVT::v8i64, 1 }, 620 621 { ISD::SRA, MVT::v2i64, 1 }, 622 { ISD::SRA, MVT::v4i64, 1 }, 623 { ISD::SRA, MVT::v8i64, 1 }, 624 625 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 626 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 627 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 628 { ISD::MUL, MVT::v8i64, 6 }, // 3*pmuludq/3*shift/2*add 629 630 { ISD::FNEG, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 631 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 632 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 633 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 634 { ISD::FDIV, MVT::f64, 4 }, // Skylake from http://www.agner.org/ 635 { ISD::FDIV, MVT::v2f64, 4 }, // Skylake from http://www.agner.org/ 636 { ISD::FDIV, MVT::v4f64, 8 }, // Skylake from http://www.agner.org/ 637 { ISD::FDIV, MVT::v8f64, 16 }, // Skylake from http://www.agner.org/ 638 639 { ISD::FNEG, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 640 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 641 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 642 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 643 { ISD::FDIV, MVT::f32, 3 }, // Skylake from http://www.agner.org/ 644 { ISD::FDIV, MVT::v4f32, 3 }, // Skylake from http://www.agner.org/ 645 { ISD::FDIV, MVT::v8f32, 5 }, // Skylake from http://www.agner.org/ 646 { ISD::FDIV, MVT::v16f32, 10 }, // Skylake from http://www.agner.org/ 647 }; 648 649 if (ST->hasAVX512()) 650 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 651 return LT.first * Entry->Cost; 652 653 static const CostTblEntry AVX2ShiftCostTable[] = { 654 // Shifts on vXi64/vXi32 on AVX2 is legal even though we declare to 655 // customize them to detect the cases where shift amount is a scalar one. 656 { ISD::SHL, MVT::v4i32, 2 }, // vpsllvd (Haswell from agner.org) 657 { ISD::SRL, MVT::v4i32, 2 }, // vpsrlvd (Haswell from agner.org) 658 { ISD::SRA, MVT::v4i32, 2 }, // vpsravd (Haswell from agner.org) 659 { ISD::SHL, MVT::v8i32, 2 }, // vpsllvd (Haswell from agner.org) 660 { ISD::SRL, MVT::v8i32, 2 }, // vpsrlvd (Haswell from agner.org) 661 { ISD::SRA, MVT::v8i32, 2 }, // vpsravd (Haswell from agner.org) 662 { ISD::SHL, MVT::v2i64, 1 }, // vpsllvq (Haswell from agner.org) 663 { ISD::SRL, MVT::v2i64, 1 }, // vpsrlvq (Haswell from agner.org) 664 { ISD::SHL, MVT::v4i64, 1 }, // vpsllvq (Haswell from agner.org) 665 { ISD::SRL, MVT::v4i64, 1 }, // vpsrlvq (Haswell from agner.org) 666 }; 667 668 if (ST->hasAVX512()) { 669 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 670 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 671 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 672 // On AVX512, a packed v32i16 shift left by a constant build_vector 673 // is lowered into a vector multiply (vpmullw). 674 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 675 Op1Info, Op2Info, 676 TargetTransformInfo::OP_None, 677 TargetTransformInfo::OP_None); 678 } 679 680 // Look for AVX2 lowering tricks (XOP is always better at v4i32 shifts). 681 if (ST->hasAVX2() && !(ST->hasXOP() && LT.second == MVT::v4i32)) { 682 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 683 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 684 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 685 // On AVX2, a packed v16i16 shift left by a constant build_vector 686 // is lowered into a vector multiply (vpmullw). 687 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 688 Op1Info, Op2Info, 689 TargetTransformInfo::OP_None, 690 TargetTransformInfo::OP_None); 691 692 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 693 return LT.first * Entry->Cost; 694 } 695 696 static const CostTblEntry XOPShiftCostTable[] = { 697 // 128bit shifts take 1cy, but right shifts require negation beforehand. 698 { ISD::SHL, MVT::v16i8, 1 }, 699 { ISD::SRL, MVT::v16i8, 2 }, 700 { ISD::SRA, MVT::v16i8, 2 }, 701 { ISD::SHL, MVT::v8i16, 1 }, 702 { ISD::SRL, MVT::v8i16, 2 }, 703 { ISD::SRA, MVT::v8i16, 2 }, 704 { ISD::SHL, MVT::v4i32, 1 }, 705 { ISD::SRL, MVT::v4i32, 2 }, 706 { ISD::SRA, MVT::v4i32, 2 }, 707 { ISD::SHL, MVT::v2i64, 1 }, 708 { ISD::SRL, MVT::v2i64, 2 }, 709 { ISD::SRA, MVT::v2i64, 2 }, 710 // 256bit shifts require splitting if AVX2 didn't catch them above. 711 { ISD::SHL, MVT::v32i8, 2+2 }, 712 { ISD::SRL, MVT::v32i8, 4+2 }, 713 { ISD::SRA, MVT::v32i8, 4+2 }, 714 { ISD::SHL, MVT::v16i16, 2+2 }, 715 { ISD::SRL, MVT::v16i16, 4+2 }, 716 { ISD::SRA, MVT::v16i16, 4+2 }, 717 { ISD::SHL, MVT::v8i32, 2+2 }, 718 { ISD::SRL, MVT::v8i32, 4+2 }, 719 { ISD::SRA, MVT::v8i32, 4+2 }, 720 { ISD::SHL, MVT::v4i64, 2+2 }, 721 { ISD::SRL, MVT::v4i64, 4+2 }, 722 { ISD::SRA, MVT::v4i64, 4+2 }, 723 }; 724 725 // Look for XOP lowering tricks. 726 if (ST->hasXOP()) { 727 // If the right shift is constant then we'll fold the negation so 728 // it's as cheap as a left shift. 729 int ShiftISD = ISD; 730 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 731 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 732 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 733 ShiftISD = ISD::SHL; 734 if (const auto *Entry = 735 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 736 return LT.first * Entry->Cost; 737 } 738 739 static const CostTblEntry SSE2UniformShiftCostTable[] = { 740 // Uniform splats are cheaper for the following instructions. 741 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 742 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 743 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 744 745 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 746 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 747 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 748 749 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 750 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 751 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 752 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 753 }; 754 755 if (ST->hasSSE2() && 756 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 757 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 758 759 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 760 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 761 return LT.first * 4; // 2*psrad + shuffle. 762 763 if (const auto *Entry = 764 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 765 return LT.first * Entry->Cost; 766 } 767 768 if (ISD == ISD::SHL && 769 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 770 MVT VT = LT.second; 771 // Vector shift left by non uniform constant can be lowered 772 // into vector multiply. 773 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 774 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 775 ISD = ISD::MUL; 776 } 777 778 static const CostTblEntry AVX2CostTable[] = { 779 { ISD::SHL, MVT::v16i8, 6 }, // vpblendvb sequence. 780 { ISD::SHL, MVT::v32i8, 6 }, // vpblendvb sequence. 781 { ISD::SHL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 782 { ISD::SHL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 783 { ISD::SHL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 784 { ISD::SHL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 785 786 { ISD::SRL, MVT::v16i8, 6 }, // vpblendvb sequence. 787 { ISD::SRL, MVT::v32i8, 6 }, // vpblendvb sequence. 788 { ISD::SRL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 789 { ISD::SRL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 790 { ISD::SRL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 791 { ISD::SRL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 792 793 { ISD::SRA, MVT::v16i8, 17 }, // vpblendvb sequence. 794 { ISD::SRA, MVT::v32i8, 17 }, // vpblendvb sequence. 795 { ISD::SRA, MVT::v64i8, 34 }, // 2*vpblendvb sequence. 796 { ISD::SRA, MVT::v8i16, 5 }, // extend/vpsravd/pack sequence. 797 { ISD::SRA, MVT::v16i16, 7 }, // extend/vpsravd/pack sequence. 798 { ISD::SRA, MVT::v32i16, 14 }, // 2*extend/vpsravd/pack sequence. 799 { ISD::SRA, MVT::v2i64, 2 }, // srl/xor/sub sequence. 800 { ISD::SRA, MVT::v4i64, 2 }, // srl/xor/sub sequence. 801 802 { ISD::SUB, MVT::v32i8, 1 }, // psubb 803 { ISD::ADD, MVT::v32i8, 1 }, // paddb 804 { ISD::SUB, MVT::v16i16, 1 }, // psubw 805 { ISD::ADD, MVT::v16i16, 1 }, // paddw 806 { ISD::SUB, MVT::v8i32, 1 }, // psubd 807 { ISD::ADD, MVT::v8i32, 1 }, // paddd 808 { ISD::SUB, MVT::v4i64, 1 }, // psubq 809 { ISD::ADD, MVT::v4i64, 1 }, // paddq 810 811 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 812 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 813 { ISD::MUL, MVT::v4i64, 6 }, // 3*pmuludq/3*shift/2*add 814 815 { ISD::FNEG, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 816 { ISD::FNEG, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 817 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 818 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 819 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 820 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 821 { ISD::FMUL, MVT::f64, 1 }, // Haswell from http://www.agner.org/ 822 { ISD::FMUL, MVT::v2f64, 1 }, // Haswell from http://www.agner.org/ 823 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 824 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 825 826 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 827 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 828 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 829 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 830 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 831 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 832 }; 833 834 // Look for AVX2 lowering tricks for custom cases. 835 if (ST->hasAVX2()) 836 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 837 return LT.first * Entry->Cost; 838 839 static const CostTblEntry AVX1CostTable[] = { 840 // We don't have to scalarize unsupported ops. We can issue two half-sized 841 // operations and we only need to extract the upper YMM half. 842 // Two ops + 1 extract + 1 insert = 4. 843 { ISD::MUL, MVT::v16i16, 4 }, 844 { ISD::MUL, MVT::v8i32, 5 }, // BTVER2 from http://www.agner.org/ 845 { ISD::MUL, MVT::v4i64, 12 }, 846 847 { ISD::SUB, MVT::v32i8, 4 }, 848 { ISD::ADD, MVT::v32i8, 4 }, 849 { ISD::SUB, MVT::v16i16, 4 }, 850 { ISD::ADD, MVT::v16i16, 4 }, 851 { ISD::SUB, MVT::v8i32, 4 }, 852 { ISD::ADD, MVT::v8i32, 4 }, 853 { ISD::SUB, MVT::v4i64, 4 }, 854 { ISD::ADD, MVT::v4i64, 4 }, 855 856 { ISD::SHL, MVT::v16i8, 10 }, // pblendvb sequence . 857 { ISD::SHL, MVT::v32i8, 22 }, // pblendvb sequence + split. 858 { ISD::SHL, MVT::v8i16, 6 }, // pblendvb sequence. 859 { ISD::SHL, MVT::v16i16, 13 }, // pblendvb sequence + split. 860 { ISD::SHL, MVT::v4i32, 3 }, // pslld/paddd/cvttps2dq/pmulld 861 { ISD::SHL, MVT::v8i32, 9 }, // pslld/paddd/cvttps2dq/pmulld + split 862 { ISD::SHL, MVT::v2i64, 2 }, // Shift each lane + blend. 863 { ISD::SHL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 864 865 { ISD::SRL, MVT::v16i8, 11 }, // pblendvb sequence. 866 { ISD::SRL, MVT::v32i8, 23 }, // pblendvb sequence + split. 867 { ISD::SRL, MVT::v8i16, 13 }, // pblendvb sequence. 868 { ISD::SRL, MVT::v16i16, 28 }, // pblendvb sequence + split. 869 { ISD::SRL, MVT::v4i32, 6 }, // Shift each lane + blend. 870 { ISD::SRL, MVT::v8i32, 14 }, // Shift each lane + blend + split. 871 { ISD::SRL, MVT::v2i64, 2 }, // Shift each lane + blend. 872 { ISD::SRL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 873 874 { ISD::SRA, MVT::v16i8, 21 }, // pblendvb sequence. 875 { ISD::SRA, MVT::v32i8, 44 }, // pblendvb sequence + split. 876 { ISD::SRA, MVT::v8i16, 13 }, // pblendvb sequence. 877 { ISD::SRA, MVT::v16i16, 28 }, // pblendvb sequence + split. 878 { ISD::SRA, MVT::v4i32, 6 }, // Shift each lane + blend. 879 { ISD::SRA, MVT::v8i32, 14 }, // Shift each lane + blend + split. 880 { ISD::SRA, MVT::v2i64, 5 }, // Shift each lane + blend. 881 { ISD::SRA, MVT::v4i64, 12 }, // Shift each lane + blend + split. 882 883 { ISD::FNEG, MVT::v4f64, 2 }, // BTVER2 from http://www.agner.org/ 884 { ISD::FNEG, MVT::v8f32, 2 }, // BTVER2 from http://www.agner.org/ 885 886 { ISD::FMUL, MVT::f64, 2 }, // BTVER2 from http://www.agner.org/ 887 { ISD::FMUL, MVT::v2f64, 2 }, // BTVER2 from http://www.agner.org/ 888 { ISD::FMUL, MVT::v4f64, 4 }, // BTVER2 from http://www.agner.org/ 889 890 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 891 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 892 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 893 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 894 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 895 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 896 }; 897 898 if (ST->hasAVX()) 899 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 900 return LT.first * Entry->Cost; 901 902 static const CostTblEntry SSE42CostTable[] = { 903 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 904 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 905 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 906 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 907 908 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 909 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 910 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 911 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 912 913 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 914 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 915 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 916 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 917 918 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 919 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 920 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 921 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 922 923 { ISD::MUL, MVT::v2i64, 6 } // 3*pmuludq/3*shift/2*add 924 }; 925 926 if (ST->hasSSE42()) 927 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 928 return LT.first * Entry->Cost; 929 930 static const CostTblEntry SSE41CostTable[] = { 931 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 932 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 933 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 934 935 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 936 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 937 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 938 939 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 940 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 941 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 942 943 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 944 }; 945 946 if (ST->hasSSE41()) 947 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 948 return LT.first * Entry->Cost; 949 950 static const CostTblEntry SSE2CostTable[] = { 951 // We don't correctly identify costs of casts because they are marked as 952 // custom. 953 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 954 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 955 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 956 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 957 958 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 959 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 960 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 961 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 962 963 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 964 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 965 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 966 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 967 968 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 969 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 970 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 971 972 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 973 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 974 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 975 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 976 977 { ISD::FNEG, MVT::f32, 1 }, // Pentium IV from http://www.agner.org/ 978 { ISD::FNEG, MVT::f64, 1 }, // Pentium IV from http://www.agner.org/ 979 { ISD::FNEG, MVT::v4f32, 1 }, // Pentium IV from http://www.agner.org/ 980 { ISD::FNEG, MVT::v2f64, 1 }, // Pentium IV from http://www.agner.org/ 981 982 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 983 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 984 985 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 986 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 987 }; 988 989 if (ST->hasSSE2()) 990 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 991 return LT.first * Entry->Cost; 992 993 static const CostTblEntry SSE1CostTable[] = { 994 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 995 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 996 997 { ISD::FNEG, MVT::f32, 2 }, // Pentium III from http://www.agner.org/ 998 { ISD::FNEG, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 999 1000 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1001 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1002 1003 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1004 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1005 }; 1006 1007 if (ST->hasSSE1()) 1008 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 1009 return LT.first * Entry->Cost; 1010 1011 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 1012 { ISD::ADD, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1013 { ISD::SUB, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1014 }; 1015 1016 if (ST->is64Bit()) 1017 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, LT.second)) 1018 return LT.first * Entry->Cost; 1019 1020 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 1021 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1022 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1023 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1024 1025 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1026 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1027 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1028 }; 1029 1030 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, LT.second)) 1031 return LT.first * Entry->Cost; 1032 1033 // It is not a good idea to vectorize division. We have to scalarize it and 1034 // in the process we will often end up having to spilling regular 1035 // registers. The overhead of division is going to dominate most kernels 1036 // anyways so try hard to prevent vectorization of division - it is 1037 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 1038 // to hide "20 cycles" for each lane. 1039 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 1040 ISD == ISD::UDIV || ISD == ISD::UREM)) { 1041 InstructionCost ScalarCost = getArithmeticInstrCost( 1042 Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info, 1043 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 1044 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 1045 } 1046 1047 // Fallback to the default implementation. 1048 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info); 1049 } 1050 1051 InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, 1052 VectorType *BaseTp, 1053 ArrayRef<int> Mask, int Index, 1054 VectorType *SubTp) { 1055 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 1056 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 1057 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 1058 1059 Kind = improveShuffleKindFromMask(Kind, Mask); 1060 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 1061 if (Kind == TTI::SK_Transpose) 1062 Kind = TTI::SK_PermuteTwoSrc; 1063 1064 // For Broadcasts we are splatting the first element from the first input 1065 // register, so only need to reference that input and all the output 1066 // registers are the same. 1067 if (Kind == TTI::SK_Broadcast) 1068 LT.first = 1; 1069 1070 // Subvector extractions are free if they start at the beginning of a 1071 // vector and cheap if the subvectors are aligned. 1072 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 1073 int NumElts = LT.second.getVectorNumElements(); 1074 if ((Index % NumElts) == 0) 1075 return 0; 1076 std::pair<InstructionCost, MVT> SubLT = 1077 TLI->getTypeLegalizationCost(DL, SubTp); 1078 if (SubLT.second.isVector()) { 1079 int NumSubElts = SubLT.second.getVectorNumElements(); 1080 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1081 return SubLT.first; 1082 // Handle some cases for widening legalization. For now we only handle 1083 // cases where the original subvector was naturally aligned and evenly 1084 // fit in its legalized subvector type. 1085 // FIXME: Remove some of the alignment restrictions. 1086 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 1087 // vectors. 1088 int OrigSubElts = cast<FixedVectorType>(SubTp)->getNumElements(); 1089 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 1090 (NumSubElts % OrigSubElts) == 0 && 1091 LT.second.getVectorElementType() == 1092 SubLT.second.getVectorElementType() && 1093 LT.second.getVectorElementType().getSizeInBits() == 1094 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 1095 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 1096 "Unexpected number of elements!"); 1097 auto *VecTy = FixedVectorType::get(BaseTp->getElementType(), 1098 LT.second.getVectorNumElements()); 1099 auto *SubTy = FixedVectorType::get(BaseTp->getElementType(), 1100 SubLT.second.getVectorNumElements()); 1101 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 1102 InstructionCost ExtractCost = getShuffleCost( 1103 TTI::SK_ExtractSubvector, VecTy, None, ExtractIndex, SubTy); 1104 1105 // If the original size is 32-bits or more, we can use pshufd. Otherwise 1106 // if we have SSSE3 we can use pshufb. 1107 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 1108 return ExtractCost + 1; // pshufd or pshufb 1109 1110 assert(SubTp->getPrimitiveSizeInBits() == 16 && 1111 "Unexpected vector size"); 1112 1113 return ExtractCost + 2; // worst case pshufhw + pshufd 1114 } 1115 } 1116 } 1117 1118 // Subvector insertions are cheap if the subvectors are aligned. 1119 // Note that in general, the insertion starting at the beginning of a vector 1120 // isn't free, because we need to preserve the rest of the wide vector. 1121 if (Kind == TTI::SK_InsertSubvector && LT.second.isVector()) { 1122 int NumElts = LT.second.getVectorNumElements(); 1123 std::pair<InstructionCost, MVT> SubLT = 1124 TLI->getTypeLegalizationCost(DL, SubTp); 1125 if (SubLT.second.isVector()) { 1126 int NumSubElts = SubLT.second.getVectorNumElements(); 1127 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1128 return SubLT.first; 1129 } 1130 } 1131 1132 // Handle some common (illegal) sub-vector types as they are often very cheap 1133 // to shuffle even on targets without PSHUFB. 1134 EVT VT = TLI->getValueType(DL, BaseTp); 1135 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 1136 !ST->hasSSSE3()) { 1137 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 1138 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 1139 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1140 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1141 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1142 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1143 1144 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1145 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1146 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1147 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1148 1149 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1150 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1151 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1152 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1153 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1154 1155 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1156 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1157 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1158 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1159 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1160 }; 1161 1162 if (ST->hasSSE2()) 1163 if (const auto *Entry = 1164 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1165 return Entry->Cost; 1166 } 1167 1168 // We are going to permute multiple sources and the result will be in multiple 1169 // destinations. Providing an accurate cost only for splits where the element 1170 // type remains the same. 1171 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1172 MVT LegalVT = LT.second; 1173 if (LegalVT.isVector() && 1174 LegalVT.getVectorElementType().getSizeInBits() == 1175 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1176 LegalVT.getVectorNumElements() < 1177 cast<FixedVectorType>(BaseTp)->getNumElements()) { 1178 1179 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1180 unsigned LegalVTSize = LegalVT.getStoreSize(); 1181 // Number of source vectors after legalization: 1182 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1183 // Number of destination vectors after legalization: 1184 InstructionCost NumOfDests = LT.first; 1185 1186 auto *SingleOpTy = FixedVectorType::get(BaseTp->getElementType(), 1187 LegalVT.getVectorNumElements()); 1188 1189 InstructionCost NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1190 return NumOfShuffles * getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 1191 None, 0, nullptr); 1192 } 1193 1194 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1195 } 1196 1197 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1198 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1199 // We assume that source and destination have the same vector type. 1200 InstructionCost NumOfDests = LT.first; 1201 InstructionCost NumOfShufflesPerDest = LT.first * 2 - 1; 1202 LT.first = NumOfDests * NumOfShufflesPerDest; 1203 } 1204 1205 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1206 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1207 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1208 1209 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1210 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1211 1212 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b 1213 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b 1214 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2} // vpermt2b 1215 }; 1216 1217 if (ST->hasVBMI()) 1218 if (const auto *Entry = 1219 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1220 return LT.first * Entry->Cost; 1221 1222 static const CostTblEntry AVX512BWShuffleTbl[] = { 1223 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1224 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1225 1226 {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw 1227 {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw 1228 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1229 1230 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw 1231 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw 1232 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1233 1234 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w 1235 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w 1236 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2}, // vpermt2w 1237 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1238 1239 {TTI::SK_Select, MVT::v32i16, 1}, // vblendmw 1240 {TTI::SK_Select, MVT::v64i8, 1}, // vblendmb 1241 }; 1242 1243 if (ST->hasBWI()) 1244 if (const auto *Entry = 1245 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1246 return LT.first * Entry->Cost; 1247 1248 static const CostTblEntry AVX512ShuffleTbl[] = { 1249 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1250 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1251 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1252 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1253 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1254 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1255 1256 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1257 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1258 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1259 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1260 {TTI::SK_Reverse, MVT::v32i16, 7}, // per mca 1261 {TTI::SK_Reverse, MVT::v64i8, 7}, // per mca 1262 1263 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1264 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1265 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1266 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1267 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1268 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1269 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1270 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1271 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1272 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1273 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1274 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1275 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1276 1277 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1278 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1279 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1280 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1281 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1282 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1283 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1284 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1285 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1286 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1287 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1288 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1289 1290 // FIXME: This just applies the type legalization cost rules above 1291 // assuming these completely split. 1292 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1293 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1294 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1295 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1296 1297 {TTI::SK_Select, MVT::v32i16, 1}, // vpternlogq 1298 {TTI::SK_Select, MVT::v64i8, 1}, // vpternlogq 1299 {TTI::SK_Select, MVT::v8f64, 1}, // vblendmpd 1300 {TTI::SK_Select, MVT::v16f32, 1}, // vblendmps 1301 {TTI::SK_Select, MVT::v8i64, 1}, // vblendmq 1302 {TTI::SK_Select, MVT::v16i32, 1}, // vblendmd 1303 }; 1304 1305 if (ST->hasAVX512()) 1306 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1307 return LT.first * Entry->Cost; 1308 1309 static const CostTblEntry AVX2ShuffleTbl[] = { 1310 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1311 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1312 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1313 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1314 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1315 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1316 1317 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1318 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1319 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1320 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1321 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1322 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1323 1324 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1325 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1326 1327 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1328 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1329 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1330 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1331 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1332 // + vpblendvb 1333 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1334 // + vpblendvb 1335 1336 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1337 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1338 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1339 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1340 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1341 // + vpblendvb 1342 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1343 // + vpblendvb 1344 }; 1345 1346 if (ST->hasAVX2()) 1347 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1348 return LT.first * Entry->Cost; 1349 1350 static const CostTblEntry XOPShuffleTbl[] = { 1351 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1352 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1353 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1354 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1355 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1356 // + vinsertf128 1357 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1358 // + vinsertf128 1359 1360 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1361 // + vinsertf128 1362 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1363 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1364 // + vinsertf128 1365 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1366 }; 1367 1368 if (ST->hasXOP()) 1369 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1370 return LT.first * Entry->Cost; 1371 1372 static const CostTblEntry AVX1ShuffleTbl[] = { 1373 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1374 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1375 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1376 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1377 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1378 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1379 1380 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1381 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1382 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1383 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1384 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1385 // + vinsertf128 1386 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1387 // + vinsertf128 1388 1389 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1390 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1391 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1392 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1393 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1394 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1395 1396 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1397 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1398 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1399 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1400 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1401 // + 2*por + vinsertf128 1402 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1403 // + 2*por + vinsertf128 1404 1405 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1406 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1407 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1408 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1409 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1410 // + 4*por + vinsertf128 1411 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1412 // + 4*por + vinsertf128 1413 }; 1414 1415 if (ST->hasAVX()) 1416 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1417 return LT.first * Entry->Cost; 1418 1419 static const CostTblEntry SSE41ShuffleTbl[] = { 1420 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1421 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1422 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1423 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1424 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1425 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1426 }; 1427 1428 if (ST->hasSSE41()) 1429 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1430 return LT.first * Entry->Cost; 1431 1432 static const CostTblEntry SSSE3ShuffleTbl[] = { 1433 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1434 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1435 1436 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1437 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1438 1439 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1440 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1441 1442 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1443 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1444 1445 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1446 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1447 }; 1448 1449 if (ST->hasSSSE3()) 1450 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1451 return LT.first * Entry->Cost; 1452 1453 static const CostTblEntry SSE2ShuffleTbl[] = { 1454 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1455 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1456 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1457 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1458 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1459 1460 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1461 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1462 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1463 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1464 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1465 // + 2*pshufd + 2*unpck + packus 1466 1467 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1468 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1469 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1470 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1471 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1472 1473 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1474 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1475 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1476 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1477 // + pshufd/unpck 1478 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1479 // + 2*pshufd + 2*unpck + 2*packus 1480 1481 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1482 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1483 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1484 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1485 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1486 }; 1487 1488 if (ST->hasSSE2()) 1489 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1490 return LT.first * Entry->Cost; 1491 1492 static const CostTblEntry SSE1ShuffleTbl[] = { 1493 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1494 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1495 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1496 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1497 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1498 }; 1499 1500 if (ST->hasSSE1()) 1501 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1502 return LT.first * Entry->Cost; 1503 1504 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1505 } 1506 1507 InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, 1508 Type *Src, 1509 TTI::CastContextHint CCH, 1510 TTI::TargetCostKind CostKind, 1511 const Instruction *I) { 1512 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1513 assert(ISD && "Invalid opcode"); 1514 1515 // TODO: Allow non-throughput costs that aren't binary. 1516 auto AdjustCost = [&CostKind](InstructionCost Cost) -> InstructionCost { 1517 if (CostKind != TTI::TCK_RecipThroughput) 1518 return Cost == 0 ? 0 : 1; 1519 return Cost; 1520 }; 1521 1522 // The cost tables include both specific, custom (non-legal) src/dst type 1523 // conversions and generic, legalized types. We test for customs first, before 1524 // falling back to legalization. 1525 // FIXME: Need a better design of the cost table to handle non-simple types of 1526 // potential massive combinations (elem_num x src_type x dst_type). 1527 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1528 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1529 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1530 1531 // Mask sign extend has an instruction. 1532 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1533 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1534 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1535 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1536 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1537 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1538 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1539 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1540 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1541 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1542 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1543 1544 // Mask zero extend is a sext + shift. 1545 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1546 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1547 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1548 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1549 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1550 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1551 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1552 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1553 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1554 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1555 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1556 1557 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, 1558 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm 1559 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // widen to zmm 1560 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // widen to zmm 1561 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // vpmovwb 1562 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // widen to zmm 1563 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // widen to zmm 1564 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // vpmovwb 1565 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // widen to zmm 1566 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // widen to zmm 1567 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // vpmovwb 1568 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // widen to zmm 1569 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // widen to zmm 1570 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // widen to zmm 1571 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, 1572 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, 1573 }; 1574 1575 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1576 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1577 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1578 1579 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1580 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1581 1582 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1583 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1584 1585 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1586 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1587 }; 1588 1589 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1590 // 256-bit wide vectors. 1591 1592 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1593 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1594 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1595 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1596 1597 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1598 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1599 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1600 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd 1601 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1602 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1603 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1604 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd 1605 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd 1606 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd 1607 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd 1608 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd 1609 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq 1610 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq 1611 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq 1612 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 2 }, // vpmovdb 1613 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 2 }, // vpmovdb 1614 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, // vpmovdb 1615 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, // vpmovdb 1616 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 2 }, // vpmovqb 1617 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 1 }, // vpshufb 1618 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, // vpmovqb 1619 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, // vpmovqw 1620 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, // vpmovqd 1621 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd 1622 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb 1623 1624 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32 1625 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, 1626 1627 // Sign extend is zmm vpternlogd+vptruncdb. 1628 // Zero extend is zmm broadcast load+vptruncdw. 1629 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 }, 1630 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 }, 1631 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, 1632 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, 1633 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, 1634 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, 1635 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 }, 1636 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 }, 1637 1638 // Sign extend is zmm vpternlogd+vptruncdw. 1639 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw. 1640 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 }, 1641 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1642 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 }, 1643 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1644 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 }, 1645 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1646 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 }, 1647 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1648 1649 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd 1650 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld 1651 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd 1652 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld 1653 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd 1654 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld 1655 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq 1656 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq 1657 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq 1658 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq 1659 1660 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd 1661 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld 1662 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq 1663 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq 1664 1665 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1666 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1667 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1668 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1669 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1670 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1671 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1672 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1673 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1674 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1675 1676 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1677 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1678 1679 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1680 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1681 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1682 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1683 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1684 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1685 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1686 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1687 1688 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1689 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1690 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1691 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1692 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1693 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1694 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1695 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1696 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1697 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1698 1699 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f64, 3 }, 1700 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, 1701 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 1 }, 1702 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 3 }, 1703 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 3 }, 1704 { ISD::FP_TO_SINT, MVT::v16i32, MVT::v16f64, 3 }, 1705 1706 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1707 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, 1708 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, 1709 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1710 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, 1711 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, 1712 }; 1713 1714 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1715 // Mask sign extend has an instruction. 1716 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1717 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1718 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1719 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1720 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1721 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1722 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1723 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1724 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1725 1726 // Mask zero extend is a sext + shift. 1727 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1728 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1729 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1730 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1731 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1732 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1733 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1734 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1735 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1736 1737 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, 1738 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // vpsllw+vptestmb 1739 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // vpsllw+vptestmw 1740 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // vpsllw+vptestmb 1741 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // vpsllw+vptestmw 1742 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // vpsllw+vptestmb 1743 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // vpsllw+vptestmw 1744 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // vpsllw+vptestmb 1745 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // vpsllw+vptestmw 1746 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // vpsllw+vptestmb 1747 }; 1748 1749 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1750 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1751 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1752 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1753 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1754 1755 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1756 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1757 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1758 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1759 1760 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1761 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1762 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1763 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1764 1765 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1766 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1767 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1768 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1769 }; 1770 1771 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 1772 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1773 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1774 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1775 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 8 }, // split+2*v8i8 1776 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1777 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1778 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1779 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16 1780 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // vpslld+vptestmd 1781 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd 1782 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // vpslld+vptestmd 1783 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // vpsllq+vptestmq 1784 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // vpsllq+vptestmq 1785 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // vpmovqd 1786 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, // vpmovqb 1787 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, // vpmovqw 1788 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, // vpmovwb 1789 1790 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb 1791 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb 1792 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 }, 1793 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 }, 1794 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 }, 1795 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 }, 1796 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 }, 1797 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 }, 1798 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 }, 1799 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 }, 1800 1801 // sign extend is vpcmpeq+maskedmove+vpmovdw 1802 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw 1803 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1804 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 }, 1805 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1806 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 }, 1807 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1808 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 }, 1809 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 }, 1810 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 }, 1811 1812 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd 1813 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld 1814 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd 1815 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld 1816 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd 1817 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld 1818 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq 1819 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq 1820 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq 1821 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq 1822 1823 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 1824 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1825 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1826 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1827 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1828 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1829 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1830 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1831 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 1832 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1833 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1834 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1835 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1836 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1837 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1838 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1839 1840 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 3 }, 1841 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 3 }, 1842 1843 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 1844 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 1845 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1846 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1847 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 1 }, 1848 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1849 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1850 }; 1851 1852 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1853 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1854 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1855 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1856 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1857 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1858 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1859 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1860 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1861 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1862 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1863 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1864 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1865 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1866 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1867 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1868 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1869 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1870 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1871 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1872 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1873 1874 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 1 }, 1875 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 1 }, 1876 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, 1877 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1878 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1879 1880 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1881 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1882 1883 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 1 }, 1884 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 1 }, 1885 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 3 }, 1886 1887 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 4 }, 1888 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 7 }, 1889 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 4 }, 1890 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 7 }, 1891 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 4 }, 1892 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 15 }, 1893 1894 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1895 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1896 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 3 }, 1897 1898 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1899 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1900 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 2 }, 1901 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 1902 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 1903 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 }, 1904 }; 1905 1906 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1907 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1908 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1909 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1910 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1911 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 1912 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 1913 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 1914 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 1915 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1916 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1917 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1918 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1919 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1920 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1921 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1922 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1923 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1924 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1925 1926 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 4 }, 1927 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 5 }, 1928 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 4 }, 1929 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 9 }, 1930 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, 11 }, 1931 1932 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // and+extract+packuswb 1933 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 2 }, // and+packusdw+packuswb 1934 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1935 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1936 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1937 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 3 }, // and+extract+2*packusdw 1938 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1939 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 11 }, 1940 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 9 }, 1941 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 }, 1942 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 11 }, 1943 1944 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1945 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1946 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1947 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1948 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1949 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1950 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1951 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1952 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1953 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 1954 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 1955 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 }, 1956 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 5 }, 1957 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 8 }, 1958 1959 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1960 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1961 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1962 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1963 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1964 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1965 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1966 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1967 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1968 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 4 }, 1969 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 10 }, 1970 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1971 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1972 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 18 }, 1973 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 10 }, 1974 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1975 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 10 }, 1976 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1977 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1978 1979 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 4 }, 1980 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f64, 3 }, 1981 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f64, 2 }, 1982 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 2 }, 1983 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 3 }, 1984 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 2 }, 1985 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 5 }, 1986 1987 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 5 }, 1988 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 9 }, 1989 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 5 }, 1990 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f64, 3 }, 1991 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f64, 2 }, 1992 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 9 }, 1993 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 4 }, 1994 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 3 }, 1995 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 9 }, 1996 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 19 }, 1997 1998 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 1999 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 2000 }; 2001 2002 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 2003 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 2004 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 2005 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 2006 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 2007 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 2008 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 2009 2010 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i8, 1 }, 2011 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i8, 1 }, 2012 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i8, 1 }, 2013 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i8, 1 }, 2014 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i8, 1 }, 2015 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i8, 1 }, 2016 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 2017 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 2018 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 2019 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 2020 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 2021 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 2022 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 2023 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 2024 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 2025 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 2026 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 2027 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 2028 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i16, 1 }, 2029 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i16, 1 }, 2030 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i16, 1 }, 2031 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i16, 1 }, 2032 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 2033 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 2034 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 2035 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 2036 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 2037 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 2038 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, 2039 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, 2040 2041 // These truncates end up widening elements. 2042 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 1 }, // PMOVXZBQ 2043 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 1 }, // PMOVXZWQ 2044 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 1 }, // PMOVXZBD 2045 2046 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 1 }, 2047 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 1 }, 2048 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 2049 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 2050 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 2051 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 2052 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 2053 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 2054 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 1 }, // PSHUFB 2055 2056 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 1 }, 2057 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 1 }, 2058 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 1 }, 2059 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 1 }, 2060 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 2061 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 1 }, 2062 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2063 2064 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 1 }, 2065 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 1 }, 2066 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 2067 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 2068 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 12 }, 2069 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 22 }, 2070 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 4 }, 2071 2072 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 3 }, 2073 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 3 }, 2074 2075 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 3 }, 2076 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 3 }, 2077 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, 2078 }; 2079 2080 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 2081 // These are somewhat magic numbers justified by comparing the 2082 // output of llvm-mca for our various supported scheduler models 2083 // and basing it off the worst case scenario. 2084 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 3 }, 2085 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 3 }, 2086 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 3 }, 2087 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 3 }, 2088 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 3 }, 2089 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 4 }, 2090 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 3 }, 2091 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 4 }, 2092 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 3 }, 2093 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4 }, 2094 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 8 }, 2095 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 8 }, 2096 2097 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 3 }, 2098 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 3 }, 2099 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 8 }, 2100 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 9 }, 2101 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 4 }, 2102 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 4 }, 2103 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 4 }, 2104 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 4 }, 2105 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 7 }, 2106 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 2107 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 15 }, 2108 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 18 }, 2109 2110 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 4 }, 2111 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 2 }, 2112 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, 2113 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, 2114 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, 2115 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 4 }, 2116 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 1 }, 2117 2118 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 2119 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 15 }, 2120 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 4 }, 2121 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 4 }, 2122 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 }, 2123 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 2 }, 2124 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 }, 2125 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 4 }, 2126 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 8 }, 2127 2128 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 2129 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 2130 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 2131 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 2132 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 2133 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 2134 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 2135 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 2136 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 2137 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 2138 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 2139 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 2140 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 2141 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 2142 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 2143 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 2144 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 2145 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 2146 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 2147 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 2148 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 2149 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 2150 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 2151 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 2152 2153 // These truncates are really widening elements. 2154 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 1 }, // PSHUFD 2155 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // PUNPCKLWD+DQ 2156 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // PUNPCKLBW+WD+PSHUFD 2157 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 1 }, // PUNPCKLWD 2158 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // PUNPCKLBW+WD 2159 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 1 }, // PUNPCKLBW 2160 2161 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // PAND+PACKUSWB 2162 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // PAND+PACKUSWB 2163 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // PAND+PACKUSWB 2164 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 2165 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 3 }, // PAND+2*PACKUSWB 2166 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 2167 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 2168 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 2169 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 2170 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 2171 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2172 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 2173 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 2174 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 2175 { ISD::TRUNCATE, MVT::v2i32, MVT::v2i64, 1 }, // PSHUFD 2176 }; 2177 2178 // Attempt to map directly to (simple) MVT types to let us match custom entries. 2179 EVT SrcTy = TLI->getValueType(DL, Src); 2180 EVT DstTy = TLI->getValueType(DL, Dst); 2181 2182 // The function getSimpleVT only handles simple value types. 2183 if (SrcTy.isSimple() && DstTy.isSimple()) { 2184 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 2185 MVT SimpleDstTy = DstTy.getSimpleVT(); 2186 2187 if (ST->useAVX512Regs()) { 2188 if (ST->hasBWI()) 2189 if (const auto *Entry = ConvertCostTableLookup( 2190 AVX512BWConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2191 return AdjustCost(Entry->Cost); 2192 2193 if (ST->hasDQI()) 2194 if (const auto *Entry = ConvertCostTableLookup( 2195 AVX512DQConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2196 return AdjustCost(Entry->Cost); 2197 2198 if (ST->hasAVX512()) 2199 if (const auto *Entry = ConvertCostTableLookup( 2200 AVX512FConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2201 return AdjustCost(Entry->Cost); 2202 } 2203 2204 if (ST->hasBWI()) 2205 if (const auto *Entry = ConvertCostTableLookup( 2206 AVX512BWVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2207 return AdjustCost(Entry->Cost); 2208 2209 if (ST->hasDQI()) 2210 if (const auto *Entry = ConvertCostTableLookup( 2211 AVX512DQVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2212 return AdjustCost(Entry->Cost); 2213 2214 if (ST->hasAVX512()) 2215 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2216 SimpleDstTy, SimpleSrcTy)) 2217 return AdjustCost(Entry->Cost); 2218 2219 if (ST->hasAVX2()) { 2220 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2221 SimpleDstTy, SimpleSrcTy)) 2222 return AdjustCost(Entry->Cost); 2223 } 2224 2225 if (ST->hasAVX()) { 2226 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2227 SimpleDstTy, SimpleSrcTy)) 2228 return AdjustCost(Entry->Cost); 2229 } 2230 2231 if (ST->hasSSE41()) { 2232 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2233 SimpleDstTy, SimpleSrcTy)) 2234 return AdjustCost(Entry->Cost); 2235 } 2236 2237 if (ST->hasSSE2()) { 2238 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2239 SimpleDstTy, SimpleSrcTy)) 2240 return AdjustCost(Entry->Cost); 2241 } 2242 } 2243 2244 // Fall back to legalized types. 2245 std::pair<InstructionCost, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 2246 std::pair<InstructionCost, MVT> LTDest = 2247 TLI->getTypeLegalizationCost(DL, Dst); 2248 2249 if (ST->useAVX512Regs()) { 2250 if (ST->hasBWI()) 2251 if (const auto *Entry = ConvertCostTableLookup( 2252 AVX512BWConversionTbl, ISD, LTDest.second, LTSrc.second)) 2253 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2254 2255 if (ST->hasDQI()) 2256 if (const auto *Entry = ConvertCostTableLookup( 2257 AVX512DQConversionTbl, ISD, LTDest.second, LTSrc.second)) 2258 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2259 2260 if (ST->hasAVX512()) 2261 if (const auto *Entry = ConvertCostTableLookup( 2262 AVX512FConversionTbl, ISD, LTDest.second, LTSrc.second)) 2263 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2264 } 2265 2266 if (ST->hasBWI()) 2267 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 2268 LTDest.second, LTSrc.second)) 2269 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2270 2271 if (ST->hasDQI()) 2272 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 2273 LTDest.second, LTSrc.second)) 2274 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2275 2276 if (ST->hasAVX512()) 2277 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2278 LTDest.second, LTSrc.second)) 2279 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2280 2281 if (ST->hasAVX2()) 2282 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2283 LTDest.second, LTSrc.second)) 2284 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2285 2286 if (ST->hasAVX()) 2287 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2288 LTDest.second, LTSrc.second)) 2289 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2290 2291 if (ST->hasSSE41()) 2292 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2293 LTDest.second, LTSrc.second)) 2294 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2295 2296 if (ST->hasSSE2()) 2297 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2298 LTDest.second, LTSrc.second)) 2299 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2300 2301 // Fallback, for i8/i16 sitofp/uitofp cases we need to extend to i32 for 2302 // sitofp. 2303 if ((ISD == ISD::SINT_TO_FP || ISD == ISD::UINT_TO_FP) && 2304 1 < Src->getScalarSizeInBits() && Src->getScalarSizeInBits() < 32) { 2305 Type *ExtSrc = Src->getWithNewBitWidth(32); 2306 unsigned ExtOpc = 2307 (ISD == ISD::SINT_TO_FP) ? Instruction::SExt : Instruction::ZExt; 2308 2309 // For scalar loads the extend would be free. 2310 InstructionCost ExtCost = 0; 2311 if (!(Src->isIntegerTy() && I && isa<LoadInst>(I->getOperand(0)))) 2312 ExtCost = getCastInstrCost(ExtOpc, ExtSrc, Src, CCH, CostKind); 2313 2314 return ExtCost + getCastInstrCost(Instruction::SIToFP, Dst, ExtSrc, 2315 TTI::CastContextHint::None, CostKind); 2316 } 2317 2318 // Fallback for fptosi/fptoui i8/i16 cases we need to truncate from fptosi 2319 // i32. 2320 if ((ISD == ISD::FP_TO_SINT || ISD == ISD::FP_TO_UINT) && 2321 1 < Dst->getScalarSizeInBits() && Dst->getScalarSizeInBits() < 32) { 2322 Type *TruncDst = Dst->getWithNewBitWidth(32); 2323 return getCastInstrCost(Instruction::FPToSI, TruncDst, Src, CCH, CostKind) + 2324 getCastInstrCost(Instruction::Trunc, Dst, TruncDst, 2325 TTI::CastContextHint::None, CostKind); 2326 } 2327 2328 return AdjustCost( 2329 BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I)); 2330 } 2331 2332 InstructionCost X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 2333 Type *CondTy, 2334 CmpInst::Predicate VecPred, 2335 TTI::TargetCostKind CostKind, 2336 const Instruction *I) { 2337 // TODO: Handle other cost kinds. 2338 if (CostKind != TTI::TCK_RecipThroughput) 2339 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, 2340 I); 2341 2342 // Legalize the type. 2343 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2344 2345 MVT MTy = LT.second; 2346 2347 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2348 assert(ISD && "Invalid opcode"); 2349 2350 unsigned ExtraCost = 0; 2351 if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) { 2352 // Some vector comparison predicates cost extra instructions. 2353 if (MTy.isVector() && 2354 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 2355 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 2356 ST->hasBWI())) { 2357 switch (cast<CmpInst>(I)->getPredicate()) { 2358 case CmpInst::Predicate::ICMP_NE: 2359 // xor(cmpeq(x,y),-1) 2360 ExtraCost = 1; 2361 break; 2362 case CmpInst::Predicate::ICMP_SGE: 2363 case CmpInst::Predicate::ICMP_SLE: 2364 // xor(cmpgt(x,y),-1) 2365 ExtraCost = 1; 2366 break; 2367 case CmpInst::Predicate::ICMP_ULT: 2368 case CmpInst::Predicate::ICMP_UGT: 2369 // cmpgt(xor(x,signbit),xor(y,signbit)) 2370 // xor(cmpeq(pmaxu(x,y),x),-1) 2371 ExtraCost = 2; 2372 break; 2373 case CmpInst::Predicate::ICMP_ULE: 2374 case CmpInst::Predicate::ICMP_UGE: 2375 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 2376 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 2377 // cmpeq(psubus(x,y),0) 2378 // cmpeq(pminu(x,y),x) 2379 ExtraCost = 1; 2380 } else { 2381 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 2382 ExtraCost = 3; 2383 } 2384 break; 2385 default: 2386 break; 2387 } 2388 } 2389 } 2390 2391 static const CostTblEntry SLMCostTbl[] = { 2392 // slm pcmpeq/pcmpgt throughput is 2 2393 { ISD::SETCC, MVT::v2i64, 2 }, 2394 }; 2395 2396 static const CostTblEntry AVX512BWCostTbl[] = { 2397 { ISD::SETCC, MVT::v32i16, 1 }, 2398 { ISD::SETCC, MVT::v64i8, 1 }, 2399 2400 { ISD::SELECT, MVT::v32i16, 1 }, 2401 { ISD::SELECT, MVT::v64i8, 1 }, 2402 }; 2403 2404 static const CostTblEntry AVX512CostTbl[] = { 2405 { ISD::SETCC, MVT::v8i64, 1 }, 2406 { ISD::SETCC, MVT::v16i32, 1 }, 2407 { ISD::SETCC, MVT::v8f64, 1 }, 2408 { ISD::SETCC, MVT::v16f32, 1 }, 2409 2410 { ISD::SELECT, MVT::v8i64, 1 }, 2411 { ISD::SELECT, MVT::v16i32, 1 }, 2412 { ISD::SELECT, MVT::v8f64, 1 }, 2413 { ISD::SELECT, MVT::v16f32, 1 }, 2414 2415 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 2416 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 2417 2418 { ISD::SELECT, MVT::v32i16, 2 }, // FIXME: should be 3 2419 { ISD::SELECT, MVT::v64i8, 2 }, // FIXME: should be 3 2420 }; 2421 2422 static const CostTblEntry AVX2CostTbl[] = { 2423 { ISD::SETCC, MVT::v4i64, 1 }, 2424 { ISD::SETCC, MVT::v8i32, 1 }, 2425 { ISD::SETCC, MVT::v16i16, 1 }, 2426 { ISD::SETCC, MVT::v32i8, 1 }, 2427 2428 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 2429 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 2430 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 2431 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 2432 }; 2433 2434 static const CostTblEntry AVX1CostTbl[] = { 2435 { ISD::SETCC, MVT::v4f64, 1 }, 2436 { ISD::SETCC, MVT::v8f32, 1 }, 2437 // AVX1 does not support 8-wide integer compare. 2438 { ISD::SETCC, MVT::v4i64, 4 }, 2439 { ISD::SETCC, MVT::v8i32, 4 }, 2440 { ISD::SETCC, MVT::v16i16, 4 }, 2441 { ISD::SETCC, MVT::v32i8, 4 }, 2442 2443 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 2444 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 2445 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 2446 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 2447 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 2448 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 2449 }; 2450 2451 static const CostTblEntry SSE42CostTbl[] = { 2452 { ISD::SETCC, MVT::v2f64, 1 }, 2453 { ISD::SETCC, MVT::v4f32, 1 }, 2454 { ISD::SETCC, MVT::v2i64, 1 }, 2455 }; 2456 2457 static const CostTblEntry SSE41CostTbl[] = { 2458 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 2459 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 2460 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 2461 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 2462 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 2463 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 2464 }; 2465 2466 static const CostTblEntry SSE2CostTbl[] = { 2467 { ISD::SETCC, MVT::v2f64, 2 }, 2468 { ISD::SETCC, MVT::f64, 1 }, 2469 { ISD::SETCC, MVT::v2i64, 8 }, 2470 { ISD::SETCC, MVT::v4i32, 1 }, 2471 { ISD::SETCC, MVT::v8i16, 1 }, 2472 { ISD::SETCC, MVT::v16i8, 1 }, 2473 2474 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 2475 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 2476 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 2477 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 2478 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 2479 }; 2480 2481 static const CostTblEntry SSE1CostTbl[] = { 2482 { ISD::SETCC, MVT::v4f32, 2 }, 2483 { ISD::SETCC, MVT::f32, 1 }, 2484 2485 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 2486 }; 2487 2488 if (ST->isSLM()) 2489 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2490 return LT.first * (ExtraCost + Entry->Cost); 2491 2492 if (ST->hasBWI()) 2493 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2494 return LT.first * (ExtraCost + Entry->Cost); 2495 2496 if (ST->hasAVX512()) 2497 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2498 return LT.first * (ExtraCost + Entry->Cost); 2499 2500 if (ST->hasAVX2()) 2501 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2502 return LT.first * (ExtraCost + Entry->Cost); 2503 2504 if (ST->hasAVX()) 2505 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2506 return LT.first * (ExtraCost + Entry->Cost); 2507 2508 if (ST->hasSSE42()) 2509 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2510 return LT.first * (ExtraCost + Entry->Cost); 2511 2512 if (ST->hasSSE41()) 2513 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2514 return LT.first * (ExtraCost + Entry->Cost); 2515 2516 if (ST->hasSSE2()) 2517 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2518 return LT.first * (ExtraCost + Entry->Cost); 2519 2520 if (ST->hasSSE1()) 2521 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2522 return LT.first * (ExtraCost + Entry->Cost); 2523 2524 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I); 2525 } 2526 2527 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2528 2529 InstructionCost 2530 X86TTIImpl::getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 2531 TTI::TargetCostKind CostKind) { 2532 2533 // Costs should match the codegen from: 2534 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2535 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2536 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2537 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2538 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2539 2540 // TODO: Overflow intrinsics (*ADDO, *SUBO, *MULO) with vector types are not 2541 // specialized in these tables yet. 2542 static const CostTblEntry AVX512CDCostTbl[] = { 2543 { ISD::CTLZ, MVT::v8i64, 1 }, 2544 { ISD::CTLZ, MVT::v16i32, 1 }, 2545 { ISD::CTLZ, MVT::v32i16, 8 }, 2546 { ISD::CTLZ, MVT::v64i8, 20 }, 2547 { ISD::CTLZ, MVT::v4i64, 1 }, 2548 { ISD::CTLZ, MVT::v8i32, 1 }, 2549 { ISD::CTLZ, MVT::v16i16, 4 }, 2550 { ISD::CTLZ, MVT::v32i8, 10 }, 2551 { ISD::CTLZ, MVT::v2i64, 1 }, 2552 { ISD::CTLZ, MVT::v4i32, 1 }, 2553 { ISD::CTLZ, MVT::v8i16, 4 }, 2554 { ISD::CTLZ, MVT::v16i8, 4 }, 2555 }; 2556 static const CostTblEntry AVX512BWCostTbl[] = { 2557 { ISD::ABS, MVT::v32i16, 1 }, 2558 { ISD::ABS, MVT::v64i8, 1 }, 2559 { ISD::BITREVERSE, MVT::v8i64, 5 }, 2560 { ISD::BITREVERSE, MVT::v16i32, 5 }, 2561 { ISD::BITREVERSE, MVT::v32i16, 5 }, 2562 { ISD::BITREVERSE, MVT::v64i8, 5 }, 2563 { ISD::BSWAP, MVT::v8i64, 1 }, 2564 { ISD::BSWAP, MVT::v16i32, 1 }, 2565 { ISD::BSWAP, MVT::v32i16, 1 }, 2566 { ISD::CTLZ, MVT::v8i64, 23 }, 2567 { ISD::CTLZ, MVT::v16i32, 22 }, 2568 { ISD::CTLZ, MVT::v32i16, 18 }, 2569 { ISD::CTLZ, MVT::v64i8, 17 }, 2570 { ISD::CTPOP, MVT::v8i64, 7 }, 2571 { ISD::CTPOP, MVT::v16i32, 11 }, 2572 { ISD::CTPOP, MVT::v32i16, 9 }, 2573 { ISD::CTPOP, MVT::v64i8, 6 }, 2574 { ISD::CTTZ, MVT::v8i64, 10 }, 2575 { ISD::CTTZ, MVT::v16i32, 14 }, 2576 { ISD::CTTZ, MVT::v32i16, 12 }, 2577 { ISD::CTTZ, MVT::v64i8, 9 }, 2578 { ISD::SADDSAT, MVT::v32i16, 1 }, 2579 { ISD::SADDSAT, MVT::v64i8, 1 }, 2580 { ISD::SMAX, MVT::v32i16, 1 }, 2581 { ISD::SMAX, MVT::v64i8, 1 }, 2582 { ISD::SMIN, MVT::v32i16, 1 }, 2583 { ISD::SMIN, MVT::v64i8, 1 }, 2584 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2585 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2586 { ISD::UADDSAT, MVT::v32i16, 1 }, 2587 { ISD::UADDSAT, MVT::v64i8, 1 }, 2588 { ISD::UMAX, MVT::v32i16, 1 }, 2589 { ISD::UMAX, MVT::v64i8, 1 }, 2590 { ISD::UMIN, MVT::v32i16, 1 }, 2591 { ISD::UMIN, MVT::v64i8, 1 }, 2592 { ISD::USUBSAT, MVT::v32i16, 1 }, 2593 { ISD::USUBSAT, MVT::v64i8, 1 }, 2594 }; 2595 static const CostTblEntry AVX512CostTbl[] = { 2596 { ISD::ABS, MVT::v8i64, 1 }, 2597 { ISD::ABS, MVT::v16i32, 1 }, 2598 { ISD::ABS, MVT::v32i16, 2 }, // FIXME: include split 2599 { ISD::ABS, MVT::v64i8, 2 }, // FIXME: include split 2600 { ISD::ABS, MVT::v4i64, 1 }, 2601 { ISD::ABS, MVT::v2i64, 1 }, 2602 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2603 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2604 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2605 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2606 { ISD::BSWAP, MVT::v8i64, 4 }, 2607 { ISD::BSWAP, MVT::v16i32, 4 }, 2608 { ISD::BSWAP, MVT::v32i16, 4 }, 2609 { ISD::CTLZ, MVT::v8i64, 29 }, 2610 { ISD::CTLZ, MVT::v16i32, 35 }, 2611 { ISD::CTLZ, MVT::v32i16, 28 }, 2612 { ISD::CTLZ, MVT::v64i8, 18 }, 2613 { ISD::CTPOP, MVT::v8i64, 16 }, 2614 { ISD::CTPOP, MVT::v16i32, 24 }, 2615 { ISD::CTPOP, MVT::v32i16, 18 }, 2616 { ISD::CTPOP, MVT::v64i8, 12 }, 2617 { ISD::CTTZ, MVT::v8i64, 20 }, 2618 { ISD::CTTZ, MVT::v16i32, 28 }, 2619 { ISD::CTTZ, MVT::v32i16, 24 }, 2620 { ISD::CTTZ, MVT::v64i8, 18 }, 2621 { ISD::SMAX, MVT::v8i64, 1 }, 2622 { ISD::SMAX, MVT::v16i32, 1 }, 2623 { ISD::SMAX, MVT::v32i16, 2 }, // FIXME: include split 2624 { ISD::SMAX, MVT::v64i8, 2 }, // FIXME: include split 2625 { ISD::SMAX, MVT::v4i64, 1 }, 2626 { ISD::SMAX, MVT::v2i64, 1 }, 2627 { ISD::SMIN, MVT::v8i64, 1 }, 2628 { ISD::SMIN, MVT::v16i32, 1 }, 2629 { ISD::SMIN, MVT::v32i16, 2 }, // FIXME: include split 2630 { ISD::SMIN, MVT::v64i8, 2 }, // FIXME: include split 2631 { ISD::SMIN, MVT::v4i64, 1 }, 2632 { ISD::SMIN, MVT::v2i64, 1 }, 2633 { ISD::UMAX, MVT::v8i64, 1 }, 2634 { ISD::UMAX, MVT::v16i32, 1 }, 2635 { ISD::UMAX, MVT::v32i16, 2 }, // FIXME: include split 2636 { ISD::UMAX, MVT::v64i8, 2 }, // FIXME: include split 2637 { ISD::UMAX, MVT::v4i64, 1 }, 2638 { ISD::UMAX, MVT::v2i64, 1 }, 2639 { ISD::UMIN, MVT::v8i64, 1 }, 2640 { ISD::UMIN, MVT::v16i32, 1 }, 2641 { ISD::UMIN, MVT::v32i16, 2 }, // FIXME: include split 2642 { ISD::UMIN, MVT::v64i8, 2 }, // FIXME: include split 2643 { ISD::UMIN, MVT::v4i64, 1 }, 2644 { ISD::UMIN, MVT::v2i64, 1 }, 2645 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2646 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2647 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2648 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2649 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2650 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2651 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2652 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2653 { ISD::SADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2654 { ISD::SADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2655 { ISD::SSUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2656 { ISD::SSUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2657 { ISD::UADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2658 { ISD::UADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2659 { ISD::USUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2660 { ISD::USUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2661 { ISD::FMAXNUM, MVT::f32, 2 }, 2662 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2663 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2664 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2665 { ISD::FMAXNUM, MVT::f64, 2 }, 2666 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2667 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2668 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2669 }; 2670 static const CostTblEntry XOPCostTbl[] = { 2671 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2672 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2673 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2674 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2675 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2676 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2677 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2678 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2679 { ISD::BITREVERSE, MVT::i64, 3 }, 2680 { ISD::BITREVERSE, MVT::i32, 3 }, 2681 { ISD::BITREVERSE, MVT::i16, 3 }, 2682 { ISD::BITREVERSE, MVT::i8, 3 } 2683 }; 2684 static const CostTblEntry AVX2CostTbl[] = { 2685 { ISD::ABS, MVT::v4i64, 2 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2686 { ISD::ABS, MVT::v8i32, 1 }, 2687 { ISD::ABS, MVT::v16i16, 1 }, 2688 { ISD::ABS, MVT::v32i8, 1 }, 2689 { ISD::BITREVERSE, MVT::v4i64, 5 }, 2690 { ISD::BITREVERSE, MVT::v8i32, 5 }, 2691 { ISD::BITREVERSE, MVT::v16i16, 5 }, 2692 { ISD::BITREVERSE, MVT::v32i8, 5 }, 2693 { ISD::BSWAP, MVT::v4i64, 1 }, 2694 { ISD::BSWAP, MVT::v8i32, 1 }, 2695 { ISD::BSWAP, MVT::v16i16, 1 }, 2696 { ISD::CTLZ, MVT::v4i64, 23 }, 2697 { ISD::CTLZ, MVT::v8i32, 18 }, 2698 { ISD::CTLZ, MVT::v16i16, 14 }, 2699 { ISD::CTLZ, MVT::v32i8, 9 }, 2700 { ISD::CTPOP, MVT::v4i64, 7 }, 2701 { ISD::CTPOP, MVT::v8i32, 11 }, 2702 { ISD::CTPOP, MVT::v16i16, 9 }, 2703 { ISD::CTPOP, MVT::v32i8, 6 }, 2704 { ISD::CTTZ, MVT::v4i64, 10 }, 2705 { ISD::CTTZ, MVT::v8i32, 14 }, 2706 { ISD::CTTZ, MVT::v16i16, 12 }, 2707 { ISD::CTTZ, MVT::v32i8, 9 }, 2708 { ISD::SADDSAT, MVT::v16i16, 1 }, 2709 { ISD::SADDSAT, MVT::v32i8, 1 }, 2710 { ISD::SMAX, MVT::v8i32, 1 }, 2711 { ISD::SMAX, MVT::v16i16, 1 }, 2712 { ISD::SMAX, MVT::v32i8, 1 }, 2713 { ISD::SMIN, MVT::v8i32, 1 }, 2714 { ISD::SMIN, MVT::v16i16, 1 }, 2715 { ISD::SMIN, MVT::v32i8, 1 }, 2716 { ISD::SSUBSAT, MVT::v16i16, 1 }, 2717 { ISD::SSUBSAT, MVT::v32i8, 1 }, 2718 { ISD::UADDSAT, MVT::v16i16, 1 }, 2719 { ISD::UADDSAT, MVT::v32i8, 1 }, 2720 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 2721 { ISD::UMAX, MVT::v8i32, 1 }, 2722 { ISD::UMAX, MVT::v16i16, 1 }, 2723 { ISD::UMAX, MVT::v32i8, 1 }, 2724 { ISD::UMIN, MVT::v8i32, 1 }, 2725 { ISD::UMIN, MVT::v16i16, 1 }, 2726 { ISD::UMIN, MVT::v32i8, 1 }, 2727 { ISD::USUBSAT, MVT::v16i16, 1 }, 2728 { ISD::USUBSAT, MVT::v32i8, 1 }, 2729 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2730 { ISD::FMAXNUM, MVT::v8f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2731 { ISD::FMAXNUM, MVT::v4f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2732 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2733 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2734 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2735 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2736 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2737 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2738 }; 2739 static const CostTblEntry AVX1CostTbl[] = { 2740 { ISD::ABS, MVT::v4i64, 5 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2741 { ISD::ABS, MVT::v8i32, 3 }, 2742 { ISD::ABS, MVT::v16i16, 3 }, 2743 { ISD::ABS, MVT::v32i8, 3 }, 2744 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 2745 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 2746 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 2747 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 2748 { ISD::BSWAP, MVT::v4i64, 4 }, 2749 { ISD::BSWAP, MVT::v8i32, 4 }, 2750 { ISD::BSWAP, MVT::v16i16, 4 }, 2751 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 2752 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 2753 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 2754 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2755 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 2756 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 2757 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 2758 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 2759 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 2760 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 2761 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 2762 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2763 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2764 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2765 { ISD::SMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2766 { ISD::SMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2767 { ISD::SMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2768 { ISD::SMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2769 { ISD::SMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2770 { ISD::SMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2771 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2772 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2773 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2774 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2775 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 2776 { ISD::UMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2777 { ISD::UMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2778 { ISD::UMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2779 { ISD::UMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2780 { ISD::UMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2781 { ISD::UMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2782 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2783 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2784 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 2785 { ISD::FMAXNUM, MVT::f32, 3 }, // MAXSS + CMPUNORDSS + BLENDVPS 2786 { ISD::FMAXNUM, MVT::v4f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2787 { ISD::FMAXNUM, MVT::v8f32, 5 }, // MAXPS + CMPUNORDPS + BLENDVPS + ? 2788 { ISD::FMAXNUM, MVT::f64, 3 }, // MAXSD + CMPUNORDSD + BLENDVPD 2789 { ISD::FMAXNUM, MVT::v2f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2790 { ISD::FMAXNUM, MVT::v4f64, 5 }, // MAXPD + CMPUNORDPD + BLENDVPD + ? 2791 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 2792 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 2793 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 2794 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 2795 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 2796 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 2797 }; 2798 static const CostTblEntry GLMCostTbl[] = { 2799 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 2800 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 2801 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 2802 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 2803 }; 2804 static const CostTblEntry SLMCostTbl[] = { 2805 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 2806 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 2807 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 2808 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 2809 }; 2810 static const CostTblEntry SSE42CostTbl[] = { 2811 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 2812 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 2813 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 2814 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 2815 }; 2816 static const CostTblEntry SSE41CostTbl[] = { 2817 { ISD::ABS, MVT::v2i64, 2 }, // BLENDVPD(X,PSUBQ(0,X),X) 2818 { ISD::SMAX, MVT::v4i32, 1 }, 2819 { ISD::SMAX, MVT::v16i8, 1 }, 2820 { ISD::SMIN, MVT::v4i32, 1 }, 2821 { ISD::SMIN, MVT::v16i8, 1 }, 2822 { ISD::UMAX, MVT::v4i32, 1 }, 2823 { ISD::UMAX, MVT::v8i16, 1 }, 2824 { ISD::UMIN, MVT::v4i32, 1 }, 2825 { ISD::UMIN, MVT::v8i16, 1 }, 2826 }; 2827 static const CostTblEntry SSSE3CostTbl[] = { 2828 { ISD::ABS, MVT::v4i32, 1 }, 2829 { ISD::ABS, MVT::v8i16, 1 }, 2830 { ISD::ABS, MVT::v16i8, 1 }, 2831 { ISD::BITREVERSE, MVT::v2i64, 5 }, 2832 { ISD::BITREVERSE, MVT::v4i32, 5 }, 2833 { ISD::BITREVERSE, MVT::v8i16, 5 }, 2834 { ISD::BITREVERSE, MVT::v16i8, 5 }, 2835 { ISD::BSWAP, MVT::v2i64, 1 }, 2836 { ISD::BSWAP, MVT::v4i32, 1 }, 2837 { ISD::BSWAP, MVT::v8i16, 1 }, 2838 { ISD::CTLZ, MVT::v2i64, 23 }, 2839 { ISD::CTLZ, MVT::v4i32, 18 }, 2840 { ISD::CTLZ, MVT::v8i16, 14 }, 2841 { ISD::CTLZ, MVT::v16i8, 9 }, 2842 { ISD::CTPOP, MVT::v2i64, 7 }, 2843 { ISD::CTPOP, MVT::v4i32, 11 }, 2844 { ISD::CTPOP, MVT::v8i16, 9 }, 2845 { ISD::CTPOP, MVT::v16i8, 6 }, 2846 { ISD::CTTZ, MVT::v2i64, 10 }, 2847 { ISD::CTTZ, MVT::v4i32, 14 }, 2848 { ISD::CTTZ, MVT::v8i16, 12 }, 2849 { ISD::CTTZ, MVT::v16i8, 9 } 2850 }; 2851 static const CostTblEntry SSE2CostTbl[] = { 2852 { ISD::ABS, MVT::v2i64, 4 }, 2853 { ISD::ABS, MVT::v4i32, 3 }, 2854 { ISD::ABS, MVT::v8i16, 2 }, 2855 { ISD::ABS, MVT::v16i8, 2 }, 2856 { ISD::BITREVERSE, MVT::v2i64, 29 }, 2857 { ISD::BITREVERSE, MVT::v4i32, 27 }, 2858 { ISD::BITREVERSE, MVT::v8i16, 27 }, 2859 { ISD::BITREVERSE, MVT::v16i8, 20 }, 2860 { ISD::BSWAP, MVT::v2i64, 7 }, 2861 { ISD::BSWAP, MVT::v4i32, 7 }, 2862 { ISD::BSWAP, MVT::v8i16, 7 }, 2863 { ISD::CTLZ, MVT::v2i64, 25 }, 2864 { ISD::CTLZ, MVT::v4i32, 26 }, 2865 { ISD::CTLZ, MVT::v8i16, 20 }, 2866 { ISD::CTLZ, MVT::v16i8, 17 }, 2867 { ISD::CTPOP, MVT::v2i64, 12 }, 2868 { ISD::CTPOP, MVT::v4i32, 15 }, 2869 { ISD::CTPOP, MVT::v8i16, 13 }, 2870 { ISD::CTPOP, MVT::v16i8, 10 }, 2871 { ISD::CTTZ, MVT::v2i64, 14 }, 2872 { ISD::CTTZ, MVT::v4i32, 18 }, 2873 { ISD::CTTZ, MVT::v8i16, 16 }, 2874 { ISD::CTTZ, MVT::v16i8, 13 }, 2875 { ISD::SADDSAT, MVT::v8i16, 1 }, 2876 { ISD::SADDSAT, MVT::v16i8, 1 }, 2877 { ISD::SMAX, MVT::v8i16, 1 }, 2878 { ISD::SMIN, MVT::v8i16, 1 }, 2879 { ISD::SSUBSAT, MVT::v8i16, 1 }, 2880 { ISD::SSUBSAT, MVT::v16i8, 1 }, 2881 { ISD::UADDSAT, MVT::v8i16, 1 }, 2882 { ISD::UADDSAT, MVT::v16i8, 1 }, 2883 { ISD::UMAX, MVT::v8i16, 2 }, 2884 { ISD::UMAX, MVT::v16i8, 1 }, 2885 { ISD::UMIN, MVT::v8i16, 2 }, 2886 { ISD::UMIN, MVT::v16i8, 1 }, 2887 { ISD::USUBSAT, MVT::v8i16, 1 }, 2888 { ISD::USUBSAT, MVT::v16i8, 1 }, 2889 { ISD::FMAXNUM, MVT::f64, 4 }, 2890 { ISD::FMAXNUM, MVT::v2f64, 4 }, 2891 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 2892 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 2893 }; 2894 static const CostTblEntry SSE1CostTbl[] = { 2895 { ISD::FMAXNUM, MVT::f32, 4 }, 2896 { ISD::FMAXNUM, MVT::v4f32, 4 }, 2897 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 2898 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 2899 }; 2900 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 2901 { ISD::CTTZ, MVT::i64, 1 }, 2902 }; 2903 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 2904 { ISD::CTTZ, MVT::i32, 1 }, 2905 { ISD::CTTZ, MVT::i16, 1 }, 2906 { ISD::CTTZ, MVT::i8, 1 }, 2907 }; 2908 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 2909 { ISD::CTLZ, MVT::i64, 1 }, 2910 }; 2911 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 2912 { ISD::CTLZ, MVT::i32, 1 }, 2913 { ISD::CTLZ, MVT::i16, 1 }, 2914 { ISD::CTLZ, MVT::i8, 1 }, 2915 }; 2916 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 2917 { ISD::CTPOP, MVT::i64, 1 }, 2918 }; 2919 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 2920 { ISD::CTPOP, MVT::i32, 1 }, 2921 { ISD::CTPOP, MVT::i16, 1 }, 2922 { ISD::CTPOP, MVT::i8, 1 }, 2923 }; 2924 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2925 { ISD::ABS, MVT::i64, 2 }, // SUB+CMOV 2926 { ISD::BITREVERSE, MVT::i64, 14 }, 2927 { ISD::BSWAP, MVT::i64, 1 }, 2928 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 2929 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 2930 { ISD::CTPOP, MVT::i64, 10 }, 2931 { ISD::SADDO, MVT::i64, 1 }, 2932 { ISD::UADDO, MVT::i64, 1 }, 2933 { ISD::UMULO, MVT::i64, 2 }, // mulq + seto 2934 }; 2935 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2936 { ISD::ABS, MVT::i32, 2 }, // SUB+CMOV 2937 { ISD::ABS, MVT::i16, 2 }, // SUB+CMOV 2938 { ISD::BITREVERSE, MVT::i32, 14 }, 2939 { ISD::BITREVERSE, MVT::i16, 14 }, 2940 { ISD::BITREVERSE, MVT::i8, 11 }, 2941 { ISD::BSWAP, MVT::i32, 1 }, 2942 { ISD::BSWAP, MVT::i16, 1 }, // ROL 2943 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 2944 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 2945 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 2946 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 2947 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 2948 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 2949 { ISD::CTPOP, MVT::i32, 8 }, 2950 { ISD::CTPOP, MVT::i16, 9 }, 2951 { ISD::CTPOP, MVT::i8, 7 }, 2952 { ISD::SADDO, MVT::i32, 1 }, 2953 { ISD::SADDO, MVT::i16, 1 }, 2954 { ISD::SADDO, MVT::i8, 1 }, 2955 { ISD::UADDO, MVT::i32, 1 }, 2956 { ISD::UADDO, MVT::i16, 1 }, 2957 { ISD::UADDO, MVT::i8, 1 }, 2958 { ISD::UMULO, MVT::i32, 2 }, // mul + seto 2959 { ISD::UMULO, MVT::i16, 2 }, 2960 { ISD::UMULO, MVT::i8, 2 }, 2961 }; 2962 2963 Type *RetTy = ICA.getReturnType(); 2964 Type *OpTy = RetTy; 2965 Intrinsic::ID IID = ICA.getID(); 2966 unsigned ISD = ISD::DELETED_NODE; 2967 switch (IID) { 2968 default: 2969 break; 2970 case Intrinsic::abs: 2971 ISD = ISD::ABS; 2972 break; 2973 case Intrinsic::bitreverse: 2974 ISD = ISD::BITREVERSE; 2975 break; 2976 case Intrinsic::bswap: 2977 ISD = ISD::BSWAP; 2978 break; 2979 case Intrinsic::ctlz: 2980 ISD = ISD::CTLZ; 2981 break; 2982 case Intrinsic::ctpop: 2983 ISD = ISD::CTPOP; 2984 break; 2985 case Intrinsic::cttz: 2986 ISD = ISD::CTTZ; 2987 break; 2988 case Intrinsic::maxnum: 2989 case Intrinsic::minnum: 2990 // FMINNUM has same costs so don't duplicate. 2991 ISD = ISD::FMAXNUM; 2992 break; 2993 case Intrinsic::sadd_sat: 2994 ISD = ISD::SADDSAT; 2995 break; 2996 case Intrinsic::smax: 2997 ISD = ISD::SMAX; 2998 break; 2999 case Intrinsic::smin: 3000 ISD = ISD::SMIN; 3001 break; 3002 case Intrinsic::ssub_sat: 3003 ISD = ISD::SSUBSAT; 3004 break; 3005 case Intrinsic::uadd_sat: 3006 ISD = ISD::UADDSAT; 3007 break; 3008 case Intrinsic::umax: 3009 ISD = ISD::UMAX; 3010 break; 3011 case Intrinsic::umin: 3012 ISD = ISD::UMIN; 3013 break; 3014 case Intrinsic::usub_sat: 3015 ISD = ISD::USUBSAT; 3016 break; 3017 case Intrinsic::sqrt: 3018 ISD = ISD::FSQRT; 3019 break; 3020 case Intrinsic::sadd_with_overflow: 3021 case Intrinsic::ssub_with_overflow: 3022 // SSUBO has same costs so don't duplicate. 3023 ISD = ISD::SADDO; 3024 OpTy = RetTy->getContainedType(0); 3025 break; 3026 case Intrinsic::uadd_with_overflow: 3027 case Intrinsic::usub_with_overflow: 3028 // USUBO has same costs so don't duplicate. 3029 ISD = ISD::UADDO; 3030 OpTy = RetTy->getContainedType(0); 3031 break; 3032 case Intrinsic::umul_with_overflow: 3033 case Intrinsic::smul_with_overflow: 3034 // SMULO has same costs so don't duplicate. 3035 ISD = ISD::UMULO; 3036 OpTy = RetTy->getContainedType(0); 3037 break; 3038 } 3039 3040 if (ISD != ISD::DELETED_NODE) { 3041 // Legalize the type. 3042 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 3043 MVT MTy = LT.second; 3044 3045 // Attempt to lookup cost. 3046 if (ISD == ISD::BITREVERSE && ST->hasGFNI() && ST->hasSSSE3() && 3047 MTy.isVector()) { 3048 // With PSHUFB the code is very similar for all types. If we have integer 3049 // byte operations, we just need a GF2P8AFFINEQB for vXi8. For other types 3050 // we also need a PSHUFB. 3051 unsigned Cost = MTy.getVectorElementType() == MVT::i8 ? 1 : 2; 3052 3053 // Without byte operations, we need twice as many GF2P8AFFINEQB and PSHUFB 3054 // instructions. We also need an extract and an insert. 3055 if (!(MTy.is128BitVector() || (ST->hasAVX2() && MTy.is256BitVector()) || 3056 (ST->hasBWI() && MTy.is512BitVector()))) 3057 Cost = Cost * 2 + 2; 3058 3059 return LT.first * Cost; 3060 } 3061 3062 auto adjustTableCost = [](const CostTblEntry &Entry, 3063 InstructionCost LegalizationCost, 3064 FastMathFlags FMF) { 3065 // If there are no NANs to deal with, then these are reduced to a 3066 // single MIN** or MAX** instruction instead of the MIN/CMP/SELECT that we 3067 // assume is used in the non-fast case. 3068 if (Entry.ISD == ISD::FMAXNUM || Entry.ISD == ISD::FMINNUM) { 3069 if (FMF.noNaNs()) 3070 return LegalizationCost * 1; 3071 } 3072 return LegalizationCost * (int)Entry.Cost; 3073 }; 3074 3075 if (ST->useGLMDivSqrtCosts()) 3076 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 3077 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3078 3079 if (ST->isSLM()) 3080 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 3081 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3082 3083 if (ST->hasCDI()) 3084 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 3085 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3086 3087 if (ST->hasBWI()) 3088 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3089 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3090 3091 if (ST->hasAVX512()) 3092 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3093 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3094 3095 if (ST->hasXOP()) 3096 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3097 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3098 3099 if (ST->hasAVX2()) 3100 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3101 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3102 3103 if (ST->hasAVX()) 3104 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3105 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3106 3107 if (ST->hasSSE42()) 3108 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3109 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3110 3111 if (ST->hasSSE41()) 3112 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3113 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3114 3115 if (ST->hasSSSE3()) 3116 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 3117 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3118 3119 if (ST->hasSSE2()) 3120 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3121 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3122 3123 if (ST->hasSSE1()) 3124 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3125 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3126 3127 if (ST->hasBMI()) { 3128 if (ST->is64Bit()) 3129 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 3130 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3131 3132 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 3133 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3134 } 3135 3136 if (ST->hasLZCNT()) { 3137 if (ST->is64Bit()) 3138 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 3139 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3140 3141 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 3142 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3143 } 3144 3145 if (ST->hasPOPCNT()) { 3146 if (ST->is64Bit()) 3147 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 3148 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3149 3150 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 3151 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3152 } 3153 3154 if (ISD == ISD::BSWAP && ST->hasMOVBE() && ST->hasFastMOVBE()) { 3155 if (const Instruction *II = ICA.getInst()) { 3156 if (II->hasOneUse() && isa<StoreInst>(II->user_back())) 3157 return TTI::TCC_Free; 3158 if (auto *LI = dyn_cast<LoadInst>(II->getOperand(0))) { 3159 if (LI->hasOneUse()) 3160 return TTI::TCC_Free; 3161 } 3162 } 3163 } 3164 3165 // TODO - add BMI (TZCNT) scalar handling 3166 3167 if (ST->is64Bit()) 3168 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3169 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3170 3171 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3172 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3173 } 3174 3175 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3176 } 3177 3178 InstructionCost 3179 X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 3180 TTI::TargetCostKind CostKind) { 3181 if (ICA.isTypeBasedOnly()) 3182 return getTypeBasedIntrinsicInstrCost(ICA, CostKind); 3183 3184 static const CostTblEntry AVX512CostTbl[] = { 3185 { ISD::ROTL, MVT::v8i64, 1 }, 3186 { ISD::ROTL, MVT::v4i64, 1 }, 3187 { ISD::ROTL, MVT::v2i64, 1 }, 3188 { ISD::ROTL, MVT::v16i32, 1 }, 3189 { ISD::ROTL, MVT::v8i32, 1 }, 3190 { ISD::ROTL, MVT::v4i32, 1 }, 3191 { ISD::ROTR, MVT::v8i64, 1 }, 3192 { ISD::ROTR, MVT::v4i64, 1 }, 3193 { ISD::ROTR, MVT::v2i64, 1 }, 3194 { ISD::ROTR, MVT::v16i32, 1 }, 3195 { ISD::ROTR, MVT::v8i32, 1 }, 3196 { ISD::ROTR, MVT::v4i32, 1 } 3197 }; 3198 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 3199 static const CostTblEntry XOPCostTbl[] = { 3200 { ISD::ROTL, MVT::v4i64, 4 }, 3201 { ISD::ROTL, MVT::v8i32, 4 }, 3202 { ISD::ROTL, MVT::v16i16, 4 }, 3203 { ISD::ROTL, MVT::v32i8, 4 }, 3204 { ISD::ROTL, MVT::v2i64, 1 }, 3205 { ISD::ROTL, MVT::v4i32, 1 }, 3206 { ISD::ROTL, MVT::v8i16, 1 }, 3207 { ISD::ROTL, MVT::v16i8, 1 }, 3208 { ISD::ROTR, MVT::v4i64, 6 }, 3209 { ISD::ROTR, MVT::v8i32, 6 }, 3210 { ISD::ROTR, MVT::v16i16, 6 }, 3211 { ISD::ROTR, MVT::v32i8, 6 }, 3212 { ISD::ROTR, MVT::v2i64, 2 }, 3213 { ISD::ROTR, MVT::v4i32, 2 }, 3214 { ISD::ROTR, MVT::v8i16, 2 }, 3215 { ISD::ROTR, MVT::v16i8, 2 } 3216 }; 3217 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 3218 { ISD::ROTL, MVT::i64, 1 }, 3219 { ISD::ROTR, MVT::i64, 1 }, 3220 { ISD::FSHL, MVT::i64, 4 } 3221 }; 3222 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 3223 { ISD::ROTL, MVT::i32, 1 }, 3224 { ISD::ROTL, MVT::i16, 1 }, 3225 { ISD::ROTL, MVT::i8, 1 }, 3226 { ISD::ROTR, MVT::i32, 1 }, 3227 { ISD::ROTR, MVT::i16, 1 }, 3228 { ISD::ROTR, MVT::i8, 1 }, 3229 { ISD::FSHL, MVT::i32, 4 }, 3230 { ISD::FSHL, MVT::i16, 4 }, 3231 { ISD::FSHL, MVT::i8, 4 } 3232 }; 3233 3234 Intrinsic::ID IID = ICA.getID(); 3235 Type *RetTy = ICA.getReturnType(); 3236 const SmallVectorImpl<const Value *> &Args = ICA.getArgs(); 3237 unsigned ISD = ISD::DELETED_NODE; 3238 switch (IID) { 3239 default: 3240 break; 3241 case Intrinsic::fshl: 3242 ISD = ISD::FSHL; 3243 if (Args[0] == Args[1]) 3244 ISD = ISD::ROTL; 3245 break; 3246 case Intrinsic::fshr: 3247 // FSHR has same costs so don't duplicate. 3248 ISD = ISD::FSHL; 3249 if (Args[0] == Args[1]) 3250 ISD = ISD::ROTR; 3251 break; 3252 } 3253 3254 if (ISD != ISD::DELETED_NODE) { 3255 // Legalize the type. 3256 std::pair<InstructionCost, MVT> LT = 3257 TLI->getTypeLegalizationCost(DL, RetTy); 3258 MVT MTy = LT.second; 3259 3260 // Attempt to lookup cost. 3261 if (ST->hasAVX512()) 3262 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3263 return LT.first * Entry->Cost; 3264 3265 if (ST->hasXOP()) 3266 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3267 return LT.first * Entry->Cost; 3268 3269 if (ST->is64Bit()) 3270 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3271 return LT.first * Entry->Cost; 3272 3273 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3274 return LT.first * Entry->Cost; 3275 } 3276 3277 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3278 } 3279 3280 InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, 3281 unsigned Index) { 3282 static const CostTblEntry SLMCostTbl[] = { 3283 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 3284 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 3285 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 3286 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 3287 }; 3288 3289 assert(Val->isVectorTy() && "This must be a vector type"); 3290 Type *ScalarType = Val->getScalarType(); 3291 int RegisterFileMoveCost = 0; 3292 3293 // Non-immediate extraction/insertion can be handled as a sequence of 3294 // aliased loads+stores via the stack. 3295 if (Index == -1U && (Opcode == Instruction::ExtractElement || 3296 Opcode == Instruction::InsertElement)) { 3297 // TODO: On some SSE41+ targets, we expand to cmp+splat+select patterns: 3298 // inselt N0, N1, N2 --> select (SplatN2 == {0,1,2...}) ? SplatN1 : N0. 3299 3300 // TODO: Move this to BasicTTIImpl.h? We'd need better gep + index handling. 3301 assert(isa<FixedVectorType>(Val) && "Fixed vector type expected"); 3302 Align VecAlign = DL.getPrefTypeAlign(Val); 3303 Align SclAlign = DL.getPrefTypeAlign(ScalarType); 3304 3305 // Extract - store vector to stack, load scalar. 3306 if (Opcode == Instruction::ExtractElement) { 3307 return getMemoryOpCost(Instruction::Store, Val, VecAlign, 0, 3308 TTI::TargetCostKind::TCK_RecipThroughput) + 3309 getMemoryOpCost(Instruction::Load, ScalarType, SclAlign, 0, 3310 TTI::TargetCostKind::TCK_RecipThroughput); 3311 } 3312 // Insert - store vector to stack, store scalar, load vector. 3313 if (Opcode == Instruction::InsertElement) { 3314 return getMemoryOpCost(Instruction::Store, Val, VecAlign, 0, 3315 TTI::TargetCostKind::TCK_RecipThroughput) + 3316 getMemoryOpCost(Instruction::Store, ScalarType, SclAlign, 0, 3317 TTI::TargetCostKind::TCK_RecipThroughput) + 3318 getMemoryOpCost(Instruction::Load, Val, VecAlign, 0, 3319 TTI::TargetCostKind::TCK_RecipThroughput); 3320 } 3321 } 3322 3323 if (Index != -1U && (Opcode == Instruction::ExtractElement || 3324 Opcode == Instruction::InsertElement)) { 3325 // Legalize the type. 3326 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 3327 3328 // This type is legalized to a scalar type. 3329 if (!LT.second.isVector()) 3330 return 0; 3331 3332 // The type may be split. Normalize the index to the new type. 3333 unsigned NumElts = LT.second.getVectorNumElements(); 3334 unsigned SubNumElts = NumElts; 3335 Index = Index % NumElts; 3336 3337 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 3338 // For inserts, we also need to insert the subvector back. 3339 if (LT.second.getSizeInBits() > 128) { 3340 assert((LT.second.getSizeInBits() % 128) == 0 && "Illegal vector"); 3341 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 3342 SubNumElts = NumElts / NumSubVecs; 3343 if (SubNumElts <= Index) { 3344 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 3345 Index %= SubNumElts; 3346 } 3347 } 3348 3349 if (Index == 0) { 3350 // Floating point scalars are already located in index #0. 3351 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 3352 // true for all. 3353 if (ScalarType->isFloatingPointTy()) 3354 return RegisterFileMoveCost; 3355 3356 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 3357 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 3358 return 1 + RegisterFileMoveCost; 3359 } 3360 3361 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3362 assert(ISD && "Unexpected vector opcode"); 3363 MVT MScalarTy = LT.second.getScalarType(); 3364 if (ST->isSLM()) 3365 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 3366 return Entry->Cost + RegisterFileMoveCost; 3367 3368 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 3369 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3370 (MScalarTy.isInteger() && ST->hasSSE41())) 3371 return 1 + RegisterFileMoveCost; 3372 3373 // Assume insertps is relatively cheap on all targets. 3374 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 3375 Opcode == Instruction::InsertElement) 3376 return 1 + RegisterFileMoveCost; 3377 3378 // For extractions we just need to shuffle the element to index 0, which 3379 // should be very cheap (assume cost = 1). For insertions we need to shuffle 3380 // the elements to its destination. In both cases we must handle the 3381 // subvector move(s). 3382 // If the vector type is already less than 128-bits then don't reduce it. 3383 // TODO: Under what circumstances should we shuffle using the full width? 3384 InstructionCost ShuffleCost = 1; 3385 if (Opcode == Instruction::InsertElement) { 3386 auto *SubTy = cast<VectorType>(Val); 3387 EVT VT = TLI->getValueType(DL, Val); 3388 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 3389 SubTy = FixedVectorType::get(ScalarType, SubNumElts); 3390 ShuffleCost = 3391 getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, None, 0, SubTy); 3392 } 3393 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 3394 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 3395 } 3396 3397 // Add to the base cost if we know that the extracted element of a vector is 3398 // destined to be moved to and used in the integer register file. 3399 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 3400 RegisterFileMoveCost += 1; 3401 3402 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 3403 } 3404 3405 InstructionCost X86TTIImpl::getScalarizationOverhead(VectorType *Ty, 3406 const APInt &DemandedElts, 3407 bool Insert, 3408 bool Extract) { 3409 InstructionCost Cost = 0; 3410 3411 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much 3412 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT. 3413 if (Insert) { 3414 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3415 MVT MScalarTy = LT.second.getScalarType(); 3416 3417 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3418 (MScalarTy.isInteger() && ST->hasSSE41()) || 3419 (MScalarTy == MVT::f32 && ST->hasSSE41())) { 3420 // For types we can insert directly, insertion into 128-bit sub vectors is 3421 // cheap, followed by a cheap chain of concatenations. 3422 if (LT.second.getSizeInBits() <= 128) { 3423 Cost += 3424 BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, false); 3425 } else { 3426 // In each 128-lane, if at least one index is demanded but not all 3427 // indices are demanded and this 128-lane is not the first 128-lane of 3428 // the legalized-vector, then this 128-lane needs a extracti128; If in 3429 // each 128-lane, there is at least one demanded index, this 128-lane 3430 // needs a inserti128. 3431 3432 // The following cases will help you build a better understanding: 3433 // Assume we insert several elements into a v8i32 vector in avx2, 3434 // Case#1: inserting into 1th index needs vpinsrd + inserti128. 3435 // Case#2: inserting into 5th index needs extracti128 + vpinsrd + 3436 // inserti128. 3437 // Case#3: inserting into 4,5,6,7 index needs 4*vpinsrd + inserti128. 3438 const int CostValue = *LT.first.getValue(); 3439 assert(CostValue >= 0 && "Negative cost!"); 3440 unsigned Num128Lanes = LT.second.getSizeInBits() / 128 * CostValue; 3441 unsigned NumElts = LT.second.getVectorNumElements() * CostValue; 3442 APInt WidenedDemandedElts = DemandedElts.zextOrSelf(NumElts); 3443 unsigned Scale = NumElts / Num128Lanes; 3444 // We iterate each 128-lane, and check if we need a 3445 // extracti128/inserti128 for this 128-lane. 3446 for (unsigned I = 0; I < NumElts; I += Scale) { 3447 APInt Mask = WidenedDemandedElts.getBitsSet(NumElts, I, I + Scale); 3448 APInt MaskedDE = Mask & WidenedDemandedElts; 3449 unsigned Population = MaskedDE.countPopulation(); 3450 Cost += (Population > 0 && Population != Scale && 3451 I % LT.second.getVectorNumElements() != 0); 3452 Cost += Population > 0; 3453 } 3454 Cost += DemandedElts.countPopulation(); 3455 3456 // For vXf32 cases, insertion into the 0'th index in each v4f32 3457 // 128-bit vector is free. 3458 // NOTE: This assumes legalization widens vXf32 vectors. 3459 if (MScalarTy == MVT::f32) 3460 for (unsigned i = 0, e = cast<FixedVectorType>(Ty)->getNumElements(); 3461 i < e; i += 4) 3462 if (DemandedElts[i]) 3463 Cost--; 3464 } 3465 } else if (LT.second.isVector()) { 3466 // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded 3467 // integer element as a SCALAR_TO_VECTOR, then we build the vector as a 3468 // series of UNPCK followed by CONCAT_VECTORS - all of these can be 3469 // considered cheap. 3470 if (Ty->isIntOrIntVectorTy()) 3471 Cost += DemandedElts.countPopulation(); 3472 3473 // Get the smaller of the legalized or original pow2-extended number of 3474 // vector elements, which represents the number of unpacks we'll end up 3475 // performing. 3476 unsigned NumElts = LT.second.getVectorNumElements(); 3477 unsigned Pow2Elts = 3478 PowerOf2Ceil(cast<FixedVectorType>(Ty)->getNumElements()); 3479 Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first; 3480 } 3481 } 3482 3483 // TODO: Use default extraction for now, but we should investigate extending this 3484 // to handle repeated subvector extraction. 3485 if (Extract) 3486 Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, false, Extract); 3487 3488 return Cost; 3489 } 3490 3491 InstructionCost X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 3492 MaybeAlign Alignment, 3493 unsigned AddressSpace, 3494 TTI::TargetCostKind CostKind, 3495 const Instruction *I) { 3496 // TODO: Handle other cost kinds. 3497 if (CostKind != TTI::TCK_RecipThroughput) { 3498 if (auto *SI = dyn_cast_or_null<StoreInst>(I)) { 3499 // Store instruction with index and scale costs 2 Uops. 3500 // Check the preceding GEP to identify non-const indices. 3501 if (auto *GEP = dyn_cast<GetElementPtrInst>(SI->getPointerOperand())) { 3502 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3503 return TTI::TCC_Basic * 2; 3504 } 3505 } 3506 return TTI::TCC_Basic; 3507 } 3508 3509 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 3510 "Invalid Opcode"); 3511 // Type legalization can't handle structs 3512 if (TLI->getValueType(DL, Src, true) == MVT::Other) 3513 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3514 CostKind); 3515 3516 // Legalize the type. 3517 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 3518 3519 auto *VTy = dyn_cast<FixedVectorType>(Src); 3520 3521 // Handle the simple case of non-vectors. 3522 // NOTE: this assumes that legalization never creates vector from scalars! 3523 if (!VTy || !LT.second.isVector()) 3524 // Each load/store unit costs 1. 3525 return LT.first * 1; 3526 3527 bool IsLoad = Opcode == Instruction::Load; 3528 3529 Type *EltTy = VTy->getElementType(); 3530 3531 const int EltTyBits = DL.getTypeSizeInBits(EltTy); 3532 3533 InstructionCost Cost = 0; 3534 3535 // Source of truth: how many elements were there in the original IR vector? 3536 const unsigned SrcNumElt = VTy->getNumElements(); 3537 3538 // How far have we gotten? 3539 int NumEltRemaining = SrcNumElt; 3540 // Note that we intentionally capture by-reference, NumEltRemaining changes. 3541 auto NumEltDone = [&]() { return SrcNumElt - NumEltRemaining; }; 3542 3543 const int MaxLegalOpSizeBytes = divideCeil(LT.second.getSizeInBits(), 8); 3544 3545 // Note that even if we can store 64 bits of an XMM, we still operate on XMM. 3546 const unsigned XMMBits = 128; 3547 if (XMMBits % EltTyBits != 0) 3548 // Vector size must be a multiple of the element size. I.e. no padding. 3549 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3550 CostKind); 3551 const int NumEltPerXMM = XMMBits / EltTyBits; 3552 3553 auto *XMMVecTy = FixedVectorType::get(EltTy, NumEltPerXMM); 3554 3555 for (int CurrOpSizeBytes = MaxLegalOpSizeBytes, SubVecEltsLeft = 0; 3556 NumEltRemaining > 0; CurrOpSizeBytes /= 2) { 3557 // How many elements would a single op deal with at once? 3558 if ((8 * CurrOpSizeBytes) % EltTyBits != 0) 3559 // Vector size must be a multiple of the element size. I.e. no padding. 3560 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3561 CostKind); 3562 int CurrNumEltPerOp = (8 * CurrOpSizeBytes) / EltTyBits; 3563 3564 assert(CurrOpSizeBytes > 0 && CurrNumEltPerOp > 0 && "How'd we get here?"); 3565 assert((((NumEltRemaining * EltTyBits) < (2 * 8 * CurrOpSizeBytes)) || 3566 (CurrOpSizeBytes == MaxLegalOpSizeBytes)) && 3567 "Unless we haven't halved the op size yet, " 3568 "we have less than two op's sized units of work left."); 3569 3570 auto *CurrVecTy = CurrNumEltPerOp > NumEltPerXMM 3571 ? FixedVectorType::get(EltTy, CurrNumEltPerOp) 3572 : XMMVecTy; 3573 3574 assert(CurrVecTy->getNumElements() % CurrNumEltPerOp == 0 && 3575 "After halving sizes, the vector elt count is no longer a multiple " 3576 "of number of elements per operation?"); 3577 auto *CoalescedVecTy = 3578 CurrNumEltPerOp == 1 3579 ? CurrVecTy 3580 : FixedVectorType::get( 3581 IntegerType::get(Src->getContext(), 3582 EltTyBits * CurrNumEltPerOp), 3583 CurrVecTy->getNumElements() / CurrNumEltPerOp); 3584 assert(DL.getTypeSizeInBits(CoalescedVecTy) == 3585 DL.getTypeSizeInBits(CurrVecTy) && 3586 "coalesciing elements doesn't change vector width."); 3587 3588 while (NumEltRemaining > 0) { 3589 assert(SubVecEltsLeft >= 0 && "Subreg element count overconsumtion?"); 3590 3591 // Can we use this vector size, as per the remaining element count? 3592 // Iff the vector is naturally aligned, we can do a wide load regardless. 3593 if (NumEltRemaining < CurrNumEltPerOp && 3594 (!IsLoad || Alignment.valueOrOne() < CurrOpSizeBytes) && 3595 CurrOpSizeBytes != 1) 3596 break; // Try smalled vector size. 3597 3598 bool Is0thSubVec = (NumEltDone() % LT.second.getVectorNumElements()) == 0; 3599 3600 // If we have fully processed the previous reg, we need to replenish it. 3601 if (SubVecEltsLeft == 0) { 3602 SubVecEltsLeft += CurrVecTy->getNumElements(); 3603 // And that's free only for the 0'th subvector of a legalized vector. 3604 if (!Is0thSubVec) 3605 Cost += getShuffleCost(IsLoad ? TTI::ShuffleKind::SK_InsertSubvector 3606 : TTI::ShuffleKind::SK_ExtractSubvector, 3607 VTy, None, NumEltDone(), CurrVecTy); 3608 } 3609 3610 // While we can directly load/store ZMM, YMM, and 64-bit halves of XMM, 3611 // for smaller widths (32/16/8) we have to insert/extract them separately. 3612 // Again, it's free for the 0'th subreg (if op is 32/64 bit wide, 3613 // but let's pretend that it is also true for 16/8 bit wide ops...) 3614 if (CurrOpSizeBytes <= 32 / 8 && !Is0thSubVec) { 3615 int NumEltDoneInCurrXMM = NumEltDone() % NumEltPerXMM; 3616 assert(NumEltDoneInCurrXMM % CurrNumEltPerOp == 0 && ""); 3617 int CoalescedVecEltIdx = NumEltDoneInCurrXMM / CurrNumEltPerOp; 3618 APInt DemandedElts = 3619 APInt::getBitsSet(CoalescedVecTy->getNumElements(), 3620 CoalescedVecEltIdx, CoalescedVecEltIdx + 1); 3621 assert(DemandedElts.countPopulation() == 1 && "Inserting single value"); 3622 Cost += getScalarizationOverhead(CoalescedVecTy, DemandedElts, IsLoad, 3623 !IsLoad); 3624 } 3625 3626 // This isn't exactly right. We're using slow unaligned 32-byte accesses 3627 // as a proxy for a double-pumped AVX memory interface such as on 3628 // Sandybridge. 3629 if (CurrOpSizeBytes == 32 && ST->isUnalignedMem32Slow()) 3630 Cost += 2; 3631 else 3632 Cost += 1; 3633 3634 SubVecEltsLeft -= CurrNumEltPerOp; 3635 NumEltRemaining -= CurrNumEltPerOp; 3636 Alignment = commonAlignment(Alignment.valueOrOne(), CurrOpSizeBytes); 3637 } 3638 } 3639 3640 assert(NumEltRemaining <= 0 && "Should have processed all the elements."); 3641 3642 return Cost; 3643 } 3644 3645 InstructionCost 3646 X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, Align Alignment, 3647 unsigned AddressSpace, 3648 TTI::TargetCostKind CostKind) { 3649 bool IsLoad = (Instruction::Load == Opcode); 3650 bool IsStore = (Instruction::Store == Opcode); 3651 3652 auto *SrcVTy = dyn_cast<FixedVectorType>(SrcTy); 3653 if (!SrcVTy) 3654 // To calculate scalar take the regular cost, without mask 3655 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace, CostKind); 3656 3657 unsigned NumElem = SrcVTy->getNumElements(); 3658 auto *MaskTy = 3659 FixedVectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 3660 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, Alignment)) || 3661 (IsStore && !isLegalMaskedStore(SrcVTy, Alignment))) { 3662 // Scalarization 3663 APInt DemandedElts = APInt::getAllOnesValue(NumElem); 3664 InstructionCost MaskSplitCost = 3665 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 3666 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 3667 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr, 3668 CmpInst::BAD_ICMP_PREDICATE, CostKind); 3669 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 3670 InstructionCost MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 3671 InstructionCost ValueSplitCost = 3672 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore); 3673 InstructionCost MemopCost = 3674 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3675 Alignment, AddressSpace, CostKind); 3676 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 3677 } 3678 3679 // Legalize the type. 3680 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3681 auto VT = TLI->getValueType(DL, SrcVTy); 3682 InstructionCost Cost = 0; 3683 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 3684 LT.second.getVectorNumElements() == NumElem) 3685 // Promotion requires extend/truncate for data and a shuffle for mask. 3686 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, None, 0, nullptr) + 3687 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, None, 0, nullptr); 3688 3689 else if (LT.first * LT.second.getVectorNumElements() > NumElem) { 3690 auto *NewMaskTy = FixedVectorType::get(MaskTy->getElementType(), 3691 LT.second.getVectorNumElements()); 3692 // Expanding requires fill mask with zeroes 3693 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, None, 0, MaskTy); 3694 } 3695 3696 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 3697 if (!ST->hasAVX512()) 3698 return Cost + LT.first * (IsLoad ? 2 : 8); 3699 3700 // AVX-512 masked load/store is cheapper 3701 return Cost + LT.first; 3702 } 3703 3704 InstructionCost X86TTIImpl::getAddressComputationCost(Type *Ty, 3705 ScalarEvolution *SE, 3706 const SCEV *Ptr) { 3707 // Address computations in vectorized code with non-consecutive addresses will 3708 // likely result in more instructions compared to scalar code where the 3709 // computation can more often be merged into the index mode. The resulting 3710 // extra micro-ops can significantly decrease throughput. 3711 const unsigned NumVectorInstToHideOverhead = 10; 3712 3713 // Cost modeling of Strided Access Computation is hidden by the indexing 3714 // modes of X86 regardless of the stride value. We dont believe that there 3715 // is a difference between constant strided access in gerenal and constant 3716 // strided value which is less than or equal to 64. 3717 // Even in the case of (loop invariant) stride whose value is not known at 3718 // compile time, the address computation will not incur more than one extra 3719 // ADD instruction. 3720 if (Ty->isVectorTy() && SE) { 3721 if (!BaseT::isStridedAccess(Ptr)) 3722 return NumVectorInstToHideOverhead; 3723 if (!BaseT::getConstantStrideStep(SE, Ptr)) 3724 return 1; 3725 } 3726 3727 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 3728 } 3729 3730 InstructionCost 3731 X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 3732 bool IsPairwise, 3733 TTI::TargetCostKind CostKind) { 3734 // Just use the default implementation for pair reductions. 3735 if (IsPairwise) 3736 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise, CostKind); 3737 3738 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3739 // and make it as the cost. 3740 3741 static const CostTblEntry SLMCostTblNoPairWise[] = { 3742 { ISD::FADD, MVT::v2f64, 3 }, 3743 { ISD::ADD, MVT::v2i64, 5 }, 3744 }; 3745 3746 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3747 { ISD::FADD, MVT::v2f64, 2 }, 3748 { ISD::FADD, MVT::v2f32, 2 }, 3749 { ISD::FADD, MVT::v4f32, 4 }, 3750 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 3751 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 3752 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 3753 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 3754 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 3755 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 3756 { ISD::ADD, MVT::v2i8, 2 }, 3757 { ISD::ADD, MVT::v4i8, 2 }, 3758 { ISD::ADD, MVT::v8i8, 2 }, 3759 { ISD::ADD, MVT::v16i8, 3 }, 3760 }; 3761 3762 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3763 { ISD::FADD, MVT::v4f64, 3 }, 3764 { ISD::FADD, MVT::v4f32, 3 }, 3765 { ISD::FADD, MVT::v8f32, 4 }, 3766 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 3767 { ISD::ADD, MVT::v4i64, 3 }, 3768 { ISD::ADD, MVT::v8i32, 5 }, 3769 { ISD::ADD, MVT::v16i16, 5 }, 3770 { ISD::ADD, MVT::v32i8, 4 }, 3771 }; 3772 3773 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3774 assert(ISD && "Invalid opcode"); 3775 3776 // Before legalizing the type, give a chance to look up illegal narrow types 3777 // in the table. 3778 // FIXME: Is there a better way to do this? 3779 EVT VT = TLI->getValueType(DL, ValTy); 3780 if (VT.isSimple()) { 3781 MVT MTy = VT.getSimpleVT(); 3782 if (ST->isSLM()) 3783 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3784 return Entry->Cost; 3785 3786 if (ST->hasAVX()) 3787 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3788 return Entry->Cost; 3789 3790 if (ST->hasSSE2()) 3791 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3792 return Entry->Cost; 3793 } 3794 3795 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3796 3797 MVT MTy = LT.second; 3798 3799 auto *ValVTy = cast<FixedVectorType>(ValTy); 3800 3801 // Special case: vXi8 mul reductions are performed as vXi16. 3802 if (ISD == ISD::MUL && MTy.getScalarType() == MVT::i8) { 3803 auto *WideSclTy = IntegerType::get(ValVTy->getContext(), 16); 3804 auto *WideVecTy = FixedVectorType::get(WideSclTy, ValVTy->getNumElements()); 3805 return getCastInstrCost(Instruction::ZExt, WideVecTy, ValTy, 3806 TargetTransformInfo::CastContextHint::None, 3807 CostKind) + 3808 getArithmeticReductionCost(Opcode, WideVecTy, IsPairwise, CostKind); 3809 } 3810 3811 InstructionCost ArithmeticCost = 0; 3812 if (LT.first != 1 && MTy.isVector() && 3813 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3814 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3815 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3816 MTy.getVectorNumElements()); 3817 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3818 ArithmeticCost *= LT.first - 1; 3819 } 3820 3821 if (ST->isSLM()) 3822 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3823 return ArithmeticCost + Entry->Cost; 3824 3825 if (ST->hasAVX()) 3826 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3827 return ArithmeticCost + Entry->Cost; 3828 3829 if (ST->hasSSE2()) 3830 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3831 return ArithmeticCost + Entry->Cost; 3832 3833 // FIXME: These assume a naive kshift+binop lowering, which is probably 3834 // conservative in most cases. 3835 static const CostTblEntry AVX512BoolReduction[] = { 3836 { ISD::AND, MVT::v2i1, 3 }, 3837 { ISD::AND, MVT::v4i1, 5 }, 3838 { ISD::AND, MVT::v8i1, 7 }, 3839 { ISD::AND, MVT::v16i1, 9 }, 3840 { ISD::AND, MVT::v32i1, 11 }, 3841 { ISD::AND, MVT::v64i1, 13 }, 3842 { ISD::OR, MVT::v2i1, 3 }, 3843 { ISD::OR, MVT::v4i1, 5 }, 3844 { ISD::OR, MVT::v8i1, 7 }, 3845 { ISD::OR, MVT::v16i1, 9 }, 3846 { ISD::OR, MVT::v32i1, 11 }, 3847 { ISD::OR, MVT::v64i1, 13 }, 3848 }; 3849 3850 static const CostTblEntry AVX2BoolReduction[] = { 3851 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 3852 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 3853 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 3854 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 3855 }; 3856 3857 static const CostTblEntry AVX1BoolReduction[] = { 3858 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 3859 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 3860 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3861 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3862 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 3863 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 3864 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3865 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3866 }; 3867 3868 static const CostTblEntry SSE2BoolReduction[] = { 3869 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 3870 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 3871 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 3872 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 3873 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 3874 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 3875 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 3876 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 3877 }; 3878 3879 // Handle bool allof/anyof patterns. 3880 if (ValVTy->getElementType()->isIntegerTy(1)) { 3881 InstructionCost ArithmeticCost = 0; 3882 if (LT.first != 1 && MTy.isVector() && 3883 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3884 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3885 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3886 MTy.getVectorNumElements()); 3887 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3888 ArithmeticCost *= LT.first - 1; 3889 } 3890 3891 if (ST->hasAVX512()) 3892 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 3893 return ArithmeticCost + Entry->Cost; 3894 if (ST->hasAVX2()) 3895 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 3896 return ArithmeticCost + Entry->Cost; 3897 if (ST->hasAVX()) 3898 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 3899 return ArithmeticCost + Entry->Cost; 3900 if (ST->hasSSE2()) 3901 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 3902 return ArithmeticCost + Entry->Cost; 3903 3904 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise, 3905 CostKind); 3906 } 3907 3908 unsigned NumVecElts = ValVTy->getNumElements(); 3909 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 3910 3911 // Special case power of 2 reductions where the scalar type isn't changed 3912 // by type legalization. 3913 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 3914 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise, 3915 CostKind); 3916 3917 InstructionCost ReductionCost = 0; 3918 3919 auto *Ty = ValVTy; 3920 if (LT.first != 1 && MTy.isVector() && 3921 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3922 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3923 Ty = FixedVectorType::get(ValVTy->getElementType(), 3924 MTy.getVectorNumElements()); 3925 ReductionCost = getArithmeticInstrCost(Opcode, Ty, CostKind); 3926 ReductionCost *= LT.first - 1; 3927 NumVecElts = MTy.getVectorNumElements(); 3928 } 3929 3930 // Now handle reduction with the legal type, taking into account size changes 3931 // at each level. 3932 while (NumVecElts > 1) { 3933 // Determine the size of the remaining vector we need to reduce. 3934 unsigned Size = NumVecElts * ScalarSize; 3935 NumVecElts /= 2; 3936 // If we're reducing from 256/512 bits, use an extract_subvector. 3937 if (Size > 128) { 3938 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 3939 ReductionCost += 3940 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 3941 Ty = SubTy; 3942 } else if (Size == 128) { 3943 // Reducing from 128 bits is a permute of v2f64/v2i64. 3944 FixedVectorType *ShufTy; 3945 if (ValVTy->isFloatingPointTy()) 3946 ShufTy = 3947 FixedVectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 3948 else 3949 ShufTy = 3950 FixedVectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 3951 ReductionCost += 3952 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3953 } else if (Size == 64) { 3954 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3955 FixedVectorType *ShufTy; 3956 if (ValVTy->isFloatingPointTy()) 3957 ShufTy = 3958 FixedVectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 3959 else 3960 ShufTy = 3961 FixedVectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 3962 ReductionCost += 3963 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3964 } else { 3965 // Reducing from smaller size is a shift by immediate. 3966 auto *ShiftTy = FixedVectorType::get( 3967 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 3968 ReductionCost += getArithmeticInstrCost( 3969 Instruction::LShr, ShiftTy, CostKind, 3970 TargetTransformInfo::OK_AnyValue, 3971 TargetTransformInfo::OK_UniformConstantValue, 3972 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3973 } 3974 3975 // Add the arithmetic op for this level. 3976 ReductionCost += getArithmeticInstrCost(Opcode, Ty, CostKind); 3977 } 3978 3979 // Add the final extract element to the cost. 3980 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3981 } 3982 3983 InstructionCost X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, 3984 bool IsUnsigned) { 3985 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3986 3987 MVT MTy = LT.second; 3988 3989 int ISD; 3990 if (Ty->isIntOrIntVectorTy()) { 3991 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3992 } else { 3993 assert(Ty->isFPOrFPVectorTy() && 3994 "Expected float point or integer vector type."); 3995 ISD = ISD::FMINNUM; 3996 } 3997 3998 static const CostTblEntry SSE1CostTbl[] = { 3999 {ISD::FMINNUM, MVT::v4f32, 1}, 4000 }; 4001 4002 static const CostTblEntry SSE2CostTbl[] = { 4003 {ISD::FMINNUM, MVT::v2f64, 1}, 4004 {ISD::SMIN, MVT::v8i16, 1}, 4005 {ISD::UMIN, MVT::v16i8, 1}, 4006 }; 4007 4008 static const CostTblEntry SSE41CostTbl[] = { 4009 {ISD::SMIN, MVT::v4i32, 1}, 4010 {ISD::UMIN, MVT::v4i32, 1}, 4011 {ISD::UMIN, MVT::v8i16, 1}, 4012 {ISD::SMIN, MVT::v16i8, 1}, 4013 }; 4014 4015 static const CostTblEntry SSE42CostTbl[] = { 4016 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 4017 }; 4018 4019 static const CostTblEntry AVX1CostTbl[] = { 4020 {ISD::FMINNUM, MVT::v8f32, 1}, 4021 {ISD::FMINNUM, MVT::v4f64, 1}, 4022 {ISD::SMIN, MVT::v8i32, 3}, 4023 {ISD::UMIN, MVT::v8i32, 3}, 4024 {ISD::SMIN, MVT::v16i16, 3}, 4025 {ISD::UMIN, MVT::v16i16, 3}, 4026 {ISD::SMIN, MVT::v32i8, 3}, 4027 {ISD::UMIN, MVT::v32i8, 3}, 4028 }; 4029 4030 static const CostTblEntry AVX2CostTbl[] = { 4031 {ISD::SMIN, MVT::v8i32, 1}, 4032 {ISD::UMIN, MVT::v8i32, 1}, 4033 {ISD::SMIN, MVT::v16i16, 1}, 4034 {ISD::UMIN, MVT::v16i16, 1}, 4035 {ISD::SMIN, MVT::v32i8, 1}, 4036 {ISD::UMIN, MVT::v32i8, 1}, 4037 }; 4038 4039 static const CostTblEntry AVX512CostTbl[] = { 4040 {ISD::FMINNUM, MVT::v16f32, 1}, 4041 {ISD::FMINNUM, MVT::v8f64, 1}, 4042 {ISD::SMIN, MVT::v2i64, 1}, 4043 {ISD::UMIN, MVT::v2i64, 1}, 4044 {ISD::SMIN, MVT::v4i64, 1}, 4045 {ISD::UMIN, MVT::v4i64, 1}, 4046 {ISD::SMIN, MVT::v8i64, 1}, 4047 {ISD::UMIN, MVT::v8i64, 1}, 4048 {ISD::SMIN, MVT::v16i32, 1}, 4049 {ISD::UMIN, MVT::v16i32, 1}, 4050 }; 4051 4052 static const CostTblEntry AVX512BWCostTbl[] = { 4053 {ISD::SMIN, MVT::v32i16, 1}, 4054 {ISD::UMIN, MVT::v32i16, 1}, 4055 {ISD::SMIN, MVT::v64i8, 1}, 4056 {ISD::UMIN, MVT::v64i8, 1}, 4057 }; 4058 4059 // If we have a native MIN/MAX instruction for this type, use it. 4060 if (ST->hasBWI()) 4061 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 4062 return LT.first * Entry->Cost; 4063 4064 if (ST->hasAVX512()) 4065 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 4066 return LT.first * Entry->Cost; 4067 4068 if (ST->hasAVX2()) 4069 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 4070 return LT.first * Entry->Cost; 4071 4072 if (ST->hasAVX()) 4073 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 4074 return LT.first * Entry->Cost; 4075 4076 if (ST->hasSSE42()) 4077 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 4078 return LT.first * Entry->Cost; 4079 4080 if (ST->hasSSE41()) 4081 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 4082 return LT.first * Entry->Cost; 4083 4084 if (ST->hasSSE2()) 4085 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 4086 return LT.first * Entry->Cost; 4087 4088 if (ST->hasSSE1()) 4089 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 4090 return LT.first * Entry->Cost; 4091 4092 unsigned CmpOpcode; 4093 if (Ty->isFPOrFPVectorTy()) { 4094 CmpOpcode = Instruction::FCmp; 4095 } else { 4096 assert(Ty->isIntOrIntVectorTy() && 4097 "expecting floating point or integer type for min/max reduction"); 4098 CmpOpcode = Instruction::ICmp; 4099 } 4100 4101 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4102 // Otherwise fall back to cmp+select. 4103 InstructionCost Result = 4104 getCmpSelInstrCost(CmpOpcode, Ty, CondTy, CmpInst::BAD_ICMP_PREDICATE, 4105 CostKind) + 4106 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, 4107 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4108 return Result; 4109 } 4110 4111 InstructionCost 4112 X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 4113 bool IsPairwise, bool IsUnsigned, 4114 TTI::TargetCostKind CostKind) { 4115 // Just use the default implementation for pair reductions. 4116 if (IsPairwise) 4117 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned, 4118 CostKind); 4119 4120 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 4121 4122 MVT MTy = LT.second; 4123 4124 int ISD; 4125 if (ValTy->isIntOrIntVectorTy()) { 4126 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 4127 } else { 4128 assert(ValTy->isFPOrFPVectorTy() && 4129 "Expected float point or integer vector type."); 4130 ISD = ISD::FMINNUM; 4131 } 4132 4133 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 4134 // and make it as the cost. 4135 4136 static const CostTblEntry SSE2CostTblNoPairWise[] = { 4137 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 4138 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 4139 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 4140 }; 4141 4142 static const CostTblEntry SSE41CostTblNoPairWise[] = { 4143 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 4144 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 4145 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 4146 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 4147 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 4148 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 4149 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 4150 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 4151 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 4152 {ISD::SMIN, MVT::v16i8, 6}, 4153 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 4154 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 4155 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 4156 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 4157 }; 4158 4159 static const CostTblEntry AVX1CostTblNoPairWise[] = { 4160 {ISD::SMIN, MVT::v16i16, 6}, 4161 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 4162 {ISD::SMIN, MVT::v32i8, 8}, 4163 {ISD::UMIN, MVT::v32i8, 8}, 4164 }; 4165 4166 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 4167 {ISD::SMIN, MVT::v32i16, 8}, 4168 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 4169 {ISD::SMIN, MVT::v64i8, 10}, 4170 {ISD::UMIN, MVT::v64i8, 10}, 4171 }; 4172 4173 // Before legalizing the type, give a chance to look up illegal narrow types 4174 // in the table. 4175 // FIXME: Is there a better way to do this? 4176 EVT VT = TLI->getValueType(DL, ValTy); 4177 if (VT.isSimple()) { 4178 MVT MTy = VT.getSimpleVT(); 4179 if (ST->hasBWI()) 4180 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4181 return Entry->Cost; 4182 4183 if (ST->hasAVX()) 4184 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4185 return Entry->Cost; 4186 4187 if (ST->hasSSE41()) 4188 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4189 return Entry->Cost; 4190 4191 if (ST->hasSSE2()) 4192 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4193 return Entry->Cost; 4194 } 4195 4196 auto *ValVTy = cast<FixedVectorType>(ValTy); 4197 unsigned NumVecElts = ValVTy->getNumElements(); 4198 4199 auto *Ty = ValVTy; 4200 InstructionCost MinMaxCost = 0; 4201 if (LT.first != 1 && MTy.isVector() && 4202 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4203 // Type needs to be split. We need LT.first - 1 operations ops. 4204 Ty = FixedVectorType::get(ValVTy->getElementType(), 4205 MTy.getVectorNumElements()); 4206 auto *SubCondTy = FixedVectorType::get(CondTy->getElementType(), 4207 MTy.getVectorNumElements()); 4208 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4209 MinMaxCost *= LT.first - 1; 4210 NumVecElts = MTy.getVectorNumElements(); 4211 } 4212 4213 if (ST->hasBWI()) 4214 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4215 return MinMaxCost + Entry->Cost; 4216 4217 if (ST->hasAVX()) 4218 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4219 return MinMaxCost + Entry->Cost; 4220 4221 if (ST->hasSSE41()) 4222 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4223 return MinMaxCost + Entry->Cost; 4224 4225 if (ST->hasSSE2()) 4226 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4227 return MinMaxCost + Entry->Cost; 4228 4229 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 4230 4231 // Special case power of 2 reductions where the scalar type isn't changed 4232 // by type legalization. 4233 if (!isPowerOf2_32(ValVTy->getNumElements()) || 4234 ScalarSize != MTy.getScalarSizeInBits()) 4235 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned, 4236 CostKind); 4237 4238 // Now handle reduction with the legal type, taking into account size changes 4239 // at each level. 4240 while (NumVecElts > 1) { 4241 // Determine the size of the remaining vector we need to reduce. 4242 unsigned Size = NumVecElts * ScalarSize; 4243 NumVecElts /= 2; 4244 // If we're reducing from 256/512 bits, use an extract_subvector. 4245 if (Size > 128) { 4246 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 4247 MinMaxCost += 4248 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 4249 Ty = SubTy; 4250 } else if (Size == 128) { 4251 // Reducing from 128 bits is a permute of v2f64/v2i64. 4252 VectorType *ShufTy; 4253 if (ValTy->isFloatingPointTy()) 4254 ShufTy = 4255 FixedVectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 4256 else 4257 ShufTy = FixedVectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 4258 MinMaxCost += 4259 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4260 } else if (Size == 64) { 4261 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 4262 FixedVectorType *ShufTy; 4263 if (ValTy->isFloatingPointTy()) 4264 ShufTy = FixedVectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 4265 else 4266 ShufTy = FixedVectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 4267 MinMaxCost += 4268 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4269 } else { 4270 // Reducing from smaller size is a shift by immediate. 4271 auto *ShiftTy = FixedVectorType::get( 4272 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 4273 MinMaxCost += getArithmeticInstrCost( 4274 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, 4275 TargetTransformInfo::OK_AnyValue, 4276 TargetTransformInfo::OK_UniformConstantValue, 4277 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 4278 } 4279 4280 // Add the arithmetic op for this level. 4281 auto *SubCondTy = 4282 FixedVectorType::get(CondTy->getElementType(), Ty->getNumElements()); 4283 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4284 } 4285 4286 // Add the final extract element to the cost. 4287 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 4288 } 4289 4290 /// Calculate the cost of materializing a 64-bit value. This helper 4291 /// method might only calculate a fraction of a larger immediate. Therefore it 4292 /// is valid to return a cost of ZERO. 4293 InstructionCost X86TTIImpl::getIntImmCost(int64_t Val) { 4294 if (Val == 0) 4295 return TTI::TCC_Free; 4296 4297 if (isInt<32>(Val)) 4298 return TTI::TCC_Basic; 4299 4300 return 2 * TTI::TCC_Basic; 4301 } 4302 4303 InstructionCost X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 4304 TTI::TargetCostKind CostKind) { 4305 assert(Ty->isIntegerTy()); 4306 4307 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4308 if (BitSize == 0) 4309 return ~0U; 4310 4311 // Never hoist constants larger than 128bit, because this might lead to 4312 // incorrect code generation or assertions in codegen. 4313 // Fixme: Create a cost model for types larger than i128 once the codegen 4314 // issues have been fixed. 4315 if (BitSize > 128) 4316 return TTI::TCC_Free; 4317 4318 if (Imm == 0) 4319 return TTI::TCC_Free; 4320 4321 // Sign-extend all constants to a multiple of 64-bit. 4322 APInt ImmVal = Imm; 4323 if (BitSize % 64 != 0) 4324 ImmVal = Imm.sext(alignTo(BitSize, 64)); 4325 4326 // Split the constant into 64-bit chunks and calculate the cost for each 4327 // chunk. 4328 InstructionCost Cost = 0; 4329 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 4330 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 4331 int64_t Val = Tmp.getSExtValue(); 4332 Cost += getIntImmCost(Val); 4333 } 4334 // We need at least one instruction to materialize the constant. 4335 return std::max<InstructionCost>(1, Cost); 4336 } 4337 4338 InstructionCost X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, 4339 const APInt &Imm, Type *Ty, 4340 TTI::TargetCostKind CostKind, 4341 Instruction *Inst) { 4342 assert(Ty->isIntegerTy()); 4343 4344 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4345 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4346 // here, so that constant hoisting will ignore this constant. 4347 if (BitSize == 0) 4348 return TTI::TCC_Free; 4349 4350 unsigned ImmIdx = ~0U; 4351 switch (Opcode) { 4352 default: 4353 return TTI::TCC_Free; 4354 case Instruction::GetElementPtr: 4355 // Always hoist the base address of a GetElementPtr. This prevents the 4356 // creation of new constants for every base constant that gets constant 4357 // folded with the offset. 4358 if (Idx == 0) 4359 return 2 * TTI::TCC_Basic; 4360 return TTI::TCC_Free; 4361 case Instruction::Store: 4362 ImmIdx = 0; 4363 break; 4364 case Instruction::ICmp: 4365 // This is an imperfect hack to prevent constant hoisting of 4366 // compares that might be trying to check if a 64-bit value fits in 4367 // 32-bits. The backend can optimize these cases using a right shift by 32. 4368 // Ideally we would check the compare predicate here. There also other 4369 // similar immediates the backend can use shifts for. 4370 if (Idx == 1 && Imm.getBitWidth() == 64) { 4371 uint64_t ImmVal = Imm.getZExtValue(); 4372 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 4373 return TTI::TCC_Free; 4374 } 4375 ImmIdx = 1; 4376 break; 4377 case Instruction::And: 4378 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 4379 // by using a 32-bit operation with implicit zero extension. Detect such 4380 // immediates here as the normal path expects bit 31 to be sign extended. 4381 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 4382 return TTI::TCC_Free; 4383 ImmIdx = 1; 4384 break; 4385 case Instruction::Add: 4386 case Instruction::Sub: 4387 // For add/sub, we can use the opposite instruction for INT32_MIN. 4388 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 4389 return TTI::TCC_Free; 4390 ImmIdx = 1; 4391 break; 4392 case Instruction::UDiv: 4393 case Instruction::SDiv: 4394 case Instruction::URem: 4395 case Instruction::SRem: 4396 // Division by constant is typically expanded later into a different 4397 // instruction sequence. This completely changes the constants. 4398 // Report them as "free" to stop ConstantHoist from marking them as opaque. 4399 return TTI::TCC_Free; 4400 case Instruction::Mul: 4401 case Instruction::Or: 4402 case Instruction::Xor: 4403 ImmIdx = 1; 4404 break; 4405 // Always return TCC_Free for the shift value of a shift instruction. 4406 case Instruction::Shl: 4407 case Instruction::LShr: 4408 case Instruction::AShr: 4409 if (Idx == 1) 4410 return TTI::TCC_Free; 4411 break; 4412 case Instruction::Trunc: 4413 case Instruction::ZExt: 4414 case Instruction::SExt: 4415 case Instruction::IntToPtr: 4416 case Instruction::PtrToInt: 4417 case Instruction::BitCast: 4418 case Instruction::PHI: 4419 case Instruction::Call: 4420 case Instruction::Select: 4421 case Instruction::Ret: 4422 case Instruction::Load: 4423 break; 4424 } 4425 4426 if (Idx == ImmIdx) { 4427 int NumConstants = divideCeil(BitSize, 64); 4428 InstructionCost Cost = X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4429 return (Cost <= NumConstants * TTI::TCC_Basic) 4430 ? static_cast<int>(TTI::TCC_Free) 4431 : Cost; 4432 } 4433 4434 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4435 } 4436 4437 InstructionCost X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 4438 const APInt &Imm, Type *Ty, 4439 TTI::TargetCostKind CostKind) { 4440 assert(Ty->isIntegerTy()); 4441 4442 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4443 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4444 // here, so that constant hoisting will ignore this constant. 4445 if (BitSize == 0) 4446 return TTI::TCC_Free; 4447 4448 switch (IID) { 4449 default: 4450 return TTI::TCC_Free; 4451 case Intrinsic::sadd_with_overflow: 4452 case Intrinsic::uadd_with_overflow: 4453 case Intrinsic::ssub_with_overflow: 4454 case Intrinsic::usub_with_overflow: 4455 case Intrinsic::smul_with_overflow: 4456 case Intrinsic::umul_with_overflow: 4457 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 4458 return TTI::TCC_Free; 4459 break; 4460 case Intrinsic::experimental_stackmap: 4461 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4462 return TTI::TCC_Free; 4463 break; 4464 case Intrinsic::experimental_patchpoint_void: 4465 case Intrinsic::experimental_patchpoint_i64: 4466 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4467 return TTI::TCC_Free; 4468 break; 4469 } 4470 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4471 } 4472 4473 InstructionCost X86TTIImpl::getCFInstrCost(unsigned Opcode, 4474 TTI::TargetCostKind CostKind, 4475 const Instruction *I) { 4476 if (CostKind != TTI::TCK_RecipThroughput) 4477 return Opcode == Instruction::PHI ? 0 : 1; 4478 // Branches are assumed to be predicted. 4479 return 0; 4480 } 4481 4482 int X86TTIImpl::getGatherOverhead() const { 4483 // Some CPUs have more overhead for gather. The specified overhead is relative 4484 // to the Load operation. "2" is the number provided by Intel architects. This 4485 // parameter is used for cost estimation of Gather Op and comparison with 4486 // other alternatives. 4487 // TODO: Remove the explicit hasAVX512()?, That would mean we would only 4488 // enable gather with a -march. 4489 if (ST->hasAVX512() || (ST->hasAVX2() && ST->hasFastGather())) 4490 return 2; 4491 4492 return 1024; 4493 } 4494 4495 int X86TTIImpl::getScatterOverhead() const { 4496 if (ST->hasAVX512()) 4497 return 2; 4498 4499 return 1024; 4500 } 4501 4502 // Return an average cost of Gather / Scatter instruction, maybe improved later. 4503 // FIXME: Add TargetCostKind support. 4504 InstructionCost X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, 4505 const Value *Ptr, Align Alignment, 4506 unsigned AddressSpace) { 4507 4508 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 4509 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4510 4511 // Try to reduce index size from 64 bit (default for GEP) 4512 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 4513 // operation will use 16 x 64 indices which do not fit in a zmm and needs 4514 // to split. Also check that the base pointer is the same for all lanes, 4515 // and that there's at most one variable index. 4516 auto getIndexSizeInBits = [](const Value *Ptr, const DataLayout &DL) { 4517 unsigned IndexSize = DL.getPointerSizeInBits(); 4518 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 4519 if (IndexSize < 64 || !GEP) 4520 return IndexSize; 4521 4522 unsigned NumOfVarIndices = 0; 4523 const Value *Ptrs = GEP->getPointerOperand(); 4524 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 4525 return IndexSize; 4526 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 4527 if (isa<Constant>(GEP->getOperand(i))) 4528 continue; 4529 Type *IndxTy = GEP->getOperand(i)->getType(); 4530 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 4531 IndxTy = IndexVTy->getElementType(); 4532 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 4533 !isa<SExtInst>(GEP->getOperand(i))) || 4534 ++NumOfVarIndices > 1) 4535 return IndexSize; // 64 4536 } 4537 return (unsigned)32; 4538 }; 4539 4540 // Trying to reduce IndexSize to 32 bits for vector 16. 4541 // By default the IndexSize is equal to pointer size. 4542 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 4543 ? getIndexSizeInBits(Ptr, DL) 4544 : DL.getPointerSizeInBits(); 4545 4546 auto *IndexVTy = FixedVectorType::get( 4547 IntegerType::get(SrcVTy->getContext(), IndexSize), VF); 4548 std::pair<InstructionCost, MVT> IdxsLT = 4549 TLI->getTypeLegalizationCost(DL, IndexVTy); 4550 std::pair<InstructionCost, MVT> SrcLT = 4551 TLI->getTypeLegalizationCost(DL, SrcVTy); 4552 InstructionCost::CostType SplitFactor = 4553 *std::max(IdxsLT.first, SrcLT.first).getValue(); 4554 if (SplitFactor > 1) { 4555 // Handle splitting of vector of pointers 4556 auto *SplitSrcTy = 4557 FixedVectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 4558 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 4559 AddressSpace); 4560 } 4561 4562 // The gather / scatter cost is given by Intel architects. It is a rough 4563 // number since we are looking at one instruction in a time. 4564 const int GSOverhead = (Opcode == Instruction::Load) 4565 ? getGatherOverhead() 4566 : getScatterOverhead(); 4567 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4568 MaybeAlign(Alignment), AddressSpace, 4569 TTI::TCK_RecipThroughput); 4570 } 4571 4572 /// Return the cost of full scalarization of gather / scatter operation. 4573 /// 4574 /// Opcode - Load or Store instruction. 4575 /// SrcVTy - The type of the data vector that should be gathered or scattered. 4576 /// VariableMask - The mask is non-constant at compile time. 4577 /// Alignment - Alignment for one element. 4578 /// AddressSpace - pointer[s] address space. 4579 /// 4580 /// FIXME: Add TargetCostKind support. 4581 InstructionCost X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 4582 bool VariableMask, Align Alignment, 4583 unsigned AddressSpace) { 4584 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4585 APInt DemandedElts = APInt::getAllOnesValue(VF); 4586 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4587 4588 InstructionCost MaskUnpackCost = 0; 4589 if (VariableMask) { 4590 auto *MaskTy = 4591 FixedVectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 4592 MaskUnpackCost = 4593 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 4594 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 4595 Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), nullptr, 4596 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4597 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 4598 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 4599 } 4600 4601 // The cost of the scalar loads/stores. 4602 InstructionCost MemoryOpCost = 4603 VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4604 MaybeAlign(Alignment), AddressSpace, CostKind); 4605 4606 InstructionCost InsertExtractCost = 0; 4607 if (Opcode == Instruction::Load) 4608 for (unsigned i = 0; i < VF; ++i) 4609 // Add the cost of inserting each scalar load into the vector 4610 InsertExtractCost += 4611 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 4612 else 4613 for (unsigned i = 0; i < VF; ++i) 4614 // Add the cost of extracting each element out of the data vector 4615 InsertExtractCost += 4616 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 4617 4618 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 4619 } 4620 4621 /// Calculate the cost of Gather / Scatter operation 4622 InstructionCost X86TTIImpl::getGatherScatterOpCost( 4623 unsigned Opcode, Type *SrcVTy, const Value *Ptr, bool VariableMask, 4624 Align Alignment, TTI::TargetCostKind CostKind, 4625 const Instruction *I = nullptr) { 4626 if (CostKind != TTI::TCK_RecipThroughput) { 4627 if ((Opcode == Instruction::Load && 4628 isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4629 (Opcode == Instruction::Store && 4630 isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4631 return 1; 4632 return BaseT::getGatherScatterOpCost(Opcode, SrcVTy, Ptr, VariableMask, 4633 Alignment, CostKind, I); 4634 } 4635 4636 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 4637 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4638 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 4639 if (!PtrTy && Ptr->getType()->isVectorTy()) 4640 PtrTy = dyn_cast<PointerType>( 4641 cast<VectorType>(Ptr->getType())->getElementType()); 4642 assert(PtrTy && "Unexpected type for Ptr argument"); 4643 unsigned AddressSpace = PtrTy->getAddressSpace(); 4644 4645 bool Scalarize = false; 4646 if ((Opcode == Instruction::Load && 4647 !isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4648 (Opcode == Instruction::Store && 4649 !isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4650 Scalarize = true; 4651 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 4652 // Vector-4 of gather/scatter instruction does not exist on KNL. 4653 // We can extend it to 8 elements, but zeroing upper bits of 4654 // the mask vector will add more instructions. Right now we give the scalar 4655 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 4656 // is better in the VariableMask case. 4657 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 4658 Scalarize = true; 4659 4660 if (Scalarize) 4661 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 4662 AddressSpace); 4663 4664 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 4665 } 4666 4667 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 4668 TargetTransformInfo::LSRCost &C2) { 4669 // X86 specific here are "instruction number 1st priority". 4670 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 4671 C1.NumIVMuls, C1.NumBaseAdds, 4672 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 4673 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 4674 C2.NumIVMuls, C2.NumBaseAdds, 4675 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 4676 } 4677 4678 bool X86TTIImpl::canMacroFuseCmp() { 4679 return ST->hasMacroFusion() || ST->hasBranchFusion(); 4680 } 4681 4682 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, Align Alignment) { 4683 if (!ST->hasAVX()) 4684 return false; 4685 4686 // The backend can't handle a single element vector. 4687 if (isa<VectorType>(DataTy) && 4688 cast<FixedVectorType>(DataTy)->getNumElements() == 1) 4689 return false; 4690 Type *ScalarTy = DataTy->getScalarType(); 4691 4692 if (ScalarTy->isPointerTy()) 4693 return true; 4694 4695 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4696 return true; 4697 4698 if (!ScalarTy->isIntegerTy()) 4699 return false; 4700 4701 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4702 return IntWidth == 32 || IntWidth == 64 || 4703 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 4704 } 4705 4706 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, Align Alignment) { 4707 return isLegalMaskedLoad(DataType, Alignment); 4708 } 4709 4710 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 4711 unsigned DataSize = DL.getTypeStoreSize(DataType); 4712 // The only supported nontemporal loads are for aligned vectors of 16 or 32 4713 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 4714 // (the equivalent stores only require AVX). 4715 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 4716 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 4717 4718 return false; 4719 } 4720 4721 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 4722 unsigned DataSize = DL.getTypeStoreSize(DataType); 4723 4724 // SSE4A supports nontemporal stores of float and double at arbitrary 4725 // alignment. 4726 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 4727 return true; 4728 4729 // Besides the SSE4A subtarget exception above, only aligned stores are 4730 // available nontemporaly on any other subtarget. And only stores with a size 4731 // of 4..32 bytes (powers of 2, only) are permitted. 4732 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 4733 !isPowerOf2_32(DataSize)) 4734 return false; 4735 4736 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 4737 // loads require AVX2). 4738 if (DataSize == 32) 4739 return ST->hasAVX(); 4740 else if (DataSize == 16) 4741 return ST->hasSSE1(); 4742 return true; 4743 } 4744 4745 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 4746 if (!isa<VectorType>(DataTy)) 4747 return false; 4748 4749 if (!ST->hasAVX512()) 4750 return false; 4751 4752 // The backend can't handle a single element vector. 4753 if (cast<FixedVectorType>(DataTy)->getNumElements() == 1) 4754 return false; 4755 4756 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 4757 4758 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4759 return true; 4760 4761 if (!ScalarTy->isIntegerTy()) 4762 return false; 4763 4764 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4765 return IntWidth == 32 || IntWidth == 64 || 4766 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 4767 } 4768 4769 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 4770 return isLegalMaskedExpandLoad(DataTy); 4771 } 4772 4773 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, Align Alignment) { 4774 // Some CPUs have better gather performance than others. 4775 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 4776 // enable gather with a -march. 4777 if (!(ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()))) 4778 return false; 4779 4780 // This function is called now in two cases: from the Loop Vectorizer 4781 // and from the Scalarizer. 4782 // When the Loop Vectorizer asks about legality of the feature, 4783 // the vectorization factor is not calculated yet. The Loop Vectorizer 4784 // sends a scalar type and the decision is based on the width of the 4785 // scalar element. 4786 // Later on, the cost model will estimate usage this intrinsic based on 4787 // the vector type. 4788 // The Scalarizer asks again about legality. It sends a vector type. 4789 // In this case we can reject non-power-of-2 vectors. 4790 // We also reject single element vectors as the type legalizer can't 4791 // scalarize it. 4792 if (auto *DataVTy = dyn_cast<FixedVectorType>(DataTy)) { 4793 unsigned NumElts = DataVTy->getNumElements(); 4794 if (NumElts == 1) 4795 return false; 4796 } 4797 Type *ScalarTy = DataTy->getScalarType(); 4798 if (ScalarTy->isPointerTy()) 4799 return true; 4800 4801 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4802 return true; 4803 4804 if (!ScalarTy->isIntegerTy()) 4805 return false; 4806 4807 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4808 return IntWidth == 32 || IntWidth == 64; 4809 } 4810 4811 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, Align Alignment) { 4812 // AVX2 doesn't support scatter 4813 if (!ST->hasAVX512()) 4814 return false; 4815 return isLegalMaskedGather(DataType, Alignment); 4816 } 4817 4818 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 4819 EVT VT = TLI->getValueType(DL, DataType); 4820 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 4821 } 4822 4823 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 4824 return false; 4825 } 4826 4827 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 4828 const Function *Callee) const { 4829 const TargetMachine &TM = getTLI()->getTargetMachine(); 4830 4831 // Work this as a subsetting of subtarget features. 4832 const FeatureBitset &CallerBits = 4833 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 4834 const FeatureBitset &CalleeBits = 4835 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 4836 4837 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 4838 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 4839 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 4840 } 4841 4842 bool X86TTIImpl::areFunctionArgsABICompatible( 4843 const Function *Caller, const Function *Callee, 4844 SmallPtrSetImpl<Argument *> &Args) const { 4845 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args)) 4846 return false; 4847 4848 // If we get here, we know the target features match. If one function 4849 // considers 512-bit vectors legal and the other does not, consider them 4850 // incompatible. 4851 const TargetMachine &TM = getTLI()->getTargetMachine(); 4852 4853 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 4854 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs()) 4855 return true; 4856 4857 // Consider the arguments compatible if they aren't vectors or aggregates. 4858 // FIXME: Look at the size of vectors. 4859 // FIXME: Look at the element types of aggregates to see if there are vectors. 4860 // FIXME: The API of this function seems intended to allow arguments 4861 // to be removed from the set, but the caller doesn't check if the set 4862 // becomes empty so that may not work in practice. 4863 return llvm::none_of(Args, [](Argument *A) { 4864 auto *EltTy = cast<PointerType>(A->getType())->getElementType(); 4865 return EltTy->isVectorTy() || EltTy->isAggregateType(); 4866 }); 4867 } 4868 4869 X86TTIImpl::TTI::MemCmpExpansionOptions 4870 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 4871 TTI::MemCmpExpansionOptions Options; 4872 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 4873 Options.NumLoadsPerBlock = 2; 4874 // All GPR and vector loads can be unaligned. 4875 Options.AllowOverlappingLoads = true; 4876 if (IsZeroCmp) { 4877 // Only enable vector loads for equality comparison. Right now the vector 4878 // version is not as fast for three way compare (see #33329). 4879 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 4880 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 4881 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 4882 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 4883 } 4884 if (ST->is64Bit()) { 4885 Options.LoadSizes.push_back(8); 4886 } 4887 Options.LoadSizes.push_back(4); 4888 Options.LoadSizes.push_back(2); 4889 Options.LoadSizes.push_back(1); 4890 return Options; 4891 } 4892 4893 bool X86TTIImpl::enableInterleavedAccessVectorization() { 4894 // TODO: We expect this to be beneficial regardless of arch, 4895 // but there are currently some unexplained performance artifacts on Atom. 4896 // As a temporary solution, disable on Atom. 4897 return !(ST->isAtom()); 4898 } 4899 4900 // Get estimation for interleaved load/store operations for AVX2. 4901 // \p Factor is the interleaved-access factor (stride) - number of 4902 // (interleaved) elements in the group. 4903 // \p Indices contains the indices for a strided load: when the 4904 // interleaved load has gaps they indicate which elements are used. 4905 // If Indices is empty (or if the number of indices is equal to the size 4906 // of the interleaved-access as given in \p Factor) the access has no gaps. 4907 // 4908 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 4909 // computing the cost using a generic formula as a function of generic 4910 // shuffles. We therefore use a lookup table instead, filled according to 4911 // the instruction sequences that codegen currently generates. 4912 InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2( 4913 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 4914 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 4915 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 4916 4917 if (UseMaskForCond || UseMaskForGaps) 4918 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4919 Alignment, AddressSpace, CostKind, 4920 UseMaskForCond, UseMaskForGaps); 4921 4922 // We currently Support only fully-interleaved groups, with no gaps. 4923 // TODO: Support also strided loads (interleaved-groups with gaps). 4924 if (Indices.size() && Indices.size() != Factor) 4925 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4926 Alignment, AddressSpace, CostKind); 4927 4928 // VecTy for interleave memop is <VF*Factor x Elt>. 4929 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4930 // VecTy = <12 x i32>. 4931 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4932 4933 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 4934 // the VF=2, while v2i128 is an unsupported MVT vector type 4935 // (see MachineValueType.h::getVectorVT()). 4936 if (!LegalVT.isVector()) 4937 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4938 Alignment, AddressSpace, CostKind); 4939 4940 unsigned VF = VecTy->getNumElements() / Factor; 4941 Type *ScalarTy = VecTy->getElementType(); 4942 // Deduplicate entries, model floats/pointers as appropriately-sized integers. 4943 if (!ScalarTy->isIntegerTy()) 4944 ScalarTy = 4945 Type::getIntNTy(ScalarTy->getContext(), DL.getTypeSizeInBits(ScalarTy)); 4946 4947 // Get the cost of all the memory operations. 4948 InstructionCost MemOpCosts = getMemoryOpCost( 4949 Opcode, VecTy, MaybeAlign(Alignment), AddressSpace, CostKind); 4950 4951 auto *VT = FixedVectorType::get(ScalarTy, VF); 4952 EVT ETy = TLI->getValueType(DL, VT); 4953 if (!ETy.isSimple()) 4954 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4955 Alignment, AddressSpace, CostKind); 4956 4957 // TODO: Complete for other data-types and strides. 4958 // Each combination of Stride, element bit width and VF results in a different 4959 // sequence; The cost tables are therefore accessed with: 4960 // Factor (stride) and VectorType=VFxiN. 4961 // The Cost accounts only for the shuffle sequence; 4962 // The cost of the loads/stores is accounted for separately. 4963 // 4964 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 4965 {2, MVT::v4i64, 6}, // (load 8i64 and) deinterleave into 2 x 4i64 4966 4967 {3, MVT::v2i8, 10}, // (load 6i8 and) deinterleave into 3 x 2i8 4968 {3, MVT::v4i8, 4}, // (load 12i8 and) deinterleave into 3 x 4i8 4969 {3, MVT::v8i8, 9}, // (load 24i8 and) deinterleave into 3 x 8i8 4970 {3, MVT::v16i8, 11}, // (load 48i8 and) deinterleave into 3 x 16i8 4971 {3, MVT::v32i8, 13}, // (load 96i8 and) deinterleave into 3 x 32i8 4972 4973 {3, MVT::v8i32, 17}, // (load 24i32 and) deinterleave into 3 x 8i32 4974 4975 {4, MVT::v2i8, 12}, // (load 8i8 and) deinterleave into 4 x 2i8 4976 {4, MVT::v4i8, 4}, // (load 16i8 and) deinterleave into 4 x 4i8 4977 {4, MVT::v8i8, 20}, // (load 32i8 and) deinterleave into 4 x 8i8 4978 {4, MVT::v16i8, 39}, // (load 64i8 and) deinterleave into 4 x 16i8 4979 {4, MVT::v32i8, 80}, // (load 128i8 and) deinterleave into 4 x 32i8 4980 4981 {8, MVT::v8i32, 40} // (load 64i32 and) deinterleave into 8 x 8i32 4982 }; 4983 4984 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 4985 {2, MVT::v4i64, 6}, // interleave 2 x 4i64 into 8i64 (and store) 4986 4987 {3, MVT::v2i8, 7}, // interleave 3 x 2i8 into 6i8 (and store) 4988 {3, MVT::v4i8, 8}, // interleave 3 x 4i8 into 12i8 (and store) 4989 {3, MVT::v8i8, 11}, // interleave 3 x 8i8 into 24i8 (and store) 4990 {3, MVT::v16i8, 11}, // interleave 3 x 16i8 into 48i8 (and store) 4991 {3, MVT::v32i8, 13}, // interleave 3 x 32i8 into 96i8 (and store) 4992 4993 {4, MVT::v2i8, 12}, // interleave 4 x 2i8 into 8i8 (and store) 4994 {4, MVT::v4i8, 9}, // interleave 4 x 4i8 into 16i8 (and store) 4995 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 4996 {4, MVT::v16i8, 10}, // interleave 4 x 16i8 into 64i8 (and store) 4997 {4, MVT::v32i8, 12} // interleave 4 x 32i8 into 128i8 (and store) 4998 }; 4999 5000 if (Opcode == Instruction::Load) { 5001 if (const auto *Entry = 5002 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 5003 return MemOpCosts + Entry->Cost; 5004 } else { 5005 assert(Opcode == Instruction::Store && 5006 "Expected Store Instruction at this point"); 5007 if (const auto *Entry = 5008 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 5009 return MemOpCosts + Entry->Cost; 5010 } 5011 5012 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5013 Alignment, AddressSpace, CostKind); 5014 } 5015 5016 // Get estimation for interleaved load/store operations and strided load. 5017 // \p Indices contains indices for strided load. 5018 // \p Factor - the factor of interleaving. 5019 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 5020 InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX512( 5021 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 5022 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 5023 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 5024 5025 if (UseMaskForCond || UseMaskForGaps) 5026 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5027 Alignment, AddressSpace, CostKind, 5028 UseMaskForCond, UseMaskForGaps); 5029 5030 // VecTy for interleave memop is <VF*Factor x Elt>. 5031 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 5032 // VecTy = <12 x i32>. 5033 5034 // Calculate the number of memory operations (NumOfMemOps), required 5035 // for load/store the VecTy. 5036 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 5037 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 5038 unsigned LegalVTSize = LegalVT.getStoreSize(); 5039 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 5040 5041 // Get the cost of one memory operation. 5042 auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(), 5043 LegalVT.getVectorNumElements()); 5044 InstructionCost MemOpCost = getMemoryOpCost( 5045 Opcode, SingleMemOpTy, MaybeAlign(Alignment), AddressSpace, CostKind); 5046 5047 unsigned VF = VecTy->getNumElements() / Factor; 5048 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 5049 5050 if (Opcode == Instruction::Load) { 5051 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 5052 // contain the cost of the optimized shuffle sequence that the 5053 // X86InterleavedAccess pass will generate. 5054 // The cost of loads and stores are computed separately from the table. 5055 5056 // X86InterleavedAccess support only the following interleaved-access group. 5057 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 5058 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 5059 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 5060 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 5061 }; 5062 5063 if (const auto *Entry = 5064 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 5065 return NumOfMemOps * MemOpCost + Entry->Cost; 5066 //If an entry does not exist, fallback to the default implementation. 5067 5068 // Kind of shuffle depends on number of loaded values. 5069 // If we load the entire data in one register, we can use a 1-src shuffle. 5070 // Otherwise, we'll merge 2 sources in each operation. 5071 TTI::ShuffleKind ShuffleKind = 5072 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 5073 5074 InstructionCost ShuffleCost = 5075 getShuffleCost(ShuffleKind, SingleMemOpTy, None, 0, nullptr); 5076 5077 unsigned NumOfLoadsInInterleaveGrp = 5078 Indices.size() ? Indices.size() : Factor; 5079 auto *ResultTy = FixedVectorType::get(VecTy->getElementType(), 5080 VecTy->getNumElements() / Factor); 5081 InstructionCost NumOfResults = 5082 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 5083 NumOfLoadsInInterleaveGrp; 5084 5085 // About a half of the loads may be folded in shuffles when we have only 5086 // one result. If we have more than one result, we do not fold loads at all. 5087 unsigned NumOfUnfoldedLoads = 5088 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 5089 5090 // Get a number of shuffle operations per result. 5091 unsigned NumOfShufflesPerResult = 5092 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 5093 5094 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 5095 // When we have more than one destination, we need additional instructions 5096 // to keep sources. 5097 InstructionCost NumOfMoves = 0; 5098 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 5099 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 5100 5101 InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 5102 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 5103 5104 return Cost; 5105 } 5106 5107 // Store. 5108 assert(Opcode == Instruction::Store && 5109 "Expected Store Instruction at this point"); 5110 // X86InterleavedAccess support only the following interleaved-access group. 5111 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 5112 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 5113 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 5114 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 5115 5116 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 5117 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 5118 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 5119 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 5120 }; 5121 5122 if (const auto *Entry = 5123 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 5124 return NumOfMemOps * MemOpCost + Entry->Cost; 5125 //If an entry does not exist, fallback to the default implementation. 5126 5127 // There is no strided stores meanwhile. And store can't be folded in 5128 // shuffle. 5129 unsigned NumOfSources = Factor; // The number of values to be merged. 5130 InstructionCost ShuffleCost = 5131 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, None, 0, nullptr); 5132 unsigned NumOfShufflesPerStore = NumOfSources - 1; 5133 5134 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 5135 // We need additional instructions to keep sources. 5136 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 5137 InstructionCost Cost = 5138 NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 5139 NumOfMoves; 5140 return Cost; 5141 } 5142 5143 InstructionCost X86TTIImpl::getInterleavedMemoryOpCost( 5144 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, 5145 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, 5146 bool UseMaskForCond, bool UseMaskForGaps) { 5147 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 5148 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 5149 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 5150 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 5151 return true; 5152 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 5153 return HasBW; 5154 return false; 5155 }; 5156 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 5157 return getInterleavedMemoryOpCostAVX512( 5158 Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment, 5159 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 5160 if (ST->hasAVX2()) 5161 return getInterleavedMemoryOpCostAVX2( 5162 Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment, 5163 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 5164 5165 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5166 Alignment, AddressSpace, CostKind, 5167 UseMaskForCond, UseMaskForGaps); 5168 } 5169