1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // X86 cost model. 56 // 57 //===----------------------------------------------------------------------===// 58 59 TargetTransformInfo::PopcntSupportKind 60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 61 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 62 // TODO: Currently the __builtin_popcount() implementation using SSE3 63 // instructions is inefficient. Once the problem is fixed, we should 64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 66 } 67 68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 69 TargetTransformInfo::CacheLevel Level) const { 70 switch (Level) { 71 case TargetTransformInfo::CacheLevel::L1D: 72 // - Penryn 73 // - Nehalem 74 // - Westmere 75 // - Sandy Bridge 76 // - Ivy Bridge 77 // - Haswell 78 // - Broadwell 79 // - Skylake 80 // - Kabylake 81 return 32 * 1024; // 32 KByte 82 case TargetTransformInfo::CacheLevel::L2D: 83 // - Penryn 84 // - Nehalem 85 // - Westmere 86 // - Sandy Bridge 87 // - Ivy Bridge 88 // - Haswell 89 // - Broadwell 90 // - Skylake 91 // - Kabylake 92 return 256 * 1024; // 256 KByte 93 } 94 95 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 96 } 97 98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 99 TargetTransformInfo::CacheLevel Level) const { 100 // - Penryn 101 // - Nehalem 102 // - Westmere 103 // - Sandy Bridge 104 // - Ivy Bridge 105 // - Haswell 106 // - Broadwell 107 // - Skylake 108 // - Kabylake 109 switch (Level) { 110 case TargetTransformInfo::CacheLevel::L1D: 111 LLVM_FALLTHROUGH; 112 case TargetTransformInfo::CacheLevel::L2D: 113 return 8; 114 } 115 116 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 117 } 118 119 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 120 bool Vector = (ClassID == 1); 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const { 133 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 134 if (Vector) { 135 if (ST->hasAVX512() && PreferVectorWidth >= 512) 136 return 512; 137 if (ST->hasAVX() && PreferVectorWidth >= 256) 138 return 256; 139 if (ST->hasSSE1() && PreferVectorWidth >= 128) 140 return 128; 141 return 0; 142 } 143 144 if (ST->is64Bit()) 145 return 64; 146 147 return 32; 148 } 149 150 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 151 return getRegisterBitWidth(true); 152 } 153 154 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 155 // If the loop will not be vectorized, don't interleave the loop. 156 // Let regular unroll to unroll the loop, which saves the overflow 157 // check and memory check cost. 158 if (VF == 1) 159 return 1; 160 161 if (ST->isAtom()) 162 return 1; 163 164 // Sandybridge and Haswell have multiple execution ports and pipelined 165 // vector units. 166 if (ST->hasAVX()) 167 return 4; 168 169 return 2; 170 } 171 172 int X86TTIImpl::getArithmeticInstrCost(unsigned Opcode, Type *Ty, 173 TTI::OperandValueKind Op1Info, 174 TTI::OperandValueKind Op2Info, 175 TTI::OperandValueProperties Opd1PropInfo, 176 TTI::OperandValueProperties Opd2PropInfo, 177 ArrayRef<const Value *> Args, 178 const Instruction *CxtI) { 179 // Legalize the type. 180 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 181 182 int ISD = TLI->InstructionOpcodeToISD(Opcode); 183 assert(ISD && "Invalid opcode"); 184 185 static const CostTblEntry GLMCostTable[] = { 186 { ISD::FDIV, MVT::f32, 18 }, // divss 187 { ISD::FDIV, MVT::v4f32, 35 }, // divps 188 { ISD::FDIV, MVT::f64, 33 }, // divsd 189 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 190 }; 191 192 if (ST->useGLMDivSqrtCosts()) 193 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 194 LT.second)) 195 return LT.first * Entry->Cost; 196 197 static const CostTblEntry SLMCostTable[] = { 198 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 199 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 200 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. 201 { ISD::FMUL, MVT::f64, 2 }, // mulsd 202 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 203 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 204 { ISD::FDIV, MVT::f32, 17 }, // divss 205 { ISD::FDIV, MVT::v4f32, 39 }, // divps 206 { ISD::FDIV, MVT::f64, 32 }, // divsd 207 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 208 { ISD::FADD, MVT::v2f64, 2 }, // addpd 209 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 210 // v2i64/v4i64 mul is custom lowered as a series of long: 211 // multiplies(3), shifts(3) and adds(2) 212 // slm muldq version throughput is 2 and addq throughput 4 213 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 214 // 3X4 (addq throughput) = 17 215 { ISD::MUL, MVT::v2i64, 17 }, 216 // slm addq\subq throughput is 4 217 { ISD::ADD, MVT::v2i64, 4 }, 218 { ISD::SUB, MVT::v2i64, 4 }, 219 }; 220 221 if (ST->isSLM()) { 222 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 223 // Check if the operands can be shrinked into a smaller datatype. 224 bool Op1Signed = false; 225 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 226 bool Op2Signed = false; 227 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 228 229 bool signedMode = Op1Signed | Op2Signed; 230 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 231 232 if (OpMinSize <= 7) 233 return LT.first * 3; // pmullw/sext 234 if (!signedMode && OpMinSize <= 8) 235 return LT.first * 3; // pmullw/zext 236 if (OpMinSize <= 15) 237 return LT.first * 5; // pmullw/pmulhw/pshuf 238 if (!signedMode && OpMinSize <= 16) 239 return LT.first * 5; // pmullw/pmulhw/pshuf 240 } 241 242 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 243 LT.second)) { 244 return LT.first * Entry->Cost; 245 } 246 } 247 248 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 249 ISD == ISD::UREM) && 250 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 251 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 252 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 253 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 254 // On X86, vector signed division by constants power-of-two are 255 // normally expanded to the sequence SRA + SRL + ADD + SRA. 256 // The OperandValue properties may not be the same as that of the previous 257 // operation; conservatively assume OP_None. 258 int Cost = 259 2 * getArithmeticInstrCost(Instruction::AShr, Ty, Op1Info, Op2Info, 260 TargetTransformInfo::OP_None, 261 TargetTransformInfo::OP_None); 262 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 263 TargetTransformInfo::OP_None, 264 TargetTransformInfo::OP_None); 265 Cost += getArithmeticInstrCost(Instruction::Add, Ty, Op1Info, Op2Info, 266 TargetTransformInfo::OP_None, 267 TargetTransformInfo::OP_None); 268 269 if (ISD == ISD::SREM) { 270 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 271 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info); 272 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, Op1Info, Op2Info); 273 } 274 275 return Cost; 276 } 277 278 // Vector unsigned division/remainder will be simplified to shifts/masks. 279 if (ISD == ISD::UDIV) 280 return getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 281 TargetTransformInfo::OP_None, 282 TargetTransformInfo::OP_None); 283 284 else // UREM 285 return getArithmeticInstrCost(Instruction::And, Ty, Op1Info, Op2Info, 286 TargetTransformInfo::OP_None, 287 TargetTransformInfo::OP_None); 288 } 289 290 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 291 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 292 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 293 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 294 }; 295 296 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 297 ST->hasBWI()) { 298 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 299 LT.second)) 300 return LT.first * Entry->Cost; 301 } 302 303 static const CostTblEntry AVX512UniformConstCostTable[] = { 304 { ISD::SRA, MVT::v2i64, 1 }, 305 { ISD::SRA, MVT::v4i64, 1 }, 306 { ISD::SRA, MVT::v8i64, 1 }, 307 308 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 309 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 310 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 311 }; 312 313 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 314 ST->hasAVX512()) { 315 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 316 LT.second)) 317 return LT.first * Entry->Cost; 318 } 319 320 static const CostTblEntry AVX2UniformConstCostTable[] = { 321 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 322 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 323 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 324 325 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 326 }; 327 328 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 329 ST->hasAVX2()) { 330 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 331 LT.second)) 332 return LT.first * Entry->Cost; 333 } 334 335 static const CostTblEntry SSE2UniformConstCostTable[] = { 336 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 337 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 338 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 339 340 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 341 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 342 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 343 }; 344 345 // XOP has faster vXi8 shifts. 346 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 347 ST->hasSSE2() && !ST->hasXOP()) { 348 if (const auto *Entry = 349 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 350 return LT.first * Entry->Cost; 351 } 352 353 static const CostTblEntry AVX512BWConstCostTable[] = { 354 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 355 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 356 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 357 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 358 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 359 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 360 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 361 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 362 }; 363 364 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 365 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 366 ST->hasBWI()) { 367 if (const auto *Entry = 368 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 369 return LT.first * Entry->Cost; 370 } 371 372 static const CostTblEntry AVX512ConstCostTable[] = { 373 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 374 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 375 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 376 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 377 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 378 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 379 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 380 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 381 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 382 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 383 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 384 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 385 }; 386 387 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 388 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 389 ST->hasAVX512()) { 390 if (const auto *Entry = 391 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 392 return LT.first * Entry->Cost; 393 } 394 395 static const CostTblEntry AVX2ConstCostTable[] = { 396 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 397 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 398 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 399 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 400 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 401 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 402 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 403 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 404 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 405 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 406 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 407 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 408 }; 409 410 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 411 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 412 ST->hasAVX2()) { 413 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 414 return LT.first * Entry->Cost; 415 } 416 417 static const CostTblEntry SSE2ConstCostTable[] = { 418 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 419 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 420 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 421 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 422 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 423 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 424 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 425 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 426 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 427 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 428 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 429 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 430 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 431 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 432 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 433 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 434 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 435 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 436 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 437 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 438 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 439 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 440 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 441 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 442 }; 443 444 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 445 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 446 ST->hasSSE2()) { 447 // pmuldq sequence. 448 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 449 return LT.first * 32; 450 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 451 return LT.first * 38; 452 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 453 return LT.first * 15; 454 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 455 return LT.first * 20; 456 457 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 458 return LT.first * Entry->Cost; 459 } 460 461 static const CostTblEntry AVX512BWShiftCostTable[] = { 462 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 463 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 464 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 465 466 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 467 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 468 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 469 470 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 471 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 472 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 473 }; 474 475 if (ST->hasBWI()) 476 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 477 return LT.first * Entry->Cost; 478 479 static const CostTblEntry AVX2UniformCostTable[] = { 480 // Uniform splats are cheaper for the following instructions. 481 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 482 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 483 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 484 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 485 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 486 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 487 }; 488 489 if (ST->hasAVX2() && 490 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 491 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 492 if (const auto *Entry = 493 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 494 return LT.first * Entry->Cost; 495 } 496 497 static const CostTblEntry SSE2UniformCostTable[] = { 498 // Uniform splats are cheaper for the following instructions. 499 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 500 { ISD::SHL, MVT::v4i32, 1 }, // pslld 501 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 502 503 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 504 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 505 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 506 507 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 508 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 509 }; 510 511 if (ST->hasSSE2() && 512 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 513 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 514 if (const auto *Entry = 515 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 516 return LT.first * Entry->Cost; 517 } 518 519 static const CostTblEntry AVX512DQCostTable[] = { 520 { ISD::MUL, MVT::v2i64, 1 }, 521 { ISD::MUL, MVT::v4i64, 1 }, 522 { ISD::MUL, MVT::v8i64, 1 } 523 }; 524 525 // Look for AVX512DQ lowering tricks for custom cases. 526 if (ST->hasDQI()) 527 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 528 return LT.first * Entry->Cost; 529 530 static const CostTblEntry AVX512BWCostTable[] = { 531 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 532 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 533 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 534 535 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence. 536 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence. 537 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence. 538 }; 539 540 // Look for AVX512BW lowering tricks for custom cases. 541 if (ST->hasBWI()) 542 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 543 return LT.first * Entry->Cost; 544 545 static const CostTblEntry AVX512CostTable[] = { 546 { ISD::SHL, MVT::v16i32, 1 }, 547 { ISD::SRL, MVT::v16i32, 1 }, 548 { ISD::SRA, MVT::v16i32, 1 }, 549 550 { ISD::SHL, MVT::v8i64, 1 }, 551 { ISD::SRL, MVT::v8i64, 1 }, 552 553 { ISD::SRA, MVT::v2i64, 1 }, 554 { ISD::SRA, MVT::v4i64, 1 }, 555 { ISD::SRA, MVT::v8i64, 1 }, 556 557 { ISD::MUL, MVT::v64i8, 26 }, // extend/pmullw/trunc sequence. 558 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence. 559 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence. 560 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 561 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 562 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 563 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add 564 565 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 566 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 567 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 568 569 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 570 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 571 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 572 }; 573 574 if (ST->hasAVX512()) 575 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 576 return LT.first * Entry->Cost; 577 578 static const CostTblEntry AVX2ShiftCostTable[] = { 579 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 580 // customize them to detect the cases where shift amount is a scalar one. 581 { ISD::SHL, MVT::v4i32, 1 }, 582 { ISD::SRL, MVT::v4i32, 1 }, 583 { ISD::SRA, MVT::v4i32, 1 }, 584 { ISD::SHL, MVT::v8i32, 1 }, 585 { ISD::SRL, MVT::v8i32, 1 }, 586 { ISD::SRA, MVT::v8i32, 1 }, 587 { ISD::SHL, MVT::v2i64, 1 }, 588 { ISD::SRL, MVT::v2i64, 1 }, 589 { ISD::SHL, MVT::v4i64, 1 }, 590 { ISD::SRL, MVT::v4i64, 1 }, 591 }; 592 593 if (ST->hasAVX512()) { 594 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 595 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 596 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 597 // On AVX512, a packed v32i16 shift left by a constant build_vector 598 // is lowered into a vector multiply (vpmullw). 599 return getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info, 600 TargetTransformInfo::OP_None, 601 TargetTransformInfo::OP_None); 602 } 603 604 // Look for AVX2 lowering tricks. 605 if (ST->hasAVX2()) { 606 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 607 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 608 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 609 // On AVX2, a packed v16i16 shift left by a constant build_vector 610 // is lowered into a vector multiply (vpmullw). 611 return getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info, 612 TargetTransformInfo::OP_None, 613 TargetTransformInfo::OP_None); 614 615 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 616 return LT.first * Entry->Cost; 617 } 618 619 static const CostTblEntry XOPShiftCostTable[] = { 620 // 128bit shifts take 1cy, but right shifts require negation beforehand. 621 { ISD::SHL, MVT::v16i8, 1 }, 622 { ISD::SRL, MVT::v16i8, 2 }, 623 { ISD::SRA, MVT::v16i8, 2 }, 624 { ISD::SHL, MVT::v8i16, 1 }, 625 { ISD::SRL, MVT::v8i16, 2 }, 626 { ISD::SRA, MVT::v8i16, 2 }, 627 { ISD::SHL, MVT::v4i32, 1 }, 628 { ISD::SRL, MVT::v4i32, 2 }, 629 { ISD::SRA, MVT::v4i32, 2 }, 630 { ISD::SHL, MVT::v2i64, 1 }, 631 { ISD::SRL, MVT::v2i64, 2 }, 632 { ISD::SRA, MVT::v2i64, 2 }, 633 // 256bit shifts require splitting if AVX2 didn't catch them above. 634 { ISD::SHL, MVT::v32i8, 2+2 }, 635 { ISD::SRL, MVT::v32i8, 4+2 }, 636 { ISD::SRA, MVT::v32i8, 4+2 }, 637 { ISD::SHL, MVT::v16i16, 2+2 }, 638 { ISD::SRL, MVT::v16i16, 4+2 }, 639 { ISD::SRA, MVT::v16i16, 4+2 }, 640 { ISD::SHL, MVT::v8i32, 2+2 }, 641 { ISD::SRL, MVT::v8i32, 4+2 }, 642 { ISD::SRA, MVT::v8i32, 4+2 }, 643 { ISD::SHL, MVT::v4i64, 2+2 }, 644 { ISD::SRL, MVT::v4i64, 4+2 }, 645 { ISD::SRA, MVT::v4i64, 4+2 }, 646 }; 647 648 // Look for XOP lowering tricks. 649 if (ST->hasXOP()) { 650 // If the right shift is constant then we'll fold the negation so 651 // it's as cheap as a left shift. 652 int ShiftISD = ISD; 653 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 654 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 655 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 656 ShiftISD = ISD::SHL; 657 if (const auto *Entry = 658 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 659 return LT.first * Entry->Cost; 660 } 661 662 static const CostTblEntry SSE2UniformShiftCostTable[] = { 663 // Uniform splats are cheaper for the following instructions. 664 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 665 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 666 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 667 668 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 669 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 670 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 671 672 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 673 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 674 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 675 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 676 }; 677 678 if (ST->hasSSE2() && 679 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 680 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 681 682 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 683 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 684 return LT.first * 4; // 2*psrad + shuffle. 685 686 if (const auto *Entry = 687 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 688 return LT.first * Entry->Cost; 689 } 690 691 if (ISD == ISD::SHL && 692 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 693 MVT VT = LT.second; 694 // Vector shift left by non uniform constant can be lowered 695 // into vector multiply. 696 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 697 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 698 ISD = ISD::MUL; 699 } 700 701 static const CostTblEntry AVX2CostTable[] = { 702 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. 703 { ISD::SHL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. 704 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 705 { ISD::SHL, MVT::v32i16, 20 }, // 2*extend/vpsrlvd/pack sequence. 706 707 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. 708 { ISD::SRL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. 709 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 710 { ISD::SRL, MVT::v32i16, 20 }, // 2*extend/vpsrlvd/pack sequence. 711 712 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. 713 { ISD::SRA, MVT::v64i8, 48 }, // 2*vpblendvb sequence. 714 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. 715 { ISD::SRA, MVT::v32i16, 20 }, // 2*extend/vpsravd/pack sequence. 716 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. 717 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 718 719 { ISD::SUB, MVT::v32i8, 1 }, // psubb 720 { ISD::ADD, MVT::v32i8, 1 }, // paddb 721 { ISD::SUB, MVT::v16i16, 1 }, // psubw 722 { ISD::ADD, MVT::v16i16, 1 }, // paddw 723 { ISD::SUB, MVT::v8i32, 1 }, // psubd 724 { ISD::ADD, MVT::v8i32, 1 }, // paddd 725 { ISD::SUB, MVT::v4i64, 1 }, // psubq 726 { ISD::ADD, MVT::v4i64, 1 }, // paddq 727 728 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence. 729 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence. 730 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 731 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 732 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add 733 734 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 735 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 736 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 737 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 738 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 739 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 740 741 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 742 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 743 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 744 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 745 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 746 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 747 }; 748 749 // Look for AVX2 lowering tricks for custom cases. 750 if (ST->hasAVX2()) 751 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 752 return LT.first * Entry->Cost; 753 754 static const CostTblEntry AVX1CostTable[] = { 755 // We don't have to scalarize unsupported ops. We can issue two half-sized 756 // operations and we only need to extract the upper YMM half. 757 // Two ops + 1 extract + 1 insert = 4. 758 { ISD::MUL, MVT::v16i16, 4 }, 759 { ISD::MUL, MVT::v8i32, 4 }, 760 { ISD::SUB, MVT::v32i8, 4 }, 761 { ISD::ADD, MVT::v32i8, 4 }, 762 { ISD::SUB, MVT::v16i16, 4 }, 763 { ISD::ADD, MVT::v16i16, 4 }, 764 { ISD::SUB, MVT::v8i32, 4 }, 765 { ISD::ADD, MVT::v8i32, 4 }, 766 { ISD::SUB, MVT::v4i64, 4 }, 767 { ISD::ADD, MVT::v4i64, 4 }, 768 769 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 770 // are lowered as a series of long multiplies(3), shifts(3) and adds(2) 771 // Because we believe v4i64 to be a legal type, we must also include the 772 // extract+insert in the cost table. Therefore, the cost here is 18 773 // instead of 8. 774 { ISD::MUL, MVT::v4i64, 18 }, 775 776 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence. 777 778 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 779 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 780 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 781 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 782 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 783 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 784 }; 785 786 if (ST->hasAVX()) 787 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 788 return LT.first * Entry->Cost; 789 790 static const CostTblEntry SSE42CostTable[] = { 791 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 792 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 793 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 794 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 795 796 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 797 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 798 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 799 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 800 801 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 802 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 803 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 804 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 805 806 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 807 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 808 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 809 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 810 }; 811 812 if (ST->hasSSE42()) 813 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 814 return LT.first * Entry->Cost; 815 816 static const CostTblEntry SSE41CostTable[] = { 817 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 818 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split. 819 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 820 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 821 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 822 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split 823 824 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 825 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split. 826 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 827 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 828 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 829 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split. 830 831 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 832 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split. 833 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 834 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 835 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 836 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split. 837 838 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 839 }; 840 841 if (ST->hasSSE41()) 842 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 843 return LT.first * Entry->Cost; 844 845 static const CostTblEntry SSE2CostTable[] = { 846 // We don't correctly identify costs of casts because they are marked as 847 // custom. 848 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 849 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 850 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 851 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 852 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 853 854 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 855 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 856 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 857 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 858 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 859 860 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 861 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 862 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 863 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 864 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split. 865 866 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence. 867 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 868 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 869 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 870 871 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 872 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 873 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 874 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 875 876 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 877 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 878 879 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 880 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 881 }; 882 883 if (ST->hasSSE2()) 884 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 885 return LT.first * Entry->Cost; 886 887 static const CostTblEntry SSE1CostTable[] = { 888 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 889 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 890 891 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 892 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 893 894 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 895 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 896 897 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 898 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 899 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 900 901 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 902 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 903 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 904 }; 905 906 if (ST->hasSSE1()) 907 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 908 return LT.first * Entry->Cost; 909 910 // It is not a good idea to vectorize division. We have to scalarize it and 911 // in the process we will often end up having to spilling regular 912 // registers. The overhead of division is going to dominate most kernels 913 // anyways so try hard to prevent vectorization of division - it is 914 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 915 // to hide "20 cycles" for each lane. 916 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 917 ISD == ISD::UDIV || ISD == ISD::UREM)) { 918 int ScalarCost = getArithmeticInstrCost( 919 Opcode, Ty->getScalarType(), Op1Info, Op2Info, 920 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 921 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 922 } 923 924 // Fallback to the default implementation. 925 return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info); 926 } 927 928 int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, VectorType *BaseTp, 929 int Index, VectorType *SubTp) { 930 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 931 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 932 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 933 934 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 935 if (Kind == TTI::SK_Transpose) 936 Kind = TTI::SK_PermuteTwoSrc; 937 938 // For Broadcasts we are splatting the first element from the first input 939 // register, so only need to reference that input and all the output 940 // registers are the same. 941 if (Kind == TTI::SK_Broadcast) 942 LT.first = 1; 943 944 // Subvector extractions are free if they start at the beginning of a 945 // vector and cheap if the subvectors are aligned. 946 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 947 int NumElts = LT.second.getVectorNumElements(); 948 if ((Index % NumElts) == 0) 949 return 0; 950 std::pair<int, MVT> SubLT = TLI->getTypeLegalizationCost(DL, SubTp); 951 if (SubLT.second.isVector()) { 952 int NumSubElts = SubLT.second.getVectorNumElements(); 953 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 954 return SubLT.first; 955 // Handle some cases for widening legalization. For now we only handle 956 // cases where the original subvector was naturally aligned and evenly 957 // fit in its legalized subvector type. 958 // FIXME: Remove some of the alignment restrictions. 959 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 960 // vectors. 961 int OrigSubElts = cast<VectorType>(SubTp)->getNumElements(); 962 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 963 (NumSubElts % OrigSubElts) == 0 && 964 LT.second.getVectorElementType() == 965 SubLT.second.getVectorElementType() && 966 LT.second.getVectorElementType().getSizeInBits() == 967 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 968 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 969 "Unexpected number of elements!"); 970 VectorType *VecTy = VectorType::get(BaseTp->getElementType(), 971 LT.second.getVectorNumElements()); 972 VectorType *SubTy = 973 VectorType::get(BaseTp->getElementType(), 974 SubLT.second.getVectorNumElements()); 975 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 976 int ExtractCost = getShuffleCost(TTI::SK_ExtractSubvector, VecTy, 977 ExtractIndex, SubTy); 978 979 // If the original size is 32-bits or more, we can use pshufd. Otherwise 980 // if we have SSSE3 we can use pshufb. 981 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 982 return ExtractCost + 1; // pshufd or pshufb 983 984 assert(SubTp->getPrimitiveSizeInBits() == 16 && 985 "Unexpected vector size"); 986 987 return ExtractCost + 2; // worst case pshufhw + pshufd 988 } 989 } 990 } 991 992 // Handle some common (illegal) sub-vector types as they are often very cheap 993 // to shuffle even on targets without PSHUFB. 994 EVT VT = TLI->getValueType(DL, BaseTp); 995 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 996 !ST->hasSSSE3()) { 997 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 998 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 999 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1000 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1001 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1002 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1003 1004 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1005 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1006 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1007 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1008 1009 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1010 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1011 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1012 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1013 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1014 1015 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1016 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1017 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1018 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1019 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1020 }; 1021 1022 if (ST->hasSSE2()) 1023 if (const auto *Entry = 1024 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1025 return Entry->Cost; 1026 } 1027 1028 // We are going to permute multiple sources and the result will be in multiple 1029 // destinations. Providing an accurate cost only for splits where the element 1030 // type remains the same. 1031 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1032 MVT LegalVT = LT.second; 1033 if (LegalVT.isVector() && 1034 LegalVT.getVectorElementType().getSizeInBits() == 1035 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1036 LegalVT.getVectorNumElements() < BaseTp->getNumElements()) { 1037 1038 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1039 unsigned LegalVTSize = LegalVT.getStoreSize(); 1040 // Number of source vectors after legalization: 1041 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1042 // Number of destination vectors after legalization: 1043 unsigned NumOfDests = LT.first; 1044 1045 VectorType *SingleOpTy = 1046 VectorType::get(BaseTp->getElementType(), 1047 LegalVT.getVectorNumElements()); 1048 1049 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1050 return NumOfShuffles * 1051 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 0, nullptr); 1052 } 1053 1054 return BaseT::getShuffleCost(Kind, BaseTp, Index, SubTp); 1055 } 1056 1057 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1058 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1059 // We assume that source and destination have the same vector type. 1060 int NumOfDests = LT.first; 1061 int NumOfShufflesPerDest = LT.first * 2 - 1; 1062 LT.first = NumOfDests * NumOfShufflesPerDest; 1063 } 1064 1065 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1066 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1067 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1068 1069 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1070 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1071 1072 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b 1073 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b 1074 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2} // vpermt2b 1075 }; 1076 1077 if (ST->hasVBMI()) 1078 if (const auto *Entry = 1079 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1080 return LT.first * Entry->Cost; 1081 1082 static const CostTblEntry AVX512BWShuffleTbl[] = { 1083 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1084 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1085 1086 {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw 1087 {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw 1088 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1089 1090 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw 1091 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw 1092 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1093 1094 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w 1095 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w 1096 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2}, // vpermt2w 1097 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1098 }; 1099 1100 if (ST->hasBWI()) 1101 if (const auto *Entry = 1102 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1103 return LT.first * Entry->Cost; 1104 1105 static const CostTblEntry AVX512ShuffleTbl[] = { 1106 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1107 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1108 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1109 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1110 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1111 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1112 1113 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1114 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1115 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1116 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1117 1118 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1119 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1120 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1121 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1122 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1123 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1124 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1125 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1126 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1127 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1128 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1129 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1130 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1131 1132 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1133 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1134 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1135 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1136 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1137 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1138 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1139 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1140 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1141 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1142 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1143 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1144 1145 // FIXME: This just applies the type legalization cost rules above 1146 // assuming these completely split. 1147 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1148 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1149 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1150 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1151 }; 1152 1153 if (ST->hasAVX512()) 1154 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1155 return LT.first * Entry->Cost; 1156 1157 static const CostTblEntry AVX2ShuffleTbl[] = { 1158 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1159 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1160 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1161 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1162 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1163 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1164 1165 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1166 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1167 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1168 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1169 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1170 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1171 1172 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1173 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1174 1175 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1176 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1177 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1178 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1179 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1180 // + vpblendvb 1181 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1182 // + vpblendvb 1183 1184 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1185 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1186 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1187 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1188 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1189 // + vpblendvb 1190 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1191 // + vpblendvb 1192 }; 1193 1194 if (ST->hasAVX2()) 1195 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1196 return LT.first * Entry->Cost; 1197 1198 static const CostTblEntry XOPShuffleTbl[] = { 1199 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1200 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1201 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1202 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1203 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1204 // + vinsertf128 1205 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1206 // + vinsertf128 1207 1208 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1209 // + vinsertf128 1210 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1211 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1212 // + vinsertf128 1213 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1214 }; 1215 1216 if (ST->hasXOP()) 1217 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1218 return LT.first * Entry->Cost; 1219 1220 static const CostTblEntry AVX1ShuffleTbl[] = { 1221 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1222 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1223 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1224 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1225 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1226 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1227 1228 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1229 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1230 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1231 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1232 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1233 // + vinsertf128 1234 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1235 // + vinsertf128 1236 1237 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1238 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1239 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1240 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1241 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1242 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1243 1244 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1245 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1246 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1247 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1248 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1249 // + 2*por + vinsertf128 1250 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1251 // + 2*por + vinsertf128 1252 1253 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1254 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1255 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1256 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1257 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1258 // + 4*por + vinsertf128 1259 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1260 // + 4*por + vinsertf128 1261 }; 1262 1263 if (ST->hasAVX()) 1264 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1265 return LT.first * Entry->Cost; 1266 1267 static const CostTblEntry SSE41ShuffleTbl[] = { 1268 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1269 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1270 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1271 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1272 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1273 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1274 }; 1275 1276 if (ST->hasSSE41()) 1277 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1278 return LT.first * Entry->Cost; 1279 1280 static const CostTblEntry SSSE3ShuffleTbl[] = { 1281 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1282 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1283 1284 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1285 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1286 1287 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1288 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1289 1290 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1291 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1292 1293 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1294 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1295 }; 1296 1297 if (ST->hasSSSE3()) 1298 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1299 return LT.first * Entry->Cost; 1300 1301 static const CostTblEntry SSE2ShuffleTbl[] = { 1302 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1303 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1304 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1305 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1306 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1307 1308 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1309 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1310 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1311 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1312 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1313 // + 2*pshufd + 2*unpck + packus 1314 1315 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1316 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1317 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1318 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1319 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1320 1321 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1322 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1323 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1324 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1325 // + pshufd/unpck 1326 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1327 // + 2*pshufd + 2*unpck + 2*packus 1328 1329 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1330 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1331 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1332 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1333 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1334 }; 1335 1336 if (ST->hasSSE2()) 1337 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1338 return LT.first * Entry->Cost; 1339 1340 static const CostTblEntry SSE1ShuffleTbl[] = { 1341 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1342 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1343 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1344 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1345 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1346 }; 1347 1348 if (ST->hasSSE1()) 1349 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1350 return LT.first * Entry->Cost; 1351 1352 return BaseT::getShuffleCost(Kind, BaseTp, Index, SubTp); 1353 } 1354 1355 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 1356 const Instruction *I) { 1357 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1358 assert(ISD && "Invalid opcode"); 1359 1360 // FIXME: Need a better design of the cost table to handle non-simple types of 1361 // potential massive combinations (elem_num x src_type x dst_type). 1362 1363 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1364 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1365 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1366 1367 // Mask sign extend has an instruction. 1368 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1369 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1370 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1371 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1372 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1373 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1374 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1375 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1376 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1377 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1378 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1379 1380 // Mask zero extend is a sext + shift. 1381 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1382 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1383 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1384 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1385 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1386 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1387 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1388 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1389 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1390 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1391 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1392 1393 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, 1394 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm 1395 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // widen to zmm 1396 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // widen to zmm 1397 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // widen to zmm 1398 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // widen to zmm 1399 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // widen to zmm 1400 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // widen to zmm 1401 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // widen to zmm 1402 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // widen to zmm 1403 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // widen to zmm 1404 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, 1405 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, 1406 }; 1407 1408 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1409 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1410 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1411 1412 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1413 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1414 1415 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1416 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1417 1418 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1419 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1420 }; 1421 1422 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1423 // 256-bit wide vectors. 1424 1425 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1426 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1427 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1428 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1429 1430 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1431 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1432 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1433 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd 1434 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1435 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1436 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1437 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd 1438 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd 1439 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd 1440 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd 1441 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd 1442 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq 1443 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq 1444 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq 1445 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, 1446 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, 1447 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, 1448 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, 1449 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 1450 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd 1451 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb 1452 1453 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32 1454 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, 1455 1456 // Sign extend is zmm vpternlogd+vptruncdb. 1457 // Zero extend is zmm broadcast load+vptruncdw. 1458 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 }, 1459 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 }, 1460 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, 1461 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, 1462 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, 1463 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, 1464 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 }, 1465 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 }, 1466 1467 // Sign extend is zmm vpternlogd+vptruncdw. 1468 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw. 1469 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 }, 1470 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1471 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 }, 1472 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1473 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 }, 1474 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1475 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 }, 1476 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1477 1478 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd 1479 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld 1480 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd 1481 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld 1482 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd 1483 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld 1484 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq 1485 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq 1486 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq 1487 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq 1488 1489 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd 1490 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld 1491 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq 1492 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq 1493 1494 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1495 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1496 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1497 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1498 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1499 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1500 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1501 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1502 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1503 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1504 1505 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1506 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1507 1508 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1509 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1510 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1511 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1512 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1513 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1514 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1515 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1516 1517 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1518 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1519 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1520 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1521 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1522 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1523 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1524 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1525 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1526 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1527 1528 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f64, 3 }, 1529 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, 1530 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 3 }, 1531 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 3 }, 1532 1533 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1534 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, 1535 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, 1536 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1537 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, 1538 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, 1539 }; 1540 1541 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1542 // Mask sign extend has an instruction. 1543 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1544 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1545 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1546 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1547 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1548 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1549 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1550 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1551 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1552 1553 // Mask zero extend is a sext + shift. 1554 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1555 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1556 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1557 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1558 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1559 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1560 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1561 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1562 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1563 1564 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, 1565 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // vpsllw+vptestmb 1566 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // vpsllw+vptestmw 1567 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // vpsllw+vptestmb 1568 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // vpsllw+vptestmw 1569 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // vpsllw+vptestmb 1570 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // vpsllw+vptestmw 1571 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // vpsllw+vptestmb 1572 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // vpsllw+vptestmw 1573 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // vpsllw+vptestmb 1574 }; 1575 1576 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1577 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1578 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1579 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1580 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1581 1582 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1583 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1584 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1585 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1586 1587 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1588 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1589 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1590 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1591 1592 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1593 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1594 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1595 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1596 }; 1597 1598 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 1599 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1600 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1601 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1602 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 8 }, // split+2*v8i8 1603 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1604 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1605 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1606 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16 1607 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // vpslld+vptestmd 1608 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd 1609 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // vpslld+vptestmd 1610 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // vpsllq+vptestmq 1611 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // vpsllq+vptestmq 1612 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // vpmovqd 1613 1614 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb 1615 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb 1616 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 }, 1617 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 }, 1618 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 }, 1619 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 }, 1620 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 }, 1621 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 }, 1622 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 }, 1623 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 }, 1624 1625 // sign extend is vpcmpeq+maskedmove+vpmovdw 1626 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw 1627 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1628 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 }, 1629 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1630 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 }, 1631 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1632 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 }, 1633 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 }, 1634 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 }, 1635 1636 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd 1637 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld 1638 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd 1639 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld 1640 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd 1641 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld 1642 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq 1643 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq 1644 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq 1645 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq 1646 1647 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1648 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1649 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1650 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1651 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1652 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1653 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1654 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1655 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1656 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1657 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1658 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1659 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1660 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1661 1662 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 1663 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1664 1665 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 3 }, 1666 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 3 }, 1667 1668 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 1669 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 1670 1671 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1672 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1673 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 1 }, 1674 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1675 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1676 }; 1677 1678 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1679 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1680 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1681 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1682 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1683 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1684 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1685 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1686 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1687 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1688 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1689 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1690 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1691 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1692 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1693 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1694 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1695 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1696 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1697 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1698 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1699 1700 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1701 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1702 1703 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 1704 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 1705 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 1706 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1707 1708 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1709 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1710 1711 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1712 }; 1713 1714 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1715 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1716 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1717 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1718 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1719 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1720 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1721 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1722 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1723 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1724 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1725 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1726 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1727 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 4 }, 1728 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1729 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1730 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1731 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1732 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1733 1734 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 4 }, 1735 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 5 }, 1736 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 4 }, 1737 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 9 }, 1738 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, 11 }, 1739 1740 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 1741 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1742 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1743 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1744 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 1745 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1746 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 11 }, 1747 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 9 }, 1748 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 }, 1749 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 11 }, 1750 1751 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1752 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1753 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1754 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1755 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1756 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1757 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1758 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1759 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1760 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1761 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1762 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1763 1764 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1765 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1766 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1767 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1768 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1769 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1770 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1771 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1772 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1773 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 }, 1774 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 1775 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1776 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 1777 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1778 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1779 // The generic code to compute the scalar overhead is currently broken. 1780 // Workaround this limitation by estimating the scalarization overhead 1781 // here. We have roughly 10 instructions per scalar element. 1782 // Multiply that by the vector width. 1783 // FIXME: remove that when PR19268 is fixed. 1784 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1785 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1786 1787 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 4 }, 1788 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f64, 3 }, 1789 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f64, 2 }, 1790 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 3 }, 1791 1792 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f64, 3 }, 1793 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f64, 2 }, 1794 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 4 }, 1795 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 3 }, 1796 // This node is expanded into scalarized operations but BasicTTI is overly 1797 // optimistic estimating its cost. It computes 3 per element (one 1798 // vector-extract, one scalar conversion and one vector-insert). The 1799 // problem is that the inserts form a read-modify-write chain so latency 1800 // should be factored in too. Inflating the cost per element by 1. 1801 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, 1802 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 1803 1804 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 1805 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 1806 }; 1807 1808 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 1809 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1810 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1811 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1812 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1813 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1814 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1815 1816 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1817 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 }, 1818 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1819 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1820 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1821 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1822 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1823 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1824 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1825 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1826 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1827 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1828 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1829 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1830 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1831 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1832 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1833 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1834 1835 // These truncates end up widening elements. 1836 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 1 }, // PMOVXZBQ 1837 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 1 }, // PMOVXZWQ 1838 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 1 }, // PMOVXZBD 1839 1840 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 1 }, 1841 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 1 }, 1842 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 1843 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 1844 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 1845 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 1846 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 1847 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 1848 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 1 }, // PSHUFB 1849 1850 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 1851 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 1852 1853 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 3 }, 1854 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 3 }, 1855 1856 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 3 }, 1857 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 3 }, 1858 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, 1859 }; 1860 1861 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 1862 // These are somewhat magic numbers justified by looking at the output of 1863 // Intel's IACA, running some kernels and making sure when we take 1864 // legalization into account the throughput will be overestimated. 1865 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1866 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1867 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1868 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1869 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1870 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 2*10 }, 1871 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2*10 }, 1872 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1873 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 1874 1875 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1876 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1877 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1878 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1879 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1880 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, 1881 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 }, 1882 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1883 1884 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 4 }, 1885 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 2 }, 1886 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, 1887 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, 1888 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, 1889 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 4 }, 1890 1891 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 1 }, 1892 1893 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 6 }, 1894 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 }, 1895 1896 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 1897 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 1898 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 4 }, 1899 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 4 }, 1900 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 }, 1901 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 2 }, 1902 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 }, 1903 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 4 }, 1904 1905 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1906 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 1907 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 1908 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 1909 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1910 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 1911 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1912 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 1913 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1914 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1915 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1916 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1917 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 1918 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 1919 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1920 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 1921 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1922 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 1923 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1924 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1925 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 1926 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 1927 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1928 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 1929 1930 // These truncates are really widening elements. 1931 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 1 }, // PSHUFD 1932 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // PUNPCKLWD+DQ 1933 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // PUNPCKLBW+WD+PSHUFD 1934 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 1 }, // PUNPCKLWD 1935 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // PUNPCKLBW+WD 1936 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 1 }, // PUNPCKLBW 1937 1938 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // PAND+PACKUSWB 1939 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // PAND+PACKUSWB 1940 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // PAND+PACKUSWB 1941 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 1942 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 3 }, // PAND+2*PACKUSWB 1943 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 1944 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 1945 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 1946 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1947 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 1948 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1949 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 1950 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 1951 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 1952 { ISD::TRUNCATE, MVT::v2i32, MVT::v2i64, 1 }, // PSHUFD 1953 }; 1954 1955 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 1956 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst); 1957 1958 if (ST->hasSSE2() && !ST->hasAVX()) { 1959 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1960 LTDest.second, LTSrc.second)) 1961 return LTSrc.first * Entry->Cost; 1962 } 1963 1964 EVT SrcTy = TLI->getValueType(DL, Src); 1965 EVT DstTy = TLI->getValueType(DL, Dst); 1966 1967 // The function getSimpleVT only handles simple value types. 1968 if (!SrcTy.isSimple() || !DstTy.isSimple()) 1969 return BaseT::getCastInstrCost(Opcode, Dst, Src); 1970 1971 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 1972 MVT SimpleDstTy = DstTy.getSimpleVT(); 1973 1974 if (ST->useAVX512Regs()) { 1975 if (ST->hasBWI()) 1976 if (const auto *Entry = ConvertCostTableLookup(AVX512BWConversionTbl, ISD, 1977 SimpleDstTy, SimpleSrcTy)) 1978 return Entry->Cost; 1979 1980 if (ST->hasDQI()) 1981 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 1982 SimpleDstTy, SimpleSrcTy)) 1983 return Entry->Cost; 1984 1985 if (ST->hasAVX512()) 1986 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 1987 SimpleDstTy, SimpleSrcTy)) 1988 return Entry->Cost; 1989 } 1990 1991 if (ST->hasBWI()) 1992 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 1993 SimpleDstTy, SimpleSrcTy)) 1994 return Entry->Cost; 1995 1996 if (ST->hasDQI()) 1997 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 1998 SimpleDstTy, SimpleSrcTy)) 1999 return Entry->Cost; 2000 2001 if (ST->hasAVX512()) 2002 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2003 SimpleDstTy, SimpleSrcTy)) 2004 return Entry->Cost; 2005 2006 if (ST->hasAVX2()) { 2007 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2008 SimpleDstTy, SimpleSrcTy)) 2009 return Entry->Cost; 2010 } 2011 2012 if (ST->hasAVX()) { 2013 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2014 SimpleDstTy, SimpleSrcTy)) 2015 return Entry->Cost; 2016 } 2017 2018 if (ST->hasSSE41()) { 2019 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2020 SimpleDstTy, SimpleSrcTy)) 2021 return Entry->Cost; 2022 } 2023 2024 if (ST->hasSSE2()) { 2025 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2026 SimpleDstTy, SimpleSrcTy)) 2027 return Entry->Cost; 2028 } 2029 2030 return BaseT::getCastInstrCost(Opcode, Dst, Src, I); 2031 } 2032 2033 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 2034 const Instruction *I) { 2035 // Legalize the type. 2036 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2037 2038 MVT MTy = LT.second; 2039 2040 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2041 assert(ISD && "Invalid opcode"); 2042 2043 unsigned ExtraCost = 0; 2044 if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) { 2045 // Some vector comparison predicates cost extra instructions. 2046 if (MTy.isVector() && 2047 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 2048 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 2049 ST->hasBWI())) { 2050 switch (cast<CmpInst>(I)->getPredicate()) { 2051 case CmpInst::Predicate::ICMP_NE: 2052 // xor(cmpeq(x,y),-1) 2053 ExtraCost = 1; 2054 break; 2055 case CmpInst::Predicate::ICMP_SGE: 2056 case CmpInst::Predicate::ICMP_SLE: 2057 // xor(cmpgt(x,y),-1) 2058 ExtraCost = 1; 2059 break; 2060 case CmpInst::Predicate::ICMP_ULT: 2061 case CmpInst::Predicate::ICMP_UGT: 2062 // cmpgt(xor(x,signbit),xor(y,signbit)) 2063 // xor(cmpeq(pmaxu(x,y),x),-1) 2064 ExtraCost = 2; 2065 break; 2066 case CmpInst::Predicate::ICMP_ULE: 2067 case CmpInst::Predicate::ICMP_UGE: 2068 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 2069 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 2070 // cmpeq(psubus(x,y),0) 2071 // cmpeq(pminu(x,y),x) 2072 ExtraCost = 1; 2073 } else { 2074 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 2075 ExtraCost = 3; 2076 } 2077 break; 2078 default: 2079 break; 2080 } 2081 } 2082 } 2083 2084 static const CostTblEntry SLMCostTbl[] = { 2085 // slm pcmpeq/pcmpgt throughput is 2 2086 { ISD::SETCC, MVT::v2i64, 2 }, 2087 }; 2088 2089 static const CostTblEntry AVX512BWCostTbl[] = { 2090 { ISD::SETCC, MVT::v32i16, 1 }, 2091 { ISD::SETCC, MVT::v64i8, 1 }, 2092 2093 { ISD::SELECT, MVT::v32i16, 1 }, 2094 { ISD::SELECT, MVT::v64i8, 1 }, 2095 }; 2096 2097 static const CostTblEntry AVX512CostTbl[] = { 2098 { ISD::SETCC, MVT::v8i64, 1 }, 2099 { ISD::SETCC, MVT::v16i32, 1 }, 2100 { ISD::SETCC, MVT::v8f64, 1 }, 2101 { ISD::SETCC, MVT::v16f32, 1 }, 2102 2103 { ISD::SELECT, MVT::v8i64, 1 }, 2104 { ISD::SELECT, MVT::v16i32, 1 }, 2105 { ISD::SELECT, MVT::v8f64, 1 }, 2106 { ISD::SELECT, MVT::v16f32, 1 }, 2107 2108 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 2109 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 2110 2111 { ISD::SELECT, MVT::v32i16, 2 }, // FIXME: should be 3 2112 { ISD::SELECT, MVT::v64i8, 2 }, // FIXME: should be 3 2113 }; 2114 2115 static const CostTblEntry AVX2CostTbl[] = { 2116 { ISD::SETCC, MVT::v4i64, 1 }, 2117 { ISD::SETCC, MVT::v8i32, 1 }, 2118 { ISD::SETCC, MVT::v16i16, 1 }, 2119 { ISD::SETCC, MVT::v32i8, 1 }, 2120 2121 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 2122 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 2123 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 2124 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 2125 }; 2126 2127 static const CostTblEntry AVX1CostTbl[] = { 2128 { ISD::SETCC, MVT::v4f64, 1 }, 2129 { ISD::SETCC, MVT::v8f32, 1 }, 2130 // AVX1 does not support 8-wide integer compare. 2131 { ISD::SETCC, MVT::v4i64, 4 }, 2132 { ISD::SETCC, MVT::v8i32, 4 }, 2133 { ISD::SETCC, MVT::v16i16, 4 }, 2134 { ISD::SETCC, MVT::v32i8, 4 }, 2135 2136 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 2137 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 2138 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 2139 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 2140 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 2141 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 2142 }; 2143 2144 static const CostTblEntry SSE42CostTbl[] = { 2145 { ISD::SETCC, MVT::v2f64, 1 }, 2146 { ISD::SETCC, MVT::v4f32, 1 }, 2147 { ISD::SETCC, MVT::v2i64, 1 }, 2148 }; 2149 2150 static const CostTblEntry SSE41CostTbl[] = { 2151 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 2152 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 2153 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 2154 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 2155 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 2156 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 2157 }; 2158 2159 static const CostTblEntry SSE2CostTbl[] = { 2160 { ISD::SETCC, MVT::v2f64, 2 }, 2161 { ISD::SETCC, MVT::f64, 1 }, 2162 { ISD::SETCC, MVT::v2i64, 8 }, 2163 { ISD::SETCC, MVT::v4i32, 1 }, 2164 { ISD::SETCC, MVT::v8i16, 1 }, 2165 { ISD::SETCC, MVT::v16i8, 1 }, 2166 2167 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 2168 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 2169 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 2170 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 2171 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 2172 }; 2173 2174 static const CostTblEntry SSE1CostTbl[] = { 2175 { ISD::SETCC, MVT::v4f32, 2 }, 2176 { ISD::SETCC, MVT::f32, 1 }, 2177 2178 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 2179 }; 2180 2181 if (ST->isSLM()) 2182 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2183 return LT.first * (ExtraCost + Entry->Cost); 2184 2185 if (ST->hasBWI()) 2186 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2187 return LT.first * (ExtraCost + Entry->Cost); 2188 2189 if (ST->hasAVX512()) 2190 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2191 return LT.first * (ExtraCost + Entry->Cost); 2192 2193 if (ST->hasAVX2()) 2194 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2195 return LT.first * (ExtraCost + Entry->Cost); 2196 2197 if (ST->hasAVX()) 2198 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2199 return LT.first * (ExtraCost + Entry->Cost); 2200 2201 if (ST->hasSSE42()) 2202 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2203 return LT.first * (ExtraCost + Entry->Cost); 2204 2205 if (ST->hasSSE41()) 2206 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2207 return LT.first * (ExtraCost + Entry->Cost); 2208 2209 if (ST->hasSSE2()) 2210 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2211 return LT.first * (ExtraCost + Entry->Cost); 2212 2213 if (ST->hasSSE1()) 2214 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2215 return LT.first * (ExtraCost + Entry->Cost); 2216 2217 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I); 2218 } 2219 2220 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2221 2222 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 2223 ArrayRef<Type *> Tys, FastMathFlags FMF, 2224 unsigned ScalarizationCostPassed, 2225 const Instruction *I) { 2226 // Costs should match the codegen from: 2227 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2228 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2229 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2230 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2231 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2232 static const CostTblEntry AVX512CDCostTbl[] = { 2233 { ISD::CTLZ, MVT::v8i64, 1 }, 2234 { ISD::CTLZ, MVT::v16i32, 1 }, 2235 { ISD::CTLZ, MVT::v32i16, 8 }, 2236 { ISD::CTLZ, MVT::v64i8, 20 }, 2237 { ISD::CTLZ, MVT::v4i64, 1 }, 2238 { ISD::CTLZ, MVT::v8i32, 1 }, 2239 { ISD::CTLZ, MVT::v16i16, 4 }, 2240 { ISD::CTLZ, MVT::v32i8, 10 }, 2241 { ISD::CTLZ, MVT::v2i64, 1 }, 2242 { ISD::CTLZ, MVT::v4i32, 1 }, 2243 { ISD::CTLZ, MVT::v8i16, 4 }, 2244 { ISD::CTLZ, MVT::v16i8, 4 }, 2245 }; 2246 static const CostTblEntry AVX512BWCostTbl[] = { 2247 { ISD::BITREVERSE, MVT::v8i64, 5 }, 2248 { ISD::BITREVERSE, MVT::v16i32, 5 }, 2249 { ISD::BITREVERSE, MVT::v32i16, 5 }, 2250 { ISD::BITREVERSE, MVT::v64i8, 5 }, 2251 { ISD::CTLZ, MVT::v8i64, 23 }, 2252 { ISD::CTLZ, MVT::v16i32, 22 }, 2253 { ISD::CTLZ, MVT::v32i16, 18 }, 2254 { ISD::CTLZ, MVT::v64i8, 17 }, 2255 { ISD::CTPOP, MVT::v8i64, 7 }, 2256 { ISD::CTPOP, MVT::v16i32, 11 }, 2257 { ISD::CTPOP, MVT::v32i16, 9 }, 2258 { ISD::CTPOP, MVT::v64i8, 6 }, 2259 { ISD::CTTZ, MVT::v8i64, 10 }, 2260 { ISD::CTTZ, MVT::v16i32, 14 }, 2261 { ISD::CTTZ, MVT::v32i16, 12 }, 2262 { ISD::CTTZ, MVT::v64i8, 9 }, 2263 { ISD::SADDSAT, MVT::v32i16, 1 }, 2264 { ISD::SADDSAT, MVT::v64i8, 1 }, 2265 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2266 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2267 { ISD::UADDSAT, MVT::v32i16, 1 }, 2268 { ISD::UADDSAT, MVT::v64i8, 1 }, 2269 { ISD::USUBSAT, MVT::v32i16, 1 }, 2270 { ISD::USUBSAT, MVT::v64i8, 1 }, 2271 }; 2272 static const CostTblEntry AVX512CostTbl[] = { 2273 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2274 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2275 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2276 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2277 { ISD::CTLZ, MVT::v8i64, 29 }, 2278 { ISD::CTLZ, MVT::v16i32, 35 }, 2279 { ISD::CTLZ, MVT::v32i16, 28 }, 2280 { ISD::CTLZ, MVT::v64i8, 18 }, 2281 { ISD::CTPOP, MVT::v8i64, 16 }, 2282 { ISD::CTPOP, MVT::v16i32, 24 }, 2283 { ISD::CTPOP, MVT::v32i16, 18 }, 2284 { ISD::CTPOP, MVT::v64i8, 12 }, 2285 { ISD::CTTZ, MVT::v8i64, 20 }, 2286 { ISD::CTTZ, MVT::v16i32, 28 }, 2287 { ISD::CTTZ, MVT::v32i16, 24 }, 2288 { ISD::CTTZ, MVT::v64i8, 18 }, 2289 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2290 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2291 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2292 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2293 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2294 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2295 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2296 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2297 { ISD::SADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2298 { ISD::SADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2299 { ISD::SSUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2300 { ISD::SSUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2301 { ISD::UADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2302 { ISD::UADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2303 { ISD::USUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2304 { ISD::USUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2305 { ISD::FMAXNUM, MVT::f32, 2 }, 2306 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2307 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2308 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2309 { ISD::FMAXNUM, MVT::f64, 2 }, 2310 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2311 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2312 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2313 }; 2314 static const CostTblEntry XOPCostTbl[] = { 2315 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2316 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2317 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2318 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2319 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2320 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2321 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2322 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2323 { ISD::BITREVERSE, MVT::i64, 3 }, 2324 { ISD::BITREVERSE, MVT::i32, 3 }, 2325 { ISD::BITREVERSE, MVT::i16, 3 }, 2326 { ISD::BITREVERSE, MVT::i8, 3 } 2327 }; 2328 static const CostTblEntry AVX2CostTbl[] = { 2329 { ISD::BITREVERSE, MVT::v4i64, 5 }, 2330 { ISD::BITREVERSE, MVT::v8i32, 5 }, 2331 { ISD::BITREVERSE, MVT::v16i16, 5 }, 2332 { ISD::BITREVERSE, MVT::v32i8, 5 }, 2333 { ISD::BSWAP, MVT::v4i64, 1 }, 2334 { ISD::BSWAP, MVT::v8i32, 1 }, 2335 { ISD::BSWAP, MVT::v16i16, 1 }, 2336 { ISD::CTLZ, MVT::v4i64, 23 }, 2337 { ISD::CTLZ, MVT::v8i32, 18 }, 2338 { ISD::CTLZ, MVT::v16i16, 14 }, 2339 { ISD::CTLZ, MVT::v32i8, 9 }, 2340 { ISD::CTPOP, MVT::v4i64, 7 }, 2341 { ISD::CTPOP, MVT::v8i32, 11 }, 2342 { ISD::CTPOP, MVT::v16i16, 9 }, 2343 { ISD::CTPOP, MVT::v32i8, 6 }, 2344 { ISD::CTTZ, MVT::v4i64, 10 }, 2345 { ISD::CTTZ, MVT::v8i32, 14 }, 2346 { ISD::CTTZ, MVT::v16i16, 12 }, 2347 { ISD::CTTZ, MVT::v32i8, 9 }, 2348 { ISD::SADDSAT, MVT::v16i16, 1 }, 2349 { ISD::SADDSAT, MVT::v32i8, 1 }, 2350 { ISD::SSUBSAT, MVT::v16i16, 1 }, 2351 { ISD::SSUBSAT, MVT::v32i8, 1 }, 2352 { ISD::UADDSAT, MVT::v16i16, 1 }, 2353 { ISD::UADDSAT, MVT::v32i8, 1 }, 2354 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 2355 { ISD::USUBSAT, MVT::v16i16, 1 }, 2356 { ISD::USUBSAT, MVT::v32i8, 1 }, 2357 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2358 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2359 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2360 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2361 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2362 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2363 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2364 }; 2365 static const CostTblEntry AVX1CostTbl[] = { 2366 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 2367 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 2368 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 2369 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 2370 { ISD::BSWAP, MVT::v4i64, 4 }, 2371 { ISD::BSWAP, MVT::v8i32, 4 }, 2372 { ISD::BSWAP, MVT::v16i16, 4 }, 2373 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 2374 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 2375 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 2376 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2377 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 2378 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 2379 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 2380 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 2381 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 2382 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 2383 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 2384 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2385 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2386 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2387 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2388 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2389 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2390 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2391 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 2392 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2393 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2394 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 2395 { ISD::FMAXNUM, MVT::f32, 3 }, 2396 { ISD::FMAXNUM, MVT::v4f32, 3 }, 2397 { ISD::FMAXNUM, MVT::v8f32, 5 }, 2398 { ISD::FMAXNUM, MVT::f64, 3 }, 2399 { ISD::FMAXNUM, MVT::v2f64, 3 }, 2400 { ISD::FMAXNUM, MVT::v4f64, 5 }, 2401 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 2402 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 2403 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 2404 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 2405 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 2406 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 2407 }; 2408 static const CostTblEntry GLMCostTbl[] = { 2409 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 2410 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 2411 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 2412 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 2413 }; 2414 static const CostTblEntry SLMCostTbl[] = { 2415 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 2416 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 2417 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 2418 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 2419 }; 2420 static const CostTblEntry SSE42CostTbl[] = { 2421 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 2422 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 2423 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 2424 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 2425 }; 2426 static const CostTblEntry SSSE3CostTbl[] = { 2427 { ISD::BITREVERSE, MVT::v2i64, 5 }, 2428 { ISD::BITREVERSE, MVT::v4i32, 5 }, 2429 { ISD::BITREVERSE, MVT::v8i16, 5 }, 2430 { ISD::BITREVERSE, MVT::v16i8, 5 }, 2431 { ISD::BSWAP, MVT::v2i64, 1 }, 2432 { ISD::BSWAP, MVT::v4i32, 1 }, 2433 { ISD::BSWAP, MVT::v8i16, 1 }, 2434 { ISD::CTLZ, MVT::v2i64, 23 }, 2435 { ISD::CTLZ, MVT::v4i32, 18 }, 2436 { ISD::CTLZ, MVT::v8i16, 14 }, 2437 { ISD::CTLZ, MVT::v16i8, 9 }, 2438 { ISD::CTPOP, MVT::v2i64, 7 }, 2439 { ISD::CTPOP, MVT::v4i32, 11 }, 2440 { ISD::CTPOP, MVT::v8i16, 9 }, 2441 { ISD::CTPOP, MVT::v16i8, 6 }, 2442 { ISD::CTTZ, MVT::v2i64, 10 }, 2443 { ISD::CTTZ, MVT::v4i32, 14 }, 2444 { ISD::CTTZ, MVT::v8i16, 12 }, 2445 { ISD::CTTZ, MVT::v16i8, 9 } 2446 }; 2447 static const CostTblEntry SSE2CostTbl[] = { 2448 { ISD::BITREVERSE, MVT::v2i64, 29 }, 2449 { ISD::BITREVERSE, MVT::v4i32, 27 }, 2450 { ISD::BITREVERSE, MVT::v8i16, 27 }, 2451 { ISD::BITREVERSE, MVT::v16i8, 20 }, 2452 { ISD::BSWAP, MVT::v2i64, 7 }, 2453 { ISD::BSWAP, MVT::v4i32, 7 }, 2454 { ISD::BSWAP, MVT::v8i16, 7 }, 2455 { ISD::CTLZ, MVT::v2i64, 25 }, 2456 { ISD::CTLZ, MVT::v4i32, 26 }, 2457 { ISD::CTLZ, MVT::v8i16, 20 }, 2458 { ISD::CTLZ, MVT::v16i8, 17 }, 2459 { ISD::CTPOP, MVT::v2i64, 12 }, 2460 { ISD::CTPOP, MVT::v4i32, 15 }, 2461 { ISD::CTPOP, MVT::v8i16, 13 }, 2462 { ISD::CTPOP, MVT::v16i8, 10 }, 2463 { ISD::CTTZ, MVT::v2i64, 14 }, 2464 { ISD::CTTZ, MVT::v4i32, 18 }, 2465 { ISD::CTTZ, MVT::v8i16, 16 }, 2466 { ISD::CTTZ, MVT::v16i8, 13 }, 2467 { ISD::SADDSAT, MVT::v8i16, 1 }, 2468 { ISD::SADDSAT, MVT::v16i8, 1 }, 2469 { ISD::SSUBSAT, MVT::v8i16, 1 }, 2470 { ISD::SSUBSAT, MVT::v16i8, 1 }, 2471 { ISD::UADDSAT, MVT::v8i16, 1 }, 2472 { ISD::UADDSAT, MVT::v16i8, 1 }, 2473 { ISD::USUBSAT, MVT::v8i16, 1 }, 2474 { ISD::USUBSAT, MVT::v16i8, 1 }, 2475 { ISD::FMAXNUM, MVT::f64, 4 }, 2476 { ISD::FMAXNUM, MVT::v2f64, 4 }, 2477 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 2478 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 2479 }; 2480 static const CostTblEntry SSE1CostTbl[] = { 2481 { ISD::FMAXNUM, MVT::f32, 4 }, 2482 { ISD::FMAXNUM, MVT::v4f32, 4 }, 2483 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 2484 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 2485 }; 2486 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 2487 { ISD::CTTZ, MVT::i64, 1 }, 2488 }; 2489 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 2490 { ISD::CTTZ, MVT::i32, 1 }, 2491 { ISD::CTTZ, MVT::i16, 1 }, 2492 { ISD::CTTZ, MVT::i8, 1 }, 2493 }; 2494 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 2495 { ISD::CTLZ, MVT::i64, 1 }, 2496 }; 2497 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 2498 { ISD::CTLZ, MVT::i32, 1 }, 2499 { ISD::CTLZ, MVT::i16, 1 }, 2500 { ISD::CTLZ, MVT::i8, 1 }, 2501 }; 2502 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 2503 { ISD::CTPOP, MVT::i64, 1 }, 2504 }; 2505 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 2506 { ISD::CTPOP, MVT::i32, 1 }, 2507 { ISD::CTPOP, MVT::i16, 1 }, 2508 { ISD::CTPOP, MVT::i8, 1 }, 2509 }; 2510 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2511 { ISD::BITREVERSE, MVT::i64, 14 }, 2512 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 2513 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 2514 { ISD::CTPOP, MVT::i64, 10 }, 2515 { ISD::SADDO, MVT::i64, 1 }, 2516 { ISD::UADDO, MVT::i64, 1 }, 2517 }; 2518 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2519 { ISD::BITREVERSE, MVT::i32, 14 }, 2520 { ISD::BITREVERSE, MVT::i16, 14 }, 2521 { ISD::BITREVERSE, MVT::i8, 11 }, 2522 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 2523 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 2524 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 2525 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 2526 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 2527 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 2528 { ISD::CTPOP, MVT::i32, 8 }, 2529 { ISD::CTPOP, MVT::i16, 9 }, 2530 { ISD::CTPOP, MVT::i8, 7 }, 2531 { ISD::SADDO, MVT::i32, 1 }, 2532 { ISD::SADDO, MVT::i16, 1 }, 2533 { ISD::SADDO, MVT::i8, 1 }, 2534 { ISD::UADDO, MVT::i32, 1 }, 2535 { ISD::UADDO, MVT::i16, 1 }, 2536 { ISD::UADDO, MVT::i8, 1 }, 2537 }; 2538 2539 Type *OpTy = RetTy; 2540 unsigned ISD = ISD::DELETED_NODE; 2541 switch (IID) { 2542 default: 2543 break; 2544 case Intrinsic::bitreverse: 2545 ISD = ISD::BITREVERSE; 2546 break; 2547 case Intrinsic::bswap: 2548 ISD = ISD::BSWAP; 2549 break; 2550 case Intrinsic::ctlz: 2551 ISD = ISD::CTLZ; 2552 break; 2553 case Intrinsic::ctpop: 2554 ISD = ISD::CTPOP; 2555 break; 2556 case Intrinsic::cttz: 2557 ISD = ISD::CTTZ; 2558 break; 2559 case Intrinsic::maxnum: 2560 case Intrinsic::minnum: 2561 // FMINNUM has same costs so don't duplicate. 2562 ISD = ISD::FMAXNUM; 2563 break; 2564 case Intrinsic::sadd_sat: 2565 ISD = ISD::SADDSAT; 2566 break; 2567 case Intrinsic::ssub_sat: 2568 ISD = ISD::SSUBSAT; 2569 break; 2570 case Intrinsic::uadd_sat: 2571 ISD = ISD::UADDSAT; 2572 break; 2573 case Intrinsic::usub_sat: 2574 ISD = ISD::USUBSAT; 2575 break; 2576 case Intrinsic::sqrt: 2577 ISD = ISD::FSQRT; 2578 break; 2579 case Intrinsic::sadd_with_overflow: 2580 case Intrinsic::ssub_with_overflow: 2581 // SSUBO has same costs so don't duplicate. 2582 ISD = ISD::SADDO; 2583 OpTy = RetTy->getContainedType(0); 2584 break; 2585 case Intrinsic::uadd_with_overflow: 2586 case Intrinsic::usub_with_overflow: 2587 // USUBO has same costs so don't duplicate. 2588 ISD = ISD::UADDO; 2589 OpTy = RetTy->getContainedType(0); 2590 break; 2591 } 2592 2593 if (ISD != ISD::DELETED_NODE) { 2594 // Legalize the type. 2595 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 2596 MVT MTy = LT.second; 2597 2598 // Attempt to lookup cost. 2599 if (ST->useGLMDivSqrtCosts()) 2600 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 2601 return LT.first * Entry->Cost; 2602 2603 if (ST->isSLM()) 2604 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2605 return LT.first * Entry->Cost; 2606 2607 if (ST->hasCDI()) 2608 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 2609 return LT.first * Entry->Cost; 2610 2611 if (ST->hasBWI()) 2612 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2613 return LT.first * Entry->Cost; 2614 2615 if (ST->hasAVX512()) 2616 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2617 return LT.first * Entry->Cost; 2618 2619 if (ST->hasXOP()) 2620 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2621 return LT.first * Entry->Cost; 2622 2623 if (ST->hasAVX2()) 2624 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2625 return LT.first * Entry->Cost; 2626 2627 if (ST->hasAVX()) 2628 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2629 return LT.first * Entry->Cost; 2630 2631 if (ST->hasSSE42()) 2632 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2633 return LT.first * Entry->Cost; 2634 2635 if (ST->hasSSSE3()) 2636 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 2637 return LT.first * Entry->Cost; 2638 2639 if (ST->hasSSE2()) 2640 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2641 return LT.first * Entry->Cost; 2642 2643 if (ST->hasSSE1()) 2644 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2645 return LT.first * Entry->Cost; 2646 2647 if (ST->hasBMI()) { 2648 if (ST->is64Bit()) 2649 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 2650 return LT.first * Entry->Cost; 2651 2652 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 2653 return LT.first * Entry->Cost; 2654 } 2655 2656 if (ST->hasLZCNT()) { 2657 if (ST->is64Bit()) 2658 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 2659 return LT.first * Entry->Cost; 2660 2661 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 2662 return LT.first * Entry->Cost; 2663 } 2664 2665 if (ST->hasPOPCNT()) { 2666 if (ST->is64Bit()) 2667 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 2668 return LT.first * Entry->Cost; 2669 2670 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 2671 return LT.first * Entry->Cost; 2672 } 2673 2674 // TODO - add BMI (TZCNT) scalar handling 2675 2676 if (ST->is64Bit()) 2677 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2678 return LT.first * Entry->Cost; 2679 2680 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2681 return LT.first * Entry->Cost; 2682 } 2683 2684 return BaseT::getIntrinsicInstrCost(IID, RetTy, Tys, FMF, 2685 ScalarizationCostPassed, I); 2686 } 2687 2688 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 2689 ArrayRef<Value *> Args, FastMathFlags FMF, 2690 unsigned VF, const Instruction *I) { 2691 static const CostTblEntry AVX512CostTbl[] = { 2692 { ISD::ROTL, MVT::v8i64, 1 }, 2693 { ISD::ROTL, MVT::v4i64, 1 }, 2694 { ISD::ROTL, MVT::v2i64, 1 }, 2695 { ISD::ROTL, MVT::v16i32, 1 }, 2696 { ISD::ROTL, MVT::v8i32, 1 }, 2697 { ISD::ROTL, MVT::v4i32, 1 }, 2698 { ISD::ROTR, MVT::v8i64, 1 }, 2699 { ISD::ROTR, MVT::v4i64, 1 }, 2700 { ISD::ROTR, MVT::v2i64, 1 }, 2701 { ISD::ROTR, MVT::v16i32, 1 }, 2702 { ISD::ROTR, MVT::v8i32, 1 }, 2703 { ISD::ROTR, MVT::v4i32, 1 } 2704 }; 2705 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 2706 static const CostTblEntry XOPCostTbl[] = { 2707 { ISD::ROTL, MVT::v4i64, 4 }, 2708 { ISD::ROTL, MVT::v8i32, 4 }, 2709 { ISD::ROTL, MVT::v16i16, 4 }, 2710 { ISD::ROTL, MVT::v32i8, 4 }, 2711 { ISD::ROTL, MVT::v2i64, 1 }, 2712 { ISD::ROTL, MVT::v4i32, 1 }, 2713 { ISD::ROTL, MVT::v8i16, 1 }, 2714 { ISD::ROTL, MVT::v16i8, 1 }, 2715 { ISD::ROTR, MVT::v4i64, 6 }, 2716 { ISD::ROTR, MVT::v8i32, 6 }, 2717 { ISD::ROTR, MVT::v16i16, 6 }, 2718 { ISD::ROTR, MVT::v32i8, 6 }, 2719 { ISD::ROTR, MVT::v2i64, 2 }, 2720 { ISD::ROTR, MVT::v4i32, 2 }, 2721 { ISD::ROTR, MVT::v8i16, 2 }, 2722 { ISD::ROTR, MVT::v16i8, 2 } 2723 }; 2724 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2725 { ISD::ROTL, MVT::i64, 1 }, 2726 { ISD::ROTR, MVT::i64, 1 }, 2727 { ISD::FSHL, MVT::i64, 4 } 2728 }; 2729 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2730 { ISD::ROTL, MVT::i32, 1 }, 2731 { ISD::ROTL, MVT::i16, 1 }, 2732 { ISD::ROTL, MVT::i8, 1 }, 2733 { ISD::ROTR, MVT::i32, 1 }, 2734 { ISD::ROTR, MVT::i16, 1 }, 2735 { ISD::ROTR, MVT::i8, 1 }, 2736 { ISD::FSHL, MVT::i32, 4 }, 2737 { ISD::FSHL, MVT::i16, 4 }, 2738 { ISD::FSHL, MVT::i8, 4 } 2739 }; 2740 2741 unsigned ISD = ISD::DELETED_NODE; 2742 switch (IID) { 2743 default: 2744 break; 2745 case Intrinsic::fshl: 2746 ISD = ISD::FSHL; 2747 if (Args[0] == Args[1]) 2748 ISD = ISD::ROTL; 2749 break; 2750 case Intrinsic::fshr: 2751 // FSHR has same costs so don't duplicate. 2752 ISD = ISD::FSHL; 2753 if (Args[0] == Args[1]) 2754 ISD = ISD::ROTR; 2755 break; 2756 } 2757 2758 if (ISD != ISD::DELETED_NODE) { 2759 // Legalize the type. 2760 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 2761 MVT MTy = LT.second; 2762 2763 // Attempt to lookup cost. 2764 if (ST->hasAVX512()) 2765 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2766 return LT.first * Entry->Cost; 2767 2768 if (ST->hasXOP()) 2769 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2770 return LT.first * Entry->Cost; 2771 2772 if (ST->is64Bit()) 2773 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2774 return LT.first * Entry->Cost; 2775 2776 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2777 return LT.first * Entry->Cost; 2778 } 2779 2780 return BaseT::getIntrinsicInstrCost(IID, RetTy, Args, FMF, VF, I); 2781 } 2782 2783 int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { 2784 static const CostTblEntry SLMCostTbl[] = { 2785 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 2786 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 2787 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 2788 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 2789 }; 2790 2791 assert(Val->isVectorTy() && "This must be a vector type"); 2792 Type *ScalarType = Val->getScalarType(); 2793 int RegisterFileMoveCost = 0; 2794 2795 if (Index != -1U && (Opcode == Instruction::ExtractElement || 2796 Opcode == Instruction::InsertElement)) { 2797 // Legalize the type. 2798 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 2799 2800 // This type is legalized to a scalar type. 2801 if (!LT.second.isVector()) 2802 return 0; 2803 2804 // The type may be split. Normalize the index to the new type. 2805 unsigned NumElts = LT.second.getVectorNumElements(); 2806 unsigned SubNumElts = NumElts; 2807 Index = Index % NumElts; 2808 2809 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 2810 // For inserts, we also need to insert the subvector back. 2811 if (LT.second.getSizeInBits() > 128) { 2812 assert((LT.second.getSizeInBits() % 128) == 0 && "Illegal vector"); 2813 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 2814 SubNumElts = NumElts / NumSubVecs; 2815 if (SubNumElts <= Index) { 2816 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 2817 Index %= SubNumElts; 2818 } 2819 } 2820 2821 if (Index == 0) { 2822 // Floating point scalars are already located in index #0. 2823 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 2824 // true for all. 2825 if (ScalarType->isFloatingPointTy()) 2826 return RegisterFileMoveCost; 2827 2828 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 2829 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 2830 return 1 + RegisterFileMoveCost; 2831 } 2832 2833 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2834 assert(ISD && "Unexpected vector opcode"); 2835 MVT MScalarTy = LT.second.getScalarType(); 2836 if (ST->isSLM()) 2837 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 2838 return Entry->Cost + RegisterFileMoveCost; 2839 2840 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 2841 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 2842 (MScalarTy.isInteger() && ST->hasSSE41())) 2843 return 1 + RegisterFileMoveCost; 2844 2845 // Assume insertps is relatively cheap on all targets. 2846 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 2847 Opcode == Instruction::InsertElement) 2848 return 1 + RegisterFileMoveCost; 2849 2850 // For extractions we just need to shuffle the element to index 0, which 2851 // should be very cheap (assume cost = 1). For insertions we need to shuffle 2852 // the elements to its destination. In both cases we must handle the 2853 // subvector move(s). 2854 // If the vector type is already less than 128-bits then don't reduce it. 2855 // TODO: Under what circumstances should we shuffle using the full width? 2856 int ShuffleCost = 1; 2857 if (Opcode == Instruction::InsertElement) { 2858 auto *SubTy = cast<VectorType>(Val); 2859 EVT VT = TLI->getValueType(DL, Val); 2860 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 2861 SubTy = VectorType::get(ScalarType, SubNumElts); 2862 ShuffleCost = getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, 0, SubTy); 2863 } 2864 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 2865 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 2866 } 2867 2868 // Add to the base cost if we know that the extracted element of a vector is 2869 // destined to be moved to and used in the integer register file. 2870 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 2871 RegisterFileMoveCost += 1; 2872 2873 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 2874 } 2875 2876 unsigned X86TTIImpl::getScalarizationOverhead(Type *Ty, 2877 const APInt &DemandedElts, 2878 bool Insert, bool Extract) { 2879 auto* VecTy = cast<VectorType>(Ty); 2880 unsigned Cost = 0; 2881 2882 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much 2883 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT. 2884 if (Insert) { 2885 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 2886 MVT MScalarTy = LT.second.getScalarType(); 2887 2888 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 2889 (MScalarTy.isInteger() && ST->hasSSE41()) || 2890 (MScalarTy == MVT::f32 && ST->hasSSE41())) { 2891 // For types we can insert directly, insertion into 128-bit sub vectors is 2892 // cheap, followed by a cheap chain of concatenations. 2893 if (LT.second.getSizeInBits() <= 128) { 2894 Cost += 2895 BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, false); 2896 } else { 2897 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 2898 Cost += (PowerOf2Ceil(NumSubVecs) - 1) * LT.first; 2899 Cost += DemandedElts.countPopulation(); 2900 2901 // For vXf32 cases, insertion into the 0'th index in each v4f32 2902 // 128-bit vector is free. 2903 // NOTE: This assumes legalization widens vXf32 vectors. 2904 if (MScalarTy == MVT::f32) 2905 for (unsigned i = 0, e = VecTy->getNumElements(); i < e; i += 4) 2906 if (DemandedElts[i]) 2907 Cost--; 2908 } 2909 } else if (LT.second.isVector()) { 2910 // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded 2911 // integer element as a SCALAR_TO_VECTOR, then we build the vector as a 2912 // series of UNPCK followed by CONCAT_VECTORS - all of these can be 2913 // considered cheap. 2914 if (Ty->isIntOrIntVectorTy()) 2915 Cost += DemandedElts.countPopulation(); 2916 2917 // Get the smaller of the legalized or original pow2-extended number of 2918 // vector elements, which represents the number of unpacks we'll end up 2919 // performing. 2920 unsigned NumElts = LT.second.getVectorNumElements(); 2921 unsigned Pow2Elts = PowerOf2Ceil(VecTy->getNumElements()); 2922 Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first; 2923 } 2924 } 2925 2926 // TODO: Use default extraction for now, but we should investigate extending this 2927 // to handle repeated subvector extraction. 2928 if (Extract) 2929 Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, false, Extract); 2930 2931 return Cost; 2932 } 2933 2934 int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 2935 MaybeAlign Alignment, unsigned AddressSpace, 2936 const Instruction *I) { 2937 // Handle non-power-of-two vectors such as <3 x float> 2938 if (VectorType *VTy = dyn_cast<VectorType>(Src)) { 2939 unsigned NumElem = VTy->getNumElements(); 2940 2941 // Handle a few common cases: 2942 // <3 x float> 2943 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 2944 // Cost = 64 bit store + extract + 32 bit store. 2945 return 3; 2946 2947 // <3 x double> 2948 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 2949 // Cost = 128 bit store + unpack + 64 bit store. 2950 return 3; 2951 2952 // Assume that all other non-power-of-two numbers are scalarized. 2953 if (!isPowerOf2_32(NumElem)) { 2954 APInt DemandedElts = APInt::getAllOnesValue(NumElem); 2955 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment, 2956 AddressSpace); 2957 int SplitCost = getScalarizationOverhead(Src, DemandedElts, 2958 Opcode == Instruction::Load, 2959 Opcode == Instruction::Store); 2960 return NumElem * Cost + SplitCost; 2961 } 2962 } 2963 2964 // Legalize the type. 2965 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 2966 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 2967 "Invalid Opcode"); 2968 2969 // Each load/store unit costs 1. 2970 int Cost = LT.first * 1; 2971 2972 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a 2973 // proxy for a double-pumped AVX memory interface such as on Sandybridge. 2974 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow()) 2975 Cost *= 2; 2976 2977 return Cost; 2978 } 2979 2980 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, 2981 unsigned Alignment, 2982 unsigned AddressSpace) { 2983 bool IsLoad = (Instruction::Load == Opcode); 2984 bool IsStore = (Instruction::Store == Opcode); 2985 2986 VectorType *SrcVTy = dyn_cast<VectorType>(SrcTy); 2987 if (!SrcVTy) 2988 // To calculate scalar take the regular cost, without mask 2989 return getMemoryOpCost(Opcode, SrcTy, MaybeAlign(Alignment), AddressSpace); 2990 2991 unsigned NumElem = SrcVTy->getNumElements(); 2992 VectorType *MaskTy = 2993 VectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 2994 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, MaybeAlign(Alignment))) || 2995 (IsStore && !isLegalMaskedStore(SrcVTy, MaybeAlign(Alignment))) || 2996 !isPowerOf2_32(NumElem)) { 2997 // Scalarization 2998 APInt DemandedElts = APInt::getAllOnesValue(NumElem); 2999 int MaskSplitCost = 3000 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 3001 int ScalarCompareCost = getCmpSelInstrCost( 3002 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr); 3003 int BranchCost = getCFInstrCost(Instruction::Br); 3004 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 3005 int ValueSplitCost = 3006 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore); 3007 int MemopCost = 3008 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3009 MaybeAlign(Alignment), AddressSpace); 3010 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 3011 } 3012 3013 // Legalize the type. 3014 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3015 auto VT = TLI->getValueType(DL, SrcVTy); 3016 int Cost = 0; 3017 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 3018 LT.second.getVectorNumElements() == NumElem) 3019 // Promotion requires expand/truncate for data and a shuffle for mask. 3020 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, 0, nullptr) + 3021 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, 0, nullptr); 3022 3023 else if (LT.second.getVectorNumElements() > NumElem) { 3024 VectorType *NewMaskTy = VectorType::get(MaskTy->getElementType(), 3025 LT.second.getVectorNumElements()); 3026 // Expanding requires fill mask with zeroes 3027 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, 0, MaskTy); 3028 } 3029 3030 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 3031 if (!ST->hasAVX512()) 3032 return Cost + LT.first * (IsLoad ? 2 : 8); 3033 3034 // AVX-512 masked load/store is cheapper 3035 return Cost + LT.first; 3036 } 3037 3038 int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE, 3039 const SCEV *Ptr) { 3040 // Address computations in vectorized code with non-consecutive addresses will 3041 // likely result in more instructions compared to scalar code where the 3042 // computation can more often be merged into the index mode. The resulting 3043 // extra micro-ops can significantly decrease throughput. 3044 const unsigned NumVectorInstToHideOverhead = 10; 3045 3046 // Cost modeling of Strided Access Computation is hidden by the indexing 3047 // modes of X86 regardless of the stride value. We dont believe that there 3048 // is a difference between constant strided access in gerenal and constant 3049 // strided value which is less than or equal to 64. 3050 // Even in the case of (loop invariant) stride whose value is not known at 3051 // compile time, the address computation will not incur more than one extra 3052 // ADD instruction. 3053 if (Ty->isVectorTy() && SE) { 3054 if (!BaseT::isStridedAccess(Ptr)) 3055 return NumVectorInstToHideOverhead; 3056 if (!BaseT::getConstantStrideStep(SE, Ptr)) 3057 return 1; 3058 } 3059 3060 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 3061 } 3062 3063 int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 3064 bool IsPairwise) { 3065 // Just use the default implementation for pair reductions. 3066 if (IsPairwise) 3067 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise); 3068 3069 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3070 // and make it as the cost. 3071 3072 static const CostTblEntry SLMCostTblNoPairWise[] = { 3073 { ISD::FADD, MVT::v2f64, 3 }, 3074 { ISD::ADD, MVT::v2i64, 5 }, 3075 }; 3076 3077 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3078 { ISD::FADD, MVT::v2f64, 2 }, 3079 { ISD::FADD, MVT::v4f32, 4 }, 3080 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 3081 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 3082 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 3083 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 3084 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 3085 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 3086 { ISD::ADD, MVT::v2i8, 2 }, 3087 { ISD::ADD, MVT::v4i8, 2 }, 3088 { ISD::ADD, MVT::v8i8, 2 }, 3089 { ISD::ADD, MVT::v16i8, 3 }, 3090 }; 3091 3092 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3093 { ISD::FADD, MVT::v4f64, 3 }, 3094 { ISD::FADD, MVT::v4f32, 3 }, 3095 { ISD::FADD, MVT::v8f32, 4 }, 3096 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 3097 { ISD::ADD, MVT::v4i64, 3 }, 3098 { ISD::ADD, MVT::v8i32, 5 }, 3099 { ISD::ADD, MVT::v16i16, 5 }, 3100 { ISD::ADD, MVT::v32i8, 4 }, 3101 }; 3102 3103 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3104 assert(ISD && "Invalid opcode"); 3105 3106 // Before legalizing the type, give a chance to look up illegal narrow types 3107 // in the table. 3108 // FIXME: Is there a better way to do this? 3109 EVT VT = TLI->getValueType(DL, ValTy); 3110 if (VT.isSimple()) { 3111 MVT MTy = VT.getSimpleVT(); 3112 if (ST->isSLM()) 3113 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3114 return Entry->Cost; 3115 3116 if (ST->hasAVX()) 3117 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3118 return Entry->Cost; 3119 3120 if (ST->hasSSE2()) 3121 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3122 return Entry->Cost; 3123 } 3124 3125 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3126 3127 MVT MTy = LT.second; 3128 3129 auto *ValVTy = cast<VectorType>(ValTy); 3130 3131 unsigned ArithmeticCost = 0; 3132 if (LT.first != 1 && MTy.isVector() && 3133 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3134 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3135 VectorType *SingleOpTy = 3136 VectorType::get(ValVTy->getElementType(), MTy.getVectorNumElements()); 3137 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy); 3138 ArithmeticCost *= LT.first - 1; 3139 } 3140 3141 if (ST->isSLM()) 3142 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3143 return ArithmeticCost + Entry->Cost; 3144 3145 if (ST->hasAVX()) 3146 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3147 return ArithmeticCost + Entry->Cost; 3148 3149 if (ST->hasSSE2()) 3150 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3151 return ArithmeticCost + Entry->Cost; 3152 3153 // FIXME: These assume a naive kshift+binop lowering, which is probably 3154 // conservative in most cases. 3155 static const CostTblEntry AVX512BoolReduction[] = { 3156 { ISD::AND, MVT::v2i1, 3 }, 3157 { ISD::AND, MVT::v4i1, 5 }, 3158 { ISD::AND, MVT::v8i1, 7 }, 3159 { ISD::AND, MVT::v16i1, 9 }, 3160 { ISD::AND, MVT::v32i1, 11 }, 3161 { ISD::AND, MVT::v64i1, 13 }, 3162 { ISD::OR, MVT::v2i1, 3 }, 3163 { ISD::OR, MVT::v4i1, 5 }, 3164 { ISD::OR, MVT::v8i1, 7 }, 3165 { ISD::OR, MVT::v16i1, 9 }, 3166 { ISD::OR, MVT::v32i1, 11 }, 3167 { ISD::OR, MVT::v64i1, 13 }, 3168 }; 3169 3170 static const CostTblEntry AVX2BoolReduction[] = { 3171 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 3172 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 3173 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 3174 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 3175 }; 3176 3177 static const CostTblEntry AVX1BoolReduction[] = { 3178 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 3179 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 3180 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3181 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3182 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 3183 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 3184 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3185 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3186 }; 3187 3188 static const CostTblEntry SSE2BoolReduction[] = { 3189 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 3190 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 3191 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 3192 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 3193 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 3194 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 3195 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 3196 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 3197 }; 3198 3199 // Handle bool allof/anyof patterns. 3200 if (ValVTy->getElementType()->isIntegerTy(1)) { 3201 unsigned ArithmeticCost = 0; 3202 if (LT.first != 1 && MTy.isVector() && 3203 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3204 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3205 Type *SingleOpTy = 3206 VectorType::get(ValVTy->getElementType(), MTy.getVectorNumElements()); 3207 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy); 3208 ArithmeticCost *= LT.first - 1; 3209 } 3210 3211 if (ST->hasAVX512()) 3212 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 3213 return ArithmeticCost + Entry->Cost; 3214 if (ST->hasAVX2()) 3215 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 3216 return ArithmeticCost + Entry->Cost; 3217 if (ST->hasAVX()) 3218 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 3219 return ArithmeticCost + Entry->Cost; 3220 if (ST->hasSSE2()) 3221 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 3222 return ArithmeticCost + Entry->Cost; 3223 3224 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise); 3225 } 3226 3227 unsigned NumVecElts = ValVTy->getNumElements(); 3228 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 3229 3230 // Special case power of 2 reductions where the scalar type isn't changed 3231 // by type legalization. 3232 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 3233 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise); 3234 3235 unsigned ReductionCost = 0; 3236 3237 auto *Ty = ValVTy; 3238 if (LT.first != 1 && MTy.isVector() && 3239 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3240 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3241 Ty = VectorType::get(ValVTy->getElementType(), MTy.getVectorNumElements()); 3242 ReductionCost = getArithmeticInstrCost(Opcode, Ty); 3243 ReductionCost *= LT.first - 1; 3244 NumVecElts = MTy.getVectorNumElements(); 3245 } 3246 3247 // Now handle reduction with the legal type, taking into account size changes 3248 // at each level. 3249 while (NumVecElts > 1) { 3250 // Determine the size of the remaining vector we need to reduce. 3251 unsigned Size = NumVecElts * ScalarSize; 3252 NumVecElts /= 2; 3253 // If we're reducing from 256/512 bits, use an extract_subvector. 3254 if (Size > 128) { 3255 auto *SubTy = VectorType::get(ValVTy->getElementType(), NumVecElts); 3256 ReductionCost += 3257 getShuffleCost(TTI::SK_ExtractSubvector, Ty, NumVecElts, SubTy); 3258 Ty = SubTy; 3259 } else if (Size == 128) { 3260 // Reducing from 128 bits is a permute of v2f64/v2i64. 3261 VectorType *ShufTy; 3262 if (ValVTy->isFloatingPointTy()) 3263 ShufTy = VectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 3264 else 3265 ShufTy = VectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 3266 ReductionCost += 3267 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3268 } else if (Size == 64) { 3269 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3270 VectorType *ShufTy; 3271 if (ValVTy->isFloatingPointTy()) 3272 ShufTy = VectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 3273 else 3274 ShufTy = VectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 3275 ReductionCost += 3276 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3277 } else { 3278 // Reducing from smaller size is a shift by immediate. 3279 auto *ShiftTy = VectorType::get( 3280 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 3281 ReductionCost += getArithmeticInstrCost( 3282 Instruction::LShr, ShiftTy, TargetTransformInfo::OK_AnyValue, 3283 TargetTransformInfo::OK_UniformConstantValue, 3284 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3285 } 3286 3287 // Add the arithmetic op for this level. 3288 ReductionCost += getArithmeticInstrCost(Opcode, Ty); 3289 } 3290 3291 // Add the final extract element to the cost. 3292 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3293 } 3294 3295 int X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, bool IsUnsigned) { 3296 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3297 3298 MVT MTy = LT.second; 3299 3300 int ISD; 3301 if (Ty->isIntOrIntVectorTy()) { 3302 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3303 } else { 3304 assert(Ty->isFPOrFPVectorTy() && 3305 "Expected float point or integer vector type."); 3306 ISD = ISD::FMINNUM; 3307 } 3308 3309 static const CostTblEntry SSE1CostTbl[] = { 3310 {ISD::FMINNUM, MVT::v4f32, 1}, 3311 }; 3312 3313 static const CostTblEntry SSE2CostTbl[] = { 3314 {ISD::FMINNUM, MVT::v2f64, 1}, 3315 {ISD::SMIN, MVT::v8i16, 1}, 3316 {ISD::UMIN, MVT::v16i8, 1}, 3317 }; 3318 3319 static const CostTblEntry SSE41CostTbl[] = { 3320 {ISD::SMIN, MVT::v4i32, 1}, 3321 {ISD::UMIN, MVT::v4i32, 1}, 3322 {ISD::UMIN, MVT::v8i16, 1}, 3323 {ISD::SMIN, MVT::v16i8, 1}, 3324 }; 3325 3326 static const CostTblEntry SSE42CostTbl[] = { 3327 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 3328 }; 3329 3330 static const CostTblEntry AVX1CostTbl[] = { 3331 {ISD::FMINNUM, MVT::v8f32, 1}, 3332 {ISD::FMINNUM, MVT::v4f64, 1}, 3333 {ISD::SMIN, MVT::v8i32, 3}, 3334 {ISD::UMIN, MVT::v8i32, 3}, 3335 {ISD::SMIN, MVT::v16i16, 3}, 3336 {ISD::UMIN, MVT::v16i16, 3}, 3337 {ISD::SMIN, MVT::v32i8, 3}, 3338 {ISD::UMIN, MVT::v32i8, 3}, 3339 }; 3340 3341 static const CostTblEntry AVX2CostTbl[] = { 3342 {ISD::SMIN, MVT::v8i32, 1}, 3343 {ISD::UMIN, MVT::v8i32, 1}, 3344 {ISD::SMIN, MVT::v16i16, 1}, 3345 {ISD::UMIN, MVT::v16i16, 1}, 3346 {ISD::SMIN, MVT::v32i8, 1}, 3347 {ISD::UMIN, MVT::v32i8, 1}, 3348 }; 3349 3350 static const CostTblEntry AVX512CostTbl[] = { 3351 {ISD::FMINNUM, MVT::v16f32, 1}, 3352 {ISD::FMINNUM, MVT::v8f64, 1}, 3353 {ISD::SMIN, MVT::v2i64, 1}, 3354 {ISD::UMIN, MVT::v2i64, 1}, 3355 {ISD::SMIN, MVT::v4i64, 1}, 3356 {ISD::UMIN, MVT::v4i64, 1}, 3357 {ISD::SMIN, MVT::v8i64, 1}, 3358 {ISD::UMIN, MVT::v8i64, 1}, 3359 {ISD::SMIN, MVT::v16i32, 1}, 3360 {ISD::UMIN, MVT::v16i32, 1}, 3361 }; 3362 3363 static const CostTblEntry AVX512BWCostTbl[] = { 3364 {ISD::SMIN, MVT::v32i16, 1}, 3365 {ISD::UMIN, MVT::v32i16, 1}, 3366 {ISD::SMIN, MVT::v64i8, 1}, 3367 {ISD::UMIN, MVT::v64i8, 1}, 3368 }; 3369 3370 // If we have a native MIN/MAX instruction for this type, use it. 3371 if (ST->hasBWI()) 3372 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3373 return LT.first * Entry->Cost; 3374 3375 if (ST->hasAVX512()) 3376 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3377 return LT.first * Entry->Cost; 3378 3379 if (ST->hasAVX2()) 3380 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3381 return LT.first * Entry->Cost; 3382 3383 if (ST->hasAVX()) 3384 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3385 return LT.first * Entry->Cost; 3386 3387 if (ST->hasSSE42()) 3388 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3389 return LT.first * Entry->Cost; 3390 3391 if (ST->hasSSE41()) 3392 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3393 return LT.first * Entry->Cost; 3394 3395 if (ST->hasSSE2()) 3396 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3397 return LT.first * Entry->Cost; 3398 3399 if (ST->hasSSE1()) 3400 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3401 return LT.first * Entry->Cost; 3402 3403 unsigned CmpOpcode; 3404 if (Ty->isFPOrFPVectorTy()) { 3405 CmpOpcode = Instruction::FCmp; 3406 } else { 3407 assert(Ty->isIntOrIntVectorTy() && 3408 "expecting floating point or integer type for min/max reduction"); 3409 CmpOpcode = Instruction::ICmp; 3410 } 3411 3412 // Otherwise fall back to cmp+select. 3413 return getCmpSelInstrCost(CmpOpcode, Ty, CondTy, nullptr) + 3414 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, nullptr); 3415 } 3416 3417 int X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 3418 bool IsPairwise, bool IsUnsigned) { 3419 // Just use the default implementation for pair reductions. 3420 if (IsPairwise) 3421 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned); 3422 3423 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3424 3425 MVT MTy = LT.second; 3426 3427 int ISD; 3428 if (ValTy->isIntOrIntVectorTy()) { 3429 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3430 } else { 3431 assert(ValTy->isFPOrFPVectorTy() && 3432 "Expected float point or integer vector type."); 3433 ISD = ISD::FMINNUM; 3434 } 3435 3436 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3437 // and make it as the cost. 3438 3439 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3440 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 3441 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 3442 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 3443 }; 3444 3445 static const CostTblEntry SSE41CostTblNoPairWise[] = { 3446 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 3447 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 3448 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 3449 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 3450 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 3451 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 3452 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 3453 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 3454 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 3455 {ISD::SMIN, MVT::v16i8, 6}, 3456 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 3457 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 3458 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 3459 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 3460 }; 3461 3462 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3463 {ISD::SMIN, MVT::v16i16, 6}, 3464 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 3465 {ISD::SMIN, MVT::v32i8, 8}, 3466 {ISD::UMIN, MVT::v32i8, 8}, 3467 }; 3468 3469 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 3470 {ISD::SMIN, MVT::v32i16, 8}, 3471 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 3472 {ISD::SMIN, MVT::v64i8, 10}, 3473 {ISD::UMIN, MVT::v64i8, 10}, 3474 }; 3475 3476 // Before legalizing the type, give a chance to look up illegal narrow types 3477 // in the table. 3478 // FIXME: Is there a better way to do this? 3479 EVT VT = TLI->getValueType(DL, ValTy); 3480 if (VT.isSimple()) { 3481 MVT MTy = VT.getSimpleVT(); 3482 if (ST->hasBWI()) 3483 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3484 return Entry->Cost; 3485 3486 if (ST->hasAVX()) 3487 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3488 return Entry->Cost; 3489 3490 if (ST->hasSSE41()) 3491 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3492 return Entry->Cost; 3493 3494 if (ST->hasSSE2()) 3495 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3496 return Entry->Cost; 3497 } 3498 3499 auto *ValVTy = cast<VectorType>(ValTy); 3500 unsigned NumVecElts = ValVTy->getNumElements(); 3501 3502 auto *Ty = ValVTy; 3503 unsigned MinMaxCost = 0; 3504 if (LT.first != 1 && MTy.isVector() && 3505 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3506 // Type needs to be split. We need LT.first - 1 operations ops. 3507 Ty = VectorType::get(ValVTy->getElementType(), MTy.getVectorNumElements()); 3508 auto *SubCondTy = VectorType::get( 3509 cast<VectorType>(CondTy)->getElementType(), MTy.getVectorNumElements()); 3510 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3511 MinMaxCost *= LT.first - 1; 3512 NumVecElts = MTy.getVectorNumElements(); 3513 } 3514 3515 if (ST->hasBWI()) 3516 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3517 return MinMaxCost + Entry->Cost; 3518 3519 if (ST->hasAVX()) 3520 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3521 return MinMaxCost + Entry->Cost; 3522 3523 if (ST->hasSSE41()) 3524 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3525 return MinMaxCost + Entry->Cost; 3526 3527 if (ST->hasSSE2()) 3528 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3529 return MinMaxCost + Entry->Cost; 3530 3531 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 3532 3533 // Special case power of 2 reductions where the scalar type isn't changed 3534 // by type legalization. 3535 if (!isPowerOf2_32(ValVTy->getNumElements()) || 3536 ScalarSize != MTy.getScalarSizeInBits()) 3537 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned); 3538 3539 // Now handle reduction with the legal type, taking into account size changes 3540 // at each level. 3541 while (NumVecElts > 1) { 3542 // Determine the size of the remaining vector we need to reduce. 3543 unsigned Size = NumVecElts * ScalarSize; 3544 NumVecElts /= 2; 3545 // If we're reducing from 256/512 bits, use an extract_subvector. 3546 if (Size > 128) { 3547 auto *SubTy = VectorType::get(ValVTy->getElementType(), NumVecElts); 3548 MinMaxCost += 3549 getShuffleCost(TTI::SK_ExtractSubvector, Ty, NumVecElts, SubTy); 3550 Ty = SubTy; 3551 } else if (Size == 128) { 3552 // Reducing from 128 bits is a permute of v2f64/v2i64. 3553 VectorType *ShufTy; 3554 if (ValTy->isFloatingPointTy()) 3555 ShufTy = VectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 3556 else 3557 ShufTy = VectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 3558 MinMaxCost += 3559 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3560 } else if (Size == 64) { 3561 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3562 VectorType *ShufTy; 3563 if (ValTy->isFloatingPointTy()) 3564 ShufTy = VectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 3565 else 3566 ShufTy = VectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 3567 MinMaxCost += 3568 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3569 } else { 3570 // Reducing from smaller size is a shift by immediate. 3571 VectorType *ShiftTy = VectorType::get( 3572 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 3573 MinMaxCost += getArithmeticInstrCost( 3574 Instruction::LShr, ShiftTy, TargetTransformInfo::OK_AnyValue, 3575 TargetTransformInfo::OK_UniformConstantValue, 3576 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3577 } 3578 3579 // Add the arithmetic op for this level. 3580 auto *SubCondTy = VectorType::get(CondTy->getElementType(), 3581 Ty->getNumElements()); 3582 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3583 } 3584 3585 // Add the final extract element to the cost. 3586 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3587 } 3588 3589 /// Calculate the cost of materializing a 64-bit value. This helper 3590 /// method might only calculate a fraction of a larger immediate. Therefore it 3591 /// is valid to return a cost of ZERO. 3592 int X86TTIImpl::getIntImmCost(int64_t Val) { 3593 if (Val == 0) 3594 return TTI::TCC_Free; 3595 3596 if (isInt<32>(Val)) 3597 return TTI::TCC_Basic; 3598 3599 return 2 * TTI::TCC_Basic; 3600 } 3601 3602 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { 3603 assert(Ty->isIntegerTy()); 3604 3605 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3606 if (BitSize == 0) 3607 return ~0U; 3608 3609 // Never hoist constants larger than 128bit, because this might lead to 3610 // incorrect code generation or assertions in codegen. 3611 // Fixme: Create a cost model for types larger than i128 once the codegen 3612 // issues have been fixed. 3613 if (BitSize > 128) 3614 return TTI::TCC_Free; 3615 3616 if (Imm == 0) 3617 return TTI::TCC_Free; 3618 3619 // Sign-extend all constants to a multiple of 64-bit. 3620 APInt ImmVal = Imm; 3621 if (BitSize % 64 != 0) 3622 ImmVal = Imm.sext(alignTo(BitSize, 64)); 3623 3624 // Split the constant into 64-bit chunks and calculate the cost for each 3625 // chunk. 3626 int Cost = 0; 3627 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 3628 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 3629 int64_t Val = Tmp.getSExtValue(); 3630 Cost += getIntImmCost(Val); 3631 } 3632 // We need at least one instruction to materialize the constant. 3633 return std::max(1, Cost); 3634 } 3635 3636 int X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, 3637 Type *Ty) { 3638 assert(Ty->isIntegerTy()); 3639 3640 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3641 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3642 // here, so that constant hoisting will ignore this constant. 3643 if (BitSize == 0) 3644 return TTI::TCC_Free; 3645 3646 unsigned ImmIdx = ~0U; 3647 switch (Opcode) { 3648 default: 3649 return TTI::TCC_Free; 3650 case Instruction::GetElementPtr: 3651 // Always hoist the base address of a GetElementPtr. This prevents the 3652 // creation of new constants for every base constant that gets constant 3653 // folded with the offset. 3654 if (Idx == 0) 3655 return 2 * TTI::TCC_Basic; 3656 return TTI::TCC_Free; 3657 case Instruction::Store: 3658 ImmIdx = 0; 3659 break; 3660 case Instruction::ICmp: 3661 // This is an imperfect hack to prevent constant hoisting of 3662 // compares that might be trying to check if a 64-bit value fits in 3663 // 32-bits. The backend can optimize these cases using a right shift by 32. 3664 // Ideally we would check the compare predicate here. There also other 3665 // similar immediates the backend can use shifts for. 3666 if (Idx == 1 && Imm.getBitWidth() == 64) { 3667 uint64_t ImmVal = Imm.getZExtValue(); 3668 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 3669 return TTI::TCC_Free; 3670 } 3671 ImmIdx = 1; 3672 break; 3673 case Instruction::And: 3674 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 3675 // by using a 32-bit operation with implicit zero extension. Detect such 3676 // immediates here as the normal path expects bit 31 to be sign extended. 3677 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 3678 return TTI::TCC_Free; 3679 ImmIdx = 1; 3680 break; 3681 case Instruction::Add: 3682 case Instruction::Sub: 3683 // For add/sub, we can use the opposite instruction for INT32_MIN. 3684 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 3685 return TTI::TCC_Free; 3686 ImmIdx = 1; 3687 break; 3688 case Instruction::UDiv: 3689 case Instruction::SDiv: 3690 case Instruction::URem: 3691 case Instruction::SRem: 3692 // Division by constant is typically expanded later into a different 3693 // instruction sequence. This completely changes the constants. 3694 // Report them as "free" to stop ConstantHoist from marking them as opaque. 3695 return TTI::TCC_Free; 3696 case Instruction::Mul: 3697 case Instruction::Or: 3698 case Instruction::Xor: 3699 ImmIdx = 1; 3700 break; 3701 // Always return TCC_Free for the shift value of a shift instruction. 3702 case Instruction::Shl: 3703 case Instruction::LShr: 3704 case Instruction::AShr: 3705 if (Idx == 1) 3706 return TTI::TCC_Free; 3707 break; 3708 case Instruction::Trunc: 3709 case Instruction::ZExt: 3710 case Instruction::SExt: 3711 case Instruction::IntToPtr: 3712 case Instruction::PtrToInt: 3713 case Instruction::BitCast: 3714 case Instruction::PHI: 3715 case Instruction::Call: 3716 case Instruction::Select: 3717 case Instruction::Ret: 3718 case Instruction::Load: 3719 break; 3720 } 3721 3722 if (Idx == ImmIdx) { 3723 int NumConstants = divideCeil(BitSize, 64); 3724 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty); 3725 return (Cost <= NumConstants * TTI::TCC_Basic) 3726 ? static_cast<int>(TTI::TCC_Free) 3727 : Cost; 3728 } 3729 3730 return X86TTIImpl::getIntImmCost(Imm, Ty); 3731 } 3732 3733 int X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 3734 const APInt &Imm, Type *Ty) { 3735 assert(Ty->isIntegerTy()); 3736 3737 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3738 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3739 // here, so that constant hoisting will ignore this constant. 3740 if (BitSize == 0) 3741 return TTI::TCC_Free; 3742 3743 switch (IID) { 3744 default: 3745 return TTI::TCC_Free; 3746 case Intrinsic::sadd_with_overflow: 3747 case Intrinsic::uadd_with_overflow: 3748 case Intrinsic::ssub_with_overflow: 3749 case Intrinsic::usub_with_overflow: 3750 case Intrinsic::smul_with_overflow: 3751 case Intrinsic::umul_with_overflow: 3752 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 3753 return TTI::TCC_Free; 3754 break; 3755 case Intrinsic::experimental_stackmap: 3756 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 3757 return TTI::TCC_Free; 3758 break; 3759 case Intrinsic::experimental_patchpoint_void: 3760 case Intrinsic::experimental_patchpoint_i64: 3761 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 3762 return TTI::TCC_Free; 3763 break; 3764 } 3765 return X86TTIImpl::getIntImmCost(Imm, Ty); 3766 } 3767 3768 unsigned 3769 X86TTIImpl::getUserCost(const User *U, ArrayRef<const Value *> Operands, 3770 TTI::TargetCostKind CostKind) { 3771 if (isa<StoreInst>(U)) { 3772 Value *Ptr = U->getOperand(1); 3773 // Store instruction with index and scale costs 2 Uops. 3774 // Check the preceding GEP to identify non-const indices. 3775 if (auto GEP = dyn_cast<GetElementPtrInst>(Ptr)) { 3776 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3777 return TTI::TCC_Basic * 2; 3778 } 3779 return TTI::TCC_Basic; 3780 } 3781 return BaseT::getUserCost(U, Operands, CostKind); 3782 } 3783 3784 // Return an average cost of Gather / Scatter instruction, maybe improved later 3785 int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, Value *Ptr, 3786 unsigned Alignment, unsigned AddressSpace) { 3787 3788 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 3789 unsigned VF = cast<VectorType>(SrcVTy)->getNumElements(); 3790 3791 // Try to reduce index size from 64 bit (default for GEP) 3792 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 3793 // operation will use 16 x 64 indices which do not fit in a zmm and needs 3794 // to split. Also check that the base pointer is the same for all lanes, 3795 // and that there's at most one variable index. 3796 auto getIndexSizeInBits = [](Value *Ptr, const DataLayout& DL) { 3797 unsigned IndexSize = DL.getPointerSizeInBits(); 3798 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 3799 if (IndexSize < 64 || !GEP) 3800 return IndexSize; 3801 3802 unsigned NumOfVarIndices = 0; 3803 Value *Ptrs = GEP->getPointerOperand(); 3804 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 3805 return IndexSize; 3806 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 3807 if (isa<Constant>(GEP->getOperand(i))) 3808 continue; 3809 Type *IndxTy = GEP->getOperand(i)->getType(); 3810 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 3811 IndxTy = IndexVTy->getElementType(); 3812 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 3813 !isa<SExtInst>(GEP->getOperand(i))) || 3814 ++NumOfVarIndices > 1) 3815 return IndexSize; // 64 3816 } 3817 return (unsigned)32; 3818 }; 3819 3820 3821 // Trying to reduce IndexSize to 32 bits for vector 16. 3822 // By default the IndexSize is equal to pointer size. 3823 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 3824 ? getIndexSizeInBits(Ptr, DL) 3825 : DL.getPointerSizeInBits(); 3826 3827 Type *IndexVTy = VectorType::get(IntegerType::get(SrcVTy->getContext(), 3828 IndexSize), VF); 3829 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy); 3830 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3831 int SplitFactor = std::max(IdxsLT.first, SrcLT.first); 3832 if (SplitFactor > 1) { 3833 // Handle splitting of vector of pointers 3834 Type *SplitSrcTy = VectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 3835 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 3836 AddressSpace); 3837 } 3838 3839 // The gather / scatter cost is given by Intel architects. It is a rough 3840 // number since we are looking at one instruction in a time. 3841 const int GSOverhead = (Opcode == Instruction::Load) 3842 ? ST->getGatherOverhead() 3843 : ST->getScatterOverhead(); 3844 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3845 MaybeAlign(Alignment), AddressSpace); 3846 } 3847 3848 /// Return the cost of full scalarization of gather / scatter operation. 3849 /// 3850 /// Opcode - Load or Store instruction. 3851 /// SrcVTy - The type of the data vector that should be gathered or scattered. 3852 /// VariableMask - The mask is non-constant at compile time. 3853 /// Alignment - Alignment for one element. 3854 /// AddressSpace - pointer[s] address space. 3855 /// 3856 int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 3857 bool VariableMask, unsigned Alignment, 3858 unsigned AddressSpace) { 3859 unsigned VF = cast<VectorType>(SrcVTy)->getNumElements(); 3860 APInt DemandedElts = APInt::getAllOnesValue(VF); 3861 3862 int MaskUnpackCost = 0; 3863 if (VariableMask) { 3864 VectorType *MaskTy = 3865 VectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 3866 MaskUnpackCost = 3867 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 3868 int ScalarCompareCost = 3869 getCmpSelInstrCost(Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), 3870 nullptr); 3871 int BranchCost = getCFInstrCost(Instruction::Br); 3872 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 3873 } 3874 3875 // The cost of the scalar loads/stores. 3876 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3877 MaybeAlign(Alignment), AddressSpace); 3878 3879 int InsertExtractCost = 0; 3880 if (Opcode == Instruction::Load) 3881 for (unsigned i = 0; i < VF; ++i) 3882 // Add the cost of inserting each scalar load into the vector 3883 InsertExtractCost += 3884 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 3885 else 3886 for (unsigned i = 0; i < VF; ++i) 3887 // Add the cost of extracting each element out of the data vector 3888 InsertExtractCost += 3889 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 3890 3891 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 3892 } 3893 3894 /// Calculate the cost of Gather / Scatter operation 3895 int X86TTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *SrcVTy, 3896 Value *Ptr, bool VariableMask, 3897 unsigned Alignment, 3898 const Instruction *I = nullptr) { 3899 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 3900 unsigned VF = cast<VectorType>(SrcVTy)->getNumElements(); 3901 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 3902 if (!PtrTy && Ptr->getType()->isVectorTy()) 3903 PtrTy = dyn_cast<PointerType>( 3904 cast<VectorType>(Ptr->getType())->getElementType()); 3905 assert(PtrTy && "Unexpected type for Ptr argument"); 3906 unsigned AddressSpace = PtrTy->getAddressSpace(); 3907 3908 bool Scalarize = false; 3909 if ((Opcode == Instruction::Load && 3910 !isLegalMaskedGather(SrcVTy, MaybeAlign(Alignment))) || 3911 (Opcode == Instruction::Store && 3912 !isLegalMaskedScatter(SrcVTy, MaybeAlign(Alignment)))) 3913 Scalarize = true; 3914 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 3915 // Vector-4 of gather/scatter instruction does not exist on KNL. 3916 // We can extend it to 8 elements, but zeroing upper bits of 3917 // the mask vector will add more instructions. Right now we give the scalar 3918 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 3919 // is better in the VariableMask case. 3920 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 3921 Scalarize = true; 3922 3923 if (Scalarize) 3924 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 3925 AddressSpace); 3926 3927 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 3928 } 3929 3930 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 3931 TargetTransformInfo::LSRCost &C2) { 3932 // X86 specific here are "instruction number 1st priority". 3933 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 3934 C1.NumIVMuls, C1.NumBaseAdds, 3935 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 3936 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 3937 C2.NumIVMuls, C2.NumBaseAdds, 3938 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 3939 } 3940 3941 bool X86TTIImpl::canMacroFuseCmp() { 3942 return ST->hasMacroFusion() || ST->hasBranchFusion(); 3943 } 3944 3945 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, MaybeAlign Alignment) { 3946 if (!ST->hasAVX()) 3947 return false; 3948 3949 // The backend can't handle a single element vector. 3950 if (isa<VectorType>(DataTy) && 3951 cast<VectorType>(DataTy)->getNumElements() == 1) 3952 return false; 3953 Type *ScalarTy = DataTy->getScalarType(); 3954 3955 if (ScalarTy->isPointerTy()) 3956 return true; 3957 3958 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 3959 return true; 3960 3961 if (!ScalarTy->isIntegerTy()) 3962 return false; 3963 3964 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 3965 return IntWidth == 32 || IntWidth == 64 || 3966 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 3967 } 3968 3969 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, MaybeAlign Alignment) { 3970 return isLegalMaskedLoad(DataType, Alignment); 3971 } 3972 3973 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 3974 unsigned DataSize = DL.getTypeStoreSize(DataType); 3975 // The only supported nontemporal loads are for aligned vectors of 16 or 32 3976 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 3977 // (the equivalent stores only require AVX). 3978 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 3979 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 3980 3981 return false; 3982 } 3983 3984 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 3985 unsigned DataSize = DL.getTypeStoreSize(DataType); 3986 3987 // SSE4A supports nontemporal stores of float and double at arbitrary 3988 // alignment. 3989 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 3990 return true; 3991 3992 // Besides the SSE4A subtarget exception above, only aligned stores are 3993 // available nontemporaly on any other subtarget. And only stores with a size 3994 // of 4..32 bytes (powers of 2, only) are permitted. 3995 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 3996 !isPowerOf2_32(DataSize)) 3997 return false; 3998 3999 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 4000 // loads require AVX2). 4001 if (DataSize == 32) 4002 return ST->hasAVX(); 4003 else if (DataSize == 16) 4004 return ST->hasSSE1(); 4005 return true; 4006 } 4007 4008 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 4009 if (!isa<VectorType>(DataTy)) 4010 return false; 4011 4012 if (!ST->hasAVX512()) 4013 return false; 4014 4015 // The backend can't handle a single element vector. 4016 if (cast<VectorType>(DataTy)->getNumElements() == 1) 4017 return false; 4018 4019 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 4020 4021 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4022 return true; 4023 4024 if (!ScalarTy->isIntegerTy()) 4025 return false; 4026 4027 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4028 return IntWidth == 32 || IntWidth == 64 || 4029 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 4030 } 4031 4032 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 4033 return isLegalMaskedExpandLoad(DataTy); 4034 } 4035 4036 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, MaybeAlign Alignment) { 4037 // Some CPUs have better gather performance than others. 4038 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 4039 // enable gather with a -march. 4040 if (!(ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()))) 4041 return false; 4042 4043 // This function is called now in two cases: from the Loop Vectorizer 4044 // and from the Scalarizer. 4045 // When the Loop Vectorizer asks about legality of the feature, 4046 // the vectorization factor is not calculated yet. The Loop Vectorizer 4047 // sends a scalar type and the decision is based on the width of the 4048 // scalar element. 4049 // Later on, the cost model will estimate usage this intrinsic based on 4050 // the vector type. 4051 // The Scalarizer asks again about legality. It sends a vector type. 4052 // In this case we can reject non-power-of-2 vectors. 4053 // We also reject single element vectors as the type legalizer can't 4054 // scalarize it. 4055 if (auto *DataVTy = dyn_cast<VectorType>(DataTy)) { 4056 unsigned NumElts = DataVTy->getNumElements(); 4057 if (NumElts == 1 || !isPowerOf2_32(NumElts)) 4058 return false; 4059 } 4060 Type *ScalarTy = DataTy->getScalarType(); 4061 if (ScalarTy->isPointerTy()) 4062 return true; 4063 4064 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4065 return true; 4066 4067 if (!ScalarTy->isIntegerTy()) 4068 return false; 4069 4070 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4071 return IntWidth == 32 || IntWidth == 64; 4072 } 4073 4074 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, MaybeAlign Alignment) { 4075 // AVX2 doesn't support scatter 4076 if (!ST->hasAVX512()) 4077 return false; 4078 return isLegalMaskedGather(DataType, Alignment); 4079 } 4080 4081 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 4082 EVT VT = TLI->getValueType(DL, DataType); 4083 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 4084 } 4085 4086 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 4087 return false; 4088 } 4089 4090 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 4091 const Function *Callee) const { 4092 const TargetMachine &TM = getTLI()->getTargetMachine(); 4093 4094 // Work this as a subsetting of subtarget features. 4095 const FeatureBitset &CallerBits = 4096 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 4097 const FeatureBitset &CalleeBits = 4098 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 4099 4100 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 4101 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 4102 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 4103 } 4104 4105 bool X86TTIImpl::areFunctionArgsABICompatible( 4106 const Function *Caller, const Function *Callee, 4107 SmallPtrSetImpl<Argument *> &Args) const { 4108 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args)) 4109 return false; 4110 4111 // If we get here, we know the target features match. If one function 4112 // considers 512-bit vectors legal and the other does not, consider them 4113 // incompatible. 4114 const TargetMachine &TM = getTLI()->getTargetMachine(); 4115 4116 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 4117 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs()) 4118 return true; 4119 4120 // Consider the arguments compatible if they aren't vectors or aggregates. 4121 // FIXME: Look at the size of vectors. 4122 // FIXME: Look at the element types of aggregates to see if there are vectors. 4123 // FIXME: The API of this function seems intended to allow arguments 4124 // to be removed from the set, but the caller doesn't check if the set 4125 // becomes empty so that may not work in practice. 4126 return llvm::none_of(Args, [](Argument *A) { 4127 auto *EltTy = cast<PointerType>(A->getType())->getElementType(); 4128 return EltTy->isVectorTy() || EltTy->isAggregateType(); 4129 }); 4130 } 4131 4132 X86TTIImpl::TTI::MemCmpExpansionOptions 4133 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 4134 TTI::MemCmpExpansionOptions Options; 4135 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 4136 Options.NumLoadsPerBlock = 2; 4137 // All GPR and vector loads can be unaligned. 4138 Options.AllowOverlappingLoads = true; 4139 if (IsZeroCmp) { 4140 // Only enable vector loads for equality comparison. Right now the vector 4141 // version is not as fast for three way compare (see #33329). 4142 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 4143 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 4144 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 4145 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 4146 } 4147 if (ST->is64Bit()) { 4148 Options.LoadSizes.push_back(8); 4149 } 4150 Options.LoadSizes.push_back(4); 4151 Options.LoadSizes.push_back(2); 4152 Options.LoadSizes.push_back(1); 4153 return Options; 4154 } 4155 4156 bool X86TTIImpl::enableInterleavedAccessVectorization() { 4157 // TODO: We expect this to be beneficial regardless of arch, 4158 // but there are currently some unexplained performance artifacts on Atom. 4159 // As a temporary solution, disable on Atom. 4160 return !(ST->isAtom()); 4161 } 4162 4163 // Get estimation for interleaved load/store operations for AVX2. 4164 // \p Factor is the interleaved-access factor (stride) - number of 4165 // (interleaved) elements in the group. 4166 // \p Indices contains the indices for a strided load: when the 4167 // interleaved load has gaps they indicate which elements are used. 4168 // If Indices is empty (or if the number of indices is equal to the size 4169 // of the interleaved-access as given in \p Factor) the access has no gaps. 4170 // 4171 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 4172 // computing the cost using a generic formula as a function of generic 4173 // shuffles. We therefore use a lookup table instead, filled according to 4174 // the instruction sequences that codegen currently generates. 4175 int X86TTIImpl::getInterleavedMemoryOpCostAVX2(unsigned Opcode, Type *VecTy, 4176 unsigned Factor, 4177 ArrayRef<unsigned> Indices, 4178 unsigned Alignment, 4179 unsigned AddressSpace, 4180 bool UseMaskForCond, 4181 bool UseMaskForGaps) { 4182 4183 if (UseMaskForCond || UseMaskForGaps) 4184 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4185 Alignment, AddressSpace, 4186 UseMaskForCond, UseMaskForGaps); 4187 4188 // We currently Support only fully-interleaved groups, with no gaps. 4189 // TODO: Support also strided loads (interleaved-groups with gaps). 4190 if (Indices.size() && Indices.size() != Factor) 4191 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4192 Alignment, AddressSpace); 4193 4194 // VecTy for interleave memop is <VF*Factor x Elt>. 4195 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4196 // VecTy = <12 x i32>. 4197 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4198 4199 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 4200 // the VF=2, while v2i128 is an unsupported MVT vector type 4201 // (see MachineValueType.h::getVectorVT()). 4202 if (!LegalVT.isVector()) 4203 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4204 Alignment, AddressSpace); 4205 4206 unsigned VF = cast<VectorType>(VecTy)->getNumElements() / Factor; 4207 Type *ScalarTy = cast<VectorType>(VecTy)->getElementType(); 4208 4209 // Calculate the number of memory operations (NumOfMemOps), required 4210 // for load/store the VecTy. 4211 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4212 unsigned LegalVTSize = LegalVT.getStoreSize(); 4213 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4214 4215 // Get the cost of one memory operation. 4216 Type *SingleMemOpTy = 4217 VectorType::get(cast<VectorType>(VecTy)->getElementType(), 4218 LegalVT.getVectorNumElements()); 4219 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 4220 MaybeAlign(Alignment), AddressSpace); 4221 4222 VectorType *VT = VectorType::get(ScalarTy, VF); 4223 EVT ETy = TLI->getValueType(DL, VT); 4224 if (!ETy.isSimple()) 4225 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4226 Alignment, AddressSpace); 4227 4228 // TODO: Complete for other data-types and strides. 4229 // Each combination of Stride, ElementTy and VF results in a different 4230 // sequence; The cost tables are therefore accessed with: 4231 // Factor (stride) and VectorType=VFxElemType. 4232 // The Cost accounts only for the shuffle sequence; 4233 // The cost of the loads/stores is accounted for separately. 4234 // 4235 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 4236 { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64 4237 { 2, MVT::v4f64, 6 }, //(load 8f64 and) deinterleave into 2 x 4f64 4238 4239 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8 4240 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8 4241 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8 4242 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8 4243 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8 4244 { 3, MVT::v8f32, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32 4245 4246 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8 4247 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8 4248 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8 4249 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8 4250 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8 4251 4252 { 8, MVT::v8f32, 40 } //(load 64f32 and)deinterleave into 8 x 8f32 4253 }; 4254 4255 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 4256 { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store) 4257 { 2, MVT::v4f64, 6 }, //interleave into 2 x 4f64 into 8f64 (and store) 4258 4259 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store) 4260 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store) 4261 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store) 4262 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store) 4263 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store) 4264 4265 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store) 4266 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store) 4267 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store) 4268 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store) 4269 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store) 4270 }; 4271 4272 if (Opcode == Instruction::Load) { 4273 if (const auto *Entry = 4274 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 4275 return NumOfMemOps * MemOpCost + Entry->Cost; 4276 } else { 4277 assert(Opcode == Instruction::Store && 4278 "Expected Store Instruction at this point"); 4279 if (const auto *Entry = 4280 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 4281 return NumOfMemOps * MemOpCost + Entry->Cost; 4282 } 4283 4284 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4285 Alignment, AddressSpace); 4286 } 4287 4288 // Get estimation for interleaved load/store operations and strided load. 4289 // \p Indices contains indices for strided load. 4290 // \p Factor - the factor of interleaving. 4291 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 4292 int X86TTIImpl::getInterleavedMemoryOpCostAVX512(unsigned Opcode, Type *VecTy, 4293 unsigned Factor, 4294 ArrayRef<unsigned> Indices, 4295 unsigned Alignment, 4296 unsigned AddressSpace, 4297 bool UseMaskForCond, 4298 bool UseMaskForGaps) { 4299 4300 if (UseMaskForCond || UseMaskForGaps) 4301 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4302 Alignment, AddressSpace, 4303 UseMaskForCond, UseMaskForGaps); 4304 4305 // VecTy for interleave memop is <VF*Factor x Elt>. 4306 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4307 // VecTy = <12 x i32>. 4308 4309 // Calculate the number of memory operations (NumOfMemOps), required 4310 // for load/store the VecTy. 4311 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4312 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4313 unsigned LegalVTSize = LegalVT.getStoreSize(); 4314 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4315 4316 // Get the cost of one memory operation. 4317 auto *SingleMemOpTy = 4318 VectorType::get(cast<VectorType>(VecTy)->getElementType(), 4319 LegalVT.getVectorNumElements()); 4320 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 4321 MaybeAlign(Alignment), AddressSpace); 4322 4323 unsigned VF = cast<VectorType>(VecTy)->getNumElements() / Factor; 4324 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 4325 4326 if (Opcode == Instruction::Load) { 4327 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 4328 // contain the cost of the optimized shuffle sequence that the 4329 // X86InterleavedAccess pass will generate. 4330 // The cost of loads and stores are computed separately from the table. 4331 4332 // X86InterleavedAccess support only the following interleaved-access group. 4333 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 4334 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 4335 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 4336 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 4337 }; 4338 4339 if (const auto *Entry = 4340 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 4341 return NumOfMemOps * MemOpCost + Entry->Cost; 4342 //If an entry does not exist, fallback to the default implementation. 4343 4344 // Kind of shuffle depends on number of loaded values. 4345 // If we load the entire data in one register, we can use a 1-src shuffle. 4346 // Otherwise, we'll merge 2 sources in each operation. 4347 TTI::ShuffleKind ShuffleKind = 4348 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 4349 4350 unsigned ShuffleCost = 4351 getShuffleCost(ShuffleKind, SingleMemOpTy, 0, nullptr); 4352 4353 unsigned NumOfLoadsInInterleaveGrp = 4354 Indices.size() ? Indices.size() : Factor; 4355 Type *ResultTy = 4356 VectorType::get(cast<VectorType>(VecTy)->getElementType(), 4357 cast<VectorType>(VecTy)->getNumElements() / Factor); 4358 unsigned NumOfResults = 4359 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 4360 NumOfLoadsInInterleaveGrp; 4361 4362 // About a half of the loads may be folded in shuffles when we have only 4363 // one result. If we have more than one result, we do not fold loads at all. 4364 unsigned NumOfUnfoldedLoads = 4365 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 4366 4367 // Get a number of shuffle operations per result. 4368 unsigned NumOfShufflesPerResult = 4369 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 4370 4371 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4372 // When we have more than one destination, we need additional instructions 4373 // to keep sources. 4374 unsigned NumOfMoves = 0; 4375 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 4376 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 4377 4378 int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 4379 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 4380 4381 return Cost; 4382 } 4383 4384 // Store. 4385 assert(Opcode == Instruction::Store && 4386 "Expected Store Instruction at this point"); 4387 // X86InterleavedAccess support only the following interleaved-access group. 4388 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 4389 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 4390 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 4391 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 4392 4393 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 4394 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 4395 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 4396 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 4397 }; 4398 4399 if (const auto *Entry = 4400 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 4401 return NumOfMemOps * MemOpCost + Entry->Cost; 4402 //If an entry does not exist, fallback to the default implementation. 4403 4404 // There is no strided stores meanwhile. And store can't be folded in 4405 // shuffle. 4406 unsigned NumOfSources = Factor; // The number of values to be merged. 4407 unsigned ShuffleCost = 4408 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, 0, nullptr); 4409 unsigned NumOfShufflesPerStore = NumOfSources - 1; 4410 4411 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4412 // We need additional instructions to keep sources. 4413 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 4414 int Cost = NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 4415 NumOfMoves; 4416 return Cost; 4417 } 4418 4419 int X86TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, 4420 unsigned Factor, 4421 ArrayRef<unsigned> Indices, 4422 unsigned Alignment, 4423 unsigned AddressSpace, 4424 bool UseMaskForCond, 4425 bool UseMaskForGaps) { 4426 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 4427 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 4428 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 4429 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 4430 return true; 4431 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 4432 return HasBW; 4433 return false; 4434 }; 4435 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 4436 return getInterleavedMemoryOpCostAVX512(Opcode, VecTy, Factor, Indices, 4437 Alignment, AddressSpace, 4438 UseMaskForCond, UseMaskForGaps); 4439 if (ST->hasAVX2()) 4440 return getInterleavedMemoryOpCostAVX2(Opcode, VecTy, Factor, Indices, 4441 Alignment, AddressSpace, 4442 UseMaskForCond, UseMaskForGaps); 4443 4444 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4445 Alignment, AddressSpace, 4446 UseMaskForCond, UseMaskForGaps); 4447 } 4448