1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // X86 cost model. 56 // 57 //===----------------------------------------------------------------------===// 58 59 TargetTransformInfo::PopcntSupportKind 60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 61 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 62 // TODO: Currently the __builtin_popcount() implementation using SSE3 63 // instructions is inefficient. Once the problem is fixed, we should 64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 66 } 67 68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 69 TargetTransformInfo::CacheLevel Level) const { 70 switch (Level) { 71 case TargetTransformInfo::CacheLevel::L1D: 72 // - Penryn 73 // - Nehalem 74 // - Westmere 75 // - Sandy Bridge 76 // - Ivy Bridge 77 // - Haswell 78 // - Broadwell 79 // - Skylake 80 // - Kabylake 81 return 32 * 1024; // 32 KByte 82 case TargetTransformInfo::CacheLevel::L2D: 83 // - Penryn 84 // - Nehalem 85 // - Westmere 86 // - Sandy Bridge 87 // - Ivy Bridge 88 // - Haswell 89 // - Broadwell 90 // - Skylake 91 // - Kabylake 92 return 256 * 1024; // 256 KByte 93 } 94 95 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 96 } 97 98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 99 TargetTransformInfo::CacheLevel Level) const { 100 // - Penryn 101 // - Nehalem 102 // - Westmere 103 // - Sandy Bridge 104 // - Ivy Bridge 105 // - Haswell 106 // - Broadwell 107 // - Skylake 108 // - Kabylake 109 switch (Level) { 110 case TargetTransformInfo::CacheLevel::L1D: 111 LLVM_FALLTHROUGH; 112 case TargetTransformInfo::CacheLevel::L2D: 113 return 8; 114 } 115 116 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 117 } 118 119 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 120 bool Vector = (ClassID == 1); 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const { 133 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 134 if (Vector) { 135 if (ST->hasAVX512() && PreferVectorWidth >= 512) 136 return 512; 137 if (ST->hasAVX() && PreferVectorWidth >= 256) 138 return 256; 139 if (ST->hasSSE1() && PreferVectorWidth >= 128) 140 return 128; 141 return 0; 142 } 143 144 if (ST->is64Bit()) 145 return 64; 146 147 return 32; 148 } 149 150 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 151 return getRegisterBitWidth(true); 152 } 153 154 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 155 // If the loop will not be vectorized, don't interleave the loop. 156 // Let regular unroll to unroll the loop, which saves the overflow 157 // check and memory check cost. 158 if (VF == 1) 159 return 1; 160 161 if (ST->isAtom()) 162 return 1; 163 164 // Sandybridge and Haswell have multiple execution ports and pipelined 165 // vector units. 166 if (ST->hasAVX()) 167 return 4; 168 169 return 2; 170 } 171 172 int X86TTIImpl::getArithmeticInstrCost(unsigned Opcode, Type *Ty, 173 TTI::OperandValueKind Op1Info, 174 TTI::OperandValueKind Op2Info, 175 TTI::OperandValueProperties Opd1PropInfo, 176 TTI::OperandValueProperties Opd2PropInfo, 177 ArrayRef<const Value *> Args, 178 const Instruction *CxtI) { 179 // Legalize the type. 180 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 181 182 int ISD = TLI->InstructionOpcodeToISD(Opcode); 183 assert(ISD && "Invalid opcode"); 184 185 static const CostTblEntry GLMCostTable[] = { 186 { ISD::FDIV, MVT::f32, 18 }, // divss 187 { ISD::FDIV, MVT::v4f32, 35 }, // divps 188 { ISD::FDIV, MVT::f64, 33 }, // divsd 189 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 190 }; 191 192 if (ST->useGLMDivSqrtCosts()) 193 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 194 LT.second)) 195 return LT.first * Entry->Cost; 196 197 static const CostTblEntry SLMCostTable[] = { 198 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 199 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 200 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. 201 { ISD::FMUL, MVT::f64, 2 }, // mulsd 202 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 203 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 204 { ISD::FDIV, MVT::f32, 17 }, // divss 205 { ISD::FDIV, MVT::v4f32, 39 }, // divps 206 { ISD::FDIV, MVT::f64, 32 }, // divsd 207 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 208 { ISD::FADD, MVT::v2f64, 2 }, // addpd 209 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 210 // v2i64/v4i64 mul is custom lowered as a series of long: 211 // multiplies(3), shifts(3) and adds(2) 212 // slm muldq version throughput is 2 and addq throughput 4 213 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 214 // 3X4 (addq throughput) = 17 215 { ISD::MUL, MVT::v2i64, 17 }, 216 // slm addq\subq throughput is 4 217 { ISD::ADD, MVT::v2i64, 4 }, 218 { ISD::SUB, MVT::v2i64, 4 }, 219 }; 220 221 if (ST->isSLM()) { 222 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 223 // Check if the operands can be shrinked into a smaller datatype. 224 bool Op1Signed = false; 225 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 226 bool Op2Signed = false; 227 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 228 229 bool signedMode = Op1Signed | Op2Signed; 230 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 231 232 if (OpMinSize <= 7) 233 return LT.first * 3; // pmullw/sext 234 if (!signedMode && OpMinSize <= 8) 235 return LT.first * 3; // pmullw/zext 236 if (OpMinSize <= 15) 237 return LT.first * 5; // pmullw/pmulhw/pshuf 238 if (!signedMode && OpMinSize <= 16) 239 return LT.first * 5; // pmullw/pmulhw/pshuf 240 } 241 242 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 243 LT.second)) { 244 return LT.first * Entry->Cost; 245 } 246 } 247 248 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 249 ISD == ISD::UREM) && 250 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 251 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 252 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 253 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 254 // On X86, vector signed division by constants power-of-two are 255 // normally expanded to the sequence SRA + SRL + ADD + SRA. 256 // The OperandValue properties may not be the same as that of the previous 257 // operation; conservatively assume OP_None. 258 int Cost = 259 2 * getArithmeticInstrCost(Instruction::AShr, Ty, Op1Info, Op2Info, 260 TargetTransformInfo::OP_None, 261 TargetTransformInfo::OP_None); 262 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 263 TargetTransformInfo::OP_None, 264 TargetTransformInfo::OP_None); 265 Cost += getArithmeticInstrCost(Instruction::Add, Ty, Op1Info, Op2Info, 266 TargetTransformInfo::OP_None, 267 TargetTransformInfo::OP_None); 268 269 if (ISD == ISD::SREM) { 270 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 271 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info); 272 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, Op1Info, Op2Info); 273 } 274 275 return Cost; 276 } 277 278 // Vector unsigned division/remainder will be simplified to shifts/masks. 279 if (ISD == ISD::UDIV) 280 return getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 281 TargetTransformInfo::OP_None, 282 TargetTransformInfo::OP_None); 283 284 else // UREM 285 return getArithmeticInstrCost(Instruction::And, Ty, Op1Info, Op2Info, 286 TargetTransformInfo::OP_None, 287 TargetTransformInfo::OP_None); 288 } 289 290 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 291 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 292 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 293 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 294 }; 295 296 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 297 ST->hasBWI()) { 298 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 299 LT.second)) 300 return LT.first * Entry->Cost; 301 } 302 303 static const CostTblEntry AVX512UniformConstCostTable[] = { 304 { ISD::SRA, MVT::v2i64, 1 }, 305 { ISD::SRA, MVT::v4i64, 1 }, 306 { ISD::SRA, MVT::v8i64, 1 }, 307 308 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 309 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 310 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 311 }; 312 313 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 314 ST->hasAVX512()) { 315 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 316 LT.second)) 317 return LT.first * Entry->Cost; 318 } 319 320 static const CostTblEntry AVX2UniformConstCostTable[] = { 321 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 322 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 323 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 324 325 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 326 }; 327 328 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 329 ST->hasAVX2()) { 330 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 331 LT.second)) 332 return LT.first * Entry->Cost; 333 } 334 335 static const CostTblEntry SSE2UniformConstCostTable[] = { 336 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 337 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 338 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 339 340 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 341 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 342 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 343 }; 344 345 // XOP has faster vXi8 shifts. 346 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 347 ST->hasSSE2() && !ST->hasXOP()) { 348 if (const auto *Entry = 349 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 350 return LT.first * Entry->Cost; 351 } 352 353 static const CostTblEntry AVX512BWConstCostTable[] = { 354 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 355 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 356 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 357 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 358 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 359 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 360 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 361 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 362 }; 363 364 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 365 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 366 ST->hasBWI()) { 367 if (const auto *Entry = 368 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 369 return LT.first * Entry->Cost; 370 } 371 372 static const CostTblEntry AVX512ConstCostTable[] = { 373 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 374 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 375 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 376 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 377 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 378 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 379 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 380 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 381 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 382 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 383 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 384 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 385 }; 386 387 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 388 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 389 ST->hasAVX512()) { 390 if (const auto *Entry = 391 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 392 return LT.first * Entry->Cost; 393 } 394 395 static const CostTblEntry AVX2ConstCostTable[] = { 396 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 397 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 398 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 399 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 400 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 401 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 402 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 403 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 404 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 405 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 406 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 407 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 408 }; 409 410 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 411 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 412 ST->hasAVX2()) { 413 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 414 return LT.first * Entry->Cost; 415 } 416 417 static const CostTblEntry SSE2ConstCostTable[] = { 418 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 419 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 420 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 421 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 422 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 423 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 424 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 425 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 426 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 427 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 428 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 429 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 430 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 431 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 432 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 433 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 434 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 435 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 436 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 437 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 438 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 439 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 440 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 441 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 442 }; 443 444 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 445 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 446 ST->hasSSE2()) { 447 // pmuldq sequence. 448 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 449 return LT.first * 32; 450 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 451 return LT.first * 38; 452 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 453 return LT.first * 15; 454 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 455 return LT.first * 20; 456 457 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 458 return LT.first * Entry->Cost; 459 } 460 461 static const CostTblEntry AVX512BWShiftCostTable[] = { 462 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 463 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 464 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 465 466 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 467 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 468 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 469 470 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 471 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 472 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 473 }; 474 475 if (ST->hasBWI()) 476 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 477 return LT.first * Entry->Cost; 478 479 static const CostTblEntry AVX2UniformCostTable[] = { 480 // Uniform splats are cheaper for the following instructions. 481 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 482 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 483 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 484 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 485 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 486 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 487 }; 488 489 if (ST->hasAVX2() && 490 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 491 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 492 if (const auto *Entry = 493 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 494 return LT.first * Entry->Cost; 495 } 496 497 static const CostTblEntry SSE2UniformCostTable[] = { 498 // Uniform splats are cheaper for the following instructions. 499 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 500 { ISD::SHL, MVT::v4i32, 1 }, // pslld 501 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 502 503 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 504 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 505 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 506 507 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 508 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 509 }; 510 511 if (ST->hasSSE2() && 512 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 513 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 514 if (const auto *Entry = 515 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 516 return LT.first * Entry->Cost; 517 } 518 519 static const CostTblEntry AVX512DQCostTable[] = { 520 { ISD::MUL, MVT::v2i64, 1 }, 521 { ISD::MUL, MVT::v4i64, 1 }, 522 { ISD::MUL, MVT::v8i64, 1 } 523 }; 524 525 // Look for AVX512DQ lowering tricks for custom cases. 526 if (ST->hasDQI()) 527 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 528 return LT.first * Entry->Cost; 529 530 static const CostTblEntry AVX512BWCostTable[] = { 531 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 532 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 533 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 534 535 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence. 536 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence. 537 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence. 538 }; 539 540 // Look for AVX512BW lowering tricks for custom cases. 541 if (ST->hasBWI()) 542 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 543 return LT.first * Entry->Cost; 544 545 static const CostTblEntry AVX512CostTable[] = { 546 { ISD::SHL, MVT::v16i32, 1 }, 547 { ISD::SRL, MVT::v16i32, 1 }, 548 { ISD::SRA, MVT::v16i32, 1 }, 549 550 { ISD::SHL, MVT::v8i64, 1 }, 551 { ISD::SRL, MVT::v8i64, 1 }, 552 553 { ISD::SRA, MVT::v2i64, 1 }, 554 { ISD::SRA, MVT::v4i64, 1 }, 555 { ISD::SRA, MVT::v8i64, 1 }, 556 557 { ISD::MUL, MVT::v64i8, 26 }, // extend/pmullw/trunc sequence. 558 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence. 559 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence. 560 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 561 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 562 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 563 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add 564 565 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 566 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 567 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 568 569 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 570 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 571 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 572 }; 573 574 if (ST->hasAVX512()) 575 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 576 return LT.first * Entry->Cost; 577 578 static const CostTblEntry AVX2ShiftCostTable[] = { 579 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 580 // customize them to detect the cases where shift amount is a scalar one. 581 { ISD::SHL, MVT::v4i32, 1 }, 582 { ISD::SRL, MVT::v4i32, 1 }, 583 { ISD::SRA, MVT::v4i32, 1 }, 584 { ISD::SHL, MVT::v8i32, 1 }, 585 { ISD::SRL, MVT::v8i32, 1 }, 586 { ISD::SRA, MVT::v8i32, 1 }, 587 { ISD::SHL, MVT::v2i64, 1 }, 588 { ISD::SRL, MVT::v2i64, 1 }, 589 { ISD::SHL, MVT::v4i64, 1 }, 590 { ISD::SRL, MVT::v4i64, 1 }, 591 }; 592 593 if (ST->hasAVX512()) { 594 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 595 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 596 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 597 // On AVX512, a packed v32i16 shift left by a constant build_vector 598 // is lowered into a vector multiply (vpmullw). 599 return getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info, 600 TargetTransformInfo::OP_None, 601 TargetTransformInfo::OP_None); 602 } 603 604 // Look for AVX2 lowering tricks. 605 if (ST->hasAVX2()) { 606 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 607 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 608 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 609 // On AVX2, a packed v16i16 shift left by a constant build_vector 610 // is lowered into a vector multiply (vpmullw). 611 return getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info, 612 TargetTransformInfo::OP_None, 613 TargetTransformInfo::OP_None); 614 615 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 616 return LT.first * Entry->Cost; 617 } 618 619 static const CostTblEntry XOPShiftCostTable[] = { 620 // 128bit shifts take 1cy, but right shifts require negation beforehand. 621 { ISD::SHL, MVT::v16i8, 1 }, 622 { ISD::SRL, MVT::v16i8, 2 }, 623 { ISD::SRA, MVT::v16i8, 2 }, 624 { ISD::SHL, MVT::v8i16, 1 }, 625 { ISD::SRL, MVT::v8i16, 2 }, 626 { ISD::SRA, MVT::v8i16, 2 }, 627 { ISD::SHL, MVT::v4i32, 1 }, 628 { ISD::SRL, MVT::v4i32, 2 }, 629 { ISD::SRA, MVT::v4i32, 2 }, 630 { ISD::SHL, MVT::v2i64, 1 }, 631 { ISD::SRL, MVT::v2i64, 2 }, 632 { ISD::SRA, MVT::v2i64, 2 }, 633 // 256bit shifts require splitting if AVX2 didn't catch them above. 634 { ISD::SHL, MVT::v32i8, 2+2 }, 635 { ISD::SRL, MVT::v32i8, 4+2 }, 636 { ISD::SRA, MVT::v32i8, 4+2 }, 637 { ISD::SHL, MVT::v16i16, 2+2 }, 638 { ISD::SRL, MVT::v16i16, 4+2 }, 639 { ISD::SRA, MVT::v16i16, 4+2 }, 640 { ISD::SHL, MVT::v8i32, 2+2 }, 641 { ISD::SRL, MVT::v8i32, 4+2 }, 642 { ISD::SRA, MVT::v8i32, 4+2 }, 643 { ISD::SHL, MVT::v4i64, 2+2 }, 644 { ISD::SRL, MVT::v4i64, 4+2 }, 645 { ISD::SRA, MVT::v4i64, 4+2 }, 646 }; 647 648 // Look for XOP lowering tricks. 649 if (ST->hasXOP()) { 650 // If the right shift is constant then we'll fold the negation so 651 // it's as cheap as a left shift. 652 int ShiftISD = ISD; 653 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 654 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 655 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 656 ShiftISD = ISD::SHL; 657 if (const auto *Entry = 658 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 659 return LT.first * Entry->Cost; 660 } 661 662 static const CostTblEntry SSE2UniformShiftCostTable[] = { 663 // Uniform splats are cheaper for the following instructions. 664 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 665 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 666 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 667 668 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 669 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 670 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 671 672 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 673 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 674 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 675 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 676 }; 677 678 if (ST->hasSSE2() && 679 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 680 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 681 682 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 683 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 684 return LT.first * 4; // 2*psrad + shuffle. 685 686 if (const auto *Entry = 687 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 688 return LT.first * Entry->Cost; 689 } 690 691 if (ISD == ISD::SHL && 692 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 693 MVT VT = LT.second; 694 // Vector shift left by non uniform constant can be lowered 695 // into vector multiply. 696 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 697 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 698 ISD = ISD::MUL; 699 } 700 701 static const CostTblEntry AVX2CostTable[] = { 702 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. 703 { ISD::SHL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. 704 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 705 { ISD::SHL, MVT::v32i16, 20 }, // 2*extend/vpsrlvd/pack sequence. 706 707 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. 708 { ISD::SRL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. 709 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 710 { ISD::SRL, MVT::v32i16, 20 }, // 2*extend/vpsrlvd/pack sequence. 711 712 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. 713 { ISD::SRA, MVT::v64i8, 48 }, // 2*vpblendvb sequence. 714 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. 715 { ISD::SRA, MVT::v32i16, 20 }, // 2*extend/vpsravd/pack sequence. 716 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. 717 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 718 719 { ISD::SUB, MVT::v32i8, 1 }, // psubb 720 { ISD::ADD, MVT::v32i8, 1 }, // paddb 721 { ISD::SUB, MVT::v16i16, 1 }, // psubw 722 { ISD::ADD, MVT::v16i16, 1 }, // paddw 723 { ISD::SUB, MVT::v8i32, 1 }, // psubd 724 { ISD::ADD, MVT::v8i32, 1 }, // paddd 725 { ISD::SUB, MVT::v4i64, 1 }, // psubq 726 { ISD::ADD, MVT::v4i64, 1 }, // paddq 727 728 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence. 729 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence. 730 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 731 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 732 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add 733 734 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 735 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 736 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 737 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 738 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 739 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 740 741 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 742 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 743 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 744 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 745 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 746 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 747 }; 748 749 // Look for AVX2 lowering tricks for custom cases. 750 if (ST->hasAVX2()) 751 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 752 return LT.first * Entry->Cost; 753 754 static const CostTblEntry AVX1CostTable[] = { 755 // We don't have to scalarize unsupported ops. We can issue two half-sized 756 // operations and we only need to extract the upper YMM half. 757 // Two ops + 1 extract + 1 insert = 4. 758 { ISD::MUL, MVT::v16i16, 4 }, 759 { ISD::MUL, MVT::v8i32, 4 }, 760 { ISD::SUB, MVT::v32i8, 4 }, 761 { ISD::ADD, MVT::v32i8, 4 }, 762 { ISD::SUB, MVT::v16i16, 4 }, 763 { ISD::ADD, MVT::v16i16, 4 }, 764 { ISD::SUB, MVT::v8i32, 4 }, 765 { ISD::ADD, MVT::v8i32, 4 }, 766 { ISD::SUB, MVT::v4i64, 4 }, 767 { ISD::ADD, MVT::v4i64, 4 }, 768 769 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 770 // are lowered as a series of long multiplies(3), shifts(3) and adds(2) 771 // Because we believe v4i64 to be a legal type, we must also include the 772 // extract+insert in the cost table. Therefore, the cost here is 18 773 // instead of 8. 774 { ISD::MUL, MVT::v4i64, 18 }, 775 776 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence. 777 778 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 779 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 780 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 781 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 782 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 783 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 784 }; 785 786 if (ST->hasAVX()) 787 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 788 return LT.first * Entry->Cost; 789 790 static const CostTblEntry SSE42CostTable[] = { 791 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 792 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 793 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 794 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 795 796 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 797 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 798 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 799 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 800 801 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 802 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 803 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 804 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 805 806 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 807 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 808 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 809 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 810 }; 811 812 if (ST->hasSSE42()) 813 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 814 return LT.first * Entry->Cost; 815 816 static const CostTblEntry SSE41CostTable[] = { 817 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 818 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split. 819 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 820 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 821 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 822 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split 823 824 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 825 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split. 826 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 827 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 828 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 829 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split. 830 831 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 832 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split. 833 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 834 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 835 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 836 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split. 837 838 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 839 }; 840 841 if (ST->hasSSE41()) 842 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 843 return LT.first * Entry->Cost; 844 845 static const CostTblEntry SSE2CostTable[] = { 846 // We don't correctly identify costs of casts because they are marked as 847 // custom. 848 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 849 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 850 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 851 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 852 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 853 854 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 855 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 856 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 857 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 858 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 859 860 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 861 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 862 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 863 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 864 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split. 865 866 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence. 867 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 868 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 869 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 870 871 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 872 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 873 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 874 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 875 876 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 877 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 878 879 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 880 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 881 }; 882 883 if (ST->hasSSE2()) 884 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 885 return LT.first * Entry->Cost; 886 887 static const CostTblEntry SSE1CostTable[] = { 888 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 889 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 890 891 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 892 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 893 894 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 895 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 896 897 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 898 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 899 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 900 901 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 902 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 903 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 904 }; 905 906 if (ST->hasSSE1()) 907 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 908 return LT.first * Entry->Cost; 909 910 // It is not a good idea to vectorize division. We have to scalarize it and 911 // in the process we will often end up having to spilling regular 912 // registers. The overhead of division is going to dominate most kernels 913 // anyways so try hard to prevent vectorization of division - it is 914 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 915 // to hide "20 cycles" for each lane. 916 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 917 ISD == ISD::UDIV || ISD == ISD::UREM)) { 918 int ScalarCost = getArithmeticInstrCost( 919 Opcode, Ty->getScalarType(), Op1Info, Op2Info, 920 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 921 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 922 } 923 924 // Fallback to the default implementation. 925 return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info); 926 } 927 928 int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, VectorType *BaseTp, 929 int Index, VectorType *SubTp) { 930 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 931 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 932 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 933 934 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 935 if (Kind == TTI::SK_Transpose) 936 Kind = TTI::SK_PermuteTwoSrc; 937 938 // For Broadcasts we are splatting the first element from the first input 939 // register, so only need to reference that input and all the output 940 // registers are the same. 941 if (Kind == TTI::SK_Broadcast) 942 LT.first = 1; 943 944 // Subvector extractions are free if they start at the beginning of a 945 // vector and cheap if the subvectors are aligned. 946 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 947 int NumElts = LT.second.getVectorNumElements(); 948 if ((Index % NumElts) == 0) 949 return 0; 950 std::pair<int, MVT> SubLT = TLI->getTypeLegalizationCost(DL, SubTp); 951 if (SubLT.second.isVector()) { 952 int NumSubElts = SubLT.second.getVectorNumElements(); 953 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 954 return SubLT.first; 955 // Handle some cases for widening legalization. For now we only handle 956 // cases where the original subvector was naturally aligned and evenly 957 // fit in its legalized subvector type. 958 // FIXME: Remove some of the alignment restrictions. 959 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 960 // vectors. 961 int OrigSubElts = cast<VectorType>(SubTp)->getNumElements(); 962 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 963 (NumSubElts % OrigSubElts) == 0 && 964 LT.second.getVectorElementType() == 965 SubLT.second.getVectorElementType() && 966 LT.second.getVectorElementType().getSizeInBits() == 967 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 968 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 969 "Unexpected number of elements!"); 970 VectorType *VecTy = VectorType::get(BaseTp->getElementType(), 971 LT.second.getVectorNumElements()); 972 VectorType *SubTy = 973 VectorType::get(BaseTp->getElementType(), 974 SubLT.second.getVectorNumElements()); 975 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 976 int ExtractCost = getShuffleCost(TTI::SK_ExtractSubvector, VecTy, 977 ExtractIndex, SubTy); 978 979 // If the original size is 32-bits or more, we can use pshufd. Otherwise 980 // if we have SSSE3 we can use pshufb. 981 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 982 return ExtractCost + 1; // pshufd or pshufb 983 984 assert(SubTp->getPrimitiveSizeInBits() == 16 && 985 "Unexpected vector size"); 986 987 return ExtractCost + 2; // worst case pshufhw + pshufd 988 } 989 } 990 } 991 992 // Handle some common (illegal) sub-vector types as they are often very cheap 993 // to shuffle even on targets without PSHUFB. 994 EVT VT = TLI->getValueType(DL, BaseTp); 995 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 996 !ST->hasSSSE3()) { 997 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 998 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 999 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1000 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1001 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1002 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1003 1004 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1005 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1006 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1007 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1008 1009 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1010 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1011 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1012 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1013 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1014 1015 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1016 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1017 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1018 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1019 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1020 }; 1021 1022 if (ST->hasSSE2()) 1023 if (const auto *Entry = 1024 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1025 return Entry->Cost; 1026 } 1027 1028 // We are going to permute multiple sources and the result will be in multiple 1029 // destinations. Providing an accurate cost only for splits where the element 1030 // type remains the same. 1031 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1032 MVT LegalVT = LT.second; 1033 if (LegalVT.isVector() && 1034 LegalVT.getVectorElementType().getSizeInBits() == 1035 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1036 LegalVT.getVectorNumElements() < BaseTp->getNumElements()) { 1037 1038 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1039 unsigned LegalVTSize = LegalVT.getStoreSize(); 1040 // Number of source vectors after legalization: 1041 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1042 // Number of destination vectors after legalization: 1043 unsigned NumOfDests = LT.first; 1044 1045 VectorType *SingleOpTy = 1046 VectorType::get(BaseTp->getElementType(), 1047 LegalVT.getVectorNumElements()); 1048 1049 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1050 return NumOfShuffles * 1051 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 0, nullptr); 1052 } 1053 1054 return BaseT::getShuffleCost(Kind, BaseTp, Index, SubTp); 1055 } 1056 1057 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1058 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1059 // We assume that source and destination have the same vector type. 1060 int NumOfDests = LT.first; 1061 int NumOfShufflesPerDest = LT.first * 2 - 1; 1062 LT.first = NumOfDests * NumOfShufflesPerDest; 1063 } 1064 1065 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1066 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1067 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1068 1069 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1070 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1071 1072 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 1}, // vpermt2b 1073 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 1}, // vpermt2b 1074 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1} // vpermt2b 1075 }; 1076 1077 if (ST->hasVBMI()) 1078 if (const auto *Entry = 1079 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1080 return LT.first * Entry->Cost; 1081 1082 static const CostTblEntry AVX512BWShuffleTbl[] = { 1083 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1084 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1085 1086 {TTI::SK_Reverse, MVT::v32i16, 1}, // vpermw 1087 {TTI::SK_Reverse, MVT::v16i16, 1}, // vpermw 1088 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1089 1090 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 1}, // vpermw 1091 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 1}, // vpermw 1092 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // vpermw 1093 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1094 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 3}, // vpermw + zext/trunc 1095 1096 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 1}, // vpermt2w 1097 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 1}, // vpermt2w 1098 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpermt2w 1099 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 3}, // zext + vpermt2w + trunc 1100 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1101 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3} // zext + vpermt2w + trunc 1102 }; 1103 1104 if (ST->hasBWI()) 1105 if (const auto *Entry = 1106 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1107 return LT.first * Entry->Cost; 1108 1109 static const CostTblEntry AVX512ShuffleTbl[] = { 1110 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1111 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1112 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1113 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1114 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1115 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1116 1117 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1118 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1119 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1120 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1121 1122 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1123 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1124 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1125 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1126 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1127 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1128 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1129 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1130 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1131 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1132 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1133 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1134 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1135 1136 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1137 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1138 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1139 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1140 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1141 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1142 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1143 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1144 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1145 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1146 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1147 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1148 1149 // FIXME: This just applies the type legalization cost rules above 1150 // assuming these completely split. 1151 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1152 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1153 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1154 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1155 }; 1156 1157 if (ST->hasAVX512()) 1158 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1159 return LT.first * Entry->Cost; 1160 1161 static const CostTblEntry AVX2ShuffleTbl[] = { 1162 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1163 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1164 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1165 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1166 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1167 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1168 1169 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1170 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1171 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1172 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1173 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1174 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1175 1176 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1177 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1178 1179 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1180 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1181 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1182 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1183 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1184 // + vpblendvb 1185 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1186 // + vpblendvb 1187 1188 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1189 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1190 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1191 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1192 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1193 // + vpblendvb 1194 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1195 // + vpblendvb 1196 }; 1197 1198 if (ST->hasAVX2()) 1199 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1200 return LT.first * Entry->Cost; 1201 1202 static const CostTblEntry XOPShuffleTbl[] = { 1203 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1204 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1205 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1206 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1207 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1208 // + vinsertf128 1209 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1210 // + vinsertf128 1211 1212 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1213 // + vinsertf128 1214 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1215 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1216 // + vinsertf128 1217 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1218 }; 1219 1220 if (ST->hasXOP()) 1221 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1222 return LT.first * Entry->Cost; 1223 1224 static const CostTblEntry AVX1ShuffleTbl[] = { 1225 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1226 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1227 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1228 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1229 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1230 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1231 1232 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1233 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1234 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1235 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1236 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1237 // + vinsertf128 1238 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1239 // + vinsertf128 1240 1241 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1242 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1243 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1244 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1245 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1246 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1247 1248 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1249 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1250 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1251 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1252 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1253 // + 2*por + vinsertf128 1254 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1255 // + 2*por + vinsertf128 1256 1257 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1258 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1259 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1260 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1261 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1262 // + 4*por + vinsertf128 1263 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1264 // + 4*por + vinsertf128 1265 }; 1266 1267 if (ST->hasAVX()) 1268 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1269 return LT.first * Entry->Cost; 1270 1271 static const CostTblEntry SSE41ShuffleTbl[] = { 1272 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1273 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1274 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1275 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1276 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1277 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1278 }; 1279 1280 if (ST->hasSSE41()) 1281 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1282 return LT.first * Entry->Cost; 1283 1284 static const CostTblEntry SSSE3ShuffleTbl[] = { 1285 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1286 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1287 1288 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1289 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1290 1291 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1292 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1293 1294 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1295 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1296 1297 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1298 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1299 }; 1300 1301 if (ST->hasSSSE3()) 1302 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1303 return LT.first * Entry->Cost; 1304 1305 static const CostTblEntry SSE2ShuffleTbl[] = { 1306 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1307 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1308 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1309 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1310 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1311 1312 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1313 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1314 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1315 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1316 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1317 // + 2*pshufd + 2*unpck + packus 1318 1319 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1320 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1321 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1322 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1323 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1324 1325 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1326 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1327 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1328 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1329 // + pshufd/unpck 1330 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1331 // + 2*pshufd + 2*unpck + 2*packus 1332 1333 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1334 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1335 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1336 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1337 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1338 }; 1339 1340 if (ST->hasSSE2()) 1341 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1342 return LT.first * Entry->Cost; 1343 1344 static const CostTblEntry SSE1ShuffleTbl[] = { 1345 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1346 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1347 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1348 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1349 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1350 }; 1351 1352 if (ST->hasSSE1()) 1353 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1354 return LT.first * Entry->Cost; 1355 1356 return BaseT::getShuffleCost(Kind, BaseTp, Index, SubTp); 1357 } 1358 1359 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 1360 const Instruction *I) { 1361 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1362 assert(ISD && "Invalid opcode"); 1363 1364 // FIXME: Need a better design of the cost table to handle non-simple types of 1365 // potential massive combinations (elem_num x src_type x dst_type). 1366 1367 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1368 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1369 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1370 1371 // Mask sign extend has an instruction. 1372 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1373 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1374 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1375 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1376 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1377 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1378 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1379 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1380 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1381 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1382 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1383 1384 // Mask zero extend is a sext + shift. 1385 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1386 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1387 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1388 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1389 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1390 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1391 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1392 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1393 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1394 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1395 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1396 1397 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, 1398 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm 1399 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // widen to zmm 1400 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // widen to zmm 1401 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // widen to zmm 1402 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // widen to zmm 1403 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // widen to zmm 1404 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // widen to zmm 1405 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // widen to zmm 1406 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // widen to zmm 1407 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // widen to zmm 1408 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, 1409 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, 1410 }; 1411 1412 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1413 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1414 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1415 1416 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1417 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1418 1419 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1420 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1421 1422 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1423 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1424 }; 1425 1426 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1427 // 256-bit wide vectors. 1428 1429 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1430 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1431 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1432 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1433 1434 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1435 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1436 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1437 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd 1438 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1439 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1440 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1441 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd 1442 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd 1443 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd 1444 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd 1445 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd 1446 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq 1447 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq 1448 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq 1449 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, 1450 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, 1451 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, 1452 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, 1453 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 1454 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb 1455 1456 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32 1457 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, 1458 1459 // Sign extend is zmm vpternlogd+vptruncdb. 1460 // Zero extend is zmm broadcast load+vptruncdw. 1461 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 }, 1462 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 }, 1463 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, 1464 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, 1465 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, 1466 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, 1467 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 }, 1468 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 }, 1469 1470 // Sign extend is zmm vpternlogd+vptruncdw. 1471 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw. 1472 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 }, 1473 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1474 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 }, 1475 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1476 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 }, 1477 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1478 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 }, 1479 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1480 1481 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd 1482 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld 1483 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd 1484 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld 1485 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd 1486 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld 1487 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq 1488 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq 1489 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq 1490 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq 1491 1492 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd 1493 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld 1494 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq 1495 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq 1496 1497 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1498 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1499 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1500 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1501 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1502 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1503 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1504 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1505 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1506 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1507 1508 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1509 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1510 1511 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1512 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1513 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1514 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1515 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1516 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1517 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1518 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1519 1520 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1521 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1522 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1523 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1524 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1525 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1526 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1527 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1528 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1529 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1530 1531 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f64, 3 }, 1532 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, 1533 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 3 }, 1534 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 3 }, 1535 1536 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1537 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, 1538 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, 1539 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1540 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, 1541 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, 1542 }; 1543 1544 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1545 // Mask sign extend has an instruction. 1546 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1547 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1548 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1549 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1550 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1551 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1552 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1553 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1554 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1555 1556 // Mask zero extend is a sext + shift. 1557 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1558 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1559 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1560 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1561 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1562 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1563 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1564 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1565 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1566 1567 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, 1568 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // vpsllw+vptestmb 1569 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // vpsllw+vptestmw 1570 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // vpsllw+vptestmb 1571 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // vpsllw+vptestmw 1572 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // vpsllw+vptestmb 1573 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // vpsllw+vptestmw 1574 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // vpsllw+vptestmb 1575 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // vpsllw+vptestmw 1576 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // vpsllw+vptestmb 1577 }; 1578 1579 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1580 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1581 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1582 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1583 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1584 1585 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1586 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1587 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1588 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1589 1590 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1591 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1592 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1593 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1594 1595 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1596 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1597 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1598 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1599 }; 1600 1601 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 1602 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1603 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1604 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1605 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 8 }, // split+2*v8i8 1606 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1607 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1608 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1609 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16 1610 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // vpslld+vptestmd 1611 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd 1612 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // vpslld+vptestmd 1613 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // vpsllq+vptestmq 1614 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // vpsllq+vptestmq 1615 1616 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb 1617 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb 1618 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 }, 1619 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 }, 1620 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 }, 1621 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 }, 1622 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 }, 1623 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 }, 1624 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 }, 1625 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 }, 1626 1627 // sign extend is vpcmpeq+maskedmove+vpmovdw 1628 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw 1629 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1630 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 }, 1631 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1632 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 }, 1633 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1634 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 }, 1635 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 }, 1636 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 }, 1637 1638 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd 1639 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld 1640 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd 1641 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld 1642 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd 1643 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld 1644 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq 1645 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq 1646 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq 1647 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq 1648 1649 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1650 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1651 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1652 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1653 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1654 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1655 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1656 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1657 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1658 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1659 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1660 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1661 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1662 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1663 1664 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 1665 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1666 1667 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 3 }, 1668 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 3 }, 1669 1670 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 1671 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 1672 1673 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1674 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1675 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 1 }, 1676 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1677 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1678 }; 1679 1680 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1681 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1682 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1683 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1684 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1685 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1686 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1687 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1688 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1689 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1690 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1691 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1692 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1693 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1694 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1695 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1696 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1697 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1698 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1699 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1700 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1701 1702 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 1703 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 1704 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1705 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 1706 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1707 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 }, 1708 1709 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1710 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1711 1712 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1713 }; 1714 1715 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1716 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1717 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1718 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1719 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1720 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1721 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1722 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1723 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1724 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1725 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1726 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1727 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1728 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 4 }, 1729 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1730 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1731 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1732 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1733 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1734 1735 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 1736 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1737 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1738 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1739 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 1740 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 }, 1741 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 11 }, 1742 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 9 }, 1743 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 }, 1744 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 11 }, 1745 1746 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1747 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1748 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1749 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1750 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1751 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1752 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1753 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1754 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1755 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1756 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1757 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1758 1759 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1760 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1761 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1762 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1763 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1764 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1765 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1766 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1767 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1768 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 }, 1769 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 1770 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1771 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 1772 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1773 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1774 // The generic code to compute the scalar overhead is currently broken. 1775 // Workaround this limitation by estimating the scalarization overhead 1776 // here. We have roughly 10 instructions per scalar element. 1777 // Multiply that by the vector width. 1778 // FIXME: remove that when PR19268 is fixed. 1779 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1780 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1781 1782 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 4 }, 1783 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f64, 3 }, 1784 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f64, 2 }, 1785 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 3 }, 1786 1787 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f64, 3 }, 1788 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f64, 2 }, 1789 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 4 }, 1790 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 3 }, 1791 // This node is expanded into scalarized operations but BasicTTI is overly 1792 // optimistic estimating its cost. It computes 3 per element (one 1793 // vector-extract, one scalar conversion and one vector-insert). The 1794 // problem is that the inserts form a read-modify-write chain so latency 1795 // should be factored in too. Inflating the cost per element by 1. 1796 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, 1797 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 1798 1799 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 1800 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 1801 }; 1802 1803 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 1804 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1805 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1806 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1807 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1808 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1809 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1810 1811 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1812 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 }, 1813 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1814 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1815 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1816 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1817 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1818 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1819 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1820 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1821 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1822 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1823 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1824 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1825 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1826 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1827 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1828 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1829 1830 // These truncates end up widening elements. 1831 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 1 }, // PMOVXZBQ 1832 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 1 }, // PMOVXZWQ 1833 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 1 }, // PMOVXZBD 1834 1835 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 1 }, 1836 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 1 }, 1837 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 1838 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 1839 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 1840 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 1841 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 1842 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 1843 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 1 }, // PSHUFB 1844 1845 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 1846 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 1847 1848 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 3 }, 1849 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 3 }, 1850 1851 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 3 }, 1852 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 3 }, 1853 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, 1854 }; 1855 1856 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 1857 // These are somewhat magic numbers justified by looking at the output of 1858 // Intel's IACA, running some kernels and making sure when we take 1859 // legalization into account the throughput will be overestimated. 1860 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1861 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1862 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1863 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1864 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1865 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 2*10 }, 1866 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2*10 }, 1867 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1868 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 1869 1870 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1871 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1872 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1873 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1874 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1875 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, 1876 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 }, 1877 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1878 1879 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 4 }, 1880 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 2 }, 1881 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, 1882 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, 1883 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, 1884 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 4 }, 1885 1886 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 1 }, 1887 1888 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 6 }, 1889 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 }, 1890 1891 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 1892 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 1893 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 4 }, 1894 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 4 }, 1895 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 }, 1896 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 2 }, 1897 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 }, 1898 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 4 }, 1899 1900 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1901 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 1902 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 1903 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 1904 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1905 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 1906 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1907 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 1908 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1909 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1910 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1911 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1912 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 1913 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 1914 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1915 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 1916 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1917 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 1918 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1919 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1920 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 1921 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 1922 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1923 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 1924 1925 // These truncates are really widening elements. 1926 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 1 }, // PSHUFD 1927 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // PUNPCKLWD+DQ 1928 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // PUNPCKLBW+WD+PSHUFD 1929 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 1 }, // PUNPCKLWD 1930 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // PUNPCKLBW+WD 1931 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 1 }, // PUNPCKLBW 1932 1933 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // PAND+PACKUSWB 1934 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // PAND+PACKUSWB 1935 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // PAND+PACKUSWB 1936 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 1937 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 3 }, // PAND+2*PACKUSWB 1938 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 1939 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 1940 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 1941 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1942 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 1943 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1944 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 1945 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 1946 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 1947 { ISD::TRUNCATE, MVT::v2i32, MVT::v2i64, 1 }, // PSHUFD 1948 }; 1949 1950 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 1951 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst); 1952 1953 if (ST->hasSSE2() && !ST->hasAVX()) { 1954 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1955 LTDest.second, LTSrc.second)) 1956 return LTSrc.first * Entry->Cost; 1957 } 1958 1959 EVT SrcTy = TLI->getValueType(DL, Src); 1960 EVT DstTy = TLI->getValueType(DL, Dst); 1961 1962 // The function getSimpleVT only handles simple value types. 1963 if (!SrcTy.isSimple() || !DstTy.isSimple()) 1964 return BaseT::getCastInstrCost(Opcode, Dst, Src); 1965 1966 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 1967 MVT SimpleDstTy = DstTy.getSimpleVT(); 1968 1969 if (ST->useAVX512Regs()) { 1970 if (ST->hasBWI()) 1971 if (const auto *Entry = ConvertCostTableLookup(AVX512BWConversionTbl, ISD, 1972 SimpleDstTy, SimpleSrcTy)) 1973 return Entry->Cost; 1974 1975 if (ST->hasDQI()) 1976 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 1977 SimpleDstTy, SimpleSrcTy)) 1978 return Entry->Cost; 1979 1980 if (ST->hasAVX512()) 1981 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 1982 SimpleDstTy, SimpleSrcTy)) 1983 return Entry->Cost; 1984 } 1985 1986 if (ST->hasBWI()) 1987 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 1988 SimpleDstTy, SimpleSrcTy)) 1989 return Entry->Cost; 1990 1991 if (ST->hasDQI()) 1992 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 1993 SimpleDstTy, SimpleSrcTy)) 1994 return Entry->Cost; 1995 1996 if (ST->hasAVX512()) 1997 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 1998 SimpleDstTy, SimpleSrcTy)) 1999 return Entry->Cost; 2000 2001 if (ST->hasAVX2()) { 2002 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2003 SimpleDstTy, SimpleSrcTy)) 2004 return Entry->Cost; 2005 } 2006 2007 if (ST->hasAVX()) { 2008 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2009 SimpleDstTy, SimpleSrcTy)) 2010 return Entry->Cost; 2011 } 2012 2013 if (ST->hasSSE41()) { 2014 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2015 SimpleDstTy, SimpleSrcTy)) 2016 return Entry->Cost; 2017 } 2018 2019 if (ST->hasSSE2()) { 2020 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2021 SimpleDstTy, SimpleSrcTy)) 2022 return Entry->Cost; 2023 } 2024 2025 return BaseT::getCastInstrCost(Opcode, Dst, Src, I); 2026 } 2027 2028 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 2029 const Instruction *I) { 2030 // Legalize the type. 2031 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2032 2033 MVT MTy = LT.second; 2034 2035 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2036 assert(ISD && "Invalid opcode"); 2037 2038 unsigned ExtraCost = 0; 2039 if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) { 2040 // Some vector comparison predicates cost extra instructions. 2041 if (MTy.isVector() && 2042 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 2043 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 2044 ST->hasBWI())) { 2045 switch (cast<CmpInst>(I)->getPredicate()) { 2046 case CmpInst::Predicate::ICMP_NE: 2047 // xor(cmpeq(x,y),-1) 2048 ExtraCost = 1; 2049 break; 2050 case CmpInst::Predicate::ICMP_SGE: 2051 case CmpInst::Predicate::ICMP_SLE: 2052 // xor(cmpgt(x,y),-1) 2053 ExtraCost = 1; 2054 break; 2055 case CmpInst::Predicate::ICMP_ULT: 2056 case CmpInst::Predicate::ICMP_UGT: 2057 // cmpgt(xor(x,signbit),xor(y,signbit)) 2058 // xor(cmpeq(pmaxu(x,y),x),-1) 2059 ExtraCost = 2; 2060 break; 2061 case CmpInst::Predicate::ICMP_ULE: 2062 case CmpInst::Predicate::ICMP_UGE: 2063 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 2064 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 2065 // cmpeq(psubus(x,y),0) 2066 // cmpeq(pminu(x,y),x) 2067 ExtraCost = 1; 2068 } else { 2069 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 2070 ExtraCost = 3; 2071 } 2072 break; 2073 default: 2074 break; 2075 } 2076 } 2077 } 2078 2079 static const CostTblEntry SLMCostTbl[] = { 2080 // slm pcmpeq/pcmpgt throughput is 2 2081 { ISD::SETCC, MVT::v2i64, 2 }, 2082 }; 2083 2084 static const CostTblEntry AVX512BWCostTbl[] = { 2085 { ISD::SETCC, MVT::v32i16, 1 }, 2086 { ISD::SETCC, MVT::v64i8, 1 }, 2087 2088 { ISD::SELECT, MVT::v32i16, 1 }, 2089 { ISD::SELECT, MVT::v64i8, 1 }, 2090 }; 2091 2092 static const CostTblEntry AVX512CostTbl[] = { 2093 { ISD::SETCC, MVT::v8i64, 1 }, 2094 { ISD::SETCC, MVT::v16i32, 1 }, 2095 { ISD::SETCC, MVT::v8f64, 1 }, 2096 { ISD::SETCC, MVT::v16f32, 1 }, 2097 2098 { ISD::SELECT, MVT::v8i64, 1 }, 2099 { ISD::SELECT, MVT::v16i32, 1 }, 2100 { ISD::SELECT, MVT::v8f64, 1 }, 2101 { ISD::SELECT, MVT::v16f32, 1 }, 2102 2103 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 2104 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 2105 2106 { ISD::SELECT, MVT::v32i16, 2 }, // FIXME: should be 3 2107 { ISD::SELECT, MVT::v64i8, 2 }, // FIXME: should be 3 2108 }; 2109 2110 static const CostTblEntry AVX2CostTbl[] = { 2111 { ISD::SETCC, MVT::v4i64, 1 }, 2112 { ISD::SETCC, MVT::v8i32, 1 }, 2113 { ISD::SETCC, MVT::v16i16, 1 }, 2114 { ISD::SETCC, MVT::v32i8, 1 }, 2115 2116 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 2117 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 2118 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 2119 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 2120 }; 2121 2122 static const CostTblEntry AVX1CostTbl[] = { 2123 { ISD::SETCC, MVT::v4f64, 1 }, 2124 { ISD::SETCC, MVT::v8f32, 1 }, 2125 // AVX1 does not support 8-wide integer compare. 2126 { ISD::SETCC, MVT::v4i64, 4 }, 2127 { ISD::SETCC, MVT::v8i32, 4 }, 2128 { ISD::SETCC, MVT::v16i16, 4 }, 2129 { ISD::SETCC, MVT::v32i8, 4 }, 2130 2131 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 2132 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 2133 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 2134 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 2135 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 2136 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 2137 }; 2138 2139 static const CostTblEntry SSE42CostTbl[] = { 2140 { ISD::SETCC, MVT::v2f64, 1 }, 2141 { ISD::SETCC, MVT::v4f32, 1 }, 2142 { ISD::SETCC, MVT::v2i64, 1 }, 2143 }; 2144 2145 static const CostTblEntry SSE41CostTbl[] = { 2146 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 2147 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 2148 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 2149 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 2150 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 2151 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 2152 }; 2153 2154 static const CostTblEntry SSE2CostTbl[] = { 2155 { ISD::SETCC, MVT::v2f64, 2 }, 2156 { ISD::SETCC, MVT::f64, 1 }, 2157 { ISD::SETCC, MVT::v2i64, 8 }, 2158 { ISD::SETCC, MVT::v4i32, 1 }, 2159 { ISD::SETCC, MVT::v8i16, 1 }, 2160 { ISD::SETCC, MVT::v16i8, 1 }, 2161 2162 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 2163 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 2164 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 2165 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 2166 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 2167 }; 2168 2169 static const CostTblEntry SSE1CostTbl[] = { 2170 { ISD::SETCC, MVT::v4f32, 2 }, 2171 { ISD::SETCC, MVT::f32, 1 }, 2172 2173 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 2174 }; 2175 2176 if (ST->isSLM()) 2177 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2178 return LT.first * (ExtraCost + Entry->Cost); 2179 2180 if (ST->hasBWI()) 2181 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2182 return LT.first * (ExtraCost + Entry->Cost); 2183 2184 if (ST->hasAVX512()) 2185 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2186 return LT.first * (ExtraCost + Entry->Cost); 2187 2188 if (ST->hasAVX2()) 2189 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2190 return LT.first * (ExtraCost + Entry->Cost); 2191 2192 if (ST->hasAVX()) 2193 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2194 return LT.first * (ExtraCost + Entry->Cost); 2195 2196 if (ST->hasSSE42()) 2197 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2198 return LT.first * (ExtraCost + Entry->Cost); 2199 2200 if (ST->hasSSE41()) 2201 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2202 return LT.first * (ExtraCost + Entry->Cost); 2203 2204 if (ST->hasSSE2()) 2205 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2206 return LT.first * (ExtraCost + Entry->Cost); 2207 2208 if (ST->hasSSE1()) 2209 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2210 return LT.first * (ExtraCost + Entry->Cost); 2211 2212 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I); 2213 } 2214 2215 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2216 2217 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 2218 ArrayRef<Type *> Tys, FastMathFlags FMF, 2219 unsigned ScalarizationCostPassed, 2220 const Instruction *I) { 2221 // Costs should match the codegen from: 2222 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2223 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2224 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2225 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2226 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2227 static const CostTblEntry AVX512CDCostTbl[] = { 2228 { ISD::CTLZ, MVT::v8i64, 1 }, 2229 { ISD::CTLZ, MVT::v16i32, 1 }, 2230 { ISD::CTLZ, MVT::v32i16, 8 }, 2231 { ISD::CTLZ, MVT::v64i8, 20 }, 2232 { ISD::CTLZ, MVT::v4i64, 1 }, 2233 { ISD::CTLZ, MVT::v8i32, 1 }, 2234 { ISD::CTLZ, MVT::v16i16, 4 }, 2235 { ISD::CTLZ, MVT::v32i8, 10 }, 2236 { ISD::CTLZ, MVT::v2i64, 1 }, 2237 { ISD::CTLZ, MVT::v4i32, 1 }, 2238 { ISD::CTLZ, MVT::v8i16, 4 }, 2239 { ISD::CTLZ, MVT::v16i8, 4 }, 2240 }; 2241 static const CostTblEntry AVX512BWCostTbl[] = { 2242 { ISD::BITREVERSE, MVT::v8i64, 5 }, 2243 { ISD::BITREVERSE, MVT::v16i32, 5 }, 2244 { ISD::BITREVERSE, MVT::v32i16, 5 }, 2245 { ISD::BITREVERSE, MVT::v64i8, 5 }, 2246 { ISD::CTLZ, MVT::v8i64, 23 }, 2247 { ISD::CTLZ, MVT::v16i32, 22 }, 2248 { ISD::CTLZ, MVT::v32i16, 18 }, 2249 { ISD::CTLZ, MVT::v64i8, 17 }, 2250 { ISD::CTPOP, MVT::v8i64, 7 }, 2251 { ISD::CTPOP, MVT::v16i32, 11 }, 2252 { ISD::CTPOP, MVT::v32i16, 9 }, 2253 { ISD::CTPOP, MVT::v64i8, 6 }, 2254 { ISD::CTTZ, MVT::v8i64, 10 }, 2255 { ISD::CTTZ, MVT::v16i32, 14 }, 2256 { ISD::CTTZ, MVT::v32i16, 12 }, 2257 { ISD::CTTZ, MVT::v64i8, 9 }, 2258 { ISD::SADDSAT, MVT::v32i16, 1 }, 2259 { ISD::SADDSAT, MVT::v64i8, 1 }, 2260 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2261 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2262 { ISD::UADDSAT, MVT::v32i16, 1 }, 2263 { ISD::UADDSAT, MVT::v64i8, 1 }, 2264 { ISD::USUBSAT, MVT::v32i16, 1 }, 2265 { ISD::USUBSAT, MVT::v64i8, 1 }, 2266 }; 2267 static const CostTblEntry AVX512CostTbl[] = { 2268 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2269 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2270 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2271 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2272 { ISD::CTLZ, MVT::v8i64, 29 }, 2273 { ISD::CTLZ, MVT::v16i32, 35 }, 2274 { ISD::CTLZ, MVT::v32i16, 28 }, 2275 { ISD::CTLZ, MVT::v64i8, 18 }, 2276 { ISD::CTPOP, MVT::v8i64, 16 }, 2277 { ISD::CTPOP, MVT::v16i32, 24 }, 2278 { ISD::CTPOP, MVT::v32i16, 18 }, 2279 { ISD::CTPOP, MVT::v64i8, 12 }, 2280 { ISD::CTTZ, MVT::v8i64, 20 }, 2281 { ISD::CTTZ, MVT::v16i32, 28 }, 2282 { ISD::CTTZ, MVT::v32i16, 24 }, 2283 { ISD::CTTZ, MVT::v64i8, 18 }, 2284 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2285 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2286 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2287 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2288 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2289 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2290 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2291 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2292 { ISD::SADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2293 { ISD::SADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2294 { ISD::SSUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2295 { ISD::SSUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2296 { ISD::UADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2297 { ISD::UADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2298 { ISD::USUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2299 { ISD::USUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2300 { ISD::FMAXNUM, MVT::f32, 2 }, 2301 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2302 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2303 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2304 { ISD::FMAXNUM, MVT::f64, 2 }, 2305 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2306 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2307 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2308 }; 2309 static const CostTblEntry XOPCostTbl[] = { 2310 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2311 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2312 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2313 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2314 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2315 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2316 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2317 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2318 { ISD::BITREVERSE, MVT::i64, 3 }, 2319 { ISD::BITREVERSE, MVT::i32, 3 }, 2320 { ISD::BITREVERSE, MVT::i16, 3 }, 2321 { ISD::BITREVERSE, MVT::i8, 3 } 2322 }; 2323 static const CostTblEntry AVX2CostTbl[] = { 2324 { ISD::BITREVERSE, MVT::v4i64, 5 }, 2325 { ISD::BITREVERSE, MVT::v8i32, 5 }, 2326 { ISD::BITREVERSE, MVT::v16i16, 5 }, 2327 { ISD::BITREVERSE, MVT::v32i8, 5 }, 2328 { ISD::BSWAP, MVT::v4i64, 1 }, 2329 { ISD::BSWAP, MVT::v8i32, 1 }, 2330 { ISD::BSWAP, MVT::v16i16, 1 }, 2331 { ISD::CTLZ, MVT::v4i64, 23 }, 2332 { ISD::CTLZ, MVT::v8i32, 18 }, 2333 { ISD::CTLZ, MVT::v16i16, 14 }, 2334 { ISD::CTLZ, MVT::v32i8, 9 }, 2335 { ISD::CTPOP, MVT::v4i64, 7 }, 2336 { ISD::CTPOP, MVT::v8i32, 11 }, 2337 { ISD::CTPOP, MVT::v16i16, 9 }, 2338 { ISD::CTPOP, MVT::v32i8, 6 }, 2339 { ISD::CTTZ, MVT::v4i64, 10 }, 2340 { ISD::CTTZ, MVT::v8i32, 14 }, 2341 { ISD::CTTZ, MVT::v16i16, 12 }, 2342 { ISD::CTTZ, MVT::v32i8, 9 }, 2343 { ISD::SADDSAT, MVT::v16i16, 1 }, 2344 { ISD::SADDSAT, MVT::v32i8, 1 }, 2345 { ISD::SSUBSAT, MVT::v16i16, 1 }, 2346 { ISD::SSUBSAT, MVT::v32i8, 1 }, 2347 { ISD::UADDSAT, MVT::v16i16, 1 }, 2348 { ISD::UADDSAT, MVT::v32i8, 1 }, 2349 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 2350 { ISD::USUBSAT, MVT::v16i16, 1 }, 2351 { ISD::USUBSAT, MVT::v32i8, 1 }, 2352 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2353 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2354 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2355 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2356 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2357 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2358 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2359 }; 2360 static const CostTblEntry AVX1CostTbl[] = { 2361 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 2362 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 2363 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 2364 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 2365 { ISD::BSWAP, MVT::v4i64, 4 }, 2366 { ISD::BSWAP, MVT::v8i32, 4 }, 2367 { ISD::BSWAP, MVT::v16i16, 4 }, 2368 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 2369 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 2370 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 2371 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2372 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 2373 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 2374 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 2375 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 2376 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 2377 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 2378 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 2379 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2380 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2381 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2382 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2383 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2384 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2385 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2386 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 2387 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2388 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2389 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 2390 { ISD::FMAXNUM, MVT::f32, 3 }, 2391 { ISD::FMAXNUM, MVT::v4f32, 3 }, 2392 { ISD::FMAXNUM, MVT::v8f32, 5 }, 2393 { ISD::FMAXNUM, MVT::f64, 3 }, 2394 { ISD::FMAXNUM, MVT::v2f64, 3 }, 2395 { ISD::FMAXNUM, MVT::v4f64, 5 }, 2396 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 2397 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 2398 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 2399 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 2400 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 2401 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 2402 }; 2403 static const CostTblEntry GLMCostTbl[] = { 2404 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 2405 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 2406 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 2407 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 2408 }; 2409 static const CostTblEntry SLMCostTbl[] = { 2410 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 2411 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 2412 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 2413 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 2414 }; 2415 static const CostTblEntry SSE42CostTbl[] = { 2416 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 2417 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 2418 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 2419 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 2420 }; 2421 static const CostTblEntry SSSE3CostTbl[] = { 2422 { ISD::BITREVERSE, MVT::v2i64, 5 }, 2423 { ISD::BITREVERSE, MVT::v4i32, 5 }, 2424 { ISD::BITREVERSE, MVT::v8i16, 5 }, 2425 { ISD::BITREVERSE, MVT::v16i8, 5 }, 2426 { ISD::BSWAP, MVT::v2i64, 1 }, 2427 { ISD::BSWAP, MVT::v4i32, 1 }, 2428 { ISD::BSWAP, MVT::v8i16, 1 }, 2429 { ISD::CTLZ, MVT::v2i64, 23 }, 2430 { ISD::CTLZ, MVT::v4i32, 18 }, 2431 { ISD::CTLZ, MVT::v8i16, 14 }, 2432 { ISD::CTLZ, MVT::v16i8, 9 }, 2433 { ISD::CTPOP, MVT::v2i64, 7 }, 2434 { ISD::CTPOP, MVT::v4i32, 11 }, 2435 { ISD::CTPOP, MVT::v8i16, 9 }, 2436 { ISD::CTPOP, MVT::v16i8, 6 }, 2437 { ISD::CTTZ, MVT::v2i64, 10 }, 2438 { ISD::CTTZ, MVT::v4i32, 14 }, 2439 { ISD::CTTZ, MVT::v8i16, 12 }, 2440 { ISD::CTTZ, MVT::v16i8, 9 } 2441 }; 2442 static const CostTblEntry SSE2CostTbl[] = { 2443 { ISD::BITREVERSE, MVT::v2i64, 29 }, 2444 { ISD::BITREVERSE, MVT::v4i32, 27 }, 2445 { ISD::BITREVERSE, MVT::v8i16, 27 }, 2446 { ISD::BITREVERSE, MVT::v16i8, 20 }, 2447 { ISD::BSWAP, MVT::v2i64, 7 }, 2448 { ISD::BSWAP, MVT::v4i32, 7 }, 2449 { ISD::BSWAP, MVT::v8i16, 7 }, 2450 { ISD::CTLZ, MVT::v2i64, 25 }, 2451 { ISD::CTLZ, MVT::v4i32, 26 }, 2452 { ISD::CTLZ, MVT::v8i16, 20 }, 2453 { ISD::CTLZ, MVT::v16i8, 17 }, 2454 { ISD::CTPOP, MVT::v2i64, 12 }, 2455 { ISD::CTPOP, MVT::v4i32, 15 }, 2456 { ISD::CTPOP, MVT::v8i16, 13 }, 2457 { ISD::CTPOP, MVT::v16i8, 10 }, 2458 { ISD::CTTZ, MVT::v2i64, 14 }, 2459 { ISD::CTTZ, MVT::v4i32, 18 }, 2460 { ISD::CTTZ, MVT::v8i16, 16 }, 2461 { ISD::CTTZ, MVT::v16i8, 13 }, 2462 { ISD::SADDSAT, MVT::v8i16, 1 }, 2463 { ISD::SADDSAT, MVT::v16i8, 1 }, 2464 { ISD::SSUBSAT, MVT::v8i16, 1 }, 2465 { ISD::SSUBSAT, MVT::v16i8, 1 }, 2466 { ISD::UADDSAT, MVT::v8i16, 1 }, 2467 { ISD::UADDSAT, MVT::v16i8, 1 }, 2468 { ISD::USUBSAT, MVT::v8i16, 1 }, 2469 { ISD::USUBSAT, MVT::v16i8, 1 }, 2470 { ISD::FMAXNUM, MVT::f64, 4 }, 2471 { ISD::FMAXNUM, MVT::v2f64, 4 }, 2472 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 2473 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 2474 }; 2475 static const CostTblEntry SSE1CostTbl[] = { 2476 { ISD::FMAXNUM, MVT::f32, 4 }, 2477 { ISD::FMAXNUM, MVT::v4f32, 4 }, 2478 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 2479 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 2480 }; 2481 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 2482 { ISD::CTTZ, MVT::i64, 1 }, 2483 }; 2484 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 2485 { ISD::CTTZ, MVT::i32, 1 }, 2486 { ISD::CTTZ, MVT::i16, 1 }, 2487 { ISD::CTTZ, MVT::i8, 1 }, 2488 }; 2489 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 2490 { ISD::CTLZ, MVT::i64, 1 }, 2491 }; 2492 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 2493 { ISD::CTLZ, MVT::i32, 1 }, 2494 { ISD::CTLZ, MVT::i16, 1 }, 2495 { ISD::CTLZ, MVT::i8, 1 }, 2496 }; 2497 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 2498 { ISD::CTPOP, MVT::i64, 1 }, 2499 }; 2500 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 2501 { ISD::CTPOP, MVT::i32, 1 }, 2502 { ISD::CTPOP, MVT::i16, 1 }, 2503 { ISD::CTPOP, MVT::i8, 1 }, 2504 }; 2505 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2506 { ISD::BITREVERSE, MVT::i64, 14 }, 2507 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 2508 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 2509 { ISD::CTPOP, MVT::i64, 10 }, 2510 { ISD::SADDO, MVT::i64, 1 }, 2511 { ISD::UADDO, MVT::i64, 1 }, 2512 }; 2513 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2514 { ISD::BITREVERSE, MVT::i32, 14 }, 2515 { ISD::BITREVERSE, MVT::i16, 14 }, 2516 { ISD::BITREVERSE, MVT::i8, 11 }, 2517 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 2518 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 2519 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 2520 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 2521 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 2522 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 2523 { ISD::CTPOP, MVT::i32, 8 }, 2524 { ISD::CTPOP, MVT::i16, 9 }, 2525 { ISD::CTPOP, MVT::i8, 7 }, 2526 { ISD::SADDO, MVT::i32, 1 }, 2527 { ISD::SADDO, MVT::i16, 1 }, 2528 { ISD::SADDO, MVT::i8, 1 }, 2529 { ISD::UADDO, MVT::i32, 1 }, 2530 { ISD::UADDO, MVT::i16, 1 }, 2531 { ISD::UADDO, MVT::i8, 1 }, 2532 }; 2533 2534 Type *OpTy = RetTy; 2535 unsigned ISD = ISD::DELETED_NODE; 2536 switch (IID) { 2537 default: 2538 break; 2539 case Intrinsic::bitreverse: 2540 ISD = ISD::BITREVERSE; 2541 break; 2542 case Intrinsic::bswap: 2543 ISD = ISD::BSWAP; 2544 break; 2545 case Intrinsic::ctlz: 2546 ISD = ISD::CTLZ; 2547 break; 2548 case Intrinsic::ctpop: 2549 ISD = ISD::CTPOP; 2550 break; 2551 case Intrinsic::cttz: 2552 ISD = ISD::CTTZ; 2553 break; 2554 case Intrinsic::maxnum: 2555 case Intrinsic::minnum: 2556 // FMINNUM has same costs so don't duplicate. 2557 ISD = ISD::FMAXNUM; 2558 break; 2559 case Intrinsic::sadd_sat: 2560 ISD = ISD::SADDSAT; 2561 break; 2562 case Intrinsic::ssub_sat: 2563 ISD = ISD::SSUBSAT; 2564 break; 2565 case Intrinsic::uadd_sat: 2566 ISD = ISD::UADDSAT; 2567 break; 2568 case Intrinsic::usub_sat: 2569 ISD = ISD::USUBSAT; 2570 break; 2571 case Intrinsic::sqrt: 2572 ISD = ISD::FSQRT; 2573 break; 2574 case Intrinsic::sadd_with_overflow: 2575 case Intrinsic::ssub_with_overflow: 2576 // SSUBO has same costs so don't duplicate. 2577 ISD = ISD::SADDO; 2578 OpTy = RetTy->getContainedType(0); 2579 break; 2580 case Intrinsic::uadd_with_overflow: 2581 case Intrinsic::usub_with_overflow: 2582 // USUBO has same costs so don't duplicate. 2583 ISD = ISD::UADDO; 2584 OpTy = RetTy->getContainedType(0); 2585 break; 2586 } 2587 2588 if (ISD != ISD::DELETED_NODE) { 2589 // Legalize the type. 2590 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 2591 MVT MTy = LT.second; 2592 2593 // Attempt to lookup cost. 2594 if (ST->useGLMDivSqrtCosts()) 2595 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 2596 return LT.first * Entry->Cost; 2597 2598 if (ST->isSLM()) 2599 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2600 return LT.first * Entry->Cost; 2601 2602 if (ST->hasCDI()) 2603 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 2604 return LT.first * Entry->Cost; 2605 2606 if (ST->hasBWI()) 2607 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2608 return LT.first * Entry->Cost; 2609 2610 if (ST->hasAVX512()) 2611 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2612 return LT.first * Entry->Cost; 2613 2614 if (ST->hasXOP()) 2615 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2616 return LT.first * Entry->Cost; 2617 2618 if (ST->hasAVX2()) 2619 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2620 return LT.first * Entry->Cost; 2621 2622 if (ST->hasAVX()) 2623 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2624 return LT.first * Entry->Cost; 2625 2626 if (ST->hasSSE42()) 2627 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2628 return LT.first * Entry->Cost; 2629 2630 if (ST->hasSSSE3()) 2631 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 2632 return LT.first * Entry->Cost; 2633 2634 if (ST->hasSSE2()) 2635 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2636 return LT.first * Entry->Cost; 2637 2638 if (ST->hasSSE1()) 2639 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2640 return LT.first * Entry->Cost; 2641 2642 if (ST->hasBMI()) { 2643 if (ST->is64Bit()) 2644 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 2645 return LT.first * Entry->Cost; 2646 2647 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 2648 return LT.first * Entry->Cost; 2649 } 2650 2651 if (ST->hasLZCNT()) { 2652 if (ST->is64Bit()) 2653 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 2654 return LT.first * Entry->Cost; 2655 2656 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 2657 return LT.first * Entry->Cost; 2658 } 2659 2660 if (ST->hasPOPCNT()) { 2661 if (ST->is64Bit()) 2662 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 2663 return LT.first * Entry->Cost; 2664 2665 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 2666 return LT.first * Entry->Cost; 2667 } 2668 2669 // TODO - add BMI (TZCNT) scalar handling 2670 2671 if (ST->is64Bit()) 2672 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2673 return LT.first * Entry->Cost; 2674 2675 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2676 return LT.first * Entry->Cost; 2677 } 2678 2679 return BaseT::getIntrinsicInstrCost(IID, RetTy, Tys, FMF, 2680 ScalarizationCostPassed, I); 2681 } 2682 2683 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 2684 ArrayRef<Value *> Args, FastMathFlags FMF, 2685 unsigned VF, const Instruction *I) { 2686 static const CostTblEntry AVX512CostTbl[] = { 2687 { ISD::ROTL, MVT::v8i64, 1 }, 2688 { ISD::ROTL, MVT::v4i64, 1 }, 2689 { ISD::ROTL, MVT::v2i64, 1 }, 2690 { ISD::ROTL, MVT::v16i32, 1 }, 2691 { ISD::ROTL, MVT::v8i32, 1 }, 2692 { ISD::ROTL, MVT::v4i32, 1 }, 2693 { ISD::ROTR, MVT::v8i64, 1 }, 2694 { ISD::ROTR, MVT::v4i64, 1 }, 2695 { ISD::ROTR, MVT::v2i64, 1 }, 2696 { ISD::ROTR, MVT::v16i32, 1 }, 2697 { ISD::ROTR, MVT::v8i32, 1 }, 2698 { ISD::ROTR, MVT::v4i32, 1 } 2699 }; 2700 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 2701 static const CostTblEntry XOPCostTbl[] = { 2702 { ISD::ROTL, MVT::v4i64, 4 }, 2703 { ISD::ROTL, MVT::v8i32, 4 }, 2704 { ISD::ROTL, MVT::v16i16, 4 }, 2705 { ISD::ROTL, MVT::v32i8, 4 }, 2706 { ISD::ROTL, MVT::v2i64, 1 }, 2707 { ISD::ROTL, MVT::v4i32, 1 }, 2708 { ISD::ROTL, MVT::v8i16, 1 }, 2709 { ISD::ROTL, MVT::v16i8, 1 }, 2710 { ISD::ROTR, MVT::v4i64, 6 }, 2711 { ISD::ROTR, MVT::v8i32, 6 }, 2712 { ISD::ROTR, MVT::v16i16, 6 }, 2713 { ISD::ROTR, MVT::v32i8, 6 }, 2714 { ISD::ROTR, MVT::v2i64, 2 }, 2715 { ISD::ROTR, MVT::v4i32, 2 }, 2716 { ISD::ROTR, MVT::v8i16, 2 }, 2717 { ISD::ROTR, MVT::v16i8, 2 } 2718 }; 2719 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2720 { ISD::ROTL, MVT::i64, 1 }, 2721 { ISD::ROTR, MVT::i64, 1 }, 2722 { ISD::FSHL, MVT::i64, 4 } 2723 }; 2724 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2725 { ISD::ROTL, MVT::i32, 1 }, 2726 { ISD::ROTL, MVT::i16, 1 }, 2727 { ISD::ROTL, MVT::i8, 1 }, 2728 { ISD::ROTR, MVT::i32, 1 }, 2729 { ISD::ROTR, MVT::i16, 1 }, 2730 { ISD::ROTR, MVT::i8, 1 }, 2731 { ISD::FSHL, MVT::i32, 4 }, 2732 { ISD::FSHL, MVT::i16, 4 }, 2733 { ISD::FSHL, MVT::i8, 4 } 2734 }; 2735 2736 unsigned ISD = ISD::DELETED_NODE; 2737 switch (IID) { 2738 default: 2739 break; 2740 case Intrinsic::fshl: 2741 ISD = ISD::FSHL; 2742 if (Args[0] == Args[1]) 2743 ISD = ISD::ROTL; 2744 break; 2745 case Intrinsic::fshr: 2746 // FSHR has same costs so don't duplicate. 2747 ISD = ISD::FSHL; 2748 if (Args[0] == Args[1]) 2749 ISD = ISD::ROTR; 2750 break; 2751 } 2752 2753 if (ISD != ISD::DELETED_NODE) { 2754 // Legalize the type. 2755 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 2756 MVT MTy = LT.second; 2757 2758 // Attempt to lookup cost. 2759 if (ST->hasAVX512()) 2760 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2761 return LT.first * Entry->Cost; 2762 2763 if (ST->hasXOP()) 2764 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2765 return LT.first * Entry->Cost; 2766 2767 if (ST->is64Bit()) 2768 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2769 return LT.first * Entry->Cost; 2770 2771 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2772 return LT.first * Entry->Cost; 2773 } 2774 2775 return BaseT::getIntrinsicInstrCost(IID, RetTy, Args, FMF, VF, I); 2776 } 2777 2778 int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { 2779 static const CostTblEntry SLMCostTbl[] = { 2780 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 2781 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 2782 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 2783 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 2784 }; 2785 2786 assert(Val->isVectorTy() && "This must be a vector type"); 2787 Type *ScalarType = Val->getScalarType(); 2788 int RegisterFileMoveCost = 0; 2789 2790 if (Index != -1U && (Opcode == Instruction::ExtractElement || 2791 Opcode == Instruction::InsertElement)) { 2792 // Legalize the type. 2793 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 2794 2795 // This type is legalized to a scalar type. 2796 if (!LT.second.isVector()) 2797 return 0; 2798 2799 // The type may be split. Normalize the index to the new type. 2800 unsigned NumElts = LT.second.getVectorNumElements(); 2801 unsigned SubNumElts = NumElts; 2802 Index = Index % NumElts; 2803 2804 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 2805 // For inserts, we also need to insert the subvector back. 2806 if (LT.second.getSizeInBits() > 128) { 2807 assert((LT.second.getSizeInBits() % 128) == 0 && "Illegal vector"); 2808 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 2809 SubNumElts = NumElts / NumSubVecs; 2810 if (SubNumElts <= Index) { 2811 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 2812 Index %= SubNumElts; 2813 } 2814 } 2815 2816 if (Index == 0) { 2817 // Floating point scalars are already located in index #0. 2818 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 2819 // true for all. 2820 if (ScalarType->isFloatingPointTy()) 2821 return RegisterFileMoveCost; 2822 2823 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 2824 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 2825 return 1 + RegisterFileMoveCost; 2826 } 2827 2828 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2829 assert(ISD && "Unexpected vector opcode"); 2830 MVT MScalarTy = LT.second.getScalarType(); 2831 if (ST->isSLM()) 2832 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 2833 return Entry->Cost + RegisterFileMoveCost; 2834 2835 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 2836 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 2837 (MScalarTy.isInteger() && ST->hasSSE41())) 2838 return 1 + RegisterFileMoveCost; 2839 2840 // Assume insertps is relatively cheap on all targets. 2841 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 2842 Opcode == Instruction::InsertElement) 2843 return 1 + RegisterFileMoveCost; 2844 2845 // For extractions we just need to shuffle the element to index 0, which 2846 // should be very cheap (assume cost = 1). For insertions we need to shuffle 2847 // the elements to its destination. In both cases we must handle the 2848 // subvector move(s). 2849 // If the vector type is already less than 128-bits then don't reduce it. 2850 // TODO: Under what circumstances should we shuffle using the full width? 2851 int ShuffleCost = 1; 2852 if (Opcode == Instruction::InsertElement) { 2853 auto *SubTy = cast<VectorType>(Val); 2854 EVT VT = TLI->getValueType(DL, Val); 2855 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 2856 SubTy = VectorType::get(ScalarType, SubNumElts); 2857 ShuffleCost = getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, 0, SubTy); 2858 } 2859 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 2860 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 2861 } 2862 2863 // Add to the base cost if we know that the extracted element of a vector is 2864 // destined to be moved to and used in the integer register file. 2865 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 2866 RegisterFileMoveCost += 1; 2867 2868 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 2869 } 2870 2871 unsigned X86TTIImpl::getScalarizationOverhead(Type *Ty, bool Insert, 2872 bool Extract) { 2873 return BaseT::getScalarizationOverhead(Ty, Insert, Extract); 2874 } 2875 2876 int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 2877 MaybeAlign Alignment, unsigned AddressSpace, 2878 const Instruction *I) { 2879 // Handle non-power-of-two vectors such as <3 x float> 2880 if (VectorType *VTy = dyn_cast<VectorType>(Src)) { 2881 unsigned NumElem = VTy->getNumElements(); 2882 2883 // Handle a few common cases: 2884 // <3 x float> 2885 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 2886 // Cost = 64 bit store + extract + 32 bit store. 2887 return 3; 2888 2889 // <3 x double> 2890 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 2891 // Cost = 128 bit store + unpack + 64 bit store. 2892 return 3; 2893 2894 // Assume that all other non-power-of-two numbers are scalarized. 2895 if (!isPowerOf2_32(NumElem)) { 2896 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment, 2897 AddressSpace); 2898 int SplitCost = getScalarizationOverhead(Src, Opcode == Instruction::Load, 2899 Opcode == Instruction::Store); 2900 return NumElem * Cost + SplitCost; 2901 } 2902 } 2903 2904 // Legalize the type. 2905 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 2906 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 2907 "Invalid Opcode"); 2908 2909 // Each load/store unit costs 1. 2910 int Cost = LT.first * 1; 2911 2912 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a 2913 // proxy for a double-pumped AVX memory interface such as on Sandybridge. 2914 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow()) 2915 Cost *= 2; 2916 2917 return Cost; 2918 } 2919 2920 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, 2921 unsigned Alignment, 2922 unsigned AddressSpace) { 2923 bool IsLoad = (Instruction::Load == Opcode); 2924 bool IsStore = (Instruction::Store == Opcode); 2925 2926 VectorType *SrcVTy = dyn_cast<VectorType>(SrcTy); 2927 if (!SrcVTy) 2928 // To calculate scalar take the regular cost, without mask 2929 return getMemoryOpCost(Opcode, SrcTy, MaybeAlign(Alignment), AddressSpace); 2930 2931 unsigned NumElem = SrcVTy->getNumElements(); 2932 VectorType *MaskTy = 2933 VectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 2934 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, MaybeAlign(Alignment))) || 2935 (IsStore && !isLegalMaskedStore(SrcVTy, MaybeAlign(Alignment))) || 2936 !isPowerOf2_32(NumElem)) { 2937 // Scalarization 2938 int MaskSplitCost = getScalarizationOverhead(MaskTy, false, true); 2939 int ScalarCompareCost = getCmpSelInstrCost( 2940 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr); 2941 int BranchCost = getCFInstrCost(Instruction::Br); 2942 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 2943 2944 int ValueSplitCost = getScalarizationOverhead(SrcVTy, IsLoad, IsStore); 2945 int MemopCost = 2946 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2947 MaybeAlign(Alignment), AddressSpace); 2948 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 2949 } 2950 2951 // Legalize the type. 2952 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 2953 auto VT = TLI->getValueType(DL, SrcVTy); 2954 int Cost = 0; 2955 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 2956 LT.second.getVectorNumElements() == NumElem) 2957 // Promotion requires expand/truncate for data and a shuffle for mask. 2958 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, 0, nullptr) + 2959 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, 0, nullptr); 2960 2961 else if (LT.second.getVectorNumElements() > NumElem) { 2962 VectorType *NewMaskTy = VectorType::get(MaskTy->getElementType(), 2963 LT.second.getVectorNumElements()); 2964 // Expanding requires fill mask with zeroes 2965 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, 0, MaskTy); 2966 } 2967 2968 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 2969 if (!ST->hasAVX512()) 2970 return Cost + LT.first * (IsLoad ? 2 : 8); 2971 2972 // AVX-512 masked load/store is cheapper 2973 return Cost + LT.first; 2974 } 2975 2976 int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE, 2977 const SCEV *Ptr) { 2978 // Address computations in vectorized code with non-consecutive addresses will 2979 // likely result in more instructions compared to scalar code where the 2980 // computation can more often be merged into the index mode. The resulting 2981 // extra micro-ops can significantly decrease throughput. 2982 const unsigned NumVectorInstToHideOverhead = 10; 2983 2984 // Cost modeling of Strided Access Computation is hidden by the indexing 2985 // modes of X86 regardless of the stride value. We dont believe that there 2986 // is a difference between constant strided access in gerenal and constant 2987 // strided value which is less than or equal to 64. 2988 // Even in the case of (loop invariant) stride whose value is not known at 2989 // compile time, the address computation will not incur more than one extra 2990 // ADD instruction. 2991 if (Ty->isVectorTy() && SE) { 2992 if (!BaseT::isStridedAccess(Ptr)) 2993 return NumVectorInstToHideOverhead; 2994 if (!BaseT::getConstantStrideStep(SE, Ptr)) 2995 return 1; 2996 } 2997 2998 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 2999 } 3000 3001 int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 3002 bool IsPairwise) { 3003 // Just use the default implementation for pair reductions. 3004 if (IsPairwise) 3005 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise); 3006 3007 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3008 // and make it as the cost. 3009 3010 static const CostTblEntry SLMCostTblNoPairWise[] = { 3011 { ISD::FADD, MVT::v2f64, 3 }, 3012 { ISD::ADD, MVT::v2i64, 5 }, 3013 }; 3014 3015 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3016 { ISD::FADD, MVT::v2f64, 2 }, 3017 { ISD::FADD, MVT::v4f32, 4 }, 3018 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 3019 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 3020 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 3021 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 3022 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 3023 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 3024 { ISD::ADD, MVT::v2i8, 2 }, 3025 { ISD::ADD, MVT::v4i8, 2 }, 3026 { ISD::ADD, MVT::v8i8, 2 }, 3027 { ISD::ADD, MVT::v16i8, 3 }, 3028 }; 3029 3030 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3031 { ISD::FADD, MVT::v4f64, 3 }, 3032 { ISD::FADD, MVT::v4f32, 3 }, 3033 { ISD::FADD, MVT::v8f32, 4 }, 3034 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 3035 { ISD::ADD, MVT::v4i64, 3 }, 3036 { ISD::ADD, MVT::v8i32, 5 }, 3037 { ISD::ADD, MVT::v16i16, 5 }, 3038 { ISD::ADD, MVT::v32i8, 4 }, 3039 }; 3040 3041 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3042 assert(ISD && "Invalid opcode"); 3043 3044 // Before legalizing the type, give a chance to look up illegal narrow types 3045 // in the table. 3046 // FIXME: Is there a better way to do this? 3047 EVT VT = TLI->getValueType(DL, ValTy); 3048 if (VT.isSimple()) { 3049 MVT MTy = VT.getSimpleVT(); 3050 if (ST->isSLM()) 3051 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3052 return Entry->Cost; 3053 3054 if (ST->hasAVX()) 3055 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3056 return Entry->Cost; 3057 3058 if (ST->hasSSE2()) 3059 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3060 return Entry->Cost; 3061 } 3062 3063 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3064 3065 MVT MTy = LT.second; 3066 3067 auto *ValVTy = cast<VectorType>(ValTy); 3068 3069 unsigned ArithmeticCost = 0; 3070 if (LT.first != 1 && MTy.isVector() && 3071 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3072 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3073 VectorType *SingleOpTy = 3074 VectorType::get(ValVTy->getElementType(), MTy.getVectorNumElements()); 3075 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy); 3076 ArithmeticCost *= LT.first - 1; 3077 } 3078 3079 if (ST->isSLM()) 3080 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3081 return ArithmeticCost + Entry->Cost; 3082 3083 if (ST->hasAVX()) 3084 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3085 return ArithmeticCost + Entry->Cost; 3086 3087 if (ST->hasSSE2()) 3088 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3089 return ArithmeticCost + Entry->Cost; 3090 3091 // FIXME: These assume a naive kshift+binop lowering, which is probably 3092 // conservative in most cases. 3093 static const CostTblEntry AVX512BoolReduction[] = { 3094 { ISD::AND, MVT::v2i1, 3 }, 3095 { ISD::AND, MVT::v4i1, 5 }, 3096 { ISD::AND, MVT::v8i1, 7 }, 3097 { ISD::AND, MVT::v16i1, 9 }, 3098 { ISD::AND, MVT::v32i1, 11 }, 3099 { ISD::AND, MVT::v64i1, 13 }, 3100 { ISD::OR, MVT::v2i1, 3 }, 3101 { ISD::OR, MVT::v4i1, 5 }, 3102 { ISD::OR, MVT::v8i1, 7 }, 3103 { ISD::OR, MVT::v16i1, 9 }, 3104 { ISD::OR, MVT::v32i1, 11 }, 3105 { ISD::OR, MVT::v64i1, 13 }, 3106 }; 3107 3108 static const CostTblEntry AVX2BoolReduction[] = { 3109 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 3110 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 3111 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 3112 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 3113 }; 3114 3115 static const CostTblEntry AVX1BoolReduction[] = { 3116 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 3117 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 3118 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3119 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3120 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 3121 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 3122 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3123 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3124 }; 3125 3126 static const CostTblEntry SSE2BoolReduction[] = { 3127 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 3128 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 3129 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 3130 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 3131 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 3132 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 3133 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 3134 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 3135 }; 3136 3137 // Handle bool allof/anyof patterns. 3138 if (ValVTy->getElementType()->isIntegerTy(1)) { 3139 unsigned ArithmeticCost = 0; 3140 if (LT.first != 1 && MTy.isVector() && 3141 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3142 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3143 Type *SingleOpTy = 3144 VectorType::get(ValVTy->getElementType(), MTy.getVectorNumElements()); 3145 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy); 3146 ArithmeticCost *= LT.first - 1; 3147 } 3148 3149 if (ST->hasAVX512()) 3150 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 3151 return ArithmeticCost + Entry->Cost; 3152 if (ST->hasAVX2()) 3153 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 3154 return ArithmeticCost + Entry->Cost; 3155 if (ST->hasAVX()) 3156 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 3157 return ArithmeticCost + Entry->Cost; 3158 if (ST->hasSSE2()) 3159 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 3160 return ArithmeticCost + Entry->Cost; 3161 3162 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise); 3163 } 3164 3165 unsigned NumVecElts = ValVTy->getNumElements(); 3166 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 3167 3168 // Special case power of 2 reductions where the scalar type isn't changed 3169 // by type legalization. 3170 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 3171 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise); 3172 3173 unsigned ReductionCost = 0; 3174 3175 auto *Ty = ValVTy; 3176 if (LT.first != 1 && MTy.isVector() && 3177 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3178 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3179 Ty = VectorType::get(ValVTy->getElementType(), MTy.getVectorNumElements()); 3180 ReductionCost = getArithmeticInstrCost(Opcode, Ty); 3181 ReductionCost *= LT.first - 1; 3182 NumVecElts = MTy.getVectorNumElements(); 3183 } 3184 3185 // Now handle reduction with the legal type, taking into account size changes 3186 // at each level. 3187 while (NumVecElts > 1) { 3188 // Determine the size of the remaining vector we need to reduce. 3189 unsigned Size = NumVecElts * ScalarSize; 3190 NumVecElts /= 2; 3191 // If we're reducing from 256/512 bits, use an extract_subvector. 3192 if (Size > 128) { 3193 auto *SubTy = VectorType::get(ValVTy->getElementType(), NumVecElts); 3194 ReductionCost += 3195 getShuffleCost(TTI::SK_ExtractSubvector, Ty, NumVecElts, SubTy); 3196 Ty = SubTy; 3197 } else if (Size == 128) { 3198 // Reducing from 128 bits is a permute of v2f64/v2i64. 3199 VectorType *ShufTy; 3200 if (ValVTy->isFloatingPointTy()) 3201 ShufTy = VectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 3202 else 3203 ShufTy = VectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 3204 ReductionCost += 3205 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3206 } else if (Size == 64) { 3207 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3208 VectorType *ShufTy; 3209 if (ValVTy->isFloatingPointTy()) 3210 ShufTy = VectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 3211 else 3212 ShufTy = VectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 3213 ReductionCost += 3214 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3215 } else { 3216 // Reducing from smaller size is a shift by immediate. 3217 auto *ShiftTy = VectorType::get( 3218 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 3219 ReductionCost += getArithmeticInstrCost( 3220 Instruction::LShr, ShiftTy, TargetTransformInfo::OK_AnyValue, 3221 TargetTransformInfo::OK_UniformConstantValue, 3222 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3223 } 3224 3225 // Add the arithmetic op for this level. 3226 ReductionCost += getArithmeticInstrCost(Opcode, Ty); 3227 } 3228 3229 // Add the final extract element to the cost. 3230 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3231 } 3232 3233 int X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, bool IsUnsigned) { 3234 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3235 3236 MVT MTy = LT.second; 3237 3238 int ISD; 3239 if (Ty->isIntOrIntVectorTy()) { 3240 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3241 } else { 3242 assert(Ty->isFPOrFPVectorTy() && 3243 "Expected float point or integer vector type."); 3244 ISD = ISD::FMINNUM; 3245 } 3246 3247 static const CostTblEntry SSE1CostTbl[] = { 3248 {ISD::FMINNUM, MVT::v4f32, 1}, 3249 }; 3250 3251 static const CostTblEntry SSE2CostTbl[] = { 3252 {ISD::FMINNUM, MVT::v2f64, 1}, 3253 {ISD::SMIN, MVT::v8i16, 1}, 3254 {ISD::UMIN, MVT::v16i8, 1}, 3255 }; 3256 3257 static const CostTblEntry SSE41CostTbl[] = { 3258 {ISD::SMIN, MVT::v4i32, 1}, 3259 {ISD::UMIN, MVT::v4i32, 1}, 3260 {ISD::UMIN, MVT::v8i16, 1}, 3261 {ISD::SMIN, MVT::v16i8, 1}, 3262 }; 3263 3264 static const CostTblEntry SSE42CostTbl[] = { 3265 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 3266 }; 3267 3268 static const CostTblEntry AVX1CostTbl[] = { 3269 {ISD::FMINNUM, MVT::v8f32, 1}, 3270 {ISD::FMINNUM, MVT::v4f64, 1}, 3271 {ISD::SMIN, MVT::v8i32, 3}, 3272 {ISD::UMIN, MVT::v8i32, 3}, 3273 {ISD::SMIN, MVT::v16i16, 3}, 3274 {ISD::UMIN, MVT::v16i16, 3}, 3275 {ISD::SMIN, MVT::v32i8, 3}, 3276 {ISD::UMIN, MVT::v32i8, 3}, 3277 }; 3278 3279 static const CostTblEntry AVX2CostTbl[] = { 3280 {ISD::SMIN, MVT::v8i32, 1}, 3281 {ISD::UMIN, MVT::v8i32, 1}, 3282 {ISD::SMIN, MVT::v16i16, 1}, 3283 {ISD::UMIN, MVT::v16i16, 1}, 3284 {ISD::SMIN, MVT::v32i8, 1}, 3285 {ISD::UMIN, MVT::v32i8, 1}, 3286 }; 3287 3288 static const CostTblEntry AVX512CostTbl[] = { 3289 {ISD::FMINNUM, MVT::v16f32, 1}, 3290 {ISD::FMINNUM, MVT::v8f64, 1}, 3291 {ISD::SMIN, MVT::v2i64, 1}, 3292 {ISD::UMIN, MVT::v2i64, 1}, 3293 {ISD::SMIN, MVT::v4i64, 1}, 3294 {ISD::UMIN, MVT::v4i64, 1}, 3295 {ISD::SMIN, MVT::v8i64, 1}, 3296 {ISD::UMIN, MVT::v8i64, 1}, 3297 {ISD::SMIN, MVT::v16i32, 1}, 3298 {ISD::UMIN, MVT::v16i32, 1}, 3299 }; 3300 3301 static const CostTblEntry AVX512BWCostTbl[] = { 3302 {ISD::SMIN, MVT::v32i16, 1}, 3303 {ISD::UMIN, MVT::v32i16, 1}, 3304 {ISD::SMIN, MVT::v64i8, 1}, 3305 {ISD::UMIN, MVT::v64i8, 1}, 3306 }; 3307 3308 // If we have a native MIN/MAX instruction for this type, use it. 3309 if (ST->hasBWI()) 3310 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3311 return LT.first * Entry->Cost; 3312 3313 if (ST->hasAVX512()) 3314 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3315 return LT.first * Entry->Cost; 3316 3317 if (ST->hasAVX2()) 3318 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3319 return LT.first * Entry->Cost; 3320 3321 if (ST->hasAVX()) 3322 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3323 return LT.first * Entry->Cost; 3324 3325 if (ST->hasSSE42()) 3326 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3327 return LT.first * Entry->Cost; 3328 3329 if (ST->hasSSE41()) 3330 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3331 return LT.first * Entry->Cost; 3332 3333 if (ST->hasSSE2()) 3334 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3335 return LT.first * Entry->Cost; 3336 3337 if (ST->hasSSE1()) 3338 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3339 return LT.first * Entry->Cost; 3340 3341 unsigned CmpOpcode; 3342 if (Ty->isFPOrFPVectorTy()) { 3343 CmpOpcode = Instruction::FCmp; 3344 } else { 3345 assert(Ty->isIntOrIntVectorTy() && 3346 "expecting floating point or integer type for min/max reduction"); 3347 CmpOpcode = Instruction::ICmp; 3348 } 3349 3350 // Otherwise fall back to cmp+select. 3351 return getCmpSelInstrCost(CmpOpcode, Ty, CondTy, nullptr) + 3352 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, nullptr); 3353 } 3354 3355 int X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 3356 bool IsPairwise, bool IsUnsigned) { 3357 // Just use the default implementation for pair reductions. 3358 if (IsPairwise) 3359 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned); 3360 3361 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3362 3363 MVT MTy = LT.second; 3364 3365 int ISD; 3366 if (ValTy->isIntOrIntVectorTy()) { 3367 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3368 } else { 3369 assert(ValTy->isFPOrFPVectorTy() && 3370 "Expected float point or integer vector type."); 3371 ISD = ISD::FMINNUM; 3372 } 3373 3374 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3375 // and make it as the cost. 3376 3377 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3378 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 3379 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 3380 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 3381 }; 3382 3383 static const CostTblEntry SSE41CostTblNoPairWise[] = { 3384 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 3385 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 3386 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 3387 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 3388 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 3389 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 3390 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 3391 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 3392 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 3393 {ISD::SMIN, MVT::v16i8, 6}, 3394 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 3395 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 3396 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 3397 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 3398 }; 3399 3400 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3401 {ISD::SMIN, MVT::v16i16, 6}, 3402 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 3403 {ISD::SMIN, MVT::v32i8, 8}, 3404 {ISD::UMIN, MVT::v32i8, 8}, 3405 }; 3406 3407 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 3408 {ISD::SMIN, MVT::v32i16, 8}, 3409 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 3410 {ISD::SMIN, MVT::v64i8, 10}, 3411 {ISD::UMIN, MVT::v64i8, 10}, 3412 }; 3413 3414 // Before legalizing the type, give a chance to look up illegal narrow types 3415 // in the table. 3416 // FIXME: Is there a better way to do this? 3417 EVT VT = TLI->getValueType(DL, ValTy); 3418 if (VT.isSimple()) { 3419 MVT MTy = VT.getSimpleVT(); 3420 if (ST->hasBWI()) 3421 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3422 return Entry->Cost; 3423 3424 if (ST->hasAVX()) 3425 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3426 return Entry->Cost; 3427 3428 if (ST->hasSSE41()) 3429 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3430 return Entry->Cost; 3431 3432 if (ST->hasSSE2()) 3433 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3434 return Entry->Cost; 3435 } 3436 3437 auto *ValVTy = cast<VectorType>(ValTy); 3438 unsigned NumVecElts = ValVTy->getNumElements(); 3439 3440 auto *Ty = ValVTy; 3441 unsigned MinMaxCost = 0; 3442 if (LT.first != 1 && MTy.isVector() && 3443 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3444 // Type needs to be split. We need LT.first - 1 operations ops. 3445 Ty = VectorType::get(ValVTy->getElementType(), MTy.getVectorNumElements()); 3446 auto *SubCondTy = VectorType::get( 3447 cast<VectorType>(CondTy)->getElementType(), MTy.getVectorNumElements()); 3448 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3449 MinMaxCost *= LT.first - 1; 3450 NumVecElts = MTy.getVectorNumElements(); 3451 } 3452 3453 if (ST->hasBWI()) 3454 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3455 return MinMaxCost + Entry->Cost; 3456 3457 if (ST->hasAVX()) 3458 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3459 return MinMaxCost + Entry->Cost; 3460 3461 if (ST->hasSSE41()) 3462 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3463 return MinMaxCost + Entry->Cost; 3464 3465 if (ST->hasSSE2()) 3466 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3467 return MinMaxCost + Entry->Cost; 3468 3469 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 3470 3471 // Special case power of 2 reductions where the scalar type isn't changed 3472 // by type legalization. 3473 if (!isPowerOf2_32(ValVTy->getNumElements()) || 3474 ScalarSize != MTy.getScalarSizeInBits()) 3475 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned); 3476 3477 // Now handle reduction with the legal type, taking into account size changes 3478 // at each level. 3479 while (NumVecElts > 1) { 3480 // Determine the size of the remaining vector we need to reduce. 3481 unsigned Size = NumVecElts * ScalarSize; 3482 NumVecElts /= 2; 3483 // If we're reducing from 256/512 bits, use an extract_subvector. 3484 if (Size > 128) { 3485 auto *SubTy = VectorType::get(ValVTy->getElementType(), NumVecElts); 3486 MinMaxCost += 3487 getShuffleCost(TTI::SK_ExtractSubvector, Ty, NumVecElts, SubTy); 3488 Ty = SubTy; 3489 } else if (Size == 128) { 3490 // Reducing from 128 bits is a permute of v2f64/v2i64. 3491 VectorType *ShufTy; 3492 if (ValTy->isFloatingPointTy()) 3493 ShufTy = VectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 3494 else 3495 ShufTy = VectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 3496 MinMaxCost += 3497 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3498 } else if (Size == 64) { 3499 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3500 VectorType *ShufTy; 3501 if (ValTy->isFloatingPointTy()) 3502 ShufTy = VectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 3503 else 3504 ShufTy = VectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 3505 MinMaxCost += 3506 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3507 } else { 3508 // Reducing from smaller size is a shift by immediate. 3509 VectorType *ShiftTy = VectorType::get( 3510 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 3511 MinMaxCost += getArithmeticInstrCost( 3512 Instruction::LShr, ShiftTy, TargetTransformInfo::OK_AnyValue, 3513 TargetTransformInfo::OK_UniformConstantValue, 3514 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3515 } 3516 3517 // Add the arithmetic op for this level. 3518 auto *SubCondTy = VectorType::get(CondTy->getElementType(), 3519 Ty->getNumElements()); 3520 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3521 } 3522 3523 // Add the final extract element to the cost. 3524 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3525 } 3526 3527 /// Calculate the cost of materializing a 64-bit value. This helper 3528 /// method might only calculate a fraction of a larger immediate. Therefore it 3529 /// is valid to return a cost of ZERO. 3530 int X86TTIImpl::getIntImmCost(int64_t Val) { 3531 if (Val == 0) 3532 return TTI::TCC_Free; 3533 3534 if (isInt<32>(Val)) 3535 return TTI::TCC_Basic; 3536 3537 return 2 * TTI::TCC_Basic; 3538 } 3539 3540 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { 3541 assert(Ty->isIntegerTy()); 3542 3543 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3544 if (BitSize == 0) 3545 return ~0U; 3546 3547 // Never hoist constants larger than 128bit, because this might lead to 3548 // incorrect code generation or assertions in codegen. 3549 // Fixme: Create a cost model for types larger than i128 once the codegen 3550 // issues have been fixed. 3551 if (BitSize > 128) 3552 return TTI::TCC_Free; 3553 3554 if (Imm == 0) 3555 return TTI::TCC_Free; 3556 3557 // Sign-extend all constants to a multiple of 64-bit. 3558 APInt ImmVal = Imm; 3559 if (BitSize % 64 != 0) 3560 ImmVal = Imm.sext(alignTo(BitSize, 64)); 3561 3562 // Split the constant into 64-bit chunks and calculate the cost for each 3563 // chunk. 3564 int Cost = 0; 3565 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 3566 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 3567 int64_t Val = Tmp.getSExtValue(); 3568 Cost += getIntImmCost(Val); 3569 } 3570 // We need at least one instruction to materialize the constant. 3571 return std::max(1, Cost); 3572 } 3573 3574 int X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, 3575 Type *Ty) { 3576 assert(Ty->isIntegerTy()); 3577 3578 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3579 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3580 // here, so that constant hoisting will ignore this constant. 3581 if (BitSize == 0) 3582 return TTI::TCC_Free; 3583 3584 unsigned ImmIdx = ~0U; 3585 switch (Opcode) { 3586 default: 3587 return TTI::TCC_Free; 3588 case Instruction::GetElementPtr: 3589 // Always hoist the base address of a GetElementPtr. This prevents the 3590 // creation of new constants for every base constant that gets constant 3591 // folded with the offset. 3592 if (Idx == 0) 3593 return 2 * TTI::TCC_Basic; 3594 return TTI::TCC_Free; 3595 case Instruction::Store: 3596 ImmIdx = 0; 3597 break; 3598 case Instruction::ICmp: 3599 // This is an imperfect hack to prevent constant hoisting of 3600 // compares that might be trying to check if a 64-bit value fits in 3601 // 32-bits. The backend can optimize these cases using a right shift by 32. 3602 // Ideally we would check the compare predicate here. There also other 3603 // similar immediates the backend can use shifts for. 3604 if (Idx == 1 && Imm.getBitWidth() == 64) { 3605 uint64_t ImmVal = Imm.getZExtValue(); 3606 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 3607 return TTI::TCC_Free; 3608 } 3609 ImmIdx = 1; 3610 break; 3611 case Instruction::And: 3612 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 3613 // by using a 32-bit operation with implicit zero extension. Detect such 3614 // immediates here as the normal path expects bit 31 to be sign extended. 3615 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 3616 return TTI::TCC_Free; 3617 ImmIdx = 1; 3618 break; 3619 case Instruction::Add: 3620 case Instruction::Sub: 3621 // For add/sub, we can use the opposite instruction for INT32_MIN. 3622 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 3623 return TTI::TCC_Free; 3624 ImmIdx = 1; 3625 break; 3626 case Instruction::UDiv: 3627 case Instruction::SDiv: 3628 case Instruction::URem: 3629 case Instruction::SRem: 3630 // Division by constant is typically expanded later into a different 3631 // instruction sequence. This completely changes the constants. 3632 // Report them as "free" to stop ConstantHoist from marking them as opaque. 3633 return TTI::TCC_Free; 3634 case Instruction::Mul: 3635 case Instruction::Or: 3636 case Instruction::Xor: 3637 ImmIdx = 1; 3638 break; 3639 // Always return TCC_Free for the shift value of a shift instruction. 3640 case Instruction::Shl: 3641 case Instruction::LShr: 3642 case Instruction::AShr: 3643 if (Idx == 1) 3644 return TTI::TCC_Free; 3645 break; 3646 case Instruction::Trunc: 3647 case Instruction::ZExt: 3648 case Instruction::SExt: 3649 case Instruction::IntToPtr: 3650 case Instruction::PtrToInt: 3651 case Instruction::BitCast: 3652 case Instruction::PHI: 3653 case Instruction::Call: 3654 case Instruction::Select: 3655 case Instruction::Ret: 3656 case Instruction::Load: 3657 break; 3658 } 3659 3660 if (Idx == ImmIdx) { 3661 int NumConstants = divideCeil(BitSize, 64); 3662 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty); 3663 return (Cost <= NumConstants * TTI::TCC_Basic) 3664 ? static_cast<int>(TTI::TCC_Free) 3665 : Cost; 3666 } 3667 3668 return X86TTIImpl::getIntImmCost(Imm, Ty); 3669 } 3670 3671 int X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 3672 const APInt &Imm, Type *Ty) { 3673 assert(Ty->isIntegerTy()); 3674 3675 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3676 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3677 // here, so that constant hoisting will ignore this constant. 3678 if (BitSize == 0) 3679 return TTI::TCC_Free; 3680 3681 switch (IID) { 3682 default: 3683 return TTI::TCC_Free; 3684 case Intrinsic::sadd_with_overflow: 3685 case Intrinsic::uadd_with_overflow: 3686 case Intrinsic::ssub_with_overflow: 3687 case Intrinsic::usub_with_overflow: 3688 case Intrinsic::smul_with_overflow: 3689 case Intrinsic::umul_with_overflow: 3690 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 3691 return TTI::TCC_Free; 3692 break; 3693 case Intrinsic::experimental_stackmap: 3694 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 3695 return TTI::TCC_Free; 3696 break; 3697 case Intrinsic::experimental_patchpoint_void: 3698 case Intrinsic::experimental_patchpoint_i64: 3699 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 3700 return TTI::TCC_Free; 3701 break; 3702 } 3703 return X86TTIImpl::getIntImmCost(Imm, Ty); 3704 } 3705 3706 unsigned 3707 X86TTIImpl::getUserCost(const User *U, ArrayRef<const Value *> Operands, 3708 TTI::TargetCostKind CostKind) { 3709 if (isa<StoreInst>(U)) { 3710 Value *Ptr = U->getOperand(1); 3711 // Store instruction with index and scale costs 2 Uops. 3712 // Check the preceding GEP to identify non-const indices. 3713 if (auto GEP = dyn_cast<GetElementPtrInst>(Ptr)) { 3714 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3715 return TTI::TCC_Basic * 2; 3716 } 3717 return TTI::TCC_Basic; 3718 } 3719 return BaseT::getUserCost(U, Operands, CostKind); 3720 } 3721 3722 // Return an average cost of Gather / Scatter instruction, maybe improved later 3723 int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, Value *Ptr, 3724 unsigned Alignment, unsigned AddressSpace) { 3725 3726 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 3727 unsigned VF = cast<VectorType>(SrcVTy)->getNumElements(); 3728 3729 // Try to reduce index size from 64 bit (default for GEP) 3730 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 3731 // operation will use 16 x 64 indices which do not fit in a zmm and needs 3732 // to split. Also check that the base pointer is the same for all lanes, 3733 // and that there's at most one variable index. 3734 auto getIndexSizeInBits = [](Value *Ptr, const DataLayout& DL) { 3735 unsigned IndexSize = DL.getPointerSizeInBits(); 3736 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 3737 if (IndexSize < 64 || !GEP) 3738 return IndexSize; 3739 3740 unsigned NumOfVarIndices = 0; 3741 Value *Ptrs = GEP->getPointerOperand(); 3742 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 3743 return IndexSize; 3744 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 3745 if (isa<Constant>(GEP->getOperand(i))) 3746 continue; 3747 Type *IndxTy = GEP->getOperand(i)->getType(); 3748 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 3749 IndxTy = IndexVTy->getElementType(); 3750 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 3751 !isa<SExtInst>(GEP->getOperand(i))) || 3752 ++NumOfVarIndices > 1) 3753 return IndexSize; // 64 3754 } 3755 return (unsigned)32; 3756 }; 3757 3758 3759 // Trying to reduce IndexSize to 32 bits for vector 16. 3760 // By default the IndexSize is equal to pointer size. 3761 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 3762 ? getIndexSizeInBits(Ptr, DL) 3763 : DL.getPointerSizeInBits(); 3764 3765 Type *IndexVTy = VectorType::get(IntegerType::get(SrcVTy->getContext(), 3766 IndexSize), VF); 3767 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy); 3768 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3769 int SplitFactor = std::max(IdxsLT.first, SrcLT.first); 3770 if (SplitFactor > 1) { 3771 // Handle splitting of vector of pointers 3772 Type *SplitSrcTy = VectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 3773 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 3774 AddressSpace); 3775 } 3776 3777 // The gather / scatter cost is given by Intel architects. It is a rough 3778 // number since we are looking at one instruction in a time. 3779 const int GSOverhead = (Opcode == Instruction::Load) 3780 ? ST->getGatherOverhead() 3781 : ST->getScatterOverhead(); 3782 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3783 MaybeAlign(Alignment), AddressSpace); 3784 } 3785 3786 /// Return the cost of full scalarization of gather / scatter operation. 3787 /// 3788 /// Opcode - Load or Store instruction. 3789 /// SrcVTy - The type of the data vector that should be gathered or scattered. 3790 /// VariableMask - The mask is non-constant at compile time. 3791 /// Alignment - Alignment for one element. 3792 /// AddressSpace - pointer[s] address space. 3793 /// 3794 int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 3795 bool VariableMask, unsigned Alignment, 3796 unsigned AddressSpace) { 3797 unsigned VF = cast<VectorType>(SrcVTy)->getNumElements(); 3798 3799 int MaskUnpackCost = 0; 3800 if (VariableMask) { 3801 VectorType *MaskTy = 3802 VectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 3803 MaskUnpackCost = getScalarizationOverhead(MaskTy, false, true); 3804 int ScalarCompareCost = 3805 getCmpSelInstrCost(Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), 3806 nullptr); 3807 int BranchCost = getCFInstrCost(Instruction::Br); 3808 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 3809 } 3810 3811 // The cost of the scalar loads/stores. 3812 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3813 MaybeAlign(Alignment), AddressSpace); 3814 3815 int InsertExtractCost = 0; 3816 if (Opcode == Instruction::Load) 3817 for (unsigned i = 0; i < VF; ++i) 3818 // Add the cost of inserting each scalar load into the vector 3819 InsertExtractCost += 3820 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 3821 else 3822 for (unsigned i = 0; i < VF; ++i) 3823 // Add the cost of extracting each element out of the data vector 3824 InsertExtractCost += 3825 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 3826 3827 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 3828 } 3829 3830 /// Calculate the cost of Gather / Scatter operation 3831 int X86TTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *SrcVTy, 3832 Value *Ptr, bool VariableMask, 3833 unsigned Alignment, 3834 const Instruction *I = nullptr) { 3835 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 3836 unsigned VF = cast<VectorType>(SrcVTy)->getNumElements(); 3837 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 3838 if (!PtrTy && Ptr->getType()->isVectorTy()) 3839 PtrTy = dyn_cast<PointerType>( 3840 cast<VectorType>(Ptr->getType())->getElementType()); 3841 assert(PtrTy && "Unexpected type for Ptr argument"); 3842 unsigned AddressSpace = PtrTy->getAddressSpace(); 3843 3844 bool Scalarize = false; 3845 if ((Opcode == Instruction::Load && 3846 !isLegalMaskedGather(SrcVTy, MaybeAlign(Alignment))) || 3847 (Opcode == Instruction::Store && 3848 !isLegalMaskedScatter(SrcVTy, MaybeAlign(Alignment)))) 3849 Scalarize = true; 3850 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 3851 // Vector-4 of gather/scatter instruction does not exist on KNL. 3852 // We can extend it to 8 elements, but zeroing upper bits of 3853 // the mask vector will add more instructions. Right now we give the scalar 3854 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 3855 // is better in the VariableMask case. 3856 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 3857 Scalarize = true; 3858 3859 if (Scalarize) 3860 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 3861 AddressSpace); 3862 3863 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 3864 } 3865 3866 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 3867 TargetTransformInfo::LSRCost &C2) { 3868 // X86 specific here are "instruction number 1st priority". 3869 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 3870 C1.NumIVMuls, C1.NumBaseAdds, 3871 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 3872 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 3873 C2.NumIVMuls, C2.NumBaseAdds, 3874 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 3875 } 3876 3877 bool X86TTIImpl::canMacroFuseCmp() { 3878 return ST->hasMacroFusion() || ST->hasBranchFusion(); 3879 } 3880 3881 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, MaybeAlign Alignment) { 3882 if (!ST->hasAVX()) 3883 return false; 3884 3885 // The backend can't handle a single element vector. 3886 if (isa<VectorType>(DataTy) && 3887 cast<VectorType>(DataTy)->getNumElements() == 1) 3888 return false; 3889 Type *ScalarTy = DataTy->getScalarType(); 3890 3891 if (ScalarTy->isPointerTy()) 3892 return true; 3893 3894 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 3895 return true; 3896 3897 if (!ScalarTy->isIntegerTy()) 3898 return false; 3899 3900 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 3901 return IntWidth == 32 || IntWidth == 64 || 3902 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 3903 } 3904 3905 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, MaybeAlign Alignment) { 3906 return isLegalMaskedLoad(DataType, Alignment); 3907 } 3908 3909 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 3910 unsigned DataSize = DL.getTypeStoreSize(DataType); 3911 // The only supported nontemporal loads are for aligned vectors of 16 or 32 3912 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 3913 // (the equivalent stores only require AVX). 3914 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 3915 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 3916 3917 return false; 3918 } 3919 3920 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 3921 unsigned DataSize = DL.getTypeStoreSize(DataType); 3922 3923 // SSE4A supports nontemporal stores of float and double at arbitrary 3924 // alignment. 3925 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 3926 return true; 3927 3928 // Besides the SSE4A subtarget exception above, only aligned stores are 3929 // available nontemporaly on any other subtarget. And only stores with a size 3930 // of 4..32 bytes (powers of 2, only) are permitted. 3931 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 3932 !isPowerOf2_32(DataSize)) 3933 return false; 3934 3935 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 3936 // loads require AVX2). 3937 if (DataSize == 32) 3938 return ST->hasAVX(); 3939 else if (DataSize == 16) 3940 return ST->hasSSE1(); 3941 return true; 3942 } 3943 3944 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 3945 if (!isa<VectorType>(DataTy)) 3946 return false; 3947 3948 if (!ST->hasAVX512()) 3949 return false; 3950 3951 // The backend can't handle a single element vector. 3952 if (cast<VectorType>(DataTy)->getNumElements() == 1) 3953 return false; 3954 3955 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 3956 3957 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 3958 return true; 3959 3960 if (!ScalarTy->isIntegerTy()) 3961 return false; 3962 3963 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 3964 return IntWidth == 32 || IntWidth == 64 || 3965 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 3966 } 3967 3968 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 3969 return isLegalMaskedExpandLoad(DataTy); 3970 } 3971 3972 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, MaybeAlign Alignment) { 3973 // Some CPUs have better gather performance than others. 3974 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 3975 // enable gather with a -march. 3976 if (!(ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()))) 3977 return false; 3978 3979 // This function is called now in two cases: from the Loop Vectorizer 3980 // and from the Scalarizer. 3981 // When the Loop Vectorizer asks about legality of the feature, 3982 // the vectorization factor is not calculated yet. The Loop Vectorizer 3983 // sends a scalar type and the decision is based on the width of the 3984 // scalar element. 3985 // Later on, the cost model will estimate usage this intrinsic based on 3986 // the vector type. 3987 // The Scalarizer asks again about legality. It sends a vector type. 3988 // In this case we can reject non-power-of-2 vectors. 3989 // We also reject single element vectors as the type legalizer can't 3990 // scalarize it. 3991 if (auto *DataVTy = dyn_cast<VectorType>(DataTy)) { 3992 unsigned NumElts = DataVTy->getNumElements(); 3993 if (NumElts == 1 || !isPowerOf2_32(NumElts)) 3994 return false; 3995 } 3996 Type *ScalarTy = DataTy->getScalarType(); 3997 if (ScalarTy->isPointerTy()) 3998 return true; 3999 4000 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4001 return true; 4002 4003 if (!ScalarTy->isIntegerTy()) 4004 return false; 4005 4006 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4007 return IntWidth == 32 || IntWidth == 64; 4008 } 4009 4010 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, MaybeAlign Alignment) { 4011 // AVX2 doesn't support scatter 4012 if (!ST->hasAVX512()) 4013 return false; 4014 return isLegalMaskedGather(DataType, Alignment); 4015 } 4016 4017 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 4018 EVT VT = TLI->getValueType(DL, DataType); 4019 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 4020 } 4021 4022 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 4023 return false; 4024 } 4025 4026 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 4027 const Function *Callee) const { 4028 const TargetMachine &TM = getTLI()->getTargetMachine(); 4029 4030 // Work this as a subsetting of subtarget features. 4031 const FeatureBitset &CallerBits = 4032 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 4033 const FeatureBitset &CalleeBits = 4034 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 4035 4036 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 4037 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 4038 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 4039 } 4040 4041 bool X86TTIImpl::areFunctionArgsABICompatible( 4042 const Function *Caller, const Function *Callee, 4043 SmallPtrSetImpl<Argument *> &Args) const { 4044 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args)) 4045 return false; 4046 4047 // If we get here, we know the target features match. If one function 4048 // considers 512-bit vectors legal and the other does not, consider them 4049 // incompatible. 4050 const TargetMachine &TM = getTLI()->getTargetMachine(); 4051 4052 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 4053 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs()) 4054 return true; 4055 4056 // Consider the arguments compatible if they aren't vectors or aggregates. 4057 // FIXME: Look at the size of vectors. 4058 // FIXME: Look at the element types of aggregates to see if there are vectors. 4059 // FIXME: The API of this function seems intended to allow arguments 4060 // to be removed from the set, but the caller doesn't check if the set 4061 // becomes empty so that may not work in practice. 4062 return llvm::none_of(Args, [](Argument *A) { 4063 auto *EltTy = cast<PointerType>(A->getType())->getElementType(); 4064 return EltTy->isVectorTy() || EltTy->isAggregateType(); 4065 }); 4066 } 4067 4068 X86TTIImpl::TTI::MemCmpExpansionOptions 4069 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 4070 TTI::MemCmpExpansionOptions Options; 4071 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 4072 Options.NumLoadsPerBlock = 2; 4073 // All GPR and vector loads can be unaligned. 4074 Options.AllowOverlappingLoads = true; 4075 if (IsZeroCmp) { 4076 // Only enable vector loads for equality comparison. Right now the vector 4077 // version is not as fast for three way compare (see #33329). 4078 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 4079 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 4080 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 4081 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 4082 } 4083 if (ST->is64Bit()) { 4084 Options.LoadSizes.push_back(8); 4085 } 4086 Options.LoadSizes.push_back(4); 4087 Options.LoadSizes.push_back(2); 4088 Options.LoadSizes.push_back(1); 4089 return Options; 4090 } 4091 4092 bool X86TTIImpl::enableInterleavedAccessVectorization() { 4093 // TODO: We expect this to be beneficial regardless of arch, 4094 // but there are currently some unexplained performance artifacts on Atom. 4095 // As a temporary solution, disable on Atom. 4096 return !(ST->isAtom()); 4097 } 4098 4099 // Get estimation for interleaved load/store operations for AVX2. 4100 // \p Factor is the interleaved-access factor (stride) - number of 4101 // (interleaved) elements in the group. 4102 // \p Indices contains the indices for a strided load: when the 4103 // interleaved load has gaps they indicate which elements are used. 4104 // If Indices is empty (or if the number of indices is equal to the size 4105 // of the interleaved-access as given in \p Factor) the access has no gaps. 4106 // 4107 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 4108 // computing the cost using a generic formula as a function of generic 4109 // shuffles. We therefore use a lookup table instead, filled according to 4110 // the instruction sequences that codegen currently generates. 4111 int X86TTIImpl::getInterleavedMemoryOpCostAVX2(unsigned Opcode, Type *VecTy, 4112 unsigned Factor, 4113 ArrayRef<unsigned> Indices, 4114 unsigned Alignment, 4115 unsigned AddressSpace, 4116 bool UseMaskForCond, 4117 bool UseMaskForGaps) { 4118 4119 if (UseMaskForCond || UseMaskForGaps) 4120 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4121 Alignment, AddressSpace, 4122 UseMaskForCond, UseMaskForGaps); 4123 4124 // We currently Support only fully-interleaved groups, with no gaps. 4125 // TODO: Support also strided loads (interleaved-groups with gaps). 4126 if (Indices.size() && Indices.size() != Factor) 4127 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4128 Alignment, AddressSpace); 4129 4130 // VecTy for interleave memop is <VF*Factor x Elt>. 4131 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4132 // VecTy = <12 x i32>. 4133 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4134 4135 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 4136 // the VF=2, while v2i128 is an unsupported MVT vector type 4137 // (see MachineValueType.h::getVectorVT()). 4138 if (!LegalVT.isVector()) 4139 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4140 Alignment, AddressSpace); 4141 4142 unsigned VF = cast<VectorType>(VecTy)->getNumElements() / Factor; 4143 Type *ScalarTy = cast<VectorType>(VecTy)->getElementType(); 4144 4145 // Calculate the number of memory operations (NumOfMemOps), required 4146 // for load/store the VecTy. 4147 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4148 unsigned LegalVTSize = LegalVT.getStoreSize(); 4149 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4150 4151 // Get the cost of one memory operation. 4152 Type *SingleMemOpTy = 4153 VectorType::get(cast<VectorType>(VecTy)->getElementType(), 4154 LegalVT.getVectorNumElements()); 4155 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 4156 MaybeAlign(Alignment), AddressSpace); 4157 4158 VectorType *VT = VectorType::get(ScalarTy, VF); 4159 EVT ETy = TLI->getValueType(DL, VT); 4160 if (!ETy.isSimple()) 4161 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4162 Alignment, AddressSpace); 4163 4164 // TODO: Complete for other data-types and strides. 4165 // Each combination of Stride, ElementTy and VF results in a different 4166 // sequence; The cost tables are therefore accessed with: 4167 // Factor (stride) and VectorType=VFxElemType. 4168 // The Cost accounts only for the shuffle sequence; 4169 // The cost of the loads/stores is accounted for separately. 4170 // 4171 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 4172 { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64 4173 { 2, MVT::v4f64, 6 }, //(load 8f64 and) deinterleave into 2 x 4f64 4174 4175 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8 4176 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8 4177 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8 4178 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8 4179 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8 4180 { 3, MVT::v8f32, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32 4181 4182 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8 4183 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8 4184 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8 4185 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8 4186 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8 4187 4188 { 8, MVT::v8f32, 40 } //(load 64f32 and)deinterleave into 8 x 8f32 4189 }; 4190 4191 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 4192 { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store) 4193 { 2, MVT::v4f64, 6 }, //interleave into 2 x 4f64 into 8f64 (and store) 4194 4195 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store) 4196 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store) 4197 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store) 4198 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store) 4199 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store) 4200 4201 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store) 4202 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store) 4203 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store) 4204 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store) 4205 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store) 4206 }; 4207 4208 if (Opcode == Instruction::Load) { 4209 if (const auto *Entry = 4210 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 4211 return NumOfMemOps * MemOpCost + Entry->Cost; 4212 } else { 4213 assert(Opcode == Instruction::Store && 4214 "Expected Store Instruction at this point"); 4215 if (const auto *Entry = 4216 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 4217 return NumOfMemOps * MemOpCost + Entry->Cost; 4218 } 4219 4220 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4221 Alignment, AddressSpace); 4222 } 4223 4224 // Get estimation for interleaved load/store operations and strided load. 4225 // \p Indices contains indices for strided load. 4226 // \p Factor - the factor of interleaving. 4227 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 4228 int X86TTIImpl::getInterleavedMemoryOpCostAVX512(unsigned Opcode, Type *VecTy, 4229 unsigned Factor, 4230 ArrayRef<unsigned> Indices, 4231 unsigned Alignment, 4232 unsigned AddressSpace, 4233 bool UseMaskForCond, 4234 bool UseMaskForGaps) { 4235 4236 if (UseMaskForCond || UseMaskForGaps) 4237 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4238 Alignment, AddressSpace, 4239 UseMaskForCond, UseMaskForGaps); 4240 4241 // VecTy for interleave memop is <VF*Factor x Elt>. 4242 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4243 // VecTy = <12 x i32>. 4244 4245 // Calculate the number of memory operations (NumOfMemOps), required 4246 // for load/store the VecTy. 4247 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4248 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4249 unsigned LegalVTSize = LegalVT.getStoreSize(); 4250 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4251 4252 // Get the cost of one memory operation. 4253 auto *SingleMemOpTy = 4254 VectorType::get(cast<VectorType>(VecTy)->getElementType(), 4255 LegalVT.getVectorNumElements()); 4256 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 4257 MaybeAlign(Alignment), AddressSpace); 4258 4259 unsigned VF = cast<VectorType>(VecTy)->getNumElements() / Factor; 4260 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 4261 4262 if (Opcode == Instruction::Load) { 4263 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 4264 // contain the cost of the optimized shuffle sequence that the 4265 // X86InterleavedAccess pass will generate. 4266 // The cost of loads and stores are computed separately from the table. 4267 4268 // X86InterleavedAccess support only the following interleaved-access group. 4269 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 4270 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 4271 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 4272 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 4273 }; 4274 4275 if (const auto *Entry = 4276 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 4277 return NumOfMemOps * MemOpCost + Entry->Cost; 4278 //If an entry does not exist, fallback to the default implementation. 4279 4280 // Kind of shuffle depends on number of loaded values. 4281 // If we load the entire data in one register, we can use a 1-src shuffle. 4282 // Otherwise, we'll merge 2 sources in each operation. 4283 TTI::ShuffleKind ShuffleKind = 4284 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 4285 4286 unsigned ShuffleCost = 4287 getShuffleCost(ShuffleKind, SingleMemOpTy, 0, nullptr); 4288 4289 unsigned NumOfLoadsInInterleaveGrp = 4290 Indices.size() ? Indices.size() : Factor; 4291 Type *ResultTy = 4292 VectorType::get(cast<VectorType>(VecTy)->getElementType(), 4293 cast<VectorType>(VecTy)->getNumElements() / Factor); 4294 unsigned NumOfResults = 4295 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 4296 NumOfLoadsInInterleaveGrp; 4297 4298 // About a half of the loads may be folded in shuffles when we have only 4299 // one result. If we have more than one result, we do not fold loads at all. 4300 unsigned NumOfUnfoldedLoads = 4301 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 4302 4303 // Get a number of shuffle operations per result. 4304 unsigned NumOfShufflesPerResult = 4305 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 4306 4307 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4308 // When we have more than one destination, we need additional instructions 4309 // to keep sources. 4310 unsigned NumOfMoves = 0; 4311 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 4312 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 4313 4314 int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 4315 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 4316 4317 return Cost; 4318 } 4319 4320 // Store. 4321 assert(Opcode == Instruction::Store && 4322 "Expected Store Instruction at this point"); 4323 // X86InterleavedAccess support only the following interleaved-access group. 4324 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 4325 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 4326 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 4327 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 4328 4329 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 4330 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 4331 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 4332 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 4333 }; 4334 4335 if (const auto *Entry = 4336 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 4337 return NumOfMemOps * MemOpCost + Entry->Cost; 4338 //If an entry does not exist, fallback to the default implementation. 4339 4340 // There is no strided stores meanwhile. And store can't be folded in 4341 // shuffle. 4342 unsigned NumOfSources = Factor; // The number of values to be merged. 4343 unsigned ShuffleCost = 4344 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, 0, nullptr); 4345 unsigned NumOfShufflesPerStore = NumOfSources - 1; 4346 4347 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4348 // We need additional instructions to keep sources. 4349 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 4350 int Cost = NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 4351 NumOfMoves; 4352 return Cost; 4353 } 4354 4355 int X86TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, 4356 unsigned Factor, 4357 ArrayRef<unsigned> Indices, 4358 unsigned Alignment, 4359 unsigned AddressSpace, 4360 bool UseMaskForCond, 4361 bool UseMaskForGaps) { 4362 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 4363 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 4364 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 4365 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 4366 return true; 4367 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 4368 return HasBW; 4369 return false; 4370 }; 4371 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 4372 return getInterleavedMemoryOpCostAVX512(Opcode, VecTy, Factor, Indices, 4373 Alignment, AddressSpace, 4374 UseMaskForCond, UseMaskForGaps); 4375 if (ST->hasAVX2()) 4376 return getInterleavedMemoryOpCostAVX2(Opcode, VecTy, Factor, Indices, 4377 Alignment, AddressSpace, 4378 UseMaskForCond, UseMaskForGaps); 4379 4380 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4381 Alignment, AddressSpace, 4382 UseMaskForCond, UseMaskForGaps); 4383 } 4384