1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// \file 10 /// This file implements a TargetTransformInfo analysis pass specific to the 11 /// X86 target machine. It uses the target's detailed information to provide 12 /// more precise answers to certain TTI queries, while letting the target 13 /// independent and default TTI implementations handle the rest. 14 /// 15 //===----------------------------------------------------------------------===// 16 /// About Cost Model numbers used below it's necessary to say the following: 17 /// the numbers correspond to some "generic" X86 CPU instead of usage of 18 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 19 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 20 /// the lookups below the cost is based on Nehalem as that was the first CPU 21 /// to support that feature level and thus has most likely the worst case cost. 22 /// Some examples of other technologies/CPUs: 23 /// SSE 3 - Pentium4 / Athlon64 24 /// SSE 4.1 - Penryn 25 /// SSE 4.2 - Nehalem 26 /// AVX - Sandy Bridge 27 /// AVX2 - Haswell 28 /// AVX-512 - Xeon Phi / Skylake 29 /// And some examples of instruction target dependent costs (latency) 30 /// divss sqrtss rsqrtss 31 /// AMD K7 11-16 19 3 32 /// Piledriver 9-24 13-15 5 33 /// Jaguar 14 16 2 34 /// Pentium II,III 18 30 2 35 /// Nehalem 7-14 7-18 3 36 /// Haswell 10-13 11 5 37 /// TODO: Develop and implement the target dependent cost model and 38 /// specialize cost numbers for different Cost Model Targets such as throughput, 39 /// code size, latency and uop count. 40 //===----------------------------------------------------------------------===// 41 42 #include "X86TargetTransformInfo.h" 43 #include "llvm/Analysis/TargetTransformInfo.h" 44 #include "llvm/CodeGen/BasicTTIImpl.h" 45 #include "llvm/CodeGen/CostTable.h" 46 #include "llvm/CodeGen/TargetLowering.h" 47 #include "llvm/IR/IntrinsicInst.h" 48 #include "llvm/Support/Debug.h" 49 50 using namespace llvm; 51 52 #define DEBUG_TYPE "x86tti" 53 54 //===----------------------------------------------------------------------===// 55 // 56 // X86 cost model. 57 // 58 //===----------------------------------------------------------------------===// 59 60 TargetTransformInfo::PopcntSupportKind 61 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 62 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 63 // TODO: Currently the __builtin_popcount() implementation using SSE3 64 // instructions is inefficient. Once the problem is fixed, we should 65 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 66 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 67 } 68 69 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 70 TargetTransformInfo::CacheLevel Level) const { 71 switch (Level) { 72 case TargetTransformInfo::CacheLevel::L1D: 73 // - Penryn 74 // - Nehalem 75 // - Westmere 76 // - Sandy Bridge 77 // - Ivy Bridge 78 // - Haswell 79 // - Broadwell 80 // - Skylake 81 // - Kabylake 82 return 32 * 1024; // 32 KByte 83 case TargetTransformInfo::CacheLevel::L2D: 84 // - Penryn 85 // - Nehalem 86 // - Westmere 87 // - Sandy Bridge 88 // - Ivy Bridge 89 // - Haswell 90 // - Broadwell 91 // - Skylake 92 // - Kabylake 93 return 256 * 1024; // 256 KByte 94 } 95 96 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 97 } 98 99 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 100 TargetTransformInfo::CacheLevel Level) const { 101 // - Penryn 102 // - Nehalem 103 // - Westmere 104 // - Sandy Bridge 105 // - Ivy Bridge 106 // - Haswell 107 // - Broadwell 108 // - Skylake 109 // - Kabylake 110 switch (Level) { 111 case TargetTransformInfo::CacheLevel::L1D: 112 LLVM_FALLTHROUGH; 113 case TargetTransformInfo::CacheLevel::L2D: 114 return 8; 115 } 116 117 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 118 } 119 120 unsigned X86TTIImpl::getNumberOfRegisters(bool Vector) { 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const { 133 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 134 if (Vector) { 135 if (ST->hasAVX512() && PreferVectorWidth >= 512) 136 return 512; 137 if (ST->hasAVX() && PreferVectorWidth >= 256) 138 return 256; 139 if (ST->hasSSE1() && PreferVectorWidth >= 128) 140 return 128; 141 return 0; 142 } 143 144 if (ST->is64Bit()) 145 return 64; 146 147 return 32; 148 } 149 150 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 151 return getRegisterBitWidth(true); 152 } 153 154 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 155 // If the loop will not be vectorized, don't interleave the loop. 156 // Let regular unroll to unroll the loop, which saves the overflow 157 // check and memory check cost. 158 if (VF == 1) 159 return 1; 160 161 if (ST->isAtom()) 162 return 1; 163 164 // Sandybridge and Haswell have multiple execution ports and pipelined 165 // vector units. 166 if (ST->hasAVX()) 167 return 4; 168 169 return 2; 170 } 171 172 int X86TTIImpl::getArithmeticInstrCost( 173 unsigned Opcode, Type *Ty, 174 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 175 TTI::OperandValueProperties Opd1PropInfo, 176 TTI::OperandValueProperties Opd2PropInfo, 177 ArrayRef<const Value *> Args) { 178 // Legalize the type. 179 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 180 181 int ISD = TLI->InstructionOpcodeToISD(Opcode); 182 assert(ISD && "Invalid opcode"); 183 184 static const CostTblEntry GLMCostTable[] = { 185 { ISD::FDIV, MVT::f32, 18 }, // divss 186 { ISD::FDIV, MVT::v4f32, 35 }, // divps 187 { ISD::FDIV, MVT::f64, 33 }, // divsd 188 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 189 }; 190 191 if (ST->isGLM()) 192 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 193 LT.second)) 194 return LT.first * Entry->Cost; 195 196 static const CostTblEntry SLMCostTable[] = { 197 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 198 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 199 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. 200 { ISD::FMUL, MVT::f64, 2 }, // mulsd 201 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 202 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 203 { ISD::FDIV, MVT::f32, 17 }, // divss 204 { ISD::FDIV, MVT::v4f32, 39 }, // divps 205 { ISD::FDIV, MVT::f64, 32 }, // divsd 206 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 207 { ISD::FADD, MVT::v2f64, 2 }, // addpd 208 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 209 // v2i64/v4i64 mul is custom lowered as a series of long: 210 // multiplies(3), shifts(3) and adds(2) 211 // slm muldq version throughput is 2 and addq throughput 4 212 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 213 // 3X4 (addq throughput) = 17 214 { ISD::MUL, MVT::v2i64, 17 }, 215 // slm addq\subq throughput is 4 216 { ISD::ADD, MVT::v2i64, 4 }, 217 { ISD::SUB, MVT::v2i64, 4 }, 218 }; 219 220 if (ST->isSLM()) { 221 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 222 // Check if the operands can be shrinked into a smaller datatype. 223 bool Op1Signed = false; 224 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 225 bool Op2Signed = false; 226 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 227 228 bool signedMode = Op1Signed | Op2Signed; 229 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 230 231 if (OpMinSize <= 7) 232 return LT.first * 3; // pmullw/sext 233 if (!signedMode && OpMinSize <= 8) 234 return LT.first * 3; // pmullw/zext 235 if (OpMinSize <= 15) 236 return LT.first * 5; // pmullw/pmulhw/pshuf 237 if (!signedMode && OpMinSize <= 16) 238 return LT.first * 5; // pmullw/pmulhw/pshuf 239 } 240 241 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 242 LT.second)) { 243 return LT.first * Entry->Cost; 244 } 245 } 246 247 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 248 ISD == ISD::UREM) && 249 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 250 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 251 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 252 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 253 // On X86, vector signed division by constants power-of-two are 254 // normally expanded to the sequence SRA + SRL + ADD + SRA. 255 // The OperandValue properties may not be the same as that of the previous 256 // operation; conservatively assume OP_None. 257 int Cost = 258 2 * getArithmeticInstrCost(Instruction::AShr, Ty, Op1Info, Op2Info, 259 TargetTransformInfo::OP_None, 260 TargetTransformInfo::OP_None); 261 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 262 TargetTransformInfo::OP_None, 263 TargetTransformInfo::OP_None); 264 Cost += getArithmeticInstrCost(Instruction::Add, Ty, Op1Info, Op2Info, 265 TargetTransformInfo::OP_None, 266 TargetTransformInfo::OP_None); 267 268 if (ISD == ISD::SREM) { 269 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 270 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info); 271 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, Op1Info, Op2Info); 272 } 273 274 return Cost; 275 } 276 277 // Vector unsigned division/remainder will be simplified to shifts/masks. 278 if (ISD == ISD::UDIV) 279 return getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 280 TargetTransformInfo::OP_None, 281 TargetTransformInfo::OP_None); 282 283 if (ISD == ISD::UREM) 284 return getArithmeticInstrCost(Instruction::And, Ty, Op1Info, Op2Info, 285 TargetTransformInfo::OP_None, 286 TargetTransformInfo::OP_None); 287 } 288 289 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 290 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 291 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 292 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 293 }; 294 295 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 296 ST->hasBWI()) { 297 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 298 LT.second)) 299 return LT.first * Entry->Cost; 300 } 301 302 static const CostTblEntry AVX512UniformConstCostTable[] = { 303 { ISD::SRA, MVT::v2i64, 1 }, 304 { ISD::SRA, MVT::v4i64, 1 }, 305 { ISD::SRA, MVT::v8i64, 1 }, 306 }; 307 308 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 309 ST->hasAVX512()) { 310 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 311 LT.second)) 312 return LT.first * Entry->Cost; 313 } 314 315 static const CostTblEntry AVX2UniformConstCostTable[] = { 316 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 317 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 318 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 319 320 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 321 }; 322 323 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 324 ST->hasAVX2()) { 325 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 326 LT.second)) 327 return LT.first * Entry->Cost; 328 } 329 330 static const CostTblEntry SSE2UniformConstCostTable[] = { 331 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 332 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 333 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 334 335 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 336 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 337 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 338 }; 339 340 // XOP has faster vXi8 shifts. 341 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 342 ST->hasSSE2() && !ST->hasXOP()) { 343 if (const auto *Entry = 344 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 345 return LT.first * Entry->Cost; 346 } 347 348 static const CostTblEntry AVX512BWConstCostTable[] = { 349 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 350 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 351 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 352 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 353 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 354 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 355 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 356 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 357 }; 358 359 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 360 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 361 ST->hasBWI()) { 362 if (const auto *Entry = 363 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 364 return LT.first * Entry->Cost; 365 } 366 367 static const CostTblEntry AVX512ConstCostTable[] = { 368 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 369 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 370 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 371 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 372 }; 373 374 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 375 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 376 ST->hasAVX512()) { 377 if (const auto *Entry = 378 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 379 return LT.first * Entry->Cost; 380 } 381 382 static const CostTblEntry AVX2ConstCostTable[] = { 383 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 384 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 385 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 386 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 387 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 388 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 389 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 390 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 391 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 392 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 393 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 394 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 395 }; 396 397 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 398 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 399 ST->hasAVX2()) { 400 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 401 return LT.first * Entry->Cost; 402 } 403 404 static const CostTblEntry SSE2ConstCostTable[] = { 405 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 406 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 407 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 408 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 409 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 410 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 411 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 412 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 413 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 414 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 415 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 416 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 417 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 418 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 419 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 420 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 421 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 422 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 423 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 424 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 425 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 426 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 427 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 428 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 429 }; 430 431 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 432 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 433 ST->hasSSE2()) { 434 // pmuldq sequence. 435 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 436 return LT.first * 32; 437 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 438 return LT.first * 38; 439 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 440 return LT.first * 15; 441 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 442 return LT.first * 20; 443 444 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 445 return LT.first * Entry->Cost; 446 } 447 448 static const CostTblEntry AVX2UniformCostTable[] = { 449 // Uniform splats are cheaper for the following instructions. 450 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 451 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 452 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 453 }; 454 455 if (ST->hasAVX2() && 456 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 457 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 458 if (const auto *Entry = 459 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 460 return LT.first * Entry->Cost; 461 } 462 463 static const CostTblEntry SSE2UniformCostTable[] = { 464 // Uniform splats are cheaper for the following instructions. 465 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 466 { ISD::SHL, MVT::v4i32, 1 }, // pslld 467 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 468 469 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 470 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 471 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 472 473 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 474 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 475 }; 476 477 if (ST->hasSSE2() && 478 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 479 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 480 if (const auto *Entry = 481 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 482 return LT.first * Entry->Cost; 483 } 484 485 static const CostTblEntry AVX512DQCostTable[] = { 486 { ISD::MUL, MVT::v2i64, 1 }, 487 { ISD::MUL, MVT::v4i64, 1 }, 488 { ISD::MUL, MVT::v8i64, 1 } 489 }; 490 491 // Look for AVX512DQ lowering tricks for custom cases. 492 if (ST->hasDQI()) 493 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 494 return LT.first * Entry->Cost; 495 496 static const CostTblEntry AVX512BWCostTable[] = { 497 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 498 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 499 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 500 501 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 502 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 503 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 504 505 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 506 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 507 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 508 509 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 510 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 511 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 512 513 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence. 514 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence. 515 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence. 516 }; 517 518 // Look for AVX512BW lowering tricks for custom cases. 519 if (ST->hasBWI()) 520 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 521 return LT.first * Entry->Cost; 522 523 static const CostTblEntry AVX512CostTable[] = { 524 { ISD::SHL, MVT::v16i32, 1 }, 525 { ISD::SRL, MVT::v16i32, 1 }, 526 { ISD::SRA, MVT::v16i32, 1 }, 527 528 { ISD::SHL, MVT::v8i64, 1 }, 529 { ISD::SRL, MVT::v8i64, 1 }, 530 531 { ISD::SRA, MVT::v2i64, 1 }, 532 { ISD::SRA, MVT::v4i64, 1 }, 533 { ISD::SRA, MVT::v8i64, 1 }, 534 535 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence. 536 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence. 537 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 538 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 539 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 540 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add 541 542 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 543 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 544 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 545 546 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 547 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 548 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 549 }; 550 551 if (ST->hasAVX512()) 552 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 553 return LT.first * Entry->Cost; 554 555 static const CostTblEntry AVX2ShiftCostTable[] = { 556 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 557 // customize them to detect the cases where shift amount is a scalar one. 558 { ISD::SHL, MVT::v4i32, 1 }, 559 { ISD::SRL, MVT::v4i32, 1 }, 560 { ISD::SRA, MVT::v4i32, 1 }, 561 { ISD::SHL, MVT::v8i32, 1 }, 562 { ISD::SRL, MVT::v8i32, 1 }, 563 { ISD::SRA, MVT::v8i32, 1 }, 564 { ISD::SHL, MVT::v2i64, 1 }, 565 { ISD::SRL, MVT::v2i64, 1 }, 566 { ISD::SHL, MVT::v4i64, 1 }, 567 { ISD::SRL, MVT::v4i64, 1 }, 568 }; 569 570 // Look for AVX2 lowering tricks. 571 if (ST->hasAVX2()) { 572 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 573 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 574 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 575 // On AVX2, a packed v16i16 shift left by a constant build_vector 576 // is lowered into a vector multiply (vpmullw). 577 return getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info, 578 TargetTransformInfo::OP_None, 579 TargetTransformInfo::OP_None); 580 581 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 582 return LT.first * Entry->Cost; 583 } 584 585 static const CostTblEntry XOPShiftCostTable[] = { 586 // 128bit shifts take 1cy, but right shifts require negation beforehand. 587 { ISD::SHL, MVT::v16i8, 1 }, 588 { ISD::SRL, MVT::v16i8, 2 }, 589 { ISD::SRA, MVT::v16i8, 2 }, 590 { ISD::SHL, MVT::v8i16, 1 }, 591 { ISD::SRL, MVT::v8i16, 2 }, 592 { ISD::SRA, MVT::v8i16, 2 }, 593 { ISD::SHL, MVT::v4i32, 1 }, 594 { ISD::SRL, MVT::v4i32, 2 }, 595 { ISD::SRA, MVT::v4i32, 2 }, 596 { ISD::SHL, MVT::v2i64, 1 }, 597 { ISD::SRL, MVT::v2i64, 2 }, 598 { ISD::SRA, MVT::v2i64, 2 }, 599 // 256bit shifts require splitting if AVX2 didn't catch them above. 600 { ISD::SHL, MVT::v32i8, 2+2 }, 601 { ISD::SRL, MVT::v32i8, 4+2 }, 602 { ISD::SRA, MVT::v32i8, 4+2 }, 603 { ISD::SHL, MVT::v16i16, 2+2 }, 604 { ISD::SRL, MVT::v16i16, 4+2 }, 605 { ISD::SRA, MVT::v16i16, 4+2 }, 606 { ISD::SHL, MVT::v8i32, 2+2 }, 607 { ISD::SRL, MVT::v8i32, 4+2 }, 608 { ISD::SRA, MVT::v8i32, 4+2 }, 609 { ISD::SHL, MVT::v4i64, 2+2 }, 610 { ISD::SRL, MVT::v4i64, 4+2 }, 611 { ISD::SRA, MVT::v4i64, 4+2 }, 612 }; 613 614 // Look for XOP lowering tricks. 615 if (ST->hasXOP()) 616 if (const auto *Entry = CostTableLookup(XOPShiftCostTable, ISD, LT.second)) 617 return LT.first * Entry->Cost; 618 619 static const CostTblEntry SSE2UniformShiftCostTable[] = { 620 // Uniform splats are cheaper for the following instructions. 621 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 622 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 623 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 624 625 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 626 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 627 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 628 629 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 630 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 631 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 632 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 633 }; 634 635 if (ST->hasSSE2() && 636 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 637 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 638 639 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 640 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 641 return LT.first * 4; // 2*psrad + shuffle. 642 643 if (const auto *Entry = 644 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 645 return LT.first * Entry->Cost; 646 } 647 648 if (ISD == ISD::SHL && 649 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 650 MVT VT = LT.second; 651 // Vector shift left by non uniform constant can be lowered 652 // into vector multiply. 653 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 654 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 655 ISD = ISD::MUL; 656 } 657 658 static const CostTblEntry AVX2CostTable[] = { 659 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. 660 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 661 662 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. 663 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 664 665 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. 666 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. 667 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. 668 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 669 670 { ISD::SUB, MVT::v32i8, 1 }, // psubb 671 { ISD::ADD, MVT::v32i8, 1 }, // paddb 672 { ISD::SUB, MVT::v16i16, 1 }, // psubw 673 { ISD::ADD, MVT::v16i16, 1 }, // paddw 674 { ISD::SUB, MVT::v8i32, 1 }, // psubd 675 { ISD::ADD, MVT::v8i32, 1 }, // paddd 676 { ISD::SUB, MVT::v4i64, 1 }, // psubq 677 { ISD::ADD, MVT::v4i64, 1 }, // paddq 678 679 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence. 680 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence. 681 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 682 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 683 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add 684 685 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 686 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 687 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 688 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 689 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 690 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 691 692 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 693 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 694 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 695 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 696 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 697 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 698 }; 699 700 // Look for AVX2 lowering tricks for custom cases. 701 if (ST->hasAVX2()) 702 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 703 return LT.first * Entry->Cost; 704 705 static const CostTblEntry AVX1CostTable[] = { 706 // We don't have to scalarize unsupported ops. We can issue two half-sized 707 // operations and we only need to extract the upper YMM half. 708 // Two ops + 1 extract + 1 insert = 4. 709 { ISD::MUL, MVT::v16i16, 4 }, 710 { ISD::MUL, MVT::v8i32, 4 }, 711 { ISD::SUB, MVT::v32i8, 4 }, 712 { ISD::ADD, MVT::v32i8, 4 }, 713 { ISD::SUB, MVT::v16i16, 4 }, 714 { ISD::ADD, MVT::v16i16, 4 }, 715 { ISD::SUB, MVT::v8i32, 4 }, 716 { ISD::ADD, MVT::v8i32, 4 }, 717 { ISD::SUB, MVT::v4i64, 4 }, 718 { ISD::ADD, MVT::v4i64, 4 }, 719 720 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 721 // are lowered as a series of long multiplies(3), shifts(3) and adds(2) 722 // Because we believe v4i64 to be a legal type, we must also include the 723 // extract+insert in the cost table. Therefore, the cost here is 18 724 // instead of 8. 725 { ISD::MUL, MVT::v4i64, 18 }, 726 727 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence. 728 729 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 730 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 731 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 732 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 733 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 734 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 735 }; 736 737 if (ST->hasAVX()) 738 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 739 return LT.first * Entry->Cost; 740 741 static const CostTblEntry SSE42CostTable[] = { 742 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 743 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 744 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 745 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 746 747 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 748 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 749 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 750 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 751 752 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 753 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 754 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 755 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 756 757 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 758 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 759 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 760 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 761 }; 762 763 if (ST->hasSSE42()) 764 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 765 return LT.first * Entry->Cost; 766 767 static const CostTblEntry SSE41CostTable[] = { 768 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 769 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split. 770 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 771 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 772 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 773 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split 774 775 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 776 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split. 777 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 778 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 779 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 780 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split. 781 782 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 783 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split. 784 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 785 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 786 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 787 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split. 788 789 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 790 }; 791 792 if (ST->hasSSE41()) 793 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 794 return LT.first * Entry->Cost; 795 796 static const CostTblEntry SSE2CostTable[] = { 797 // We don't correctly identify costs of casts because they are marked as 798 // custom. 799 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 800 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 801 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 802 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 803 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 804 805 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 806 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 807 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 808 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 809 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 810 811 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 812 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 813 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 814 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 815 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split. 816 817 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence. 818 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 819 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 820 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 821 822 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 823 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 824 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 825 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 826 }; 827 828 if (ST->hasSSE2()) 829 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 830 return LT.first * Entry->Cost; 831 832 static const CostTblEntry SSE1CostTable[] = { 833 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 834 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 835 }; 836 837 if (ST->hasSSE1()) 838 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 839 return LT.first * Entry->Cost; 840 841 // It is not a good idea to vectorize division. We have to scalarize it and 842 // in the process we will often end up having to spilling regular 843 // registers. The overhead of division is going to dominate most kernels 844 // anyways so try hard to prevent vectorization of division - it is 845 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 846 // to hide "20 cycles" for each lane. 847 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 848 ISD == ISD::UDIV || ISD == ISD::UREM)) { 849 int ScalarCost = getArithmeticInstrCost( 850 Opcode, Ty->getScalarType(), Op1Info, Op2Info, 851 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 852 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 853 } 854 855 // Fallback to the default implementation. 856 return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info); 857 } 858 859 int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, 860 Type *SubTp) { 861 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 862 // 64-bit packed integer vectors (v2i32) are promoted to type v2i64. 863 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp); 864 865 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 866 if (Kind == TTI::SK_Transpose) 867 Kind = TTI::SK_PermuteTwoSrc; 868 869 // For Broadcasts we are splatting the first element from the first input 870 // register, so only need to reference that input and all the output 871 // registers are the same. 872 if (Kind == TTI::SK_Broadcast) 873 LT.first = 1; 874 875 // Subvector extractions are free if they start at beginning of the 876 // vector. 877 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector() && 878 ((Index % LT.second.getVectorNumElements()) == 0)) 879 return 0; 880 881 // We are going to permute multiple sources and the result will be in multiple 882 // destinations. Providing an accurate cost only for splits where the element 883 // type remains the same. 884 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 885 MVT LegalVT = LT.second; 886 if (LegalVT.isVector() && 887 LegalVT.getVectorElementType().getSizeInBits() == 888 Tp->getVectorElementType()->getPrimitiveSizeInBits() && 889 LegalVT.getVectorNumElements() < Tp->getVectorNumElements()) { 890 891 unsigned VecTySize = DL.getTypeStoreSize(Tp); 892 unsigned LegalVTSize = LegalVT.getStoreSize(); 893 // Number of source vectors after legalization: 894 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 895 // Number of destination vectors after legalization: 896 unsigned NumOfDests = LT.first; 897 898 Type *SingleOpTy = VectorType::get(Tp->getVectorElementType(), 899 LegalVT.getVectorNumElements()); 900 901 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 902 return NumOfShuffles * 903 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 0, nullptr); 904 } 905 906 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 907 } 908 909 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 910 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 911 // We assume that source and destination have the same vector type. 912 int NumOfDests = LT.first; 913 int NumOfShufflesPerDest = LT.first * 2 - 1; 914 LT.first = NumOfDests * NumOfShufflesPerDest; 915 } 916 917 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 918 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 919 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 920 921 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 922 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 923 924 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 1}, // vpermt2b 925 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 1}, // vpermt2b 926 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1} // vpermt2b 927 }; 928 929 if (ST->hasVBMI()) 930 if (const auto *Entry = 931 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 932 return LT.first * Entry->Cost; 933 934 static const CostTblEntry AVX512BWShuffleTbl[] = { 935 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 936 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 937 938 {TTI::SK_Reverse, MVT::v32i16, 1}, // vpermw 939 {TTI::SK_Reverse, MVT::v16i16, 1}, // vpermw 940 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 941 942 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 1}, // vpermw 943 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 1}, // vpermw 944 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // vpermw 945 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 946 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 3}, // vpermw + zext/trunc 947 948 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 1}, // vpermt2w 949 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 1}, // vpermt2w 950 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpermt2w 951 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 3}, // zext + vpermt2w + trunc 952 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 953 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3} // zext + vpermt2w + trunc 954 }; 955 956 if (ST->hasBWI()) 957 if (const auto *Entry = 958 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 959 return LT.first * Entry->Cost; 960 961 static const CostTblEntry AVX512ShuffleTbl[] = { 962 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 963 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 964 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 965 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 966 967 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 968 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 969 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 970 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 971 972 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 973 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 974 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 975 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 976 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 977 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 978 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 979 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 980 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 981 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 982 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 983 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 984 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 985 986 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 987 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 988 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 989 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 990 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 991 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 992 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 993 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 994 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 995 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 996 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 997 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1} // vpermt2d 998 }; 999 1000 if (ST->hasAVX512()) 1001 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1002 return LT.first * Entry->Cost; 1003 1004 static const CostTblEntry AVX2ShuffleTbl[] = { 1005 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1006 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1007 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1008 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1009 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1010 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1011 1012 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1013 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1014 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1015 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1016 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1017 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1018 1019 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1020 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1021 1022 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1023 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1024 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1025 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1026 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1027 // + vpblendvb 1028 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1029 // + vpblendvb 1030 1031 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1032 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1033 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1034 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1035 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1036 // + vpblendvb 1037 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1038 // + vpblendvb 1039 }; 1040 1041 if (ST->hasAVX2()) 1042 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1043 return LT.first * Entry->Cost; 1044 1045 static const CostTblEntry XOPShuffleTbl[] = { 1046 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1047 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1048 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1049 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1050 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1051 // + vinsertf128 1052 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1053 // + vinsertf128 1054 1055 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1056 // + vinsertf128 1057 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1058 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1059 // + vinsertf128 1060 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1061 }; 1062 1063 if (ST->hasXOP()) 1064 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1065 return LT.first * Entry->Cost; 1066 1067 static const CostTblEntry AVX1ShuffleTbl[] = { 1068 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1069 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1070 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1071 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1072 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1073 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1074 1075 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1076 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1077 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1078 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1079 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1080 // + vinsertf128 1081 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1082 // + vinsertf128 1083 1084 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1085 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1086 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1087 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1088 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1089 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1090 1091 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1092 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1093 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1094 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1095 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1096 // + 2*por + vinsertf128 1097 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1098 // + 2*por + vinsertf128 1099 1100 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1101 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1102 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1103 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1104 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1105 // + 4*por + vinsertf128 1106 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1107 // + 4*por + vinsertf128 1108 }; 1109 1110 if (ST->hasAVX()) 1111 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1112 return LT.first * Entry->Cost; 1113 1114 static const CostTblEntry SSE41ShuffleTbl[] = { 1115 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1116 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1117 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1118 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1119 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1120 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1121 }; 1122 1123 if (ST->hasSSE41()) 1124 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1125 return LT.first * Entry->Cost; 1126 1127 static const CostTblEntry SSSE3ShuffleTbl[] = { 1128 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1129 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1130 1131 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1132 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1133 1134 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1135 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1136 1137 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1138 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1139 1140 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1141 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1142 }; 1143 1144 if (ST->hasSSSE3()) 1145 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1146 return LT.first * Entry->Cost; 1147 1148 static const CostTblEntry SSE2ShuffleTbl[] = { 1149 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1150 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1151 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1152 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1153 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1154 1155 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1156 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1157 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1158 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1159 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1160 // + 2*pshufd + 2*unpck + packus 1161 1162 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1163 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1164 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1165 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1166 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1167 1168 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1169 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1170 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1171 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1172 // + pshufd/unpck 1173 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1174 // + 2*pshufd + 2*unpck + 2*packus 1175 1176 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1177 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1178 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1179 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1180 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1181 }; 1182 1183 if (ST->hasSSE2()) 1184 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1185 return LT.first * Entry->Cost; 1186 1187 static const CostTblEntry SSE1ShuffleTbl[] = { 1188 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1189 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1190 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1191 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1192 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1193 }; 1194 1195 if (ST->hasSSE1()) 1196 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1197 return LT.first * Entry->Cost; 1198 1199 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 1200 } 1201 1202 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 1203 const Instruction *I) { 1204 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1205 assert(ISD && "Invalid opcode"); 1206 1207 // FIXME: Need a better design of the cost table to handle non-simple types of 1208 // potential massive combinations (elem_num x src_type x dst_type). 1209 1210 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1211 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1212 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1213 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1214 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1215 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1216 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1217 1218 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1219 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1220 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1221 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1222 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1223 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1224 1225 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1226 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1227 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1228 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1229 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1230 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1231 1232 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1233 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1234 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1235 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1236 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1237 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1238 }; 1239 1240 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1241 // 256-bit wide vectors. 1242 1243 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1244 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1245 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1246 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1247 1248 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 }, 1249 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 }, 1250 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 }, 1251 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 1252 1253 // v16i1 -> v16i32 - load + broadcast 1254 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1255 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1256 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1257 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1258 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1259 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1260 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1261 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1262 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1263 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1264 1265 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1266 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1267 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1268 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1269 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1270 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1271 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1272 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1273 1274 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1275 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1276 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1277 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1278 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1279 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1280 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1281 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1282 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1283 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1284 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1285 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1286 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1287 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1288 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1289 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1290 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1291 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1292 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1293 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1294 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1295 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1296 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1297 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1298 1299 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1300 1301 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1302 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1303 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1304 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1305 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 2 }, 1306 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 2 }, 1307 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1308 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 2 }, 1309 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 2 }, 1310 }; 1311 1312 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1313 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1314 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1315 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1316 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1317 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 1318 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 1319 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 1320 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 1321 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1322 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1323 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1324 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1325 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1326 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1327 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1328 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1329 1330 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 1331 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 1332 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1333 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 1334 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1335 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 }, 1336 1337 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1338 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1339 1340 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1341 }; 1342 1343 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1344 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1345 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1346 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1347 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1348 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 }, 1349 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1350 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 7 }, 1351 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1352 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1353 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1354 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 }, 1355 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1356 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1357 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1358 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1359 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1360 1361 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 1362 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1363 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1364 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1365 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 1366 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 }, 1367 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 }, 1368 1369 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1370 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1371 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1372 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1373 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1374 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1375 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1376 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1377 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1378 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1379 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1380 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1381 1382 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1383 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1384 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1385 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1386 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1387 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1388 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1389 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1390 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1391 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 }, 1392 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 1393 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1394 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 1395 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1396 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1397 // The generic code to compute the scalar overhead is currently broken. 1398 // Workaround this limitation by estimating the scalarization overhead 1399 // here. We have roughly 10 instructions per scalar element. 1400 // Multiply that by the vector width. 1401 // FIXME: remove that when PR19268 is fixed. 1402 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1403 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1404 1405 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 }, 1406 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 }, 1407 // This node is expanded into scalarized operations but BasicTTI is overly 1408 // optimistic estimating its cost. It computes 3 per element (one 1409 // vector-extract, one scalar conversion and one vector-insert). The 1410 // problem is that the inserts form a read-modify-write chain so latency 1411 // should be factored in too. Inflating the cost per element by 1. 1412 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, 1413 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 1414 1415 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 1416 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 1417 }; 1418 1419 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 1420 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1421 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1422 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1423 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1424 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1425 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1426 1427 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1428 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 }, 1429 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1430 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1431 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1432 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1433 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1434 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1435 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1436 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1437 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1438 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1439 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1440 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1441 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1442 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1443 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1444 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1445 1446 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, 1447 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 1448 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 1449 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 1450 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 1451 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 1452 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 1453 1454 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 1455 }; 1456 1457 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 1458 // These are somewhat magic numbers justified by looking at the output of 1459 // Intel's IACA, running some kernels and making sure when we take 1460 // legalization into account the throughput will be overestimated. 1461 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1462 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1463 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1464 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1465 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1466 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1467 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1468 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 1469 1470 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1471 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1472 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1473 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1474 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1475 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, 1476 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 }, 1477 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1478 1479 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 3 }, 1480 1481 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 }, 1482 1483 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1484 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 1485 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 1486 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 1487 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1488 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 1489 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1490 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 1491 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1492 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1493 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1494 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1495 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 1496 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 1497 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1498 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 1499 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1500 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 1501 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1502 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1503 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 1504 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 1505 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1506 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 1507 1508 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 4 }, 1509 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, 1510 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 1511 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 1512 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 1513 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1514 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 1515 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1516 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 1517 }; 1518 1519 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 1520 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst); 1521 1522 if (ST->hasSSE2() && !ST->hasAVX()) { 1523 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1524 LTDest.second, LTSrc.second)) 1525 return LTSrc.first * Entry->Cost; 1526 } 1527 1528 EVT SrcTy = TLI->getValueType(DL, Src); 1529 EVT DstTy = TLI->getValueType(DL, Dst); 1530 1531 // The function getSimpleVT only handles simple value types. 1532 if (!SrcTy.isSimple() || !DstTy.isSimple()) 1533 return BaseT::getCastInstrCost(Opcode, Dst, Src); 1534 1535 if (ST->hasDQI()) 1536 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 1537 DstTy.getSimpleVT(), 1538 SrcTy.getSimpleVT())) 1539 return Entry->Cost; 1540 1541 if (ST->hasAVX512()) 1542 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 1543 DstTy.getSimpleVT(), 1544 SrcTy.getSimpleVT())) 1545 return Entry->Cost; 1546 1547 if (ST->hasAVX2()) { 1548 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 1549 DstTy.getSimpleVT(), 1550 SrcTy.getSimpleVT())) 1551 return Entry->Cost; 1552 } 1553 1554 if (ST->hasAVX()) { 1555 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 1556 DstTy.getSimpleVT(), 1557 SrcTy.getSimpleVT())) 1558 return Entry->Cost; 1559 } 1560 1561 if (ST->hasSSE41()) { 1562 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 1563 DstTy.getSimpleVT(), 1564 SrcTy.getSimpleVT())) 1565 return Entry->Cost; 1566 } 1567 1568 if (ST->hasSSE2()) { 1569 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1570 DstTy.getSimpleVT(), 1571 SrcTy.getSimpleVT())) 1572 return Entry->Cost; 1573 } 1574 1575 return BaseT::getCastInstrCost(Opcode, Dst, Src, I); 1576 } 1577 1578 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 1579 const Instruction *I) { 1580 // Legalize the type. 1581 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 1582 1583 MVT MTy = LT.second; 1584 1585 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1586 assert(ISD && "Invalid opcode"); 1587 1588 static const CostTblEntry SSE2CostTbl[] = { 1589 { ISD::SETCC, MVT::v2i64, 8 }, 1590 { ISD::SETCC, MVT::v4i32, 1 }, 1591 { ISD::SETCC, MVT::v8i16, 1 }, 1592 { ISD::SETCC, MVT::v16i8, 1 }, 1593 }; 1594 1595 static const CostTblEntry SSE42CostTbl[] = { 1596 { ISD::SETCC, MVT::v2f64, 1 }, 1597 { ISD::SETCC, MVT::v4f32, 1 }, 1598 { ISD::SETCC, MVT::v2i64, 1 }, 1599 }; 1600 1601 static const CostTblEntry AVX1CostTbl[] = { 1602 { ISD::SETCC, MVT::v4f64, 1 }, 1603 { ISD::SETCC, MVT::v8f32, 1 }, 1604 // AVX1 does not support 8-wide integer compare. 1605 { ISD::SETCC, MVT::v4i64, 4 }, 1606 { ISD::SETCC, MVT::v8i32, 4 }, 1607 { ISD::SETCC, MVT::v16i16, 4 }, 1608 { ISD::SETCC, MVT::v32i8, 4 }, 1609 }; 1610 1611 static const CostTblEntry AVX2CostTbl[] = { 1612 { ISD::SETCC, MVT::v4i64, 1 }, 1613 { ISD::SETCC, MVT::v8i32, 1 }, 1614 { ISD::SETCC, MVT::v16i16, 1 }, 1615 { ISD::SETCC, MVT::v32i8, 1 }, 1616 }; 1617 1618 static const CostTblEntry AVX512CostTbl[] = { 1619 { ISD::SETCC, MVT::v8i64, 1 }, 1620 { ISD::SETCC, MVT::v16i32, 1 }, 1621 { ISD::SETCC, MVT::v8f64, 1 }, 1622 { ISD::SETCC, MVT::v16f32, 1 }, 1623 }; 1624 1625 static const CostTblEntry AVX512BWCostTbl[] = { 1626 { ISD::SETCC, MVT::v32i16, 1 }, 1627 { ISD::SETCC, MVT::v64i8, 1 }, 1628 }; 1629 1630 if (ST->hasBWI()) 1631 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 1632 return LT.first * Entry->Cost; 1633 1634 if (ST->hasAVX512()) 1635 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 1636 return LT.first * Entry->Cost; 1637 1638 if (ST->hasAVX2()) 1639 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 1640 return LT.first * Entry->Cost; 1641 1642 if (ST->hasAVX()) 1643 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 1644 return LT.first * Entry->Cost; 1645 1646 if (ST->hasSSE42()) 1647 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 1648 return LT.first * Entry->Cost; 1649 1650 if (ST->hasSSE2()) 1651 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 1652 return LT.first * Entry->Cost; 1653 1654 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I); 1655 } 1656 1657 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 1658 1659 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 1660 ArrayRef<Type *> Tys, FastMathFlags FMF, 1661 unsigned ScalarizationCostPassed) { 1662 // Costs should match the codegen from: 1663 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 1664 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 1665 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 1666 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 1667 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 1668 static const CostTblEntry AVX512CDCostTbl[] = { 1669 { ISD::CTLZ, MVT::v8i64, 1 }, 1670 { ISD::CTLZ, MVT::v16i32, 1 }, 1671 { ISD::CTLZ, MVT::v32i16, 8 }, 1672 { ISD::CTLZ, MVT::v64i8, 20 }, 1673 { ISD::CTLZ, MVT::v4i64, 1 }, 1674 { ISD::CTLZ, MVT::v8i32, 1 }, 1675 { ISD::CTLZ, MVT::v16i16, 4 }, 1676 { ISD::CTLZ, MVT::v32i8, 10 }, 1677 { ISD::CTLZ, MVT::v2i64, 1 }, 1678 { ISD::CTLZ, MVT::v4i32, 1 }, 1679 { ISD::CTLZ, MVT::v8i16, 4 }, 1680 { ISD::CTLZ, MVT::v16i8, 4 }, 1681 }; 1682 static const CostTblEntry AVX512BWCostTbl[] = { 1683 { ISD::BITREVERSE, MVT::v8i64, 5 }, 1684 { ISD::BITREVERSE, MVT::v16i32, 5 }, 1685 { ISD::BITREVERSE, MVT::v32i16, 5 }, 1686 { ISD::BITREVERSE, MVT::v64i8, 5 }, 1687 { ISD::CTLZ, MVT::v8i64, 23 }, 1688 { ISD::CTLZ, MVT::v16i32, 22 }, 1689 { ISD::CTLZ, MVT::v32i16, 18 }, 1690 { ISD::CTLZ, MVT::v64i8, 17 }, 1691 { ISD::CTPOP, MVT::v8i64, 7 }, 1692 { ISD::CTPOP, MVT::v16i32, 11 }, 1693 { ISD::CTPOP, MVT::v32i16, 9 }, 1694 { ISD::CTPOP, MVT::v64i8, 6 }, 1695 { ISD::CTTZ, MVT::v8i64, 10 }, 1696 { ISD::CTTZ, MVT::v16i32, 14 }, 1697 { ISD::CTTZ, MVT::v32i16, 12 }, 1698 { ISD::CTTZ, MVT::v64i8, 9 }, 1699 }; 1700 static const CostTblEntry AVX512CostTbl[] = { 1701 { ISD::BITREVERSE, MVT::v8i64, 36 }, 1702 { ISD::BITREVERSE, MVT::v16i32, 24 }, 1703 { ISD::CTLZ, MVT::v8i64, 29 }, 1704 { ISD::CTLZ, MVT::v16i32, 35 }, 1705 { ISD::CTPOP, MVT::v8i64, 16 }, 1706 { ISD::CTPOP, MVT::v16i32, 24 }, 1707 { ISD::CTTZ, MVT::v8i64, 20 }, 1708 { ISD::CTTZ, MVT::v16i32, 28 }, 1709 }; 1710 static const CostTblEntry XOPCostTbl[] = { 1711 { ISD::BITREVERSE, MVT::v4i64, 4 }, 1712 { ISD::BITREVERSE, MVT::v8i32, 4 }, 1713 { ISD::BITREVERSE, MVT::v16i16, 4 }, 1714 { ISD::BITREVERSE, MVT::v32i8, 4 }, 1715 { ISD::BITREVERSE, MVT::v2i64, 1 }, 1716 { ISD::BITREVERSE, MVT::v4i32, 1 }, 1717 { ISD::BITREVERSE, MVT::v8i16, 1 }, 1718 { ISD::BITREVERSE, MVT::v16i8, 1 }, 1719 { ISD::BITREVERSE, MVT::i64, 3 }, 1720 { ISD::BITREVERSE, MVT::i32, 3 }, 1721 { ISD::BITREVERSE, MVT::i16, 3 }, 1722 { ISD::BITREVERSE, MVT::i8, 3 } 1723 }; 1724 static const CostTblEntry AVX2CostTbl[] = { 1725 { ISD::BITREVERSE, MVT::v4i64, 5 }, 1726 { ISD::BITREVERSE, MVT::v8i32, 5 }, 1727 { ISD::BITREVERSE, MVT::v16i16, 5 }, 1728 { ISD::BITREVERSE, MVT::v32i8, 5 }, 1729 { ISD::BSWAP, MVT::v4i64, 1 }, 1730 { ISD::BSWAP, MVT::v8i32, 1 }, 1731 { ISD::BSWAP, MVT::v16i16, 1 }, 1732 { ISD::CTLZ, MVT::v4i64, 23 }, 1733 { ISD::CTLZ, MVT::v8i32, 18 }, 1734 { ISD::CTLZ, MVT::v16i16, 14 }, 1735 { ISD::CTLZ, MVT::v32i8, 9 }, 1736 { ISD::CTPOP, MVT::v4i64, 7 }, 1737 { ISD::CTPOP, MVT::v8i32, 11 }, 1738 { ISD::CTPOP, MVT::v16i16, 9 }, 1739 { ISD::CTPOP, MVT::v32i8, 6 }, 1740 { ISD::CTTZ, MVT::v4i64, 10 }, 1741 { ISD::CTTZ, MVT::v8i32, 14 }, 1742 { ISD::CTTZ, MVT::v16i16, 12 }, 1743 { ISD::CTTZ, MVT::v32i8, 9 }, 1744 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 1745 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 1746 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 1747 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 1748 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 1749 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 1750 }; 1751 static const CostTblEntry AVX1CostTbl[] = { 1752 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 1753 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 1754 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 1755 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 1756 { ISD::BSWAP, MVT::v4i64, 4 }, 1757 { ISD::BSWAP, MVT::v8i32, 4 }, 1758 { ISD::BSWAP, MVT::v16i16, 4 }, 1759 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 1760 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 1761 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 1762 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 1763 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 1764 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 1765 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 1766 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 1767 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 1768 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 1769 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 1770 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 1771 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 1772 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 1773 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 1774 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 1775 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 1776 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 1777 }; 1778 static const CostTblEntry GLMCostTbl[] = { 1779 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 1780 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 1781 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 1782 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 1783 }; 1784 static const CostTblEntry SLMCostTbl[] = { 1785 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 1786 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 1787 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 1788 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 1789 }; 1790 static const CostTblEntry SSE42CostTbl[] = { 1791 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 1792 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 1793 }; 1794 static const CostTblEntry SSSE3CostTbl[] = { 1795 { ISD::BITREVERSE, MVT::v2i64, 5 }, 1796 { ISD::BITREVERSE, MVT::v4i32, 5 }, 1797 { ISD::BITREVERSE, MVT::v8i16, 5 }, 1798 { ISD::BITREVERSE, MVT::v16i8, 5 }, 1799 { ISD::BSWAP, MVT::v2i64, 1 }, 1800 { ISD::BSWAP, MVT::v4i32, 1 }, 1801 { ISD::BSWAP, MVT::v8i16, 1 }, 1802 { ISD::CTLZ, MVT::v2i64, 23 }, 1803 { ISD::CTLZ, MVT::v4i32, 18 }, 1804 { ISD::CTLZ, MVT::v8i16, 14 }, 1805 { ISD::CTLZ, MVT::v16i8, 9 }, 1806 { ISD::CTPOP, MVT::v2i64, 7 }, 1807 { ISD::CTPOP, MVT::v4i32, 11 }, 1808 { ISD::CTPOP, MVT::v8i16, 9 }, 1809 { ISD::CTPOP, MVT::v16i8, 6 }, 1810 { ISD::CTTZ, MVT::v2i64, 10 }, 1811 { ISD::CTTZ, MVT::v4i32, 14 }, 1812 { ISD::CTTZ, MVT::v8i16, 12 }, 1813 { ISD::CTTZ, MVT::v16i8, 9 } 1814 }; 1815 static const CostTblEntry SSE2CostTbl[] = { 1816 { ISD::BITREVERSE, MVT::v2i64, 29 }, 1817 { ISD::BITREVERSE, MVT::v4i32, 27 }, 1818 { ISD::BITREVERSE, MVT::v8i16, 27 }, 1819 { ISD::BITREVERSE, MVT::v16i8, 20 }, 1820 { ISD::BSWAP, MVT::v2i64, 7 }, 1821 { ISD::BSWAP, MVT::v4i32, 7 }, 1822 { ISD::BSWAP, MVT::v8i16, 7 }, 1823 { ISD::CTLZ, MVT::v2i64, 25 }, 1824 { ISD::CTLZ, MVT::v4i32, 26 }, 1825 { ISD::CTLZ, MVT::v8i16, 20 }, 1826 { ISD::CTLZ, MVT::v16i8, 17 }, 1827 { ISD::CTPOP, MVT::v2i64, 12 }, 1828 { ISD::CTPOP, MVT::v4i32, 15 }, 1829 { ISD::CTPOP, MVT::v8i16, 13 }, 1830 { ISD::CTPOP, MVT::v16i8, 10 }, 1831 { ISD::CTTZ, MVT::v2i64, 14 }, 1832 { ISD::CTTZ, MVT::v4i32, 18 }, 1833 { ISD::CTTZ, MVT::v8i16, 16 }, 1834 { ISD::CTTZ, MVT::v16i8, 13 }, 1835 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 1836 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 1837 }; 1838 static const CostTblEntry SSE1CostTbl[] = { 1839 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 1840 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 1841 }; 1842 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 1843 { ISD::BITREVERSE, MVT::i64, 14 } 1844 }; 1845 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 1846 { ISD::BITREVERSE, MVT::i32, 14 }, 1847 { ISD::BITREVERSE, MVT::i16, 14 }, 1848 { ISD::BITREVERSE, MVT::i8, 11 } 1849 }; 1850 1851 unsigned ISD = ISD::DELETED_NODE; 1852 switch (IID) { 1853 default: 1854 break; 1855 case Intrinsic::bitreverse: 1856 ISD = ISD::BITREVERSE; 1857 break; 1858 case Intrinsic::bswap: 1859 ISD = ISD::BSWAP; 1860 break; 1861 case Intrinsic::ctlz: 1862 ISD = ISD::CTLZ; 1863 break; 1864 case Intrinsic::ctpop: 1865 ISD = ISD::CTPOP; 1866 break; 1867 case Intrinsic::cttz: 1868 ISD = ISD::CTTZ; 1869 break; 1870 case Intrinsic::sqrt: 1871 ISD = ISD::FSQRT; 1872 break; 1873 } 1874 1875 // Legalize the type. 1876 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 1877 MVT MTy = LT.second; 1878 1879 // Attempt to lookup cost. 1880 if (ST->isGLM()) 1881 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 1882 return LT.first * Entry->Cost; 1883 1884 if (ST->isSLM()) 1885 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 1886 return LT.first * Entry->Cost; 1887 1888 if (ST->hasCDI()) 1889 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 1890 return LT.first * Entry->Cost; 1891 1892 if (ST->hasBWI()) 1893 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 1894 return LT.first * Entry->Cost; 1895 1896 if (ST->hasAVX512()) 1897 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 1898 return LT.first * Entry->Cost; 1899 1900 if (ST->hasXOP()) 1901 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 1902 return LT.first * Entry->Cost; 1903 1904 if (ST->hasAVX2()) 1905 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 1906 return LT.first * Entry->Cost; 1907 1908 if (ST->hasAVX()) 1909 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 1910 return LT.first * Entry->Cost; 1911 1912 if (ST->hasSSE42()) 1913 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 1914 return LT.first * Entry->Cost; 1915 1916 if (ST->hasSSSE3()) 1917 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 1918 return LT.first * Entry->Cost; 1919 1920 if (ST->hasSSE2()) 1921 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 1922 return LT.first * Entry->Cost; 1923 1924 if (ST->hasSSE1()) 1925 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 1926 return LT.first * Entry->Cost; 1927 1928 if (ST->is64Bit()) 1929 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 1930 return LT.first * Entry->Cost; 1931 1932 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 1933 return LT.first * Entry->Cost; 1934 1935 return BaseT::getIntrinsicInstrCost(IID, RetTy, Tys, FMF, ScalarizationCostPassed); 1936 } 1937 1938 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 1939 ArrayRef<Value *> Args, FastMathFlags FMF, unsigned VF) { 1940 return BaseT::getIntrinsicInstrCost(IID, RetTy, Args, FMF, VF); 1941 } 1942 1943 int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { 1944 assert(Val->isVectorTy() && "This must be a vector type"); 1945 1946 Type *ScalarType = Val->getScalarType(); 1947 1948 if (Index != -1U) { 1949 // Legalize the type. 1950 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 1951 1952 // This type is legalized to a scalar type. 1953 if (!LT.second.isVector()) 1954 return 0; 1955 1956 // The type may be split. Normalize the index to the new type. 1957 unsigned Width = LT.second.getVectorNumElements(); 1958 Index = Index % Width; 1959 1960 // Floating point scalars are already located in index #0. 1961 if (ScalarType->isFloatingPointTy() && Index == 0) 1962 return 0; 1963 } 1964 1965 // Add to the base cost if we know that the extracted element of a vector is 1966 // destined to be moved to and used in the integer register file. 1967 int RegisterFileMoveCost = 0; 1968 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 1969 RegisterFileMoveCost = 1; 1970 1971 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 1972 } 1973 1974 int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, 1975 unsigned AddressSpace, const Instruction *I) { 1976 // Handle non-power-of-two vectors such as <3 x float> 1977 if (VectorType *VTy = dyn_cast<VectorType>(Src)) { 1978 unsigned NumElem = VTy->getVectorNumElements(); 1979 1980 // Handle a few common cases: 1981 // <3 x float> 1982 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 1983 // Cost = 64 bit store + extract + 32 bit store. 1984 return 3; 1985 1986 // <3 x double> 1987 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 1988 // Cost = 128 bit store + unpack + 64 bit store. 1989 return 3; 1990 1991 // Assume that all other non-power-of-two numbers are scalarized. 1992 if (!isPowerOf2_32(NumElem)) { 1993 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment, 1994 AddressSpace); 1995 int SplitCost = getScalarizationOverhead(Src, Opcode == Instruction::Load, 1996 Opcode == Instruction::Store); 1997 return NumElem * Cost + SplitCost; 1998 } 1999 } 2000 2001 // Legalize the type. 2002 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 2003 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 2004 "Invalid Opcode"); 2005 2006 // Each load/store unit costs 1. 2007 int Cost = LT.first * 1; 2008 2009 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a 2010 // proxy for a double-pumped AVX memory interface such as on Sandybridge. 2011 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow()) 2012 Cost *= 2; 2013 2014 return Cost; 2015 } 2016 2017 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, 2018 unsigned Alignment, 2019 unsigned AddressSpace) { 2020 VectorType *SrcVTy = dyn_cast<VectorType>(SrcTy); 2021 if (!SrcVTy) 2022 // To calculate scalar take the regular cost, without mask 2023 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace); 2024 2025 unsigned NumElem = SrcVTy->getVectorNumElements(); 2026 VectorType *MaskTy = 2027 VectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 2028 if ((Opcode == Instruction::Load && !isLegalMaskedLoad(SrcVTy)) || 2029 (Opcode == Instruction::Store && !isLegalMaskedStore(SrcVTy)) || 2030 !isPowerOf2_32(NumElem)) { 2031 // Scalarization 2032 int MaskSplitCost = getScalarizationOverhead(MaskTy, false, true); 2033 int ScalarCompareCost = getCmpSelInstrCost( 2034 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr); 2035 int BranchCost = getCFInstrCost(Instruction::Br); 2036 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 2037 2038 int ValueSplitCost = getScalarizationOverhead( 2039 SrcVTy, Opcode == Instruction::Load, Opcode == Instruction::Store); 2040 int MemopCost = 2041 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2042 Alignment, AddressSpace); 2043 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 2044 } 2045 2046 // Legalize the type. 2047 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 2048 auto VT = TLI->getValueType(DL, SrcVTy); 2049 int Cost = 0; 2050 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 2051 LT.second.getVectorNumElements() == NumElem) 2052 // Promotion requires expand/truncate for data and a shuffle for mask. 2053 Cost += getShuffleCost(TTI::SK_Select, SrcVTy, 0, nullptr) + 2054 getShuffleCost(TTI::SK_Select, MaskTy, 0, nullptr); 2055 2056 else if (LT.second.getVectorNumElements() > NumElem) { 2057 VectorType *NewMaskTy = VectorType::get(MaskTy->getVectorElementType(), 2058 LT.second.getVectorNumElements()); 2059 // Expanding requires fill mask with zeroes 2060 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, 0, MaskTy); 2061 } 2062 if (!ST->hasAVX512()) 2063 return Cost + LT.first*4; // Each maskmov costs 4 2064 2065 // AVX-512 masked load/store is cheapper 2066 return Cost+LT.first; 2067 } 2068 2069 int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE, 2070 const SCEV *Ptr) { 2071 // Address computations in vectorized code with non-consecutive addresses will 2072 // likely result in more instructions compared to scalar code where the 2073 // computation can more often be merged into the index mode. The resulting 2074 // extra micro-ops can significantly decrease throughput. 2075 unsigned NumVectorInstToHideOverhead = 10; 2076 2077 // Cost modeling of Strided Access Computation is hidden by the indexing 2078 // modes of X86 regardless of the stride value. We dont believe that there 2079 // is a difference between constant strided access in gerenal and constant 2080 // strided value which is less than or equal to 64. 2081 // Even in the case of (loop invariant) stride whose value is not known at 2082 // compile time, the address computation will not incur more than one extra 2083 // ADD instruction. 2084 if (Ty->isVectorTy() && SE) { 2085 if (!BaseT::isStridedAccess(Ptr)) 2086 return NumVectorInstToHideOverhead; 2087 if (!BaseT::getConstantStrideStep(SE, Ptr)) 2088 return 1; 2089 } 2090 2091 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 2092 } 2093 2094 int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, Type *ValTy, 2095 bool IsPairwise) { 2096 2097 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2098 2099 MVT MTy = LT.second; 2100 2101 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2102 assert(ISD && "Invalid opcode"); 2103 2104 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 2105 // and make it as the cost. 2106 2107 static const CostTblEntry SSE42CostTblPairWise[] = { 2108 { ISD::FADD, MVT::v2f64, 2 }, 2109 { ISD::FADD, MVT::v4f32, 4 }, 2110 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 2111 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5". 2112 { ISD::ADD, MVT::v8i16, 5 }, 2113 }; 2114 2115 static const CostTblEntry AVX1CostTblPairWise[] = { 2116 { ISD::FADD, MVT::v4f32, 4 }, 2117 { ISD::FADD, MVT::v4f64, 5 }, 2118 { ISD::FADD, MVT::v8f32, 7 }, 2119 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 2120 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5". 2121 { ISD::ADD, MVT::v4i64, 5 }, // The data reported by the IACA tool is "4.8". 2122 { ISD::ADD, MVT::v8i16, 5 }, 2123 { ISD::ADD, MVT::v8i32, 5 }, 2124 }; 2125 2126 static const CostTblEntry SSE42CostTblNoPairWise[] = { 2127 { ISD::FADD, MVT::v2f64, 2 }, 2128 { ISD::FADD, MVT::v4f32, 4 }, 2129 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 2130 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 2131 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 2132 }; 2133 2134 static const CostTblEntry AVX1CostTblNoPairWise[] = { 2135 { ISD::FADD, MVT::v4f32, 3 }, 2136 { ISD::FADD, MVT::v4f64, 3 }, 2137 { ISD::FADD, MVT::v8f32, 4 }, 2138 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 2139 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "2.8". 2140 { ISD::ADD, MVT::v4i64, 3 }, 2141 { ISD::ADD, MVT::v8i16, 4 }, 2142 { ISD::ADD, MVT::v8i32, 5 }, 2143 }; 2144 2145 if (IsPairwise) { 2146 if (ST->hasAVX()) 2147 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy)) 2148 return LT.first * Entry->Cost; 2149 2150 if (ST->hasSSE42()) 2151 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy)) 2152 return LT.first * Entry->Cost; 2153 } else { 2154 if (ST->hasAVX()) 2155 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 2156 return LT.first * Entry->Cost; 2157 2158 if (ST->hasSSE42()) 2159 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy)) 2160 return LT.first * Entry->Cost; 2161 } 2162 2163 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise); 2164 } 2165 2166 int X86TTIImpl::getMinMaxReductionCost(Type *ValTy, Type *CondTy, 2167 bool IsPairwise, bool IsUnsigned) { 2168 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2169 2170 MVT MTy = LT.second; 2171 2172 int ISD; 2173 if (ValTy->isIntOrIntVectorTy()) { 2174 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 2175 } else { 2176 assert(ValTy->isFPOrFPVectorTy() && 2177 "Expected float point or integer vector type."); 2178 ISD = ISD::FMINNUM; 2179 } 2180 2181 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 2182 // and make it as the cost. 2183 2184 static const CostTblEntry SSE42CostTblPairWise[] = { 2185 {ISD::FMINNUM, MVT::v2f64, 3}, 2186 {ISD::FMINNUM, MVT::v4f32, 2}, 2187 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8" 2188 {ISD::UMIN, MVT::v2i64, 8}, // The data reported by the IACA is "8.6" 2189 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5" 2190 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8" 2191 {ISD::SMIN, MVT::v8i16, 2}, 2192 {ISD::UMIN, MVT::v8i16, 2}, 2193 }; 2194 2195 static const CostTblEntry AVX1CostTblPairWise[] = { 2196 {ISD::FMINNUM, MVT::v4f32, 1}, 2197 {ISD::FMINNUM, MVT::v4f64, 1}, 2198 {ISD::FMINNUM, MVT::v8f32, 2}, 2199 {ISD::SMIN, MVT::v2i64, 3}, 2200 {ISD::UMIN, MVT::v2i64, 3}, 2201 {ISD::SMIN, MVT::v4i32, 1}, 2202 {ISD::UMIN, MVT::v4i32, 1}, 2203 {ISD::SMIN, MVT::v8i16, 1}, 2204 {ISD::UMIN, MVT::v8i16, 1}, 2205 {ISD::SMIN, MVT::v8i32, 3}, 2206 {ISD::UMIN, MVT::v8i32, 3}, 2207 }; 2208 2209 static const CostTblEntry AVX2CostTblPairWise[] = { 2210 {ISD::SMIN, MVT::v4i64, 2}, 2211 {ISD::UMIN, MVT::v4i64, 2}, 2212 {ISD::SMIN, MVT::v8i32, 1}, 2213 {ISD::UMIN, MVT::v8i32, 1}, 2214 {ISD::SMIN, MVT::v16i16, 1}, 2215 {ISD::UMIN, MVT::v16i16, 1}, 2216 {ISD::SMIN, MVT::v32i8, 2}, 2217 {ISD::UMIN, MVT::v32i8, 2}, 2218 }; 2219 2220 static const CostTblEntry AVX512CostTblPairWise[] = { 2221 {ISD::FMINNUM, MVT::v8f64, 1}, 2222 {ISD::FMINNUM, MVT::v16f32, 2}, 2223 {ISD::SMIN, MVT::v8i64, 2}, 2224 {ISD::UMIN, MVT::v8i64, 2}, 2225 {ISD::SMIN, MVT::v16i32, 1}, 2226 {ISD::UMIN, MVT::v16i32, 1}, 2227 }; 2228 2229 static const CostTblEntry SSE42CostTblNoPairWise[] = { 2230 {ISD::FMINNUM, MVT::v2f64, 3}, 2231 {ISD::FMINNUM, MVT::v4f32, 3}, 2232 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8" 2233 {ISD::UMIN, MVT::v2i64, 9}, // The data reported by the IACA is "8.6" 2234 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5" 2235 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8" 2236 {ISD::SMIN, MVT::v8i16, 1}, // The data reported by the IACA is "1.5" 2237 {ISD::UMIN, MVT::v8i16, 2}, // The data reported by the IACA is "1.8" 2238 }; 2239 2240 static const CostTblEntry AVX1CostTblNoPairWise[] = { 2241 {ISD::FMINNUM, MVT::v4f32, 1}, 2242 {ISD::FMINNUM, MVT::v4f64, 1}, 2243 {ISD::FMINNUM, MVT::v8f32, 1}, 2244 {ISD::SMIN, MVT::v2i64, 3}, 2245 {ISD::UMIN, MVT::v2i64, 3}, 2246 {ISD::SMIN, MVT::v4i32, 1}, 2247 {ISD::UMIN, MVT::v4i32, 1}, 2248 {ISD::SMIN, MVT::v8i16, 1}, 2249 {ISD::UMIN, MVT::v8i16, 1}, 2250 {ISD::SMIN, MVT::v8i32, 2}, 2251 {ISD::UMIN, MVT::v8i32, 2}, 2252 }; 2253 2254 static const CostTblEntry AVX2CostTblNoPairWise[] = { 2255 {ISD::SMIN, MVT::v4i64, 1}, 2256 {ISD::UMIN, MVT::v4i64, 1}, 2257 {ISD::SMIN, MVT::v8i32, 1}, 2258 {ISD::UMIN, MVT::v8i32, 1}, 2259 {ISD::SMIN, MVT::v16i16, 1}, 2260 {ISD::UMIN, MVT::v16i16, 1}, 2261 {ISD::SMIN, MVT::v32i8, 1}, 2262 {ISD::UMIN, MVT::v32i8, 1}, 2263 }; 2264 2265 static const CostTblEntry AVX512CostTblNoPairWise[] = { 2266 {ISD::FMINNUM, MVT::v8f64, 1}, 2267 {ISD::FMINNUM, MVT::v16f32, 2}, 2268 {ISD::SMIN, MVT::v8i64, 1}, 2269 {ISD::UMIN, MVT::v8i64, 1}, 2270 {ISD::SMIN, MVT::v16i32, 1}, 2271 {ISD::UMIN, MVT::v16i32, 1}, 2272 }; 2273 2274 if (IsPairwise) { 2275 if (ST->hasAVX512()) 2276 if (const auto *Entry = CostTableLookup(AVX512CostTblPairWise, ISD, MTy)) 2277 return LT.first * Entry->Cost; 2278 2279 if (ST->hasAVX2()) 2280 if (const auto *Entry = CostTableLookup(AVX2CostTblPairWise, ISD, MTy)) 2281 return LT.first * Entry->Cost; 2282 2283 if (ST->hasAVX()) 2284 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy)) 2285 return LT.first * Entry->Cost; 2286 2287 if (ST->hasSSE42()) 2288 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy)) 2289 return LT.first * Entry->Cost; 2290 } else { 2291 if (ST->hasAVX512()) 2292 if (const auto *Entry = 2293 CostTableLookup(AVX512CostTblNoPairWise, ISD, MTy)) 2294 return LT.first * Entry->Cost; 2295 2296 if (ST->hasAVX2()) 2297 if (const auto *Entry = CostTableLookup(AVX2CostTblNoPairWise, ISD, MTy)) 2298 return LT.first * Entry->Cost; 2299 2300 if (ST->hasAVX()) 2301 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 2302 return LT.first * Entry->Cost; 2303 2304 if (ST->hasSSE42()) 2305 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy)) 2306 return LT.first * Entry->Cost; 2307 } 2308 2309 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned); 2310 } 2311 2312 /// Calculate the cost of materializing a 64-bit value. This helper 2313 /// method might only calculate a fraction of a larger immediate. Therefore it 2314 /// is valid to return a cost of ZERO. 2315 int X86TTIImpl::getIntImmCost(int64_t Val) { 2316 if (Val == 0) 2317 return TTI::TCC_Free; 2318 2319 if (isInt<32>(Val)) 2320 return TTI::TCC_Basic; 2321 2322 return 2 * TTI::TCC_Basic; 2323 } 2324 2325 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { 2326 assert(Ty->isIntegerTy()); 2327 2328 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 2329 if (BitSize == 0) 2330 return ~0U; 2331 2332 // Never hoist constants larger than 128bit, because this might lead to 2333 // incorrect code generation or assertions in codegen. 2334 // Fixme: Create a cost model for types larger than i128 once the codegen 2335 // issues have been fixed. 2336 if (BitSize > 128) 2337 return TTI::TCC_Free; 2338 2339 if (Imm == 0) 2340 return TTI::TCC_Free; 2341 2342 // Sign-extend all constants to a multiple of 64-bit. 2343 APInt ImmVal = Imm; 2344 if (BitSize % 64 != 0) 2345 ImmVal = Imm.sext(alignTo(BitSize, 64)); 2346 2347 // Split the constant into 64-bit chunks and calculate the cost for each 2348 // chunk. 2349 int Cost = 0; 2350 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 2351 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 2352 int64_t Val = Tmp.getSExtValue(); 2353 Cost += getIntImmCost(Val); 2354 } 2355 // We need at least one instruction to materialize the constant. 2356 return std::max(1, Cost); 2357 } 2358 2359 int X86TTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, 2360 Type *Ty) { 2361 assert(Ty->isIntegerTy()); 2362 2363 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 2364 // There is no cost model for constants with a bit size of 0. Return TCC_Free 2365 // here, so that constant hoisting will ignore this constant. 2366 if (BitSize == 0) 2367 return TTI::TCC_Free; 2368 2369 unsigned ImmIdx = ~0U; 2370 switch (Opcode) { 2371 default: 2372 return TTI::TCC_Free; 2373 case Instruction::GetElementPtr: 2374 // Always hoist the base address of a GetElementPtr. This prevents the 2375 // creation of new constants for every base constant that gets constant 2376 // folded with the offset. 2377 if (Idx == 0) 2378 return 2 * TTI::TCC_Basic; 2379 return TTI::TCC_Free; 2380 case Instruction::Store: 2381 ImmIdx = 0; 2382 break; 2383 case Instruction::ICmp: 2384 // This is an imperfect hack to prevent constant hoisting of 2385 // compares that might be trying to check if a 64-bit value fits in 2386 // 32-bits. The backend can optimize these cases using a right shift by 32. 2387 // Ideally we would check the compare predicate here. There also other 2388 // similar immediates the backend can use shifts for. 2389 if (Idx == 1 && Imm.getBitWidth() == 64) { 2390 uint64_t ImmVal = Imm.getZExtValue(); 2391 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 2392 return TTI::TCC_Free; 2393 } 2394 ImmIdx = 1; 2395 break; 2396 case Instruction::And: 2397 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 2398 // by using a 32-bit operation with implicit zero extension. Detect such 2399 // immediates here as the normal path expects bit 31 to be sign extended. 2400 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 2401 return TTI::TCC_Free; 2402 ImmIdx = 1; 2403 break; 2404 case Instruction::Add: 2405 case Instruction::Sub: 2406 // For add/sub, we can use the opposite instruction for INT32_MIN. 2407 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 2408 return TTI::TCC_Free; 2409 ImmIdx = 1; 2410 break; 2411 case Instruction::UDiv: 2412 case Instruction::SDiv: 2413 case Instruction::URem: 2414 case Instruction::SRem: 2415 // Division by constant is typically expanded later into a different 2416 // instruction sequence. This completely changes the constants. 2417 // Report them as "free" to stop ConstantHoist from marking them as opaque. 2418 return TTI::TCC_Free; 2419 case Instruction::Mul: 2420 case Instruction::Or: 2421 case Instruction::Xor: 2422 ImmIdx = 1; 2423 break; 2424 // Always return TCC_Free for the shift value of a shift instruction. 2425 case Instruction::Shl: 2426 case Instruction::LShr: 2427 case Instruction::AShr: 2428 if (Idx == 1) 2429 return TTI::TCC_Free; 2430 break; 2431 case Instruction::Trunc: 2432 case Instruction::ZExt: 2433 case Instruction::SExt: 2434 case Instruction::IntToPtr: 2435 case Instruction::PtrToInt: 2436 case Instruction::BitCast: 2437 case Instruction::PHI: 2438 case Instruction::Call: 2439 case Instruction::Select: 2440 case Instruction::Ret: 2441 case Instruction::Load: 2442 break; 2443 } 2444 2445 if (Idx == ImmIdx) { 2446 int NumConstants = divideCeil(BitSize, 64); 2447 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty); 2448 return (Cost <= NumConstants * TTI::TCC_Basic) 2449 ? static_cast<int>(TTI::TCC_Free) 2450 : Cost; 2451 } 2452 2453 return X86TTIImpl::getIntImmCost(Imm, Ty); 2454 } 2455 2456 int X86TTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, 2457 Type *Ty) { 2458 assert(Ty->isIntegerTy()); 2459 2460 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 2461 // There is no cost model for constants with a bit size of 0. Return TCC_Free 2462 // here, so that constant hoisting will ignore this constant. 2463 if (BitSize == 0) 2464 return TTI::TCC_Free; 2465 2466 switch (IID) { 2467 default: 2468 return TTI::TCC_Free; 2469 case Intrinsic::sadd_with_overflow: 2470 case Intrinsic::uadd_with_overflow: 2471 case Intrinsic::ssub_with_overflow: 2472 case Intrinsic::usub_with_overflow: 2473 case Intrinsic::smul_with_overflow: 2474 case Intrinsic::umul_with_overflow: 2475 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 2476 return TTI::TCC_Free; 2477 break; 2478 case Intrinsic::experimental_stackmap: 2479 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 2480 return TTI::TCC_Free; 2481 break; 2482 case Intrinsic::experimental_patchpoint_void: 2483 case Intrinsic::experimental_patchpoint_i64: 2484 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 2485 return TTI::TCC_Free; 2486 break; 2487 } 2488 return X86TTIImpl::getIntImmCost(Imm, Ty); 2489 } 2490 2491 unsigned X86TTIImpl::getUserCost(const User *U, 2492 ArrayRef<const Value *> Operands) { 2493 if (isa<StoreInst>(U)) { 2494 Value *Ptr = U->getOperand(1); 2495 // Store instruction with index and scale costs 2 Uops. 2496 // Check the preceding GEP to identify non-const indices. 2497 if (auto GEP = dyn_cast<GetElementPtrInst>(Ptr)) { 2498 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 2499 return TTI::TCC_Basic * 2; 2500 } 2501 return TTI::TCC_Basic; 2502 } 2503 return BaseT::getUserCost(U, Operands); 2504 } 2505 2506 // Return an average cost of Gather / Scatter instruction, maybe improved later 2507 int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, Value *Ptr, 2508 unsigned Alignment, unsigned AddressSpace) { 2509 2510 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 2511 unsigned VF = SrcVTy->getVectorNumElements(); 2512 2513 // Try to reduce index size from 64 bit (default for GEP) 2514 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 2515 // operation will use 16 x 64 indices which do not fit in a zmm and needs 2516 // to split. Also check that the base pointer is the same for all lanes, 2517 // and that there's at most one variable index. 2518 auto getIndexSizeInBits = [](Value *Ptr, const DataLayout& DL) { 2519 unsigned IndexSize = DL.getPointerSizeInBits(); 2520 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 2521 if (IndexSize < 64 || !GEP) 2522 return IndexSize; 2523 2524 unsigned NumOfVarIndices = 0; 2525 Value *Ptrs = GEP->getPointerOperand(); 2526 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 2527 return IndexSize; 2528 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 2529 if (isa<Constant>(GEP->getOperand(i))) 2530 continue; 2531 Type *IndxTy = GEP->getOperand(i)->getType(); 2532 if (IndxTy->isVectorTy()) 2533 IndxTy = IndxTy->getVectorElementType(); 2534 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 2535 !isa<SExtInst>(GEP->getOperand(i))) || 2536 ++NumOfVarIndices > 1) 2537 return IndexSize; // 64 2538 } 2539 return (unsigned)32; 2540 }; 2541 2542 2543 // Trying to reduce IndexSize to 32 bits for vector 16. 2544 // By default the IndexSize is equal to pointer size. 2545 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 2546 ? getIndexSizeInBits(Ptr, DL) 2547 : DL.getPointerSizeInBits(); 2548 2549 Type *IndexVTy = VectorType::get(IntegerType::get(SrcVTy->getContext(), 2550 IndexSize), VF); 2551 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy); 2552 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy); 2553 int SplitFactor = std::max(IdxsLT.first, SrcLT.first); 2554 if (SplitFactor > 1) { 2555 // Handle splitting of vector of pointers 2556 Type *SplitSrcTy = VectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 2557 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 2558 AddressSpace); 2559 } 2560 2561 // The gather / scatter cost is given by Intel architects. It is a rough 2562 // number since we are looking at one instruction in a time. 2563 const int GSOverhead = (Opcode == Instruction::Load) 2564 ? ST->getGatherOverhead() 2565 : ST->getScatterOverhead(); 2566 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2567 Alignment, AddressSpace); 2568 } 2569 2570 /// Return the cost of full scalarization of gather / scatter operation. 2571 /// 2572 /// Opcode - Load or Store instruction. 2573 /// SrcVTy - The type of the data vector that should be gathered or scattered. 2574 /// VariableMask - The mask is non-constant at compile time. 2575 /// Alignment - Alignment for one element. 2576 /// AddressSpace - pointer[s] address space. 2577 /// 2578 int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 2579 bool VariableMask, unsigned Alignment, 2580 unsigned AddressSpace) { 2581 unsigned VF = SrcVTy->getVectorNumElements(); 2582 2583 int MaskUnpackCost = 0; 2584 if (VariableMask) { 2585 VectorType *MaskTy = 2586 VectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 2587 MaskUnpackCost = getScalarizationOverhead(MaskTy, false, true); 2588 int ScalarCompareCost = 2589 getCmpSelInstrCost(Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), 2590 nullptr); 2591 int BranchCost = getCFInstrCost(Instruction::Br); 2592 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 2593 } 2594 2595 // The cost of the scalar loads/stores. 2596 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2597 Alignment, AddressSpace); 2598 2599 int InsertExtractCost = 0; 2600 if (Opcode == Instruction::Load) 2601 for (unsigned i = 0; i < VF; ++i) 2602 // Add the cost of inserting each scalar load into the vector 2603 InsertExtractCost += 2604 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 2605 else 2606 for (unsigned i = 0; i < VF; ++i) 2607 // Add the cost of extracting each element out of the data vector 2608 InsertExtractCost += 2609 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 2610 2611 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 2612 } 2613 2614 /// Calculate the cost of Gather / Scatter operation 2615 int X86TTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *SrcVTy, 2616 Value *Ptr, bool VariableMask, 2617 unsigned Alignment) { 2618 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 2619 unsigned VF = SrcVTy->getVectorNumElements(); 2620 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 2621 if (!PtrTy && Ptr->getType()->isVectorTy()) 2622 PtrTy = dyn_cast<PointerType>(Ptr->getType()->getVectorElementType()); 2623 assert(PtrTy && "Unexpected type for Ptr argument"); 2624 unsigned AddressSpace = PtrTy->getAddressSpace(); 2625 2626 bool Scalarize = false; 2627 if ((Opcode == Instruction::Load && !isLegalMaskedGather(SrcVTy)) || 2628 (Opcode == Instruction::Store && !isLegalMaskedScatter(SrcVTy))) 2629 Scalarize = true; 2630 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 2631 // Vector-4 of gather/scatter instruction does not exist on KNL. 2632 // We can extend it to 8 elements, but zeroing upper bits of 2633 // the mask vector will add more instructions. Right now we give the scalar 2634 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 2635 // is better in the VariableMask case. 2636 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 2637 Scalarize = true; 2638 2639 if (Scalarize) 2640 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 2641 AddressSpace); 2642 2643 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 2644 } 2645 2646 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 2647 TargetTransformInfo::LSRCost &C2) { 2648 // X86 specific here are "instruction number 1st priority". 2649 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 2650 C1.NumIVMuls, C1.NumBaseAdds, 2651 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 2652 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 2653 C2.NumIVMuls, C2.NumBaseAdds, 2654 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 2655 } 2656 2657 bool X86TTIImpl::canMacroFuseCmp() { 2658 return ST->hasMacroFusion(); 2659 } 2660 2661 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy) { 2662 // The backend can't handle a single element vector. 2663 if (isa<VectorType>(DataTy) && DataTy->getVectorNumElements() == 1) 2664 return false; 2665 Type *ScalarTy = DataTy->getScalarType(); 2666 int DataWidth = isa<PointerType>(ScalarTy) ? 2667 DL.getPointerSizeInBits() : ScalarTy->getPrimitiveSizeInBits(); 2668 2669 return ((DataWidth == 32 || DataWidth == 64) && ST->hasAVX()) || 2670 ((DataWidth == 8 || DataWidth == 16) && ST->hasBWI()); 2671 } 2672 2673 bool X86TTIImpl::isLegalMaskedStore(Type *DataType) { 2674 return isLegalMaskedLoad(DataType); 2675 } 2676 2677 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy) { 2678 // This function is called now in two cases: from the Loop Vectorizer 2679 // and from the Scalarizer. 2680 // When the Loop Vectorizer asks about legality of the feature, 2681 // the vectorization factor is not calculated yet. The Loop Vectorizer 2682 // sends a scalar type and the decision is based on the width of the 2683 // scalar element. 2684 // Later on, the cost model will estimate usage this intrinsic based on 2685 // the vector type. 2686 // The Scalarizer asks again about legality. It sends a vector type. 2687 // In this case we can reject non-power-of-2 vectors. 2688 // We also reject single element vectors as the type legalizer can't 2689 // scalarize it. 2690 if (isa<VectorType>(DataTy)) { 2691 unsigned NumElts = DataTy->getVectorNumElements(); 2692 if (NumElts == 1 || !isPowerOf2_32(NumElts)) 2693 return false; 2694 } 2695 Type *ScalarTy = DataTy->getScalarType(); 2696 int DataWidth = isa<PointerType>(ScalarTy) ? 2697 DL.getPointerSizeInBits() : ScalarTy->getPrimitiveSizeInBits(); 2698 2699 // Some CPUs have better gather performance than others. 2700 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 2701 // enable gather with a -march. 2702 return (DataWidth == 32 || DataWidth == 64) && 2703 (ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2())); 2704 } 2705 2706 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType) { 2707 // AVX2 doesn't support scatter 2708 if (!ST->hasAVX512()) 2709 return false; 2710 return isLegalMaskedGather(DataType); 2711 } 2712 2713 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 2714 EVT VT = TLI->getValueType(DL, DataType); 2715 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 2716 } 2717 2718 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 2719 return false; 2720 } 2721 2722 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 2723 const Function *Callee) const { 2724 const TargetMachine &TM = getTLI()->getTargetMachine(); 2725 2726 // Work this as a subsetting of subtarget features. 2727 const FeatureBitset &CallerBits = 2728 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 2729 const FeatureBitset &CalleeBits = 2730 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 2731 2732 // FIXME: This is likely too limiting as it will include subtarget features 2733 // that we might not care about for inlining, but it is conservatively 2734 // correct. 2735 return (CallerBits & CalleeBits) == CalleeBits; 2736 } 2737 2738 const X86TTIImpl::TTI::MemCmpExpansionOptions * 2739 X86TTIImpl::enableMemCmpExpansion(bool IsZeroCmp) const { 2740 // Only enable vector loads for equality comparison. 2741 // Right now the vector version is not as fast, see #33329. 2742 static const auto ThreeWayOptions = [this]() { 2743 TTI::MemCmpExpansionOptions Options; 2744 if (ST->is64Bit()) { 2745 Options.LoadSizes.push_back(8); 2746 } 2747 Options.LoadSizes.push_back(4); 2748 Options.LoadSizes.push_back(2); 2749 Options.LoadSizes.push_back(1); 2750 return Options; 2751 }(); 2752 static const auto EqZeroOptions = [this]() { 2753 TTI::MemCmpExpansionOptions Options; 2754 // TODO: enable AVX512 when the DAG is ready. 2755 // if (ST->hasAVX512()) Options.LoadSizes.push_back(64); 2756 if (ST->hasAVX2()) Options.LoadSizes.push_back(32); 2757 if (ST->hasSSE2()) Options.LoadSizes.push_back(16); 2758 if (ST->is64Bit()) { 2759 Options.LoadSizes.push_back(8); 2760 } 2761 Options.LoadSizes.push_back(4); 2762 Options.LoadSizes.push_back(2); 2763 Options.LoadSizes.push_back(1); 2764 return Options; 2765 }(); 2766 return IsZeroCmp ? &EqZeroOptions : &ThreeWayOptions; 2767 } 2768 2769 bool X86TTIImpl::enableInterleavedAccessVectorization() { 2770 // TODO: We expect this to be beneficial regardless of arch, 2771 // but there are currently some unexplained performance artifacts on Atom. 2772 // As a temporary solution, disable on Atom. 2773 return !(ST->isAtom()); 2774 } 2775 2776 // Get estimation for interleaved load/store operations for AVX2. 2777 // \p Factor is the interleaved-access factor (stride) - number of 2778 // (interleaved) elements in the group. 2779 // \p Indices contains the indices for a strided load: when the 2780 // interleaved load has gaps they indicate which elements are used. 2781 // If Indices is empty (or if the number of indices is equal to the size 2782 // of the interleaved-access as given in \p Factor) the access has no gaps. 2783 // 2784 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 2785 // computing the cost using a generic formula as a function of generic 2786 // shuffles. We therefore use a lookup table instead, filled according to 2787 // the instruction sequences that codegen currently generates. 2788 int X86TTIImpl::getInterleavedMemoryOpCostAVX2(unsigned Opcode, Type *VecTy, 2789 unsigned Factor, 2790 ArrayRef<unsigned> Indices, 2791 unsigned Alignment, 2792 unsigned AddressSpace, 2793 bool UseMaskForCond, 2794 bool UseMaskForGaps) { 2795 2796 if (UseMaskForCond || UseMaskForGaps) 2797 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 2798 Alignment, AddressSpace, 2799 UseMaskForCond, UseMaskForGaps); 2800 2801 // We currently Support only fully-interleaved groups, with no gaps. 2802 // TODO: Support also strided loads (interleaved-groups with gaps). 2803 if (Indices.size() && Indices.size() != Factor) 2804 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 2805 Alignment, AddressSpace); 2806 2807 // VecTy for interleave memop is <VF*Factor x Elt>. 2808 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 2809 // VecTy = <12 x i32>. 2810 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 2811 2812 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 2813 // the VF=2, while v2i128 is an unsupported MVT vector type 2814 // (see MachineValueType.h::getVectorVT()). 2815 if (!LegalVT.isVector()) 2816 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 2817 Alignment, AddressSpace); 2818 2819 unsigned VF = VecTy->getVectorNumElements() / Factor; 2820 Type *ScalarTy = VecTy->getVectorElementType(); 2821 2822 // Calculate the number of memory operations (NumOfMemOps), required 2823 // for load/store the VecTy. 2824 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 2825 unsigned LegalVTSize = LegalVT.getStoreSize(); 2826 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 2827 2828 // Get the cost of one memory operation. 2829 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(), 2830 LegalVT.getVectorNumElements()); 2831 unsigned MemOpCost = 2832 getMemoryOpCost(Opcode, SingleMemOpTy, Alignment, AddressSpace); 2833 2834 VectorType *VT = VectorType::get(ScalarTy, VF); 2835 EVT ETy = TLI->getValueType(DL, VT); 2836 if (!ETy.isSimple()) 2837 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 2838 Alignment, AddressSpace); 2839 2840 // TODO: Complete for other data-types and strides. 2841 // Each combination of Stride, ElementTy and VF results in a different 2842 // sequence; The cost tables are therefore accessed with: 2843 // Factor (stride) and VectorType=VFxElemType. 2844 // The Cost accounts only for the shuffle sequence; 2845 // The cost of the loads/stores is accounted for separately. 2846 // 2847 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 2848 { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64 2849 { 2, MVT::v4f64, 6 }, //(load 8f64 and) deinterleave into 2 x 4f64 2850 2851 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8 2852 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8 2853 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8 2854 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8 2855 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8 2856 { 3, MVT::v8f32, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32 2857 2858 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8 2859 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8 2860 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8 2861 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8 2862 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8 2863 2864 { 8, MVT::v8f32, 40 } //(load 64f32 and)deinterleave into 8 x 8f32 2865 }; 2866 2867 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 2868 { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store) 2869 { 2, MVT::v4f64, 6 }, //interleave into 2 x 4f64 into 8f64 (and store) 2870 2871 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store) 2872 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store) 2873 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store) 2874 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store) 2875 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store) 2876 2877 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store) 2878 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store) 2879 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store) 2880 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store) 2881 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store) 2882 }; 2883 2884 if (Opcode == Instruction::Load) { 2885 if (const auto *Entry = 2886 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 2887 return NumOfMemOps * MemOpCost + Entry->Cost; 2888 } else { 2889 assert(Opcode == Instruction::Store && 2890 "Expected Store Instruction at this point"); 2891 if (const auto *Entry = 2892 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 2893 return NumOfMemOps * MemOpCost + Entry->Cost; 2894 } 2895 2896 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 2897 Alignment, AddressSpace); 2898 } 2899 2900 // Get estimation for interleaved load/store operations and strided load. 2901 // \p Indices contains indices for strided load. 2902 // \p Factor - the factor of interleaving. 2903 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 2904 int X86TTIImpl::getInterleavedMemoryOpCostAVX512(unsigned Opcode, Type *VecTy, 2905 unsigned Factor, 2906 ArrayRef<unsigned> Indices, 2907 unsigned Alignment, 2908 unsigned AddressSpace, 2909 bool UseMaskForCond, 2910 bool UseMaskForGaps) { 2911 2912 if (UseMaskForCond || UseMaskForGaps) 2913 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 2914 Alignment, AddressSpace, 2915 UseMaskForCond, UseMaskForGaps); 2916 2917 // VecTy for interleave memop is <VF*Factor x Elt>. 2918 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 2919 // VecTy = <12 x i32>. 2920 2921 // Calculate the number of memory operations (NumOfMemOps), required 2922 // for load/store the VecTy. 2923 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 2924 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 2925 unsigned LegalVTSize = LegalVT.getStoreSize(); 2926 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 2927 2928 // Get the cost of one memory operation. 2929 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(), 2930 LegalVT.getVectorNumElements()); 2931 unsigned MemOpCost = 2932 getMemoryOpCost(Opcode, SingleMemOpTy, Alignment, AddressSpace); 2933 2934 unsigned VF = VecTy->getVectorNumElements() / Factor; 2935 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 2936 2937 if (Opcode == Instruction::Load) { 2938 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 2939 // contain the cost of the optimized shuffle sequence that the 2940 // X86InterleavedAccess pass will generate. 2941 // The cost of loads and stores are computed separately from the table. 2942 2943 // X86InterleavedAccess support only the following interleaved-access group. 2944 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 2945 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 2946 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 2947 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 2948 }; 2949 2950 if (const auto *Entry = 2951 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 2952 return NumOfMemOps * MemOpCost + Entry->Cost; 2953 //If an entry does not exist, fallback to the default implementation. 2954 2955 // Kind of shuffle depends on number of loaded values. 2956 // If we load the entire data in one register, we can use a 1-src shuffle. 2957 // Otherwise, we'll merge 2 sources in each operation. 2958 TTI::ShuffleKind ShuffleKind = 2959 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 2960 2961 unsigned ShuffleCost = 2962 getShuffleCost(ShuffleKind, SingleMemOpTy, 0, nullptr); 2963 2964 unsigned NumOfLoadsInInterleaveGrp = 2965 Indices.size() ? Indices.size() : Factor; 2966 Type *ResultTy = VectorType::get(VecTy->getVectorElementType(), 2967 VecTy->getVectorNumElements() / Factor); 2968 unsigned NumOfResults = 2969 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 2970 NumOfLoadsInInterleaveGrp; 2971 2972 // About a half of the loads may be folded in shuffles when we have only 2973 // one result. If we have more than one result, we do not fold loads at all. 2974 unsigned NumOfUnfoldedLoads = 2975 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 2976 2977 // Get a number of shuffle operations per result. 2978 unsigned NumOfShufflesPerResult = 2979 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 2980 2981 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 2982 // When we have more than one destination, we need additional instructions 2983 // to keep sources. 2984 unsigned NumOfMoves = 0; 2985 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 2986 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 2987 2988 int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 2989 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 2990 2991 return Cost; 2992 } 2993 2994 // Store. 2995 assert(Opcode == Instruction::Store && 2996 "Expected Store Instruction at this point"); 2997 // X86InterleavedAccess support only the following interleaved-access group. 2998 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 2999 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 3000 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 3001 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 3002 3003 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 3004 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 3005 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 3006 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 3007 }; 3008 3009 if (const auto *Entry = 3010 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 3011 return NumOfMemOps * MemOpCost + Entry->Cost; 3012 //If an entry does not exist, fallback to the default implementation. 3013 3014 // There is no strided stores meanwhile. And store can't be folded in 3015 // shuffle. 3016 unsigned NumOfSources = Factor; // The number of values to be merged. 3017 unsigned ShuffleCost = 3018 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, 0, nullptr); 3019 unsigned NumOfShufflesPerStore = NumOfSources - 1; 3020 3021 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 3022 // We need additional instructions to keep sources. 3023 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 3024 int Cost = NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 3025 NumOfMoves; 3026 return Cost; 3027 } 3028 3029 int X86TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, 3030 unsigned Factor, 3031 ArrayRef<unsigned> Indices, 3032 unsigned Alignment, 3033 unsigned AddressSpace, 3034 bool UseMaskForCond, 3035 bool UseMaskForGaps) { 3036 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 3037 Type *EltTy = VecTy->getVectorElementType(); 3038 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 3039 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 3040 return true; 3041 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 3042 return HasBW; 3043 return false; 3044 }; 3045 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 3046 return getInterleavedMemoryOpCostAVX512(Opcode, VecTy, Factor, Indices, 3047 Alignment, AddressSpace, 3048 UseMaskForCond, UseMaskForGaps); 3049 if (ST->hasAVX2()) 3050 return getInterleavedMemoryOpCostAVX2(Opcode, VecTy, Factor, Indices, 3051 Alignment, AddressSpace, 3052 UseMaskForCond, UseMaskForGaps); 3053 3054 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3055 Alignment, AddressSpace, 3056 UseMaskForCond, UseMaskForGaps); 3057 } 3058