1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // X86 cost model. 56 // 57 //===----------------------------------------------------------------------===// 58 59 TargetTransformInfo::PopcntSupportKind 60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 61 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 62 // TODO: Currently the __builtin_popcount() implementation using SSE3 63 // instructions is inefficient. Once the problem is fixed, we should 64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 66 } 67 68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 69 TargetTransformInfo::CacheLevel Level) const { 70 switch (Level) { 71 case TargetTransformInfo::CacheLevel::L1D: 72 // - Penryn 73 // - Nehalem 74 // - Westmere 75 // - Sandy Bridge 76 // - Ivy Bridge 77 // - Haswell 78 // - Broadwell 79 // - Skylake 80 // - Kabylake 81 return 32 * 1024; // 32 KByte 82 case TargetTransformInfo::CacheLevel::L2D: 83 // - Penryn 84 // - Nehalem 85 // - Westmere 86 // - Sandy Bridge 87 // - Ivy Bridge 88 // - Haswell 89 // - Broadwell 90 // - Skylake 91 // - Kabylake 92 return 256 * 1024; // 256 KByte 93 } 94 95 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 96 } 97 98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 99 TargetTransformInfo::CacheLevel Level) const { 100 // - Penryn 101 // - Nehalem 102 // - Westmere 103 // - Sandy Bridge 104 // - Ivy Bridge 105 // - Haswell 106 // - Broadwell 107 // - Skylake 108 // - Kabylake 109 switch (Level) { 110 case TargetTransformInfo::CacheLevel::L1D: 111 LLVM_FALLTHROUGH; 112 case TargetTransformInfo::CacheLevel::L2D: 113 return 8; 114 } 115 116 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 117 } 118 119 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 120 bool Vector = (ClassID == 1); 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const { 133 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 134 if (Vector) { 135 if (ST->hasAVX512() && PreferVectorWidth >= 512) 136 return 512; 137 if (ST->hasAVX() && PreferVectorWidth >= 256) 138 return 256; 139 if (ST->hasSSE1() && PreferVectorWidth >= 128) 140 return 128; 141 return 0; 142 } 143 144 if (ST->is64Bit()) 145 return 64; 146 147 return 32; 148 } 149 150 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 151 return getRegisterBitWidth(true); 152 } 153 154 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 155 // If the loop will not be vectorized, don't interleave the loop. 156 // Let regular unroll to unroll the loop, which saves the overflow 157 // check and memory check cost. 158 if (VF == 1) 159 return 1; 160 161 if (ST->isAtom()) 162 return 1; 163 164 // Sandybridge and Haswell have multiple execution ports and pipelined 165 // vector units. 166 if (ST->hasAVX()) 167 return 4; 168 169 return 2; 170 } 171 172 int X86TTIImpl::getArithmeticInstrCost(unsigned Opcode, Type *Ty, 173 TTI::TargetCostKind CostKind, 174 TTI::OperandValueKind Op1Info, 175 TTI::OperandValueKind Op2Info, 176 TTI::OperandValueProperties Opd1PropInfo, 177 TTI::OperandValueProperties Opd2PropInfo, 178 ArrayRef<const Value *> Args, 179 const Instruction *CxtI) { 180 // Legalize the type. 181 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 182 183 int ISD = TLI->InstructionOpcodeToISD(Opcode); 184 assert(ISD && "Invalid opcode"); 185 186 static const CostTblEntry GLMCostTable[] = { 187 { ISD::FDIV, MVT::f32, 18 }, // divss 188 { ISD::FDIV, MVT::v4f32, 35 }, // divps 189 { ISD::FDIV, MVT::f64, 33 }, // divsd 190 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 191 }; 192 193 if (ST->useGLMDivSqrtCosts()) 194 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 195 LT.second)) 196 return LT.first * Entry->Cost; 197 198 static const CostTblEntry SLMCostTable[] = { 199 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 200 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 201 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. 202 { ISD::FMUL, MVT::f64, 2 }, // mulsd 203 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 204 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 205 { ISD::FDIV, MVT::f32, 17 }, // divss 206 { ISD::FDIV, MVT::v4f32, 39 }, // divps 207 { ISD::FDIV, MVT::f64, 32 }, // divsd 208 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 209 { ISD::FADD, MVT::v2f64, 2 }, // addpd 210 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 211 // v2i64/v4i64 mul is custom lowered as a series of long: 212 // multiplies(3), shifts(3) and adds(2) 213 // slm muldq version throughput is 2 and addq throughput 4 214 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 215 // 3X4 (addq throughput) = 17 216 { ISD::MUL, MVT::v2i64, 17 }, 217 // slm addq\subq throughput is 4 218 { ISD::ADD, MVT::v2i64, 4 }, 219 { ISD::SUB, MVT::v2i64, 4 }, 220 }; 221 222 if (ST->isSLM()) { 223 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 224 // Check if the operands can be shrinked into a smaller datatype. 225 bool Op1Signed = false; 226 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 227 bool Op2Signed = false; 228 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 229 230 bool signedMode = Op1Signed | Op2Signed; 231 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 232 233 if (OpMinSize <= 7) 234 return LT.first * 3; // pmullw/sext 235 if (!signedMode && OpMinSize <= 8) 236 return LT.first * 3; // pmullw/zext 237 if (OpMinSize <= 15) 238 return LT.first * 5; // pmullw/pmulhw/pshuf 239 if (!signedMode && OpMinSize <= 16) 240 return LT.first * 5; // pmullw/pmulhw/pshuf 241 } 242 243 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 244 LT.second)) { 245 return LT.first * Entry->Cost; 246 } 247 } 248 249 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 250 ISD == ISD::UREM) && 251 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 252 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 253 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 254 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 255 // On X86, vector signed division by constants power-of-two are 256 // normally expanded to the sequence SRA + SRL + ADD + SRA. 257 // The OperandValue properties may not be the same as that of the previous 258 // operation; conservatively assume OP_None. 259 int Cost = 260 2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Op1Info, 261 Op2Info, 262 TargetTransformInfo::OP_None, 263 TargetTransformInfo::OP_None); 264 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 265 Op2Info, 266 TargetTransformInfo::OP_None, 267 TargetTransformInfo::OP_None); 268 Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind, Op1Info, 269 Op2Info, 270 TargetTransformInfo::OP_None, 271 TargetTransformInfo::OP_None); 272 273 if (ISD == ISD::SREM) { 274 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 275 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info, 276 Op2Info); 277 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info, 278 Op2Info); 279 } 280 281 return Cost; 282 } 283 284 // Vector unsigned division/remainder will be simplified to shifts/masks. 285 if (ISD == ISD::UDIV) 286 return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, 287 Op1Info, Op2Info, 288 TargetTransformInfo::OP_None, 289 TargetTransformInfo::OP_None); 290 291 else // UREM 292 return getArithmeticInstrCost(Instruction::And, Ty, CostKind, 293 Op1Info, Op2Info, 294 TargetTransformInfo::OP_None, 295 TargetTransformInfo::OP_None); 296 } 297 298 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 299 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 300 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 301 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 302 }; 303 304 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 305 ST->hasBWI()) { 306 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 307 LT.second)) 308 return LT.first * Entry->Cost; 309 } 310 311 static const CostTblEntry AVX512UniformConstCostTable[] = { 312 { ISD::SRA, MVT::v2i64, 1 }, 313 { ISD::SRA, MVT::v4i64, 1 }, 314 { ISD::SRA, MVT::v8i64, 1 }, 315 316 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 317 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 318 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 319 }; 320 321 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 322 ST->hasAVX512()) { 323 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 324 LT.second)) 325 return LT.first * Entry->Cost; 326 } 327 328 static const CostTblEntry AVX2UniformConstCostTable[] = { 329 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 330 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 331 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 332 333 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 334 }; 335 336 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 337 ST->hasAVX2()) { 338 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 339 LT.second)) 340 return LT.first * Entry->Cost; 341 } 342 343 static const CostTblEntry SSE2UniformConstCostTable[] = { 344 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 345 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 346 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 347 348 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 349 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 350 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 351 }; 352 353 // XOP has faster vXi8 shifts. 354 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 355 ST->hasSSE2() && !ST->hasXOP()) { 356 if (const auto *Entry = 357 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 358 return LT.first * Entry->Cost; 359 } 360 361 static const CostTblEntry AVX512BWConstCostTable[] = { 362 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 363 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 364 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 365 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 366 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 367 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 368 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 369 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 370 }; 371 372 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 373 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 374 ST->hasBWI()) { 375 if (const auto *Entry = 376 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 377 return LT.first * Entry->Cost; 378 } 379 380 static const CostTblEntry AVX512ConstCostTable[] = { 381 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 382 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 383 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 384 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 385 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 386 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 387 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 388 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 389 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 390 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 391 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 392 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 393 }; 394 395 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 396 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 397 ST->hasAVX512()) { 398 if (const auto *Entry = 399 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 400 return LT.first * Entry->Cost; 401 } 402 403 static const CostTblEntry AVX2ConstCostTable[] = { 404 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 405 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 406 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 407 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 408 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 409 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 410 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 411 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 412 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 413 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 414 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 415 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 416 }; 417 418 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 419 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 420 ST->hasAVX2()) { 421 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 422 return LT.first * Entry->Cost; 423 } 424 425 static const CostTblEntry SSE2ConstCostTable[] = { 426 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 427 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 428 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 429 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 430 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 431 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 432 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 433 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 434 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 435 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 436 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 437 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 438 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 439 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 440 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 441 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 442 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 443 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 444 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 445 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 446 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 447 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 448 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 449 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 450 }; 451 452 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 453 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 454 ST->hasSSE2()) { 455 // pmuldq sequence. 456 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 457 return LT.first * 32; 458 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 459 return LT.first * 38; 460 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 461 return LT.first * 15; 462 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 463 return LT.first * 20; 464 465 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 466 return LT.first * Entry->Cost; 467 } 468 469 static const CostTblEntry AVX512BWShiftCostTable[] = { 470 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 471 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 472 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 473 474 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 475 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 476 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 477 478 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 479 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 480 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 481 }; 482 483 if (ST->hasBWI()) 484 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 485 return LT.first * Entry->Cost; 486 487 static const CostTblEntry AVX2UniformCostTable[] = { 488 // Uniform splats are cheaper for the following instructions. 489 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 490 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 491 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 492 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 493 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 494 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 495 }; 496 497 if (ST->hasAVX2() && 498 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 499 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 500 if (const auto *Entry = 501 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 502 return LT.first * Entry->Cost; 503 } 504 505 static const CostTblEntry SSE2UniformCostTable[] = { 506 // Uniform splats are cheaper for the following instructions. 507 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 508 { ISD::SHL, MVT::v4i32, 1 }, // pslld 509 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 510 511 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 512 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 513 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 514 515 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 516 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 517 }; 518 519 if (ST->hasSSE2() && 520 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 521 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 522 if (const auto *Entry = 523 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 524 return LT.first * Entry->Cost; 525 } 526 527 static const CostTblEntry AVX512DQCostTable[] = { 528 { ISD::MUL, MVT::v2i64, 1 }, 529 { ISD::MUL, MVT::v4i64, 1 }, 530 { ISD::MUL, MVT::v8i64, 1 } 531 }; 532 533 // Look for AVX512DQ lowering tricks for custom cases. 534 if (ST->hasDQI()) 535 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 536 return LT.first * Entry->Cost; 537 538 static const CostTblEntry AVX512BWCostTable[] = { 539 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 540 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 541 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 542 543 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence. 544 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence. 545 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence. 546 }; 547 548 // Look for AVX512BW lowering tricks for custom cases. 549 if (ST->hasBWI()) 550 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 551 return LT.first * Entry->Cost; 552 553 static const CostTblEntry AVX512CostTable[] = { 554 { ISD::SHL, MVT::v16i32, 1 }, 555 { ISD::SRL, MVT::v16i32, 1 }, 556 { ISD::SRA, MVT::v16i32, 1 }, 557 558 { ISD::SHL, MVT::v8i64, 1 }, 559 { ISD::SRL, MVT::v8i64, 1 }, 560 561 { ISD::SRA, MVT::v2i64, 1 }, 562 { ISD::SRA, MVT::v4i64, 1 }, 563 { ISD::SRA, MVT::v8i64, 1 }, 564 565 { ISD::MUL, MVT::v64i8, 26 }, // extend/pmullw/trunc sequence. 566 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence. 567 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence. 568 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 569 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 570 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 571 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add 572 573 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 574 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 575 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 576 577 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 578 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 579 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 580 }; 581 582 if (ST->hasAVX512()) 583 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 584 return LT.first * Entry->Cost; 585 586 static const CostTblEntry AVX2ShiftCostTable[] = { 587 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 588 // customize them to detect the cases where shift amount is a scalar one. 589 { ISD::SHL, MVT::v4i32, 1 }, 590 { ISD::SRL, MVT::v4i32, 1 }, 591 { ISD::SRA, MVT::v4i32, 1 }, 592 { ISD::SHL, MVT::v8i32, 1 }, 593 { ISD::SRL, MVT::v8i32, 1 }, 594 { ISD::SRA, MVT::v8i32, 1 }, 595 { ISD::SHL, MVT::v2i64, 1 }, 596 { ISD::SRL, MVT::v2i64, 1 }, 597 { ISD::SHL, MVT::v4i64, 1 }, 598 { ISD::SRL, MVT::v4i64, 1 }, 599 }; 600 601 if (ST->hasAVX512()) { 602 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 603 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 604 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 605 // On AVX512, a packed v32i16 shift left by a constant build_vector 606 // is lowered into a vector multiply (vpmullw). 607 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 608 Op1Info, Op2Info, 609 TargetTransformInfo::OP_None, 610 TargetTransformInfo::OP_None); 611 } 612 613 // Look for AVX2 lowering tricks. 614 if (ST->hasAVX2()) { 615 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 616 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 617 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 618 // On AVX2, a packed v16i16 shift left by a constant build_vector 619 // is lowered into a vector multiply (vpmullw). 620 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 621 Op1Info, Op2Info, 622 TargetTransformInfo::OP_None, 623 TargetTransformInfo::OP_None); 624 625 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 626 return LT.first * Entry->Cost; 627 } 628 629 static const CostTblEntry XOPShiftCostTable[] = { 630 // 128bit shifts take 1cy, but right shifts require negation beforehand. 631 { ISD::SHL, MVT::v16i8, 1 }, 632 { ISD::SRL, MVT::v16i8, 2 }, 633 { ISD::SRA, MVT::v16i8, 2 }, 634 { ISD::SHL, MVT::v8i16, 1 }, 635 { ISD::SRL, MVT::v8i16, 2 }, 636 { ISD::SRA, MVT::v8i16, 2 }, 637 { ISD::SHL, MVT::v4i32, 1 }, 638 { ISD::SRL, MVT::v4i32, 2 }, 639 { ISD::SRA, MVT::v4i32, 2 }, 640 { ISD::SHL, MVT::v2i64, 1 }, 641 { ISD::SRL, MVT::v2i64, 2 }, 642 { ISD::SRA, MVT::v2i64, 2 }, 643 // 256bit shifts require splitting if AVX2 didn't catch them above. 644 { ISD::SHL, MVT::v32i8, 2+2 }, 645 { ISD::SRL, MVT::v32i8, 4+2 }, 646 { ISD::SRA, MVT::v32i8, 4+2 }, 647 { ISD::SHL, MVT::v16i16, 2+2 }, 648 { ISD::SRL, MVT::v16i16, 4+2 }, 649 { ISD::SRA, MVT::v16i16, 4+2 }, 650 { ISD::SHL, MVT::v8i32, 2+2 }, 651 { ISD::SRL, MVT::v8i32, 4+2 }, 652 { ISD::SRA, MVT::v8i32, 4+2 }, 653 { ISD::SHL, MVT::v4i64, 2+2 }, 654 { ISD::SRL, MVT::v4i64, 4+2 }, 655 { ISD::SRA, MVT::v4i64, 4+2 }, 656 }; 657 658 // Look for XOP lowering tricks. 659 if (ST->hasXOP()) { 660 // If the right shift is constant then we'll fold the negation so 661 // it's as cheap as a left shift. 662 int ShiftISD = ISD; 663 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 664 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 665 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 666 ShiftISD = ISD::SHL; 667 if (const auto *Entry = 668 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 669 return LT.first * Entry->Cost; 670 } 671 672 static const CostTblEntry SSE2UniformShiftCostTable[] = { 673 // Uniform splats are cheaper for the following instructions. 674 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 675 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 676 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 677 678 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 679 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 680 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 681 682 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 683 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 684 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 685 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 686 }; 687 688 if (ST->hasSSE2() && 689 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 690 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 691 692 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 693 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 694 return LT.first * 4; // 2*psrad + shuffle. 695 696 if (const auto *Entry = 697 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 698 return LT.first * Entry->Cost; 699 } 700 701 if (ISD == ISD::SHL && 702 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 703 MVT VT = LT.second; 704 // Vector shift left by non uniform constant can be lowered 705 // into vector multiply. 706 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 707 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 708 ISD = ISD::MUL; 709 } 710 711 static const CostTblEntry AVX2CostTable[] = { 712 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. 713 { ISD::SHL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. 714 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 715 { ISD::SHL, MVT::v32i16, 20 }, // 2*extend/vpsrlvd/pack sequence. 716 717 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. 718 { ISD::SRL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. 719 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 720 { ISD::SRL, MVT::v32i16, 20 }, // 2*extend/vpsrlvd/pack sequence. 721 722 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. 723 { ISD::SRA, MVT::v64i8, 48 }, // 2*vpblendvb sequence. 724 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. 725 { ISD::SRA, MVT::v32i16, 20 }, // 2*extend/vpsravd/pack sequence. 726 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. 727 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 728 729 { ISD::SUB, MVT::v32i8, 1 }, // psubb 730 { ISD::ADD, MVT::v32i8, 1 }, // paddb 731 { ISD::SUB, MVT::v16i16, 1 }, // psubw 732 { ISD::ADD, MVT::v16i16, 1 }, // paddw 733 { ISD::SUB, MVT::v8i32, 1 }, // psubd 734 { ISD::ADD, MVT::v8i32, 1 }, // paddd 735 { ISD::SUB, MVT::v4i64, 1 }, // psubq 736 { ISD::ADD, MVT::v4i64, 1 }, // paddq 737 738 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence. 739 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence. 740 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 741 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 742 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add 743 744 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 745 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 746 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 747 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 748 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 749 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 750 751 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 752 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 753 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 754 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 755 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 756 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 757 }; 758 759 // Look for AVX2 lowering tricks for custom cases. 760 if (ST->hasAVX2()) 761 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 762 return LT.first * Entry->Cost; 763 764 static const CostTblEntry AVX1CostTable[] = { 765 // We don't have to scalarize unsupported ops. We can issue two half-sized 766 // operations and we only need to extract the upper YMM half. 767 // Two ops + 1 extract + 1 insert = 4. 768 { ISD::MUL, MVT::v16i16, 4 }, 769 { ISD::MUL, MVT::v8i32, 4 }, 770 { ISD::SUB, MVT::v32i8, 4 }, 771 { ISD::ADD, MVT::v32i8, 4 }, 772 { ISD::SUB, MVT::v16i16, 4 }, 773 { ISD::ADD, MVT::v16i16, 4 }, 774 { ISD::SUB, MVT::v8i32, 4 }, 775 { ISD::ADD, MVT::v8i32, 4 }, 776 { ISD::SUB, MVT::v4i64, 4 }, 777 { ISD::ADD, MVT::v4i64, 4 }, 778 779 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 780 // are lowered as a series of long multiplies(3), shifts(3) and adds(2) 781 // Because we believe v4i64 to be a legal type, we must also include the 782 // extract+insert in the cost table. Therefore, the cost here is 18 783 // instead of 8. 784 { ISD::MUL, MVT::v4i64, 18 }, 785 786 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence. 787 788 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 789 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 790 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 791 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 792 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 793 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 794 }; 795 796 if (ST->hasAVX()) 797 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 798 return LT.first * Entry->Cost; 799 800 static const CostTblEntry SSE42CostTable[] = { 801 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 802 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 803 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 804 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 805 806 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 807 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 808 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 809 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 810 811 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 812 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 813 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 814 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 815 816 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 817 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 818 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 819 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 820 }; 821 822 if (ST->hasSSE42()) 823 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 824 return LT.first * Entry->Cost; 825 826 static const CostTblEntry SSE41CostTable[] = { 827 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 828 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split. 829 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 830 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 831 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 832 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split 833 834 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 835 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split. 836 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 837 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 838 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 839 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split. 840 841 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 842 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split. 843 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 844 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 845 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 846 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split. 847 848 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 849 }; 850 851 if (ST->hasSSE41()) 852 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 853 return LT.first * Entry->Cost; 854 855 static const CostTblEntry SSE2CostTable[] = { 856 // We don't correctly identify costs of casts because they are marked as 857 // custom. 858 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 859 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 860 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 861 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 862 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 863 864 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 865 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 866 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 867 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 868 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 869 870 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 871 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 872 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 873 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 874 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split. 875 876 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence. 877 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 878 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 879 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 880 881 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 882 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 883 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 884 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 885 886 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 887 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 888 889 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 890 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 891 }; 892 893 if (ST->hasSSE2()) 894 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 895 return LT.first * Entry->Cost; 896 897 static const CostTblEntry SSE1CostTable[] = { 898 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 899 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 900 901 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 902 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 903 904 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 905 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 906 907 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 908 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 909 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 910 911 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 912 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 913 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 914 }; 915 916 if (ST->hasSSE1()) 917 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 918 return LT.first * Entry->Cost; 919 920 // It is not a good idea to vectorize division. We have to scalarize it and 921 // in the process we will often end up having to spilling regular 922 // registers. The overhead of division is going to dominate most kernels 923 // anyways so try hard to prevent vectorization of division - it is 924 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 925 // to hide "20 cycles" for each lane. 926 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 927 ISD == ISD::UDIV || ISD == ISD::UREM)) { 928 int ScalarCost = getArithmeticInstrCost( 929 Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info, 930 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 931 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 932 } 933 934 // Fallback to the default implementation. 935 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info); 936 } 937 938 int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, VectorType *BaseTp, 939 int Index, VectorType *SubTp) { 940 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 941 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 942 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 943 944 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 945 if (Kind == TTI::SK_Transpose) 946 Kind = TTI::SK_PermuteTwoSrc; 947 948 // For Broadcasts we are splatting the first element from the first input 949 // register, so only need to reference that input and all the output 950 // registers are the same. 951 if (Kind == TTI::SK_Broadcast) 952 LT.first = 1; 953 954 // Subvector extractions are free if they start at the beginning of a 955 // vector and cheap if the subvectors are aligned. 956 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 957 int NumElts = LT.second.getVectorNumElements(); 958 if ((Index % NumElts) == 0) 959 return 0; 960 std::pair<int, MVT> SubLT = TLI->getTypeLegalizationCost(DL, SubTp); 961 if (SubLT.second.isVector()) { 962 int NumSubElts = SubLT.second.getVectorNumElements(); 963 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 964 return SubLT.first; 965 // Handle some cases for widening legalization. For now we only handle 966 // cases where the original subvector was naturally aligned and evenly 967 // fit in its legalized subvector type. 968 // FIXME: Remove some of the alignment restrictions. 969 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 970 // vectors. 971 int OrigSubElts = cast<VectorType>(SubTp)->getNumElements(); 972 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 973 (NumSubElts % OrigSubElts) == 0 && 974 LT.second.getVectorElementType() == 975 SubLT.second.getVectorElementType() && 976 LT.second.getVectorElementType().getSizeInBits() == 977 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 978 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 979 "Unexpected number of elements!"); 980 VectorType *VecTy = VectorType::get(BaseTp->getElementType(), 981 LT.second.getVectorNumElements()); 982 VectorType *SubTy = 983 VectorType::get(BaseTp->getElementType(), 984 SubLT.second.getVectorNumElements()); 985 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 986 int ExtractCost = getShuffleCost(TTI::SK_ExtractSubvector, VecTy, 987 ExtractIndex, SubTy); 988 989 // If the original size is 32-bits or more, we can use pshufd. Otherwise 990 // if we have SSSE3 we can use pshufb. 991 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 992 return ExtractCost + 1; // pshufd or pshufb 993 994 assert(SubTp->getPrimitiveSizeInBits() == 16 && 995 "Unexpected vector size"); 996 997 return ExtractCost + 2; // worst case pshufhw + pshufd 998 } 999 } 1000 } 1001 1002 // Handle some common (illegal) sub-vector types as they are often very cheap 1003 // to shuffle even on targets without PSHUFB. 1004 EVT VT = TLI->getValueType(DL, BaseTp); 1005 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 1006 !ST->hasSSSE3()) { 1007 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 1008 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 1009 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1010 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1011 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1012 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1013 1014 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1015 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1016 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1017 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1018 1019 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1020 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1021 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1022 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1023 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1024 1025 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1026 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1027 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1028 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1029 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1030 }; 1031 1032 if (ST->hasSSE2()) 1033 if (const auto *Entry = 1034 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1035 return Entry->Cost; 1036 } 1037 1038 // We are going to permute multiple sources and the result will be in multiple 1039 // destinations. Providing an accurate cost only for splits where the element 1040 // type remains the same. 1041 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1042 MVT LegalVT = LT.second; 1043 if (LegalVT.isVector() && 1044 LegalVT.getVectorElementType().getSizeInBits() == 1045 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1046 LegalVT.getVectorNumElements() < BaseTp->getNumElements()) { 1047 1048 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1049 unsigned LegalVTSize = LegalVT.getStoreSize(); 1050 // Number of source vectors after legalization: 1051 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1052 // Number of destination vectors after legalization: 1053 unsigned NumOfDests = LT.first; 1054 1055 VectorType *SingleOpTy = 1056 VectorType::get(BaseTp->getElementType(), 1057 LegalVT.getVectorNumElements()); 1058 1059 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1060 return NumOfShuffles * 1061 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 0, nullptr); 1062 } 1063 1064 return BaseT::getShuffleCost(Kind, BaseTp, Index, SubTp); 1065 } 1066 1067 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1068 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1069 // We assume that source and destination have the same vector type. 1070 int NumOfDests = LT.first; 1071 int NumOfShufflesPerDest = LT.first * 2 - 1; 1072 LT.first = NumOfDests * NumOfShufflesPerDest; 1073 } 1074 1075 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1076 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1077 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1078 1079 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1080 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1081 1082 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b 1083 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b 1084 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2} // vpermt2b 1085 }; 1086 1087 if (ST->hasVBMI()) 1088 if (const auto *Entry = 1089 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1090 return LT.first * Entry->Cost; 1091 1092 static const CostTblEntry AVX512BWShuffleTbl[] = { 1093 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1094 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1095 1096 {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw 1097 {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw 1098 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1099 1100 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw 1101 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw 1102 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1103 1104 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w 1105 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w 1106 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2}, // vpermt2w 1107 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1108 }; 1109 1110 if (ST->hasBWI()) 1111 if (const auto *Entry = 1112 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1113 return LT.first * Entry->Cost; 1114 1115 static const CostTblEntry AVX512ShuffleTbl[] = { 1116 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1117 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1118 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1119 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1120 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1121 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1122 1123 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1124 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1125 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1126 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1127 1128 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1129 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1130 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1131 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1132 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1133 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1134 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1135 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1136 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1137 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1138 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1139 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1140 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1141 1142 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1143 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1144 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1145 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1146 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1147 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1148 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1149 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1150 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1151 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1152 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1153 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1154 1155 // FIXME: This just applies the type legalization cost rules above 1156 // assuming these completely split. 1157 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1158 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1159 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1160 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1161 }; 1162 1163 if (ST->hasAVX512()) 1164 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1165 return LT.first * Entry->Cost; 1166 1167 static const CostTblEntry AVX2ShuffleTbl[] = { 1168 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1169 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1170 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1171 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1172 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1173 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1174 1175 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1176 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1177 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1178 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1179 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1180 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1181 1182 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1183 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1184 1185 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1186 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1187 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1188 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1189 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1190 // + vpblendvb 1191 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1192 // + vpblendvb 1193 1194 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1195 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1196 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1197 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1198 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1199 // + vpblendvb 1200 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1201 // + vpblendvb 1202 }; 1203 1204 if (ST->hasAVX2()) 1205 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1206 return LT.first * Entry->Cost; 1207 1208 static const CostTblEntry XOPShuffleTbl[] = { 1209 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1210 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1211 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1212 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1213 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1214 // + vinsertf128 1215 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1216 // + vinsertf128 1217 1218 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1219 // + vinsertf128 1220 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1221 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1222 // + vinsertf128 1223 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1224 }; 1225 1226 if (ST->hasXOP()) 1227 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1228 return LT.first * Entry->Cost; 1229 1230 static const CostTblEntry AVX1ShuffleTbl[] = { 1231 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1232 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1233 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1234 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1235 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1236 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1237 1238 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1239 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1240 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1241 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1242 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1243 // + vinsertf128 1244 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1245 // + vinsertf128 1246 1247 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1248 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1249 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1250 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1251 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1252 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1253 1254 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1255 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1256 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1257 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1258 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1259 // + 2*por + vinsertf128 1260 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1261 // + 2*por + vinsertf128 1262 1263 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1264 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1265 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1266 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1267 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1268 // + 4*por + vinsertf128 1269 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1270 // + 4*por + vinsertf128 1271 }; 1272 1273 if (ST->hasAVX()) 1274 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1275 return LT.first * Entry->Cost; 1276 1277 static const CostTblEntry SSE41ShuffleTbl[] = { 1278 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1279 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1280 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1281 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1282 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1283 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1284 }; 1285 1286 if (ST->hasSSE41()) 1287 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1288 return LT.first * Entry->Cost; 1289 1290 static const CostTblEntry SSSE3ShuffleTbl[] = { 1291 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1292 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1293 1294 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1295 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1296 1297 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1298 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1299 1300 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1301 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1302 1303 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1304 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1305 }; 1306 1307 if (ST->hasSSSE3()) 1308 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1309 return LT.first * Entry->Cost; 1310 1311 static const CostTblEntry SSE2ShuffleTbl[] = { 1312 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1313 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1314 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1315 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1316 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1317 1318 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1319 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1320 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1321 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1322 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1323 // + 2*pshufd + 2*unpck + packus 1324 1325 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1326 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1327 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1328 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1329 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1330 1331 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1332 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1333 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1334 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1335 // + pshufd/unpck 1336 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1337 // + 2*pshufd + 2*unpck + 2*packus 1338 1339 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1340 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1341 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1342 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1343 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1344 }; 1345 1346 if (ST->hasSSE2()) 1347 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1348 return LT.first * Entry->Cost; 1349 1350 static const CostTblEntry SSE1ShuffleTbl[] = { 1351 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1352 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1353 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1354 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1355 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1356 }; 1357 1358 if (ST->hasSSE1()) 1359 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1360 return LT.first * Entry->Cost; 1361 1362 return BaseT::getShuffleCost(Kind, BaseTp, Index, SubTp); 1363 } 1364 1365 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 1366 TTI::TargetCostKind CostKind, 1367 const Instruction *I) { 1368 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1369 assert(ISD && "Invalid opcode"); 1370 1371 // FIXME: Need a better design of the cost table to handle non-simple types of 1372 // potential massive combinations (elem_num x src_type x dst_type). 1373 1374 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1375 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1376 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1377 1378 // Mask sign extend has an instruction. 1379 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1380 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1381 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1382 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1383 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1384 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1385 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1386 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1387 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1388 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1389 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1390 1391 // Mask zero extend is a sext + shift. 1392 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1393 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1394 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1395 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1396 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1397 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1398 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1399 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1400 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1401 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1402 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1403 1404 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, 1405 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm 1406 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // widen to zmm 1407 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // widen to zmm 1408 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // widen to zmm 1409 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // widen to zmm 1410 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // widen to zmm 1411 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // widen to zmm 1412 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // widen to zmm 1413 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // widen to zmm 1414 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // widen to zmm 1415 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, 1416 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, 1417 }; 1418 1419 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1420 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1421 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1422 1423 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1424 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1425 1426 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1427 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1428 1429 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1430 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1431 }; 1432 1433 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1434 // 256-bit wide vectors. 1435 1436 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1437 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1438 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1439 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1440 1441 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1442 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1443 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1444 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd 1445 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1446 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1447 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1448 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd 1449 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd 1450 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd 1451 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd 1452 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd 1453 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq 1454 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq 1455 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq 1456 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, 1457 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, 1458 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, 1459 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, 1460 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 1461 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd 1462 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb 1463 1464 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32 1465 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, 1466 1467 // Sign extend is zmm vpternlogd+vptruncdb. 1468 // Zero extend is zmm broadcast load+vptruncdw. 1469 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 }, 1470 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 }, 1471 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, 1472 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, 1473 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, 1474 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, 1475 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 }, 1476 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 }, 1477 1478 // Sign extend is zmm vpternlogd+vptruncdw. 1479 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw. 1480 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 }, 1481 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1482 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 }, 1483 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1484 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 }, 1485 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1486 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 }, 1487 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1488 1489 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd 1490 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld 1491 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd 1492 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld 1493 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd 1494 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld 1495 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq 1496 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq 1497 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq 1498 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq 1499 1500 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd 1501 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld 1502 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq 1503 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq 1504 1505 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1506 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1507 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1508 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1509 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1510 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1511 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1512 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1513 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1514 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1515 1516 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1517 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1518 1519 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1520 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1521 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1522 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1523 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1524 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1525 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1526 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1527 1528 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1529 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1530 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1531 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1532 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1533 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1534 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1535 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1536 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1537 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1538 1539 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f64, 3 }, 1540 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, 1541 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 3 }, 1542 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 3 }, 1543 1544 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1545 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, 1546 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, 1547 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1548 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, 1549 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, 1550 }; 1551 1552 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1553 // Mask sign extend has an instruction. 1554 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1555 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1556 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1557 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1558 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1559 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1560 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1561 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1562 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1563 1564 // Mask zero extend is a sext + shift. 1565 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1566 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1567 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1568 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1569 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1570 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1571 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1572 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1573 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1574 1575 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, 1576 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // vpsllw+vptestmb 1577 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // vpsllw+vptestmw 1578 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // vpsllw+vptestmb 1579 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // vpsllw+vptestmw 1580 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // vpsllw+vptestmb 1581 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // vpsllw+vptestmw 1582 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // vpsllw+vptestmb 1583 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // vpsllw+vptestmw 1584 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // vpsllw+vptestmb 1585 }; 1586 1587 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1588 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1589 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1590 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1591 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1592 1593 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1594 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1595 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1596 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1597 1598 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1599 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1600 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1601 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1602 1603 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1604 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1605 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1606 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1607 }; 1608 1609 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 1610 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1611 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1612 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1613 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 8 }, // split+2*v8i8 1614 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1615 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1616 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1617 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16 1618 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // vpslld+vptestmd 1619 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd 1620 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // vpslld+vptestmd 1621 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // vpsllq+vptestmq 1622 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // vpsllq+vptestmq 1623 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // vpmovqd 1624 1625 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb 1626 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb 1627 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 }, 1628 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 }, 1629 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 }, 1630 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 }, 1631 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 }, 1632 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 }, 1633 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 }, 1634 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 }, 1635 1636 // sign extend is vpcmpeq+maskedmove+vpmovdw 1637 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw 1638 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1639 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 }, 1640 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1641 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 }, 1642 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1643 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 }, 1644 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 }, 1645 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 }, 1646 1647 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd 1648 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld 1649 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd 1650 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld 1651 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd 1652 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld 1653 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq 1654 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq 1655 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq 1656 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq 1657 1658 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1659 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1660 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1661 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1662 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1663 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1664 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1665 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1666 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1667 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1668 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1669 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1670 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1671 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1672 1673 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 1674 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1675 1676 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 3 }, 1677 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 3 }, 1678 1679 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 1680 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 1681 1682 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1683 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1684 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 1 }, 1685 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1686 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1687 }; 1688 1689 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1690 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1691 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1692 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1693 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1694 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1695 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1696 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1697 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1698 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1699 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1700 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1701 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1702 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1703 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1704 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1705 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1706 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1707 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1708 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1709 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1710 1711 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1712 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1713 1714 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 1715 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 1716 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 1717 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1718 1719 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1720 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1721 1722 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1723 }; 1724 1725 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1726 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1727 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1728 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1729 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1730 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1731 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1732 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1733 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1734 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1735 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1736 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1737 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1738 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 4 }, 1739 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1740 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1741 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1742 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1743 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1744 1745 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 4 }, 1746 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 5 }, 1747 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 4 }, 1748 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 9 }, 1749 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, 11 }, 1750 1751 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 1752 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1753 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1754 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1755 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 1756 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1757 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 11 }, 1758 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 9 }, 1759 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 }, 1760 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 11 }, 1761 1762 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1763 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1764 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1765 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1766 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1767 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1768 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1769 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1770 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1771 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1772 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1773 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1774 1775 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1776 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1777 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1778 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1779 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1780 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1781 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1782 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1783 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1784 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 }, 1785 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 1786 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1787 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 1788 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1789 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1790 // The generic code to compute the scalar overhead is currently broken. 1791 // Workaround this limitation by estimating the scalarization overhead 1792 // here. We have roughly 10 instructions per scalar element. 1793 // Multiply that by the vector width. 1794 // FIXME: remove that when PR19268 is fixed. 1795 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1796 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1797 1798 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 4 }, 1799 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f64, 3 }, 1800 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f64, 2 }, 1801 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 3 }, 1802 1803 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f64, 3 }, 1804 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f64, 2 }, 1805 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 4 }, 1806 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 3 }, 1807 // This node is expanded into scalarized operations but BasicTTI is overly 1808 // optimistic estimating its cost. It computes 3 per element (one 1809 // vector-extract, one scalar conversion and one vector-insert). The 1810 // problem is that the inserts form a read-modify-write chain so latency 1811 // should be factored in too. Inflating the cost per element by 1. 1812 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, 1813 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 1814 1815 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 1816 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 1817 }; 1818 1819 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 1820 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1821 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1822 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1823 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1824 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1825 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1826 1827 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1828 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 }, 1829 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1830 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1831 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1832 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1833 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1834 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1835 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1836 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1837 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1838 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1839 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1840 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1841 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1842 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1843 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1844 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1845 1846 // These truncates end up widening elements. 1847 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 1 }, // PMOVXZBQ 1848 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 1 }, // PMOVXZWQ 1849 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 1 }, // PMOVXZBD 1850 1851 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 1 }, 1852 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 1 }, 1853 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 1854 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 1855 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 1856 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 1857 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 1858 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 1859 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 1 }, // PSHUFB 1860 1861 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 1862 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 1863 1864 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 3 }, 1865 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 3 }, 1866 1867 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 3 }, 1868 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 3 }, 1869 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, 1870 }; 1871 1872 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 1873 // These are somewhat magic numbers justified by looking at the output of 1874 // Intel's IACA, running some kernels and making sure when we take 1875 // legalization into account the throughput will be overestimated. 1876 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1877 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1878 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1879 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1880 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1881 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 2*10 }, 1882 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2*10 }, 1883 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1884 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 1885 1886 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1887 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1888 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1889 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1890 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1891 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, 1892 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 }, 1893 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1894 1895 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 4 }, 1896 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 2 }, 1897 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, 1898 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, 1899 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, 1900 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 4 }, 1901 1902 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 1 }, 1903 1904 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 6 }, 1905 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 }, 1906 1907 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 1908 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 1909 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 4 }, 1910 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 4 }, 1911 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 }, 1912 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 2 }, 1913 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 }, 1914 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 4 }, 1915 1916 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1917 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 1918 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 1919 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 1920 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1921 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 1922 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1923 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 1924 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1925 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1926 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1927 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1928 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 1929 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 1930 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1931 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 1932 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1933 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 1934 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1935 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1936 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 1937 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 1938 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1939 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 1940 1941 // These truncates are really widening elements. 1942 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 1 }, // PSHUFD 1943 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // PUNPCKLWD+DQ 1944 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // PUNPCKLBW+WD+PSHUFD 1945 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 1 }, // PUNPCKLWD 1946 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // PUNPCKLBW+WD 1947 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 1 }, // PUNPCKLBW 1948 1949 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // PAND+PACKUSWB 1950 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // PAND+PACKUSWB 1951 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // PAND+PACKUSWB 1952 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 1953 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 3 }, // PAND+2*PACKUSWB 1954 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 1955 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 1956 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 1957 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1958 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 1959 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1960 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 1961 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 1962 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 1963 { ISD::TRUNCATE, MVT::v2i32, MVT::v2i64, 1 }, // PSHUFD 1964 }; 1965 1966 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 1967 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst); 1968 1969 if (ST->hasSSE2() && !ST->hasAVX()) { 1970 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1971 LTDest.second, LTSrc.second)) 1972 return LTSrc.first * Entry->Cost; 1973 } 1974 1975 EVT SrcTy = TLI->getValueType(DL, Src); 1976 EVT DstTy = TLI->getValueType(DL, Dst); 1977 1978 // The function getSimpleVT only handles simple value types. 1979 if (!SrcTy.isSimple() || !DstTy.isSimple()) 1980 return BaseT::getCastInstrCost(Opcode, Dst, Src, CostKind); 1981 1982 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 1983 MVT SimpleDstTy = DstTy.getSimpleVT(); 1984 1985 if (ST->useAVX512Regs()) { 1986 if (ST->hasBWI()) 1987 if (const auto *Entry = ConvertCostTableLookup(AVX512BWConversionTbl, ISD, 1988 SimpleDstTy, SimpleSrcTy)) 1989 return Entry->Cost; 1990 1991 if (ST->hasDQI()) 1992 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 1993 SimpleDstTy, SimpleSrcTy)) 1994 return Entry->Cost; 1995 1996 if (ST->hasAVX512()) 1997 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 1998 SimpleDstTy, SimpleSrcTy)) 1999 return Entry->Cost; 2000 } 2001 2002 if (ST->hasBWI()) 2003 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 2004 SimpleDstTy, SimpleSrcTy)) 2005 return Entry->Cost; 2006 2007 if (ST->hasDQI()) 2008 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 2009 SimpleDstTy, SimpleSrcTy)) 2010 return Entry->Cost; 2011 2012 if (ST->hasAVX512()) 2013 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2014 SimpleDstTy, SimpleSrcTy)) 2015 return Entry->Cost; 2016 2017 if (ST->hasAVX2()) { 2018 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2019 SimpleDstTy, SimpleSrcTy)) 2020 return Entry->Cost; 2021 } 2022 2023 if (ST->hasAVX()) { 2024 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2025 SimpleDstTy, SimpleSrcTy)) 2026 return Entry->Cost; 2027 } 2028 2029 if (ST->hasSSE41()) { 2030 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2031 SimpleDstTy, SimpleSrcTy)) 2032 return Entry->Cost; 2033 } 2034 2035 if (ST->hasSSE2()) { 2036 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2037 SimpleDstTy, SimpleSrcTy)) 2038 return Entry->Cost; 2039 } 2040 2041 return BaseT::getCastInstrCost(Opcode, Dst, Src, CostKind, I); 2042 } 2043 2044 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 2045 TTI::TargetCostKind CostKind, 2046 const Instruction *I) { 2047 // Legalize the type. 2048 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2049 2050 MVT MTy = LT.second; 2051 2052 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2053 assert(ISD && "Invalid opcode"); 2054 2055 unsigned ExtraCost = 0; 2056 if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) { 2057 // Some vector comparison predicates cost extra instructions. 2058 if (MTy.isVector() && 2059 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 2060 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 2061 ST->hasBWI())) { 2062 switch (cast<CmpInst>(I)->getPredicate()) { 2063 case CmpInst::Predicate::ICMP_NE: 2064 // xor(cmpeq(x,y),-1) 2065 ExtraCost = 1; 2066 break; 2067 case CmpInst::Predicate::ICMP_SGE: 2068 case CmpInst::Predicate::ICMP_SLE: 2069 // xor(cmpgt(x,y),-1) 2070 ExtraCost = 1; 2071 break; 2072 case CmpInst::Predicate::ICMP_ULT: 2073 case CmpInst::Predicate::ICMP_UGT: 2074 // cmpgt(xor(x,signbit),xor(y,signbit)) 2075 // xor(cmpeq(pmaxu(x,y),x),-1) 2076 ExtraCost = 2; 2077 break; 2078 case CmpInst::Predicate::ICMP_ULE: 2079 case CmpInst::Predicate::ICMP_UGE: 2080 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 2081 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 2082 // cmpeq(psubus(x,y),0) 2083 // cmpeq(pminu(x,y),x) 2084 ExtraCost = 1; 2085 } else { 2086 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 2087 ExtraCost = 3; 2088 } 2089 break; 2090 default: 2091 break; 2092 } 2093 } 2094 } 2095 2096 static const CostTblEntry SLMCostTbl[] = { 2097 // slm pcmpeq/pcmpgt throughput is 2 2098 { ISD::SETCC, MVT::v2i64, 2 }, 2099 }; 2100 2101 static const CostTblEntry AVX512BWCostTbl[] = { 2102 { ISD::SETCC, MVT::v32i16, 1 }, 2103 { ISD::SETCC, MVT::v64i8, 1 }, 2104 2105 { ISD::SELECT, MVT::v32i16, 1 }, 2106 { ISD::SELECT, MVT::v64i8, 1 }, 2107 }; 2108 2109 static const CostTblEntry AVX512CostTbl[] = { 2110 { ISD::SETCC, MVT::v8i64, 1 }, 2111 { ISD::SETCC, MVT::v16i32, 1 }, 2112 { ISD::SETCC, MVT::v8f64, 1 }, 2113 { ISD::SETCC, MVT::v16f32, 1 }, 2114 2115 { ISD::SELECT, MVT::v8i64, 1 }, 2116 { ISD::SELECT, MVT::v16i32, 1 }, 2117 { ISD::SELECT, MVT::v8f64, 1 }, 2118 { ISD::SELECT, MVT::v16f32, 1 }, 2119 2120 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 2121 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 2122 2123 { ISD::SELECT, MVT::v32i16, 2 }, // FIXME: should be 3 2124 { ISD::SELECT, MVT::v64i8, 2 }, // FIXME: should be 3 2125 }; 2126 2127 static const CostTblEntry AVX2CostTbl[] = { 2128 { ISD::SETCC, MVT::v4i64, 1 }, 2129 { ISD::SETCC, MVT::v8i32, 1 }, 2130 { ISD::SETCC, MVT::v16i16, 1 }, 2131 { ISD::SETCC, MVT::v32i8, 1 }, 2132 2133 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 2134 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 2135 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 2136 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 2137 }; 2138 2139 static const CostTblEntry AVX1CostTbl[] = { 2140 { ISD::SETCC, MVT::v4f64, 1 }, 2141 { ISD::SETCC, MVT::v8f32, 1 }, 2142 // AVX1 does not support 8-wide integer compare. 2143 { ISD::SETCC, MVT::v4i64, 4 }, 2144 { ISD::SETCC, MVT::v8i32, 4 }, 2145 { ISD::SETCC, MVT::v16i16, 4 }, 2146 { ISD::SETCC, MVT::v32i8, 4 }, 2147 2148 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 2149 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 2150 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 2151 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 2152 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 2153 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 2154 }; 2155 2156 static const CostTblEntry SSE42CostTbl[] = { 2157 { ISD::SETCC, MVT::v2f64, 1 }, 2158 { ISD::SETCC, MVT::v4f32, 1 }, 2159 { ISD::SETCC, MVT::v2i64, 1 }, 2160 }; 2161 2162 static const CostTblEntry SSE41CostTbl[] = { 2163 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 2164 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 2165 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 2166 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 2167 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 2168 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 2169 }; 2170 2171 static const CostTblEntry SSE2CostTbl[] = { 2172 { ISD::SETCC, MVT::v2f64, 2 }, 2173 { ISD::SETCC, MVT::f64, 1 }, 2174 { ISD::SETCC, MVT::v2i64, 8 }, 2175 { ISD::SETCC, MVT::v4i32, 1 }, 2176 { ISD::SETCC, MVT::v8i16, 1 }, 2177 { ISD::SETCC, MVT::v16i8, 1 }, 2178 2179 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 2180 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 2181 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 2182 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 2183 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 2184 }; 2185 2186 static const CostTblEntry SSE1CostTbl[] = { 2187 { ISD::SETCC, MVT::v4f32, 2 }, 2188 { ISD::SETCC, MVT::f32, 1 }, 2189 2190 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 2191 }; 2192 2193 if (ST->isSLM()) 2194 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2195 return LT.first * (ExtraCost + Entry->Cost); 2196 2197 if (ST->hasBWI()) 2198 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2199 return LT.first * (ExtraCost + Entry->Cost); 2200 2201 if (ST->hasAVX512()) 2202 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2203 return LT.first * (ExtraCost + Entry->Cost); 2204 2205 if (ST->hasAVX2()) 2206 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2207 return LT.first * (ExtraCost + Entry->Cost); 2208 2209 if (ST->hasAVX()) 2210 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2211 return LT.first * (ExtraCost + Entry->Cost); 2212 2213 if (ST->hasSSE42()) 2214 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2215 return LT.first * (ExtraCost + Entry->Cost); 2216 2217 if (ST->hasSSE41()) 2218 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2219 return LT.first * (ExtraCost + Entry->Cost); 2220 2221 if (ST->hasSSE2()) 2222 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2223 return LT.first * (ExtraCost + Entry->Cost); 2224 2225 if (ST->hasSSE1()) 2226 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2227 return LT.first * (ExtraCost + Entry->Cost); 2228 2229 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, CostKind, I); 2230 } 2231 2232 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2233 2234 int X86TTIImpl::getTypeBasedIntrinsicInstrCost( 2235 const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) { 2236 2237 // Costs should match the codegen from: 2238 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2239 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2240 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2241 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2242 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2243 static const CostTblEntry AVX512CDCostTbl[] = { 2244 { ISD::CTLZ, MVT::v8i64, 1 }, 2245 { ISD::CTLZ, MVT::v16i32, 1 }, 2246 { ISD::CTLZ, MVT::v32i16, 8 }, 2247 { ISD::CTLZ, MVT::v64i8, 20 }, 2248 { ISD::CTLZ, MVT::v4i64, 1 }, 2249 { ISD::CTLZ, MVT::v8i32, 1 }, 2250 { ISD::CTLZ, MVT::v16i16, 4 }, 2251 { ISD::CTLZ, MVT::v32i8, 10 }, 2252 { ISD::CTLZ, MVT::v2i64, 1 }, 2253 { ISD::CTLZ, MVT::v4i32, 1 }, 2254 { ISD::CTLZ, MVT::v8i16, 4 }, 2255 { ISD::CTLZ, MVT::v16i8, 4 }, 2256 }; 2257 static const CostTblEntry AVX512BWCostTbl[] = { 2258 { ISD::BITREVERSE, MVT::v8i64, 5 }, 2259 { ISD::BITREVERSE, MVT::v16i32, 5 }, 2260 { ISD::BITREVERSE, MVT::v32i16, 5 }, 2261 { ISD::BITREVERSE, MVT::v64i8, 5 }, 2262 { ISD::CTLZ, MVT::v8i64, 23 }, 2263 { ISD::CTLZ, MVT::v16i32, 22 }, 2264 { ISD::CTLZ, MVT::v32i16, 18 }, 2265 { ISD::CTLZ, MVT::v64i8, 17 }, 2266 { ISD::CTPOP, MVT::v8i64, 7 }, 2267 { ISD::CTPOP, MVT::v16i32, 11 }, 2268 { ISD::CTPOP, MVT::v32i16, 9 }, 2269 { ISD::CTPOP, MVT::v64i8, 6 }, 2270 { ISD::CTTZ, MVT::v8i64, 10 }, 2271 { ISD::CTTZ, MVT::v16i32, 14 }, 2272 { ISD::CTTZ, MVT::v32i16, 12 }, 2273 { ISD::CTTZ, MVT::v64i8, 9 }, 2274 { ISD::SADDSAT, MVT::v32i16, 1 }, 2275 { ISD::SADDSAT, MVT::v64i8, 1 }, 2276 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2277 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2278 { ISD::UADDSAT, MVT::v32i16, 1 }, 2279 { ISD::UADDSAT, MVT::v64i8, 1 }, 2280 { ISD::USUBSAT, MVT::v32i16, 1 }, 2281 { ISD::USUBSAT, MVT::v64i8, 1 }, 2282 }; 2283 static const CostTblEntry AVX512CostTbl[] = { 2284 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2285 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2286 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2287 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2288 { ISD::CTLZ, MVT::v8i64, 29 }, 2289 { ISD::CTLZ, MVT::v16i32, 35 }, 2290 { ISD::CTLZ, MVT::v32i16, 28 }, 2291 { ISD::CTLZ, MVT::v64i8, 18 }, 2292 { ISD::CTPOP, MVT::v8i64, 16 }, 2293 { ISD::CTPOP, MVT::v16i32, 24 }, 2294 { ISD::CTPOP, MVT::v32i16, 18 }, 2295 { ISD::CTPOP, MVT::v64i8, 12 }, 2296 { ISD::CTTZ, MVT::v8i64, 20 }, 2297 { ISD::CTTZ, MVT::v16i32, 28 }, 2298 { ISD::CTTZ, MVT::v32i16, 24 }, 2299 { ISD::CTTZ, MVT::v64i8, 18 }, 2300 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2301 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2302 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2303 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2304 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2305 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2306 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2307 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2308 { ISD::SADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2309 { ISD::SADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2310 { ISD::SSUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2311 { ISD::SSUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2312 { ISD::UADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2313 { ISD::UADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2314 { ISD::USUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2315 { ISD::USUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2316 { ISD::FMAXNUM, MVT::f32, 2 }, 2317 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2318 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2319 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2320 { ISD::FMAXNUM, MVT::f64, 2 }, 2321 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2322 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2323 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2324 }; 2325 static const CostTblEntry XOPCostTbl[] = { 2326 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2327 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2328 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2329 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2330 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2331 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2332 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2333 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2334 { ISD::BITREVERSE, MVT::i64, 3 }, 2335 { ISD::BITREVERSE, MVT::i32, 3 }, 2336 { ISD::BITREVERSE, MVT::i16, 3 }, 2337 { ISD::BITREVERSE, MVT::i8, 3 } 2338 }; 2339 static const CostTblEntry AVX2CostTbl[] = { 2340 { ISD::BITREVERSE, MVT::v4i64, 5 }, 2341 { ISD::BITREVERSE, MVT::v8i32, 5 }, 2342 { ISD::BITREVERSE, MVT::v16i16, 5 }, 2343 { ISD::BITREVERSE, MVT::v32i8, 5 }, 2344 { ISD::BSWAP, MVT::v4i64, 1 }, 2345 { ISD::BSWAP, MVT::v8i32, 1 }, 2346 { ISD::BSWAP, MVT::v16i16, 1 }, 2347 { ISD::CTLZ, MVT::v4i64, 23 }, 2348 { ISD::CTLZ, MVT::v8i32, 18 }, 2349 { ISD::CTLZ, MVT::v16i16, 14 }, 2350 { ISD::CTLZ, MVT::v32i8, 9 }, 2351 { ISD::CTPOP, MVT::v4i64, 7 }, 2352 { ISD::CTPOP, MVT::v8i32, 11 }, 2353 { ISD::CTPOP, MVT::v16i16, 9 }, 2354 { ISD::CTPOP, MVT::v32i8, 6 }, 2355 { ISD::CTTZ, MVT::v4i64, 10 }, 2356 { ISD::CTTZ, MVT::v8i32, 14 }, 2357 { ISD::CTTZ, MVT::v16i16, 12 }, 2358 { ISD::CTTZ, MVT::v32i8, 9 }, 2359 { ISD::SADDSAT, MVT::v16i16, 1 }, 2360 { ISD::SADDSAT, MVT::v32i8, 1 }, 2361 { ISD::SSUBSAT, MVT::v16i16, 1 }, 2362 { ISD::SSUBSAT, MVT::v32i8, 1 }, 2363 { ISD::UADDSAT, MVT::v16i16, 1 }, 2364 { ISD::UADDSAT, MVT::v32i8, 1 }, 2365 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 2366 { ISD::USUBSAT, MVT::v16i16, 1 }, 2367 { ISD::USUBSAT, MVT::v32i8, 1 }, 2368 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2369 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2370 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2371 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2372 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2373 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2374 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2375 }; 2376 static const CostTblEntry AVX1CostTbl[] = { 2377 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 2378 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 2379 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 2380 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 2381 { ISD::BSWAP, MVT::v4i64, 4 }, 2382 { ISD::BSWAP, MVT::v8i32, 4 }, 2383 { ISD::BSWAP, MVT::v16i16, 4 }, 2384 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 2385 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 2386 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 2387 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2388 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 2389 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 2390 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 2391 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 2392 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 2393 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 2394 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 2395 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2396 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2397 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2398 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2399 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2400 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2401 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2402 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 2403 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2404 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2405 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 2406 { ISD::FMAXNUM, MVT::f32, 3 }, 2407 { ISD::FMAXNUM, MVT::v4f32, 3 }, 2408 { ISD::FMAXNUM, MVT::v8f32, 5 }, 2409 { ISD::FMAXNUM, MVT::f64, 3 }, 2410 { ISD::FMAXNUM, MVT::v2f64, 3 }, 2411 { ISD::FMAXNUM, MVT::v4f64, 5 }, 2412 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 2413 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 2414 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 2415 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 2416 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 2417 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 2418 }; 2419 static const CostTblEntry GLMCostTbl[] = { 2420 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 2421 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 2422 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 2423 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 2424 }; 2425 static const CostTblEntry SLMCostTbl[] = { 2426 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 2427 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 2428 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 2429 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 2430 }; 2431 static const CostTblEntry SSE42CostTbl[] = { 2432 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 2433 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 2434 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 2435 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 2436 }; 2437 static const CostTblEntry SSSE3CostTbl[] = { 2438 { ISD::BITREVERSE, MVT::v2i64, 5 }, 2439 { ISD::BITREVERSE, MVT::v4i32, 5 }, 2440 { ISD::BITREVERSE, MVT::v8i16, 5 }, 2441 { ISD::BITREVERSE, MVT::v16i8, 5 }, 2442 { ISD::BSWAP, MVT::v2i64, 1 }, 2443 { ISD::BSWAP, MVT::v4i32, 1 }, 2444 { ISD::BSWAP, MVT::v8i16, 1 }, 2445 { ISD::CTLZ, MVT::v2i64, 23 }, 2446 { ISD::CTLZ, MVT::v4i32, 18 }, 2447 { ISD::CTLZ, MVT::v8i16, 14 }, 2448 { ISD::CTLZ, MVT::v16i8, 9 }, 2449 { ISD::CTPOP, MVT::v2i64, 7 }, 2450 { ISD::CTPOP, MVT::v4i32, 11 }, 2451 { ISD::CTPOP, MVT::v8i16, 9 }, 2452 { ISD::CTPOP, MVT::v16i8, 6 }, 2453 { ISD::CTTZ, MVT::v2i64, 10 }, 2454 { ISD::CTTZ, MVT::v4i32, 14 }, 2455 { ISD::CTTZ, MVT::v8i16, 12 }, 2456 { ISD::CTTZ, MVT::v16i8, 9 } 2457 }; 2458 static const CostTblEntry SSE2CostTbl[] = { 2459 { ISD::BITREVERSE, MVT::v2i64, 29 }, 2460 { ISD::BITREVERSE, MVT::v4i32, 27 }, 2461 { ISD::BITREVERSE, MVT::v8i16, 27 }, 2462 { ISD::BITREVERSE, MVT::v16i8, 20 }, 2463 { ISD::BSWAP, MVT::v2i64, 7 }, 2464 { ISD::BSWAP, MVT::v4i32, 7 }, 2465 { ISD::BSWAP, MVT::v8i16, 7 }, 2466 { ISD::CTLZ, MVT::v2i64, 25 }, 2467 { ISD::CTLZ, MVT::v4i32, 26 }, 2468 { ISD::CTLZ, MVT::v8i16, 20 }, 2469 { ISD::CTLZ, MVT::v16i8, 17 }, 2470 { ISD::CTPOP, MVT::v2i64, 12 }, 2471 { ISD::CTPOP, MVT::v4i32, 15 }, 2472 { ISD::CTPOP, MVT::v8i16, 13 }, 2473 { ISD::CTPOP, MVT::v16i8, 10 }, 2474 { ISD::CTTZ, MVT::v2i64, 14 }, 2475 { ISD::CTTZ, MVT::v4i32, 18 }, 2476 { ISD::CTTZ, MVT::v8i16, 16 }, 2477 { ISD::CTTZ, MVT::v16i8, 13 }, 2478 { ISD::SADDSAT, MVT::v8i16, 1 }, 2479 { ISD::SADDSAT, MVT::v16i8, 1 }, 2480 { ISD::SSUBSAT, MVT::v8i16, 1 }, 2481 { ISD::SSUBSAT, MVT::v16i8, 1 }, 2482 { ISD::UADDSAT, MVT::v8i16, 1 }, 2483 { ISD::UADDSAT, MVT::v16i8, 1 }, 2484 { ISD::USUBSAT, MVT::v8i16, 1 }, 2485 { ISD::USUBSAT, MVT::v16i8, 1 }, 2486 { ISD::FMAXNUM, MVT::f64, 4 }, 2487 { ISD::FMAXNUM, MVT::v2f64, 4 }, 2488 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 2489 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 2490 }; 2491 static const CostTblEntry SSE1CostTbl[] = { 2492 { ISD::FMAXNUM, MVT::f32, 4 }, 2493 { ISD::FMAXNUM, MVT::v4f32, 4 }, 2494 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 2495 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 2496 }; 2497 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 2498 { ISD::CTTZ, MVT::i64, 1 }, 2499 }; 2500 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 2501 { ISD::CTTZ, MVT::i32, 1 }, 2502 { ISD::CTTZ, MVT::i16, 1 }, 2503 { ISD::CTTZ, MVT::i8, 1 }, 2504 }; 2505 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 2506 { ISD::CTLZ, MVT::i64, 1 }, 2507 }; 2508 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 2509 { ISD::CTLZ, MVT::i32, 1 }, 2510 { ISD::CTLZ, MVT::i16, 1 }, 2511 { ISD::CTLZ, MVT::i8, 1 }, 2512 }; 2513 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 2514 { ISD::CTPOP, MVT::i64, 1 }, 2515 }; 2516 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 2517 { ISD::CTPOP, MVT::i32, 1 }, 2518 { ISD::CTPOP, MVT::i16, 1 }, 2519 { ISD::CTPOP, MVT::i8, 1 }, 2520 }; 2521 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2522 { ISD::BITREVERSE, MVT::i64, 14 }, 2523 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 2524 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 2525 { ISD::CTPOP, MVT::i64, 10 }, 2526 { ISD::SADDO, MVT::i64, 1 }, 2527 { ISD::UADDO, MVT::i64, 1 }, 2528 }; 2529 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2530 { ISD::BITREVERSE, MVT::i32, 14 }, 2531 { ISD::BITREVERSE, MVT::i16, 14 }, 2532 { ISD::BITREVERSE, MVT::i8, 11 }, 2533 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 2534 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 2535 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 2536 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 2537 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 2538 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 2539 { ISD::CTPOP, MVT::i32, 8 }, 2540 { ISD::CTPOP, MVT::i16, 9 }, 2541 { ISD::CTPOP, MVT::i8, 7 }, 2542 { ISD::SADDO, MVT::i32, 1 }, 2543 { ISD::SADDO, MVT::i16, 1 }, 2544 { ISD::SADDO, MVT::i8, 1 }, 2545 { ISD::UADDO, MVT::i32, 1 }, 2546 { ISD::UADDO, MVT::i16, 1 }, 2547 { ISD::UADDO, MVT::i8, 1 }, 2548 }; 2549 2550 Type *RetTy = ICA.getReturnType(); 2551 Type *OpTy = RetTy; 2552 Intrinsic::ID IID = ICA.getID(); 2553 unsigned ISD = ISD::DELETED_NODE; 2554 switch (IID) { 2555 default: 2556 break; 2557 case Intrinsic::bitreverse: 2558 ISD = ISD::BITREVERSE; 2559 break; 2560 case Intrinsic::bswap: 2561 ISD = ISD::BSWAP; 2562 break; 2563 case Intrinsic::ctlz: 2564 ISD = ISD::CTLZ; 2565 break; 2566 case Intrinsic::ctpop: 2567 ISD = ISD::CTPOP; 2568 break; 2569 case Intrinsic::cttz: 2570 ISD = ISD::CTTZ; 2571 break; 2572 case Intrinsic::maxnum: 2573 case Intrinsic::minnum: 2574 // FMINNUM has same costs so don't duplicate. 2575 ISD = ISD::FMAXNUM; 2576 break; 2577 case Intrinsic::sadd_sat: 2578 ISD = ISD::SADDSAT; 2579 break; 2580 case Intrinsic::ssub_sat: 2581 ISD = ISD::SSUBSAT; 2582 break; 2583 case Intrinsic::uadd_sat: 2584 ISD = ISD::UADDSAT; 2585 break; 2586 case Intrinsic::usub_sat: 2587 ISD = ISD::USUBSAT; 2588 break; 2589 case Intrinsic::sqrt: 2590 ISD = ISD::FSQRT; 2591 break; 2592 case Intrinsic::sadd_with_overflow: 2593 case Intrinsic::ssub_with_overflow: 2594 // SSUBO has same costs so don't duplicate. 2595 ISD = ISD::SADDO; 2596 OpTy = RetTy->getContainedType(0); 2597 break; 2598 case Intrinsic::uadd_with_overflow: 2599 case Intrinsic::usub_with_overflow: 2600 // USUBO has same costs so don't duplicate. 2601 ISD = ISD::UADDO; 2602 OpTy = RetTy->getContainedType(0); 2603 break; 2604 } 2605 2606 if (ISD != ISD::DELETED_NODE) { 2607 // Legalize the type. 2608 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 2609 MVT MTy = LT.second; 2610 2611 // Attempt to lookup cost. 2612 if (ST->useGLMDivSqrtCosts()) 2613 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 2614 return LT.first * Entry->Cost; 2615 2616 if (ST->isSLM()) 2617 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2618 return LT.first * Entry->Cost; 2619 2620 if (ST->hasCDI()) 2621 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 2622 return LT.first * Entry->Cost; 2623 2624 if (ST->hasBWI()) 2625 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2626 return LT.first * Entry->Cost; 2627 2628 if (ST->hasAVX512()) 2629 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2630 return LT.first * Entry->Cost; 2631 2632 if (ST->hasXOP()) 2633 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2634 return LT.first * Entry->Cost; 2635 2636 if (ST->hasAVX2()) 2637 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2638 return LT.first * Entry->Cost; 2639 2640 if (ST->hasAVX()) 2641 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2642 return LT.first * Entry->Cost; 2643 2644 if (ST->hasSSE42()) 2645 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2646 return LT.first * Entry->Cost; 2647 2648 if (ST->hasSSSE3()) 2649 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 2650 return LT.first * Entry->Cost; 2651 2652 if (ST->hasSSE2()) 2653 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2654 return LT.first * Entry->Cost; 2655 2656 if (ST->hasSSE1()) 2657 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2658 return LT.first * Entry->Cost; 2659 2660 if (ST->hasBMI()) { 2661 if (ST->is64Bit()) 2662 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 2663 return LT.first * Entry->Cost; 2664 2665 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 2666 return LT.first * Entry->Cost; 2667 } 2668 2669 if (ST->hasLZCNT()) { 2670 if (ST->is64Bit()) 2671 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 2672 return LT.first * Entry->Cost; 2673 2674 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 2675 return LT.first * Entry->Cost; 2676 } 2677 2678 if (ST->hasPOPCNT()) { 2679 if (ST->is64Bit()) 2680 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 2681 return LT.first * Entry->Cost; 2682 2683 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 2684 return LT.first * Entry->Cost; 2685 } 2686 2687 // TODO - add BMI (TZCNT) scalar handling 2688 2689 if (ST->is64Bit()) 2690 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2691 return LT.first * Entry->Cost; 2692 2693 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2694 return LT.first * Entry->Cost; 2695 } 2696 2697 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 2698 } 2699 2700 int X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 2701 TTI::TargetCostKind CostKind) { 2702 if (ICA.isTypeBasedOnly()) 2703 return getTypeBasedIntrinsicInstrCost(ICA, CostKind); 2704 2705 static const CostTblEntry AVX512CostTbl[] = { 2706 { ISD::ROTL, MVT::v8i64, 1 }, 2707 { ISD::ROTL, MVT::v4i64, 1 }, 2708 { ISD::ROTL, MVT::v2i64, 1 }, 2709 { ISD::ROTL, MVT::v16i32, 1 }, 2710 { ISD::ROTL, MVT::v8i32, 1 }, 2711 { ISD::ROTL, MVT::v4i32, 1 }, 2712 { ISD::ROTR, MVT::v8i64, 1 }, 2713 { ISD::ROTR, MVT::v4i64, 1 }, 2714 { ISD::ROTR, MVT::v2i64, 1 }, 2715 { ISD::ROTR, MVT::v16i32, 1 }, 2716 { ISD::ROTR, MVT::v8i32, 1 }, 2717 { ISD::ROTR, MVT::v4i32, 1 } 2718 }; 2719 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 2720 static const CostTblEntry XOPCostTbl[] = { 2721 { ISD::ROTL, MVT::v4i64, 4 }, 2722 { ISD::ROTL, MVT::v8i32, 4 }, 2723 { ISD::ROTL, MVT::v16i16, 4 }, 2724 { ISD::ROTL, MVT::v32i8, 4 }, 2725 { ISD::ROTL, MVT::v2i64, 1 }, 2726 { ISD::ROTL, MVT::v4i32, 1 }, 2727 { ISD::ROTL, MVT::v8i16, 1 }, 2728 { ISD::ROTL, MVT::v16i8, 1 }, 2729 { ISD::ROTR, MVT::v4i64, 6 }, 2730 { ISD::ROTR, MVT::v8i32, 6 }, 2731 { ISD::ROTR, MVT::v16i16, 6 }, 2732 { ISD::ROTR, MVT::v32i8, 6 }, 2733 { ISD::ROTR, MVT::v2i64, 2 }, 2734 { ISD::ROTR, MVT::v4i32, 2 }, 2735 { ISD::ROTR, MVT::v8i16, 2 }, 2736 { ISD::ROTR, MVT::v16i8, 2 } 2737 }; 2738 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2739 { ISD::ROTL, MVT::i64, 1 }, 2740 { ISD::ROTR, MVT::i64, 1 }, 2741 { ISD::FSHL, MVT::i64, 4 } 2742 }; 2743 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2744 { ISD::ROTL, MVT::i32, 1 }, 2745 { ISD::ROTL, MVT::i16, 1 }, 2746 { ISD::ROTL, MVT::i8, 1 }, 2747 { ISD::ROTR, MVT::i32, 1 }, 2748 { ISD::ROTR, MVT::i16, 1 }, 2749 { ISD::ROTR, MVT::i8, 1 }, 2750 { ISD::FSHL, MVT::i32, 4 }, 2751 { ISD::FSHL, MVT::i16, 4 }, 2752 { ISD::FSHL, MVT::i8, 4 } 2753 }; 2754 2755 Intrinsic::ID IID = ICA.getID(); 2756 Type *RetTy = ICA.getReturnType(); 2757 const SmallVectorImpl<Value *> &Args = ICA.getArgs(); 2758 unsigned ISD = ISD::DELETED_NODE; 2759 switch (IID) { 2760 default: 2761 break; 2762 case Intrinsic::fshl: 2763 ISD = ISD::FSHL; 2764 if (Args[0] == Args[1]) 2765 ISD = ISD::ROTL; 2766 break; 2767 case Intrinsic::fshr: 2768 // FSHR has same costs so don't duplicate. 2769 ISD = ISD::FSHL; 2770 if (Args[0] == Args[1]) 2771 ISD = ISD::ROTR; 2772 break; 2773 } 2774 2775 if (ISD != ISD::DELETED_NODE) { 2776 // Legalize the type. 2777 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 2778 MVT MTy = LT.second; 2779 2780 // Attempt to lookup cost. 2781 if (ST->hasAVX512()) 2782 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2783 return LT.first * Entry->Cost; 2784 2785 if (ST->hasXOP()) 2786 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2787 return LT.first * Entry->Cost; 2788 2789 if (ST->is64Bit()) 2790 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2791 return LT.first * Entry->Cost; 2792 2793 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2794 return LT.first * Entry->Cost; 2795 } 2796 2797 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 2798 } 2799 2800 int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { 2801 static const CostTblEntry SLMCostTbl[] = { 2802 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 2803 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 2804 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 2805 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 2806 }; 2807 2808 assert(Val->isVectorTy() && "This must be a vector type"); 2809 Type *ScalarType = Val->getScalarType(); 2810 int RegisterFileMoveCost = 0; 2811 2812 if (Index != -1U && (Opcode == Instruction::ExtractElement || 2813 Opcode == Instruction::InsertElement)) { 2814 // Legalize the type. 2815 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 2816 2817 // This type is legalized to a scalar type. 2818 if (!LT.second.isVector()) 2819 return 0; 2820 2821 // The type may be split. Normalize the index to the new type. 2822 unsigned NumElts = LT.second.getVectorNumElements(); 2823 unsigned SubNumElts = NumElts; 2824 Index = Index % NumElts; 2825 2826 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 2827 // For inserts, we also need to insert the subvector back. 2828 if (LT.second.getSizeInBits() > 128) { 2829 assert((LT.second.getSizeInBits() % 128) == 0 && "Illegal vector"); 2830 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 2831 SubNumElts = NumElts / NumSubVecs; 2832 if (SubNumElts <= Index) { 2833 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 2834 Index %= SubNumElts; 2835 } 2836 } 2837 2838 if (Index == 0) { 2839 // Floating point scalars are already located in index #0. 2840 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 2841 // true for all. 2842 if (ScalarType->isFloatingPointTy()) 2843 return RegisterFileMoveCost; 2844 2845 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 2846 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 2847 return 1 + RegisterFileMoveCost; 2848 } 2849 2850 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2851 assert(ISD && "Unexpected vector opcode"); 2852 MVT MScalarTy = LT.second.getScalarType(); 2853 if (ST->isSLM()) 2854 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 2855 return Entry->Cost + RegisterFileMoveCost; 2856 2857 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 2858 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 2859 (MScalarTy.isInteger() && ST->hasSSE41())) 2860 return 1 + RegisterFileMoveCost; 2861 2862 // Assume insertps is relatively cheap on all targets. 2863 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 2864 Opcode == Instruction::InsertElement) 2865 return 1 + RegisterFileMoveCost; 2866 2867 // For extractions we just need to shuffle the element to index 0, which 2868 // should be very cheap (assume cost = 1). For insertions we need to shuffle 2869 // the elements to its destination. In both cases we must handle the 2870 // subvector move(s). 2871 // If the vector type is already less than 128-bits then don't reduce it. 2872 // TODO: Under what circumstances should we shuffle using the full width? 2873 int ShuffleCost = 1; 2874 if (Opcode == Instruction::InsertElement) { 2875 auto *SubTy = cast<VectorType>(Val); 2876 EVT VT = TLI->getValueType(DL, Val); 2877 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 2878 SubTy = VectorType::get(ScalarType, SubNumElts); 2879 ShuffleCost = getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, 0, SubTy); 2880 } 2881 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 2882 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 2883 } 2884 2885 // Add to the base cost if we know that the extracted element of a vector is 2886 // destined to be moved to and used in the integer register file. 2887 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 2888 RegisterFileMoveCost += 1; 2889 2890 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 2891 } 2892 2893 unsigned X86TTIImpl::getScalarizationOverhead(VectorType *Ty, 2894 const APInt &DemandedElts, 2895 bool Insert, bool Extract) { 2896 unsigned Cost = 0; 2897 2898 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much 2899 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT. 2900 if (Insert) { 2901 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 2902 MVT MScalarTy = LT.second.getScalarType(); 2903 2904 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 2905 (MScalarTy.isInteger() && ST->hasSSE41()) || 2906 (MScalarTy == MVT::f32 && ST->hasSSE41())) { 2907 // For types we can insert directly, insertion into 128-bit sub vectors is 2908 // cheap, followed by a cheap chain of concatenations. 2909 if (LT.second.getSizeInBits() <= 128) { 2910 Cost += 2911 BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, false); 2912 } else { 2913 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 2914 Cost += (PowerOf2Ceil(NumSubVecs) - 1) * LT.first; 2915 Cost += DemandedElts.countPopulation(); 2916 2917 // For vXf32 cases, insertion into the 0'th index in each v4f32 2918 // 128-bit vector is free. 2919 // NOTE: This assumes legalization widens vXf32 vectors. 2920 if (MScalarTy == MVT::f32) 2921 for (unsigned i = 0, e = Ty->getNumElements(); i < e; i += 4) 2922 if (DemandedElts[i]) 2923 Cost--; 2924 } 2925 } else if (LT.second.isVector()) { 2926 // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded 2927 // integer element as a SCALAR_TO_VECTOR, then we build the vector as a 2928 // series of UNPCK followed by CONCAT_VECTORS - all of these can be 2929 // considered cheap. 2930 if (Ty->isIntOrIntVectorTy()) 2931 Cost += DemandedElts.countPopulation(); 2932 2933 // Get the smaller of the legalized or original pow2-extended number of 2934 // vector elements, which represents the number of unpacks we'll end up 2935 // performing. 2936 unsigned NumElts = LT.second.getVectorNumElements(); 2937 unsigned Pow2Elts = PowerOf2Ceil(Ty->getNumElements()); 2938 Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first; 2939 } 2940 } 2941 2942 // TODO: Use default extraction for now, but we should investigate extending this 2943 // to handle repeated subvector extraction. 2944 if (Extract) 2945 Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, false, Extract); 2946 2947 return Cost; 2948 } 2949 2950 int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 2951 MaybeAlign Alignment, unsigned AddressSpace, 2952 TTI::TargetCostKind CostKind, 2953 const Instruction *I) { 2954 // Handle non-power-of-two vectors such as <3 x float> 2955 if (VectorType *VTy = dyn_cast<VectorType>(Src)) { 2956 unsigned NumElem = VTy->getNumElements(); 2957 2958 // Handle a few common cases: 2959 // <3 x float> 2960 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 2961 // Cost = 64 bit store + extract + 32 bit store. 2962 return 3; 2963 2964 // <3 x double> 2965 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 2966 // Cost = 128 bit store + unpack + 64 bit store. 2967 return 3; 2968 2969 // Assume that all other non-power-of-two numbers are scalarized. 2970 if (!isPowerOf2_32(NumElem)) { 2971 APInt DemandedElts = APInt::getAllOnesValue(NumElem); 2972 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment, 2973 AddressSpace, CostKind); 2974 int SplitCost = getScalarizationOverhead(VTy, DemandedElts, 2975 Opcode == Instruction::Load, 2976 Opcode == Instruction::Store); 2977 return NumElem * Cost + SplitCost; 2978 } 2979 } 2980 2981 // Legalize the type. 2982 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 2983 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 2984 "Invalid Opcode"); 2985 2986 // Each load/store unit costs 1. 2987 int Cost = LT.first * 1; 2988 2989 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a 2990 // proxy for a double-pumped AVX memory interface such as on Sandybridge. 2991 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow()) 2992 Cost *= 2; 2993 2994 return Cost; 2995 } 2996 2997 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, 2998 unsigned Alignment, 2999 unsigned AddressSpace, 3000 TTI::TargetCostKind CostKind) { 3001 bool IsLoad = (Instruction::Load == Opcode); 3002 bool IsStore = (Instruction::Store == Opcode); 3003 3004 VectorType *SrcVTy = dyn_cast<VectorType>(SrcTy); 3005 if (!SrcVTy) 3006 // To calculate scalar take the regular cost, without mask 3007 return getMemoryOpCost(Opcode, SrcTy, MaybeAlign(Alignment), AddressSpace, 3008 CostKind); 3009 3010 unsigned NumElem = SrcVTy->getNumElements(); 3011 VectorType *MaskTy = 3012 VectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 3013 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, MaybeAlign(Alignment))) || 3014 (IsStore && !isLegalMaskedStore(SrcVTy, MaybeAlign(Alignment))) || 3015 !isPowerOf2_32(NumElem)) { 3016 // Scalarization 3017 APInt DemandedElts = APInt::getAllOnesValue(NumElem); 3018 int MaskSplitCost = 3019 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 3020 int ScalarCompareCost = getCmpSelInstrCost( 3021 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr, 3022 CostKind); 3023 int BranchCost = getCFInstrCost(Instruction::Br, CostKind); 3024 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 3025 int ValueSplitCost = 3026 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore); 3027 int MemopCost = 3028 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3029 MaybeAlign(Alignment), AddressSpace, 3030 CostKind); 3031 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 3032 } 3033 3034 // Legalize the type. 3035 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3036 auto VT = TLI->getValueType(DL, SrcVTy); 3037 int Cost = 0; 3038 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 3039 LT.second.getVectorNumElements() == NumElem) 3040 // Promotion requires expand/truncate for data and a shuffle for mask. 3041 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, 0, nullptr) + 3042 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, 0, nullptr); 3043 3044 else if (LT.second.getVectorNumElements() > NumElem) { 3045 VectorType *NewMaskTy = VectorType::get(MaskTy->getElementType(), 3046 LT.second.getVectorNumElements()); 3047 // Expanding requires fill mask with zeroes 3048 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, 0, MaskTy); 3049 } 3050 3051 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 3052 if (!ST->hasAVX512()) 3053 return Cost + LT.first * (IsLoad ? 2 : 8); 3054 3055 // AVX-512 masked load/store is cheapper 3056 return Cost + LT.first; 3057 } 3058 3059 int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE, 3060 const SCEV *Ptr) { 3061 // Address computations in vectorized code with non-consecutive addresses will 3062 // likely result in more instructions compared to scalar code where the 3063 // computation can more often be merged into the index mode. The resulting 3064 // extra micro-ops can significantly decrease throughput. 3065 const unsigned NumVectorInstToHideOverhead = 10; 3066 3067 // Cost modeling of Strided Access Computation is hidden by the indexing 3068 // modes of X86 regardless of the stride value. We dont believe that there 3069 // is a difference between constant strided access in gerenal and constant 3070 // strided value which is less than or equal to 64. 3071 // Even in the case of (loop invariant) stride whose value is not known at 3072 // compile time, the address computation will not incur more than one extra 3073 // ADD instruction. 3074 if (Ty->isVectorTy() && SE) { 3075 if (!BaseT::isStridedAccess(Ptr)) 3076 return NumVectorInstToHideOverhead; 3077 if (!BaseT::getConstantStrideStep(SE, Ptr)) 3078 return 1; 3079 } 3080 3081 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 3082 } 3083 3084 int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 3085 bool IsPairwise, 3086 TTI::TargetCostKind CostKind) { 3087 // Just use the default implementation for pair reductions. 3088 if (IsPairwise) 3089 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise, CostKind); 3090 3091 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3092 // and make it as the cost. 3093 3094 static const CostTblEntry SLMCostTblNoPairWise[] = { 3095 { ISD::FADD, MVT::v2f64, 3 }, 3096 { ISD::ADD, MVT::v2i64, 5 }, 3097 }; 3098 3099 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3100 { ISD::FADD, MVT::v2f64, 2 }, 3101 { ISD::FADD, MVT::v4f32, 4 }, 3102 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 3103 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 3104 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 3105 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 3106 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 3107 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 3108 { ISD::ADD, MVT::v2i8, 2 }, 3109 { ISD::ADD, MVT::v4i8, 2 }, 3110 { ISD::ADD, MVT::v8i8, 2 }, 3111 { ISD::ADD, MVT::v16i8, 3 }, 3112 }; 3113 3114 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3115 { ISD::FADD, MVT::v4f64, 3 }, 3116 { ISD::FADD, MVT::v4f32, 3 }, 3117 { ISD::FADD, MVT::v8f32, 4 }, 3118 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 3119 { ISD::ADD, MVT::v4i64, 3 }, 3120 { ISD::ADD, MVT::v8i32, 5 }, 3121 { ISD::ADD, MVT::v16i16, 5 }, 3122 { ISD::ADD, MVT::v32i8, 4 }, 3123 }; 3124 3125 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3126 assert(ISD && "Invalid opcode"); 3127 3128 // Before legalizing the type, give a chance to look up illegal narrow types 3129 // in the table. 3130 // FIXME: Is there a better way to do this? 3131 EVT VT = TLI->getValueType(DL, ValTy); 3132 if (VT.isSimple()) { 3133 MVT MTy = VT.getSimpleVT(); 3134 if (ST->isSLM()) 3135 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3136 return Entry->Cost; 3137 3138 if (ST->hasAVX()) 3139 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3140 return Entry->Cost; 3141 3142 if (ST->hasSSE2()) 3143 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3144 return Entry->Cost; 3145 } 3146 3147 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3148 3149 MVT MTy = LT.second; 3150 3151 auto *ValVTy = cast<VectorType>(ValTy); 3152 3153 unsigned ArithmeticCost = 0; 3154 if (LT.first != 1 && MTy.isVector() && 3155 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3156 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3157 VectorType *SingleOpTy = 3158 VectorType::get(ValVTy->getElementType(), MTy.getVectorNumElements()); 3159 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3160 ArithmeticCost *= LT.first - 1; 3161 } 3162 3163 if (ST->isSLM()) 3164 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3165 return ArithmeticCost + Entry->Cost; 3166 3167 if (ST->hasAVX()) 3168 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3169 return ArithmeticCost + Entry->Cost; 3170 3171 if (ST->hasSSE2()) 3172 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3173 return ArithmeticCost + Entry->Cost; 3174 3175 // FIXME: These assume a naive kshift+binop lowering, which is probably 3176 // conservative in most cases. 3177 static const CostTblEntry AVX512BoolReduction[] = { 3178 { ISD::AND, MVT::v2i1, 3 }, 3179 { ISD::AND, MVT::v4i1, 5 }, 3180 { ISD::AND, MVT::v8i1, 7 }, 3181 { ISD::AND, MVT::v16i1, 9 }, 3182 { ISD::AND, MVT::v32i1, 11 }, 3183 { ISD::AND, MVT::v64i1, 13 }, 3184 { ISD::OR, MVT::v2i1, 3 }, 3185 { ISD::OR, MVT::v4i1, 5 }, 3186 { ISD::OR, MVT::v8i1, 7 }, 3187 { ISD::OR, MVT::v16i1, 9 }, 3188 { ISD::OR, MVT::v32i1, 11 }, 3189 { ISD::OR, MVT::v64i1, 13 }, 3190 }; 3191 3192 static const CostTblEntry AVX2BoolReduction[] = { 3193 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 3194 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 3195 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 3196 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 3197 }; 3198 3199 static const CostTblEntry AVX1BoolReduction[] = { 3200 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 3201 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 3202 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3203 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3204 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 3205 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 3206 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3207 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3208 }; 3209 3210 static const CostTblEntry SSE2BoolReduction[] = { 3211 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 3212 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 3213 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 3214 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 3215 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 3216 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 3217 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 3218 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 3219 }; 3220 3221 // Handle bool allof/anyof patterns. 3222 if (ValVTy->getElementType()->isIntegerTy(1)) { 3223 unsigned ArithmeticCost = 0; 3224 if (LT.first != 1 && MTy.isVector() && 3225 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3226 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3227 Type *SingleOpTy = 3228 VectorType::get(ValVTy->getElementType(), MTy.getVectorNumElements()); 3229 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3230 ArithmeticCost *= LT.first - 1; 3231 } 3232 3233 if (ST->hasAVX512()) 3234 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 3235 return ArithmeticCost + Entry->Cost; 3236 if (ST->hasAVX2()) 3237 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 3238 return ArithmeticCost + Entry->Cost; 3239 if (ST->hasAVX()) 3240 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 3241 return ArithmeticCost + Entry->Cost; 3242 if (ST->hasSSE2()) 3243 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 3244 return ArithmeticCost + Entry->Cost; 3245 3246 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise, 3247 CostKind); 3248 } 3249 3250 unsigned NumVecElts = ValVTy->getNumElements(); 3251 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 3252 3253 // Special case power of 2 reductions where the scalar type isn't changed 3254 // by type legalization. 3255 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 3256 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise, 3257 CostKind); 3258 3259 unsigned ReductionCost = 0; 3260 3261 auto *Ty = ValVTy; 3262 if (LT.first != 1 && MTy.isVector() && 3263 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3264 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3265 Ty = VectorType::get(ValVTy->getElementType(), MTy.getVectorNumElements()); 3266 ReductionCost = getArithmeticInstrCost(Opcode, Ty, CostKind); 3267 ReductionCost *= LT.first - 1; 3268 NumVecElts = MTy.getVectorNumElements(); 3269 } 3270 3271 // Now handle reduction with the legal type, taking into account size changes 3272 // at each level. 3273 while (NumVecElts > 1) { 3274 // Determine the size of the remaining vector we need to reduce. 3275 unsigned Size = NumVecElts * ScalarSize; 3276 NumVecElts /= 2; 3277 // If we're reducing from 256/512 bits, use an extract_subvector. 3278 if (Size > 128) { 3279 auto *SubTy = VectorType::get(ValVTy->getElementType(), NumVecElts); 3280 ReductionCost += 3281 getShuffleCost(TTI::SK_ExtractSubvector, Ty, NumVecElts, SubTy); 3282 Ty = SubTy; 3283 } else if (Size == 128) { 3284 // Reducing from 128 bits is a permute of v2f64/v2i64. 3285 VectorType *ShufTy; 3286 if (ValVTy->isFloatingPointTy()) 3287 ShufTy = VectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 3288 else 3289 ShufTy = VectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 3290 ReductionCost += 3291 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3292 } else if (Size == 64) { 3293 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3294 VectorType *ShufTy; 3295 if (ValVTy->isFloatingPointTy()) 3296 ShufTy = VectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 3297 else 3298 ShufTy = VectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 3299 ReductionCost += 3300 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3301 } else { 3302 // Reducing from smaller size is a shift by immediate. 3303 auto *ShiftTy = VectorType::get( 3304 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 3305 ReductionCost += getArithmeticInstrCost( 3306 Instruction::LShr, ShiftTy, CostKind, 3307 TargetTransformInfo::OK_AnyValue, 3308 TargetTransformInfo::OK_UniformConstantValue, 3309 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3310 } 3311 3312 // Add the arithmetic op for this level. 3313 ReductionCost += getArithmeticInstrCost(Opcode, Ty, CostKind); 3314 } 3315 3316 // Add the final extract element to the cost. 3317 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3318 } 3319 3320 int X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, bool IsUnsigned) { 3321 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3322 3323 MVT MTy = LT.second; 3324 3325 int ISD; 3326 if (Ty->isIntOrIntVectorTy()) { 3327 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3328 } else { 3329 assert(Ty->isFPOrFPVectorTy() && 3330 "Expected float point or integer vector type."); 3331 ISD = ISD::FMINNUM; 3332 } 3333 3334 static const CostTblEntry SSE1CostTbl[] = { 3335 {ISD::FMINNUM, MVT::v4f32, 1}, 3336 }; 3337 3338 static const CostTblEntry SSE2CostTbl[] = { 3339 {ISD::FMINNUM, MVT::v2f64, 1}, 3340 {ISD::SMIN, MVT::v8i16, 1}, 3341 {ISD::UMIN, MVT::v16i8, 1}, 3342 }; 3343 3344 static const CostTblEntry SSE41CostTbl[] = { 3345 {ISD::SMIN, MVT::v4i32, 1}, 3346 {ISD::UMIN, MVT::v4i32, 1}, 3347 {ISD::UMIN, MVT::v8i16, 1}, 3348 {ISD::SMIN, MVT::v16i8, 1}, 3349 }; 3350 3351 static const CostTblEntry SSE42CostTbl[] = { 3352 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 3353 }; 3354 3355 static const CostTblEntry AVX1CostTbl[] = { 3356 {ISD::FMINNUM, MVT::v8f32, 1}, 3357 {ISD::FMINNUM, MVT::v4f64, 1}, 3358 {ISD::SMIN, MVT::v8i32, 3}, 3359 {ISD::UMIN, MVT::v8i32, 3}, 3360 {ISD::SMIN, MVT::v16i16, 3}, 3361 {ISD::UMIN, MVT::v16i16, 3}, 3362 {ISD::SMIN, MVT::v32i8, 3}, 3363 {ISD::UMIN, MVT::v32i8, 3}, 3364 }; 3365 3366 static const CostTblEntry AVX2CostTbl[] = { 3367 {ISD::SMIN, MVT::v8i32, 1}, 3368 {ISD::UMIN, MVT::v8i32, 1}, 3369 {ISD::SMIN, MVT::v16i16, 1}, 3370 {ISD::UMIN, MVT::v16i16, 1}, 3371 {ISD::SMIN, MVT::v32i8, 1}, 3372 {ISD::UMIN, MVT::v32i8, 1}, 3373 }; 3374 3375 static const CostTblEntry AVX512CostTbl[] = { 3376 {ISD::FMINNUM, MVT::v16f32, 1}, 3377 {ISD::FMINNUM, MVT::v8f64, 1}, 3378 {ISD::SMIN, MVT::v2i64, 1}, 3379 {ISD::UMIN, MVT::v2i64, 1}, 3380 {ISD::SMIN, MVT::v4i64, 1}, 3381 {ISD::UMIN, MVT::v4i64, 1}, 3382 {ISD::SMIN, MVT::v8i64, 1}, 3383 {ISD::UMIN, MVT::v8i64, 1}, 3384 {ISD::SMIN, MVT::v16i32, 1}, 3385 {ISD::UMIN, MVT::v16i32, 1}, 3386 }; 3387 3388 static const CostTblEntry AVX512BWCostTbl[] = { 3389 {ISD::SMIN, MVT::v32i16, 1}, 3390 {ISD::UMIN, MVT::v32i16, 1}, 3391 {ISD::SMIN, MVT::v64i8, 1}, 3392 {ISD::UMIN, MVT::v64i8, 1}, 3393 }; 3394 3395 // If we have a native MIN/MAX instruction for this type, use it. 3396 if (ST->hasBWI()) 3397 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3398 return LT.first * Entry->Cost; 3399 3400 if (ST->hasAVX512()) 3401 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3402 return LT.first * Entry->Cost; 3403 3404 if (ST->hasAVX2()) 3405 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3406 return LT.first * Entry->Cost; 3407 3408 if (ST->hasAVX()) 3409 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3410 return LT.first * Entry->Cost; 3411 3412 if (ST->hasSSE42()) 3413 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3414 return LT.first * Entry->Cost; 3415 3416 if (ST->hasSSE41()) 3417 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3418 return LT.first * Entry->Cost; 3419 3420 if (ST->hasSSE2()) 3421 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3422 return LT.first * Entry->Cost; 3423 3424 if (ST->hasSSE1()) 3425 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3426 return LT.first * Entry->Cost; 3427 3428 unsigned CmpOpcode; 3429 if (Ty->isFPOrFPVectorTy()) { 3430 CmpOpcode = Instruction::FCmp; 3431 } else { 3432 assert(Ty->isIntOrIntVectorTy() && 3433 "expecting floating point or integer type for min/max reduction"); 3434 CmpOpcode = Instruction::ICmp; 3435 } 3436 3437 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 3438 // Otherwise fall back to cmp+select. 3439 return getCmpSelInstrCost(CmpOpcode, Ty, CondTy, CostKind) + 3440 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, CostKind); 3441 } 3442 3443 int X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 3444 bool IsPairwise, bool IsUnsigned, 3445 TTI::TargetCostKind CostKind) { 3446 // Just use the default implementation for pair reductions. 3447 if (IsPairwise) 3448 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned, 3449 CostKind); 3450 3451 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3452 3453 MVT MTy = LT.second; 3454 3455 int ISD; 3456 if (ValTy->isIntOrIntVectorTy()) { 3457 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3458 } else { 3459 assert(ValTy->isFPOrFPVectorTy() && 3460 "Expected float point or integer vector type."); 3461 ISD = ISD::FMINNUM; 3462 } 3463 3464 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3465 // and make it as the cost. 3466 3467 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3468 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 3469 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 3470 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 3471 }; 3472 3473 static const CostTblEntry SSE41CostTblNoPairWise[] = { 3474 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 3475 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 3476 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 3477 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 3478 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 3479 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 3480 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 3481 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 3482 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 3483 {ISD::SMIN, MVT::v16i8, 6}, 3484 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 3485 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 3486 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 3487 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 3488 }; 3489 3490 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3491 {ISD::SMIN, MVT::v16i16, 6}, 3492 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 3493 {ISD::SMIN, MVT::v32i8, 8}, 3494 {ISD::UMIN, MVT::v32i8, 8}, 3495 }; 3496 3497 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 3498 {ISD::SMIN, MVT::v32i16, 8}, 3499 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 3500 {ISD::SMIN, MVT::v64i8, 10}, 3501 {ISD::UMIN, MVT::v64i8, 10}, 3502 }; 3503 3504 // Before legalizing the type, give a chance to look up illegal narrow types 3505 // in the table. 3506 // FIXME: Is there a better way to do this? 3507 EVT VT = TLI->getValueType(DL, ValTy); 3508 if (VT.isSimple()) { 3509 MVT MTy = VT.getSimpleVT(); 3510 if (ST->hasBWI()) 3511 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3512 return Entry->Cost; 3513 3514 if (ST->hasAVX()) 3515 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3516 return Entry->Cost; 3517 3518 if (ST->hasSSE41()) 3519 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3520 return Entry->Cost; 3521 3522 if (ST->hasSSE2()) 3523 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3524 return Entry->Cost; 3525 } 3526 3527 auto *ValVTy = cast<VectorType>(ValTy); 3528 unsigned NumVecElts = ValVTy->getNumElements(); 3529 3530 auto *Ty = ValVTy; 3531 unsigned MinMaxCost = 0; 3532 if (LT.first != 1 && MTy.isVector() && 3533 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3534 // Type needs to be split. We need LT.first - 1 operations ops. 3535 Ty = VectorType::get(ValVTy->getElementType(), MTy.getVectorNumElements()); 3536 auto *SubCondTy = VectorType::get( 3537 cast<VectorType>(CondTy)->getElementType(), MTy.getVectorNumElements()); 3538 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3539 MinMaxCost *= LT.first - 1; 3540 NumVecElts = MTy.getVectorNumElements(); 3541 } 3542 3543 if (ST->hasBWI()) 3544 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3545 return MinMaxCost + Entry->Cost; 3546 3547 if (ST->hasAVX()) 3548 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3549 return MinMaxCost + Entry->Cost; 3550 3551 if (ST->hasSSE41()) 3552 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3553 return MinMaxCost + Entry->Cost; 3554 3555 if (ST->hasSSE2()) 3556 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3557 return MinMaxCost + Entry->Cost; 3558 3559 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 3560 3561 // Special case power of 2 reductions where the scalar type isn't changed 3562 // by type legalization. 3563 if (!isPowerOf2_32(ValVTy->getNumElements()) || 3564 ScalarSize != MTy.getScalarSizeInBits()) 3565 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned, 3566 CostKind); 3567 3568 // Now handle reduction with the legal type, taking into account size changes 3569 // at each level. 3570 while (NumVecElts > 1) { 3571 // Determine the size of the remaining vector we need to reduce. 3572 unsigned Size = NumVecElts * ScalarSize; 3573 NumVecElts /= 2; 3574 // If we're reducing from 256/512 bits, use an extract_subvector. 3575 if (Size > 128) { 3576 auto *SubTy = VectorType::get(ValVTy->getElementType(), NumVecElts); 3577 MinMaxCost += 3578 getShuffleCost(TTI::SK_ExtractSubvector, Ty, NumVecElts, SubTy); 3579 Ty = SubTy; 3580 } else if (Size == 128) { 3581 // Reducing from 128 bits is a permute of v2f64/v2i64. 3582 VectorType *ShufTy; 3583 if (ValTy->isFloatingPointTy()) 3584 ShufTy = VectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 3585 else 3586 ShufTy = VectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 3587 MinMaxCost += 3588 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3589 } else if (Size == 64) { 3590 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3591 VectorType *ShufTy; 3592 if (ValTy->isFloatingPointTy()) 3593 ShufTy = VectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 3594 else 3595 ShufTy = VectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 3596 MinMaxCost += 3597 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, 0, nullptr); 3598 } else { 3599 // Reducing from smaller size is a shift by immediate. 3600 VectorType *ShiftTy = VectorType::get( 3601 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 3602 MinMaxCost += getArithmeticInstrCost( 3603 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, 3604 TargetTransformInfo::OK_AnyValue, 3605 TargetTransformInfo::OK_UniformConstantValue, 3606 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3607 } 3608 3609 // Add the arithmetic op for this level. 3610 auto *SubCondTy = VectorType::get(CondTy->getElementType(), 3611 Ty->getNumElements()); 3612 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3613 } 3614 3615 // Add the final extract element to the cost. 3616 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3617 } 3618 3619 /// Calculate the cost of materializing a 64-bit value. This helper 3620 /// method might only calculate a fraction of a larger immediate. Therefore it 3621 /// is valid to return a cost of ZERO. 3622 int X86TTIImpl::getIntImmCost(int64_t Val) { 3623 if (Val == 0) 3624 return TTI::TCC_Free; 3625 3626 if (isInt<32>(Val)) 3627 return TTI::TCC_Basic; 3628 3629 return 2 * TTI::TCC_Basic; 3630 } 3631 3632 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 3633 TTI::TargetCostKind CostKind) { 3634 assert(Ty->isIntegerTy()); 3635 3636 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3637 if (BitSize == 0) 3638 return ~0U; 3639 3640 // Never hoist constants larger than 128bit, because this might lead to 3641 // incorrect code generation or assertions in codegen. 3642 // Fixme: Create a cost model for types larger than i128 once the codegen 3643 // issues have been fixed. 3644 if (BitSize > 128) 3645 return TTI::TCC_Free; 3646 3647 if (Imm == 0) 3648 return TTI::TCC_Free; 3649 3650 // Sign-extend all constants to a multiple of 64-bit. 3651 APInt ImmVal = Imm; 3652 if (BitSize % 64 != 0) 3653 ImmVal = Imm.sext(alignTo(BitSize, 64)); 3654 3655 // Split the constant into 64-bit chunks and calculate the cost for each 3656 // chunk. 3657 int Cost = 0; 3658 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 3659 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 3660 int64_t Val = Tmp.getSExtValue(); 3661 Cost += getIntImmCost(Val); 3662 } 3663 // We need at least one instruction to materialize the constant. 3664 return std::max(1, Cost); 3665 } 3666 3667 int X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, 3668 Type *Ty, TTI::TargetCostKind CostKind) { 3669 assert(Ty->isIntegerTy()); 3670 3671 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3672 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3673 // here, so that constant hoisting will ignore this constant. 3674 if (BitSize == 0) 3675 return TTI::TCC_Free; 3676 3677 unsigned ImmIdx = ~0U; 3678 switch (Opcode) { 3679 default: 3680 return TTI::TCC_Free; 3681 case Instruction::GetElementPtr: 3682 // Always hoist the base address of a GetElementPtr. This prevents the 3683 // creation of new constants for every base constant that gets constant 3684 // folded with the offset. 3685 if (Idx == 0) 3686 return 2 * TTI::TCC_Basic; 3687 return TTI::TCC_Free; 3688 case Instruction::Store: 3689 ImmIdx = 0; 3690 break; 3691 case Instruction::ICmp: 3692 // This is an imperfect hack to prevent constant hoisting of 3693 // compares that might be trying to check if a 64-bit value fits in 3694 // 32-bits. The backend can optimize these cases using a right shift by 32. 3695 // Ideally we would check the compare predicate here. There also other 3696 // similar immediates the backend can use shifts for. 3697 if (Idx == 1 && Imm.getBitWidth() == 64) { 3698 uint64_t ImmVal = Imm.getZExtValue(); 3699 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 3700 return TTI::TCC_Free; 3701 } 3702 ImmIdx = 1; 3703 break; 3704 case Instruction::And: 3705 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 3706 // by using a 32-bit operation with implicit zero extension. Detect such 3707 // immediates here as the normal path expects bit 31 to be sign extended. 3708 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 3709 return TTI::TCC_Free; 3710 ImmIdx = 1; 3711 break; 3712 case Instruction::Add: 3713 case Instruction::Sub: 3714 // For add/sub, we can use the opposite instruction for INT32_MIN. 3715 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 3716 return TTI::TCC_Free; 3717 ImmIdx = 1; 3718 break; 3719 case Instruction::UDiv: 3720 case Instruction::SDiv: 3721 case Instruction::URem: 3722 case Instruction::SRem: 3723 // Division by constant is typically expanded later into a different 3724 // instruction sequence. This completely changes the constants. 3725 // Report them as "free" to stop ConstantHoist from marking them as opaque. 3726 return TTI::TCC_Free; 3727 case Instruction::Mul: 3728 case Instruction::Or: 3729 case Instruction::Xor: 3730 ImmIdx = 1; 3731 break; 3732 // Always return TCC_Free for the shift value of a shift instruction. 3733 case Instruction::Shl: 3734 case Instruction::LShr: 3735 case Instruction::AShr: 3736 if (Idx == 1) 3737 return TTI::TCC_Free; 3738 break; 3739 case Instruction::Trunc: 3740 case Instruction::ZExt: 3741 case Instruction::SExt: 3742 case Instruction::IntToPtr: 3743 case Instruction::PtrToInt: 3744 case Instruction::BitCast: 3745 case Instruction::PHI: 3746 case Instruction::Call: 3747 case Instruction::Select: 3748 case Instruction::Ret: 3749 case Instruction::Load: 3750 break; 3751 } 3752 3753 if (Idx == ImmIdx) { 3754 int NumConstants = divideCeil(BitSize, 64); 3755 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 3756 return (Cost <= NumConstants * TTI::TCC_Basic) 3757 ? static_cast<int>(TTI::TCC_Free) 3758 : Cost; 3759 } 3760 3761 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 3762 } 3763 3764 int X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 3765 const APInt &Imm, Type *Ty, 3766 TTI::TargetCostKind CostKind) { 3767 assert(Ty->isIntegerTy()); 3768 3769 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3770 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3771 // here, so that constant hoisting will ignore this constant. 3772 if (BitSize == 0) 3773 return TTI::TCC_Free; 3774 3775 switch (IID) { 3776 default: 3777 return TTI::TCC_Free; 3778 case Intrinsic::sadd_with_overflow: 3779 case Intrinsic::uadd_with_overflow: 3780 case Intrinsic::ssub_with_overflow: 3781 case Intrinsic::usub_with_overflow: 3782 case Intrinsic::smul_with_overflow: 3783 case Intrinsic::umul_with_overflow: 3784 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 3785 return TTI::TCC_Free; 3786 break; 3787 case Intrinsic::experimental_stackmap: 3788 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 3789 return TTI::TCC_Free; 3790 break; 3791 case Intrinsic::experimental_patchpoint_void: 3792 case Intrinsic::experimental_patchpoint_i64: 3793 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 3794 return TTI::TCC_Free; 3795 break; 3796 } 3797 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 3798 } 3799 3800 unsigned 3801 X86TTIImpl::getUserCost(const User *U, ArrayRef<const Value *> Operands, 3802 TTI::TargetCostKind CostKind) { 3803 if (isa<StoreInst>(U)) { 3804 Value *Ptr = U->getOperand(1); 3805 // Store instruction with index and scale costs 2 Uops. 3806 // Check the preceding GEP to identify non-const indices. 3807 if (auto GEP = dyn_cast<GetElementPtrInst>(Ptr)) { 3808 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3809 return TTI::TCC_Basic * 2; 3810 } 3811 return TTI::TCC_Basic; 3812 } 3813 return BaseT::getUserCost(U, Operands, CostKind); 3814 } 3815 3816 // Return an average cost of Gather / Scatter instruction, maybe improved later 3817 int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, Value *Ptr, 3818 unsigned Alignment, unsigned AddressSpace) { 3819 3820 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 3821 unsigned VF = cast<VectorType>(SrcVTy)->getNumElements(); 3822 3823 // Try to reduce index size from 64 bit (default for GEP) 3824 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 3825 // operation will use 16 x 64 indices which do not fit in a zmm and needs 3826 // to split. Also check that the base pointer is the same for all lanes, 3827 // and that there's at most one variable index. 3828 auto getIndexSizeInBits = [](Value *Ptr, const DataLayout& DL) { 3829 unsigned IndexSize = DL.getPointerSizeInBits(); 3830 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 3831 if (IndexSize < 64 || !GEP) 3832 return IndexSize; 3833 3834 unsigned NumOfVarIndices = 0; 3835 Value *Ptrs = GEP->getPointerOperand(); 3836 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 3837 return IndexSize; 3838 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 3839 if (isa<Constant>(GEP->getOperand(i))) 3840 continue; 3841 Type *IndxTy = GEP->getOperand(i)->getType(); 3842 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 3843 IndxTy = IndexVTy->getElementType(); 3844 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 3845 !isa<SExtInst>(GEP->getOperand(i))) || 3846 ++NumOfVarIndices > 1) 3847 return IndexSize; // 64 3848 } 3849 return (unsigned)32; 3850 }; 3851 3852 3853 // Trying to reduce IndexSize to 32 bits for vector 16. 3854 // By default the IndexSize is equal to pointer size. 3855 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 3856 ? getIndexSizeInBits(Ptr, DL) 3857 : DL.getPointerSizeInBits(); 3858 3859 Type *IndexVTy = VectorType::get(IntegerType::get(SrcVTy->getContext(), 3860 IndexSize), VF); 3861 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy); 3862 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3863 int SplitFactor = std::max(IdxsLT.first, SrcLT.first); 3864 if (SplitFactor > 1) { 3865 // Handle splitting of vector of pointers 3866 Type *SplitSrcTy = VectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 3867 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 3868 AddressSpace); 3869 } 3870 3871 // The gather / scatter cost is given by Intel architects. It is a rough 3872 // number since we are looking at one instruction in a time. 3873 const int GSOverhead = (Opcode == Instruction::Load) 3874 ? ST->getGatherOverhead() 3875 : ST->getScatterOverhead(); 3876 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3877 MaybeAlign(Alignment), AddressSpace, 3878 TTI::TCK_RecipThroughput); 3879 } 3880 3881 /// Return the cost of full scalarization of gather / scatter operation. 3882 /// 3883 /// Opcode - Load or Store instruction. 3884 /// SrcVTy - The type of the data vector that should be gathered or scattered. 3885 /// VariableMask - The mask is non-constant at compile time. 3886 /// Alignment - Alignment for one element. 3887 /// AddressSpace - pointer[s] address space. 3888 /// 3889 int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 3890 bool VariableMask, unsigned Alignment, 3891 unsigned AddressSpace) { 3892 unsigned VF = cast<VectorType>(SrcVTy)->getNumElements(); 3893 APInt DemandedElts = APInt::getAllOnesValue(VF); 3894 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 3895 3896 int MaskUnpackCost = 0; 3897 if (VariableMask) { 3898 VectorType *MaskTy = 3899 VectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 3900 MaskUnpackCost = 3901 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 3902 int ScalarCompareCost = 3903 getCmpSelInstrCost(Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), 3904 nullptr, CostKind); 3905 int BranchCost = getCFInstrCost(Instruction::Br, CostKind); 3906 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 3907 } 3908 3909 // The cost of the scalar loads/stores. 3910 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3911 MaybeAlign(Alignment), AddressSpace, 3912 CostKind); 3913 3914 int InsertExtractCost = 0; 3915 if (Opcode == Instruction::Load) 3916 for (unsigned i = 0; i < VF; ++i) 3917 // Add the cost of inserting each scalar load into the vector 3918 InsertExtractCost += 3919 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 3920 else 3921 for (unsigned i = 0; i < VF; ++i) 3922 // Add the cost of extracting each element out of the data vector 3923 InsertExtractCost += 3924 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 3925 3926 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 3927 } 3928 3929 /// Calculate the cost of Gather / Scatter operation 3930 int X86TTIImpl::getGatherScatterOpCost( 3931 unsigned Opcode, Type *SrcVTy, Value *Ptr, bool VariableMask, 3932 unsigned Alignment, TTI::TargetCostKind CostKind, 3933 const Instruction *I = nullptr) { 3934 3935 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 3936 unsigned VF = cast<VectorType>(SrcVTy)->getNumElements(); 3937 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 3938 if (!PtrTy && Ptr->getType()->isVectorTy()) 3939 PtrTy = dyn_cast<PointerType>( 3940 cast<VectorType>(Ptr->getType())->getElementType()); 3941 assert(PtrTy && "Unexpected type for Ptr argument"); 3942 unsigned AddressSpace = PtrTy->getAddressSpace(); 3943 3944 bool Scalarize = false; 3945 if ((Opcode == Instruction::Load && 3946 !isLegalMaskedGather(SrcVTy, MaybeAlign(Alignment))) || 3947 (Opcode == Instruction::Store && 3948 !isLegalMaskedScatter(SrcVTy, MaybeAlign(Alignment)))) 3949 Scalarize = true; 3950 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 3951 // Vector-4 of gather/scatter instruction does not exist on KNL. 3952 // We can extend it to 8 elements, but zeroing upper bits of 3953 // the mask vector will add more instructions. Right now we give the scalar 3954 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 3955 // is better in the VariableMask case. 3956 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 3957 Scalarize = true; 3958 3959 if (Scalarize) 3960 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 3961 AddressSpace); 3962 3963 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 3964 } 3965 3966 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 3967 TargetTransformInfo::LSRCost &C2) { 3968 // X86 specific here are "instruction number 1st priority". 3969 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 3970 C1.NumIVMuls, C1.NumBaseAdds, 3971 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 3972 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 3973 C2.NumIVMuls, C2.NumBaseAdds, 3974 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 3975 } 3976 3977 bool X86TTIImpl::canMacroFuseCmp() { 3978 return ST->hasMacroFusion() || ST->hasBranchFusion(); 3979 } 3980 3981 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, MaybeAlign Alignment) { 3982 if (!ST->hasAVX()) 3983 return false; 3984 3985 // The backend can't handle a single element vector. 3986 if (isa<VectorType>(DataTy) && 3987 cast<VectorType>(DataTy)->getNumElements() == 1) 3988 return false; 3989 Type *ScalarTy = DataTy->getScalarType(); 3990 3991 if (ScalarTy->isPointerTy()) 3992 return true; 3993 3994 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 3995 return true; 3996 3997 if (!ScalarTy->isIntegerTy()) 3998 return false; 3999 4000 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4001 return IntWidth == 32 || IntWidth == 64 || 4002 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 4003 } 4004 4005 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, MaybeAlign Alignment) { 4006 return isLegalMaskedLoad(DataType, Alignment); 4007 } 4008 4009 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 4010 unsigned DataSize = DL.getTypeStoreSize(DataType); 4011 // The only supported nontemporal loads are for aligned vectors of 16 or 32 4012 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 4013 // (the equivalent stores only require AVX). 4014 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 4015 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 4016 4017 return false; 4018 } 4019 4020 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 4021 unsigned DataSize = DL.getTypeStoreSize(DataType); 4022 4023 // SSE4A supports nontemporal stores of float and double at arbitrary 4024 // alignment. 4025 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 4026 return true; 4027 4028 // Besides the SSE4A subtarget exception above, only aligned stores are 4029 // available nontemporaly on any other subtarget. And only stores with a size 4030 // of 4..32 bytes (powers of 2, only) are permitted. 4031 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 4032 !isPowerOf2_32(DataSize)) 4033 return false; 4034 4035 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 4036 // loads require AVX2). 4037 if (DataSize == 32) 4038 return ST->hasAVX(); 4039 else if (DataSize == 16) 4040 return ST->hasSSE1(); 4041 return true; 4042 } 4043 4044 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 4045 if (!isa<VectorType>(DataTy)) 4046 return false; 4047 4048 if (!ST->hasAVX512()) 4049 return false; 4050 4051 // The backend can't handle a single element vector. 4052 if (cast<VectorType>(DataTy)->getNumElements() == 1) 4053 return false; 4054 4055 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 4056 4057 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4058 return true; 4059 4060 if (!ScalarTy->isIntegerTy()) 4061 return false; 4062 4063 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4064 return IntWidth == 32 || IntWidth == 64 || 4065 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 4066 } 4067 4068 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 4069 return isLegalMaskedExpandLoad(DataTy); 4070 } 4071 4072 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, MaybeAlign Alignment) { 4073 // Some CPUs have better gather performance than others. 4074 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 4075 // enable gather with a -march. 4076 if (!(ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()))) 4077 return false; 4078 4079 // This function is called now in two cases: from the Loop Vectorizer 4080 // and from the Scalarizer. 4081 // When the Loop Vectorizer asks about legality of the feature, 4082 // the vectorization factor is not calculated yet. The Loop Vectorizer 4083 // sends a scalar type and the decision is based on the width of the 4084 // scalar element. 4085 // Later on, the cost model will estimate usage this intrinsic based on 4086 // the vector type. 4087 // The Scalarizer asks again about legality. It sends a vector type. 4088 // In this case we can reject non-power-of-2 vectors. 4089 // We also reject single element vectors as the type legalizer can't 4090 // scalarize it. 4091 if (auto *DataVTy = dyn_cast<VectorType>(DataTy)) { 4092 unsigned NumElts = DataVTy->getNumElements(); 4093 if (NumElts == 1 || !isPowerOf2_32(NumElts)) 4094 return false; 4095 } 4096 Type *ScalarTy = DataTy->getScalarType(); 4097 if (ScalarTy->isPointerTy()) 4098 return true; 4099 4100 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4101 return true; 4102 4103 if (!ScalarTy->isIntegerTy()) 4104 return false; 4105 4106 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4107 return IntWidth == 32 || IntWidth == 64; 4108 } 4109 4110 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, MaybeAlign Alignment) { 4111 // AVX2 doesn't support scatter 4112 if (!ST->hasAVX512()) 4113 return false; 4114 return isLegalMaskedGather(DataType, Alignment); 4115 } 4116 4117 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 4118 EVT VT = TLI->getValueType(DL, DataType); 4119 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 4120 } 4121 4122 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 4123 return false; 4124 } 4125 4126 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 4127 const Function *Callee) const { 4128 const TargetMachine &TM = getTLI()->getTargetMachine(); 4129 4130 // Work this as a subsetting of subtarget features. 4131 const FeatureBitset &CallerBits = 4132 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 4133 const FeatureBitset &CalleeBits = 4134 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 4135 4136 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 4137 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 4138 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 4139 } 4140 4141 bool X86TTIImpl::areFunctionArgsABICompatible( 4142 const Function *Caller, const Function *Callee, 4143 SmallPtrSetImpl<Argument *> &Args) const { 4144 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args)) 4145 return false; 4146 4147 // If we get here, we know the target features match. If one function 4148 // considers 512-bit vectors legal and the other does not, consider them 4149 // incompatible. 4150 const TargetMachine &TM = getTLI()->getTargetMachine(); 4151 4152 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 4153 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs()) 4154 return true; 4155 4156 // Consider the arguments compatible if they aren't vectors or aggregates. 4157 // FIXME: Look at the size of vectors. 4158 // FIXME: Look at the element types of aggregates to see if there are vectors. 4159 // FIXME: The API of this function seems intended to allow arguments 4160 // to be removed from the set, but the caller doesn't check if the set 4161 // becomes empty so that may not work in practice. 4162 return llvm::none_of(Args, [](Argument *A) { 4163 auto *EltTy = cast<PointerType>(A->getType())->getElementType(); 4164 return EltTy->isVectorTy() || EltTy->isAggregateType(); 4165 }); 4166 } 4167 4168 X86TTIImpl::TTI::MemCmpExpansionOptions 4169 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 4170 TTI::MemCmpExpansionOptions Options; 4171 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 4172 Options.NumLoadsPerBlock = 2; 4173 // All GPR and vector loads can be unaligned. 4174 Options.AllowOverlappingLoads = true; 4175 if (IsZeroCmp) { 4176 // Only enable vector loads for equality comparison. Right now the vector 4177 // version is not as fast for three way compare (see #33329). 4178 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 4179 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 4180 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 4181 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 4182 } 4183 if (ST->is64Bit()) { 4184 Options.LoadSizes.push_back(8); 4185 } 4186 Options.LoadSizes.push_back(4); 4187 Options.LoadSizes.push_back(2); 4188 Options.LoadSizes.push_back(1); 4189 return Options; 4190 } 4191 4192 bool X86TTIImpl::enableInterleavedAccessVectorization() { 4193 // TODO: We expect this to be beneficial regardless of arch, 4194 // but there are currently some unexplained performance artifacts on Atom. 4195 // As a temporary solution, disable on Atom. 4196 return !(ST->isAtom()); 4197 } 4198 4199 // Get estimation for interleaved load/store operations for AVX2. 4200 // \p Factor is the interleaved-access factor (stride) - number of 4201 // (interleaved) elements in the group. 4202 // \p Indices contains the indices for a strided load: when the 4203 // interleaved load has gaps they indicate which elements are used. 4204 // If Indices is empty (or if the number of indices is equal to the size 4205 // of the interleaved-access as given in \p Factor) the access has no gaps. 4206 // 4207 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 4208 // computing the cost using a generic formula as a function of generic 4209 // shuffles. We therefore use a lookup table instead, filled according to 4210 // the instruction sequences that codegen currently generates. 4211 int X86TTIImpl::getInterleavedMemoryOpCostAVX2(unsigned Opcode, Type *VecTy, 4212 unsigned Factor, 4213 ArrayRef<unsigned> Indices, 4214 unsigned Alignment, 4215 unsigned AddressSpace, 4216 TTI::TargetCostKind CostKind, 4217 bool UseMaskForCond, 4218 bool UseMaskForGaps) { 4219 4220 if (UseMaskForCond || UseMaskForGaps) 4221 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4222 Alignment, AddressSpace, CostKind, 4223 UseMaskForCond, UseMaskForGaps); 4224 4225 // We currently Support only fully-interleaved groups, with no gaps. 4226 // TODO: Support also strided loads (interleaved-groups with gaps). 4227 if (Indices.size() && Indices.size() != Factor) 4228 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4229 Alignment, AddressSpace, 4230 CostKind); 4231 4232 // VecTy for interleave memop is <VF*Factor x Elt>. 4233 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4234 // VecTy = <12 x i32>. 4235 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4236 4237 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 4238 // the VF=2, while v2i128 is an unsupported MVT vector type 4239 // (see MachineValueType.h::getVectorVT()). 4240 if (!LegalVT.isVector()) 4241 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4242 Alignment, AddressSpace, 4243 CostKind); 4244 4245 unsigned VF = cast<VectorType>(VecTy)->getNumElements() / Factor; 4246 Type *ScalarTy = cast<VectorType>(VecTy)->getElementType(); 4247 4248 // Calculate the number of memory operations (NumOfMemOps), required 4249 // for load/store the VecTy. 4250 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4251 unsigned LegalVTSize = LegalVT.getStoreSize(); 4252 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4253 4254 // Get the cost of one memory operation. 4255 Type *SingleMemOpTy = 4256 VectorType::get(cast<VectorType>(VecTy)->getElementType(), 4257 LegalVT.getVectorNumElements()); 4258 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 4259 MaybeAlign(Alignment), AddressSpace, 4260 CostKind); 4261 4262 VectorType *VT = VectorType::get(ScalarTy, VF); 4263 EVT ETy = TLI->getValueType(DL, VT); 4264 if (!ETy.isSimple()) 4265 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4266 Alignment, AddressSpace, 4267 CostKind); 4268 4269 // TODO: Complete for other data-types and strides. 4270 // Each combination of Stride, ElementTy and VF results in a different 4271 // sequence; The cost tables are therefore accessed with: 4272 // Factor (stride) and VectorType=VFxElemType. 4273 // The Cost accounts only for the shuffle sequence; 4274 // The cost of the loads/stores is accounted for separately. 4275 // 4276 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 4277 { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64 4278 { 2, MVT::v4f64, 6 }, //(load 8f64 and) deinterleave into 2 x 4f64 4279 4280 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8 4281 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8 4282 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8 4283 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8 4284 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8 4285 { 3, MVT::v8f32, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32 4286 4287 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8 4288 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8 4289 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8 4290 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8 4291 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8 4292 4293 { 8, MVT::v8f32, 40 } //(load 64f32 and)deinterleave into 8 x 8f32 4294 }; 4295 4296 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 4297 { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store) 4298 { 2, MVT::v4f64, 6 }, //interleave into 2 x 4f64 into 8f64 (and store) 4299 4300 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store) 4301 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store) 4302 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store) 4303 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store) 4304 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store) 4305 4306 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store) 4307 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store) 4308 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store) 4309 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store) 4310 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store) 4311 }; 4312 4313 if (Opcode == Instruction::Load) { 4314 if (const auto *Entry = 4315 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 4316 return NumOfMemOps * MemOpCost + Entry->Cost; 4317 } else { 4318 assert(Opcode == Instruction::Store && 4319 "Expected Store Instruction at this point"); 4320 if (const auto *Entry = 4321 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 4322 return NumOfMemOps * MemOpCost + Entry->Cost; 4323 } 4324 4325 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4326 Alignment, AddressSpace, CostKind); 4327 } 4328 4329 // Get estimation for interleaved load/store operations and strided load. 4330 // \p Indices contains indices for strided load. 4331 // \p Factor - the factor of interleaving. 4332 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 4333 int X86TTIImpl::getInterleavedMemoryOpCostAVX512(unsigned Opcode, Type *VecTy, 4334 unsigned Factor, 4335 ArrayRef<unsigned> Indices, 4336 unsigned Alignment, 4337 unsigned AddressSpace, 4338 TTI::TargetCostKind CostKind, 4339 bool UseMaskForCond, 4340 bool UseMaskForGaps) { 4341 4342 if (UseMaskForCond || UseMaskForGaps) 4343 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4344 Alignment, AddressSpace, CostKind, 4345 UseMaskForCond, UseMaskForGaps); 4346 4347 // VecTy for interleave memop is <VF*Factor x Elt>. 4348 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4349 // VecTy = <12 x i32>. 4350 4351 // Calculate the number of memory operations (NumOfMemOps), required 4352 // for load/store the VecTy. 4353 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4354 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4355 unsigned LegalVTSize = LegalVT.getStoreSize(); 4356 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4357 4358 // Get the cost of one memory operation. 4359 auto *SingleMemOpTy = 4360 VectorType::get(cast<VectorType>(VecTy)->getElementType(), 4361 LegalVT.getVectorNumElements()); 4362 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 4363 MaybeAlign(Alignment), AddressSpace, 4364 CostKind); 4365 4366 unsigned VF = cast<VectorType>(VecTy)->getNumElements() / Factor; 4367 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 4368 4369 if (Opcode == Instruction::Load) { 4370 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 4371 // contain the cost of the optimized shuffle sequence that the 4372 // X86InterleavedAccess pass will generate. 4373 // The cost of loads and stores are computed separately from the table. 4374 4375 // X86InterleavedAccess support only the following interleaved-access group. 4376 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 4377 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 4378 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 4379 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 4380 }; 4381 4382 if (const auto *Entry = 4383 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 4384 return NumOfMemOps * MemOpCost + Entry->Cost; 4385 //If an entry does not exist, fallback to the default implementation. 4386 4387 // Kind of shuffle depends on number of loaded values. 4388 // If we load the entire data in one register, we can use a 1-src shuffle. 4389 // Otherwise, we'll merge 2 sources in each operation. 4390 TTI::ShuffleKind ShuffleKind = 4391 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 4392 4393 unsigned ShuffleCost = 4394 getShuffleCost(ShuffleKind, SingleMemOpTy, 0, nullptr); 4395 4396 unsigned NumOfLoadsInInterleaveGrp = 4397 Indices.size() ? Indices.size() : Factor; 4398 Type *ResultTy = 4399 VectorType::get(cast<VectorType>(VecTy)->getElementType(), 4400 cast<VectorType>(VecTy)->getNumElements() / Factor); 4401 unsigned NumOfResults = 4402 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 4403 NumOfLoadsInInterleaveGrp; 4404 4405 // About a half of the loads may be folded in shuffles when we have only 4406 // one result. If we have more than one result, we do not fold loads at all. 4407 unsigned NumOfUnfoldedLoads = 4408 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 4409 4410 // Get a number of shuffle operations per result. 4411 unsigned NumOfShufflesPerResult = 4412 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 4413 4414 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4415 // When we have more than one destination, we need additional instructions 4416 // to keep sources. 4417 unsigned NumOfMoves = 0; 4418 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 4419 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 4420 4421 int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 4422 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 4423 4424 return Cost; 4425 } 4426 4427 // Store. 4428 assert(Opcode == Instruction::Store && 4429 "Expected Store Instruction at this point"); 4430 // X86InterleavedAccess support only the following interleaved-access group. 4431 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 4432 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 4433 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 4434 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 4435 4436 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 4437 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 4438 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 4439 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 4440 }; 4441 4442 if (const auto *Entry = 4443 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 4444 return NumOfMemOps * MemOpCost + Entry->Cost; 4445 //If an entry does not exist, fallback to the default implementation. 4446 4447 // There is no strided stores meanwhile. And store can't be folded in 4448 // shuffle. 4449 unsigned NumOfSources = Factor; // The number of values to be merged. 4450 unsigned ShuffleCost = 4451 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, 0, nullptr); 4452 unsigned NumOfShufflesPerStore = NumOfSources - 1; 4453 4454 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4455 // We need additional instructions to keep sources. 4456 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 4457 int Cost = NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 4458 NumOfMoves; 4459 return Cost; 4460 } 4461 4462 int X86TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, 4463 unsigned Factor, 4464 ArrayRef<unsigned> Indices, 4465 unsigned Alignment, 4466 unsigned AddressSpace, 4467 TTI::TargetCostKind CostKind, 4468 bool UseMaskForCond, 4469 bool UseMaskForGaps) { 4470 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 4471 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 4472 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 4473 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 4474 return true; 4475 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 4476 return HasBW; 4477 return false; 4478 }; 4479 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 4480 return getInterleavedMemoryOpCostAVX512(Opcode, VecTy, Factor, Indices, 4481 Alignment, AddressSpace, CostKind, 4482 UseMaskForCond, UseMaskForGaps); 4483 if (ST->hasAVX2()) 4484 return getInterleavedMemoryOpCostAVX2(Opcode, VecTy, Factor, Indices, 4485 Alignment, AddressSpace, CostKind, 4486 UseMaskForCond, UseMaskForGaps); 4487 4488 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4489 Alignment, AddressSpace, CostKind, 4490 UseMaskForCond, UseMaskForGaps); 4491 } 4492