1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // X86 cost model. 56 // 57 //===----------------------------------------------------------------------===// 58 59 TargetTransformInfo::PopcntSupportKind 60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 61 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 62 // TODO: Currently the __builtin_popcount() implementation using SSE3 63 // instructions is inefficient. Once the problem is fixed, we should 64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 66 } 67 68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 69 TargetTransformInfo::CacheLevel Level) const { 70 switch (Level) { 71 case TargetTransformInfo::CacheLevel::L1D: 72 // - Penryn 73 // - Nehalem 74 // - Westmere 75 // - Sandy Bridge 76 // - Ivy Bridge 77 // - Haswell 78 // - Broadwell 79 // - Skylake 80 // - Kabylake 81 return 32 * 1024; // 32 KByte 82 case TargetTransformInfo::CacheLevel::L2D: 83 // - Penryn 84 // - Nehalem 85 // - Westmere 86 // - Sandy Bridge 87 // - Ivy Bridge 88 // - Haswell 89 // - Broadwell 90 // - Skylake 91 // - Kabylake 92 return 256 * 1024; // 256 KByte 93 } 94 95 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 96 } 97 98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 99 TargetTransformInfo::CacheLevel Level) const { 100 // - Penryn 101 // - Nehalem 102 // - Westmere 103 // - Sandy Bridge 104 // - Ivy Bridge 105 // - Haswell 106 // - Broadwell 107 // - Skylake 108 // - Kabylake 109 switch (Level) { 110 case TargetTransformInfo::CacheLevel::L1D: 111 LLVM_FALLTHROUGH; 112 case TargetTransformInfo::CacheLevel::L2D: 113 return 8; 114 } 115 116 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 117 } 118 119 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 120 bool Vector = (ClassID == 1); 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 TypeSize 133 X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { 134 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 135 switch (K) { 136 case TargetTransformInfo::RGK_Scalar: 137 return TypeSize::getFixed(ST->is64Bit() ? 64 : 32); 138 case TargetTransformInfo::RGK_FixedWidthVector: 139 if (ST->hasAVX512() && PreferVectorWidth >= 512) 140 return TypeSize::getFixed(512); 141 if (ST->hasAVX() && PreferVectorWidth >= 256) 142 return TypeSize::getFixed(256); 143 if (ST->hasSSE1() && PreferVectorWidth >= 128) 144 return TypeSize::getFixed(128); 145 return TypeSize::getFixed(0); 146 case TargetTransformInfo::RGK_ScalableVector: 147 return TypeSize::getScalable(0); 148 } 149 150 llvm_unreachable("Unsupported register kind"); 151 } 152 153 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 154 return getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector) 155 .getFixedSize(); 156 } 157 158 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 159 // If the loop will not be vectorized, don't interleave the loop. 160 // Let regular unroll to unroll the loop, which saves the overflow 161 // check and memory check cost. 162 if (VF == 1) 163 return 1; 164 165 if (ST->isAtom()) 166 return 1; 167 168 // Sandybridge and Haswell have multiple execution ports and pipelined 169 // vector units. 170 if (ST->hasAVX()) 171 return 4; 172 173 return 2; 174 } 175 176 InstructionCost X86TTIImpl::getArithmeticInstrCost( 177 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, 178 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 179 TTI::OperandValueProperties Opd1PropInfo, 180 TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, 181 const Instruction *CxtI) { 182 // TODO: Handle more cost kinds. 183 if (CostKind != TTI::TCK_RecipThroughput) 184 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, 185 Op2Info, Opd1PropInfo, 186 Opd2PropInfo, Args, CxtI); 187 188 // vXi8 multiplications are always promoted to vXi16. 189 if (Opcode == Instruction::Mul && Ty->isVectorTy() && 190 Ty->getScalarSizeInBits() == 8) { 191 Type *WideVecTy = 192 VectorType::getExtendedElementVectorType(cast<VectorType>(Ty)); 193 return getCastInstrCost(Instruction::ZExt, WideVecTy, Ty, 194 TargetTransformInfo::CastContextHint::None, 195 CostKind) + 196 getCastInstrCost(Instruction::Trunc, Ty, WideVecTy, 197 TargetTransformInfo::CastContextHint::None, 198 CostKind) + 199 getArithmeticInstrCost(Opcode, WideVecTy, CostKind, Op1Info, Op2Info, 200 Opd1PropInfo, Opd2PropInfo); 201 } 202 203 // Legalize the type. 204 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 205 206 int ISD = TLI->InstructionOpcodeToISD(Opcode); 207 assert(ISD && "Invalid opcode"); 208 209 static const CostTblEntry GLMCostTable[] = { 210 { ISD::FDIV, MVT::f32, 18 }, // divss 211 { ISD::FDIV, MVT::v4f32, 35 }, // divps 212 { ISD::FDIV, MVT::f64, 33 }, // divsd 213 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 214 }; 215 216 if (ST->useGLMDivSqrtCosts()) 217 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 218 LT.second)) 219 return LT.first * Entry->Cost; 220 221 static const CostTblEntry SLMCostTable[] = { 222 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 223 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 224 { ISD::FMUL, MVT::f64, 2 }, // mulsd 225 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 226 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 227 { ISD::FDIV, MVT::f32, 17 }, // divss 228 { ISD::FDIV, MVT::v4f32, 39 }, // divps 229 { ISD::FDIV, MVT::f64, 32 }, // divsd 230 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 231 { ISD::FADD, MVT::v2f64, 2 }, // addpd 232 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 233 // v2i64/v4i64 mul is custom lowered as a series of long: 234 // multiplies(3), shifts(3) and adds(2) 235 // slm muldq version throughput is 2 and addq throughput 4 236 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 237 // 3X4 (addq throughput) = 17 238 { ISD::MUL, MVT::v2i64, 17 }, 239 // slm addq\subq throughput is 4 240 { ISD::ADD, MVT::v2i64, 4 }, 241 { ISD::SUB, MVT::v2i64, 4 }, 242 }; 243 244 if (ST->isSLM()) { 245 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 246 // Check if the operands can be shrinked into a smaller datatype. 247 bool Op1Signed = false; 248 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 249 bool Op2Signed = false; 250 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 251 252 bool SignedMode = Op1Signed || Op2Signed; 253 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 254 255 if (OpMinSize <= 7) 256 return LT.first * 3; // pmullw/sext 257 if (!SignedMode && OpMinSize <= 8) 258 return LT.first * 3; // pmullw/zext 259 if (OpMinSize <= 15) 260 return LT.first * 5; // pmullw/pmulhw/pshuf 261 if (!SignedMode && OpMinSize <= 16) 262 return LT.first * 5; // pmullw/pmulhw/pshuf 263 } 264 265 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 266 LT.second)) { 267 return LT.first * Entry->Cost; 268 } 269 } 270 271 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 272 ISD == ISD::UREM) && 273 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 274 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 275 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 276 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 277 // On X86, vector signed division by constants power-of-two are 278 // normally expanded to the sequence SRA + SRL + ADD + SRA. 279 // The OperandValue properties may not be the same as that of the previous 280 // operation; conservatively assume OP_None. 281 InstructionCost Cost = 282 2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Op1Info, 283 Op2Info, TargetTransformInfo::OP_None, 284 TargetTransformInfo::OP_None); 285 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 286 Op2Info, 287 TargetTransformInfo::OP_None, 288 TargetTransformInfo::OP_None); 289 Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind, Op1Info, 290 Op2Info, 291 TargetTransformInfo::OP_None, 292 TargetTransformInfo::OP_None); 293 294 if (ISD == ISD::SREM) { 295 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 296 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info, 297 Op2Info); 298 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info, 299 Op2Info); 300 } 301 302 return Cost; 303 } 304 305 // Vector unsigned division/remainder will be simplified to shifts/masks. 306 if (ISD == ISD::UDIV) 307 return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, 308 Op1Info, Op2Info, 309 TargetTransformInfo::OP_None, 310 TargetTransformInfo::OP_None); 311 312 else // UREM 313 return getArithmeticInstrCost(Instruction::And, Ty, CostKind, 314 Op1Info, Op2Info, 315 TargetTransformInfo::OP_None, 316 TargetTransformInfo::OP_None); 317 } 318 319 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 320 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 321 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 322 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 323 }; 324 325 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 326 ST->hasBWI()) { 327 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 328 LT.second)) 329 return LT.first * Entry->Cost; 330 } 331 332 static const CostTblEntry AVX512UniformConstCostTable[] = { 333 { ISD::SRA, MVT::v2i64, 1 }, 334 { ISD::SRA, MVT::v4i64, 1 }, 335 { ISD::SRA, MVT::v8i64, 1 }, 336 337 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 338 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 339 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 340 341 { ISD::SDIV, MVT::v16i32, 6 }, // pmuludq sequence 342 { ISD::SREM, MVT::v16i32, 8 }, // pmuludq+mul+sub sequence 343 { ISD::UDIV, MVT::v16i32, 5 }, // pmuludq sequence 344 { ISD::UREM, MVT::v16i32, 7 }, // pmuludq+mul+sub sequence 345 }; 346 347 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 348 ST->hasAVX512()) { 349 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 350 LT.second)) 351 return LT.first * Entry->Cost; 352 } 353 354 static const CostTblEntry AVX2UniformConstCostTable[] = { 355 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 356 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 357 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 358 359 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 360 361 { ISD::SDIV, MVT::v8i32, 6 }, // pmuludq sequence 362 { ISD::SREM, MVT::v8i32, 8 }, // pmuludq+mul+sub sequence 363 { ISD::UDIV, MVT::v8i32, 5 }, // pmuludq sequence 364 { ISD::UREM, MVT::v8i32, 7 }, // pmuludq+mul+sub sequence 365 }; 366 367 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 368 ST->hasAVX2()) { 369 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 370 LT.second)) 371 return LT.first * Entry->Cost; 372 } 373 374 static const CostTblEntry SSE2UniformConstCostTable[] = { 375 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 376 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 377 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 378 379 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 380 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 381 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 382 383 { ISD::SDIV, MVT::v8i32, 12+2 }, // 2*pmuludq sequence + split. 384 { ISD::SREM, MVT::v8i32, 16+2 }, // 2*pmuludq+mul+sub sequence + split. 385 { ISD::SDIV, MVT::v4i32, 6 }, // pmuludq sequence 386 { ISD::SREM, MVT::v4i32, 8 }, // pmuludq+mul+sub sequence 387 { ISD::UDIV, MVT::v8i32, 10+2 }, // 2*pmuludq sequence + split. 388 { ISD::UREM, MVT::v8i32, 14+2 }, // 2*pmuludq+mul+sub sequence + split. 389 { ISD::UDIV, MVT::v4i32, 5 }, // pmuludq sequence 390 { ISD::UREM, MVT::v4i32, 7 }, // pmuludq+mul+sub sequence 391 }; 392 393 // XOP has faster vXi8 shifts. 394 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 395 ST->hasSSE2() && !ST->hasXOP()) { 396 if (const auto *Entry = 397 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 398 return LT.first * Entry->Cost; 399 } 400 401 static const CostTblEntry AVX512BWConstCostTable[] = { 402 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 403 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 404 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 405 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 406 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 407 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 408 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 409 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 410 }; 411 412 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 413 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 414 ST->hasBWI()) { 415 if (const auto *Entry = 416 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 417 return LT.first * Entry->Cost; 418 } 419 420 static const CostTblEntry AVX512ConstCostTable[] = { 421 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 422 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 423 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 424 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 425 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 426 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 427 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 428 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 429 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 430 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 431 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 432 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 433 }; 434 435 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 436 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 437 ST->hasAVX512()) { 438 if (const auto *Entry = 439 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 440 return LT.first * Entry->Cost; 441 } 442 443 static const CostTblEntry AVX2ConstCostTable[] = { 444 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 445 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 446 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 447 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 448 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 449 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 450 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 451 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 452 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 453 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 454 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 455 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 456 }; 457 458 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 459 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 460 ST->hasAVX2()) { 461 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 462 return LT.first * Entry->Cost; 463 } 464 465 static const CostTblEntry SSE2ConstCostTable[] = { 466 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 467 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 468 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 469 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 470 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 471 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 472 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 473 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 474 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 475 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 476 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 477 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 478 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 479 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 480 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 481 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 482 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 483 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 484 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 485 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 486 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 487 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 488 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 489 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 490 }; 491 492 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 493 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 494 ST->hasSSE2()) { 495 // pmuldq sequence. 496 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 497 return LT.first * 32; 498 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 499 return LT.first * 38; 500 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 501 return LT.first * 15; 502 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 503 return LT.first * 20; 504 505 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 506 return LT.first * Entry->Cost; 507 } 508 509 static const CostTblEntry AVX512BWShiftCostTable[] = { 510 { ISD::SHL, MVT::v16i8, 4 }, // extend/vpsllvw/pack sequence. 511 { ISD::SRL, MVT::v16i8, 4 }, // extend/vpsrlvw/pack sequence. 512 { ISD::SRA, MVT::v16i8, 4 }, // extend/vpsravw/pack sequence. 513 { ISD::SHL, MVT::v32i8, 4 }, // extend/vpsllvw/pack sequence. 514 { ISD::SRL, MVT::v32i8, 4 }, // extend/vpsrlvw/pack sequence. 515 { ISD::SRA, MVT::v32i8, 6 }, // extend/vpsravw/pack sequence. 516 { ISD::SHL, MVT::v64i8, 6 }, // extend/vpsllvw/pack sequence. 517 { ISD::SRL, MVT::v64i8, 7 }, // extend/vpsrlvw/pack sequence. 518 { ISD::SRA, MVT::v64i8, 15 }, // extend/vpsravw/pack sequence. 519 520 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 521 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 522 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 523 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 524 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 525 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 526 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 527 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 528 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 529 }; 530 531 if (ST->hasBWI()) 532 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 533 return LT.first * Entry->Cost; 534 535 static const CostTblEntry AVX2UniformCostTable[] = { 536 // Uniform splats are cheaper for the following instructions. 537 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 538 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 539 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 540 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 541 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 542 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 543 544 { ISD::SHL, MVT::v8i32, 1 }, // pslld 545 { ISD::SRL, MVT::v8i32, 1 }, // psrld 546 { ISD::SRA, MVT::v8i32, 1 }, // psrad 547 { ISD::SHL, MVT::v4i64, 1 }, // psllq 548 { ISD::SRL, MVT::v4i64, 1 }, // psrlq 549 }; 550 551 if (ST->hasAVX2() && 552 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 553 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 554 if (const auto *Entry = 555 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 556 return LT.first * Entry->Cost; 557 } 558 559 static const CostTblEntry SSE2UniformCostTable[] = { 560 // Uniform splats are cheaper for the following instructions. 561 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 562 { ISD::SHL, MVT::v4i32, 1 }, // pslld 563 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 564 565 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 566 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 567 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 568 569 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 570 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 571 }; 572 573 if (ST->hasSSE2() && 574 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 575 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 576 if (const auto *Entry = 577 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 578 return LT.first * Entry->Cost; 579 } 580 581 static const CostTblEntry AVX512DQCostTable[] = { 582 { ISD::MUL, MVT::v2i64, 2 }, // pmullq 583 { ISD::MUL, MVT::v4i64, 2 }, // pmullq 584 { ISD::MUL, MVT::v8i64, 2 } // pmullq 585 }; 586 587 // Look for AVX512DQ lowering tricks for custom cases. 588 if (ST->hasDQI()) 589 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 590 return LT.first * Entry->Cost; 591 592 static const CostTblEntry AVX512BWCostTable[] = { 593 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 594 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 595 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 596 }; 597 598 // Look for AVX512BW lowering tricks for custom cases. 599 if (ST->hasBWI()) 600 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 601 return LT.first * Entry->Cost; 602 603 static const CostTblEntry AVX512CostTable[] = { 604 { ISD::SHL, MVT::v4i32, 1 }, 605 { ISD::SRL, MVT::v4i32, 1 }, 606 { ISD::SRA, MVT::v4i32, 1 }, 607 { ISD::SHL, MVT::v8i32, 1 }, 608 { ISD::SRL, MVT::v8i32, 1 }, 609 { ISD::SRA, MVT::v8i32, 1 }, 610 { ISD::SHL, MVT::v16i32, 1 }, 611 { ISD::SRL, MVT::v16i32, 1 }, 612 { ISD::SRA, MVT::v16i32, 1 }, 613 614 { ISD::SHL, MVT::v2i64, 1 }, 615 { ISD::SRL, MVT::v2i64, 1 }, 616 { ISD::SHL, MVT::v4i64, 1 }, 617 { ISD::SRL, MVT::v4i64, 1 }, 618 { ISD::SHL, MVT::v8i64, 1 }, 619 { ISD::SRL, MVT::v8i64, 1 }, 620 621 { ISD::SRA, MVT::v2i64, 1 }, 622 { ISD::SRA, MVT::v4i64, 1 }, 623 { ISD::SRA, MVT::v8i64, 1 }, 624 625 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 626 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 627 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 628 { ISD::MUL, MVT::v8i64, 6 }, // 3*pmuludq/3*shift/2*add 629 630 { ISD::FNEG, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 631 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 632 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 633 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 634 { ISD::FDIV, MVT::f64, 4 }, // Skylake from http://www.agner.org/ 635 { ISD::FDIV, MVT::v2f64, 4 }, // Skylake from http://www.agner.org/ 636 { ISD::FDIV, MVT::v4f64, 8 }, // Skylake from http://www.agner.org/ 637 { ISD::FDIV, MVT::v8f64, 16 }, // Skylake from http://www.agner.org/ 638 639 { ISD::FNEG, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 640 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 641 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 642 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 643 { ISD::FDIV, MVT::f32, 3 }, // Skylake from http://www.agner.org/ 644 { ISD::FDIV, MVT::v4f32, 3 }, // Skylake from http://www.agner.org/ 645 { ISD::FDIV, MVT::v8f32, 5 }, // Skylake from http://www.agner.org/ 646 { ISD::FDIV, MVT::v16f32, 10 }, // Skylake from http://www.agner.org/ 647 }; 648 649 if (ST->hasAVX512()) 650 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 651 return LT.first * Entry->Cost; 652 653 static const CostTblEntry AVX2ShiftCostTable[] = { 654 // Shifts on vXi64/vXi32 on AVX2 is legal even though we declare to 655 // customize them to detect the cases where shift amount is a scalar one. 656 { ISD::SHL, MVT::v4i32, 2 }, // vpsllvd (Haswell from agner.org) 657 { ISD::SRL, MVT::v4i32, 2 }, // vpsrlvd (Haswell from agner.org) 658 { ISD::SRA, MVT::v4i32, 2 }, // vpsravd (Haswell from agner.org) 659 { ISD::SHL, MVT::v8i32, 2 }, // vpsllvd (Haswell from agner.org) 660 { ISD::SRL, MVT::v8i32, 2 }, // vpsrlvd (Haswell from agner.org) 661 { ISD::SRA, MVT::v8i32, 2 }, // vpsravd (Haswell from agner.org) 662 { ISD::SHL, MVT::v2i64, 1 }, // vpsllvq (Haswell from agner.org) 663 { ISD::SRL, MVT::v2i64, 1 }, // vpsrlvq (Haswell from agner.org) 664 { ISD::SHL, MVT::v4i64, 1 }, // vpsllvq (Haswell from agner.org) 665 { ISD::SRL, MVT::v4i64, 1 }, // vpsrlvq (Haswell from agner.org) 666 }; 667 668 if (ST->hasAVX512()) { 669 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 670 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 671 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 672 // On AVX512, a packed v32i16 shift left by a constant build_vector 673 // is lowered into a vector multiply (vpmullw). 674 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 675 Op1Info, Op2Info, 676 TargetTransformInfo::OP_None, 677 TargetTransformInfo::OP_None); 678 } 679 680 // Look for AVX2 lowering tricks (XOP is always better at v4i32 shifts). 681 if (ST->hasAVX2() && !(ST->hasXOP() && LT.second == MVT::v4i32)) { 682 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 683 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 684 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 685 // On AVX2, a packed v16i16 shift left by a constant build_vector 686 // is lowered into a vector multiply (vpmullw). 687 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 688 Op1Info, Op2Info, 689 TargetTransformInfo::OP_None, 690 TargetTransformInfo::OP_None); 691 692 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 693 return LT.first * Entry->Cost; 694 } 695 696 static const CostTblEntry XOPShiftCostTable[] = { 697 // 128bit shifts take 1cy, but right shifts require negation beforehand. 698 { ISD::SHL, MVT::v16i8, 1 }, 699 { ISD::SRL, MVT::v16i8, 2 }, 700 { ISD::SRA, MVT::v16i8, 2 }, 701 { ISD::SHL, MVT::v8i16, 1 }, 702 { ISD::SRL, MVT::v8i16, 2 }, 703 { ISD::SRA, MVT::v8i16, 2 }, 704 { ISD::SHL, MVT::v4i32, 1 }, 705 { ISD::SRL, MVT::v4i32, 2 }, 706 { ISD::SRA, MVT::v4i32, 2 }, 707 { ISD::SHL, MVT::v2i64, 1 }, 708 { ISD::SRL, MVT::v2i64, 2 }, 709 { ISD::SRA, MVT::v2i64, 2 }, 710 // 256bit shifts require splitting if AVX2 didn't catch them above. 711 { ISD::SHL, MVT::v32i8, 2+2 }, 712 { ISD::SRL, MVT::v32i8, 4+2 }, 713 { ISD::SRA, MVT::v32i8, 4+2 }, 714 { ISD::SHL, MVT::v16i16, 2+2 }, 715 { ISD::SRL, MVT::v16i16, 4+2 }, 716 { ISD::SRA, MVT::v16i16, 4+2 }, 717 { ISD::SHL, MVT::v8i32, 2+2 }, 718 { ISD::SRL, MVT::v8i32, 4+2 }, 719 { ISD::SRA, MVT::v8i32, 4+2 }, 720 { ISD::SHL, MVT::v4i64, 2+2 }, 721 { ISD::SRL, MVT::v4i64, 4+2 }, 722 { ISD::SRA, MVT::v4i64, 4+2 }, 723 }; 724 725 // Look for XOP lowering tricks. 726 if (ST->hasXOP()) { 727 // If the right shift is constant then we'll fold the negation so 728 // it's as cheap as a left shift. 729 int ShiftISD = ISD; 730 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 731 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 732 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 733 ShiftISD = ISD::SHL; 734 if (const auto *Entry = 735 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 736 return LT.first * Entry->Cost; 737 } 738 739 static const CostTblEntry SSE2UniformShiftCostTable[] = { 740 // Uniform splats are cheaper for the following instructions. 741 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 742 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 743 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 744 745 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 746 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 747 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 748 749 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 750 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 751 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 752 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 753 }; 754 755 if (ST->hasSSE2() && 756 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 757 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 758 759 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 760 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 761 return LT.first * 4; // 2*psrad + shuffle. 762 763 if (const auto *Entry = 764 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 765 return LT.first * Entry->Cost; 766 } 767 768 if (ISD == ISD::SHL && 769 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 770 MVT VT = LT.second; 771 // Vector shift left by non uniform constant can be lowered 772 // into vector multiply. 773 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 774 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 775 ISD = ISD::MUL; 776 } 777 778 static const CostTblEntry AVX2CostTable[] = { 779 { ISD::SHL, MVT::v16i8, 6 }, // vpblendvb sequence. 780 { ISD::SHL, MVT::v32i8, 6 }, // vpblendvb sequence. 781 { ISD::SHL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 782 { ISD::SHL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 783 { ISD::SHL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 784 { ISD::SHL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 785 786 { ISD::SRL, MVT::v16i8, 6 }, // vpblendvb sequence. 787 { ISD::SRL, MVT::v32i8, 6 }, // vpblendvb sequence. 788 { ISD::SRL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 789 { ISD::SRL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 790 { ISD::SRL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 791 { ISD::SRL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 792 793 { ISD::SRA, MVT::v16i8, 17 }, // vpblendvb sequence. 794 { ISD::SRA, MVT::v32i8, 17 }, // vpblendvb sequence. 795 { ISD::SRA, MVT::v64i8, 34 }, // 2*vpblendvb sequence. 796 { ISD::SRA, MVT::v8i16, 5 }, // extend/vpsravd/pack sequence. 797 { ISD::SRA, MVT::v16i16, 7 }, // extend/vpsravd/pack sequence. 798 { ISD::SRA, MVT::v32i16, 14 }, // 2*extend/vpsravd/pack sequence. 799 { ISD::SRA, MVT::v2i64, 2 }, // srl/xor/sub sequence. 800 { ISD::SRA, MVT::v4i64, 2 }, // srl/xor/sub sequence. 801 802 { ISD::SUB, MVT::v32i8, 1 }, // psubb 803 { ISD::ADD, MVT::v32i8, 1 }, // paddb 804 { ISD::SUB, MVT::v16i16, 1 }, // psubw 805 { ISD::ADD, MVT::v16i16, 1 }, // paddw 806 { ISD::SUB, MVT::v8i32, 1 }, // psubd 807 { ISD::ADD, MVT::v8i32, 1 }, // paddd 808 { ISD::SUB, MVT::v4i64, 1 }, // psubq 809 { ISD::ADD, MVT::v4i64, 1 }, // paddq 810 811 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 812 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 813 { ISD::MUL, MVT::v4i64, 6 }, // 3*pmuludq/3*shift/2*add 814 815 { ISD::FNEG, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 816 { ISD::FNEG, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 817 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 818 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 819 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 820 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 821 { ISD::FMUL, MVT::f64, 1 }, // Haswell from http://www.agner.org/ 822 { ISD::FMUL, MVT::v2f64, 1 }, // Haswell from http://www.agner.org/ 823 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 824 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 825 826 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 827 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 828 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 829 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 830 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 831 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 832 }; 833 834 // Look for AVX2 lowering tricks for custom cases. 835 if (ST->hasAVX2()) 836 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 837 return LT.first * Entry->Cost; 838 839 static const CostTblEntry AVX1CostTable[] = { 840 // We don't have to scalarize unsupported ops. We can issue two half-sized 841 // operations and we only need to extract the upper YMM half. 842 // Two ops + 1 extract + 1 insert = 4. 843 { ISD::MUL, MVT::v16i16, 4 }, 844 { ISD::MUL, MVT::v8i32, 5 }, // BTVER2 from http://www.agner.org/ 845 { ISD::MUL, MVT::v4i64, 12 }, 846 847 { ISD::SUB, MVT::v32i8, 4 }, 848 { ISD::ADD, MVT::v32i8, 4 }, 849 { ISD::SUB, MVT::v16i16, 4 }, 850 { ISD::ADD, MVT::v16i16, 4 }, 851 { ISD::SUB, MVT::v8i32, 4 }, 852 { ISD::ADD, MVT::v8i32, 4 }, 853 { ISD::SUB, MVT::v4i64, 4 }, 854 { ISD::ADD, MVT::v4i64, 4 }, 855 856 { ISD::SHL, MVT::v16i8, 10 }, // pblendvb sequence . 857 { ISD::SHL, MVT::v32i8, 22 }, // pblendvb sequence + split. 858 { ISD::SHL, MVT::v8i16, 6 }, // pblendvb sequence. 859 { ISD::SHL, MVT::v16i16, 13 }, // pblendvb sequence + split. 860 { ISD::SHL, MVT::v4i32, 3 }, // pslld/paddd/cvttps2dq/pmulld 861 { ISD::SHL, MVT::v8i32, 9 }, // pslld/paddd/cvttps2dq/pmulld + split 862 { ISD::SHL, MVT::v2i64, 2 }, // Shift each lane + blend. 863 { ISD::SHL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 864 865 { ISD::SRL, MVT::v16i8, 11 }, // pblendvb sequence. 866 { ISD::SRL, MVT::v32i8, 23 }, // pblendvb sequence + split. 867 { ISD::SRL, MVT::v8i16, 13 }, // pblendvb sequence. 868 { ISD::SRL, MVT::v16i16, 28 }, // pblendvb sequence + split. 869 { ISD::SRL, MVT::v4i32, 6 }, // Shift each lane + blend. 870 { ISD::SRL, MVT::v8i32, 14 }, // Shift each lane + blend + split. 871 { ISD::SRL, MVT::v2i64, 2 }, // Shift each lane + blend. 872 { ISD::SRL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 873 874 { ISD::SRA, MVT::v16i8, 21 }, // pblendvb sequence. 875 { ISD::SRA, MVT::v32i8, 44 }, // pblendvb sequence + split. 876 { ISD::SRA, MVT::v8i16, 13 }, // pblendvb sequence. 877 { ISD::SRA, MVT::v16i16, 28 }, // pblendvb sequence + split. 878 { ISD::SRA, MVT::v4i32, 6 }, // Shift each lane + blend. 879 { ISD::SRA, MVT::v8i32, 14 }, // Shift each lane + blend + split. 880 { ISD::SRA, MVT::v2i64, 5 }, // Shift each lane + blend. 881 { ISD::SRA, MVT::v4i64, 12 }, // Shift each lane + blend + split. 882 883 { ISD::FNEG, MVT::v4f64, 2 }, // BTVER2 from http://www.agner.org/ 884 { ISD::FNEG, MVT::v8f32, 2 }, // BTVER2 from http://www.agner.org/ 885 886 { ISD::FMUL, MVT::f64, 2 }, // BTVER2 from http://www.agner.org/ 887 { ISD::FMUL, MVT::v2f64, 2 }, // BTVER2 from http://www.agner.org/ 888 { ISD::FMUL, MVT::v4f64, 4 }, // BTVER2 from http://www.agner.org/ 889 890 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 891 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 892 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 893 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 894 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 895 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 896 }; 897 898 if (ST->hasAVX()) 899 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 900 return LT.first * Entry->Cost; 901 902 static const CostTblEntry SSE42CostTable[] = { 903 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 904 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 905 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 906 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 907 908 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 909 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 910 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 911 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 912 913 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 914 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 915 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 916 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 917 918 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 919 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 920 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 921 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 922 923 { ISD::MUL, MVT::v2i64, 6 } // 3*pmuludq/3*shift/2*add 924 }; 925 926 if (ST->hasSSE42()) 927 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 928 return LT.first * Entry->Cost; 929 930 static const CostTblEntry SSE41CostTable[] = { 931 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 932 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 933 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 934 935 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 936 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 937 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 938 939 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 940 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 941 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 942 943 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 944 }; 945 946 if (ST->hasSSE41()) 947 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 948 return LT.first * Entry->Cost; 949 950 static const CostTblEntry SSE2CostTable[] = { 951 // We don't correctly identify costs of casts because they are marked as 952 // custom. 953 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 954 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 955 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 956 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 957 958 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 959 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 960 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 961 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 962 963 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 964 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 965 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 966 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 967 968 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 969 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 970 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 971 972 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 973 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 974 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 975 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 976 977 { ISD::FNEG, MVT::f32, 1 }, // Pentium IV from http://www.agner.org/ 978 { ISD::FNEG, MVT::f64, 1 }, // Pentium IV from http://www.agner.org/ 979 { ISD::FNEG, MVT::v4f32, 1 }, // Pentium IV from http://www.agner.org/ 980 { ISD::FNEG, MVT::v2f64, 1 }, // Pentium IV from http://www.agner.org/ 981 982 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 983 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 984 985 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 986 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 987 }; 988 989 if (ST->hasSSE2()) 990 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 991 return LT.first * Entry->Cost; 992 993 static const CostTblEntry SSE1CostTable[] = { 994 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 995 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 996 997 { ISD::FNEG, MVT::f32, 2 }, // Pentium III from http://www.agner.org/ 998 { ISD::FNEG, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 999 1000 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1001 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1002 1003 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1004 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1005 }; 1006 1007 if (ST->hasSSE1()) 1008 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 1009 return LT.first * Entry->Cost; 1010 1011 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 1012 { ISD::ADD, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1013 { ISD::SUB, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1014 }; 1015 1016 if (ST->is64Bit()) 1017 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, LT.second)) 1018 return LT.first * Entry->Cost; 1019 1020 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 1021 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1022 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1023 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1024 1025 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1026 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1027 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1028 }; 1029 1030 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, LT.second)) 1031 return LT.first * Entry->Cost; 1032 1033 // It is not a good idea to vectorize division. We have to scalarize it and 1034 // in the process we will often end up having to spilling regular 1035 // registers. The overhead of division is going to dominate most kernels 1036 // anyways so try hard to prevent vectorization of division - it is 1037 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 1038 // to hide "20 cycles" for each lane. 1039 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 1040 ISD == ISD::UDIV || ISD == ISD::UREM)) { 1041 InstructionCost ScalarCost = getArithmeticInstrCost( 1042 Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info, 1043 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 1044 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 1045 } 1046 1047 // Fallback to the default implementation. 1048 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info); 1049 } 1050 1051 InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, 1052 VectorType *BaseTp, 1053 ArrayRef<int> Mask, int Index, 1054 VectorType *SubTp) { 1055 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 1056 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 1057 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 1058 1059 Kind = improveShuffleKindFromMask(Kind, Mask); 1060 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 1061 if (Kind == TTI::SK_Transpose) 1062 Kind = TTI::SK_PermuteTwoSrc; 1063 1064 // For Broadcasts we are splatting the first element from the first input 1065 // register, so only need to reference that input and all the output 1066 // registers are the same. 1067 if (Kind == TTI::SK_Broadcast) 1068 LT.first = 1; 1069 1070 // Subvector extractions are free if they start at the beginning of a 1071 // vector and cheap if the subvectors are aligned. 1072 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 1073 int NumElts = LT.second.getVectorNumElements(); 1074 if ((Index % NumElts) == 0) 1075 return 0; 1076 std::pair<InstructionCost, MVT> SubLT = 1077 TLI->getTypeLegalizationCost(DL, SubTp); 1078 if (SubLT.second.isVector()) { 1079 int NumSubElts = SubLT.second.getVectorNumElements(); 1080 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1081 return SubLT.first; 1082 // Handle some cases for widening legalization. For now we only handle 1083 // cases where the original subvector was naturally aligned and evenly 1084 // fit in its legalized subvector type. 1085 // FIXME: Remove some of the alignment restrictions. 1086 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 1087 // vectors. 1088 int OrigSubElts = cast<FixedVectorType>(SubTp)->getNumElements(); 1089 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 1090 (NumSubElts % OrigSubElts) == 0 && 1091 LT.second.getVectorElementType() == 1092 SubLT.second.getVectorElementType() && 1093 LT.second.getVectorElementType().getSizeInBits() == 1094 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 1095 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 1096 "Unexpected number of elements!"); 1097 auto *VecTy = FixedVectorType::get(BaseTp->getElementType(), 1098 LT.second.getVectorNumElements()); 1099 auto *SubTy = FixedVectorType::get(BaseTp->getElementType(), 1100 SubLT.second.getVectorNumElements()); 1101 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 1102 InstructionCost ExtractCost = getShuffleCost( 1103 TTI::SK_ExtractSubvector, VecTy, None, ExtractIndex, SubTy); 1104 1105 // If the original size is 32-bits or more, we can use pshufd. Otherwise 1106 // if we have SSSE3 we can use pshufb. 1107 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 1108 return ExtractCost + 1; // pshufd or pshufb 1109 1110 assert(SubTp->getPrimitiveSizeInBits() == 16 && 1111 "Unexpected vector size"); 1112 1113 return ExtractCost + 2; // worst case pshufhw + pshufd 1114 } 1115 } 1116 } 1117 1118 // Subvector insertions are cheap if the subvectors are aligned. 1119 // Note that in general, the insertion starting at the beginning of a vector 1120 // isn't free, because we need to preserve the rest of the wide vector. 1121 if (Kind == TTI::SK_InsertSubvector && LT.second.isVector()) { 1122 int NumElts = LT.second.getVectorNumElements(); 1123 std::pair<InstructionCost, MVT> SubLT = 1124 TLI->getTypeLegalizationCost(DL, SubTp); 1125 if (SubLT.second.isVector()) { 1126 int NumSubElts = SubLT.second.getVectorNumElements(); 1127 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1128 return SubLT.first; 1129 } 1130 } 1131 1132 // Handle some common (illegal) sub-vector types as they are often very cheap 1133 // to shuffle even on targets without PSHUFB. 1134 EVT VT = TLI->getValueType(DL, BaseTp); 1135 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 1136 !ST->hasSSSE3()) { 1137 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 1138 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 1139 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1140 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1141 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1142 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1143 1144 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1145 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1146 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1147 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1148 1149 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1150 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1151 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1152 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1153 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1154 1155 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1156 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1157 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1158 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1159 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1160 }; 1161 1162 if (ST->hasSSE2()) 1163 if (const auto *Entry = 1164 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1165 return Entry->Cost; 1166 } 1167 1168 // We are going to permute multiple sources and the result will be in multiple 1169 // destinations. Providing an accurate cost only for splits where the element 1170 // type remains the same. 1171 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1172 MVT LegalVT = LT.second; 1173 if (LegalVT.isVector() && 1174 LegalVT.getVectorElementType().getSizeInBits() == 1175 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1176 LegalVT.getVectorNumElements() < 1177 cast<FixedVectorType>(BaseTp)->getNumElements()) { 1178 1179 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1180 unsigned LegalVTSize = LegalVT.getStoreSize(); 1181 // Number of source vectors after legalization: 1182 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1183 // Number of destination vectors after legalization: 1184 InstructionCost NumOfDests = LT.first; 1185 1186 auto *SingleOpTy = FixedVectorType::get(BaseTp->getElementType(), 1187 LegalVT.getVectorNumElements()); 1188 1189 InstructionCost NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1190 return NumOfShuffles * getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 1191 None, 0, nullptr); 1192 } 1193 1194 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1195 } 1196 1197 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1198 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1199 // We assume that source and destination have the same vector type. 1200 InstructionCost NumOfDests = LT.first; 1201 InstructionCost NumOfShufflesPerDest = LT.first * 2 - 1; 1202 LT.first = NumOfDests * NumOfShufflesPerDest; 1203 } 1204 1205 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1206 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1207 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1208 1209 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1210 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1211 1212 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b 1213 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b 1214 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2} // vpermt2b 1215 }; 1216 1217 if (ST->hasVBMI()) 1218 if (const auto *Entry = 1219 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1220 return LT.first * Entry->Cost; 1221 1222 static const CostTblEntry AVX512BWShuffleTbl[] = { 1223 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1224 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1225 1226 {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw 1227 {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw 1228 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1229 1230 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw 1231 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw 1232 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1233 1234 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w 1235 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w 1236 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2}, // vpermt2w 1237 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1238 1239 {TTI::SK_Select, MVT::v32i16, 1}, // vblendmw 1240 {TTI::SK_Select, MVT::v64i8, 1}, // vblendmb 1241 }; 1242 1243 if (ST->hasBWI()) 1244 if (const auto *Entry = 1245 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1246 return LT.first * Entry->Cost; 1247 1248 static const CostTblEntry AVX512ShuffleTbl[] = { 1249 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1250 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1251 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1252 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1253 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1254 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1255 1256 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1257 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1258 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1259 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1260 {TTI::SK_Reverse, MVT::v32i16, 7}, // per mca 1261 {TTI::SK_Reverse, MVT::v64i8, 7}, // per mca 1262 1263 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1264 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1265 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1266 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1267 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1268 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1269 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1270 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1271 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1272 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1273 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1274 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1275 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1276 1277 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1278 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1279 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1280 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1281 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1282 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1283 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1284 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1285 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1286 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1287 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1288 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1289 1290 // FIXME: This just applies the type legalization cost rules above 1291 // assuming these completely split. 1292 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1293 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1294 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1295 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1296 1297 {TTI::SK_Select, MVT::v32i16, 1}, // vpternlogq 1298 {TTI::SK_Select, MVT::v64i8, 1}, // vpternlogq 1299 {TTI::SK_Select, MVT::v8f64, 1}, // vblendmpd 1300 {TTI::SK_Select, MVT::v16f32, 1}, // vblendmps 1301 {TTI::SK_Select, MVT::v8i64, 1}, // vblendmq 1302 {TTI::SK_Select, MVT::v16i32, 1}, // vblendmd 1303 }; 1304 1305 if (ST->hasAVX512()) 1306 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1307 return LT.first * Entry->Cost; 1308 1309 static const CostTblEntry AVX2ShuffleTbl[] = { 1310 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1311 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1312 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1313 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1314 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1315 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1316 1317 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1318 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1319 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1320 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1321 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1322 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1323 1324 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1325 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1326 1327 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1328 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1329 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1330 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1331 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1332 // + vpblendvb 1333 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1334 // + vpblendvb 1335 1336 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1337 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1338 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1339 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1340 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1341 // + vpblendvb 1342 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1343 // + vpblendvb 1344 }; 1345 1346 if (ST->hasAVX2()) 1347 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1348 return LT.first * Entry->Cost; 1349 1350 static const CostTblEntry XOPShuffleTbl[] = { 1351 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1352 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1353 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1354 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1355 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1356 // + vinsertf128 1357 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1358 // + vinsertf128 1359 1360 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1361 // + vinsertf128 1362 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1363 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1364 // + vinsertf128 1365 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1366 }; 1367 1368 if (ST->hasXOP()) 1369 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1370 return LT.first * Entry->Cost; 1371 1372 static const CostTblEntry AVX1ShuffleTbl[] = { 1373 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1374 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1375 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1376 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1377 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1378 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1379 1380 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1381 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1382 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1383 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1384 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1385 // + vinsertf128 1386 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1387 // + vinsertf128 1388 1389 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1390 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1391 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1392 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1393 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1394 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1395 1396 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1397 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1398 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1399 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1400 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1401 // + 2*por + vinsertf128 1402 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1403 // + 2*por + vinsertf128 1404 1405 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1406 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1407 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1408 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1409 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1410 // + 4*por + vinsertf128 1411 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1412 // + 4*por + vinsertf128 1413 }; 1414 1415 if (ST->hasAVX()) 1416 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1417 return LT.first * Entry->Cost; 1418 1419 static const CostTblEntry SSE41ShuffleTbl[] = { 1420 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1421 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1422 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1423 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1424 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1425 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1426 }; 1427 1428 if (ST->hasSSE41()) 1429 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1430 return LT.first * Entry->Cost; 1431 1432 static const CostTblEntry SSSE3ShuffleTbl[] = { 1433 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1434 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1435 1436 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1437 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1438 1439 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1440 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1441 1442 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1443 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1444 1445 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1446 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1447 }; 1448 1449 if (ST->hasSSSE3()) 1450 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1451 return LT.first * Entry->Cost; 1452 1453 static const CostTblEntry SSE2ShuffleTbl[] = { 1454 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1455 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1456 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1457 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1458 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1459 1460 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1461 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1462 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1463 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1464 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1465 // + 2*pshufd + 2*unpck + packus 1466 1467 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1468 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1469 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1470 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1471 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1472 1473 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1474 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1475 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1476 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1477 // + pshufd/unpck 1478 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1479 // + 2*pshufd + 2*unpck + 2*packus 1480 1481 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1482 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1483 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1484 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1485 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1486 }; 1487 1488 if (ST->hasSSE2()) 1489 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1490 return LT.first * Entry->Cost; 1491 1492 static const CostTblEntry SSE1ShuffleTbl[] = { 1493 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1494 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1495 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1496 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1497 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1498 }; 1499 1500 if (ST->hasSSE1()) 1501 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1502 return LT.first * Entry->Cost; 1503 1504 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1505 } 1506 1507 InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, 1508 Type *Src, 1509 TTI::CastContextHint CCH, 1510 TTI::TargetCostKind CostKind, 1511 const Instruction *I) { 1512 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1513 assert(ISD && "Invalid opcode"); 1514 1515 // TODO: Allow non-throughput costs that aren't binary. 1516 auto AdjustCost = [&CostKind](InstructionCost Cost) -> InstructionCost { 1517 if (CostKind != TTI::TCK_RecipThroughput) 1518 return Cost == 0 ? 0 : 1; 1519 return Cost; 1520 }; 1521 1522 // FIXME: Need a better design of the cost table to handle non-simple types of 1523 // potential massive combinations (elem_num x src_type x dst_type). 1524 1525 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1526 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1527 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1528 1529 // Mask sign extend has an instruction. 1530 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1531 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1532 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1533 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1534 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1535 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1536 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1537 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1538 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1539 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1540 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1541 1542 // Mask zero extend is a sext + shift. 1543 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1544 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1545 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1546 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1547 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1548 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1549 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1550 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1551 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1552 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1553 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1554 1555 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, 1556 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm 1557 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // widen to zmm 1558 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // widen to zmm 1559 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // vpmovwb 1560 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // widen to zmm 1561 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // widen to zmm 1562 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // vpmovwb 1563 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // widen to zmm 1564 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // widen to zmm 1565 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // vpmovwb 1566 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // widen to zmm 1567 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // widen to zmm 1568 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // widen to zmm 1569 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, 1570 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, 1571 }; 1572 1573 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1574 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1575 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1576 1577 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1578 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1579 1580 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1581 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1582 1583 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1584 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1585 }; 1586 1587 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1588 // 256-bit wide vectors. 1589 1590 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1591 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1592 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1593 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1594 1595 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1596 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1597 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1598 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd 1599 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1600 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1601 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1602 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd 1603 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd 1604 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd 1605 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd 1606 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd 1607 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq 1608 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq 1609 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq 1610 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 2 }, // vpmovdb 1611 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 2 }, // vpmovdb 1612 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, // vpmovdb 1613 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, // vpmovdb 1614 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 2 }, // vpmovqb 1615 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 1 }, // vpshufb 1616 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, // vpmovqb 1617 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, // vpmovqw 1618 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, // vpmovqd 1619 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd 1620 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb 1621 1622 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32 1623 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, 1624 1625 // Sign extend is zmm vpternlogd+vptruncdb. 1626 // Zero extend is zmm broadcast load+vptruncdw. 1627 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 }, 1628 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 }, 1629 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, 1630 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, 1631 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, 1632 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, 1633 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 }, 1634 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 }, 1635 1636 // Sign extend is zmm vpternlogd+vptruncdw. 1637 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw. 1638 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 }, 1639 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1640 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 }, 1641 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1642 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 }, 1643 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1644 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 }, 1645 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1646 1647 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd 1648 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld 1649 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd 1650 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld 1651 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd 1652 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld 1653 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq 1654 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq 1655 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq 1656 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq 1657 1658 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd 1659 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld 1660 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq 1661 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq 1662 1663 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1664 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1665 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1666 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1667 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1668 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1669 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1670 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1671 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1672 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1673 1674 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1675 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1676 1677 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1678 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1679 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1680 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1681 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1682 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1683 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1684 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1685 1686 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1687 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1688 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1689 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1690 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1691 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1692 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1693 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1694 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1695 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1696 1697 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f64, 3 }, 1698 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, 1699 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 3 }, 1700 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 3 }, 1701 1702 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1703 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, 1704 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, 1705 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1706 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, 1707 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, 1708 }; 1709 1710 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1711 // Mask sign extend has an instruction. 1712 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1713 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1714 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1715 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1716 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1717 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1718 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1719 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1720 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1721 1722 // Mask zero extend is a sext + shift. 1723 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1724 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1725 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1726 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1727 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1728 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1729 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1730 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1731 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1732 1733 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, 1734 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // vpsllw+vptestmb 1735 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // vpsllw+vptestmw 1736 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // vpsllw+vptestmb 1737 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // vpsllw+vptestmw 1738 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // vpsllw+vptestmb 1739 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // vpsllw+vptestmw 1740 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // vpsllw+vptestmb 1741 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // vpsllw+vptestmw 1742 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // vpsllw+vptestmb 1743 }; 1744 1745 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1746 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1747 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1748 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1749 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1750 1751 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1752 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1753 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1754 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1755 1756 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1757 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1758 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1759 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1760 1761 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1762 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1763 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1764 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1765 }; 1766 1767 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 1768 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1769 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1770 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1771 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 8 }, // split+2*v8i8 1772 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1773 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1774 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1775 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16 1776 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // vpslld+vptestmd 1777 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd 1778 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // vpslld+vptestmd 1779 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // vpsllq+vptestmq 1780 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // vpsllq+vptestmq 1781 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // vpmovqd 1782 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, // vpmovqb 1783 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, // vpmovqw 1784 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, // vpmovwb 1785 1786 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb 1787 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb 1788 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 }, 1789 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 }, 1790 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 }, 1791 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 }, 1792 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 }, 1793 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 }, 1794 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 }, 1795 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 }, 1796 1797 // sign extend is vpcmpeq+maskedmove+vpmovdw 1798 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw 1799 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1800 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 }, 1801 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1802 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 }, 1803 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1804 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 }, 1805 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 }, 1806 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 }, 1807 1808 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd 1809 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld 1810 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd 1811 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld 1812 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd 1813 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld 1814 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq 1815 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq 1816 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq 1817 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq 1818 1819 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1820 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1821 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1822 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1823 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1824 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1825 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1826 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1827 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1828 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1829 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1830 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1831 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1832 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1833 1834 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 1835 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1836 1837 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 3 }, 1838 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 3 }, 1839 1840 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 1841 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 1842 1843 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1844 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1845 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 1 }, 1846 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1847 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1848 }; 1849 1850 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1851 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1852 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1853 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1854 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1855 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1856 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1857 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1858 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1859 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1860 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1861 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1862 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1863 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1864 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1865 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1866 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1867 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1868 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1869 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1870 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1871 1872 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1873 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1874 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1875 1876 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1877 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1878 1879 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 5 }, 1880 }; 1881 1882 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1883 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1884 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1885 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1886 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1887 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 1888 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 1889 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 1890 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 1891 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1892 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1893 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1894 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1895 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1896 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1897 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1898 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1899 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1900 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1901 1902 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 4 }, 1903 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 5 }, 1904 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 4 }, 1905 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 9 }, 1906 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, 11 }, 1907 1908 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 1909 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1910 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1911 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1912 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 1913 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1914 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 11 }, 1915 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 9 }, 1916 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 }, 1917 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 11 }, 1918 1919 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1920 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1921 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1922 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1923 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1924 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1925 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1926 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1927 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1928 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1929 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1930 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1931 1932 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1933 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1934 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1935 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1936 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1937 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1938 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1939 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1940 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1941 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 }, 1942 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 1943 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1944 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1945 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1946 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1947 // The generic code to compute the scalar overhead is currently broken. 1948 // Workaround this limitation by estimating the scalarization overhead 1949 // here. We have roughly 10 instructions per scalar element. 1950 // Multiply that by the vector width. 1951 // FIXME: remove that when PR19268 is fixed. 1952 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1953 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1954 1955 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 4 }, 1956 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f64, 3 }, 1957 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f64, 2 }, 1958 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 3 }, 1959 1960 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f64, 3 }, 1961 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f64, 2 }, 1962 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 4 }, 1963 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 3 }, 1964 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 9 }, 1965 // This node is expanded into scalarized operations but BasicTTI is overly 1966 // optimistic estimating its cost. It computes 3 per element (one 1967 // vector-extract, one scalar conversion and one vector-insert). The 1968 // problem is that the inserts form a read-modify-write chain so latency 1969 // should be factored in too. Inflating the cost per element by 1. 1970 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 1971 1972 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 1973 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 1974 }; 1975 1976 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 1977 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1978 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1979 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1980 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1981 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1982 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1983 1984 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i8, 1 }, 1985 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i8, 1 }, 1986 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i8, 1 }, 1987 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i8, 1 }, 1988 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i8, 1 }, 1989 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i8, 1 }, 1990 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1991 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1992 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1993 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1994 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1995 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1996 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1997 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1998 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1999 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 2000 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 2001 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 2002 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i16, 1 }, 2003 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i16, 1 }, 2004 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i16, 1 }, 2005 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i16, 1 }, 2006 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 2007 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 2008 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 2009 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 2010 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 2011 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 2012 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, 2013 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, 2014 2015 // These truncates end up widening elements. 2016 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 1 }, // PMOVXZBQ 2017 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 1 }, // PMOVXZWQ 2018 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 1 }, // PMOVXZBD 2019 2020 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 1 }, 2021 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 1 }, 2022 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 2023 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 2024 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 2025 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 2026 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 2027 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 2028 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 1 }, // PSHUFB 2029 2030 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 2031 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 2032 2033 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 3 }, 2034 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 3 }, 2035 2036 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 3 }, 2037 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 3 }, 2038 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, 2039 }; 2040 2041 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 2042 // These are somewhat magic numbers justified by looking at the output of 2043 // Intel's IACA, running some kernels and making sure when we take 2044 // legalization into account the throughput will be overestimated. 2045 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 2046 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 2047 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 2048 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 2049 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 2050 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 2*10 }, 2051 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2*10 }, 2052 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 2053 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 2054 2055 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 2056 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 2057 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 2058 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 2059 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 2060 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 2061 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 }, 2062 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 2063 2064 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 4 }, 2065 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 2 }, 2066 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, 2067 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, 2068 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, 2069 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 4 }, 2070 2071 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 1 }, 2072 2073 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 6 }, 2074 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 }, 2075 2076 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 2077 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 2078 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 4 }, 2079 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 4 }, 2080 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 }, 2081 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 2 }, 2082 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 }, 2083 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 4 }, 2084 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 8 }, 2085 2086 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 2087 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 2088 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 2089 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 2090 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 2091 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 2092 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 2093 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 2094 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 2095 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 2096 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 2097 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 2098 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 2099 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 2100 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 2101 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 2102 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 2103 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 2104 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 2105 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 2106 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 2107 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 2108 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 2109 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 2110 2111 // These truncates are really widening elements. 2112 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 1 }, // PSHUFD 2113 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // PUNPCKLWD+DQ 2114 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // PUNPCKLBW+WD+PSHUFD 2115 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 1 }, // PUNPCKLWD 2116 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // PUNPCKLBW+WD 2117 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 1 }, // PUNPCKLBW 2118 2119 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // PAND+PACKUSWB 2120 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // PAND+PACKUSWB 2121 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // PAND+PACKUSWB 2122 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 2123 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 3 }, // PAND+2*PACKUSWB 2124 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 2125 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 2126 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 2127 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 2128 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 2129 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2130 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 2131 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 2132 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 2133 { ISD::TRUNCATE, MVT::v2i32, MVT::v2i64, 1 }, // PSHUFD 2134 }; 2135 2136 std::pair<InstructionCost, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 2137 std::pair<InstructionCost, MVT> LTDest = 2138 TLI->getTypeLegalizationCost(DL, Dst); 2139 2140 if (ST->hasSSE41() && !ST->hasAVX()) 2141 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2142 LTDest.second, LTSrc.second)) 2143 return AdjustCost(LTSrc.first * Entry->Cost); 2144 2145 if (ST->hasSSE2() && !ST->hasAVX()) 2146 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2147 LTDest.second, LTSrc.second)) 2148 return AdjustCost(LTSrc.first * Entry->Cost); 2149 2150 EVT SrcTy = TLI->getValueType(DL, Src); 2151 EVT DstTy = TLI->getValueType(DL, Dst); 2152 2153 // The function getSimpleVT only handles simple value types. 2154 if (!SrcTy.isSimple() || !DstTy.isSimple()) 2155 return AdjustCost(BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind)); 2156 2157 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 2158 MVT SimpleDstTy = DstTy.getSimpleVT(); 2159 2160 if (ST->useAVX512Regs()) { 2161 if (ST->hasBWI()) 2162 if (const auto *Entry = ConvertCostTableLookup(AVX512BWConversionTbl, ISD, 2163 SimpleDstTy, SimpleSrcTy)) 2164 return AdjustCost(Entry->Cost); 2165 2166 if (ST->hasDQI()) 2167 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 2168 SimpleDstTy, SimpleSrcTy)) 2169 return AdjustCost(Entry->Cost); 2170 2171 if (ST->hasAVX512()) 2172 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 2173 SimpleDstTy, SimpleSrcTy)) 2174 return AdjustCost(Entry->Cost); 2175 } 2176 2177 if (ST->hasBWI()) 2178 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 2179 SimpleDstTy, SimpleSrcTy)) 2180 return AdjustCost(Entry->Cost); 2181 2182 if (ST->hasDQI()) 2183 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 2184 SimpleDstTy, SimpleSrcTy)) 2185 return AdjustCost(Entry->Cost); 2186 2187 if (ST->hasAVX512()) 2188 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2189 SimpleDstTy, SimpleSrcTy)) 2190 return AdjustCost(Entry->Cost); 2191 2192 if (ST->hasAVX2()) { 2193 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2194 SimpleDstTy, SimpleSrcTy)) 2195 return AdjustCost(Entry->Cost); 2196 } 2197 2198 if (ST->hasAVX()) { 2199 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2200 SimpleDstTy, SimpleSrcTy)) 2201 return AdjustCost(Entry->Cost); 2202 } 2203 2204 if (ST->hasSSE41()) { 2205 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2206 SimpleDstTy, SimpleSrcTy)) 2207 return AdjustCost(Entry->Cost); 2208 } 2209 2210 if (ST->hasSSE2()) { 2211 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2212 SimpleDstTy, SimpleSrcTy)) 2213 return AdjustCost(Entry->Cost); 2214 } 2215 2216 return AdjustCost( 2217 BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I)); 2218 } 2219 2220 InstructionCost X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 2221 Type *CondTy, 2222 CmpInst::Predicate VecPred, 2223 TTI::TargetCostKind CostKind, 2224 const Instruction *I) { 2225 // TODO: Handle other cost kinds. 2226 if (CostKind != TTI::TCK_RecipThroughput) 2227 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, 2228 I); 2229 2230 // Legalize the type. 2231 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2232 2233 MVT MTy = LT.second; 2234 2235 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2236 assert(ISD && "Invalid opcode"); 2237 2238 unsigned ExtraCost = 0; 2239 if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) { 2240 // Some vector comparison predicates cost extra instructions. 2241 if (MTy.isVector() && 2242 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 2243 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 2244 ST->hasBWI())) { 2245 switch (cast<CmpInst>(I)->getPredicate()) { 2246 case CmpInst::Predicate::ICMP_NE: 2247 // xor(cmpeq(x,y),-1) 2248 ExtraCost = 1; 2249 break; 2250 case CmpInst::Predicate::ICMP_SGE: 2251 case CmpInst::Predicate::ICMP_SLE: 2252 // xor(cmpgt(x,y),-1) 2253 ExtraCost = 1; 2254 break; 2255 case CmpInst::Predicate::ICMP_ULT: 2256 case CmpInst::Predicate::ICMP_UGT: 2257 // cmpgt(xor(x,signbit),xor(y,signbit)) 2258 // xor(cmpeq(pmaxu(x,y),x),-1) 2259 ExtraCost = 2; 2260 break; 2261 case CmpInst::Predicate::ICMP_ULE: 2262 case CmpInst::Predicate::ICMP_UGE: 2263 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 2264 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 2265 // cmpeq(psubus(x,y),0) 2266 // cmpeq(pminu(x,y),x) 2267 ExtraCost = 1; 2268 } else { 2269 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 2270 ExtraCost = 3; 2271 } 2272 break; 2273 default: 2274 break; 2275 } 2276 } 2277 } 2278 2279 static const CostTblEntry SLMCostTbl[] = { 2280 // slm pcmpeq/pcmpgt throughput is 2 2281 { ISD::SETCC, MVT::v2i64, 2 }, 2282 }; 2283 2284 static const CostTblEntry AVX512BWCostTbl[] = { 2285 { ISD::SETCC, MVT::v32i16, 1 }, 2286 { ISD::SETCC, MVT::v64i8, 1 }, 2287 2288 { ISD::SELECT, MVT::v32i16, 1 }, 2289 { ISD::SELECT, MVT::v64i8, 1 }, 2290 }; 2291 2292 static const CostTblEntry AVX512CostTbl[] = { 2293 { ISD::SETCC, MVT::v8i64, 1 }, 2294 { ISD::SETCC, MVT::v16i32, 1 }, 2295 { ISD::SETCC, MVT::v8f64, 1 }, 2296 { ISD::SETCC, MVT::v16f32, 1 }, 2297 2298 { ISD::SELECT, MVT::v8i64, 1 }, 2299 { ISD::SELECT, MVT::v16i32, 1 }, 2300 { ISD::SELECT, MVT::v8f64, 1 }, 2301 { ISD::SELECT, MVT::v16f32, 1 }, 2302 2303 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 2304 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 2305 2306 { ISD::SELECT, MVT::v32i16, 2 }, // FIXME: should be 3 2307 { ISD::SELECT, MVT::v64i8, 2 }, // FIXME: should be 3 2308 }; 2309 2310 static const CostTblEntry AVX2CostTbl[] = { 2311 { ISD::SETCC, MVT::v4i64, 1 }, 2312 { ISD::SETCC, MVT::v8i32, 1 }, 2313 { ISD::SETCC, MVT::v16i16, 1 }, 2314 { ISD::SETCC, MVT::v32i8, 1 }, 2315 2316 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 2317 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 2318 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 2319 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 2320 }; 2321 2322 static const CostTblEntry AVX1CostTbl[] = { 2323 { ISD::SETCC, MVT::v4f64, 1 }, 2324 { ISD::SETCC, MVT::v8f32, 1 }, 2325 // AVX1 does not support 8-wide integer compare. 2326 { ISD::SETCC, MVT::v4i64, 4 }, 2327 { ISD::SETCC, MVT::v8i32, 4 }, 2328 { ISD::SETCC, MVT::v16i16, 4 }, 2329 { ISD::SETCC, MVT::v32i8, 4 }, 2330 2331 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 2332 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 2333 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 2334 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 2335 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 2336 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 2337 }; 2338 2339 static const CostTblEntry SSE42CostTbl[] = { 2340 { ISD::SETCC, MVT::v2f64, 1 }, 2341 { ISD::SETCC, MVT::v4f32, 1 }, 2342 { ISD::SETCC, MVT::v2i64, 1 }, 2343 }; 2344 2345 static const CostTblEntry SSE41CostTbl[] = { 2346 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 2347 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 2348 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 2349 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 2350 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 2351 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 2352 }; 2353 2354 static const CostTblEntry SSE2CostTbl[] = { 2355 { ISD::SETCC, MVT::v2f64, 2 }, 2356 { ISD::SETCC, MVT::f64, 1 }, 2357 { ISD::SETCC, MVT::v2i64, 8 }, 2358 { ISD::SETCC, MVT::v4i32, 1 }, 2359 { ISD::SETCC, MVT::v8i16, 1 }, 2360 { ISD::SETCC, MVT::v16i8, 1 }, 2361 2362 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 2363 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 2364 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 2365 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 2366 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 2367 }; 2368 2369 static const CostTblEntry SSE1CostTbl[] = { 2370 { ISD::SETCC, MVT::v4f32, 2 }, 2371 { ISD::SETCC, MVT::f32, 1 }, 2372 2373 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 2374 }; 2375 2376 if (ST->isSLM()) 2377 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2378 return LT.first * (ExtraCost + Entry->Cost); 2379 2380 if (ST->hasBWI()) 2381 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2382 return LT.first * (ExtraCost + Entry->Cost); 2383 2384 if (ST->hasAVX512()) 2385 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2386 return LT.first * (ExtraCost + Entry->Cost); 2387 2388 if (ST->hasAVX2()) 2389 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2390 return LT.first * (ExtraCost + Entry->Cost); 2391 2392 if (ST->hasAVX()) 2393 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2394 return LT.first * (ExtraCost + Entry->Cost); 2395 2396 if (ST->hasSSE42()) 2397 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2398 return LT.first * (ExtraCost + Entry->Cost); 2399 2400 if (ST->hasSSE41()) 2401 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2402 return LT.first * (ExtraCost + Entry->Cost); 2403 2404 if (ST->hasSSE2()) 2405 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2406 return LT.first * (ExtraCost + Entry->Cost); 2407 2408 if (ST->hasSSE1()) 2409 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2410 return LT.first * (ExtraCost + Entry->Cost); 2411 2412 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I); 2413 } 2414 2415 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2416 2417 InstructionCost 2418 X86TTIImpl::getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 2419 TTI::TargetCostKind CostKind) { 2420 2421 // Costs should match the codegen from: 2422 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2423 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2424 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2425 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2426 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2427 2428 // TODO: Overflow intrinsics (*ADDO, *SUBO, *MULO) with vector types are not 2429 // specialized in these tables yet. 2430 static const CostTblEntry AVX512CDCostTbl[] = { 2431 { ISD::CTLZ, MVT::v8i64, 1 }, 2432 { ISD::CTLZ, MVT::v16i32, 1 }, 2433 { ISD::CTLZ, MVT::v32i16, 8 }, 2434 { ISD::CTLZ, MVT::v64i8, 20 }, 2435 { ISD::CTLZ, MVT::v4i64, 1 }, 2436 { ISD::CTLZ, MVT::v8i32, 1 }, 2437 { ISD::CTLZ, MVT::v16i16, 4 }, 2438 { ISD::CTLZ, MVT::v32i8, 10 }, 2439 { ISD::CTLZ, MVT::v2i64, 1 }, 2440 { ISD::CTLZ, MVT::v4i32, 1 }, 2441 { ISD::CTLZ, MVT::v8i16, 4 }, 2442 { ISD::CTLZ, MVT::v16i8, 4 }, 2443 }; 2444 static const CostTblEntry AVX512BWCostTbl[] = { 2445 { ISD::ABS, MVT::v32i16, 1 }, 2446 { ISD::ABS, MVT::v64i8, 1 }, 2447 { ISD::BITREVERSE, MVT::v8i64, 5 }, 2448 { ISD::BITREVERSE, MVT::v16i32, 5 }, 2449 { ISD::BITREVERSE, MVT::v32i16, 5 }, 2450 { ISD::BITREVERSE, MVT::v64i8, 5 }, 2451 { ISD::BSWAP, MVT::v8i64, 1 }, 2452 { ISD::BSWAP, MVT::v16i32, 1 }, 2453 { ISD::BSWAP, MVT::v32i16, 1 }, 2454 { ISD::CTLZ, MVT::v8i64, 23 }, 2455 { ISD::CTLZ, MVT::v16i32, 22 }, 2456 { ISD::CTLZ, MVT::v32i16, 18 }, 2457 { ISD::CTLZ, MVT::v64i8, 17 }, 2458 { ISD::CTPOP, MVT::v8i64, 7 }, 2459 { ISD::CTPOP, MVT::v16i32, 11 }, 2460 { ISD::CTPOP, MVT::v32i16, 9 }, 2461 { ISD::CTPOP, MVT::v64i8, 6 }, 2462 { ISD::CTTZ, MVT::v8i64, 10 }, 2463 { ISD::CTTZ, MVT::v16i32, 14 }, 2464 { ISD::CTTZ, MVT::v32i16, 12 }, 2465 { ISD::CTTZ, MVT::v64i8, 9 }, 2466 { ISD::SADDSAT, MVT::v32i16, 1 }, 2467 { ISD::SADDSAT, MVT::v64i8, 1 }, 2468 { ISD::SMAX, MVT::v32i16, 1 }, 2469 { ISD::SMAX, MVT::v64i8, 1 }, 2470 { ISD::SMIN, MVT::v32i16, 1 }, 2471 { ISD::SMIN, MVT::v64i8, 1 }, 2472 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2473 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2474 { ISD::UADDSAT, MVT::v32i16, 1 }, 2475 { ISD::UADDSAT, MVT::v64i8, 1 }, 2476 { ISD::UMAX, MVT::v32i16, 1 }, 2477 { ISD::UMAX, MVT::v64i8, 1 }, 2478 { ISD::UMIN, MVT::v32i16, 1 }, 2479 { ISD::UMIN, MVT::v64i8, 1 }, 2480 { ISD::USUBSAT, MVT::v32i16, 1 }, 2481 { ISD::USUBSAT, MVT::v64i8, 1 }, 2482 }; 2483 static const CostTblEntry AVX512CostTbl[] = { 2484 { ISD::ABS, MVT::v8i64, 1 }, 2485 { ISD::ABS, MVT::v16i32, 1 }, 2486 { ISD::ABS, MVT::v32i16, 2 }, // FIXME: include split 2487 { ISD::ABS, MVT::v64i8, 2 }, // FIXME: include split 2488 { ISD::ABS, MVT::v4i64, 1 }, 2489 { ISD::ABS, MVT::v2i64, 1 }, 2490 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2491 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2492 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2493 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2494 { ISD::BSWAP, MVT::v8i64, 4 }, 2495 { ISD::BSWAP, MVT::v16i32, 4 }, 2496 { ISD::BSWAP, MVT::v32i16, 4 }, 2497 { ISD::CTLZ, MVT::v8i64, 29 }, 2498 { ISD::CTLZ, MVT::v16i32, 35 }, 2499 { ISD::CTLZ, MVT::v32i16, 28 }, 2500 { ISD::CTLZ, MVT::v64i8, 18 }, 2501 { ISD::CTPOP, MVT::v8i64, 16 }, 2502 { ISD::CTPOP, MVT::v16i32, 24 }, 2503 { ISD::CTPOP, MVT::v32i16, 18 }, 2504 { ISD::CTPOP, MVT::v64i8, 12 }, 2505 { ISD::CTTZ, MVT::v8i64, 20 }, 2506 { ISD::CTTZ, MVT::v16i32, 28 }, 2507 { ISD::CTTZ, MVT::v32i16, 24 }, 2508 { ISD::CTTZ, MVT::v64i8, 18 }, 2509 { ISD::SMAX, MVT::v8i64, 1 }, 2510 { ISD::SMAX, MVT::v16i32, 1 }, 2511 { ISD::SMAX, MVT::v32i16, 2 }, // FIXME: include split 2512 { ISD::SMAX, MVT::v64i8, 2 }, // FIXME: include split 2513 { ISD::SMAX, MVT::v4i64, 1 }, 2514 { ISD::SMAX, MVT::v2i64, 1 }, 2515 { ISD::SMIN, MVT::v8i64, 1 }, 2516 { ISD::SMIN, MVT::v16i32, 1 }, 2517 { ISD::SMIN, MVT::v32i16, 2 }, // FIXME: include split 2518 { ISD::SMIN, MVT::v64i8, 2 }, // FIXME: include split 2519 { ISD::SMIN, MVT::v4i64, 1 }, 2520 { ISD::SMIN, MVT::v2i64, 1 }, 2521 { ISD::UMAX, MVT::v8i64, 1 }, 2522 { ISD::UMAX, MVT::v16i32, 1 }, 2523 { ISD::UMAX, MVT::v32i16, 2 }, // FIXME: include split 2524 { ISD::UMAX, MVT::v64i8, 2 }, // FIXME: include split 2525 { ISD::UMAX, MVT::v4i64, 1 }, 2526 { ISD::UMAX, MVT::v2i64, 1 }, 2527 { ISD::UMIN, MVT::v8i64, 1 }, 2528 { ISD::UMIN, MVT::v16i32, 1 }, 2529 { ISD::UMIN, MVT::v32i16, 2 }, // FIXME: include split 2530 { ISD::UMIN, MVT::v64i8, 2 }, // FIXME: include split 2531 { ISD::UMIN, MVT::v4i64, 1 }, 2532 { ISD::UMIN, MVT::v2i64, 1 }, 2533 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2534 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2535 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2536 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2537 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2538 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2539 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2540 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2541 { ISD::SADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2542 { ISD::SADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2543 { ISD::SSUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2544 { ISD::SSUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2545 { ISD::UADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2546 { ISD::UADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2547 { ISD::USUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2548 { ISD::USUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2549 { ISD::FMAXNUM, MVT::f32, 2 }, 2550 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2551 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2552 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2553 { ISD::FMAXNUM, MVT::f64, 2 }, 2554 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2555 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2556 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2557 }; 2558 static const CostTblEntry XOPCostTbl[] = { 2559 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2560 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2561 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2562 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2563 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2564 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2565 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2566 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2567 { ISD::BITREVERSE, MVT::i64, 3 }, 2568 { ISD::BITREVERSE, MVT::i32, 3 }, 2569 { ISD::BITREVERSE, MVT::i16, 3 }, 2570 { ISD::BITREVERSE, MVT::i8, 3 } 2571 }; 2572 static const CostTblEntry AVX2CostTbl[] = { 2573 { ISD::ABS, MVT::v4i64, 2 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2574 { ISD::ABS, MVT::v8i32, 1 }, 2575 { ISD::ABS, MVT::v16i16, 1 }, 2576 { ISD::ABS, MVT::v32i8, 1 }, 2577 { ISD::BITREVERSE, MVT::v4i64, 5 }, 2578 { ISD::BITREVERSE, MVT::v8i32, 5 }, 2579 { ISD::BITREVERSE, MVT::v16i16, 5 }, 2580 { ISD::BITREVERSE, MVT::v32i8, 5 }, 2581 { ISD::BSWAP, MVT::v4i64, 1 }, 2582 { ISD::BSWAP, MVT::v8i32, 1 }, 2583 { ISD::BSWAP, MVT::v16i16, 1 }, 2584 { ISD::CTLZ, MVT::v4i64, 23 }, 2585 { ISD::CTLZ, MVT::v8i32, 18 }, 2586 { ISD::CTLZ, MVT::v16i16, 14 }, 2587 { ISD::CTLZ, MVT::v32i8, 9 }, 2588 { ISD::CTPOP, MVT::v4i64, 7 }, 2589 { ISD::CTPOP, MVT::v8i32, 11 }, 2590 { ISD::CTPOP, MVT::v16i16, 9 }, 2591 { ISD::CTPOP, MVT::v32i8, 6 }, 2592 { ISD::CTTZ, MVT::v4i64, 10 }, 2593 { ISD::CTTZ, MVT::v8i32, 14 }, 2594 { ISD::CTTZ, MVT::v16i16, 12 }, 2595 { ISD::CTTZ, MVT::v32i8, 9 }, 2596 { ISD::SADDSAT, MVT::v16i16, 1 }, 2597 { ISD::SADDSAT, MVT::v32i8, 1 }, 2598 { ISD::SMAX, MVT::v8i32, 1 }, 2599 { ISD::SMAX, MVT::v16i16, 1 }, 2600 { ISD::SMAX, MVT::v32i8, 1 }, 2601 { ISD::SMIN, MVT::v8i32, 1 }, 2602 { ISD::SMIN, MVT::v16i16, 1 }, 2603 { ISD::SMIN, MVT::v32i8, 1 }, 2604 { ISD::SSUBSAT, MVT::v16i16, 1 }, 2605 { ISD::SSUBSAT, MVT::v32i8, 1 }, 2606 { ISD::UADDSAT, MVT::v16i16, 1 }, 2607 { ISD::UADDSAT, MVT::v32i8, 1 }, 2608 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 2609 { ISD::UMAX, MVT::v8i32, 1 }, 2610 { ISD::UMAX, MVT::v16i16, 1 }, 2611 { ISD::UMAX, MVT::v32i8, 1 }, 2612 { ISD::UMIN, MVT::v8i32, 1 }, 2613 { ISD::UMIN, MVT::v16i16, 1 }, 2614 { ISD::UMIN, MVT::v32i8, 1 }, 2615 { ISD::USUBSAT, MVT::v16i16, 1 }, 2616 { ISD::USUBSAT, MVT::v32i8, 1 }, 2617 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2618 { ISD::FMAXNUM, MVT::v8f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2619 { ISD::FMAXNUM, MVT::v4f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2620 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2621 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2622 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2623 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2624 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2625 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2626 }; 2627 static const CostTblEntry AVX1CostTbl[] = { 2628 { ISD::ABS, MVT::v4i64, 5 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2629 { ISD::ABS, MVT::v8i32, 3 }, 2630 { ISD::ABS, MVT::v16i16, 3 }, 2631 { ISD::ABS, MVT::v32i8, 3 }, 2632 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 2633 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 2634 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 2635 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 2636 { ISD::BSWAP, MVT::v4i64, 4 }, 2637 { ISD::BSWAP, MVT::v8i32, 4 }, 2638 { ISD::BSWAP, MVT::v16i16, 4 }, 2639 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 2640 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 2641 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 2642 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2643 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 2644 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 2645 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 2646 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 2647 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 2648 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 2649 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 2650 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2651 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2652 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2653 { ISD::SMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2654 { ISD::SMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2655 { ISD::SMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2656 { ISD::SMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2657 { ISD::SMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2658 { ISD::SMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2659 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2660 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2661 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2662 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2663 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 2664 { ISD::UMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2665 { ISD::UMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2666 { ISD::UMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2667 { ISD::UMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2668 { ISD::UMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2669 { ISD::UMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2670 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2671 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2672 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 2673 { ISD::FMAXNUM, MVT::f32, 3 }, // MAXSS + CMPUNORDSS + BLENDVPS 2674 { ISD::FMAXNUM, MVT::v4f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2675 { ISD::FMAXNUM, MVT::v8f32, 5 }, // MAXPS + CMPUNORDPS + BLENDVPS + ? 2676 { ISD::FMAXNUM, MVT::f64, 3 }, // MAXSD + CMPUNORDSD + BLENDVPD 2677 { ISD::FMAXNUM, MVT::v2f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2678 { ISD::FMAXNUM, MVT::v4f64, 5 }, // MAXPD + CMPUNORDPD + BLENDVPD + ? 2679 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 2680 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 2681 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 2682 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 2683 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 2684 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 2685 }; 2686 static const CostTblEntry GLMCostTbl[] = { 2687 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 2688 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 2689 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 2690 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 2691 }; 2692 static const CostTblEntry SLMCostTbl[] = { 2693 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 2694 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 2695 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 2696 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 2697 }; 2698 static const CostTblEntry SSE42CostTbl[] = { 2699 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 2700 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 2701 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 2702 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 2703 }; 2704 static const CostTblEntry SSE41CostTbl[] = { 2705 { ISD::ABS, MVT::v2i64, 2 }, // BLENDVPD(X,PSUBQ(0,X),X) 2706 { ISD::SMAX, MVT::v4i32, 1 }, 2707 { ISD::SMAX, MVT::v16i8, 1 }, 2708 { ISD::SMIN, MVT::v4i32, 1 }, 2709 { ISD::SMIN, MVT::v16i8, 1 }, 2710 { ISD::UMAX, MVT::v4i32, 1 }, 2711 { ISD::UMAX, MVT::v8i16, 1 }, 2712 { ISD::UMIN, MVT::v4i32, 1 }, 2713 { ISD::UMIN, MVT::v8i16, 1 }, 2714 }; 2715 static const CostTblEntry SSSE3CostTbl[] = { 2716 { ISD::ABS, MVT::v4i32, 1 }, 2717 { ISD::ABS, MVT::v8i16, 1 }, 2718 { ISD::ABS, MVT::v16i8, 1 }, 2719 { ISD::BITREVERSE, MVT::v2i64, 5 }, 2720 { ISD::BITREVERSE, MVT::v4i32, 5 }, 2721 { ISD::BITREVERSE, MVT::v8i16, 5 }, 2722 { ISD::BITREVERSE, MVT::v16i8, 5 }, 2723 { ISD::BSWAP, MVT::v2i64, 1 }, 2724 { ISD::BSWAP, MVT::v4i32, 1 }, 2725 { ISD::BSWAP, MVT::v8i16, 1 }, 2726 { ISD::CTLZ, MVT::v2i64, 23 }, 2727 { ISD::CTLZ, MVT::v4i32, 18 }, 2728 { ISD::CTLZ, MVT::v8i16, 14 }, 2729 { ISD::CTLZ, MVT::v16i8, 9 }, 2730 { ISD::CTPOP, MVT::v2i64, 7 }, 2731 { ISD::CTPOP, MVT::v4i32, 11 }, 2732 { ISD::CTPOP, MVT::v8i16, 9 }, 2733 { ISD::CTPOP, MVT::v16i8, 6 }, 2734 { ISD::CTTZ, MVT::v2i64, 10 }, 2735 { ISD::CTTZ, MVT::v4i32, 14 }, 2736 { ISD::CTTZ, MVT::v8i16, 12 }, 2737 { ISD::CTTZ, MVT::v16i8, 9 } 2738 }; 2739 static const CostTblEntry SSE2CostTbl[] = { 2740 { ISD::ABS, MVT::v2i64, 4 }, 2741 { ISD::ABS, MVT::v4i32, 3 }, 2742 { ISD::ABS, MVT::v8i16, 2 }, 2743 { ISD::ABS, MVT::v16i8, 2 }, 2744 { ISD::BITREVERSE, MVT::v2i64, 29 }, 2745 { ISD::BITREVERSE, MVT::v4i32, 27 }, 2746 { ISD::BITREVERSE, MVT::v8i16, 27 }, 2747 { ISD::BITREVERSE, MVT::v16i8, 20 }, 2748 { ISD::BSWAP, MVT::v2i64, 7 }, 2749 { ISD::BSWAP, MVT::v4i32, 7 }, 2750 { ISD::BSWAP, MVT::v8i16, 7 }, 2751 { ISD::CTLZ, MVT::v2i64, 25 }, 2752 { ISD::CTLZ, MVT::v4i32, 26 }, 2753 { ISD::CTLZ, MVT::v8i16, 20 }, 2754 { ISD::CTLZ, MVT::v16i8, 17 }, 2755 { ISD::CTPOP, MVT::v2i64, 12 }, 2756 { ISD::CTPOP, MVT::v4i32, 15 }, 2757 { ISD::CTPOP, MVT::v8i16, 13 }, 2758 { ISD::CTPOP, MVT::v16i8, 10 }, 2759 { ISD::CTTZ, MVT::v2i64, 14 }, 2760 { ISD::CTTZ, MVT::v4i32, 18 }, 2761 { ISD::CTTZ, MVT::v8i16, 16 }, 2762 { ISD::CTTZ, MVT::v16i8, 13 }, 2763 { ISD::SADDSAT, MVT::v8i16, 1 }, 2764 { ISD::SADDSAT, MVT::v16i8, 1 }, 2765 { ISD::SMAX, MVT::v8i16, 1 }, 2766 { ISD::SMIN, MVT::v8i16, 1 }, 2767 { ISD::SSUBSAT, MVT::v8i16, 1 }, 2768 { ISD::SSUBSAT, MVT::v16i8, 1 }, 2769 { ISD::UADDSAT, MVT::v8i16, 1 }, 2770 { ISD::UADDSAT, MVT::v16i8, 1 }, 2771 { ISD::UMAX, MVT::v8i16, 2 }, 2772 { ISD::UMAX, MVT::v16i8, 1 }, 2773 { ISD::UMIN, MVT::v8i16, 2 }, 2774 { ISD::UMIN, MVT::v16i8, 1 }, 2775 { ISD::USUBSAT, MVT::v8i16, 1 }, 2776 { ISD::USUBSAT, MVT::v16i8, 1 }, 2777 { ISD::FMAXNUM, MVT::f64, 4 }, 2778 { ISD::FMAXNUM, MVT::v2f64, 4 }, 2779 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 2780 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 2781 }; 2782 static const CostTblEntry SSE1CostTbl[] = { 2783 { ISD::FMAXNUM, MVT::f32, 4 }, 2784 { ISD::FMAXNUM, MVT::v4f32, 4 }, 2785 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 2786 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 2787 }; 2788 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 2789 { ISD::CTTZ, MVT::i64, 1 }, 2790 }; 2791 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 2792 { ISD::CTTZ, MVT::i32, 1 }, 2793 { ISD::CTTZ, MVT::i16, 1 }, 2794 { ISD::CTTZ, MVT::i8, 1 }, 2795 }; 2796 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 2797 { ISD::CTLZ, MVT::i64, 1 }, 2798 }; 2799 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 2800 { ISD::CTLZ, MVT::i32, 1 }, 2801 { ISD::CTLZ, MVT::i16, 1 }, 2802 { ISD::CTLZ, MVT::i8, 1 }, 2803 }; 2804 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 2805 { ISD::CTPOP, MVT::i64, 1 }, 2806 }; 2807 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 2808 { ISD::CTPOP, MVT::i32, 1 }, 2809 { ISD::CTPOP, MVT::i16, 1 }, 2810 { ISD::CTPOP, MVT::i8, 1 }, 2811 }; 2812 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2813 { ISD::ABS, MVT::i64, 2 }, // SUB+CMOV 2814 { ISD::BITREVERSE, MVT::i64, 14 }, 2815 { ISD::BSWAP, MVT::i64, 1 }, 2816 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 2817 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 2818 { ISD::CTPOP, MVT::i64, 10 }, 2819 { ISD::SADDO, MVT::i64, 1 }, 2820 { ISD::UADDO, MVT::i64, 1 }, 2821 { ISD::UMULO, MVT::i64, 2 }, // mulq + seto 2822 }; 2823 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2824 { ISD::ABS, MVT::i32, 2 }, // SUB+CMOV 2825 { ISD::ABS, MVT::i16, 2 }, // SUB+CMOV 2826 { ISD::BITREVERSE, MVT::i32, 14 }, 2827 { ISD::BITREVERSE, MVT::i16, 14 }, 2828 { ISD::BITREVERSE, MVT::i8, 11 }, 2829 { ISD::BSWAP, MVT::i32, 1 }, 2830 { ISD::BSWAP, MVT::i16, 1 }, // ROL 2831 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 2832 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 2833 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 2834 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 2835 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 2836 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 2837 { ISD::CTPOP, MVT::i32, 8 }, 2838 { ISD::CTPOP, MVT::i16, 9 }, 2839 { ISD::CTPOP, MVT::i8, 7 }, 2840 { ISD::SADDO, MVT::i32, 1 }, 2841 { ISD::SADDO, MVT::i16, 1 }, 2842 { ISD::SADDO, MVT::i8, 1 }, 2843 { ISD::UADDO, MVT::i32, 1 }, 2844 { ISD::UADDO, MVT::i16, 1 }, 2845 { ISD::UADDO, MVT::i8, 1 }, 2846 { ISD::UMULO, MVT::i32, 2 }, // mul + seto 2847 { ISD::UMULO, MVT::i16, 2 }, 2848 { ISD::UMULO, MVT::i8, 2 }, 2849 }; 2850 2851 Type *RetTy = ICA.getReturnType(); 2852 Type *OpTy = RetTy; 2853 Intrinsic::ID IID = ICA.getID(); 2854 unsigned ISD = ISD::DELETED_NODE; 2855 switch (IID) { 2856 default: 2857 break; 2858 case Intrinsic::abs: 2859 ISD = ISD::ABS; 2860 break; 2861 case Intrinsic::bitreverse: 2862 ISD = ISD::BITREVERSE; 2863 break; 2864 case Intrinsic::bswap: 2865 ISD = ISD::BSWAP; 2866 break; 2867 case Intrinsic::ctlz: 2868 ISD = ISD::CTLZ; 2869 break; 2870 case Intrinsic::ctpop: 2871 ISD = ISD::CTPOP; 2872 break; 2873 case Intrinsic::cttz: 2874 ISD = ISD::CTTZ; 2875 break; 2876 case Intrinsic::maxnum: 2877 case Intrinsic::minnum: 2878 // FMINNUM has same costs so don't duplicate. 2879 ISD = ISD::FMAXNUM; 2880 break; 2881 case Intrinsic::sadd_sat: 2882 ISD = ISD::SADDSAT; 2883 break; 2884 case Intrinsic::smax: 2885 ISD = ISD::SMAX; 2886 break; 2887 case Intrinsic::smin: 2888 ISD = ISD::SMIN; 2889 break; 2890 case Intrinsic::ssub_sat: 2891 ISD = ISD::SSUBSAT; 2892 break; 2893 case Intrinsic::uadd_sat: 2894 ISD = ISD::UADDSAT; 2895 break; 2896 case Intrinsic::umax: 2897 ISD = ISD::UMAX; 2898 break; 2899 case Intrinsic::umin: 2900 ISD = ISD::UMIN; 2901 break; 2902 case Intrinsic::usub_sat: 2903 ISD = ISD::USUBSAT; 2904 break; 2905 case Intrinsic::sqrt: 2906 ISD = ISD::FSQRT; 2907 break; 2908 case Intrinsic::sadd_with_overflow: 2909 case Intrinsic::ssub_with_overflow: 2910 // SSUBO has same costs so don't duplicate. 2911 ISD = ISD::SADDO; 2912 OpTy = RetTy->getContainedType(0); 2913 break; 2914 case Intrinsic::uadd_with_overflow: 2915 case Intrinsic::usub_with_overflow: 2916 // USUBO has same costs so don't duplicate. 2917 ISD = ISD::UADDO; 2918 OpTy = RetTy->getContainedType(0); 2919 break; 2920 case Intrinsic::umul_with_overflow: 2921 case Intrinsic::smul_with_overflow: 2922 // SMULO has same costs so don't duplicate. 2923 ISD = ISD::UMULO; 2924 OpTy = RetTy->getContainedType(0); 2925 break; 2926 } 2927 2928 if (ISD != ISD::DELETED_NODE) { 2929 // Legalize the type. 2930 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 2931 MVT MTy = LT.second; 2932 2933 // Attempt to lookup cost. 2934 if (ISD == ISD::BITREVERSE && ST->hasGFNI() && ST->hasSSSE3() && 2935 MTy.isVector()) { 2936 // With PSHUFB the code is very similar for all types. If we have integer 2937 // byte operations, we just need a GF2P8AFFINEQB for vXi8. For other types 2938 // we also need a PSHUFB. 2939 unsigned Cost = MTy.getVectorElementType() == MVT::i8 ? 1 : 2; 2940 2941 // Without byte operations, we need twice as many GF2P8AFFINEQB and PSHUFB 2942 // instructions. We also need an extract and an insert. 2943 if (!(MTy.is128BitVector() || (ST->hasAVX2() && MTy.is256BitVector()) || 2944 (ST->hasBWI() && MTy.is512BitVector()))) 2945 Cost = Cost * 2 + 2; 2946 2947 return LT.first * Cost; 2948 } 2949 2950 auto adjustTableCost = [](const CostTblEntry &Entry, 2951 InstructionCost LegalizationCost, 2952 FastMathFlags FMF) { 2953 // If there are no NANs to deal with, then these are reduced to a 2954 // single MIN** or MAX** instruction instead of the MIN/CMP/SELECT that we 2955 // assume is used in the non-fast case. 2956 if (Entry.ISD == ISD::FMAXNUM || Entry.ISD == ISD::FMINNUM) { 2957 if (FMF.noNaNs()) 2958 return LegalizationCost * 1; 2959 } 2960 return LegalizationCost * (int)Entry.Cost; 2961 }; 2962 2963 if (ST->useGLMDivSqrtCosts()) 2964 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 2965 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2966 2967 if (ST->isSLM()) 2968 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2969 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2970 2971 if (ST->hasCDI()) 2972 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 2973 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2974 2975 if (ST->hasBWI()) 2976 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2977 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2978 2979 if (ST->hasAVX512()) 2980 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2981 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2982 2983 if (ST->hasXOP()) 2984 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2985 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2986 2987 if (ST->hasAVX2()) 2988 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2989 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2990 2991 if (ST->hasAVX()) 2992 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2993 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2994 2995 if (ST->hasSSE42()) 2996 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2997 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2998 2999 if (ST->hasSSE41()) 3000 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3001 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3002 3003 if (ST->hasSSSE3()) 3004 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 3005 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3006 3007 if (ST->hasSSE2()) 3008 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3009 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3010 3011 if (ST->hasSSE1()) 3012 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3013 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3014 3015 if (ST->hasBMI()) { 3016 if (ST->is64Bit()) 3017 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 3018 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3019 3020 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 3021 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3022 } 3023 3024 if (ST->hasLZCNT()) { 3025 if (ST->is64Bit()) 3026 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 3027 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3028 3029 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 3030 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3031 } 3032 3033 if (ST->hasPOPCNT()) { 3034 if (ST->is64Bit()) 3035 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 3036 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3037 3038 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 3039 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3040 } 3041 3042 if (ISD == ISD::BSWAP && ST->hasMOVBE() && ST->hasFastMOVBE()) { 3043 if (const Instruction *II = ICA.getInst()) { 3044 if (II->hasOneUse() && isa<StoreInst>(II->user_back())) 3045 return TTI::TCC_Free; 3046 if (auto *LI = dyn_cast<LoadInst>(II->getOperand(0))) { 3047 if (LI->hasOneUse()) 3048 return TTI::TCC_Free; 3049 } 3050 } 3051 } 3052 3053 // TODO - add BMI (TZCNT) scalar handling 3054 3055 if (ST->is64Bit()) 3056 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3057 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3058 3059 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3060 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3061 } 3062 3063 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3064 } 3065 3066 InstructionCost 3067 X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 3068 TTI::TargetCostKind CostKind) { 3069 if (ICA.isTypeBasedOnly()) 3070 return getTypeBasedIntrinsicInstrCost(ICA, CostKind); 3071 3072 static const CostTblEntry AVX512CostTbl[] = { 3073 { ISD::ROTL, MVT::v8i64, 1 }, 3074 { ISD::ROTL, MVT::v4i64, 1 }, 3075 { ISD::ROTL, MVT::v2i64, 1 }, 3076 { ISD::ROTL, MVT::v16i32, 1 }, 3077 { ISD::ROTL, MVT::v8i32, 1 }, 3078 { ISD::ROTL, MVT::v4i32, 1 }, 3079 { ISD::ROTR, MVT::v8i64, 1 }, 3080 { ISD::ROTR, MVT::v4i64, 1 }, 3081 { ISD::ROTR, MVT::v2i64, 1 }, 3082 { ISD::ROTR, MVT::v16i32, 1 }, 3083 { ISD::ROTR, MVT::v8i32, 1 }, 3084 { ISD::ROTR, MVT::v4i32, 1 } 3085 }; 3086 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 3087 static const CostTblEntry XOPCostTbl[] = { 3088 { ISD::ROTL, MVT::v4i64, 4 }, 3089 { ISD::ROTL, MVT::v8i32, 4 }, 3090 { ISD::ROTL, MVT::v16i16, 4 }, 3091 { ISD::ROTL, MVT::v32i8, 4 }, 3092 { ISD::ROTL, MVT::v2i64, 1 }, 3093 { ISD::ROTL, MVT::v4i32, 1 }, 3094 { ISD::ROTL, MVT::v8i16, 1 }, 3095 { ISD::ROTL, MVT::v16i8, 1 }, 3096 { ISD::ROTR, MVT::v4i64, 6 }, 3097 { ISD::ROTR, MVT::v8i32, 6 }, 3098 { ISD::ROTR, MVT::v16i16, 6 }, 3099 { ISD::ROTR, MVT::v32i8, 6 }, 3100 { ISD::ROTR, MVT::v2i64, 2 }, 3101 { ISD::ROTR, MVT::v4i32, 2 }, 3102 { ISD::ROTR, MVT::v8i16, 2 }, 3103 { ISD::ROTR, MVT::v16i8, 2 } 3104 }; 3105 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 3106 { ISD::ROTL, MVT::i64, 1 }, 3107 { ISD::ROTR, MVT::i64, 1 }, 3108 { ISD::FSHL, MVT::i64, 4 } 3109 }; 3110 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 3111 { ISD::ROTL, MVT::i32, 1 }, 3112 { ISD::ROTL, MVT::i16, 1 }, 3113 { ISD::ROTL, MVT::i8, 1 }, 3114 { ISD::ROTR, MVT::i32, 1 }, 3115 { ISD::ROTR, MVT::i16, 1 }, 3116 { ISD::ROTR, MVT::i8, 1 }, 3117 { ISD::FSHL, MVT::i32, 4 }, 3118 { ISD::FSHL, MVT::i16, 4 }, 3119 { ISD::FSHL, MVT::i8, 4 } 3120 }; 3121 3122 Intrinsic::ID IID = ICA.getID(); 3123 Type *RetTy = ICA.getReturnType(); 3124 const SmallVectorImpl<const Value *> &Args = ICA.getArgs(); 3125 unsigned ISD = ISD::DELETED_NODE; 3126 switch (IID) { 3127 default: 3128 break; 3129 case Intrinsic::fshl: 3130 ISD = ISD::FSHL; 3131 if (Args[0] == Args[1]) 3132 ISD = ISD::ROTL; 3133 break; 3134 case Intrinsic::fshr: 3135 // FSHR has same costs so don't duplicate. 3136 ISD = ISD::FSHL; 3137 if (Args[0] == Args[1]) 3138 ISD = ISD::ROTR; 3139 break; 3140 } 3141 3142 if (ISD != ISD::DELETED_NODE) { 3143 // Legalize the type. 3144 std::pair<InstructionCost, MVT> LT = 3145 TLI->getTypeLegalizationCost(DL, RetTy); 3146 MVT MTy = LT.second; 3147 3148 // Attempt to lookup cost. 3149 if (ST->hasAVX512()) 3150 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3151 return LT.first * Entry->Cost; 3152 3153 if (ST->hasXOP()) 3154 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3155 return LT.first * Entry->Cost; 3156 3157 if (ST->is64Bit()) 3158 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3159 return LT.first * Entry->Cost; 3160 3161 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3162 return LT.first * Entry->Cost; 3163 } 3164 3165 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3166 } 3167 3168 InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, 3169 unsigned Index) { 3170 static const CostTblEntry SLMCostTbl[] = { 3171 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 3172 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 3173 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 3174 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 3175 }; 3176 3177 assert(Val->isVectorTy() && "This must be a vector type"); 3178 Type *ScalarType = Val->getScalarType(); 3179 int RegisterFileMoveCost = 0; 3180 3181 if (Index != -1U && (Opcode == Instruction::ExtractElement || 3182 Opcode == Instruction::InsertElement)) { 3183 // Legalize the type. 3184 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 3185 3186 // This type is legalized to a scalar type. 3187 if (!LT.second.isVector()) 3188 return 0; 3189 3190 // The type may be split. Normalize the index to the new type. 3191 unsigned NumElts = LT.second.getVectorNumElements(); 3192 unsigned SubNumElts = NumElts; 3193 Index = Index % NumElts; 3194 3195 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 3196 // For inserts, we also need to insert the subvector back. 3197 if (LT.second.getSizeInBits() > 128) { 3198 assert((LT.second.getSizeInBits() % 128) == 0 && "Illegal vector"); 3199 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 3200 SubNumElts = NumElts / NumSubVecs; 3201 if (SubNumElts <= Index) { 3202 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 3203 Index %= SubNumElts; 3204 } 3205 } 3206 3207 if (Index == 0) { 3208 // Floating point scalars are already located in index #0. 3209 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 3210 // true for all. 3211 if (ScalarType->isFloatingPointTy()) 3212 return RegisterFileMoveCost; 3213 3214 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 3215 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 3216 return 1 + RegisterFileMoveCost; 3217 } 3218 3219 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3220 assert(ISD && "Unexpected vector opcode"); 3221 MVT MScalarTy = LT.second.getScalarType(); 3222 if (ST->isSLM()) 3223 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 3224 return Entry->Cost + RegisterFileMoveCost; 3225 3226 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 3227 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3228 (MScalarTy.isInteger() && ST->hasSSE41())) 3229 return 1 + RegisterFileMoveCost; 3230 3231 // Assume insertps is relatively cheap on all targets. 3232 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 3233 Opcode == Instruction::InsertElement) 3234 return 1 + RegisterFileMoveCost; 3235 3236 // For extractions we just need to shuffle the element to index 0, which 3237 // should be very cheap (assume cost = 1). For insertions we need to shuffle 3238 // the elements to its destination. In both cases we must handle the 3239 // subvector move(s). 3240 // If the vector type is already less than 128-bits then don't reduce it. 3241 // TODO: Under what circumstances should we shuffle using the full width? 3242 InstructionCost ShuffleCost = 1; 3243 if (Opcode == Instruction::InsertElement) { 3244 auto *SubTy = cast<VectorType>(Val); 3245 EVT VT = TLI->getValueType(DL, Val); 3246 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 3247 SubTy = FixedVectorType::get(ScalarType, SubNumElts); 3248 ShuffleCost = 3249 getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, None, 0, SubTy); 3250 } 3251 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 3252 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 3253 } 3254 3255 // Add to the base cost if we know that the extracted element of a vector is 3256 // destined to be moved to and used in the integer register file. 3257 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 3258 RegisterFileMoveCost += 1; 3259 3260 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 3261 } 3262 3263 InstructionCost X86TTIImpl::getScalarizationOverhead(VectorType *Ty, 3264 const APInt &DemandedElts, 3265 bool Insert, 3266 bool Extract) { 3267 InstructionCost Cost = 0; 3268 3269 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much 3270 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT. 3271 if (Insert) { 3272 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3273 MVT MScalarTy = LT.second.getScalarType(); 3274 3275 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3276 (MScalarTy.isInteger() && ST->hasSSE41()) || 3277 (MScalarTy == MVT::f32 && ST->hasSSE41())) { 3278 // For types we can insert directly, insertion into 128-bit sub vectors is 3279 // cheap, followed by a cheap chain of concatenations. 3280 if (LT.second.getSizeInBits() <= 128) { 3281 Cost += 3282 BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, false); 3283 } else { 3284 // In each 128-lane, if at least one index is demanded but not all 3285 // indices are demanded and this 128-lane is not the first 128-lane of 3286 // the legalized-vector, then this 128-lane needs a extracti128; If in 3287 // each 128-lane, there is at least one demanded index, this 128-lane 3288 // needs a inserti128. 3289 3290 // The following cases will help you build a better understanding: 3291 // Assume we insert several elements into a v8i32 vector in avx2, 3292 // Case#1: inserting into 1th index needs vpinsrd + inserti128. 3293 // Case#2: inserting into 5th index needs extracti128 + vpinsrd + 3294 // inserti128. 3295 // Case#3: inserting into 4,5,6,7 index needs 4*vpinsrd + inserti128. 3296 const int CostValue = *LT.first.getValue(); 3297 assert(CostValue >= 0 && "Negative cost!"); 3298 unsigned Num128Lanes = LT.second.getSizeInBits() / 128 * CostValue; 3299 unsigned NumElts = LT.second.getVectorNumElements() * CostValue; 3300 APInt WidenedDemandedElts = DemandedElts.zextOrSelf(NumElts); 3301 unsigned Scale = NumElts / Num128Lanes; 3302 // We iterate each 128-lane, and check if we need a 3303 // extracti128/inserti128 for this 128-lane. 3304 for (unsigned I = 0; I < NumElts; I += Scale) { 3305 APInt Mask = WidenedDemandedElts.getBitsSet(NumElts, I, I + Scale); 3306 APInt MaskedDE = Mask & WidenedDemandedElts; 3307 unsigned Population = MaskedDE.countPopulation(); 3308 Cost += (Population > 0 && Population != Scale && 3309 I % LT.second.getVectorNumElements() != 0); 3310 Cost += Population > 0; 3311 } 3312 Cost += DemandedElts.countPopulation(); 3313 3314 // For vXf32 cases, insertion into the 0'th index in each v4f32 3315 // 128-bit vector is free. 3316 // NOTE: This assumes legalization widens vXf32 vectors. 3317 if (MScalarTy == MVT::f32) 3318 for (unsigned i = 0, e = cast<FixedVectorType>(Ty)->getNumElements(); 3319 i < e; i += 4) 3320 if (DemandedElts[i]) 3321 Cost--; 3322 } 3323 } else if (LT.second.isVector()) { 3324 // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded 3325 // integer element as a SCALAR_TO_VECTOR, then we build the vector as a 3326 // series of UNPCK followed by CONCAT_VECTORS - all of these can be 3327 // considered cheap. 3328 if (Ty->isIntOrIntVectorTy()) 3329 Cost += DemandedElts.countPopulation(); 3330 3331 // Get the smaller of the legalized or original pow2-extended number of 3332 // vector elements, which represents the number of unpacks we'll end up 3333 // performing. 3334 unsigned NumElts = LT.second.getVectorNumElements(); 3335 unsigned Pow2Elts = 3336 PowerOf2Ceil(cast<FixedVectorType>(Ty)->getNumElements()); 3337 Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first; 3338 } 3339 } 3340 3341 // TODO: Use default extraction for now, but we should investigate extending this 3342 // to handle repeated subvector extraction. 3343 if (Extract) 3344 Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, false, Extract); 3345 3346 return Cost; 3347 } 3348 3349 InstructionCost X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 3350 MaybeAlign Alignment, 3351 unsigned AddressSpace, 3352 TTI::TargetCostKind CostKind, 3353 const Instruction *I) { 3354 // TODO: Handle other cost kinds. 3355 if (CostKind != TTI::TCK_RecipThroughput) { 3356 if (auto *SI = dyn_cast_or_null<StoreInst>(I)) { 3357 // Store instruction with index and scale costs 2 Uops. 3358 // Check the preceding GEP to identify non-const indices. 3359 if (auto *GEP = dyn_cast<GetElementPtrInst>(SI->getPointerOperand())) { 3360 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3361 return TTI::TCC_Basic * 2; 3362 } 3363 } 3364 return TTI::TCC_Basic; 3365 } 3366 3367 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 3368 "Invalid Opcode"); 3369 // Type legalization can't handle structs 3370 if (TLI->getValueType(DL, Src, true) == MVT::Other) 3371 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3372 CostKind); 3373 3374 // Legalize the type. 3375 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 3376 3377 auto *VTy = dyn_cast<FixedVectorType>(Src); 3378 3379 // Handle the simple case of non-vectors. 3380 // NOTE: this assumes that legalization never creates vector from scalars! 3381 if (!VTy || !LT.second.isVector()) 3382 // Each load/store unit costs 1. 3383 return LT.first * 1; 3384 3385 bool IsLoad = Opcode == Instruction::Load; 3386 3387 Type *EltTy = VTy->getElementType(); 3388 3389 const int EltTyBits = DL.getTypeSizeInBits(EltTy); 3390 3391 InstructionCost Cost = 0; 3392 3393 // Source of truth: how many elements were there in the original IR vector? 3394 const unsigned SrcNumElt = VTy->getNumElements(); 3395 3396 // How far have we gotten? 3397 int NumEltRemaining = SrcNumElt; 3398 // Note that we intentionally capture by-reference, NumEltRemaining changes. 3399 auto NumEltDone = [&]() { return SrcNumElt - NumEltRemaining; }; 3400 3401 const int MaxLegalOpSizeBytes = divideCeil(LT.second.getSizeInBits(), 8); 3402 3403 // Note that even if we can store 64 bits of an XMM, we still operate on XMM. 3404 const unsigned XMMBits = 128; 3405 if (XMMBits % EltTyBits != 0) 3406 // Vector size must be a multiple of the element size. I.e. no padding. 3407 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3408 CostKind); 3409 const int NumEltPerXMM = XMMBits / EltTyBits; 3410 3411 auto *XMMVecTy = FixedVectorType::get(EltTy, NumEltPerXMM); 3412 3413 for (int CurrOpSizeBytes = MaxLegalOpSizeBytes, SubVecEltsLeft = 0; 3414 NumEltRemaining > 0; CurrOpSizeBytes /= 2) { 3415 // How many elements would a single op deal with at once? 3416 if ((8 * CurrOpSizeBytes) % EltTyBits != 0) 3417 // Vector size must be a multiple of the element size. I.e. no padding. 3418 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3419 CostKind); 3420 int CurrNumEltPerOp = (8 * CurrOpSizeBytes) / EltTyBits; 3421 3422 assert(CurrOpSizeBytes > 0 && CurrNumEltPerOp > 0 && "How'd we get here?"); 3423 assert((((NumEltRemaining * EltTyBits) < (2 * 8 * CurrOpSizeBytes)) || 3424 (CurrOpSizeBytes == MaxLegalOpSizeBytes)) && 3425 "Unless we haven't halved the op size yet, " 3426 "we have less than two op's sized units of work left."); 3427 3428 auto *CurrVecTy = CurrNumEltPerOp > NumEltPerXMM 3429 ? FixedVectorType::get(EltTy, CurrNumEltPerOp) 3430 : XMMVecTy; 3431 3432 assert(CurrVecTy->getNumElements() % CurrNumEltPerOp == 0 && 3433 "After halving sizes, the vector elt count is no longer a multiple " 3434 "of number of elements per operation?"); 3435 auto *CoalescedVecTy = 3436 CurrNumEltPerOp == 1 3437 ? CurrVecTy 3438 : FixedVectorType::get( 3439 IntegerType::get(Src->getContext(), 3440 EltTyBits * CurrNumEltPerOp), 3441 CurrVecTy->getNumElements() / CurrNumEltPerOp); 3442 assert(DL.getTypeSizeInBits(CoalescedVecTy) == 3443 DL.getTypeSizeInBits(CurrVecTy) && 3444 "coalesciing elements doesn't change vector width."); 3445 3446 while (NumEltRemaining > 0) { 3447 assert(SubVecEltsLeft >= 0 && "Subreg element count overconsumtion?"); 3448 3449 // Can we use this vector size, as per the remaining element count? 3450 // Iff the vector is naturally aligned, we can do a wide load regardless. 3451 if (NumEltRemaining < CurrNumEltPerOp && 3452 (!IsLoad || Alignment.valueOrOne() < CurrOpSizeBytes) && 3453 CurrOpSizeBytes != 1) 3454 break; // Try smalled vector size. 3455 3456 bool Is0thSubVec = (NumEltDone() % LT.second.getVectorNumElements()) == 0; 3457 3458 // If we have fully processed the previous reg, we need to replenish it. 3459 if (SubVecEltsLeft == 0) { 3460 SubVecEltsLeft += CurrVecTy->getNumElements(); 3461 // And that's free only for the 0'th subvector of a legalized vector. 3462 if (!Is0thSubVec) 3463 Cost += getShuffleCost(IsLoad ? TTI::ShuffleKind::SK_InsertSubvector 3464 : TTI::ShuffleKind::SK_ExtractSubvector, 3465 VTy, None, NumEltDone(), CurrVecTy); 3466 } 3467 3468 // While we can directly load/store ZMM, YMM, and 64-bit halves of XMM, 3469 // for smaller widths (32/16/8) we have to insert/extract them separately. 3470 // Again, it's free for the 0'th subreg (if op is 32/64 bit wide, 3471 // but let's pretend that it is also true for 16/8 bit wide ops...) 3472 if (CurrOpSizeBytes <= 32 / 8 && !Is0thSubVec) { 3473 int NumEltDoneInCurrXMM = NumEltDone() % NumEltPerXMM; 3474 assert(NumEltDoneInCurrXMM % CurrNumEltPerOp == 0 && ""); 3475 int CoalescedVecEltIdx = NumEltDoneInCurrXMM / CurrNumEltPerOp; 3476 APInt DemandedElts = 3477 APInt::getBitsSet(CoalescedVecTy->getNumElements(), 3478 CoalescedVecEltIdx, CoalescedVecEltIdx + 1); 3479 assert(DemandedElts.countPopulation() == 1 && "Inserting single value"); 3480 Cost += getScalarizationOverhead(CoalescedVecTy, DemandedElts, IsLoad, 3481 !IsLoad); 3482 } 3483 3484 // This isn't exactly right. We're using slow unaligned 32-byte accesses 3485 // as a proxy for a double-pumped AVX memory interface such as on 3486 // Sandybridge. 3487 if (CurrOpSizeBytes == 32 && ST->isUnalignedMem32Slow()) 3488 Cost += 2; 3489 else 3490 Cost += 1; 3491 3492 SubVecEltsLeft -= CurrNumEltPerOp; 3493 NumEltRemaining -= CurrNumEltPerOp; 3494 Alignment = commonAlignment(Alignment.valueOrOne(), CurrOpSizeBytes); 3495 } 3496 } 3497 3498 assert(NumEltRemaining <= 0 && "Should have processed all the elements."); 3499 3500 return Cost; 3501 } 3502 3503 InstructionCost 3504 X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, Align Alignment, 3505 unsigned AddressSpace, 3506 TTI::TargetCostKind CostKind) { 3507 bool IsLoad = (Instruction::Load == Opcode); 3508 bool IsStore = (Instruction::Store == Opcode); 3509 3510 auto *SrcVTy = dyn_cast<FixedVectorType>(SrcTy); 3511 if (!SrcVTy) 3512 // To calculate scalar take the regular cost, without mask 3513 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace, CostKind); 3514 3515 unsigned NumElem = SrcVTy->getNumElements(); 3516 auto *MaskTy = 3517 FixedVectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 3518 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, Alignment)) || 3519 (IsStore && !isLegalMaskedStore(SrcVTy, Alignment))) { 3520 // Scalarization 3521 APInt DemandedElts = APInt::getAllOnesValue(NumElem); 3522 InstructionCost MaskSplitCost = 3523 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 3524 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 3525 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr, 3526 CmpInst::BAD_ICMP_PREDICATE, CostKind); 3527 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 3528 InstructionCost MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 3529 InstructionCost ValueSplitCost = 3530 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore); 3531 InstructionCost MemopCost = 3532 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3533 Alignment, AddressSpace, CostKind); 3534 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 3535 } 3536 3537 // Legalize the type. 3538 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3539 auto VT = TLI->getValueType(DL, SrcVTy); 3540 InstructionCost Cost = 0; 3541 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 3542 LT.second.getVectorNumElements() == NumElem) 3543 // Promotion requires extend/truncate for data and a shuffle for mask. 3544 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, None, 0, nullptr) + 3545 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, None, 0, nullptr); 3546 3547 else if (LT.first * LT.second.getVectorNumElements() > NumElem) { 3548 auto *NewMaskTy = FixedVectorType::get(MaskTy->getElementType(), 3549 LT.second.getVectorNumElements()); 3550 // Expanding requires fill mask with zeroes 3551 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, None, 0, MaskTy); 3552 } 3553 3554 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 3555 if (!ST->hasAVX512()) 3556 return Cost + LT.first * (IsLoad ? 2 : 8); 3557 3558 // AVX-512 masked load/store is cheapper 3559 return Cost + LT.first; 3560 } 3561 3562 InstructionCost X86TTIImpl::getAddressComputationCost(Type *Ty, 3563 ScalarEvolution *SE, 3564 const SCEV *Ptr) { 3565 // Address computations in vectorized code with non-consecutive addresses will 3566 // likely result in more instructions compared to scalar code where the 3567 // computation can more often be merged into the index mode. The resulting 3568 // extra micro-ops can significantly decrease throughput. 3569 const unsigned NumVectorInstToHideOverhead = 10; 3570 3571 // Cost modeling of Strided Access Computation is hidden by the indexing 3572 // modes of X86 regardless of the stride value. We dont believe that there 3573 // is a difference between constant strided access in gerenal and constant 3574 // strided value which is less than or equal to 64. 3575 // Even in the case of (loop invariant) stride whose value is not known at 3576 // compile time, the address computation will not incur more than one extra 3577 // ADD instruction. 3578 if (Ty->isVectorTy() && SE) { 3579 if (!BaseT::isStridedAccess(Ptr)) 3580 return NumVectorInstToHideOverhead; 3581 if (!BaseT::getConstantStrideStep(SE, Ptr)) 3582 return 1; 3583 } 3584 3585 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 3586 } 3587 3588 InstructionCost 3589 X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 3590 bool IsPairwise, 3591 TTI::TargetCostKind CostKind) { 3592 // Just use the default implementation for pair reductions. 3593 if (IsPairwise) 3594 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise, CostKind); 3595 3596 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3597 // and make it as the cost. 3598 3599 static const CostTblEntry SLMCostTblNoPairWise[] = { 3600 { ISD::FADD, MVT::v2f64, 3 }, 3601 { ISD::ADD, MVT::v2i64, 5 }, 3602 }; 3603 3604 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3605 { ISD::FADD, MVT::v2f64, 2 }, 3606 { ISD::FADD, MVT::v2f32, 2 }, 3607 { ISD::FADD, MVT::v4f32, 4 }, 3608 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 3609 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 3610 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 3611 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 3612 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 3613 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 3614 { ISD::ADD, MVT::v2i8, 2 }, 3615 { ISD::ADD, MVT::v4i8, 2 }, 3616 { ISD::ADD, MVT::v8i8, 2 }, 3617 { ISD::ADD, MVT::v16i8, 3 }, 3618 }; 3619 3620 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3621 { ISD::FADD, MVT::v4f64, 3 }, 3622 { ISD::FADD, MVT::v4f32, 3 }, 3623 { ISD::FADD, MVT::v8f32, 4 }, 3624 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 3625 { ISD::ADD, MVT::v4i64, 3 }, 3626 { ISD::ADD, MVT::v8i32, 5 }, 3627 { ISD::ADD, MVT::v16i16, 5 }, 3628 { ISD::ADD, MVT::v32i8, 4 }, 3629 }; 3630 3631 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3632 assert(ISD && "Invalid opcode"); 3633 3634 // Before legalizing the type, give a chance to look up illegal narrow types 3635 // in the table. 3636 // FIXME: Is there a better way to do this? 3637 EVT VT = TLI->getValueType(DL, ValTy); 3638 if (VT.isSimple()) { 3639 MVT MTy = VT.getSimpleVT(); 3640 if (ST->isSLM()) 3641 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3642 return Entry->Cost; 3643 3644 if (ST->hasAVX()) 3645 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3646 return Entry->Cost; 3647 3648 if (ST->hasSSE2()) 3649 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3650 return Entry->Cost; 3651 } 3652 3653 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3654 3655 MVT MTy = LT.second; 3656 3657 auto *ValVTy = cast<FixedVectorType>(ValTy); 3658 3659 // Special case: vXi8 mul reductions are performed as vXi16. 3660 if (ISD == ISD::MUL && MTy.getScalarType() == MVT::i8) { 3661 auto *WideSclTy = IntegerType::get(ValVTy->getContext(), 16); 3662 auto *WideVecTy = FixedVectorType::get(WideSclTy, ValVTy->getNumElements()); 3663 return getCastInstrCost(Instruction::ZExt, WideVecTy, ValTy, 3664 TargetTransformInfo::CastContextHint::None, 3665 CostKind) + 3666 getArithmeticReductionCost(Opcode, WideVecTy, IsPairwise, CostKind); 3667 } 3668 3669 InstructionCost ArithmeticCost = 0; 3670 if (LT.first != 1 && MTy.isVector() && 3671 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3672 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3673 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3674 MTy.getVectorNumElements()); 3675 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3676 ArithmeticCost *= LT.first - 1; 3677 } 3678 3679 if (ST->isSLM()) 3680 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3681 return ArithmeticCost + Entry->Cost; 3682 3683 if (ST->hasAVX()) 3684 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3685 return ArithmeticCost + Entry->Cost; 3686 3687 if (ST->hasSSE2()) 3688 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3689 return ArithmeticCost + Entry->Cost; 3690 3691 // FIXME: These assume a naive kshift+binop lowering, which is probably 3692 // conservative in most cases. 3693 static const CostTblEntry AVX512BoolReduction[] = { 3694 { ISD::AND, MVT::v2i1, 3 }, 3695 { ISD::AND, MVT::v4i1, 5 }, 3696 { ISD::AND, MVT::v8i1, 7 }, 3697 { ISD::AND, MVT::v16i1, 9 }, 3698 { ISD::AND, MVT::v32i1, 11 }, 3699 { ISD::AND, MVT::v64i1, 13 }, 3700 { ISD::OR, MVT::v2i1, 3 }, 3701 { ISD::OR, MVT::v4i1, 5 }, 3702 { ISD::OR, MVT::v8i1, 7 }, 3703 { ISD::OR, MVT::v16i1, 9 }, 3704 { ISD::OR, MVT::v32i1, 11 }, 3705 { ISD::OR, MVT::v64i1, 13 }, 3706 }; 3707 3708 static const CostTblEntry AVX2BoolReduction[] = { 3709 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 3710 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 3711 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 3712 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 3713 }; 3714 3715 static const CostTblEntry AVX1BoolReduction[] = { 3716 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 3717 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 3718 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3719 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3720 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 3721 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 3722 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3723 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3724 }; 3725 3726 static const CostTblEntry SSE2BoolReduction[] = { 3727 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 3728 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 3729 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 3730 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 3731 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 3732 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 3733 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 3734 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 3735 }; 3736 3737 // Handle bool allof/anyof patterns. 3738 if (ValVTy->getElementType()->isIntegerTy(1)) { 3739 InstructionCost ArithmeticCost = 0; 3740 if (LT.first != 1 && MTy.isVector() && 3741 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3742 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3743 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3744 MTy.getVectorNumElements()); 3745 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3746 ArithmeticCost *= LT.first - 1; 3747 } 3748 3749 if (ST->hasAVX512()) 3750 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 3751 return ArithmeticCost + Entry->Cost; 3752 if (ST->hasAVX2()) 3753 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 3754 return ArithmeticCost + Entry->Cost; 3755 if (ST->hasAVX()) 3756 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 3757 return ArithmeticCost + Entry->Cost; 3758 if (ST->hasSSE2()) 3759 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 3760 return ArithmeticCost + Entry->Cost; 3761 3762 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise, 3763 CostKind); 3764 } 3765 3766 unsigned NumVecElts = ValVTy->getNumElements(); 3767 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 3768 3769 // Special case power of 2 reductions where the scalar type isn't changed 3770 // by type legalization. 3771 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 3772 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise, 3773 CostKind); 3774 3775 InstructionCost ReductionCost = 0; 3776 3777 auto *Ty = ValVTy; 3778 if (LT.first != 1 && MTy.isVector() && 3779 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3780 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3781 Ty = FixedVectorType::get(ValVTy->getElementType(), 3782 MTy.getVectorNumElements()); 3783 ReductionCost = getArithmeticInstrCost(Opcode, Ty, CostKind); 3784 ReductionCost *= LT.first - 1; 3785 NumVecElts = MTy.getVectorNumElements(); 3786 } 3787 3788 // Now handle reduction with the legal type, taking into account size changes 3789 // at each level. 3790 while (NumVecElts > 1) { 3791 // Determine the size of the remaining vector we need to reduce. 3792 unsigned Size = NumVecElts * ScalarSize; 3793 NumVecElts /= 2; 3794 // If we're reducing from 256/512 bits, use an extract_subvector. 3795 if (Size > 128) { 3796 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 3797 ReductionCost += 3798 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 3799 Ty = SubTy; 3800 } else if (Size == 128) { 3801 // Reducing from 128 bits is a permute of v2f64/v2i64. 3802 FixedVectorType *ShufTy; 3803 if (ValVTy->isFloatingPointTy()) 3804 ShufTy = 3805 FixedVectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 3806 else 3807 ShufTy = 3808 FixedVectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 3809 ReductionCost += 3810 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3811 } else if (Size == 64) { 3812 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3813 FixedVectorType *ShufTy; 3814 if (ValVTy->isFloatingPointTy()) 3815 ShufTy = 3816 FixedVectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 3817 else 3818 ShufTy = 3819 FixedVectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 3820 ReductionCost += 3821 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3822 } else { 3823 // Reducing from smaller size is a shift by immediate. 3824 auto *ShiftTy = FixedVectorType::get( 3825 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 3826 ReductionCost += getArithmeticInstrCost( 3827 Instruction::LShr, ShiftTy, CostKind, 3828 TargetTransformInfo::OK_AnyValue, 3829 TargetTransformInfo::OK_UniformConstantValue, 3830 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3831 } 3832 3833 // Add the arithmetic op for this level. 3834 ReductionCost += getArithmeticInstrCost(Opcode, Ty, CostKind); 3835 } 3836 3837 // Add the final extract element to the cost. 3838 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3839 } 3840 3841 InstructionCost X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, 3842 bool IsUnsigned) { 3843 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3844 3845 MVT MTy = LT.second; 3846 3847 int ISD; 3848 if (Ty->isIntOrIntVectorTy()) { 3849 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3850 } else { 3851 assert(Ty->isFPOrFPVectorTy() && 3852 "Expected float point or integer vector type."); 3853 ISD = ISD::FMINNUM; 3854 } 3855 3856 static const CostTblEntry SSE1CostTbl[] = { 3857 {ISD::FMINNUM, MVT::v4f32, 1}, 3858 }; 3859 3860 static const CostTblEntry SSE2CostTbl[] = { 3861 {ISD::FMINNUM, MVT::v2f64, 1}, 3862 {ISD::SMIN, MVT::v8i16, 1}, 3863 {ISD::UMIN, MVT::v16i8, 1}, 3864 }; 3865 3866 static const CostTblEntry SSE41CostTbl[] = { 3867 {ISD::SMIN, MVT::v4i32, 1}, 3868 {ISD::UMIN, MVT::v4i32, 1}, 3869 {ISD::UMIN, MVT::v8i16, 1}, 3870 {ISD::SMIN, MVT::v16i8, 1}, 3871 }; 3872 3873 static const CostTblEntry SSE42CostTbl[] = { 3874 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 3875 }; 3876 3877 static const CostTblEntry AVX1CostTbl[] = { 3878 {ISD::FMINNUM, MVT::v8f32, 1}, 3879 {ISD::FMINNUM, MVT::v4f64, 1}, 3880 {ISD::SMIN, MVT::v8i32, 3}, 3881 {ISD::UMIN, MVT::v8i32, 3}, 3882 {ISD::SMIN, MVT::v16i16, 3}, 3883 {ISD::UMIN, MVT::v16i16, 3}, 3884 {ISD::SMIN, MVT::v32i8, 3}, 3885 {ISD::UMIN, MVT::v32i8, 3}, 3886 }; 3887 3888 static const CostTblEntry AVX2CostTbl[] = { 3889 {ISD::SMIN, MVT::v8i32, 1}, 3890 {ISD::UMIN, MVT::v8i32, 1}, 3891 {ISD::SMIN, MVT::v16i16, 1}, 3892 {ISD::UMIN, MVT::v16i16, 1}, 3893 {ISD::SMIN, MVT::v32i8, 1}, 3894 {ISD::UMIN, MVT::v32i8, 1}, 3895 }; 3896 3897 static const CostTblEntry AVX512CostTbl[] = { 3898 {ISD::FMINNUM, MVT::v16f32, 1}, 3899 {ISD::FMINNUM, MVT::v8f64, 1}, 3900 {ISD::SMIN, MVT::v2i64, 1}, 3901 {ISD::UMIN, MVT::v2i64, 1}, 3902 {ISD::SMIN, MVT::v4i64, 1}, 3903 {ISD::UMIN, MVT::v4i64, 1}, 3904 {ISD::SMIN, MVT::v8i64, 1}, 3905 {ISD::UMIN, MVT::v8i64, 1}, 3906 {ISD::SMIN, MVT::v16i32, 1}, 3907 {ISD::UMIN, MVT::v16i32, 1}, 3908 }; 3909 3910 static const CostTblEntry AVX512BWCostTbl[] = { 3911 {ISD::SMIN, MVT::v32i16, 1}, 3912 {ISD::UMIN, MVT::v32i16, 1}, 3913 {ISD::SMIN, MVT::v64i8, 1}, 3914 {ISD::UMIN, MVT::v64i8, 1}, 3915 }; 3916 3917 // If we have a native MIN/MAX instruction for this type, use it. 3918 if (ST->hasBWI()) 3919 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3920 return LT.first * Entry->Cost; 3921 3922 if (ST->hasAVX512()) 3923 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3924 return LT.first * Entry->Cost; 3925 3926 if (ST->hasAVX2()) 3927 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3928 return LT.first * Entry->Cost; 3929 3930 if (ST->hasAVX()) 3931 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3932 return LT.first * Entry->Cost; 3933 3934 if (ST->hasSSE42()) 3935 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3936 return LT.first * Entry->Cost; 3937 3938 if (ST->hasSSE41()) 3939 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3940 return LT.first * Entry->Cost; 3941 3942 if (ST->hasSSE2()) 3943 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3944 return LT.first * Entry->Cost; 3945 3946 if (ST->hasSSE1()) 3947 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3948 return LT.first * Entry->Cost; 3949 3950 unsigned CmpOpcode; 3951 if (Ty->isFPOrFPVectorTy()) { 3952 CmpOpcode = Instruction::FCmp; 3953 } else { 3954 assert(Ty->isIntOrIntVectorTy() && 3955 "expecting floating point or integer type for min/max reduction"); 3956 CmpOpcode = Instruction::ICmp; 3957 } 3958 3959 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 3960 // Otherwise fall back to cmp+select. 3961 InstructionCost Result = 3962 getCmpSelInstrCost(CmpOpcode, Ty, CondTy, CmpInst::BAD_ICMP_PREDICATE, 3963 CostKind) + 3964 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, 3965 CmpInst::BAD_ICMP_PREDICATE, CostKind); 3966 return Result; 3967 } 3968 3969 InstructionCost 3970 X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 3971 bool IsPairwise, bool IsUnsigned, 3972 TTI::TargetCostKind CostKind) { 3973 // Just use the default implementation for pair reductions. 3974 if (IsPairwise) 3975 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned, 3976 CostKind); 3977 3978 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3979 3980 MVT MTy = LT.second; 3981 3982 int ISD; 3983 if (ValTy->isIntOrIntVectorTy()) { 3984 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3985 } else { 3986 assert(ValTy->isFPOrFPVectorTy() && 3987 "Expected float point or integer vector type."); 3988 ISD = ISD::FMINNUM; 3989 } 3990 3991 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3992 // and make it as the cost. 3993 3994 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3995 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 3996 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 3997 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 3998 }; 3999 4000 static const CostTblEntry SSE41CostTblNoPairWise[] = { 4001 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 4002 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 4003 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 4004 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 4005 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 4006 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 4007 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 4008 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 4009 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 4010 {ISD::SMIN, MVT::v16i8, 6}, 4011 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 4012 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 4013 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 4014 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 4015 }; 4016 4017 static const CostTblEntry AVX1CostTblNoPairWise[] = { 4018 {ISD::SMIN, MVT::v16i16, 6}, 4019 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 4020 {ISD::SMIN, MVT::v32i8, 8}, 4021 {ISD::UMIN, MVT::v32i8, 8}, 4022 }; 4023 4024 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 4025 {ISD::SMIN, MVT::v32i16, 8}, 4026 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 4027 {ISD::SMIN, MVT::v64i8, 10}, 4028 {ISD::UMIN, MVT::v64i8, 10}, 4029 }; 4030 4031 // Before legalizing the type, give a chance to look up illegal narrow types 4032 // in the table. 4033 // FIXME: Is there a better way to do this? 4034 EVT VT = TLI->getValueType(DL, ValTy); 4035 if (VT.isSimple()) { 4036 MVT MTy = VT.getSimpleVT(); 4037 if (ST->hasBWI()) 4038 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4039 return Entry->Cost; 4040 4041 if (ST->hasAVX()) 4042 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4043 return Entry->Cost; 4044 4045 if (ST->hasSSE41()) 4046 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4047 return Entry->Cost; 4048 4049 if (ST->hasSSE2()) 4050 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4051 return Entry->Cost; 4052 } 4053 4054 auto *ValVTy = cast<FixedVectorType>(ValTy); 4055 unsigned NumVecElts = ValVTy->getNumElements(); 4056 4057 auto *Ty = ValVTy; 4058 InstructionCost MinMaxCost = 0; 4059 if (LT.first != 1 && MTy.isVector() && 4060 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4061 // Type needs to be split. We need LT.first - 1 operations ops. 4062 Ty = FixedVectorType::get(ValVTy->getElementType(), 4063 MTy.getVectorNumElements()); 4064 auto *SubCondTy = FixedVectorType::get(CondTy->getElementType(), 4065 MTy.getVectorNumElements()); 4066 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4067 MinMaxCost *= LT.first - 1; 4068 NumVecElts = MTy.getVectorNumElements(); 4069 } 4070 4071 if (ST->hasBWI()) 4072 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4073 return MinMaxCost + Entry->Cost; 4074 4075 if (ST->hasAVX()) 4076 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4077 return MinMaxCost + Entry->Cost; 4078 4079 if (ST->hasSSE41()) 4080 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4081 return MinMaxCost + Entry->Cost; 4082 4083 if (ST->hasSSE2()) 4084 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4085 return MinMaxCost + Entry->Cost; 4086 4087 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 4088 4089 // Special case power of 2 reductions where the scalar type isn't changed 4090 // by type legalization. 4091 if (!isPowerOf2_32(ValVTy->getNumElements()) || 4092 ScalarSize != MTy.getScalarSizeInBits()) 4093 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned, 4094 CostKind); 4095 4096 // Now handle reduction with the legal type, taking into account size changes 4097 // at each level. 4098 while (NumVecElts > 1) { 4099 // Determine the size of the remaining vector we need to reduce. 4100 unsigned Size = NumVecElts * ScalarSize; 4101 NumVecElts /= 2; 4102 // If we're reducing from 256/512 bits, use an extract_subvector. 4103 if (Size > 128) { 4104 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 4105 MinMaxCost += 4106 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 4107 Ty = SubTy; 4108 } else if (Size == 128) { 4109 // Reducing from 128 bits is a permute of v2f64/v2i64. 4110 VectorType *ShufTy; 4111 if (ValTy->isFloatingPointTy()) 4112 ShufTy = 4113 FixedVectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 4114 else 4115 ShufTy = FixedVectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 4116 MinMaxCost += 4117 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4118 } else if (Size == 64) { 4119 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 4120 FixedVectorType *ShufTy; 4121 if (ValTy->isFloatingPointTy()) 4122 ShufTy = FixedVectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 4123 else 4124 ShufTy = FixedVectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 4125 MinMaxCost += 4126 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4127 } else { 4128 // Reducing from smaller size is a shift by immediate. 4129 auto *ShiftTy = FixedVectorType::get( 4130 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 4131 MinMaxCost += getArithmeticInstrCost( 4132 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, 4133 TargetTransformInfo::OK_AnyValue, 4134 TargetTransformInfo::OK_UniformConstantValue, 4135 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 4136 } 4137 4138 // Add the arithmetic op for this level. 4139 auto *SubCondTy = 4140 FixedVectorType::get(CondTy->getElementType(), Ty->getNumElements()); 4141 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4142 } 4143 4144 // Add the final extract element to the cost. 4145 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 4146 } 4147 4148 /// Calculate the cost of materializing a 64-bit value. This helper 4149 /// method might only calculate a fraction of a larger immediate. Therefore it 4150 /// is valid to return a cost of ZERO. 4151 InstructionCost X86TTIImpl::getIntImmCost(int64_t Val) { 4152 if (Val == 0) 4153 return TTI::TCC_Free; 4154 4155 if (isInt<32>(Val)) 4156 return TTI::TCC_Basic; 4157 4158 return 2 * TTI::TCC_Basic; 4159 } 4160 4161 InstructionCost X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 4162 TTI::TargetCostKind CostKind) { 4163 assert(Ty->isIntegerTy()); 4164 4165 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4166 if (BitSize == 0) 4167 return ~0U; 4168 4169 // Never hoist constants larger than 128bit, because this might lead to 4170 // incorrect code generation or assertions in codegen. 4171 // Fixme: Create a cost model for types larger than i128 once the codegen 4172 // issues have been fixed. 4173 if (BitSize > 128) 4174 return TTI::TCC_Free; 4175 4176 if (Imm == 0) 4177 return TTI::TCC_Free; 4178 4179 // Sign-extend all constants to a multiple of 64-bit. 4180 APInt ImmVal = Imm; 4181 if (BitSize % 64 != 0) 4182 ImmVal = Imm.sext(alignTo(BitSize, 64)); 4183 4184 // Split the constant into 64-bit chunks and calculate the cost for each 4185 // chunk. 4186 InstructionCost Cost = 0; 4187 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 4188 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 4189 int64_t Val = Tmp.getSExtValue(); 4190 Cost += getIntImmCost(Val); 4191 } 4192 // We need at least one instruction to materialize the constant. 4193 return std::max<InstructionCost>(1, Cost); 4194 } 4195 4196 InstructionCost X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, 4197 const APInt &Imm, Type *Ty, 4198 TTI::TargetCostKind CostKind, 4199 Instruction *Inst) { 4200 assert(Ty->isIntegerTy()); 4201 4202 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4203 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4204 // here, so that constant hoisting will ignore this constant. 4205 if (BitSize == 0) 4206 return TTI::TCC_Free; 4207 4208 unsigned ImmIdx = ~0U; 4209 switch (Opcode) { 4210 default: 4211 return TTI::TCC_Free; 4212 case Instruction::GetElementPtr: 4213 // Always hoist the base address of a GetElementPtr. This prevents the 4214 // creation of new constants for every base constant that gets constant 4215 // folded with the offset. 4216 if (Idx == 0) 4217 return 2 * TTI::TCC_Basic; 4218 return TTI::TCC_Free; 4219 case Instruction::Store: 4220 ImmIdx = 0; 4221 break; 4222 case Instruction::ICmp: 4223 // This is an imperfect hack to prevent constant hoisting of 4224 // compares that might be trying to check if a 64-bit value fits in 4225 // 32-bits. The backend can optimize these cases using a right shift by 32. 4226 // Ideally we would check the compare predicate here. There also other 4227 // similar immediates the backend can use shifts for. 4228 if (Idx == 1 && Imm.getBitWidth() == 64) { 4229 uint64_t ImmVal = Imm.getZExtValue(); 4230 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 4231 return TTI::TCC_Free; 4232 } 4233 ImmIdx = 1; 4234 break; 4235 case Instruction::And: 4236 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 4237 // by using a 32-bit operation with implicit zero extension. Detect such 4238 // immediates here as the normal path expects bit 31 to be sign extended. 4239 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 4240 return TTI::TCC_Free; 4241 ImmIdx = 1; 4242 break; 4243 case Instruction::Add: 4244 case Instruction::Sub: 4245 // For add/sub, we can use the opposite instruction for INT32_MIN. 4246 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 4247 return TTI::TCC_Free; 4248 ImmIdx = 1; 4249 break; 4250 case Instruction::UDiv: 4251 case Instruction::SDiv: 4252 case Instruction::URem: 4253 case Instruction::SRem: 4254 // Division by constant is typically expanded later into a different 4255 // instruction sequence. This completely changes the constants. 4256 // Report them as "free" to stop ConstantHoist from marking them as opaque. 4257 return TTI::TCC_Free; 4258 case Instruction::Mul: 4259 case Instruction::Or: 4260 case Instruction::Xor: 4261 ImmIdx = 1; 4262 break; 4263 // Always return TCC_Free for the shift value of a shift instruction. 4264 case Instruction::Shl: 4265 case Instruction::LShr: 4266 case Instruction::AShr: 4267 if (Idx == 1) 4268 return TTI::TCC_Free; 4269 break; 4270 case Instruction::Trunc: 4271 case Instruction::ZExt: 4272 case Instruction::SExt: 4273 case Instruction::IntToPtr: 4274 case Instruction::PtrToInt: 4275 case Instruction::BitCast: 4276 case Instruction::PHI: 4277 case Instruction::Call: 4278 case Instruction::Select: 4279 case Instruction::Ret: 4280 case Instruction::Load: 4281 break; 4282 } 4283 4284 if (Idx == ImmIdx) { 4285 int NumConstants = divideCeil(BitSize, 64); 4286 InstructionCost Cost = X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4287 return (Cost <= NumConstants * TTI::TCC_Basic) 4288 ? static_cast<int>(TTI::TCC_Free) 4289 : Cost; 4290 } 4291 4292 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4293 } 4294 4295 InstructionCost X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 4296 const APInt &Imm, Type *Ty, 4297 TTI::TargetCostKind CostKind) { 4298 assert(Ty->isIntegerTy()); 4299 4300 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4301 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4302 // here, so that constant hoisting will ignore this constant. 4303 if (BitSize == 0) 4304 return TTI::TCC_Free; 4305 4306 switch (IID) { 4307 default: 4308 return TTI::TCC_Free; 4309 case Intrinsic::sadd_with_overflow: 4310 case Intrinsic::uadd_with_overflow: 4311 case Intrinsic::ssub_with_overflow: 4312 case Intrinsic::usub_with_overflow: 4313 case Intrinsic::smul_with_overflow: 4314 case Intrinsic::umul_with_overflow: 4315 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 4316 return TTI::TCC_Free; 4317 break; 4318 case Intrinsic::experimental_stackmap: 4319 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4320 return TTI::TCC_Free; 4321 break; 4322 case Intrinsic::experimental_patchpoint_void: 4323 case Intrinsic::experimental_patchpoint_i64: 4324 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4325 return TTI::TCC_Free; 4326 break; 4327 } 4328 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4329 } 4330 4331 InstructionCost X86TTIImpl::getCFInstrCost(unsigned Opcode, 4332 TTI::TargetCostKind CostKind, 4333 const Instruction *I) { 4334 if (CostKind != TTI::TCK_RecipThroughput) 4335 return Opcode == Instruction::PHI ? 0 : 1; 4336 // Branches are assumed to be predicted. 4337 return 0; 4338 } 4339 4340 int X86TTIImpl::getGatherOverhead() const { 4341 // Some CPUs have more overhead for gather. The specified overhead is relative 4342 // to the Load operation. "2" is the number provided by Intel architects. This 4343 // parameter is used for cost estimation of Gather Op and comparison with 4344 // other alternatives. 4345 // TODO: Remove the explicit hasAVX512()?, That would mean we would only 4346 // enable gather with a -march. 4347 if (ST->hasAVX512() || (ST->hasAVX2() && ST->hasFastGather())) 4348 return 2; 4349 4350 return 1024; 4351 } 4352 4353 int X86TTIImpl::getScatterOverhead() const { 4354 if (ST->hasAVX512()) 4355 return 2; 4356 4357 return 1024; 4358 } 4359 4360 // Return an average cost of Gather / Scatter instruction, maybe improved later. 4361 // FIXME: Add TargetCostKind support. 4362 InstructionCost X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, 4363 const Value *Ptr, Align Alignment, 4364 unsigned AddressSpace) { 4365 4366 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 4367 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4368 4369 // Try to reduce index size from 64 bit (default for GEP) 4370 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 4371 // operation will use 16 x 64 indices which do not fit in a zmm and needs 4372 // to split. Also check that the base pointer is the same for all lanes, 4373 // and that there's at most one variable index. 4374 auto getIndexSizeInBits = [](const Value *Ptr, const DataLayout &DL) { 4375 unsigned IndexSize = DL.getPointerSizeInBits(); 4376 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 4377 if (IndexSize < 64 || !GEP) 4378 return IndexSize; 4379 4380 unsigned NumOfVarIndices = 0; 4381 const Value *Ptrs = GEP->getPointerOperand(); 4382 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 4383 return IndexSize; 4384 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 4385 if (isa<Constant>(GEP->getOperand(i))) 4386 continue; 4387 Type *IndxTy = GEP->getOperand(i)->getType(); 4388 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 4389 IndxTy = IndexVTy->getElementType(); 4390 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 4391 !isa<SExtInst>(GEP->getOperand(i))) || 4392 ++NumOfVarIndices > 1) 4393 return IndexSize; // 64 4394 } 4395 return (unsigned)32; 4396 }; 4397 4398 // Trying to reduce IndexSize to 32 bits for vector 16. 4399 // By default the IndexSize is equal to pointer size. 4400 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 4401 ? getIndexSizeInBits(Ptr, DL) 4402 : DL.getPointerSizeInBits(); 4403 4404 auto *IndexVTy = FixedVectorType::get( 4405 IntegerType::get(SrcVTy->getContext(), IndexSize), VF); 4406 std::pair<InstructionCost, MVT> IdxsLT = 4407 TLI->getTypeLegalizationCost(DL, IndexVTy); 4408 std::pair<InstructionCost, MVT> SrcLT = 4409 TLI->getTypeLegalizationCost(DL, SrcVTy); 4410 InstructionCost::CostType SplitFactor = 4411 *std::max(IdxsLT.first, SrcLT.first).getValue(); 4412 if (SplitFactor > 1) { 4413 // Handle splitting of vector of pointers 4414 auto *SplitSrcTy = 4415 FixedVectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 4416 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 4417 AddressSpace); 4418 } 4419 4420 // The gather / scatter cost is given by Intel architects. It is a rough 4421 // number since we are looking at one instruction in a time. 4422 const int GSOverhead = (Opcode == Instruction::Load) 4423 ? getGatherOverhead() 4424 : getScatterOverhead(); 4425 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4426 MaybeAlign(Alignment), AddressSpace, 4427 TTI::TCK_RecipThroughput); 4428 } 4429 4430 /// Return the cost of full scalarization of gather / scatter operation. 4431 /// 4432 /// Opcode - Load or Store instruction. 4433 /// SrcVTy - The type of the data vector that should be gathered or scattered. 4434 /// VariableMask - The mask is non-constant at compile time. 4435 /// Alignment - Alignment for one element. 4436 /// AddressSpace - pointer[s] address space. 4437 /// 4438 /// FIXME: Add TargetCostKind support. 4439 InstructionCost X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 4440 bool VariableMask, Align Alignment, 4441 unsigned AddressSpace) { 4442 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4443 APInt DemandedElts = APInt::getAllOnesValue(VF); 4444 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4445 4446 InstructionCost MaskUnpackCost = 0; 4447 if (VariableMask) { 4448 auto *MaskTy = 4449 FixedVectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 4450 MaskUnpackCost = 4451 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 4452 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 4453 Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), nullptr, 4454 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4455 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 4456 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 4457 } 4458 4459 // The cost of the scalar loads/stores. 4460 InstructionCost MemoryOpCost = 4461 VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4462 MaybeAlign(Alignment), AddressSpace, CostKind); 4463 4464 InstructionCost InsertExtractCost = 0; 4465 if (Opcode == Instruction::Load) 4466 for (unsigned i = 0; i < VF; ++i) 4467 // Add the cost of inserting each scalar load into the vector 4468 InsertExtractCost += 4469 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 4470 else 4471 for (unsigned i = 0; i < VF; ++i) 4472 // Add the cost of extracting each element out of the data vector 4473 InsertExtractCost += 4474 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 4475 4476 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 4477 } 4478 4479 /// Calculate the cost of Gather / Scatter operation 4480 InstructionCost X86TTIImpl::getGatherScatterOpCost( 4481 unsigned Opcode, Type *SrcVTy, const Value *Ptr, bool VariableMask, 4482 Align Alignment, TTI::TargetCostKind CostKind, 4483 const Instruction *I = nullptr) { 4484 if (CostKind != TTI::TCK_RecipThroughput) { 4485 if ((Opcode == Instruction::Load && 4486 isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4487 (Opcode == Instruction::Store && 4488 isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4489 return 1; 4490 return BaseT::getGatherScatterOpCost(Opcode, SrcVTy, Ptr, VariableMask, 4491 Alignment, CostKind, I); 4492 } 4493 4494 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 4495 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4496 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 4497 if (!PtrTy && Ptr->getType()->isVectorTy()) 4498 PtrTy = dyn_cast<PointerType>( 4499 cast<VectorType>(Ptr->getType())->getElementType()); 4500 assert(PtrTy && "Unexpected type for Ptr argument"); 4501 unsigned AddressSpace = PtrTy->getAddressSpace(); 4502 4503 bool Scalarize = false; 4504 if ((Opcode == Instruction::Load && 4505 !isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4506 (Opcode == Instruction::Store && 4507 !isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4508 Scalarize = true; 4509 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 4510 // Vector-4 of gather/scatter instruction does not exist on KNL. 4511 // We can extend it to 8 elements, but zeroing upper bits of 4512 // the mask vector will add more instructions. Right now we give the scalar 4513 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 4514 // is better in the VariableMask case. 4515 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 4516 Scalarize = true; 4517 4518 if (Scalarize) 4519 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 4520 AddressSpace); 4521 4522 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 4523 } 4524 4525 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 4526 TargetTransformInfo::LSRCost &C2) { 4527 // X86 specific here are "instruction number 1st priority". 4528 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 4529 C1.NumIVMuls, C1.NumBaseAdds, 4530 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 4531 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 4532 C2.NumIVMuls, C2.NumBaseAdds, 4533 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 4534 } 4535 4536 bool X86TTIImpl::canMacroFuseCmp() { 4537 return ST->hasMacroFusion() || ST->hasBranchFusion(); 4538 } 4539 4540 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, Align Alignment) { 4541 if (!ST->hasAVX()) 4542 return false; 4543 4544 // The backend can't handle a single element vector. 4545 if (isa<VectorType>(DataTy) && 4546 cast<FixedVectorType>(DataTy)->getNumElements() == 1) 4547 return false; 4548 Type *ScalarTy = DataTy->getScalarType(); 4549 4550 if (ScalarTy->isPointerTy()) 4551 return true; 4552 4553 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4554 return true; 4555 4556 if (!ScalarTy->isIntegerTy()) 4557 return false; 4558 4559 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4560 return IntWidth == 32 || IntWidth == 64 || 4561 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 4562 } 4563 4564 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, Align Alignment) { 4565 return isLegalMaskedLoad(DataType, Alignment); 4566 } 4567 4568 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 4569 unsigned DataSize = DL.getTypeStoreSize(DataType); 4570 // The only supported nontemporal loads are for aligned vectors of 16 or 32 4571 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 4572 // (the equivalent stores only require AVX). 4573 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 4574 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 4575 4576 return false; 4577 } 4578 4579 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 4580 unsigned DataSize = DL.getTypeStoreSize(DataType); 4581 4582 // SSE4A supports nontemporal stores of float and double at arbitrary 4583 // alignment. 4584 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 4585 return true; 4586 4587 // Besides the SSE4A subtarget exception above, only aligned stores are 4588 // available nontemporaly on any other subtarget. And only stores with a size 4589 // of 4..32 bytes (powers of 2, only) are permitted. 4590 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 4591 !isPowerOf2_32(DataSize)) 4592 return false; 4593 4594 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 4595 // loads require AVX2). 4596 if (DataSize == 32) 4597 return ST->hasAVX(); 4598 else if (DataSize == 16) 4599 return ST->hasSSE1(); 4600 return true; 4601 } 4602 4603 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 4604 if (!isa<VectorType>(DataTy)) 4605 return false; 4606 4607 if (!ST->hasAVX512()) 4608 return false; 4609 4610 // The backend can't handle a single element vector. 4611 if (cast<FixedVectorType>(DataTy)->getNumElements() == 1) 4612 return false; 4613 4614 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 4615 4616 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4617 return true; 4618 4619 if (!ScalarTy->isIntegerTy()) 4620 return false; 4621 4622 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4623 return IntWidth == 32 || IntWidth == 64 || 4624 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 4625 } 4626 4627 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 4628 return isLegalMaskedExpandLoad(DataTy); 4629 } 4630 4631 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, Align Alignment) { 4632 // Some CPUs have better gather performance than others. 4633 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 4634 // enable gather with a -march. 4635 if (!(ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()))) 4636 return false; 4637 4638 // This function is called now in two cases: from the Loop Vectorizer 4639 // and from the Scalarizer. 4640 // When the Loop Vectorizer asks about legality of the feature, 4641 // the vectorization factor is not calculated yet. The Loop Vectorizer 4642 // sends a scalar type and the decision is based on the width of the 4643 // scalar element. 4644 // Later on, the cost model will estimate usage this intrinsic based on 4645 // the vector type. 4646 // The Scalarizer asks again about legality. It sends a vector type. 4647 // In this case we can reject non-power-of-2 vectors. 4648 // We also reject single element vectors as the type legalizer can't 4649 // scalarize it. 4650 if (auto *DataVTy = dyn_cast<FixedVectorType>(DataTy)) { 4651 unsigned NumElts = DataVTy->getNumElements(); 4652 if (NumElts == 1) 4653 return false; 4654 } 4655 Type *ScalarTy = DataTy->getScalarType(); 4656 if (ScalarTy->isPointerTy()) 4657 return true; 4658 4659 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4660 return true; 4661 4662 if (!ScalarTy->isIntegerTy()) 4663 return false; 4664 4665 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4666 return IntWidth == 32 || IntWidth == 64; 4667 } 4668 4669 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, Align Alignment) { 4670 // AVX2 doesn't support scatter 4671 if (!ST->hasAVX512()) 4672 return false; 4673 return isLegalMaskedGather(DataType, Alignment); 4674 } 4675 4676 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 4677 EVT VT = TLI->getValueType(DL, DataType); 4678 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 4679 } 4680 4681 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 4682 return false; 4683 } 4684 4685 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 4686 const Function *Callee) const { 4687 const TargetMachine &TM = getTLI()->getTargetMachine(); 4688 4689 // Work this as a subsetting of subtarget features. 4690 const FeatureBitset &CallerBits = 4691 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 4692 const FeatureBitset &CalleeBits = 4693 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 4694 4695 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 4696 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 4697 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 4698 } 4699 4700 bool X86TTIImpl::areFunctionArgsABICompatible( 4701 const Function *Caller, const Function *Callee, 4702 SmallPtrSetImpl<Argument *> &Args) const { 4703 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args)) 4704 return false; 4705 4706 // If we get here, we know the target features match. If one function 4707 // considers 512-bit vectors legal and the other does not, consider them 4708 // incompatible. 4709 const TargetMachine &TM = getTLI()->getTargetMachine(); 4710 4711 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 4712 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs()) 4713 return true; 4714 4715 // Consider the arguments compatible if they aren't vectors or aggregates. 4716 // FIXME: Look at the size of vectors. 4717 // FIXME: Look at the element types of aggregates to see if there are vectors. 4718 // FIXME: The API of this function seems intended to allow arguments 4719 // to be removed from the set, but the caller doesn't check if the set 4720 // becomes empty so that may not work in practice. 4721 return llvm::none_of(Args, [](Argument *A) { 4722 auto *EltTy = cast<PointerType>(A->getType())->getElementType(); 4723 return EltTy->isVectorTy() || EltTy->isAggregateType(); 4724 }); 4725 } 4726 4727 X86TTIImpl::TTI::MemCmpExpansionOptions 4728 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 4729 TTI::MemCmpExpansionOptions Options; 4730 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 4731 Options.NumLoadsPerBlock = 2; 4732 // All GPR and vector loads can be unaligned. 4733 Options.AllowOverlappingLoads = true; 4734 if (IsZeroCmp) { 4735 // Only enable vector loads for equality comparison. Right now the vector 4736 // version is not as fast for three way compare (see #33329). 4737 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 4738 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 4739 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 4740 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 4741 } 4742 if (ST->is64Bit()) { 4743 Options.LoadSizes.push_back(8); 4744 } 4745 Options.LoadSizes.push_back(4); 4746 Options.LoadSizes.push_back(2); 4747 Options.LoadSizes.push_back(1); 4748 return Options; 4749 } 4750 4751 bool X86TTIImpl::enableInterleavedAccessVectorization() { 4752 // TODO: We expect this to be beneficial regardless of arch, 4753 // but there are currently some unexplained performance artifacts on Atom. 4754 // As a temporary solution, disable on Atom. 4755 return !(ST->isAtom()); 4756 } 4757 4758 // Get estimation for interleaved load/store operations for AVX2. 4759 // \p Factor is the interleaved-access factor (stride) - number of 4760 // (interleaved) elements in the group. 4761 // \p Indices contains the indices for a strided load: when the 4762 // interleaved load has gaps they indicate which elements are used. 4763 // If Indices is empty (or if the number of indices is equal to the size 4764 // of the interleaved-access as given in \p Factor) the access has no gaps. 4765 // 4766 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 4767 // computing the cost using a generic formula as a function of generic 4768 // shuffles. We therefore use a lookup table instead, filled according to 4769 // the instruction sequences that codegen currently generates. 4770 InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2( 4771 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 4772 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 4773 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 4774 4775 if (UseMaskForCond || UseMaskForGaps) 4776 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4777 Alignment, AddressSpace, CostKind, 4778 UseMaskForCond, UseMaskForGaps); 4779 4780 // We currently Support only fully-interleaved groups, with no gaps. 4781 // TODO: Support also strided loads (interleaved-groups with gaps). 4782 if (Indices.size() && Indices.size() != Factor) 4783 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4784 Alignment, AddressSpace, CostKind); 4785 4786 // VecTy for interleave memop is <VF*Factor x Elt>. 4787 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4788 // VecTy = <12 x i32>. 4789 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4790 4791 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 4792 // the VF=2, while v2i128 is an unsupported MVT vector type 4793 // (see MachineValueType.h::getVectorVT()). 4794 if (!LegalVT.isVector()) 4795 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4796 Alignment, AddressSpace, CostKind); 4797 4798 unsigned VF = VecTy->getNumElements() / Factor; 4799 Type *ScalarTy = VecTy->getElementType(); 4800 // Deduplicate entries, model floats/pointers as appropriately-sized integers. 4801 if (!ScalarTy->isIntegerTy()) 4802 ScalarTy = 4803 Type::getIntNTy(ScalarTy->getContext(), DL.getTypeSizeInBits(ScalarTy)); 4804 4805 // Get the cost of all the memory operations. 4806 InstructionCost MemOpCosts = getMemoryOpCost( 4807 Opcode, VecTy, MaybeAlign(Alignment), AddressSpace, CostKind); 4808 4809 auto *VT = FixedVectorType::get(ScalarTy, VF); 4810 EVT ETy = TLI->getValueType(DL, VT); 4811 if (!ETy.isSimple()) 4812 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4813 Alignment, AddressSpace, CostKind); 4814 4815 // TODO: Complete for other data-types and strides. 4816 // Each combination of Stride, element bit width and VF results in a different 4817 // sequence; The cost tables are therefore accessed with: 4818 // Factor (stride) and VectorType=VFxiN. 4819 // The Cost accounts only for the shuffle sequence; 4820 // The cost of the loads/stores is accounted for separately. 4821 // 4822 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 4823 {2, MVT::v4i64, 6}, // (load 8i64 and) deinterleave into 2 x 4i64 4824 4825 {3, MVT::v2i8, 10}, // (load 6i8 and) deinterleave into 3 x 2i8 4826 {3, MVT::v4i8, 4}, // (load 12i8 and) deinterleave into 3 x 4i8 4827 {3, MVT::v8i8, 9}, // (load 24i8 and) deinterleave into 3 x 8i8 4828 {3, MVT::v16i8, 11}, // (load 48i8 and) deinterleave into 3 x 16i8 4829 {3, MVT::v32i8, 13}, // (load 96i8 and) deinterleave into 3 x 32i8 4830 4831 {3, MVT::v8i32, 17}, // (load 24i32 and) deinterleave into 3 x 8i32 4832 4833 {4, MVT::v2i8, 12}, // (load 8i8 and) deinterleave into 4 x 2i8 4834 {4, MVT::v4i8, 4}, // (load 16i8 and) deinterleave into 4 x 4i8 4835 {4, MVT::v8i8, 20}, // (load 32i8 and) deinterleave into 4 x 8i8 4836 {4, MVT::v16i8, 39}, // (load 64i8 and) deinterleave into 4 x 16i8 4837 {4, MVT::v32i8, 80}, // (load 128i8 and) deinterleave into 4 x 32i8 4838 4839 {8, MVT::v8i32, 40} // (load 64i32 and) deinterleave into 8 x 8i32 4840 }; 4841 4842 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 4843 {2, MVT::v4i64, 6}, // interleave 2 x 4i64 into 8i64 (and store) 4844 4845 {3, MVT::v2i8, 7}, // interleave 3 x 2i8 into 6i8 (and store) 4846 {3, MVT::v4i8, 8}, // interleave 3 x 4i8 into 12i8 (and store) 4847 {3, MVT::v8i8, 11}, // interleave 3 x 8i8 into 24i8 (and store) 4848 {3, MVT::v16i8, 11}, // interleave 3 x 16i8 into 48i8 (and store) 4849 {3, MVT::v32i8, 13}, // interleave 3 x 32i8 into 96i8 (and store) 4850 4851 {4, MVT::v2i8, 12}, // interleave 4 x 2i8 into 8i8 (and store) 4852 {4, MVT::v4i8, 9}, // interleave 4 x 4i8 into 16i8 (and store) 4853 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 4854 {4, MVT::v16i8, 10}, // interleave 4 x 16i8 into 64i8 (and store) 4855 {4, MVT::v32i8, 12} // interleave 4 x 32i8 into 128i8 (and store) 4856 }; 4857 4858 if (Opcode == Instruction::Load) { 4859 if (const auto *Entry = 4860 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 4861 return MemOpCosts + Entry->Cost; 4862 } else { 4863 assert(Opcode == Instruction::Store && 4864 "Expected Store Instruction at this point"); 4865 if (const auto *Entry = 4866 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 4867 return MemOpCosts + Entry->Cost; 4868 } 4869 4870 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4871 Alignment, AddressSpace, CostKind); 4872 } 4873 4874 // Get estimation for interleaved load/store operations and strided load. 4875 // \p Indices contains indices for strided load. 4876 // \p Factor - the factor of interleaving. 4877 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 4878 InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX512( 4879 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 4880 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 4881 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 4882 4883 if (UseMaskForCond || UseMaskForGaps) 4884 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4885 Alignment, AddressSpace, CostKind, 4886 UseMaskForCond, UseMaskForGaps); 4887 4888 // VecTy for interleave memop is <VF*Factor x Elt>. 4889 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4890 // VecTy = <12 x i32>. 4891 4892 // Calculate the number of memory operations (NumOfMemOps), required 4893 // for load/store the VecTy. 4894 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4895 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4896 unsigned LegalVTSize = LegalVT.getStoreSize(); 4897 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4898 4899 // Get the cost of one memory operation. 4900 auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(), 4901 LegalVT.getVectorNumElements()); 4902 InstructionCost MemOpCost = getMemoryOpCost( 4903 Opcode, SingleMemOpTy, MaybeAlign(Alignment), AddressSpace, CostKind); 4904 4905 unsigned VF = VecTy->getNumElements() / Factor; 4906 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 4907 4908 if (Opcode == Instruction::Load) { 4909 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 4910 // contain the cost of the optimized shuffle sequence that the 4911 // X86InterleavedAccess pass will generate. 4912 // The cost of loads and stores are computed separately from the table. 4913 4914 // X86InterleavedAccess support only the following interleaved-access group. 4915 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 4916 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 4917 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 4918 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 4919 }; 4920 4921 if (const auto *Entry = 4922 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 4923 return NumOfMemOps * MemOpCost + Entry->Cost; 4924 //If an entry does not exist, fallback to the default implementation. 4925 4926 // Kind of shuffle depends on number of loaded values. 4927 // If we load the entire data in one register, we can use a 1-src shuffle. 4928 // Otherwise, we'll merge 2 sources in each operation. 4929 TTI::ShuffleKind ShuffleKind = 4930 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 4931 4932 InstructionCost ShuffleCost = 4933 getShuffleCost(ShuffleKind, SingleMemOpTy, None, 0, nullptr); 4934 4935 unsigned NumOfLoadsInInterleaveGrp = 4936 Indices.size() ? Indices.size() : Factor; 4937 auto *ResultTy = FixedVectorType::get(VecTy->getElementType(), 4938 VecTy->getNumElements() / Factor); 4939 InstructionCost NumOfResults = 4940 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 4941 NumOfLoadsInInterleaveGrp; 4942 4943 // About a half of the loads may be folded in shuffles when we have only 4944 // one result. If we have more than one result, we do not fold loads at all. 4945 unsigned NumOfUnfoldedLoads = 4946 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 4947 4948 // Get a number of shuffle operations per result. 4949 unsigned NumOfShufflesPerResult = 4950 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 4951 4952 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4953 // When we have more than one destination, we need additional instructions 4954 // to keep sources. 4955 InstructionCost NumOfMoves = 0; 4956 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 4957 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 4958 4959 InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 4960 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 4961 4962 return Cost; 4963 } 4964 4965 // Store. 4966 assert(Opcode == Instruction::Store && 4967 "Expected Store Instruction at this point"); 4968 // X86InterleavedAccess support only the following interleaved-access group. 4969 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 4970 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 4971 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 4972 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 4973 4974 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 4975 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 4976 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 4977 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 4978 }; 4979 4980 if (const auto *Entry = 4981 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 4982 return NumOfMemOps * MemOpCost + Entry->Cost; 4983 //If an entry does not exist, fallback to the default implementation. 4984 4985 // There is no strided stores meanwhile. And store can't be folded in 4986 // shuffle. 4987 unsigned NumOfSources = Factor; // The number of values to be merged. 4988 InstructionCost ShuffleCost = 4989 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, None, 0, nullptr); 4990 unsigned NumOfShufflesPerStore = NumOfSources - 1; 4991 4992 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4993 // We need additional instructions to keep sources. 4994 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 4995 InstructionCost Cost = 4996 NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 4997 NumOfMoves; 4998 return Cost; 4999 } 5000 5001 InstructionCost X86TTIImpl::getInterleavedMemoryOpCost( 5002 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, 5003 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, 5004 bool UseMaskForCond, bool UseMaskForGaps) { 5005 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 5006 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 5007 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 5008 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 5009 return true; 5010 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 5011 return HasBW; 5012 return false; 5013 }; 5014 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 5015 return getInterleavedMemoryOpCostAVX512( 5016 Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment, 5017 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 5018 if (ST->hasAVX2()) 5019 return getInterleavedMemoryOpCostAVX2( 5020 Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment, 5021 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 5022 5023 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5024 Alignment, AddressSpace, CostKind, 5025 UseMaskForCond, UseMaskForGaps); 5026 } 5027