1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements a TargetTransformInfo analysis pass specific to the
10 /// X86 target machine. It uses the target's detailed information to provide
11 /// more precise answers to certain TTI queries, while letting the target
12 /// independent and default TTI implementations handle the rest.
13 ///
14 //===----------------------------------------------------------------------===//
15 /// About Cost Model numbers used below it's necessary to say the following:
16 /// the numbers correspond to some "generic" X86 CPU instead of usage of
17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature
18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in
19 /// the lookups below the cost is based on Nehalem as that was the first CPU
20 /// to support that feature level and thus has most likely the worst case cost.
21 /// Some examples of other technologies/CPUs:
22 ///   SSE 3   - Pentium4 / Athlon64
23 ///   SSE 4.1 - Penryn
24 ///   SSE 4.2 - Nehalem
25 ///   AVX     - Sandy Bridge
26 ///   AVX2    - Haswell
27 ///   AVX-512 - Xeon Phi / Skylake
28 /// And some examples of instruction target dependent costs (latency)
29 ///                   divss     sqrtss          rsqrtss
30 ///   AMD K7            11-16     19              3
31 ///   Piledriver        9-24      13-15           5
32 ///   Jaguar            14        16              2
33 ///   Pentium II,III    18        30              2
34 ///   Nehalem           7-14      7-18            3
35 ///   Haswell           10-13     11              5
36 /// TODO: Develop and implement  the target dependent cost model and
37 /// specialize cost numbers for different Cost Model Targets such as throughput,
38 /// code size, latency and uop count.
39 //===----------------------------------------------------------------------===//
40 
41 #include "X86TargetTransformInfo.h"
42 #include "llvm/Analysis/TargetTransformInfo.h"
43 #include "llvm/CodeGen/BasicTTIImpl.h"
44 #include "llvm/CodeGen/CostTable.h"
45 #include "llvm/CodeGen/TargetLowering.h"
46 #include "llvm/IR/IntrinsicInst.h"
47 #include "llvm/Support/Debug.h"
48 
49 using namespace llvm;
50 
51 #define DEBUG_TYPE "x86tti"
52 
53 //===----------------------------------------------------------------------===//
54 //
55 // X86 cost model.
56 //
57 //===----------------------------------------------------------------------===//
58 
59 TargetTransformInfo::PopcntSupportKind
60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) {
61   assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
62   // TODO: Currently the __builtin_popcount() implementation using SSE3
63   //   instructions is inefficient. Once the problem is fixed, we should
64   //   call ST->hasSSE3() instead of ST->hasPOPCNT().
65   return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software;
66 }
67 
68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize(
69   TargetTransformInfo::CacheLevel Level) const {
70   switch (Level) {
71   case TargetTransformInfo::CacheLevel::L1D:
72     //   - Penryn
73     //   - Nehalem
74     //   - Westmere
75     //   - Sandy Bridge
76     //   - Ivy Bridge
77     //   - Haswell
78     //   - Broadwell
79     //   - Skylake
80     //   - Kabylake
81     return 32 * 1024;  //  32 KByte
82   case TargetTransformInfo::CacheLevel::L2D:
83     //   - Penryn
84     //   - Nehalem
85     //   - Westmere
86     //   - Sandy Bridge
87     //   - Ivy Bridge
88     //   - Haswell
89     //   - Broadwell
90     //   - Skylake
91     //   - Kabylake
92     return 256 * 1024; // 256 KByte
93   }
94 
95   llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
96 }
97 
98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity(
99   TargetTransformInfo::CacheLevel Level) const {
100   //   - Penryn
101   //   - Nehalem
102   //   - Westmere
103   //   - Sandy Bridge
104   //   - Ivy Bridge
105   //   - Haswell
106   //   - Broadwell
107   //   - Skylake
108   //   - Kabylake
109   switch (Level) {
110   case TargetTransformInfo::CacheLevel::L1D:
111     LLVM_FALLTHROUGH;
112   case TargetTransformInfo::CacheLevel::L2D:
113     return 8;
114   }
115 
116   llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
117 }
118 
119 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const {
120   bool Vector = (ClassID == 1);
121   if (Vector && !ST->hasSSE1())
122     return 0;
123 
124   if (ST->is64Bit()) {
125     if (Vector && ST->hasAVX512())
126       return 32;
127     return 16;
128   }
129   return 8;
130 }
131 
132 TypeSize
133 X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
134   unsigned PreferVectorWidth = ST->getPreferVectorWidth();
135   switch (K) {
136   case TargetTransformInfo::RGK_Scalar:
137     return TypeSize::getFixed(ST->is64Bit() ? 64 : 32);
138   case TargetTransformInfo::RGK_FixedWidthVector:
139     if (ST->hasAVX512() && PreferVectorWidth >= 512)
140       return TypeSize::getFixed(512);
141     if (ST->hasAVX() && PreferVectorWidth >= 256)
142       return TypeSize::getFixed(256);
143     if (ST->hasSSE1() && PreferVectorWidth >= 128)
144       return TypeSize::getFixed(128);
145     return TypeSize::getFixed(0);
146   case TargetTransformInfo::RGK_ScalableVector:
147     return TypeSize::getScalable(0);
148   }
149 
150   llvm_unreachable("Unsupported register kind");
151 }
152 
153 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const {
154   return getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector)
155       .getFixedSize();
156 }
157 
158 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) {
159   // If the loop will not be vectorized, don't interleave the loop.
160   // Let regular unroll to unroll the loop, which saves the overflow
161   // check and memory check cost.
162   if (VF == 1)
163     return 1;
164 
165   if (ST->isAtom())
166     return 1;
167 
168   // Sandybridge and Haswell have multiple execution ports and pipelined
169   // vector units.
170   if (ST->hasAVX())
171     return 4;
172 
173   return 2;
174 }
175 
176 InstructionCost X86TTIImpl::getArithmeticInstrCost(
177     unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
178     TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info,
179     TTI::OperandValueProperties Opd1PropInfo,
180     TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args,
181     const Instruction *CxtI) {
182   // TODO: Handle more cost kinds.
183   if (CostKind != TTI::TCK_RecipThroughput)
184     return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
185                                          Op2Info, Opd1PropInfo,
186                                          Opd2PropInfo, Args, CxtI);
187 
188   // vXi8 multiplications are always promoted to vXi16.
189   if (Opcode == Instruction::Mul && Ty->isVectorTy() &&
190       Ty->getScalarSizeInBits() == 8) {
191     Type *WideVecTy =
192         VectorType::getExtendedElementVectorType(cast<VectorType>(Ty));
193     return getCastInstrCost(Instruction::ZExt, WideVecTy, Ty,
194                             TargetTransformInfo::CastContextHint::None,
195                             CostKind) +
196            getCastInstrCost(Instruction::Trunc, Ty, WideVecTy,
197                             TargetTransformInfo::CastContextHint::None,
198                             CostKind) +
199            getArithmeticInstrCost(Opcode, WideVecTy, CostKind, Op1Info, Op2Info,
200                                   Opd1PropInfo, Opd2PropInfo);
201   }
202 
203   // Legalize the type.
204   std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
205 
206   int ISD = TLI->InstructionOpcodeToISD(Opcode);
207   assert(ISD && "Invalid opcode");
208 
209   static const CostTblEntry GLMCostTable[] = {
210     { ISD::FDIV,  MVT::f32,   18 }, // divss
211     { ISD::FDIV,  MVT::v4f32, 35 }, // divps
212     { ISD::FDIV,  MVT::f64,   33 }, // divsd
213     { ISD::FDIV,  MVT::v2f64, 65 }, // divpd
214   };
215 
216   if (ST->useGLMDivSqrtCosts())
217     if (const auto *Entry = CostTableLookup(GLMCostTable, ISD,
218                                             LT.second))
219       return LT.first * Entry->Cost;
220 
221   static const CostTblEntry SLMCostTable[] = {
222     { ISD::MUL,   MVT::v4i32, 11 }, // pmulld
223     { ISD::MUL,   MVT::v8i16, 2  }, // pmullw
224     { ISD::FMUL,  MVT::f64,   2  }, // mulsd
225     { ISD::FMUL,  MVT::v2f64, 4  }, // mulpd
226     { ISD::FMUL,  MVT::v4f32, 2  }, // mulps
227     { ISD::FDIV,  MVT::f32,   17 }, // divss
228     { ISD::FDIV,  MVT::v4f32, 39 }, // divps
229     { ISD::FDIV,  MVT::f64,   32 }, // divsd
230     { ISD::FDIV,  MVT::v2f64, 69 }, // divpd
231     { ISD::FADD,  MVT::v2f64, 2  }, // addpd
232     { ISD::FSUB,  MVT::v2f64, 2  }, // subpd
233     // v2i64/v4i64 mul is custom lowered as a series of long:
234     // multiplies(3), shifts(3) and adds(2)
235     // slm muldq version throughput is 2 and addq throughput 4
236     // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) +
237     //       3X4 (addq throughput) = 17
238     { ISD::MUL,   MVT::v2i64, 17 },
239     // slm addq\subq throughput is 4
240     { ISD::ADD,   MVT::v2i64, 4  },
241     { ISD::SUB,   MVT::v2i64, 4  },
242   };
243 
244   if (ST->isSLM()) {
245     if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) {
246       // Check if the operands can be shrinked into a smaller datatype.
247       bool Op1Signed = false;
248       unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed);
249       bool Op2Signed = false;
250       unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed);
251 
252       bool SignedMode = Op1Signed || Op2Signed;
253       unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize);
254 
255       if (OpMinSize <= 7)
256         return LT.first * 3; // pmullw/sext
257       if (!SignedMode && OpMinSize <= 8)
258         return LT.first * 3; // pmullw/zext
259       if (OpMinSize <= 15)
260         return LT.first * 5; // pmullw/pmulhw/pshuf
261       if (!SignedMode && OpMinSize <= 16)
262         return LT.first * 5; // pmullw/pmulhw/pshuf
263     }
264 
265     if (const auto *Entry = CostTableLookup(SLMCostTable, ISD,
266                                             LT.second)) {
267       return LT.first * Entry->Cost;
268     }
269   }
270 
271   if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV ||
272        ISD == ISD::UREM) &&
273       (Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
274        Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) &&
275       Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) {
276     if (ISD == ISD::SDIV || ISD == ISD::SREM) {
277       // On X86, vector signed division by constants power-of-two are
278       // normally expanded to the sequence SRA + SRL + ADD + SRA.
279       // The OperandValue properties may not be the same as that of the previous
280       // operation; conservatively assume OP_None.
281       InstructionCost Cost =
282           2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Op1Info,
283                                      Op2Info, TargetTransformInfo::OP_None,
284                                      TargetTransformInfo::OP_None);
285       Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info,
286                                      Op2Info,
287                                      TargetTransformInfo::OP_None,
288                                      TargetTransformInfo::OP_None);
289       Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind, Op1Info,
290                                      Op2Info,
291                                      TargetTransformInfo::OP_None,
292                                      TargetTransformInfo::OP_None);
293 
294       if (ISD == ISD::SREM) {
295         // For SREM: (X % C) is the equivalent of (X - (X/C)*C)
296         Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info,
297                                        Op2Info);
298         Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info,
299                                        Op2Info);
300       }
301 
302       return Cost;
303     }
304 
305     // Vector unsigned division/remainder will be simplified to shifts/masks.
306     if (ISD == ISD::UDIV)
307       return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind,
308                                     Op1Info, Op2Info,
309                                     TargetTransformInfo::OP_None,
310                                     TargetTransformInfo::OP_None);
311 
312     else // UREM
313       return getArithmeticInstrCost(Instruction::And, Ty, CostKind,
314                                     Op1Info, Op2Info,
315                                     TargetTransformInfo::OP_None,
316                                     TargetTransformInfo::OP_None);
317   }
318 
319   static const CostTblEntry AVX512BWUniformConstCostTable[] = {
320     { ISD::SHL,  MVT::v64i8,   2 }, // psllw + pand.
321     { ISD::SRL,  MVT::v64i8,   2 }, // psrlw + pand.
322     { ISD::SRA,  MVT::v64i8,   4 }, // psrlw, pand, pxor, psubb.
323   };
324 
325   if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
326       ST->hasBWI()) {
327     if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD,
328                                             LT.second))
329       return LT.first * Entry->Cost;
330   }
331 
332   static const CostTblEntry AVX512UniformConstCostTable[] = {
333     { ISD::SRA,  MVT::v2i64,   1 },
334     { ISD::SRA,  MVT::v4i64,   1 },
335     { ISD::SRA,  MVT::v8i64,   1 },
336 
337     { ISD::SHL,  MVT::v64i8,   4 }, // psllw + pand.
338     { ISD::SRL,  MVT::v64i8,   4 }, // psrlw + pand.
339     { ISD::SRA,  MVT::v64i8,   8 }, // psrlw, pand, pxor, psubb.
340 
341     { ISD::SDIV, MVT::v16i32,  6 }, // pmuludq sequence
342     { ISD::SREM, MVT::v16i32,  8 }, // pmuludq+mul+sub sequence
343     { ISD::UDIV, MVT::v16i32,  5 }, // pmuludq sequence
344     { ISD::UREM, MVT::v16i32,  7 }, // pmuludq+mul+sub sequence
345   };
346 
347   if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
348       ST->hasAVX512()) {
349     if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD,
350                                             LT.second))
351       return LT.first * Entry->Cost;
352   }
353 
354   static const CostTblEntry AVX2UniformConstCostTable[] = {
355     { ISD::SHL,  MVT::v32i8,   2 }, // psllw + pand.
356     { ISD::SRL,  MVT::v32i8,   2 }, // psrlw + pand.
357     { ISD::SRA,  MVT::v32i8,   4 }, // psrlw, pand, pxor, psubb.
358 
359     { ISD::SRA,  MVT::v4i64,   4 }, // 2 x psrad + shuffle.
360 
361     { ISD::SDIV, MVT::v8i32,   6 }, // pmuludq sequence
362     { ISD::SREM, MVT::v8i32,   8 }, // pmuludq+mul+sub sequence
363     { ISD::UDIV, MVT::v8i32,   5 }, // pmuludq sequence
364     { ISD::UREM, MVT::v8i32,   7 }, // pmuludq+mul+sub sequence
365   };
366 
367   if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
368       ST->hasAVX2()) {
369     if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD,
370                                             LT.second))
371       return LT.first * Entry->Cost;
372   }
373 
374   static const CostTblEntry SSE2UniformConstCostTable[] = {
375     { ISD::SHL,  MVT::v16i8,     2 }, // psllw + pand.
376     { ISD::SRL,  MVT::v16i8,     2 }, // psrlw + pand.
377     { ISD::SRA,  MVT::v16i8,     4 }, // psrlw, pand, pxor, psubb.
378 
379     { ISD::SHL,  MVT::v32i8,   4+2 }, // 2*(psllw + pand) + split.
380     { ISD::SRL,  MVT::v32i8,   4+2 }, // 2*(psrlw + pand) + split.
381     { ISD::SRA,  MVT::v32i8,   8+2 }, // 2*(psrlw, pand, pxor, psubb) + split.
382 
383     { ISD::SDIV, MVT::v8i32,  12+2 }, // 2*pmuludq sequence + split.
384     { ISD::SREM, MVT::v8i32,  16+2 }, // 2*pmuludq+mul+sub sequence + split.
385     { ISD::SDIV, MVT::v4i32,     6 }, // pmuludq sequence
386     { ISD::SREM, MVT::v4i32,     8 }, // pmuludq+mul+sub sequence
387     { ISD::UDIV, MVT::v8i32,  10+2 }, // 2*pmuludq sequence + split.
388     { ISD::UREM, MVT::v8i32,  14+2 }, // 2*pmuludq+mul+sub sequence + split.
389     { ISD::UDIV, MVT::v4i32,     5 }, // pmuludq sequence
390     { ISD::UREM, MVT::v4i32,     7 }, // pmuludq+mul+sub sequence
391   };
392 
393   // XOP has faster vXi8 shifts.
394   if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
395       ST->hasSSE2() && !ST->hasXOP()) {
396     if (const auto *Entry =
397             CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second))
398       return LT.first * Entry->Cost;
399   }
400 
401   static const CostTblEntry AVX512BWConstCostTable[] = {
402     { ISD::SDIV, MVT::v64i8,  14 }, // 2*ext+2*pmulhw sequence
403     { ISD::SREM, MVT::v64i8,  16 }, // 2*ext+2*pmulhw+mul+sub sequence
404     { ISD::UDIV, MVT::v64i8,  14 }, // 2*ext+2*pmulhw sequence
405     { ISD::UREM, MVT::v64i8,  16 }, // 2*ext+2*pmulhw+mul+sub sequence
406     { ISD::SDIV, MVT::v32i16,  6 }, // vpmulhw sequence
407     { ISD::SREM, MVT::v32i16,  8 }, // vpmulhw+mul+sub sequence
408     { ISD::UDIV, MVT::v32i16,  6 }, // vpmulhuw sequence
409     { ISD::UREM, MVT::v32i16,  8 }, // vpmulhuw+mul+sub sequence
410   };
411 
412   if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
413        Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) &&
414       ST->hasBWI()) {
415     if (const auto *Entry =
416             CostTableLookup(AVX512BWConstCostTable, ISD, LT.second))
417       return LT.first * Entry->Cost;
418   }
419 
420   static const CostTblEntry AVX512ConstCostTable[] = {
421     { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence
422     { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence
423     { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence
424     { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence
425     { ISD::SDIV, MVT::v64i8,  28 }, // 4*ext+4*pmulhw sequence
426     { ISD::SREM, MVT::v64i8,  32 }, // 4*ext+4*pmulhw+mul+sub sequence
427     { ISD::UDIV, MVT::v64i8,  28 }, // 4*ext+4*pmulhw sequence
428     { ISD::UREM, MVT::v64i8,  32 }, // 4*ext+4*pmulhw+mul+sub sequence
429     { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence
430     { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence
431     { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence
432     { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence
433   };
434 
435   if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
436        Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) &&
437       ST->hasAVX512()) {
438     if (const auto *Entry =
439             CostTableLookup(AVX512ConstCostTable, ISD, LT.second))
440       return LT.first * Entry->Cost;
441   }
442 
443   static const CostTblEntry AVX2ConstCostTable[] = {
444     { ISD::SDIV, MVT::v32i8,  14 }, // 2*ext+2*pmulhw sequence
445     { ISD::SREM, MVT::v32i8,  16 }, // 2*ext+2*pmulhw+mul+sub sequence
446     { ISD::UDIV, MVT::v32i8,  14 }, // 2*ext+2*pmulhw sequence
447     { ISD::UREM, MVT::v32i8,  16 }, // 2*ext+2*pmulhw+mul+sub sequence
448     { ISD::SDIV, MVT::v16i16,  6 }, // vpmulhw sequence
449     { ISD::SREM, MVT::v16i16,  8 }, // vpmulhw+mul+sub sequence
450     { ISD::UDIV, MVT::v16i16,  6 }, // vpmulhuw sequence
451     { ISD::UREM, MVT::v16i16,  8 }, // vpmulhuw+mul+sub sequence
452     { ISD::SDIV, MVT::v8i32,  15 }, // vpmuldq sequence
453     { ISD::SREM, MVT::v8i32,  19 }, // vpmuldq+mul+sub sequence
454     { ISD::UDIV, MVT::v8i32,  15 }, // vpmuludq sequence
455     { ISD::UREM, MVT::v8i32,  19 }, // vpmuludq+mul+sub sequence
456   };
457 
458   if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
459        Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) &&
460       ST->hasAVX2()) {
461     if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second))
462       return LT.first * Entry->Cost;
463   }
464 
465   static const CostTblEntry SSE2ConstCostTable[] = {
466     { ISD::SDIV, MVT::v32i8,  28+2 }, // 4*ext+4*pmulhw sequence + split.
467     { ISD::SREM, MVT::v32i8,  32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split.
468     { ISD::SDIV, MVT::v16i8,    14 }, // 2*ext+2*pmulhw sequence
469     { ISD::SREM, MVT::v16i8,    16 }, // 2*ext+2*pmulhw+mul+sub sequence
470     { ISD::UDIV, MVT::v32i8,  28+2 }, // 4*ext+4*pmulhw sequence + split.
471     { ISD::UREM, MVT::v32i8,  32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split.
472     { ISD::UDIV, MVT::v16i8,    14 }, // 2*ext+2*pmulhw sequence
473     { ISD::UREM, MVT::v16i8,    16 }, // 2*ext+2*pmulhw+mul+sub sequence
474     { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split.
475     { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split.
476     { ISD::SDIV, MVT::v8i16,     6 }, // pmulhw sequence
477     { ISD::SREM, MVT::v8i16,     8 }, // pmulhw+mul+sub sequence
478     { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split.
479     { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split.
480     { ISD::UDIV, MVT::v8i16,     6 }, // pmulhuw sequence
481     { ISD::UREM, MVT::v8i16,     8 }, // pmulhuw+mul+sub sequence
482     { ISD::SDIV, MVT::v8i32,  38+2 }, // 2*pmuludq sequence + split.
483     { ISD::SREM, MVT::v8i32,  48+2 }, // 2*pmuludq+mul+sub sequence + split.
484     { ISD::SDIV, MVT::v4i32,    19 }, // pmuludq sequence
485     { ISD::SREM, MVT::v4i32,    24 }, // pmuludq+mul+sub sequence
486     { ISD::UDIV, MVT::v8i32,  30+2 }, // 2*pmuludq sequence + split.
487     { ISD::UREM, MVT::v8i32,  40+2 }, // 2*pmuludq+mul+sub sequence + split.
488     { ISD::UDIV, MVT::v4i32,    15 }, // pmuludq sequence
489     { ISD::UREM, MVT::v4i32,    20 }, // pmuludq+mul+sub sequence
490   };
491 
492   if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
493        Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) &&
494       ST->hasSSE2()) {
495     // pmuldq sequence.
496     if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX())
497       return LT.first * 32;
498     if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX())
499       return LT.first * 38;
500     if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41())
501       return LT.first * 15;
502     if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41())
503       return LT.first * 20;
504 
505     if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second))
506       return LT.first * Entry->Cost;
507   }
508 
509   static const CostTblEntry AVX512BWShiftCostTable[] = {
510     { ISD::SHL,   MVT::v16i8,      4 }, // extend/vpsllvw/pack sequence.
511     { ISD::SRL,   MVT::v16i8,      4 }, // extend/vpsrlvw/pack sequence.
512     { ISD::SRA,   MVT::v16i8,      4 }, // extend/vpsravw/pack sequence.
513     { ISD::SHL,   MVT::v32i8,      4 }, // extend/vpsllvw/pack sequence.
514     { ISD::SRL,   MVT::v32i8,      4 }, // extend/vpsrlvw/pack sequence.
515     { ISD::SRA,   MVT::v32i8,      6 }, // extend/vpsravw/pack sequence.
516     { ISD::SHL,   MVT::v64i8,      6 }, // extend/vpsllvw/pack sequence.
517     { ISD::SRL,   MVT::v64i8,      7 }, // extend/vpsrlvw/pack sequence.
518     { ISD::SRA,   MVT::v64i8,     15 }, // extend/vpsravw/pack sequence.
519 
520     { ISD::SHL,   MVT::v8i16,      1 }, // vpsllvw
521     { ISD::SRL,   MVT::v8i16,      1 }, // vpsrlvw
522     { ISD::SRA,   MVT::v8i16,      1 }, // vpsravw
523     { ISD::SHL,   MVT::v16i16,     1 }, // vpsllvw
524     { ISD::SRL,   MVT::v16i16,     1 }, // vpsrlvw
525     { ISD::SRA,   MVT::v16i16,     1 }, // vpsravw
526     { ISD::SHL,   MVT::v32i16,     1 }, // vpsllvw
527     { ISD::SRL,   MVT::v32i16,     1 }, // vpsrlvw
528     { ISD::SRA,   MVT::v32i16,     1 }, // vpsravw
529   };
530 
531   if (ST->hasBWI())
532     if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second))
533       return LT.first * Entry->Cost;
534 
535   static const CostTblEntry AVX2UniformCostTable[] = {
536     // Uniform splats are cheaper for the following instructions.
537     { ISD::SHL,  MVT::v16i16, 1 }, // psllw.
538     { ISD::SRL,  MVT::v16i16, 1 }, // psrlw.
539     { ISD::SRA,  MVT::v16i16, 1 }, // psraw.
540     { ISD::SHL,  MVT::v32i16, 2 }, // 2*psllw.
541     { ISD::SRL,  MVT::v32i16, 2 }, // 2*psrlw.
542     { ISD::SRA,  MVT::v32i16, 2 }, // 2*psraw.
543 
544     { ISD::SHL,  MVT::v8i32,  1 }, // pslld
545     { ISD::SRL,  MVT::v8i32,  1 }, // psrld
546     { ISD::SRA,  MVT::v8i32,  1 }, // psrad
547     { ISD::SHL,  MVT::v4i64,  1 }, // psllq
548     { ISD::SRL,  MVT::v4i64,  1 }, // psrlq
549   };
550 
551   if (ST->hasAVX2() &&
552       ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) ||
553        (Op2Info == TargetTransformInfo::OK_UniformValue))) {
554     if (const auto *Entry =
555             CostTableLookup(AVX2UniformCostTable, ISD, LT.second))
556       return LT.first * Entry->Cost;
557   }
558 
559   static const CostTblEntry SSE2UniformCostTable[] = {
560     // Uniform splats are cheaper for the following instructions.
561     { ISD::SHL,  MVT::v8i16,  1 }, // psllw.
562     { ISD::SHL,  MVT::v4i32,  1 }, // pslld
563     { ISD::SHL,  MVT::v2i64,  1 }, // psllq.
564 
565     { ISD::SRL,  MVT::v8i16,  1 }, // psrlw.
566     { ISD::SRL,  MVT::v4i32,  1 }, // psrld.
567     { ISD::SRL,  MVT::v2i64,  1 }, // psrlq.
568 
569     { ISD::SRA,  MVT::v8i16,  1 }, // psraw.
570     { ISD::SRA,  MVT::v4i32,  1 }, // psrad.
571   };
572 
573   if (ST->hasSSE2() &&
574       ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) ||
575        (Op2Info == TargetTransformInfo::OK_UniformValue))) {
576     if (const auto *Entry =
577             CostTableLookup(SSE2UniformCostTable, ISD, LT.second))
578       return LT.first * Entry->Cost;
579   }
580 
581   static const CostTblEntry AVX512DQCostTable[] = {
582     { ISD::MUL,  MVT::v2i64, 2 }, // pmullq
583     { ISD::MUL,  MVT::v4i64, 2 }, // pmullq
584     { ISD::MUL,  MVT::v8i64, 2 }  // pmullq
585   };
586 
587   // Look for AVX512DQ lowering tricks for custom cases.
588   if (ST->hasDQI())
589     if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second))
590       return LT.first * Entry->Cost;
591 
592   static const CostTblEntry AVX512BWCostTable[] = {
593     { ISD::SHL,   MVT::v64i8,     11 }, // vpblendvb sequence.
594     { ISD::SRL,   MVT::v64i8,     11 }, // vpblendvb sequence.
595     { ISD::SRA,   MVT::v64i8,     24 }, // vpblendvb sequence.
596   };
597 
598   // Look for AVX512BW lowering tricks for custom cases.
599   if (ST->hasBWI())
600     if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second))
601       return LT.first * Entry->Cost;
602 
603   static const CostTblEntry AVX512CostTable[] = {
604     { ISD::SHL,     MVT::v4i32,      1 },
605     { ISD::SRL,     MVT::v4i32,      1 },
606     { ISD::SRA,     MVT::v4i32,      1 },
607     { ISD::SHL,     MVT::v8i32,      1 },
608     { ISD::SRL,     MVT::v8i32,      1 },
609     { ISD::SRA,     MVT::v8i32,      1 },
610     { ISD::SHL,     MVT::v16i32,     1 },
611     { ISD::SRL,     MVT::v16i32,     1 },
612     { ISD::SRA,     MVT::v16i32,     1 },
613 
614     { ISD::SHL,     MVT::v2i64,      1 },
615     { ISD::SRL,     MVT::v2i64,      1 },
616     { ISD::SHL,     MVT::v4i64,      1 },
617     { ISD::SRL,     MVT::v4i64,      1 },
618     { ISD::SHL,     MVT::v8i64,      1 },
619     { ISD::SRL,     MVT::v8i64,      1 },
620 
621     { ISD::SRA,     MVT::v2i64,      1 },
622     { ISD::SRA,     MVT::v4i64,      1 },
623     { ISD::SRA,     MVT::v8i64,      1 },
624 
625     { ISD::MUL,     MVT::v16i32,     1 }, // pmulld (Skylake from agner.org)
626     { ISD::MUL,     MVT::v8i32,      1 }, // pmulld (Skylake from agner.org)
627     { ISD::MUL,     MVT::v4i32,      1 }, // pmulld (Skylake from agner.org)
628     { ISD::MUL,     MVT::v8i64,      6 }, // 3*pmuludq/3*shift/2*add
629 
630     { ISD::FNEG,    MVT::v8f64,      1 }, // Skylake from http://www.agner.org/
631     { ISD::FADD,    MVT::v8f64,      1 }, // Skylake from http://www.agner.org/
632     { ISD::FSUB,    MVT::v8f64,      1 }, // Skylake from http://www.agner.org/
633     { ISD::FMUL,    MVT::v8f64,      1 }, // Skylake from http://www.agner.org/
634 
635     { ISD::FNEG,    MVT::v16f32,     1 }, // Skylake from http://www.agner.org/
636     { ISD::FADD,    MVT::v16f32,     1 }, // Skylake from http://www.agner.org/
637     { ISD::FSUB,    MVT::v16f32,     1 }, // Skylake from http://www.agner.org/
638     { ISD::FMUL,    MVT::v16f32,     1 }, // Skylake from http://www.agner.org/
639   };
640 
641   if (ST->hasAVX512())
642     if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second))
643       return LT.first * Entry->Cost;
644 
645   static const CostTblEntry AVX2ShiftCostTable[] = {
646     // Shifts on vXi64/vXi32 on AVX2 is legal even though we declare to
647     // customize them to detect the cases where shift amount is a scalar one.
648     { ISD::SHL,     MVT::v4i32,    2 }, // vpsllvd (Haswell from agner.org)
649     { ISD::SRL,     MVT::v4i32,    2 }, // vpsrlvd (Haswell from agner.org)
650     { ISD::SRA,     MVT::v4i32,    2 }, // vpsravd (Haswell from agner.org)
651     { ISD::SHL,     MVT::v8i32,    2 }, // vpsllvd (Haswell from agner.org)
652     { ISD::SRL,     MVT::v8i32,    2 }, // vpsrlvd (Haswell from agner.org)
653     { ISD::SRA,     MVT::v8i32,    2 }, // vpsravd (Haswell from agner.org)
654     { ISD::SHL,     MVT::v2i64,    1 }, // vpsllvq (Haswell from agner.org)
655     { ISD::SRL,     MVT::v2i64,    1 }, // vpsrlvq (Haswell from agner.org)
656     { ISD::SHL,     MVT::v4i64,    1 }, // vpsllvq (Haswell from agner.org)
657     { ISD::SRL,     MVT::v4i64,    1 }, // vpsrlvq (Haswell from agner.org)
658   };
659 
660   if (ST->hasAVX512()) {
661     if (ISD == ISD::SHL && LT.second == MVT::v32i16 &&
662         (Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
663          Op2Info == TargetTransformInfo::OK_NonUniformConstantValue))
664       // On AVX512, a packed v32i16 shift left by a constant build_vector
665       // is lowered into a vector multiply (vpmullw).
666       return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind,
667                                     Op1Info, Op2Info,
668                                     TargetTransformInfo::OP_None,
669                                     TargetTransformInfo::OP_None);
670   }
671 
672   // Look for AVX2 lowering tricks (XOP is always better at v4i32 shifts).
673   if (ST->hasAVX2() && !(ST->hasXOP() && LT.second == MVT::v4i32)) {
674     if (ISD == ISD::SHL && LT.second == MVT::v16i16 &&
675         (Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
676          Op2Info == TargetTransformInfo::OK_NonUniformConstantValue))
677       // On AVX2, a packed v16i16 shift left by a constant build_vector
678       // is lowered into a vector multiply (vpmullw).
679       return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind,
680                                     Op1Info, Op2Info,
681                                     TargetTransformInfo::OP_None,
682                                     TargetTransformInfo::OP_None);
683 
684     if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second))
685       return LT.first * Entry->Cost;
686   }
687 
688   static const CostTblEntry XOPShiftCostTable[] = {
689     // 128bit shifts take 1cy, but right shifts require negation beforehand.
690     { ISD::SHL,     MVT::v16i8,    1 },
691     { ISD::SRL,     MVT::v16i8,    2 },
692     { ISD::SRA,     MVT::v16i8,    2 },
693     { ISD::SHL,     MVT::v8i16,    1 },
694     { ISD::SRL,     MVT::v8i16,    2 },
695     { ISD::SRA,     MVT::v8i16,    2 },
696     { ISD::SHL,     MVT::v4i32,    1 },
697     { ISD::SRL,     MVT::v4i32,    2 },
698     { ISD::SRA,     MVT::v4i32,    2 },
699     { ISD::SHL,     MVT::v2i64,    1 },
700     { ISD::SRL,     MVT::v2i64,    2 },
701     { ISD::SRA,     MVT::v2i64,    2 },
702     // 256bit shifts require splitting if AVX2 didn't catch them above.
703     { ISD::SHL,     MVT::v32i8,  2+2 },
704     { ISD::SRL,     MVT::v32i8,  4+2 },
705     { ISD::SRA,     MVT::v32i8,  4+2 },
706     { ISD::SHL,     MVT::v16i16, 2+2 },
707     { ISD::SRL,     MVT::v16i16, 4+2 },
708     { ISD::SRA,     MVT::v16i16, 4+2 },
709     { ISD::SHL,     MVT::v8i32,  2+2 },
710     { ISD::SRL,     MVT::v8i32,  4+2 },
711     { ISD::SRA,     MVT::v8i32,  4+2 },
712     { ISD::SHL,     MVT::v4i64,  2+2 },
713     { ISD::SRL,     MVT::v4i64,  4+2 },
714     { ISD::SRA,     MVT::v4i64,  4+2 },
715   };
716 
717   // Look for XOP lowering tricks.
718   if (ST->hasXOP()) {
719     // If the right shift is constant then we'll fold the negation so
720     // it's as cheap as a left shift.
721     int ShiftISD = ISD;
722     if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) &&
723         (Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
724          Op2Info == TargetTransformInfo::OK_NonUniformConstantValue))
725       ShiftISD = ISD::SHL;
726     if (const auto *Entry =
727             CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second))
728       return LT.first * Entry->Cost;
729   }
730 
731   static const CostTblEntry SSE2UniformShiftCostTable[] = {
732     // Uniform splats are cheaper for the following instructions.
733     { ISD::SHL,  MVT::v16i16, 2+2 }, // 2*psllw + split.
734     { ISD::SHL,  MVT::v8i32,  2+2 }, // 2*pslld + split.
735     { ISD::SHL,  MVT::v4i64,  2+2 }, // 2*psllq + split.
736 
737     { ISD::SRL,  MVT::v16i16, 2+2 }, // 2*psrlw + split.
738     { ISD::SRL,  MVT::v8i32,  2+2 }, // 2*psrld + split.
739     { ISD::SRL,  MVT::v4i64,  2+2 }, // 2*psrlq + split.
740 
741     { ISD::SRA,  MVT::v16i16, 2+2 }, // 2*psraw + split.
742     { ISD::SRA,  MVT::v8i32,  2+2 }, // 2*psrad + split.
743     { ISD::SRA,  MVT::v2i64,    4 }, // 2*psrad + shuffle.
744     { ISD::SRA,  MVT::v4i64,  8+2 }, // 2*(2*psrad + shuffle) + split.
745   };
746 
747   if (ST->hasSSE2() &&
748       ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) ||
749        (Op2Info == TargetTransformInfo::OK_UniformValue))) {
750 
751     // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table.
752     if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2())
753       return LT.first * 4; // 2*psrad + shuffle.
754 
755     if (const auto *Entry =
756             CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second))
757       return LT.first * Entry->Cost;
758   }
759 
760   if (ISD == ISD::SHL &&
761       Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) {
762     MVT VT = LT.second;
763     // Vector shift left by non uniform constant can be lowered
764     // into vector multiply.
765     if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) ||
766         ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX()))
767       ISD = ISD::MUL;
768   }
769 
770   static const CostTblEntry AVX2CostTable[] = {
771     { ISD::SHL,  MVT::v16i8,      6 }, // vpblendvb sequence.
772     { ISD::SHL,  MVT::v32i8,      6 }, // vpblendvb sequence.
773     { ISD::SHL,  MVT::v64i8,     12 }, // 2*vpblendvb sequence.
774     { ISD::SHL,  MVT::v8i16,      5 }, // extend/vpsrlvd/pack sequence.
775     { ISD::SHL,  MVT::v16i16,     7 }, // extend/vpsrlvd/pack sequence.
776     { ISD::SHL,  MVT::v32i16,    14 }, // 2*extend/vpsrlvd/pack sequence.
777 
778     { ISD::SRL,  MVT::v16i8,      6 }, // vpblendvb sequence.
779     { ISD::SRL,  MVT::v32i8,      6 }, // vpblendvb sequence.
780     { ISD::SRL,  MVT::v64i8,     12 }, // 2*vpblendvb sequence.
781     { ISD::SRL,  MVT::v8i16,      5 }, // extend/vpsrlvd/pack sequence.
782     { ISD::SRL,  MVT::v16i16,     7 }, // extend/vpsrlvd/pack sequence.
783     { ISD::SRL,  MVT::v32i16,    14 }, // 2*extend/vpsrlvd/pack sequence.
784 
785     { ISD::SRA,  MVT::v16i8,     17 }, // vpblendvb sequence.
786     { ISD::SRA,  MVT::v32i8,     17 }, // vpblendvb sequence.
787     { ISD::SRA,  MVT::v64i8,     34 }, // 2*vpblendvb sequence.
788     { ISD::SRA,  MVT::v8i16,      5 }, // extend/vpsravd/pack sequence.
789     { ISD::SRA,  MVT::v16i16,     7 }, // extend/vpsravd/pack sequence.
790     { ISD::SRA,  MVT::v32i16,    14 }, // 2*extend/vpsravd/pack sequence.
791     { ISD::SRA,  MVT::v2i64,      2 }, // srl/xor/sub sequence.
792     { ISD::SRA,  MVT::v4i64,      2 }, // srl/xor/sub sequence.
793 
794     { ISD::SUB,  MVT::v32i8,      1 }, // psubb
795     { ISD::ADD,  MVT::v32i8,      1 }, // paddb
796     { ISD::SUB,  MVT::v16i16,     1 }, // psubw
797     { ISD::ADD,  MVT::v16i16,     1 }, // paddw
798     { ISD::SUB,  MVT::v8i32,      1 }, // psubd
799     { ISD::ADD,  MVT::v8i32,      1 }, // paddd
800     { ISD::SUB,  MVT::v4i64,      1 }, // psubq
801     { ISD::ADD,  MVT::v4i64,      1 }, // paddq
802 
803     { ISD::MUL,  MVT::v16i16,     1 }, // pmullw
804     { ISD::MUL,  MVT::v8i32,      2 }, // pmulld (Haswell from agner.org)
805     { ISD::MUL,  MVT::v4i64,      6 }, // 3*pmuludq/3*shift/2*add
806 
807     { ISD::FNEG, MVT::v4f64,      1 }, // Haswell from http://www.agner.org/
808     { ISD::FNEG, MVT::v8f32,      1 }, // Haswell from http://www.agner.org/
809     { ISD::FADD, MVT::v4f64,      1 }, // Haswell from http://www.agner.org/
810     { ISD::FADD, MVT::v8f32,      1 }, // Haswell from http://www.agner.org/
811     { ISD::FSUB, MVT::v4f64,      1 }, // Haswell from http://www.agner.org/
812     { ISD::FSUB, MVT::v8f32,      1 }, // Haswell from http://www.agner.org/
813     { ISD::FMUL, MVT::f64,        1 }, // Haswell from http://www.agner.org/
814     { ISD::FMUL, MVT::v2f64,      1 }, // Haswell from http://www.agner.org/
815     { ISD::FMUL, MVT::v4f64,      1 }, // Haswell from http://www.agner.org/
816     { ISD::FMUL, MVT::v8f32,      1 }, // Haswell from http://www.agner.org/
817 
818     { ISD::FDIV, MVT::f32,        7 }, // Haswell from http://www.agner.org/
819     { ISD::FDIV, MVT::v4f32,      7 }, // Haswell from http://www.agner.org/
820     { ISD::FDIV, MVT::v8f32,     14 }, // Haswell from http://www.agner.org/
821     { ISD::FDIV, MVT::f64,       14 }, // Haswell from http://www.agner.org/
822     { ISD::FDIV, MVT::v2f64,     14 }, // Haswell from http://www.agner.org/
823     { ISD::FDIV, MVT::v4f64,     28 }, // Haswell from http://www.agner.org/
824   };
825 
826   // Look for AVX2 lowering tricks for custom cases.
827   if (ST->hasAVX2())
828     if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second))
829       return LT.first * Entry->Cost;
830 
831   static const CostTblEntry AVX1CostTable[] = {
832     // We don't have to scalarize unsupported ops. We can issue two half-sized
833     // operations and we only need to extract the upper YMM half.
834     // Two ops + 1 extract + 1 insert = 4.
835     { ISD::MUL,     MVT::v16i16,     4 },
836     { ISD::MUL,     MVT::v8i32,      5 }, // BTVER2 from http://www.agner.org/
837     { ISD::MUL,     MVT::v4i64,     12 },
838 
839     { ISD::SUB,     MVT::v32i8,      4 },
840     { ISD::ADD,     MVT::v32i8,      4 },
841     { ISD::SUB,     MVT::v16i16,     4 },
842     { ISD::ADD,     MVT::v16i16,     4 },
843     { ISD::SUB,     MVT::v8i32,      4 },
844     { ISD::ADD,     MVT::v8i32,      4 },
845     { ISD::SUB,     MVT::v4i64,      4 },
846     { ISD::ADD,     MVT::v4i64,      4 },
847 
848     { ISD::SHL,     MVT::v16i8,     10 }, // pblendvb sequence .
849     { ISD::SHL,     MVT::v32i8,     22 }, // pblendvb sequence + split.
850     { ISD::SHL,     MVT::v8i16,      6 }, // pblendvb sequence.
851     { ISD::SHL,     MVT::v16i16,    13 }, // pblendvb sequence + split.
852     { ISD::SHL,     MVT::v4i32,      3 }, // pslld/paddd/cvttps2dq/pmulld
853     { ISD::SHL,     MVT::v8i32,      9 }, // pslld/paddd/cvttps2dq/pmulld + split
854     { ISD::SHL,     MVT::v2i64,      2 }, // Shift each lane + blend.
855     { ISD::SHL,     MVT::v4i64,      6 }, // Shift each lane + blend + split.
856 
857     { ISD::SRL,     MVT::v16i8,     11 }, // pblendvb sequence.
858     { ISD::SRL,     MVT::v32i8,     23 }, // pblendvb sequence + split.
859     { ISD::SRL,     MVT::v8i16,     13 }, // pblendvb sequence.
860     { ISD::SRL,     MVT::v16i16,    28 }, // pblendvb sequence + split.
861     { ISD::SRL,     MVT::v4i32,      6 }, // Shift each lane + blend.
862     { ISD::SRL,     MVT::v8i32,     14 }, // Shift each lane + blend + split.
863     { ISD::SRL,     MVT::v2i64,      2 }, // Shift each lane + blend.
864     { ISD::SRL,     MVT::v4i64,      6 }, // Shift each lane + blend + split.
865 
866     { ISD::SRA,     MVT::v16i8,     21 }, // pblendvb sequence.
867     { ISD::SRA,     MVT::v32i8,     44 }, // pblendvb sequence + split.
868     { ISD::SRA,     MVT::v8i16,     13 }, // pblendvb sequence.
869     { ISD::SRA,     MVT::v16i16,    28 }, // pblendvb sequence + split.
870     { ISD::SRA,     MVT::v4i32,      6 }, // Shift each lane + blend.
871     { ISD::SRA,     MVT::v8i32,     14 }, // Shift each lane + blend + split.
872     { ISD::SRA,     MVT::v2i64,      5 }, // Shift each lane + blend.
873     { ISD::SRA,     MVT::v4i64,     12 }, // Shift each lane + blend + split.
874 
875     { ISD::FNEG,    MVT::v4f64,      2 }, // BTVER2 from http://www.agner.org/
876     { ISD::FNEG,    MVT::v8f32,      2 }, // BTVER2 from http://www.agner.org/
877 
878     { ISD::FMUL,    MVT::f64,        2 }, // BTVER2 from http://www.agner.org/
879     { ISD::FMUL,    MVT::v2f64,      2 }, // BTVER2 from http://www.agner.org/
880     { ISD::FMUL,    MVT::v4f64,      4 }, // BTVER2 from http://www.agner.org/
881 
882     { ISD::FDIV,    MVT::f32,       14 }, // SNB from http://www.agner.org/
883     { ISD::FDIV,    MVT::v4f32,     14 }, // SNB from http://www.agner.org/
884     { ISD::FDIV,    MVT::v8f32,     28 }, // SNB from http://www.agner.org/
885     { ISD::FDIV,    MVT::f64,       22 }, // SNB from http://www.agner.org/
886     { ISD::FDIV,    MVT::v2f64,     22 }, // SNB from http://www.agner.org/
887     { ISD::FDIV,    MVT::v4f64,     44 }, // SNB from http://www.agner.org/
888   };
889 
890   if (ST->hasAVX())
891     if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second))
892       return LT.first * Entry->Cost;
893 
894   static const CostTblEntry SSE42CostTable[] = {
895     { ISD::FADD, MVT::f64,     1 }, // Nehalem from http://www.agner.org/
896     { ISD::FADD, MVT::f32,     1 }, // Nehalem from http://www.agner.org/
897     { ISD::FADD, MVT::v2f64,   1 }, // Nehalem from http://www.agner.org/
898     { ISD::FADD, MVT::v4f32,   1 }, // Nehalem from http://www.agner.org/
899 
900     { ISD::FSUB, MVT::f64,     1 }, // Nehalem from http://www.agner.org/
901     { ISD::FSUB, MVT::f32 ,    1 }, // Nehalem from http://www.agner.org/
902     { ISD::FSUB, MVT::v2f64,   1 }, // Nehalem from http://www.agner.org/
903     { ISD::FSUB, MVT::v4f32,   1 }, // Nehalem from http://www.agner.org/
904 
905     { ISD::FMUL, MVT::f64,     1 }, // Nehalem from http://www.agner.org/
906     { ISD::FMUL, MVT::f32,     1 }, // Nehalem from http://www.agner.org/
907     { ISD::FMUL, MVT::v2f64,   1 }, // Nehalem from http://www.agner.org/
908     { ISD::FMUL, MVT::v4f32,   1 }, // Nehalem from http://www.agner.org/
909 
910     { ISD::FDIV,  MVT::f32,   14 }, // Nehalem from http://www.agner.org/
911     { ISD::FDIV,  MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/
912     { ISD::FDIV,  MVT::f64,   22 }, // Nehalem from http://www.agner.org/
913     { ISD::FDIV,  MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/
914 
915     { ISD::MUL,   MVT::v2i64,  6 }  // 3*pmuludq/3*shift/2*add
916   };
917 
918   if (ST->hasSSE42())
919     if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second))
920       return LT.first * Entry->Cost;
921 
922   static const CostTblEntry SSE41CostTable[] = {
923     { ISD::SHL,  MVT::v16i8,      11 }, // pblendvb sequence.
924     { ISD::SHL,  MVT::v8i16,      14 }, // pblendvb sequence.
925     { ISD::SHL,  MVT::v4i32,       4 }, // pslld/paddd/cvttps2dq/pmulld
926 
927     { ISD::SRL,  MVT::v16i8,      12 }, // pblendvb sequence.
928     { ISD::SRL,  MVT::v8i16,      14 }, // pblendvb sequence.
929     { ISD::SRL,  MVT::v4i32,      11 }, // Shift each lane + blend.
930 
931     { ISD::SRA,  MVT::v16i8,      24 }, // pblendvb sequence.
932     { ISD::SRA,  MVT::v8i16,      14 }, // pblendvb sequence.
933     { ISD::SRA,  MVT::v4i32,      12 }, // Shift each lane + blend.
934 
935     { ISD::MUL,  MVT::v4i32,       2 }  // pmulld (Nehalem from agner.org)
936   };
937 
938   if (ST->hasSSE41())
939     if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second))
940       return LT.first * Entry->Cost;
941 
942   static const CostTblEntry SSE2CostTable[] = {
943     // We don't correctly identify costs of casts because they are marked as
944     // custom.
945     { ISD::SHL,  MVT::v16i8,      26 }, // cmpgtb sequence.
946     { ISD::SHL,  MVT::v8i16,      32 }, // cmpgtb sequence.
947     { ISD::SHL,  MVT::v4i32,     2*5 }, // We optimized this using mul.
948     { ISD::SHL,  MVT::v2i64,       4 }, // splat+shuffle sequence.
949 
950     { ISD::SRL,  MVT::v16i8,      26 }, // cmpgtb sequence.
951     { ISD::SRL,  MVT::v8i16,      32 }, // cmpgtb sequence.
952     { ISD::SRL,  MVT::v4i32,      16 }, // Shift each lane + blend.
953     { ISD::SRL,  MVT::v2i64,       4 }, // splat+shuffle sequence.
954 
955     { ISD::SRA,  MVT::v16i8,      54 }, // unpacked cmpgtb sequence.
956     { ISD::SRA,  MVT::v8i16,      32 }, // cmpgtb sequence.
957     { ISD::SRA,  MVT::v4i32,      16 }, // Shift each lane + blend.
958     { ISD::SRA,  MVT::v2i64,      12 }, // srl/xor/sub sequence.
959 
960     { ISD::MUL,  MVT::v8i16,       1 }, // pmullw
961     { ISD::MUL,  MVT::v4i32,       6 }, // 3*pmuludq/4*shuffle
962     { ISD::MUL,  MVT::v2i64,       8 }, // 3*pmuludq/3*shift/2*add
963 
964     { ISD::FDIV, MVT::f32,        23 }, // Pentium IV from http://www.agner.org/
965     { ISD::FDIV, MVT::v4f32,      39 }, // Pentium IV from http://www.agner.org/
966     { ISD::FDIV, MVT::f64,        38 }, // Pentium IV from http://www.agner.org/
967     { ISD::FDIV, MVT::v2f64,      69 }, // Pentium IV from http://www.agner.org/
968 
969     { ISD::FNEG, MVT::f32,         1 }, // Pentium IV from http://www.agner.org/
970     { ISD::FNEG, MVT::f64,         1 }, // Pentium IV from http://www.agner.org/
971     { ISD::FNEG, MVT::v4f32,       1 }, // Pentium IV from http://www.agner.org/
972     { ISD::FNEG, MVT::v2f64,       1 }, // Pentium IV from http://www.agner.org/
973 
974     { ISD::FADD, MVT::f32,         2 }, // Pentium IV from http://www.agner.org/
975     { ISD::FADD, MVT::f64,         2 }, // Pentium IV from http://www.agner.org/
976 
977     { ISD::FSUB, MVT::f32,         2 }, // Pentium IV from http://www.agner.org/
978     { ISD::FSUB, MVT::f64,         2 }, // Pentium IV from http://www.agner.org/
979   };
980 
981   if (ST->hasSSE2())
982     if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second))
983       return LT.first * Entry->Cost;
984 
985   static const CostTblEntry SSE1CostTable[] = {
986     { ISD::FDIV, MVT::f32,   17 }, // Pentium III from http://www.agner.org/
987     { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/
988 
989     { ISD::FNEG, MVT::f32,    2 }, // Pentium III from http://www.agner.org/
990     { ISD::FNEG, MVT::v4f32,  2 }, // Pentium III from http://www.agner.org/
991 
992     { ISD::FADD, MVT::f32,    1 }, // Pentium III from http://www.agner.org/
993     { ISD::FADD, MVT::v4f32,  2 }, // Pentium III from http://www.agner.org/
994 
995     { ISD::FSUB, MVT::f32,    1 }, // Pentium III from http://www.agner.org/
996     { ISD::FSUB, MVT::v4f32,  2 }, // Pentium III from http://www.agner.org/
997   };
998 
999   if (ST->hasSSE1())
1000     if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second))
1001       return LT.first * Entry->Cost;
1002 
1003   static const CostTblEntry X64CostTbl[] = { // 64-bit targets
1004     { ISD::ADD,  MVT::i64,    1 }, // Core (Merom) from http://www.agner.org/
1005     { ISD::SUB,  MVT::i64,    1 }, // Core (Merom) from http://www.agner.org/
1006   };
1007 
1008   if (ST->is64Bit())
1009     if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, LT.second))
1010       return LT.first * Entry->Cost;
1011 
1012   static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets
1013     { ISD::ADD,  MVT::i8,    1 }, // Pentium III from http://www.agner.org/
1014     { ISD::ADD,  MVT::i16,   1 }, // Pentium III from http://www.agner.org/
1015     { ISD::ADD,  MVT::i32,   1 }, // Pentium III from http://www.agner.org/
1016 
1017     { ISD::SUB,  MVT::i8,    1 }, // Pentium III from http://www.agner.org/
1018     { ISD::SUB,  MVT::i16,   1 }, // Pentium III from http://www.agner.org/
1019     { ISD::SUB,  MVT::i32,   1 }, // Pentium III from http://www.agner.org/
1020   };
1021 
1022   if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, LT.second))
1023     return LT.first * Entry->Cost;
1024 
1025   // It is not a good idea to vectorize division. We have to scalarize it and
1026   // in the process we will often end up having to spilling regular
1027   // registers. The overhead of division is going to dominate most kernels
1028   // anyways so try hard to prevent vectorization of division - it is
1029   // generally a bad idea. Assume somewhat arbitrarily that we have to be able
1030   // to hide "20 cycles" for each lane.
1031   if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM ||
1032                                ISD == ISD::UDIV || ISD == ISD::UREM)) {
1033     InstructionCost ScalarCost = getArithmeticInstrCost(
1034         Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info,
1035         TargetTransformInfo::OP_None, TargetTransformInfo::OP_None);
1036     return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost;
1037   }
1038 
1039   // Fallback to the default implementation.
1040   return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info);
1041 }
1042 
1043 InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
1044                                            VectorType *BaseTp,
1045                                            ArrayRef<int> Mask, int Index,
1046                                            VectorType *SubTp) {
1047   // 64-bit packed float vectors (v2f32) are widened to type v4f32.
1048   // 64-bit packed integer vectors (v2i32) are widened to type v4i32.
1049   std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp);
1050 
1051   Kind = improveShuffleKindFromMask(Kind, Mask);
1052   // Treat Transpose as 2-op shuffles - there's no difference in lowering.
1053   if (Kind == TTI::SK_Transpose)
1054     Kind = TTI::SK_PermuteTwoSrc;
1055 
1056   // For Broadcasts we are splatting the first element from the first input
1057   // register, so only need to reference that input and all the output
1058   // registers are the same.
1059   if (Kind == TTI::SK_Broadcast)
1060     LT.first = 1;
1061 
1062   // Subvector extractions are free if they start at the beginning of a
1063   // vector and cheap if the subvectors are aligned.
1064   if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) {
1065     int NumElts = LT.second.getVectorNumElements();
1066     if ((Index % NumElts) == 0)
1067       return 0;
1068     std::pair<InstructionCost, MVT> SubLT =
1069         TLI->getTypeLegalizationCost(DL, SubTp);
1070     if (SubLT.second.isVector()) {
1071       int NumSubElts = SubLT.second.getVectorNumElements();
1072       if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0)
1073         return SubLT.first;
1074       // Handle some cases for widening legalization. For now we only handle
1075       // cases where the original subvector was naturally aligned and evenly
1076       // fit in its legalized subvector type.
1077       // FIXME: Remove some of the alignment restrictions.
1078       // FIXME: We can use permq for 64-bit or larger extracts from 256-bit
1079       // vectors.
1080       int OrigSubElts = cast<FixedVectorType>(SubTp)->getNumElements();
1081       if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 &&
1082           (NumSubElts % OrigSubElts) == 0 &&
1083           LT.second.getVectorElementType() ==
1084               SubLT.second.getVectorElementType() &&
1085           LT.second.getVectorElementType().getSizeInBits() ==
1086               BaseTp->getElementType()->getPrimitiveSizeInBits()) {
1087         assert(NumElts >= NumSubElts && NumElts > OrigSubElts &&
1088                "Unexpected number of elements!");
1089         auto *VecTy = FixedVectorType::get(BaseTp->getElementType(),
1090                                            LT.second.getVectorNumElements());
1091         auto *SubTy = FixedVectorType::get(BaseTp->getElementType(),
1092                                            SubLT.second.getVectorNumElements());
1093         int ExtractIndex = alignDown((Index % NumElts), NumSubElts);
1094         InstructionCost ExtractCost = getShuffleCost(
1095             TTI::SK_ExtractSubvector, VecTy, None, ExtractIndex, SubTy);
1096 
1097         // If the original size is 32-bits or more, we can use pshufd. Otherwise
1098         // if we have SSSE3 we can use pshufb.
1099         if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3())
1100           return ExtractCost + 1; // pshufd or pshufb
1101 
1102         assert(SubTp->getPrimitiveSizeInBits() == 16 &&
1103                "Unexpected vector size");
1104 
1105         return ExtractCost + 2; // worst case pshufhw + pshufd
1106       }
1107     }
1108   }
1109 
1110   // Subvector insertions are cheap if the subvectors are aligned.
1111   // Note that in general, the insertion starting at the beginning of a vector
1112   // isn't free, because we need to preserve the rest of the wide vector.
1113   if (Kind == TTI::SK_InsertSubvector && LT.second.isVector()) {
1114     int NumElts = LT.second.getVectorNumElements();
1115     std::pair<InstructionCost, MVT> SubLT =
1116         TLI->getTypeLegalizationCost(DL, SubTp);
1117     if (SubLT.second.isVector()) {
1118       int NumSubElts = SubLT.second.getVectorNumElements();
1119       if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0)
1120         return SubLT.first;
1121     }
1122   }
1123 
1124   // Handle some common (illegal) sub-vector types as they are often very cheap
1125   // to shuffle even on targets without PSHUFB.
1126   EVT VT = TLI->getValueType(DL, BaseTp);
1127   if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 &&
1128       !ST->hasSSSE3()) {
1129      static const CostTblEntry SSE2SubVectorShuffleTbl[] = {
1130       {TTI::SK_Broadcast,        MVT::v4i16, 1}, // pshuflw
1131       {TTI::SK_Broadcast,        MVT::v2i16, 1}, // pshuflw
1132       {TTI::SK_Broadcast,        MVT::v8i8,  2}, // punpck/pshuflw
1133       {TTI::SK_Broadcast,        MVT::v4i8,  2}, // punpck/pshuflw
1134       {TTI::SK_Broadcast,        MVT::v2i8,  1}, // punpck
1135 
1136       {TTI::SK_Reverse,          MVT::v4i16, 1}, // pshuflw
1137       {TTI::SK_Reverse,          MVT::v2i16, 1}, // pshuflw
1138       {TTI::SK_Reverse,          MVT::v4i8,  3}, // punpck/pshuflw/packus
1139       {TTI::SK_Reverse,          MVT::v2i8,  1}, // punpck
1140 
1141       {TTI::SK_PermuteTwoSrc,    MVT::v4i16, 2}, // punpck/pshuflw
1142       {TTI::SK_PermuteTwoSrc,    MVT::v2i16, 2}, // punpck/pshuflw
1143       {TTI::SK_PermuteTwoSrc,    MVT::v8i8,  7}, // punpck/pshuflw
1144       {TTI::SK_PermuteTwoSrc,    MVT::v4i8,  4}, // punpck/pshuflw
1145       {TTI::SK_PermuteTwoSrc,    MVT::v2i8,  2}, // punpck
1146 
1147       {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw
1148       {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw
1149       {TTI::SK_PermuteSingleSrc, MVT::v8i8,  5}, // punpck/pshuflw
1150       {TTI::SK_PermuteSingleSrc, MVT::v4i8,  3}, // punpck/pshuflw
1151       {TTI::SK_PermuteSingleSrc, MVT::v2i8,  1}, // punpck
1152     };
1153 
1154     if (ST->hasSSE2())
1155       if (const auto *Entry =
1156               CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT()))
1157         return Entry->Cost;
1158   }
1159 
1160   // We are going to permute multiple sources and the result will be in multiple
1161   // destinations. Providing an accurate cost only for splits where the element
1162   // type remains the same.
1163   if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) {
1164     MVT LegalVT = LT.second;
1165     if (LegalVT.isVector() &&
1166         LegalVT.getVectorElementType().getSizeInBits() ==
1167             BaseTp->getElementType()->getPrimitiveSizeInBits() &&
1168         LegalVT.getVectorNumElements() <
1169             cast<FixedVectorType>(BaseTp)->getNumElements()) {
1170 
1171       unsigned VecTySize = DL.getTypeStoreSize(BaseTp);
1172       unsigned LegalVTSize = LegalVT.getStoreSize();
1173       // Number of source vectors after legalization:
1174       unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize;
1175       // Number of destination vectors after legalization:
1176       InstructionCost NumOfDests = LT.first;
1177 
1178       auto *SingleOpTy = FixedVectorType::get(BaseTp->getElementType(),
1179                                               LegalVT.getVectorNumElements());
1180 
1181       InstructionCost NumOfShuffles = (NumOfSrcs - 1) * NumOfDests;
1182       return NumOfShuffles * getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy,
1183                                             None, 0, nullptr);
1184     }
1185 
1186     return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp);
1187   }
1188 
1189   // For 2-input shuffles, we must account for splitting the 2 inputs into many.
1190   if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) {
1191     // We assume that source and destination have the same vector type.
1192     InstructionCost NumOfDests = LT.first;
1193     InstructionCost NumOfShufflesPerDest = LT.first * 2 - 1;
1194     LT.first = NumOfDests * NumOfShufflesPerDest;
1195   }
1196 
1197   static const CostTblEntry AVX512VBMIShuffleTbl[] = {
1198       {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb
1199       {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb
1200 
1201       {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb
1202       {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb
1203 
1204       {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b
1205       {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b
1206       {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2}  // vpermt2b
1207   };
1208 
1209   if (ST->hasVBMI())
1210     if (const auto *Entry =
1211             CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second))
1212       return LT.first * Entry->Cost;
1213 
1214   static const CostTblEntry AVX512BWShuffleTbl[] = {
1215       {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw
1216       {TTI::SK_Broadcast, MVT::v64i8, 1},  // vpbroadcastb
1217 
1218       {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw
1219       {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw
1220       {TTI::SK_Reverse, MVT::v64i8, 2},  // pshufb + vshufi64x2
1221 
1222       {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw
1223       {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw
1224       {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8},  // extend to v32i16
1225 
1226       {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w
1227       {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w
1228       {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2},  // vpermt2w
1229       {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1
1230 
1231       {TTI::SK_Select, MVT::v32i16, 1}, // vblendmw
1232       {TTI::SK_Select, MVT::v64i8,  1}, // vblendmb
1233   };
1234 
1235   if (ST->hasBWI())
1236     if (const auto *Entry =
1237             CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second))
1238       return LT.first * Entry->Cost;
1239 
1240   static const CostTblEntry AVX512ShuffleTbl[] = {
1241       {TTI::SK_Broadcast, MVT::v8f64, 1},  // vbroadcastpd
1242       {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps
1243       {TTI::SK_Broadcast, MVT::v8i64, 1},  // vpbroadcastq
1244       {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd
1245       {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw
1246       {TTI::SK_Broadcast, MVT::v64i8, 1},  // vpbroadcastb
1247 
1248       {TTI::SK_Reverse, MVT::v8f64, 1},  // vpermpd
1249       {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps
1250       {TTI::SK_Reverse, MVT::v8i64, 1},  // vpermq
1251       {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd
1252       {TTI::SK_Reverse, MVT::v32i16, 7}, // per mca
1253       {TTI::SK_Reverse, MVT::v64i8,  7}, // per mca
1254 
1255       {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1},  // vpermpd
1256       {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1},  // vpermpd
1257       {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1},  // vpermpd
1258       {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps
1259       {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1},  // vpermps
1260       {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1},  // vpermps
1261       {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1},  // vpermq
1262       {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1},  // vpermq
1263       {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1},  // vpermq
1264       {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd
1265       {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1},  // vpermd
1266       {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1},  // vpermd
1267       {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1},  // pshufb
1268 
1269       {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1},  // vpermt2pd
1270       {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps
1271       {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1},  // vpermt2q
1272       {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d
1273       {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1},  // vpermt2pd
1274       {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1},  // vpermt2ps
1275       {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1},  // vpermt2q
1276       {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1},  // vpermt2d
1277       {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1},  // vpermt2pd
1278       {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1},  // vpermt2ps
1279       {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1},  // vpermt2q
1280       {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1},  // vpermt2d
1281 
1282       // FIXME: This just applies the type legalization cost rules above
1283       // assuming these completely split.
1284       {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14},
1285       {TTI::SK_PermuteSingleSrc, MVT::v64i8,  14},
1286       {TTI::SK_PermuteTwoSrc,    MVT::v32i16, 42},
1287       {TTI::SK_PermuteTwoSrc,    MVT::v64i8,  42},
1288 
1289       {TTI::SK_Select, MVT::v32i16, 1}, // vpternlogq
1290       {TTI::SK_Select, MVT::v64i8,  1}, // vpternlogq
1291       {TTI::SK_Select, MVT::v8f64,  1}, // vblendmpd
1292       {TTI::SK_Select, MVT::v16f32, 1}, // vblendmps
1293       {TTI::SK_Select, MVT::v8i64,  1}, // vblendmq
1294       {TTI::SK_Select, MVT::v16i32, 1}, // vblendmd
1295   };
1296 
1297   if (ST->hasAVX512())
1298     if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second))
1299       return LT.first * Entry->Cost;
1300 
1301   static const CostTblEntry AVX2ShuffleTbl[] = {
1302       {TTI::SK_Broadcast, MVT::v4f64, 1},  // vbroadcastpd
1303       {TTI::SK_Broadcast, MVT::v8f32, 1},  // vbroadcastps
1304       {TTI::SK_Broadcast, MVT::v4i64, 1},  // vpbroadcastq
1305       {TTI::SK_Broadcast, MVT::v8i32, 1},  // vpbroadcastd
1306       {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw
1307       {TTI::SK_Broadcast, MVT::v32i8, 1},  // vpbroadcastb
1308 
1309       {TTI::SK_Reverse, MVT::v4f64, 1},  // vpermpd
1310       {TTI::SK_Reverse, MVT::v8f32, 1},  // vpermps
1311       {TTI::SK_Reverse, MVT::v4i64, 1},  // vpermq
1312       {TTI::SK_Reverse, MVT::v8i32, 1},  // vpermd
1313       {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb
1314       {TTI::SK_Reverse, MVT::v32i8, 2},  // vperm2i128 + pshufb
1315 
1316       {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb
1317       {TTI::SK_Select, MVT::v32i8, 1},  // vpblendvb
1318 
1319       {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1},  // vpermpd
1320       {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1},  // vpermps
1321       {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1},  // vpermq
1322       {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1},  // vpermd
1323       {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb
1324                                                   // + vpblendvb
1325       {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4},  // vperm2i128 + 2*vpshufb
1326                                                   // + vpblendvb
1327 
1328       {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3},  // 2*vpermpd + vblendpd
1329       {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3},  // 2*vpermps + vblendps
1330       {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3},  // 2*vpermq + vpblendd
1331       {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3},  // 2*vpermd + vpblendd
1332       {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb
1333                                                // + vpblendvb
1334       {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7},  // 2*vperm2i128 + 4*vpshufb
1335                                                // + vpblendvb
1336   };
1337 
1338   if (ST->hasAVX2())
1339     if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second))
1340       return LT.first * Entry->Cost;
1341 
1342   static const CostTblEntry XOPShuffleTbl[] = {
1343       {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2},  // vperm2f128 + vpermil2pd
1344       {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2},  // vperm2f128 + vpermil2ps
1345       {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2},  // vperm2f128 + vpermil2pd
1346       {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2},  // vperm2f128 + vpermil2ps
1347       {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm
1348                                                   // + vinsertf128
1349       {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4},  // vextractf128 + 2*vpperm
1350                                                   // + vinsertf128
1351 
1352       {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm
1353                                                // + vinsertf128
1354       {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1},  // vpperm
1355       {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9},  // 2*vextractf128 + 6*vpperm
1356                                                // + vinsertf128
1357       {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1},  // vpperm
1358   };
1359 
1360   if (ST->hasXOP())
1361     if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second))
1362       return LT.first * Entry->Cost;
1363 
1364   static const CostTblEntry AVX1ShuffleTbl[] = {
1365       {TTI::SK_Broadcast, MVT::v4f64, 2},  // vperm2f128 + vpermilpd
1366       {TTI::SK_Broadcast, MVT::v8f32, 2},  // vperm2f128 + vpermilps
1367       {TTI::SK_Broadcast, MVT::v4i64, 2},  // vperm2f128 + vpermilpd
1368       {TTI::SK_Broadcast, MVT::v8i32, 2},  // vperm2f128 + vpermilps
1369       {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128
1370       {TTI::SK_Broadcast, MVT::v32i8, 2},  // vpshufb + vinsertf128
1371 
1372       {TTI::SK_Reverse, MVT::v4f64, 2},  // vperm2f128 + vpermilpd
1373       {TTI::SK_Reverse, MVT::v8f32, 2},  // vperm2f128 + vpermilps
1374       {TTI::SK_Reverse, MVT::v4i64, 2},  // vperm2f128 + vpermilpd
1375       {TTI::SK_Reverse, MVT::v8i32, 2},  // vperm2f128 + vpermilps
1376       {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb
1377                                          // + vinsertf128
1378       {TTI::SK_Reverse, MVT::v32i8, 4},  // vextractf128 + 2*pshufb
1379                                          // + vinsertf128
1380 
1381       {TTI::SK_Select, MVT::v4i64, 1},  // vblendpd
1382       {TTI::SK_Select, MVT::v4f64, 1},  // vblendpd
1383       {TTI::SK_Select, MVT::v8i32, 1},  // vblendps
1384       {TTI::SK_Select, MVT::v8f32, 1},  // vblendps
1385       {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor
1386       {TTI::SK_Select, MVT::v32i8, 3},  // vpand + vpandn + vpor
1387 
1388       {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2},  // vperm2f128 + vshufpd
1389       {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2},  // vperm2f128 + vshufpd
1390       {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4},  // 2*vperm2f128 + 2*vshufps
1391       {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4},  // 2*vperm2f128 + 2*vshufps
1392       {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb
1393                                                   // + 2*por + vinsertf128
1394       {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8},  // vextractf128 + 4*pshufb
1395                                                   // + 2*por + vinsertf128
1396 
1397       {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3},   // 2*vperm2f128 + vshufpd
1398       {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3},   // 2*vperm2f128 + vshufpd
1399       {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4},   // 2*vperm2f128 + 2*vshufps
1400       {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4},   // 2*vperm2f128 + 2*vshufps
1401       {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb
1402                                                 // + 4*por + vinsertf128
1403       {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15},  // 2*vextractf128 + 8*pshufb
1404                                                 // + 4*por + vinsertf128
1405   };
1406 
1407   if (ST->hasAVX())
1408     if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second))
1409       return LT.first * Entry->Cost;
1410 
1411   static const CostTblEntry SSE41ShuffleTbl[] = {
1412       {TTI::SK_Select, MVT::v2i64, 1}, // pblendw
1413       {TTI::SK_Select, MVT::v2f64, 1}, // movsd
1414       {TTI::SK_Select, MVT::v4i32, 1}, // pblendw
1415       {TTI::SK_Select, MVT::v4f32, 1}, // blendps
1416       {TTI::SK_Select, MVT::v8i16, 1}, // pblendw
1417       {TTI::SK_Select, MVT::v16i8, 1}  // pblendvb
1418   };
1419 
1420   if (ST->hasSSE41())
1421     if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second))
1422       return LT.first * Entry->Cost;
1423 
1424   static const CostTblEntry SSSE3ShuffleTbl[] = {
1425       {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb
1426       {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb
1427 
1428       {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb
1429       {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb
1430 
1431       {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por
1432       {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por
1433 
1434       {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb
1435       {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb
1436 
1437       {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por
1438       {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por
1439   };
1440 
1441   if (ST->hasSSSE3())
1442     if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second))
1443       return LT.first * Entry->Cost;
1444 
1445   static const CostTblEntry SSE2ShuffleTbl[] = {
1446       {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd
1447       {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd
1448       {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd
1449       {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd
1450       {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd
1451 
1452       {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd
1453       {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd
1454       {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd
1455       {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd
1456       {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw
1457                                         // + 2*pshufd + 2*unpck + packus
1458 
1459       {TTI::SK_Select, MVT::v2i64, 1}, // movsd
1460       {TTI::SK_Select, MVT::v2f64, 1}, // movsd
1461       {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps
1462       {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por
1463       {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por
1464 
1465       {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd
1466       {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd
1467       {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd
1468       {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw
1469                                                   // + pshufd/unpck
1470     { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw
1471                                                   // + 2*pshufd + 2*unpck + 2*packus
1472 
1473     { TTI::SK_PermuteTwoSrc,    MVT::v2f64,  1 }, // shufpd
1474     { TTI::SK_PermuteTwoSrc,    MVT::v2i64,  1 }, // shufpd
1475     { TTI::SK_PermuteTwoSrc,    MVT::v4i32,  2 }, // 2*{unpck,movsd,pshufd}
1476     { TTI::SK_PermuteTwoSrc,    MVT::v8i16,  8 }, // blend+permute
1477     { TTI::SK_PermuteTwoSrc,    MVT::v16i8, 13 }, // blend+permute
1478   };
1479 
1480   if (ST->hasSSE2())
1481     if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second))
1482       return LT.first * Entry->Cost;
1483 
1484   static const CostTblEntry SSE1ShuffleTbl[] = {
1485     { TTI::SK_Broadcast,        MVT::v4f32, 1 }, // shufps
1486     { TTI::SK_Reverse,          MVT::v4f32, 1 }, // shufps
1487     { TTI::SK_Select,           MVT::v4f32, 2 }, // 2*shufps
1488     { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps
1489     { TTI::SK_PermuteTwoSrc,    MVT::v4f32, 2 }, // 2*shufps
1490   };
1491 
1492   if (ST->hasSSE1())
1493     if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second))
1494       return LT.first * Entry->Cost;
1495 
1496   return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp);
1497 }
1498 
1499 InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst,
1500                                              Type *Src,
1501                                              TTI::CastContextHint CCH,
1502                                              TTI::TargetCostKind CostKind,
1503                                              const Instruction *I) {
1504   int ISD = TLI->InstructionOpcodeToISD(Opcode);
1505   assert(ISD && "Invalid opcode");
1506 
1507   // TODO: Allow non-throughput costs that aren't binary.
1508   auto AdjustCost = [&CostKind](InstructionCost Cost) -> InstructionCost {
1509     if (CostKind != TTI::TCK_RecipThroughput)
1510       return Cost == 0 ? 0 : 1;
1511     return Cost;
1512   };
1513 
1514   // FIXME: Need a better design of the cost table to handle non-simple types of
1515   // potential massive combinations (elem_num x src_type x dst_type).
1516 
1517   static const TypeConversionCostTblEntry AVX512BWConversionTbl[] {
1518     { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 },
1519     { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 },
1520 
1521     // Mask sign extend has an instruction.
1522     { ISD::SIGN_EXTEND, MVT::v2i8,   MVT::v2i1,  1 },
1523     { ISD::SIGN_EXTEND, MVT::v2i16,  MVT::v2i1,  1 },
1524     { ISD::SIGN_EXTEND, MVT::v4i8,   MVT::v4i1,  1 },
1525     { ISD::SIGN_EXTEND, MVT::v4i16,  MVT::v4i1,  1 },
1526     { ISD::SIGN_EXTEND, MVT::v8i8,   MVT::v8i1,  1 },
1527     { ISD::SIGN_EXTEND, MVT::v8i16,  MVT::v8i1,  1 },
1528     { ISD::SIGN_EXTEND, MVT::v16i8,  MVT::v16i1, 1 },
1529     { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 },
1530     { ISD::SIGN_EXTEND, MVT::v32i8,  MVT::v32i1, 1 },
1531     { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 },
1532     { ISD::SIGN_EXTEND, MVT::v64i8,  MVT::v64i1, 1 },
1533 
1534     // Mask zero extend is a sext + shift.
1535     { ISD::ZERO_EXTEND, MVT::v2i8,   MVT::v2i1,  2 },
1536     { ISD::ZERO_EXTEND, MVT::v2i16,  MVT::v2i1,  2 },
1537     { ISD::ZERO_EXTEND, MVT::v4i8,   MVT::v4i1,  2 },
1538     { ISD::ZERO_EXTEND, MVT::v4i16,  MVT::v4i1,  2 },
1539     { ISD::ZERO_EXTEND, MVT::v8i8,   MVT::v8i1,  2 },
1540     { ISD::ZERO_EXTEND, MVT::v8i16,  MVT::v8i1,  2 },
1541     { ISD::ZERO_EXTEND, MVT::v16i8,  MVT::v16i1, 2 },
1542     { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 },
1543     { ISD::ZERO_EXTEND, MVT::v32i8,  MVT::v32i1, 2 },
1544     { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 },
1545     { ISD::ZERO_EXTEND, MVT::v64i8,  MVT::v64i1, 2 },
1546 
1547     { ISD::TRUNCATE,    MVT::v32i8,  MVT::v32i16, 2 },
1548     { ISD::TRUNCATE,    MVT::v16i8,  MVT::v16i16, 2 }, // widen to zmm
1549     { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i8,   2 }, // widen to zmm
1550     { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i16,  2 }, // widen to zmm
1551     { ISD::TRUNCATE,    MVT::v2i8,   MVT::v2i16,  2 }, // vpmovwb
1552     { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i8,   2 }, // widen to zmm
1553     { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i16,  2 }, // widen to zmm
1554     { ISD::TRUNCATE,    MVT::v4i8,   MVT::v4i16,  2 }, // vpmovwb
1555     { ISD::TRUNCATE,    MVT::v8i1,   MVT::v8i8,   2 }, // widen to zmm
1556     { ISD::TRUNCATE,    MVT::v8i1,   MVT::v8i16,  2 }, // widen to zmm
1557     { ISD::TRUNCATE,    MVT::v8i8,   MVT::v8i16,  2 }, // vpmovwb
1558     { ISD::TRUNCATE,    MVT::v16i1,  MVT::v16i8,  2 }, // widen to zmm
1559     { ISD::TRUNCATE,    MVT::v16i1,  MVT::v16i16, 2 }, // widen to zmm
1560     { ISD::TRUNCATE,    MVT::v32i1,  MVT::v32i8,  2 }, // widen to zmm
1561     { ISD::TRUNCATE,    MVT::v32i1,  MVT::v32i16, 2 },
1562     { ISD::TRUNCATE,    MVT::v64i1,  MVT::v64i8,  2 },
1563   };
1564 
1565   static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = {
1566     { ISD::SINT_TO_FP,  MVT::v8f32,  MVT::v8i64,  1 },
1567     { ISD::SINT_TO_FP,  MVT::v8f64,  MVT::v8i64,  1 },
1568 
1569     { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v8i64,  1 },
1570     { ISD::UINT_TO_FP,  MVT::v8f64,  MVT::v8i64,  1 },
1571 
1572     { ISD::FP_TO_SINT,  MVT::v8i64,  MVT::v8f32,  1 },
1573     { ISD::FP_TO_SINT,  MVT::v8i64,  MVT::v8f64,  1 },
1574 
1575     { ISD::FP_TO_UINT,  MVT::v8i64,  MVT::v8f32,  1 },
1576     { ISD::FP_TO_UINT,  MVT::v8i64,  MVT::v8f64,  1 },
1577   };
1578 
1579   // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and
1580   // 256-bit wide vectors.
1581 
1582   static const TypeConversionCostTblEntry AVX512FConversionTbl[] = {
1583     { ISD::FP_EXTEND, MVT::v8f64,   MVT::v8f32,  1 },
1584     { ISD::FP_EXTEND, MVT::v8f64,   MVT::v16f32, 3 },
1585     { ISD::FP_ROUND,  MVT::v8f32,   MVT::v8f64,  1 },
1586 
1587     { ISD::TRUNCATE,  MVT::v2i1,    MVT::v2i8,   3 }, // sext+vpslld+vptestmd
1588     { ISD::TRUNCATE,  MVT::v4i1,    MVT::v4i8,   3 }, // sext+vpslld+vptestmd
1589     { ISD::TRUNCATE,  MVT::v8i1,    MVT::v8i8,   3 }, // sext+vpslld+vptestmd
1590     { ISD::TRUNCATE,  MVT::v16i1,   MVT::v16i8,  3 }, // sext+vpslld+vptestmd
1591     { ISD::TRUNCATE,  MVT::v2i1,    MVT::v2i16,  3 }, // sext+vpsllq+vptestmq
1592     { ISD::TRUNCATE,  MVT::v4i1,    MVT::v4i16,  3 }, // sext+vpsllq+vptestmq
1593     { ISD::TRUNCATE,  MVT::v8i1,    MVT::v8i16,  3 }, // sext+vpsllq+vptestmq
1594     { ISD::TRUNCATE,  MVT::v16i1,   MVT::v16i16, 3 }, // sext+vpslld+vptestmd
1595     { ISD::TRUNCATE,  MVT::v2i1,    MVT::v2i32,  2 }, // zmm vpslld+vptestmd
1596     { ISD::TRUNCATE,  MVT::v4i1,    MVT::v4i32,  2 }, // zmm vpslld+vptestmd
1597     { ISD::TRUNCATE,  MVT::v8i1,    MVT::v8i32,  2 }, // zmm vpslld+vptestmd
1598     { ISD::TRUNCATE,  MVT::v16i1,   MVT::v16i32, 2 }, // vpslld+vptestmd
1599     { ISD::TRUNCATE,  MVT::v2i1,    MVT::v2i64,  2 }, // zmm vpsllq+vptestmq
1600     { ISD::TRUNCATE,  MVT::v4i1,    MVT::v4i64,  2 }, // zmm vpsllq+vptestmq
1601     { ISD::TRUNCATE,  MVT::v8i1,    MVT::v8i64,  2 }, // vpsllq+vptestmq
1602     { ISD::TRUNCATE,  MVT::v2i8,    MVT::v2i32,  2 }, // vpmovdb
1603     { ISD::TRUNCATE,  MVT::v4i8,    MVT::v4i32,  2 }, // vpmovdb
1604     { ISD::TRUNCATE,  MVT::v16i8,   MVT::v16i32, 2 }, // vpmovdb
1605     { ISD::TRUNCATE,  MVT::v16i16,  MVT::v16i32, 2 }, // vpmovdb
1606     { ISD::TRUNCATE,  MVT::v2i8,    MVT::v2i64,  2 }, // vpmovqb
1607     { ISD::TRUNCATE,  MVT::v2i16,   MVT::v2i64,  1 }, // vpshufb
1608     { ISD::TRUNCATE,  MVT::v8i8,    MVT::v8i64,  2 }, // vpmovqb
1609     { ISD::TRUNCATE,  MVT::v8i16,   MVT::v8i64,  2 }, // vpmovqw
1610     { ISD::TRUNCATE,  MVT::v8i32,   MVT::v8i64,  1 }, // vpmovqd
1611     { ISD::TRUNCATE,  MVT::v4i32,   MVT::v4i64,  1 }, // zmm vpmovqd
1612     { ISD::TRUNCATE,  MVT::v16i8,   MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb
1613 
1614     { ISD::TRUNCATE,  MVT::v16i8,  MVT::v16i16,  3 }, // extend to v16i32
1615     { ISD::TRUNCATE,  MVT::v32i8,  MVT::v32i16,  8 },
1616 
1617     // Sign extend is zmm vpternlogd+vptruncdb.
1618     // Zero extend is zmm broadcast load+vptruncdw.
1619     { ISD::SIGN_EXTEND, MVT::v2i8,   MVT::v2i1,   3 },
1620     { ISD::ZERO_EXTEND, MVT::v2i8,   MVT::v2i1,   4 },
1621     { ISD::SIGN_EXTEND, MVT::v4i8,   MVT::v4i1,   3 },
1622     { ISD::ZERO_EXTEND, MVT::v4i8,   MVT::v4i1,   4 },
1623     { ISD::SIGN_EXTEND, MVT::v8i8,   MVT::v8i1,   3 },
1624     { ISD::ZERO_EXTEND, MVT::v8i8,   MVT::v8i1,   4 },
1625     { ISD::SIGN_EXTEND, MVT::v16i8,  MVT::v16i1,  3 },
1626     { ISD::ZERO_EXTEND, MVT::v16i8,  MVT::v16i1,  4 },
1627 
1628     // Sign extend is zmm vpternlogd+vptruncdw.
1629     // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw.
1630     { ISD::SIGN_EXTEND, MVT::v2i16,  MVT::v2i1,   3 },
1631     { ISD::ZERO_EXTEND, MVT::v2i16,  MVT::v2i1,   4 },
1632     { ISD::SIGN_EXTEND, MVT::v4i16,  MVT::v4i1,   3 },
1633     { ISD::ZERO_EXTEND, MVT::v4i16,  MVT::v4i1,   4 },
1634     { ISD::SIGN_EXTEND, MVT::v8i16,  MVT::v8i1,   3 },
1635     { ISD::ZERO_EXTEND, MVT::v8i16,  MVT::v8i1,   4 },
1636     { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1,  3 },
1637     { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1,  4 },
1638 
1639     { ISD::SIGN_EXTEND, MVT::v2i32,  MVT::v2i1,   1 }, // zmm vpternlogd
1640     { ISD::ZERO_EXTEND, MVT::v2i32,  MVT::v2i1,   2 }, // zmm vpternlogd+psrld
1641     { ISD::SIGN_EXTEND, MVT::v4i32,  MVT::v4i1,   1 }, // zmm vpternlogd
1642     { ISD::ZERO_EXTEND, MVT::v4i32,  MVT::v4i1,   2 }, // zmm vpternlogd+psrld
1643     { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i1,   1 }, // zmm vpternlogd
1644     { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i1,   2 }, // zmm vpternlogd+psrld
1645     { ISD::SIGN_EXTEND, MVT::v2i64,  MVT::v2i1,   1 }, // zmm vpternlogq
1646     { ISD::ZERO_EXTEND, MVT::v2i64,  MVT::v2i1,   2 }, // zmm vpternlogq+psrlq
1647     { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i1,   1 }, // zmm vpternlogq
1648     { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i1,   2 }, // zmm vpternlogq+psrlq
1649 
1650     { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1,  1 }, // vpternlogd
1651     { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1,  2 }, // vpternlogd+psrld
1652     { ISD::SIGN_EXTEND, MVT::v8i64,  MVT::v8i1,   1 }, // vpternlogq
1653     { ISD::ZERO_EXTEND, MVT::v8i64,  MVT::v8i1,   2 }, // vpternlogq+psrlq
1654 
1655     { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8,  1 },
1656     { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8,  1 },
1657     { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 },
1658     { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 },
1659     { ISD::SIGN_EXTEND, MVT::v8i64,  MVT::v8i8,   1 },
1660     { ISD::ZERO_EXTEND, MVT::v8i64,  MVT::v8i8,   1 },
1661     { ISD::SIGN_EXTEND, MVT::v8i64,  MVT::v8i16,  1 },
1662     { ISD::ZERO_EXTEND, MVT::v8i64,  MVT::v8i16,  1 },
1663     { ISD::SIGN_EXTEND, MVT::v8i64,  MVT::v8i32,  1 },
1664     { ISD::ZERO_EXTEND, MVT::v8i64,  MVT::v8i32,  1 },
1665 
1666     { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right
1667     { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right
1668 
1669     { ISD::SINT_TO_FP,  MVT::v8f64,  MVT::v8i1,   4 },
1670     { ISD::SINT_TO_FP,  MVT::v16f32, MVT::v16i1,  3 },
1671     { ISD::SINT_TO_FP,  MVT::v8f64,  MVT::v8i8,   2 },
1672     { ISD::SINT_TO_FP,  MVT::v16f32, MVT::v16i8,  2 },
1673     { ISD::SINT_TO_FP,  MVT::v8f64,  MVT::v8i16,  2 },
1674     { ISD::SINT_TO_FP,  MVT::v16f32, MVT::v16i16, 2 },
1675     { ISD::SINT_TO_FP,  MVT::v16f32, MVT::v16i32, 1 },
1676     { ISD::SINT_TO_FP,  MVT::v8f64,  MVT::v8i32,  1 },
1677 
1678     { ISD::UINT_TO_FP,  MVT::v8f64,  MVT::v8i1,   4 },
1679     { ISD::UINT_TO_FP,  MVT::v16f32, MVT::v16i1,  3 },
1680     { ISD::UINT_TO_FP,  MVT::v8f64,  MVT::v8i8,   2 },
1681     { ISD::UINT_TO_FP,  MVT::v16f32, MVT::v16i8,  2 },
1682     { ISD::UINT_TO_FP,  MVT::v8f64,  MVT::v8i16,  2 },
1683     { ISD::UINT_TO_FP,  MVT::v16f32, MVT::v16i16, 2 },
1684     { ISD::UINT_TO_FP,  MVT::v8f64,  MVT::v8i32,  1 },
1685     { ISD::UINT_TO_FP,  MVT::v16f32, MVT::v16i32, 1 },
1686     { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v8i64, 26 },
1687     { ISD::UINT_TO_FP,  MVT::v8f64,  MVT::v8i64,  5 },
1688 
1689     { ISD::FP_TO_SINT,  MVT::v8i8,   MVT::v8f64,  3 },
1690     { ISD::FP_TO_SINT,  MVT::v8i16,  MVT::v8f64,  3 },
1691     { ISD::FP_TO_SINT,  MVT::v16i8,  MVT::v16f32, 3 },
1692     { ISD::FP_TO_SINT,  MVT::v16i16, MVT::v16f32, 3 },
1693 
1694     { ISD::FP_TO_UINT,  MVT::v8i32,  MVT::v8f64,  1 },
1695     { ISD::FP_TO_UINT,  MVT::v8i16,  MVT::v8f64,  3 },
1696     { ISD::FP_TO_UINT,  MVT::v8i8,   MVT::v8f64,  3 },
1697     { ISD::FP_TO_UINT,  MVT::v16i32, MVT::v16f32, 1 },
1698     { ISD::FP_TO_UINT,  MVT::v16i16, MVT::v16f32, 3 },
1699     { ISD::FP_TO_UINT,  MVT::v16i8,  MVT::v16f32, 3 },
1700   };
1701 
1702   static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] {
1703     // Mask sign extend has an instruction.
1704     { ISD::SIGN_EXTEND, MVT::v2i8,   MVT::v2i1,  1 },
1705     { ISD::SIGN_EXTEND, MVT::v2i16,  MVT::v2i1,  1 },
1706     { ISD::SIGN_EXTEND, MVT::v4i8,   MVT::v4i1,  1 },
1707     { ISD::SIGN_EXTEND, MVT::v4i16,  MVT::v4i1,  1 },
1708     { ISD::SIGN_EXTEND, MVT::v8i8,   MVT::v8i1,  1 },
1709     { ISD::SIGN_EXTEND, MVT::v8i16,  MVT::v8i1,  1 },
1710     { ISD::SIGN_EXTEND, MVT::v16i8,  MVT::v16i1, 1 },
1711     { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 },
1712     { ISD::SIGN_EXTEND, MVT::v32i8,  MVT::v32i1, 1 },
1713 
1714     // Mask zero extend is a sext + shift.
1715     { ISD::ZERO_EXTEND, MVT::v2i8,   MVT::v2i1,  2 },
1716     { ISD::ZERO_EXTEND, MVT::v2i16,  MVT::v2i1,  2 },
1717     { ISD::ZERO_EXTEND, MVT::v4i8,   MVT::v4i1,  2 },
1718     { ISD::ZERO_EXTEND, MVT::v4i16,  MVT::v4i1,  2 },
1719     { ISD::ZERO_EXTEND, MVT::v8i8,   MVT::v8i1,  2 },
1720     { ISD::ZERO_EXTEND, MVT::v8i16,  MVT::v8i1,  2 },
1721     { ISD::ZERO_EXTEND, MVT::v16i8,  MVT::v16i1, 2 },
1722     { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 },
1723     { ISD::ZERO_EXTEND, MVT::v32i8,  MVT::v32i1, 2 },
1724 
1725     { ISD::TRUNCATE,    MVT::v16i8,  MVT::v16i16, 2 },
1726     { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i8,   2 }, // vpsllw+vptestmb
1727     { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i16,  2 }, // vpsllw+vptestmw
1728     { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i8,   2 }, // vpsllw+vptestmb
1729     { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i16,  2 }, // vpsllw+vptestmw
1730     { ISD::TRUNCATE,    MVT::v8i1,   MVT::v8i8,   2 }, // vpsllw+vptestmb
1731     { ISD::TRUNCATE,    MVT::v8i1,   MVT::v8i16,  2 }, // vpsllw+vptestmw
1732     { ISD::TRUNCATE,    MVT::v16i1,  MVT::v16i8,  2 }, // vpsllw+vptestmb
1733     { ISD::TRUNCATE,    MVT::v16i1,  MVT::v16i16, 2 }, // vpsllw+vptestmw
1734     { ISD::TRUNCATE,    MVT::v32i1,  MVT::v32i8,  2 }, // vpsllw+vptestmb
1735   };
1736 
1737   static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = {
1738     { ISD::SINT_TO_FP,  MVT::v2f32,  MVT::v2i64,  1 },
1739     { ISD::SINT_TO_FP,  MVT::v2f64,  MVT::v2i64,  1 },
1740     { ISD::SINT_TO_FP,  MVT::v4f32,  MVT::v4i64,  1 },
1741     { ISD::SINT_TO_FP,  MVT::v4f64,  MVT::v4i64,  1 },
1742 
1743     { ISD::UINT_TO_FP,  MVT::v2f32,  MVT::v2i64,  1 },
1744     { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v2i64,  1 },
1745     { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v4i64,  1 },
1746     { ISD::UINT_TO_FP,  MVT::v4f64,  MVT::v4i64,  1 },
1747 
1748     { ISD::FP_TO_SINT,  MVT::v2i64,  MVT::v2f32,  1 },
1749     { ISD::FP_TO_SINT,  MVT::v4i64,  MVT::v4f32,  1 },
1750     { ISD::FP_TO_SINT,  MVT::v2i64,  MVT::v2f64,  1 },
1751     { ISD::FP_TO_SINT,  MVT::v4i64,  MVT::v4f64,  1 },
1752 
1753     { ISD::FP_TO_UINT,  MVT::v2i64,  MVT::v2f32,  1 },
1754     { ISD::FP_TO_UINT,  MVT::v4i64,  MVT::v4f32,  1 },
1755     { ISD::FP_TO_UINT,  MVT::v2i64,  MVT::v2f64,  1 },
1756     { ISD::FP_TO_UINT,  MVT::v4i64,  MVT::v4f64,  1 },
1757   };
1758 
1759   static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = {
1760     { ISD::TRUNCATE,  MVT::v2i1,    MVT::v2i8,   3 }, // sext+vpslld+vptestmd
1761     { ISD::TRUNCATE,  MVT::v4i1,    MVT::v4i8,   3 }, // sext+vpslld+vptestmd
1762     { ISD::TRUNCATE,  MVT::v8i1,    MVT::v8i8,   3 }, // sext+vpslld+vptestmd
1763     { ISD::TRUNCATE,  MVT::v16i1,   MVT::v16i8,  8 }, // split+2*v8i8
1764     { ISD::TRUNCATE,  MVT::v2i1,    MVT::v2i16,  3 }, // sext+vpsllq+vptestmq
1765     { ISD::TRUNCATE,  MVT::v4i1,    MVT::v4i16,  3 }, // sext+vpsllq+vptestmq
1766     { ISD::TRUNCATE,  MVT::v8i1,    MVT::v8i16,  3 }, // sext+vpsllq+vptestmq
1767     { ISD::TRUNCATE,  MVT::v16i1,   MVT::v16i16, 8 }, // split+2*v8i16
1768     { ISD::TRUNCATE,  MVT::v2i1,    MVT::v2i32,  2 }, // vpslld+vptestmd
1769     { ISD::TRUNCATE,  MVT::v4i1,    MVT::v4i32,  2 }, // vpslld+vptestmd
1770     { ISD::TRUNCATE,  MVT::v8i1,    MVT::v8i32,  2 }, // vpslld+vptestmd
1771     { ISD::TRUNCATE,  MVT::v2i1,    MVT::v2i64,  2 }, // vpsllq+vptestmq
1772     { ISD::TRUNCATE,  MVT::v4i1,    MVT::v4i64,  2 }, // vpsllq+vptestmq
1773     { ISD::TRUNCATE,  MVT::v4i32,   MVT::v4i64,  1 }, // vpmovqd
1774     { ISD::TRUNCATE,  MVT::v4i8,    MVT::v4i64,  2 }, // vpmovqb
1775     { ISD::TRUNCATE,  MVT::v4i16,   MVT::v4i64,  2 }, // vpmovqw
1776     { ISD::TRUNCATE,  MVT::v8i8,    MVT::v8i32,  2 }, // vpmovwb
1777 
1778     // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb
1779     // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb
1780     { ISD::SIGN_EXTEND, MVT::v2i8,   MVT::v2i1,   5 },
1781     { ISD::ZERO_EXTEND, MVT::v2i8,   MVT::v2i1,   6 },
1782     { ISD::SIGN_EXTEND, MVT::v4i8,   MVT::v4i1,   5 },
1783     { ISD::ZERO_EXTEND, MVT::v4i8,   MVT::v4i1,   6 },
1784     { ISD::SIGN_EXTEND, MVT::v8i8,   MVT::v8i1,   5 },
1785     { ISD::ZERO_EXTEND, MVT::v8i8,   MVT::v8i1,   6 },
1786     { ISD::SIGN_EXTEND, MVT::v16i8,  MVT::v16i1, 10 },
1787     { ISD::ZERO_EXTEND, MVT::v16i8,  MVT::v16i1, 12 },
1788 
1789     // sign extend is vpcmpeq+maskedmove+vpmovdw
1790     // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw
1791     { ISD::SIGN_EXTEND, MVT::v2i16,  MVT::v2i1,   4 },
1792     { ISD::ZERO_EXTEND, MVT::v2i16,  MVT::v2i1,   5 },
1793     { ISD::SIGN_EXTEND, MVT::v4i16,  MVT::v4i1,   4 },
1794     { ISD::ZERO_EXTEND, MVT::v4i16,  MVT::v4i1,   5 },
1795     { ISD::SIGN_EXTEND, MVT::v8i16,  MVT::v8i1,   4 },
1796     { ISD::ZERO_EXTEND, MVT::v8i16,  MVT::v8i1,   5 },
1797     { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 },
1798     { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 },
1799 
1800     { ISD::SIGN_EXTEND, MVT::v2i32,  MVT::v2i1,   1 }, // vpternlogd
1801     { ISD::ZERO_EXTEND, MVT::v2i32,  MVT::v2i1,   2 }, // vpternlogd+psrld
1802     { ISD::SIGN_EXTEND, MVT::v4i32,  MVT::v4i1,   1 }, // vpternlogd
1803     { ISD::ZERO_EXTEND, MVT::v4i32,  MVT::v4i1,   2 }, // vpternlogd+psrld
1804     { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i1,   1 }, // vpternlogd
1805     { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i1,   2 }, // vpternlogd+psrld
1806     { ISD::SIGN_EXTEND, MVT::v2i64,  MVT::v2i1,   1 }, // vpternlogq
1807     { ISD::ZERO_EXTEND, MVT::v2i64,  MVT::v2i1,   2 }, // vpternlogq+psrlq
1808     { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i1,   1 }, // vpternlogq
1809     { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i1,   2 }, // vpternlogq+psrlq
1810 
1811     { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v2i8,   2 },
1812     { ISD::UINT_TO_FP,  MVT::v4f64,  MVT::v4i8,   2 },
1813     { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v8i8,   2 },
1814     { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v2i16,  5 },
1815     { ISD::UINT_TO_FP,  MVT::v4f64,  MVT::v4i16,  2 },
1816     { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v8i16,  2 },
1817     { ISD::UINT_TO_FP,  MVT::v2f32,  MVT::v2i32,  2 },
1818     { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v2i32,  1 },
1819     { ISD::UINT_TO_FP,  MVT::v4f32,  MVT::v4i32,  1 },
1820     { ISD::UINT_TO_FP,  MVT::v4f64,  MVT::v4i32,  1 },
1821     { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v8i32,  1 },
1822     { ISD::UINT_TO_FP,  MVT::v2f32,  MVT::v2i64,  5 },
1823     { ISD::UINT_TO_FP,  MVT::v2f64,  MVT::v2i64,  5 },
1824     { ISD::UINT_TO_FP,  MVT::v4f64,  MVT::v4i64,  5 },
1825 
1826     { ISD::UINT_TO_FP,  MVT::f32,    MVT::i64,    1 },
1827     { ISD::UINT_TO_FP,  MVT::f64,    MVT::i64,    1 },
1828 
1829     { ISD::FP_TO_SINT,  MVT::v8i8,   MVT::v8f32,  3 },
1830     { ISD::FP_TO_UINT,  MVT::v8i8,   MVT::v8f32,  3 },
1831 
1832     { ISD::FP_TO_UINT,  MVT::i64,    MVT::f32,    1 },
1833     { ISD::FP_TO_UINT,  MVT::i64,    MVT::f64,    1 },
1834 
1835     { ISD::FP_TO_UINT,  MVT::v2i32,  MVT::v2f32,  1 },
1836     { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v4f32,  1 },
1837     { ISD::FP_TO_UINT,  MVT::v2i32,  MVT::v2f64,  1 },
1838     { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v4f64,  1 },
1839     { ISD::FP_TO_UINT,  MVT::v8i32,  MVT::v8f32,  1 },
1840   };
1841 
1842   static const TypeConversionCostTblEntry AVX2ConversionTbl[] = {
1843     { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i1,   3 },
1844     { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i1,   3 },
1845     { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i1,   3 },
1846     { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i1,   3 },
1847     { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i8,   1 },
1848     { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i8,   1 },
1849     { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i8,   1 },
1850     { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i8,   1 },
1851     { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1,  1 },
1852     { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1,  1 },
1853     { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8,  1 },
1854     { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8,  1 },
1855     { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i16,  1 },
1856     { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i16,  1 },
1857     { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i16,  1 },
1858     { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i16,  1 },
1859     { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i32,  1 },
1860     { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i32,  1 },
1861     { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 },
1862     { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 },
1863 
1864     { ISD::TRUNCATE,    MVT::v4i32,  MVT::v4i64,  2 },
1865     { ISD::TRUNCATE,    MVT::v8i1,   MVT::v8i32,  2 },
1866     { ISD::TRUNCATE,    MVT::v8i16,  MVT::v8i32,  2 },
1867 
1868     { ISD::FP_EXTEND,   MVT::v8f64,  MVT::v8f32,  3 },
1869     { ISD::FP_ROUND,    MVT::v8f32,  MVT::v8f64,  3 },
1870 
1871     { ISD::UINT_TO_FP,  MVT::v8f32,  MVT::v8i32,  5 },
1872   };
1873 
1874   static const TypeConversionCostTblEntry AVXConversionTbl[] = {
1875     { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i1,  6 },
1876     { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i1,  4 },
1877     { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i1,  7 },
1878     { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i1,  4 },
1879     { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i8,  3 },
1880     { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i8,  3 },
1881     { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i8,  3 },
1882     { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i8,  3 },
1883     { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 },
1884     { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 },
1885     { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 3 },
1886     { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 },
1887     { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i16, 3 },
1888     { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i16, 3 },
1889     { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i16, 3 },
1890     { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i16, 3 },
1891     { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i32, 3 },
1892     { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i32, 3 },
1893 
1894     { ISD::TRUNCATE,    MVT::v4i1,  MVT::v4i64,  4 },
1895     { ISD::TRUNCATE,    MVT::v8i1,  MVT::v8i32,  5 },
1896     { ISD::TRUNCATE,    MVT::v16i1, MVT::v16i16, 4 },
1897     { ISD::TRUNCATE,    MVT::v8i1,  MVT::v8i64,  9 },
1898     { ISD::TRUNCATE,    MVT::v16i1, MVT::v16i64, 11 },
1899 
1900     { ISD::TRUNCATE,    MVT::v16i8, MVT::v16i16, 4 },
1901     { ISD::TRUNCATE,    MVT::v8i8,  MVT::v8i32,  4 },
1902     { ISD::TRUNCATE,    MVT::v8i16, MVT::v8i32,  5 },
1903     { ISD::TRUNCATE,    MVT::v4i8,  MVT::v4i64,  4 },
1904     { ISD::TRUNCATE,    MVT::v4i16, MVT::v4i64,  4 },
1905     { ISD::TRUNCATE,    MVT::v4i32, MVT::v4i64,  2 },
1906     { ISD::TRUNCATE,    MVT::v8i8,  MVT::v8i64, 11 },
1907     { ISD::TRUNCATE,    MVT::v8i16, MVT::v8i64,  9 },
1908     { ISD::TRUNCATE,    MVT::v8i32, MVT::v8i64,  3 },
1909     { ISD::TRUNCATE,    MVT::v16i8, MVT::v16i64, 11 },
1910 
1911     { ISD::SINT_TO_FP,  MVT::v4f32, MVT::v4i1,  3 },
1912     { ISD::SINT_TO_FP,  MVT::v4f64, MVT::v4i1,  3 },
1913     { ISD::SINT_TO_FP,  MVT::v8f32, MVT::v8i1,  8 },
1914     { ISD::SINT_TO_FP,  MVT::v4f32, MVT::v4i8,  3 },
1915     { ISD::SINT_TO_FP,  MVT::v4f64, MVT::v4i8,  3 },
1916     { ISD::SINT_TO_FP,  MVT::v8f32, MVT::v8i8,  8 },
1917     { ISD::SINT_TO_FP,  MVT::v4f32, MVT::v4i16, 3 },
1918     { ISD::SINT_TO_FP,  MVT::v4f64, MVT::v4i16, 3 },
1919     { ISD::SINT_TO_FP,  MVT::v8f32, MVT::v8i16, 5 },
1920     { ISD::SINT_TO_FP,  MVT::v4f32, MVT::v4i32, 1 },
1921     { ISD::SINT_TO_FP,  MVT::v4f64, MVT::v4i32, 1 },
1922     { ISD::SINT_TO_FP,  MVT::v8f32, MVT::v8i32, 1 },
1923 
1924     { ISD::UINT_TO_FP,  MVT::v4f32, MVT::v4i1,  7 },
1925     { ISD::UINT_TO_FP,  MVT::v4f64, MVT::v4i1,  7 },
1926     { ISD::UINT_TO_FP,  MVT::v8f32, MVT::v8i1,  6 },
1927     { ISD::UINT_TO_FP,  MVT::v4f32, MVT::v4i8,  2 },
1928     { ISD::UINT_TO_FP,  MVT::v4f64, MVT::v4i8,  2 },
1929     { ISD::UINT_TO_FP,  MVT::v8f32, MVT::v8i8,  5 },
1930     { ISD::UINT_TO_FP,  MVT::v4f32, MVT::v4i16, 2 },
1931     { ISD::UINT_TO_FP,  MVT::v4f64, MVT::v4i16, 2 },
1932     { ISD::UINT_TO_FP,  MVT::v8f32, MVT::v8i16, 5 },
1933     { ISD::UINT_TO_FP,  MVT::v2f64, MVT::v2i32, 6 },
1934     { ISD::UINT_TO_FP,  MVT::v4f32, MVT::v4i32, 6 },
1935     { ISD::UINT_TO_FP,  MVT::v4f64, MVT::v4i32, 6 },
1936     { ISD::UINT_TO_FP,  MVT::v8f32, MVT::v8i32, 8 },
1937     { ISD::UINT_TO_FP,  MVT::v2f64, MVT::v2i64, 5 },
1938     { ISD::UINT_TO_FP,  MVT::v4f64, MVT::v4i64, 6 },
1939     // The generic code to compute the scalar overhead is currently broken.
1940     // Workaround this limitation by estimating the scalarization overhead
1941     // here. We have roughly 10 instructions per scalar element.
1942     // Multiply that by the vector width.
1943     // FIXME: remove that when PR19268 is fixed.
1944     { ISD::SINT_TO_FP,  MVT::v4f64, MVT::v4i64, 13 },
1945     { ISD::SINT_TO_FP,  MVT::v4f64, MVT::v4i64, 13 },
1946 
1947     { ISD::FP_TO_SINT,  MVT::v8i8,  MVT::v8f32, 4 },
1948     { ISD::FP_TO_SINT,  MVT::v4i8,  MVT::v4f64, 3 },
1949     { ISD::FP_TO_SINT,  MVT::v4i16, MVT::v4f64, 2 },
1950     { ISD::FP_TO_SINT,  MVT::v8i16, MVT::v8f32, 3 },
1951 
1952     { ISD::FP_TO_UINT,  MVT::v4i8,  MVT::v4f64, 3 },
1953     { ISD::FP_TO_UINT,  MVT::v4i16, MVT::v4f64, 2 },
1954     { ISD::FP_TO_UINT,  MVT::v8i8,  MVT::v8f32, 4 },
1955     { ISD::FP_TO_UINT,  MVT::v8i16, MVT::v8f32, 3 },
1956     { ISD::FP_TO_UINT,  MVT::v8i32, MVT::v8f32, 9 },
1957     // This node is expanded into scalarized operations but BasicTTI is overly
1958     // optimistic estimating its cost.  It computes 3 per element (one
1959     // vector-extract, one scalar conversion and one vector-insert).  The
1960     // problem is that the inserts form a read-modify-write chain so latency
1961     // should be factored in too.  Inflating the cost per element by 1.
1962     { ISD::FP_TO_UINT,  MVT::v4i32, MVT::v4f64, 4*4 },
1963 
1964     { ISD::FP_EXTEND,   MVT::v4f64,  MVT::v4f32,  1 },
1965     { ISD::FP_ROUND,    MVT::v4f32,  MVT::v4f64,  1 },
1966   };
1967 
1968   static const TypeConversionCostTblEntry SSE41ConversionTbl[] = {
1969     { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8,    2 },
1970     { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8,    2 },
1971     { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16,   2 },
1972     { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16,   2 },
1973     { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32,   2 },
1974     { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32,   2 },
1975 
1976     { ISD::ZERO_EXTEND, MVT::v2i16,  MVT::v2i8,   1 },
1977     { ISD::SIGN_EXTEND, MVT::v2i16,  MVT::v2i8,   1 },
1978     { ISD::ZERO_EXTEND, MVT::v2i32,  MVT::v2i8,   1 },
1979     { ISD::SIGN_EXTEND, MVT::v2i32,  MVT::v2i8,   1 },
1980     { ISD::ZERO_EXTEND, MVT::v2i64,  MVT::v2i8,   1 },
1981     { ISD::SIGN_EXTEND, MVT::v2i64,  MVT::v2i8,   1 },
1982     { ISD::ZERO_EXTEND, MVT::v4i16,  MVT::v4i8,   1 },
1983     { ISD::SIGN_EXTEND, MVT::v4i16,  MVT::v4i8,   1 },
1984     { ISD::ZERO_EXTEND, MVT::v4i32,  MVT::v4i8,   1 },
1985     { ISD::SIGN_EXTEND, MVT::v4i32,  MVT::v4i8,   1 },
1986     { ISD::ZERO_EXTEND, MVT::v8i16,  MVT::v8i8,   1 },
1987     { ISD::SIGN_EXTEND, MVT::v8i16,  MVT::v8i8,   1 },
1988     { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i8,   2 },
1989     { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i8,   2 },
1990     { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8,  2 },
1991     { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8,  2 },
1992     { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8,  4 },
1993     { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8,  4 },
1994     { ISD::ZERO_EXTEND, MVT::v2i32,  MVT::v2i16,  1 },
1995     { ISD::SIGN_EXTEND, MVT::v2i32,  MVT::v2i16,  1 },
1996     { ISD::ZERO_EXTEND, MVT::v2i64,  MVT::v2i16,  1 },
1997     { ISD::SIGN_EXTEND, MVT::v2i64,  MVT::v2i16,  1 },
1998     { ISD::ZERO_EXTEND, MVT::v4i32,  MVT::v4i16,  1 },
1999     { ISD::SIGN_EXTEND, MVT::v4i32,  MVT::v4i16,  1 },
2000     { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i16,  2 },
2001     { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i16,  2 },
2002     { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 },
2003     { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 },
2004     { ISD::ZERO_EXTEND, MVT::v2i64,  MVT::v2i32,  1 },
2005     { ISD::SIGN_EXTEND, MVT::v2i64,  MVT::v2i32,  1 },
2006 
2007     // These truncates end up widening elements.
2008     { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i8,   1 }, // PMOVXZBQ
2009     { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i16,  1 }, // PMOVXZWQ
2010     { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i8,   1 }, // PMOVXZBD
2011 
2012     { ISD::TRUNCATE,    MVT::v2i8,   MVT::v2i16,  1 },
2013     { ISD::TRUNCATE,    MVT::v4i8,   MVT::v4i16,  1 },
2014     { ISD::TRUNCATE,    MVT::v8i8,   MVT::v8i16,  1 },
2015     { ISD::TRUNCATE,    MVT::v4i8,   MVT::v4i32,  1 },
2016     { ISD::TRUNCATE,    MVT::v4i16,  MVT::v4i32,  1 },
2017     { ISD::TRUNCATE,    MVT::v8i8,   MVT::v8i32,  3 },
2018     { ISD::TRUNCATE,    MVT::v8i16,  MVT::v8i32,  3 },
2019     { ISD::TRUNCATE,    MVT::v16i16, MVT::v16i32, 6 },
2020     { ISD::TRUNCATE,    MVT::v2i8,   MVT::v2i64,  1 }, // PSHUFB
2021 
2022     { ISD::UINT_TO_FP,  MVT::f32,    MVT::i64,    4 },
2023     { ISD::UINT_TO_FP,  MVT::f64,    MVT::i64,    4 },
2024 
2025     { ISD::FP_TO_SINT,  MVT::v2i8,   MVT::v2f32,  3 },
2026     { ISD::FP_TO_SINT,  MVT::v2i8,   MVT::v2f64,  3 },
2027 
2028     { ISD::FP_TO_UINT,  MVT::v2i8,   MVT::v2f32,  3 },
2029     { ISD::FP_TO_UINT,  MVT::v2i8,   MVT::v2f64,  3 },
2030     { ISD::FP_TO_UINT,  MVT::v4i16,  MVT::v4f32,  2 },
2031   };
2032 
2033   static const TypeConversionCostTblEntry SSE2ConversionTbl[] = {
2034     // These are somewhat magic numbers justified by looking at the output of
2035     // Intel's IACA, running some kernels and making sure when we take
2036     // legalization into account the throughput will be overestimated.
2037     { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
2038     { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
2039     { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
2040     { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
2041     { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 },
2042     { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 2*10 },
2043     { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2*10 },
2044     { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
2045     { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
2046 
2047     { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
2048     { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
2049     { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
2050     { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
2051     { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
2052     { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 },
2053     { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 },
2054     { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
2055 
2056     { ISD::FP_TO_SINT,  MVT::v2i8,   MVT::v2f32,  4 },
2057     { ISD::FP_TO_SINT,  MVT::v2i16,  MVT::v2f32,  2 },
2058     { ISD::FP_TO_SINT,  MVT::v4i8,   MVT::v4f32,  3 },
2059     { ISD::FP_TO_SINT,  MVT::v4i16,  MVT::v4f32,  2 },
2060     { ISD::FP_TO_SINT,  MVT::v2i16,  MVT::v2f64,  2 },
2061     { ISD::FP_TO_SINT,  MVT::v2i8,   MVT::v2f64,  4 },
2062 
2063     { ISD::FP_TO_SINT,  MVT::v2i32,  MVT::v2f64,  1 },
2064 
2065     { ISD::UINT_TO_FP,  MVT::f32,    MVT::i64,    6 },
2066     { ISD::UINT_TO_FP,  MVT::f64,    MVT::i64,    6 },
2067 
2068     { ISD::FP_TO_UINT,  MVT::i64,    MVT::f32,    4 },
2069     { ISD::FP_TO_UINT,  MVT::i64,    MVT::f64,    4 },
2070     { ISD::FP_TO_UINT,  MVT::v2i8,   MVT::v2f32,  4 },
2071     { ISD::FP_TO_UINT,  MVT::v2i8,   MVT::v2f64,  4 },
2072     { ISD::FP_TO_UINT,  MVT::v4i8,   MVT::v4f32,  3 },
2073     { ISD::FP_TO_UINT,  MVT::v2i16,  MVT::v2f32,  2 },
2074     { ISD::FP_TO_UINT,  MVT::v2i16,  MVT::v2f64,  2 },
2075     { ISD::FP_TO_UINT,  MVT::v4i16,  MVT::v4f32,  4 },
2076     { ISD::FP_TO_UINT,  MVT::v4i32,  MVT::v4f32,  8 },
2077 
2078     { ISD::ZERO_EXTEND, MVT::v4i16,  MVT::v4i8,   1 },
2079     { ISD::SIGN_EXTEND, MVT::v4i16,  MVT::v4i8,   6 },
2080     { ISD::ZERO_EXTEND, MVT::v4i32,  MVT::v4i8,   2 },
2081     { ISD::SIGN_EXTEND, MVT::v4i32,  MVT::v4i8,   3 },
2082     { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i8,   4 },
2083     { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i8,   8 },
2084     { ISD::ZERO_EXTEND, MVT::v8i16,  MVT::v8i8,   1 },
2085     { ISD::SIGN_EXTEND, MVT::v8i16,  MVT::v8i8,   2 },
2086     { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i8,   6 },
2087     { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i8,   6 },
2088     { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8,  3 },
2089     { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8,  4 },
2090     { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8,  9 },
2091     { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8,  12 },
2092     { ISD::ZERO_EXTEND, MVT::v4i32,  MVT::v4i16,  1 },
2093     { ISD::SIGN_EXTEND, MVT::v4i32,  MVT::v4i16,  2 },
2094     { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i16,  3 },
2095     { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i16,  10 },
2096     { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i16,  3 },
2097     { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i16,  4 },
2098     { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 },
2099     { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 },
2100     { ISD::ZERO_EXTEND, MVT::v4i64,  MVT::v4i32,  3 },
2101     { ISD::SIGN_EXTEND, MVT::v4i64,  MVT::v4i32,  5 },
2102 
2103     // These truncates are really widening elements.
2104     { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i32,  1 }, // PSHUFD
2105     { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i16,  2 }, // PUNPCKLWD+DQ
2106     { ISD::TRUNCATE,    MVT::v2i1,   MVT::v2i8,   3 }, // PUNPCKLBW+WD+PSHUFD
2107     { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i16,  1 }, // PUNPCKLWD
2108     { ISD::TRUNCATE,    MVT::v4i1,   MVT::v4i8,   2 }, // PUNPCKLBW+WD
2109     { ISD::TRUNCATE,    MVT::v8i1,   MVT::v8i8,   1 }, // PUNPCKLBW
2110 
2111     { ISD::TRUNCATE,    MVT::v2i8,   MVT::v2i16,  2 }, // PAND+PACKUSWB
2112     { ISD::TRUNCATE,    MVT::v4i8,   MVT::v4i16,  2 }, // PAND+PACKUSWB
2113     { ISD::TRUNCATE,    MVT::v8i8,   MVT::v8i16,  2 }, // PAND+PACKUSWB
2114     { ISD::TRUNCATE,    MVT::v16i8,  MVT::v16i16, 3 },
2115     { ISD::TRUNCATE,    MVT::v2i8,   MVT::v2i32,  3 }, // PAND+2*PACKUSWB
2116     { ISD::TRUNCATE,    MVT::v2i16,  MVT::v2i32,  1 },
2117     { ISD::TRUNCATE,    MVT::v4i8,   MVT::v4i32,  3 },
2118     { ISD::TRUNCATE,    MVT::v4i16,  MVT::v4i32,  3 },
2119     { ISD::TRUNCATE,    MVT::v8i8,   MVT::v8i32,  4 },
2120     { ISD::TRUNCATE,    MVT::v16i8,  MVT::v16i32, 7 },
2121     { ISD::TRUNCATE,    MVT::v8i16,  MVT::v8i32,  5 },
2122     { ISD::TRUNCATE,    MVT::v16i16, MVT::v16i32, 10 },
2123     { ISD::TRUNCATE,    MVT::v2i8,   MVT::v2i64,  4 }, // PAND+3*PACKUSWB
2124     { ISD::TRUNCATE,    MVT::v2i16,  MVT::v2i64,  2 }, // PSHUFD+PSHUFLW
2125     { ISD::TRUNCATE,    MVT::v2i32,  MVT::v2i64,  1 }, // PSHUFD
2126   };
2127 
2128   std::pair<InstructionCost, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src);
2129   std::pair<InstructionCost, MVT> LTDest =
2130       TLI->getTypeLegalizationCost(DL, Dst);
2131 
2132   if (ST->hasSSE41() && !ST->hasAVX())
2133     if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD,
2134                                                    LTDest.second, LTSrc.second))
2135       return AdjustCost(LTSrc.first * Entry->Cost);
2136 
2137   if (ST->hasSSE2() && !ST->hasAVX())
2138     if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD,
2139                                                    LTDest.second, LTSrc.second))
2140       return AdjustCost(LTSrc.first * Entry->Cost);
2141 
2142   EVT SrcTy = TLI->getValueType(DL, Src);
2143   EVT DstTy = TLI->getValueType(DL, Dst);
2144 
2145   // The function getSimpleVT only handles simple value types.
2146   if (!SrcTy.isSimple() || !DstTy.isSimple())
2147     return AdjustCost(BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind));
2148 
2149   MVT SimpleSrcTy = SrcTy.getSimpleVT();
2150   MVT SimpleDstTy = DstTy.getSimpleVT();
2151 
2152   if (ST->useAVX512Regs()) {
2153     if (ST->hasBWI())
2154       if (const auto *Entry = ConvertCostTableLookup(AVX512BWConversionTbl, ISD,
2155                                                      SimpleDstTy, SimpleSrcTy))
2156         return AdjustCost(Entry->Cost);
2157 
2158     if (ST->hasDQI())
2159       if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD,
2160                                                      SimpleDstTy, SimpleSrcTy))
2161         return AdjustCost(Entry->Cost);
2162 
2163     if (ST->hasAVX512())
2164       if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD,
2165                                                      SimpleDstTy, SimpleSrcTy))
2166         return AdjustCost(Entry->Cost);
2167   }
2168 
2169   if (ST->hasBWI())
2170     if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD,
2171                                                    SimpleDstTy, SimpleSrcTy))
2172       return AdjustCost(Entry->Cost);
2173 
2174   if (ST->hasDQI())
2175     if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD,
2176                                                    SimpleDstTy, SimpleSrcTy))
2177       return AdjustCost(Entry->Cost);
2178 
2179   if (ST->hasAVX512())
2180     if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD,
2181                                                    SimpleDstTy, SimpleSrcTy))
2182       return AdjustCost(Entry->Cost);
2183 
2184   if (ST->hasAVX2()) {
2185     if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD,
2186                                                    SimpleDstTy, SimpleSrcTy))
2187       return AdjustCost(Entry->Cost);
2188   }
2189 
2190   if (ST->hasAVX()) {
2191     if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD,
2192                                                    SimpleDstTy, SimpleSrcTy))
2193       return AdjustCost(Entry->Cost);
2194   }
2195 
2196   if (ST->hasSSE41()) {
2197     if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD,
2198                                                    SimpleDstTy, SimpleSrcTy))
2199       return AdjustCost(Entry->Cost);
2200   }
2201 
2202   if (ST->hasSSE2()) {
2203     if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD,
2204                                                    SimpleDstTy, SimpleSrcTy))
2205       return AdjustCost(Entry->Cost);
2206   }
2207 
2208   return AdjustCost(
2209       BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I));
2210 }
2211 
2212 InstructionCost X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
2213                                                Type *CondTy,
2214                                                CmpInst::Predicate VecPred,
2215                                                TTI::TargetCostKind CostKind,
2216                                                const Instruction *I) {
2217   // TODO: Handle other cost kinds.
2218   if (CostKind != TTI::TCK_RecipThroughput)
2219     return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind,
2220                                      I);
2221 
2222   // Legalize the type.
2223   std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
2224 
2225   MVT MTy = LT.second;
2226 
2227   int ISD = TLI->InstructionOpcodeToISD(Opcode);
2228   assert(ISD && "Invalid opcode");
2229 
2230   unsigned ExtraCost = 0;
2231   if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) {
2232     // Some vector comparison predicates cost extra instructions.
2233     if (MTy.isVector() &&
2234         !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) ||
2235           (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) ||
2236           ST->hasBWI())) {
2237       switch (cast<CmpInst>(I)->getPredicate()) {
2238       case CmpInst::Predicate::ICMP_NE:
2239         // xor(cmpeq(x,y),-1)
2240         ExtraCost = 1;
2241         break;
2242       case CmpInst::Predicate::ICMP_SGE:
2243       case CmpInst::Predicate::ICMP_SLE:
2244         // xor(cmpgt(x,y),-1)
2245         ExtraCost = 1;
2246         break;
2247       case CmpInst::Predicate::ICMP_ULT:
2248       case CmpInst::Predicate::ICMP_UGT:
2249         // cmpgt(xor(x,signbit),xor(y,signbit))
2250         // xor(cmpeq(pmaxu(x,y),x),-1)
2251         ExtraCost = 2;
2252         break;
2253       case CmpInst::Predicate::ICMP_ULE:
2254       case CmpInst::Predicate::ICMP_UGE:
2255         if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) ||
2256             (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) {
2257           // cmpeq(psubus(x,y),0)
2258           // cmpeq(pminu(x,y),x)
2259           ExtraCost = 1;
2260         } else {
2261           // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1)
2262           ExtraCost = 3;
2263         }
2264         break;
2265       default:
2266         break;
2267       }
2268     }
2269   }
2270 
2271   static const CostTblEntry SLMCostTbl[] = {
2272     // slm pcmpeq/pcmpgt throughput is 2
2273     { ISD::SETCC,   MVT::v2i64,   2 },
2274   };
2275 
2276   static const CostTblEntry AVX512BWCostTbl[] = {
2277     { ISD::SETCC,   MVT::v32i16,  1 },
2278     { ISD::SETCC,   MVT::v64i8,   1 },
2279 
2280     { ISD::SELECT,  MVT::v32i16,  1 },
2281     { ISD::SELECT,  MVT::v64i8,   1 },
2282   };
2283 
2284   static const CostTblEntry AVX512CostTbl[] = {
2285     { ISD::SETCC,   MVT::v8i64,   1 },
2286     { ISD::SETCC,   MVT::v16i32,  1 },
2287     { ISD::SETCC,   MVT::v8f64,   1 },
2288     { ISD::SETCC,   MVT::v16f32,  1 },
2289 
2290     { ISD::SELECT,  MVT::v8i64,   1 },
2291     { ISD::SELECT,  MVT::v16i32,  1 },
2292     { ISD::SELECT,  MVT::v8f64,   1 },
2293     { ISD::SELECT,  MVT::v16f32,  1 },
2294 
2295     { ISD::SETCC,   MVT::v32i16,  2 }, // FIXME: should probably be 4
2296     { ISD::SETCC,   MVT::v64i8,   2 }, // FIXME: should probably be 4
2297 
2298     { ISD::SELECT,  MVT::v32i16,  2 }, // FIXME: should be 3
2299     { ISD::SELECT,  MVT::v64i8,   2 }, // FIXME: should be 3
2300   };
2301 
2302   static const CostTblEntry AVX2CostTbl[] = {
2303     { ISD::SETCC,   MVT::v4i64,   1 },
2304     { ISD::SETCC,   MVT::v8i32,   1 },
2305     { ISD::SETCC,   MVT::v16i16,  1 },
2306     { ISD::SETCC,   MVT::v32i8,   1 },
2307 
2308     { ISD::SELECT,  MVT::v4i64,   1 }, // pblendvb
2309     { ISD::SELECT,  MVT::v8i32,   1 }, // pblendvb
2310     { ISD::SELECT,  MVT::v16i16,  1 }, // pblendvb
2311     { ISD::SELECT,  MVT::v32i8,   1 }, // pblendvb
2312   };
2313 
2314   static const CostTblEntry AVX1CostTbl[] = {
2315     { ISD::SETCC,   MVT::v4f64,   1 },
2316     { ISD::SETCC,   MVT::v8f32,   1 },
2317     // AVX1 does not support 8-wide integer compare.
2318     { ISD::SETCC,   MVT::v4i64,   4 },
2319     { ISD::SETCC,   MVT::v8i32,   4 },
2320     { ISD::SETCC,   MVT::v16i16,  4 },
2321     { ISD::SETCC,   MVT::v32i8,   4 },
2322 
2323     { ISD::SELECT,  MVT::v4f64,   1 }, // vblendvpd
2324     { ISD::SELECT,  MVT::v8f32,   1 }, // vblendvps
2325     { ISD::SELECT,  MVT::v4i64,   1 }, // vblendvpd
2326     { ISD::SELECT,  MVT::v8i32,   1 }, // vblendvps
2327     { ISD::SELECT,  MVT::v16i16,  3 }, // vandps + vandnps + vorps
2328     { ISD::SELECT,  MVT::v32i8,   3 }, // vandps + vandnps + vorps
2329   };
2330 
2331   static const CostTblEntry SSE42CostTbl[] = {
2332     { ISD::SETCC,   MVT::v2f64,   1 },
2333     { ISD::SETCC,   MVT::v4f32,   1 },
2334     { ISD::SETCC,   MVT::v2i64,   1 },
2335   };
2336 
2337   static const CostTblEntry SSE41CostTbl[] = {
2338     { ISD::SELECT,  MVT::v2f64,   1 }, // blendvpd
2339     { ISD::SELECT,  MVT::v4f32,   1 }, // blendvps
2340     { ISD::SELECT,  MVT::v2i64,   1 }, // pblendvb
2341     { ISD::SELECT,  MVT::v4i32,   1 }, // pblendvb
2342     { ISD::SELECT,  MVT::v8i16,   1 }, // pblendvb
2343     { ISD::SELECT,  MVT::v16i8,   1 }, // pblendvb
2344   };
2345 
2346   static const CostTblEntry SSE2CostTbl[] = {
2347     { ISD::SETCC,   MVT::v2f64,   2 },
2348     { ISD::SETCC,   MVT::f64,     1 },
2349     { ISD::SETCC,   MVT::v2i64,   8 },
2350     { ISD::SETCC,   MVT::v4i32,   1 },
2351     { ISD::SETCC,   MVT::v8i16,   1 },
2352     { ISD::SETCC,   MVT::v16i8,   1 },
2353 
2354     { ISD::SELECT,  MVT::v2f64,   3 }, // andpd + andnpd + orpd
2355     { ISD::SELECT,  MVT::v2i64,   3 }, // pand + pandn + por
2356     { ISD::SELECT,  MVT::v4i32,   3 }, // pand + pandn + por
2357     { ISD::SELECT,  MVT::v8i16,   3 }, // pand + pandn + por
2358     { ISD::SELECT,  MVT::v16i8,   3 }, // pand + pandn + por
2359   };
2360 
2361   static const CostTblEntry SSE1CostTbl[] = {
2362     { ISD::SETCC,   MVT::v4f32,   2 },
2363     { ISD::SETCC,   MVT::f32,     1 },
2364 
2365     { ISD::SELECT,  MVT::v4f32,   3 }, // andps + andnps + orps
2366   };
2367 
2368   if (ST->isSLM())
2369     if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy))
2370       return LT.first * (ExtraCost + Entry->Cost);
2371 
2372   if (ST->hasBWI())
2373     if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
2374       return LT.first * (ExtraCost + Entry->Cost);
2375 
2376   if (ST->hasAVX512())
2377     if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy))
2378       return LT.first * (ExtraCost + Entry->Cost);
2379 
2380   if (ST->hasAVX2())
2381     if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy))
2382       return LT.first * (ExtraCost + Entry->Cost);
2383 
2384   if (ST->hasAVX())
2385     if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
2386       return LT.first * (ExtraCost + Entry->Cost);
2387 
2388   if (ST->hasSSE42())
2389     if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy))
2390       return LT.first * (ExtraCost + Entry->Cost);
2391 
2392   if (ST->hasSSE41())
2393     if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy))
2394       return LT.first * (ExtraCost + Entry->Cost);
2395 
2396   if (ST->hasSSE2())
2397     if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
2398       return LT.first * (ExtraCost + Entry->Cost);
2399 
2400   if (ST->hasSSE1())
2401     if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy))
2402       return LT.first * (ExtraCost + Entry->Cost);
2403 
2404   return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I);
2405 }
2406 
2407 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; }
2408 
2409 InstructionCost
2410 X86TTIImpl::getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
2411                                            TTI::TargetCostKind CostKind) {
2412 
2413   // Costs should match the codegen from:
2414   // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll
2415   // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll
2416   // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll
2417   // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll
2418   // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll
2419 
2420   // TODO: Overflow intrinsics (*ADDO, *SUBO, *MULO) with vector types are not
2421   //       specialized in these tables yet.
2422   static const CostTblEntry AVX512CDCostTbl[] = {
2423     { ISD::CTLZ,       MVT::v8i64,   1 },
2424     { ISD::CTLZ,       MVT::v16i32,  1 },
2425     { ISD::CTLZ,       MVT::v32i16,  8 },
2426     { ISD::CTLZ,       MVT::v64i8,  20 },
2427     { ISD::CTLZ,       MVT::v4i64,   1 },
2428     { ISD::CTLZ,       MVT::v8i32,   1 },
2429     { ISD::CTLZ,       MVT::v16i16,  4 },
2430     { ISD::CTLZ,       MVT::v32i8,  10 },
2431     { ISD::CTLZ,       MVT::v2i64,   1 },
2432     { ISD::CTLZ,       MVT::v4i32,   1 },
2433     { ISD::CTLZ,       MVT::v8i16,   4 },
2434     { ISD::CTLZ,       MVT::v16i8,   4 },
2435   };
2436   static const CostTblEntry AVX512BWCostTbl[] = {
2437     { ISD::ABS,        MVT::v32i16,  1 },
2438     { ISD::ABS,        MVT::v64i8,   1 },
2439     { ISD::BITREVERSE, MVT::v8i64,   5 },
2440     { ISD::BITREVERSE, MVT::v16i32,  5 },
2441     { ISD::BITREVERSE, MVT::v32i16,  5 },
2442     { ISD::BITREVERSE, MVT::v64i8,   5 },
2443     { ISD::CTLZ,       MVT::v8i64,  23 },
2444     { ISD::CTLZ,       MVT::v16i32, 22 },
2445     { ISD::CTLZ,       MVT::v32i16, 18 },
2446     { ISD::CTLZ,       MVT::v64i8,  17 },
2447     { ISD::CTPOP,      MVT::v8i64,   7 },
2448     { ISD::CTPOP,      MVT::v16i32, 11 },
2449     { ISD::CTPOP,      MVT::v32i16,  9 },
2450     { ISD::CTPOP,      MVT::v64i8,   6 },
2451     { ISD::CTTZ,       MVT::v8i64,  10 },
2452     { ISD::CTTZ,       MVT::v16i32, 14 },
2453     { ISD::CTTZ,       MVT::v32i16, 12 },
2454     { ISD::CTTZ,       MVT::v64i8,   9 },
2455     { ISD::SADDSAT,    MVT::v32i16,  1 },
2456     { ISD::SADDSAT,    MVT::v64i8,   1 },
2457     { ISD::SMAX,       MVT::v32i16,  1 },
2458     { ISD::SMAX,       MVT::v64i8,   1 },
2459     { ISD::SMIN,       MVT::v32i16,  1 },
2460     { ISD::SMIN,       MVT::v64i8,   1 },
2461     { ISD::SSUBSAT,    MVT::v32i16,  1 },
2462     { ISD::SSUBSAT,    MVT::v64i8,   1 },
2463     { ISD::UADDSAT,    MVT::v32i16,  1 },
2464     { ISD::UADDSAT,    MVT::v64i8,   1 },
2465     { ISD::UMAX,       MVT::v32i16,  1 },
2466     { ISD::UMAX,       MVT::v64i8,   1 },
2467     { ISD::UMIN,       MVT::v32i16,  1 },
2468     { ISD::UMIN,       MVT::v64i8,   1 },
2469     { ISD::USUBSAT,    MVT::v32i16,  1 },
2470     { ISD::USUBSAT,    MVT::v64i8,   1 },
2471   };
2472   static const CostTblEntry AVX512CostTbl[] = {
2473     { ISD::ABS,        MVT::v8i64,   1 },
2474     { ISD::ABS,        MVT::v16i32,  1 },
2475     { ISD::ABS,        MVT::v32i16,  2 }, // FIXME: include split
2476     { ISD::ABS,        MVT::v64i8,   2 }, // FIXME: include split
2477     { ISD::ABS,        MVT::v4i64,   1 },
2478     { ISD::ABS,        MVT::v2i64,   1 },
2479     { ISD::BITREVERSE, MVT::v8i64,  36 },
2480     { ISD::BITREVERSE, MVT::v16i32, 24 },
2481     { ISD::BITREVERSE, MVT::v32i16, 10 },
2482     { ISD::BITREVERSE, MVT::v64i8,  10 },
2483     { ISD::CTLZ,       MVT::v8i64,  29 },
2484     { ISD::CTLZ,       MVT::v16i32, 35 },
2485     { ISD::CTLZ,       MVT::v32i16, 28 },
2486     { ISD::CTLZ,       MVT::v64i8,  18 },
2487     { ISD::CTPOP,      MVT::v8i64,  16 },
2488     { ISD::CTPOP,      MVT::v16i32, 24 },
2489     { ISD::CTPOP,      MVT::v32i16, 18 },
2490     { ISD::CTPOP,      MVT::v64i8,  12 },
2491     { ISD::CTTZ,       MVT::v8i64,  20 },
2492     { ISD::CTTZ,       MVT::v16i32, 28 },
2493     { ISD::CTTZ,       MVT::v32i16, 24 },
2494     { ISD::CTTZ,       MVT::v64i8,  18 },
2495     { ISD::SMAX,       MVT::v8i64,   1 },
2496     { ISD::SMAX,       MVT::v16i32,  1 },
2497     { ISD::SMAX,       MVT::v32i16,  2 }, // FIXME: include split
2498     { ISD::SMAX,       MVT::v64i8,   2 }, // FIXME: include split
2499     { ISD::SMAX,       MVT::v4i64,   1 },
2500     { ISD::SMAX,       MVT::v2i64,   1 },
2501     { ISD::SMIN,       MVT::v8i64,   1 },
2502     { ISD::SMIN,       MVT::v16i32,  1 },
2503     { ISD::SMIN,       MVT::v32i16,  2 }, // FIXME: include split
2504     { ISD::SMIN,       MVT::v64i8,   2 }, // FIXME: include split
2505     { ISD::SMIN,       MVT::v4i64,   1 },
2506     { ISD::SMIN,       MVT::v2i64,   1 },
2507     { ISD::UMAX,       MVT::v8i64,   1 },
2508     { ISD::UMAX,       MVT::v16i32,  1 },
2509     { ISD::UMAX,       MVT::v32i16,  2 }, // FIXME: include split
2510     { ISD::UMAX,       MVT::v64i8,   2 }, // FIXME: include split
2511     { ISD::UMAX,       MVT::v4i64,   1 },
2512     { ISD::UMAX,       MVT::v2i64,   1 },
2513     { ISD::UMIN,       MVT::v8i64,   1 },
2514     { ISD::UMIN,       MVT::v16i32,  1 },
2515     { ISD::UMIN,       MVT::v32i16,  2 }, // FIXME: include split
2516     { ISD::UMIN,       MVT::v64i8,   2 }, // FIXME: include split
2517     { ISD::UMIN,       MVT::v4i64,   1 },
2518     { ISD::UMIN,       MVT::v2i64,   1 },
2519     { ISD::USUBSAT,    MVT::v16i32,  2 }, // pmaxud + psubd
2520     { ISD::USUBSAT,    MVT::v2i64,   2 }, // pmaxuq + psubq
2521     { ISD::USUBSAT,    MVT::v4i64,   2 }, // pmaxuq + psubq
2522     { ISD::USUBSAT,    MVT::v8i64,   2 }, // pmaxuq + psubq
2523     { ISD::UADDSAT,    MVT::v16i32,  3 }, // not + pminud + paddd
2524     { ISD::UADDSAT,    MVT::v2i64,   3 }, // not + pminuq + paddq
2525     { ISD::UADDSAT,    MVT::v4i64,   3 }, // not + pminuq + paddq
2526     { ISD::UADDSAT,    MVT::v8i64,   3 }, // not + pminuq + paddq
2527     { ISD::SADDSAT,    MVT::v32i16,  2 }, // FIXME: include split
2528     { ISD::SADDSAT,    MVT::v64i8,   2 }, // FIXME: include split
2529     { ISD::SSUBSAT,    MVT::v32i16,  2 }, // FIXME: include split
2530     { ISD::SSUBSAT,    MVT::v64i8,   2 }, // FIXME: include split
2531     { ISD::UADDSAT,    MVT::v32i16,  2 }, // FIXME: include split
2532     { ISD::UADDSAT,    MVT::v64i8,   2 }, // FIXME: include split
2533     { ISD::USUBSAT,    MVT::v32i16,  2 }, // FIXME: include split
2534     { ISD::USUBSAT,    MVT::v64i8,   2 }, // FIXME: include split
2535     { ISD::FMAXNUM,    MVT::f32,     2 },
2536     { ISD::FMAXNUM,    MVT::v4f32,   2 },
2537     { ISD::FMAXNUM,    MVT::v8f32,   2 },
2538     { ISD::FMAXNUM,    MVT::v16f32,  2 },
2539     { ISD::FMAXNUM,    MVT::f64,     2 },
2540     { ISD::FMAXNUM,    MVT::v2f64,   2 },
2541     { ISD::FMAXNUM,    MVT::v4f64,   2 },
2542     { ISD::FMAXNUM,    MVT::v8f64,   2 },
2543   };
2544   static const CostTblEntry XOPCostTbl[] = {
2545     { ISD::BITREVERSE, MVT::v4i64,   4 },
2546     { ISD::BITREVERSE, MVT::v8i32,   4 },
2547     { ISD::BITREVERSE, MVT::v16i16,  4 },
2548     { ISD::BITREVERSE, MVT::v32i8,   4 },
2549     { ISD::BITREVERSE, MVT::v2i64,   1 },
2550     { ISD::BITREVERSE, MVT::v4i32,   1 },
2551     { ISD::BITREVERSE, MVT::v8i16,   1 },
2552     { ISD::BITREVERSE, MVT::v16i8,   1 },
2553     { ISD::BITREVERSE, MVT::i64,     3 },
2554     { ISD::BITREVERSE, MVT::i32,     3 },
2555     { ISD::BITREVERSE, MVT::i16,     3 },
2556     { ISD::BITREVERSE, MVT::i8,      3 }
2557   };
2558   static const CostTblEntry AVX2CostTbl[] = {
2559     { ISD::ABS,        MVT::v4i64,   2 }, // VBLENDVPD(X,VPSUBQ(0,X),X)
2560     { ISD::ABS,        MVT::v8i32,   1 },
2561     { ISD::ABS,        MVT::v16i16,  1 },
2562     { ISD::ABS,        MVT::v32i8,   1 },
2563     { ISD::BITREVERSE, MVT::v4i64,   5 },
2564     { ISD::BITREVERSE, MVT::v8i32,   5 },
2565     { ISD::BITREVERSE, MVT::v16i16,  5 },
2566     { ISD::BITREVERSE, MVT::v32i8,   5 },
2567     { ISD::BSWAP,      MVT::v4i64,   1 },
2568     { ISD::BSWAP,      MVT::v8i32,   1 },
2569     { ISD::BSWAP,      MVT::v16i16,  1 },
2570     { ISD::CTLZ,       MVT::v4i64,  23 },
2571     { ISD::CTLZ,       MVT::v8i32,  18 },
2572     { ISD::CTLZ,       MVT::v16i16, 14 },
2573     { ISD::CTLZ,       MVT::v32i8,   9 },
2574     { ISD::CTPOP,      MVT::v4i64,   7 },
2575     { ISD::CTPOP,      MVT::v8i32,  11 },
2576     { ISD::CTPOP,      MVT::v16i16,  9 },
2577     { ISD::CTPOP,      MVT::v32i8,   6 },
2578     { ISD::CTTZ,       MVT::v4i64,  10 },
2579     { ISD::CTTZ,       MVT::v8i32,  14 },
2580     { ISD::CTTZ,       MVT::v16i16, 12 },
2581     { ISD::CTTZ,       MVT::v32i8,   9 },
2582     { ISD::SADDSAT,    MVT::v16i16,  1 },
2583     { ISD::SADDSAT,    MVT::v32i8,   1 },
2584     { ISD::SMAX,       MVT::v8i32,   1 },
2585     { ISD::SMAX,       MVT::v16i16,  1 },
2586     { ISD::SMAX,       MVT::v32i8,   1 },
2587     { ISD::SMIN,       MVT::v8i32,   1 },
2588     { ISD::SMIN,       MVT::v16i16,  1 },
2589     { ISD::SMIN,       MVT::v32i8,   1 },
2590     { ISD::SSUBSAT,    MVT::v16i16,  1 },
2591     { ISD::SSUBSAT,    MVT::v32i8,   1 },
2592     { ISD::UADDSAT,    MVT::v16i16,  1 },
2593     { ISD::UADDSAT,    MVT::v32i8,   1 },
2594     { ISD::UADDSAT,    MVT::v8i32,   3 }, // not + pminud + paddd
2595     { ISD::UMAX,       MVT::v8i32,   1 },
2596     { ISD::UMAX,       MVT::v16i16,  1 },
2597     { ISD::UMAX,       MVT::v32i8,   1 },
2598     { ISD::UMIN,       MVT::v8i32,   1 },
2599     { ISD::UMIN,       MVT::v16i16,  1 },
2600     { ISD::UMIN,       MVT::v32i8,   1 },
2601     { ISD::USUBSAT,    MVT::v16i16,  1 },
2602     { ISD::USUBSAT,    MVT::v32i8,   1 },
2603     { ISD::USUBSAT,    MVT::v8i32,   2 }, // pmaxud + psubd
2604     { ISD::FMAXNUM,    MVT::v8f32,   3 }, // MAXPS + CMPUNORDPS + BLENDVPS
2605     { ISD::FMAXNUM,    MVT::v4f64,   3 }, // MAXPD + CMPUNORDPD + BLENDVPD
2606     { ISD::FSQRT,      MVT::f32,     7 }, // Haswell from http://www.agner.org/
2607     { ISD::FSQRT,      MVT::v4f32,   7 }, // Haswell from http://www.agner.org/
2608     { ISD::FSQRT,      MVT::v8f32,  14 }, // Haswell from http://www.agner.org/
2609     { ISD::FSQRT,      MVT::f64,    14 }, // Haswell from http://www.agner.org/
2610     { ISD::FSQRT,      MVT::v2f64,  14 }, // Haswell from http://www.agner.org/
2611     { ISD::FSQRT,      MVT::v4f64,  28 }, // Haswell from http://www.agner.org/
2612   };
2613   static const CostTblEntry AVX1CostTbl[] = {
2614     { ISD::ABS,        MVT::v4i64,   5 }, // VBLENDVPD(X,VPSUBQ(0,X),X)
2615     { ISD::ABS,        MVT::v8i32,   3 },
2616     { ISD::ABS,        MVT::v16i16,  3 },
2617     { ISD::ABS,        MVT::v32i8,   3 },
2618     { ISD::BITREVERSE, MVT::v4i64,  12 }, // 2 x 128-bit Op + extract/insert
2619     { ISD::BITREVERSE, MVT::v8i32,  12 }, // 2 x 128-bit Op + extract/insert
2620     { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert
2621     { ISD::BITREVERSE, MVT::v32i8,  12 }, // 2 x 128-bit Op + extract/insert
2622     { ISD::BSWAP,      MVT::v4i64,   4 },
2623     { ISD::BSWAP,      MVT::v8i32,   4 },
2624     { ISD::BSWAP,      MVT::v16i16,  4 },
2625     { ISD::CTLZ,       MVT::v4i64,  48 }, // 2 x 128-bit Op + extract/insert
2626     { ISD::CTLZ,       MVT::v8i32,  38 }, // 2 x 128-bit Op + extract/insert
2627     { ISD::CTLZ,       MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert
2628     { ISD::CTLZ,       MVT::v32i8,  20 }, // 2 x 128-bit Op + extract/insert
2629     { ISD::CTPOP,      MVT::v4i64,  16 }, // 2 x 128-bit Op + extract/insert
2630     { ISD::CTPOP,      MVT::v8i32,  24 }, // 2 x 128-bit Op + extract/insert
2631     { ISD::CTPOP,      MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert
2632     { ISD::CTPOP,      MVT::v32i8,  14 }, // 2 x 128-bit Op + extract/insert
2633     { ISD::CTTZ,       MVT::v4i64,  22 }, // 2 x 128-bit Op + extract/insert
2634     { ISD::CTTZ,       MVT::v8i32,  30 }, // 2 x 128-bit Op + extract/insert
2635     { ISD::CTTZ,       MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert
2636     { ISD::CTTZ,       MVT::v32i8,  20 }, // 2 x 128-bit Op + extract/insert
2637     { ISD::SADDSAT,    MVT::v16i16,  4 }, // 2 x 128-bit Op + extract/insert
2638     { ISD::SADDSAT,    MVT::v32i8,   4 }, // 2 x 128-bit Op + extract/insert
2639     { ISD::SMAX,       MVT::v8i32,   4 }, // 2 x 128-bit Op + extract/insert
2640     { ISD::SMAX,       MVT::v16i16,  4 }, // 2 x 128-bit Op + extract/insert
2641     { ISD::SMAX,       MVT::v32i8,   4 }, // 2 x 128-bit Op + extract/insert
2642     { ISD::SMIN,       MVT::v8i32,   4 }, // 2 x 128-bit Op + extract/insert
2643     { ISD::SMIN,       MVT::v16i16,  4 }, // 2 x 128-bit Op + extract/insert
2644     { ISD::SMIN,       MVT::v32i8,   4 }, // 2 x 128-bit Op + extract/insert
2645     { ISD::SSUBSAT,    MVT::v16i16,  4 }, // 2 x 128-bit Op + extract/insert
2646     { ISD::SSUBSAT,    MVT::v32i8,   4 }, // 2 x 128-bit Op + extract/insert
2647     { ISD::UADDSAT,    MVT::v16i16,  4 }, // 2 x 128-bit Op + extract/insert
2648     { ISD::UADDSAT,    MVT::v32i8,   4 }, // 2 x 128-bit Op + extract/insert
2649     { ISD::UADDSAT,    MVT::v8i32,   8 }, // 2 x 128-bit Op + extract/insert
2650     { ISD::UMAX,       MVT::v8i32,   4 }, // 2 x 128-bit Op + extract/insert
2651     { ISD::UMAX,       MVT::v16i16,  4 }, // 2 x 128-bit Op + extract/insert
2652     { ISD::UMAX,       MVT::v32i8,   4 }, // 2 x 128-bit Op + extract/insert
2653     { ISD::UMIN,       MVT::v8i32,   4 }, // 2 x 128-bit Op + extract/insert
2654     { ISD::UMIN,       MVT::v16i16,  4 }, // 2 x 128-bit Op + extract/insert
2655     { ISD::UMIN,       MVT::v32i8,   4 }, // 2 x 128-bit Op + extract/insert
2656     { ISD::USUBSAT,    MVT::v16i16,  4 }, // 2 x 128-bit Op + extract/insert
2657     { ISD::USUBSAT,    MVT::v32i8,   4 }, // 2 x 128-bit Op + extract/insert
2658     { ISD::USUBSAT,    MVT::v8i32,   6 }, // 2 x 128-bit Op + extract/insert
2659     { ISD::FMAXNUM,    MVT::f32,     3 }, // MAXSS + CMPUNORDSS + BLENDVPS
2660     { ISD::FMAXNUM,    MVT::v4f32,   3 }, // MAXPS + CMPUNORDPS + BLENDVPS
2661     { ISD::FMAXNUM,    MVT::v8f32,   5 }, // MAXPS + CMPUNORDPS + BLENDVPS + ?
2662     { ISD::FMAXNUM,    MVT::f64,     3 }, // MAXSD + CMPUNORDSD + BLENDVPD
2663     { ISD::FMAXNUM,    MVT::v2f64,   3 }, // MAXPD + CMPUNORDPD + BLENDVPD
2664     { ISD::FMAXNUM,    MVT::v4f64,   5 }, // MAXPD + CMPUNORDPD + BLENDVPD + ?
2665     { ISD::FSQRT,      MVT::f32,    14 }, // SNB from http://www.agner.org/
2666     { ISD::FSQRT,      MVT::v4f32,  14 }, // SNB from http://www.agner.org/
2667     { ISD::FSQRT,      MVT::v8f32,  28 }, // SNB from http://www.agner.org/
2668     { ISD::FSQRT,      MVT::f64,    21 }, // SNB from http://www.agner.org/
2669     { ISD::FSQRT,      MVT::v2f64,  21 }, // SNB from http://www.agner.org/
2670     { ISD::FSQRT,      MVT::v4f64,  43 }, // SNB from http://www.agner.org/
2671   };
2672   static const CostTblEntry GLMCostTbl[] = {
2673     { ISD::FSQRT, MVT::f32,   19 }, // sqrtss
2674     { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps
2675     { ISD::FSQRT, MVT::f64,   34 }, // sqrtsd
2676     { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd
2677   };
2678   static const CostTblEntry SLMCostTbl[] = {
2679     { ISD::FSQRT, MVT::f32,   20 }, // sqrtss
2680     { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps
2681     { ISD::FSQRT, MVT::f64,   35 }, // sqrtsd
2682     { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd
2683   };
2684   static const CostTblEntry SSE42CostTbl[] = {
2685     { ISD::USUBSAT,    MVT::v4i32,   2 }, // pmaxud + psubd
2686     { ISD::UADDSAT,    MVT::v4i32,   3 }, // not + pminud + paddd
2687     { ISD::FSQRT,      MVT::f32,    18 }, // Nehalem from http://www.agner.org/
2688     { ISD::FSQRT,      MVT::v4f32,  18 }, // Nehalem from http://www.agner.org/
2689   };
2690   static const CostTblEntry SSE41CostTbl[] = {
2691     { ISD::ABS,        MVT::v2i64,   2 }, // BLENDVPD(X,PSUBQ(0,X),X)
2692     { ISD::SMAX,       MVT::v4i32,   1 },
2693     { ISD::SMAX,       MVT::v16i8,   1 },
2694     { ISD::SMIN,       MVT::v4i32,   1 },
2695     { ISD::SMIN,       MVT::v16i8,   1 },
2696     { ISD::UMAX,       MVT::v4i32,   1 },
2697     { ISD::UMAX,       MVT::v8i16,   1 },
2698     { ISD::UMIN,       MVT::v4i32,   1 },
2699     { ISD::UMIN,       MVT::v8i16,   1 },
2700   };
2701   static const CostTblEntry SSSE3CostTbl[] = {
2702     { ISD::ABS,        MVT::v4i32,   1 },
2703     { ISD::ABS,        MVT::v8i16,   1 },
2704     { ISD::ABS,        MVT::v16i8,   1 },
2705     { ISD::BITREVERSE, MVT::v2i64,   5 },
2706     { ISD::BITREVERSE, MVT::v4i32,   5 },
2707     { ISD::BITREVERSE, MVT::v8i16,   5 },
2708     { ISD::BITREVERSE, MVT::v16i8,   5 },
2709     { ISD::BSWAP,      MVT::v2i64,   1 },
2710     { ISD::BSWAP,      MVT::v4i32,   1 },
2711     { ISD::BSWAP,      MVT::v8i16,   1 },
2712     { ISD::CTLZ,       MVT::v2i64,  23 },
2713     { ISD::CTLZ,       MVT::v4i32,  18 },
2714     { ISD::CTLZ,       MVT::v8i16,  14 },
2715     { ISD::CTLZ,       MVT::v16i8,   9 },
2716     { ISD::CTPOP,      MVT::v2i64,   7 },
2717     { ISD::CTPOP,      MVT::v4i32,  11 },
2718     { ISD::CTPOP,      MVT::v8i16,   9 },
2719     { ISD::CTPOP,      MVT::v16i8,   6 },
2720     { ISD::CTTZ,       MVT::v2i64,  10 },
2721     { ISD::CTTZ,       MVT::v4i32,  14 },
2722     { ISD::CTTZ,       MVT::v8i16,  12 },
2723     { ISD::CTTZ,       MVT::v16i8,   9 }
2724   };
2725   static const CostTblEntry SSE2CostTbl[] = {
2726     { ISD::ABS,        MVT::v2i64,   4 },
2727     { ISD::ABS,        MVT::v4i32,   3 },
2728     { ISD::ABS,        MVT::v8i16,   2 },
2729     { ISD::ABS,        MVT::v16i8,   2 },
2730     { ISD::BITREVERSE, MVT::v2i64,  29 },
2731     { ISD::BITREVERSE, MVT::v4i32,  27 },
2732     { ISD::BITREVERSE, MVT::v8i16,  27 },
2733     { ISD::BITREVERSE, MVT::v16i8,  20 },
2734     { ISD::BSWAP,      MVT::v2i64,   7 },
2735     { ISD::BSWAP,      MVT::v4i32,   7 },
2736     { ISD::BSWAP,      MVT::v8i16,   7 },
2737     { ISD::CTLZ,       MVT::v2i64,  25 },
2738     { ISD::CTLZ,       MVT::v4i32,  26 },
2739     { ISD::CTLZ,       MVT::v8i16,  20 },
2740     { ISD::CTLZ,       MVT::v16i8,  17 },
2741     { ISD::CTPOP,      MVT::v2i64,  12 },
2742     { ISD::CTPOP,      MVT::v4i32,  15 },
2743     { ISD::CTPOP,      MVT::v8i16,  13 },
2744     { ISD::CTPOP,      MVT::v16i8,  10 },
2745     { ISD::CTTZ,       MVT::v2i64,  14 },
2746     { ISD::CTTZ,       MVT::v4i32,  18 },
2747     { ISD::CTTZ,       MVT::v8i16,  16 },
2748     { ISD::CTTZ,       MVT::v16i8,  13 },
2749     { ISD::SADDSAT,    MVT::v8i16,   1 },
2750     { ISD::SADDSAT,    MVT::v16i8,   1 },
2751     { ISD::SMAX,       MVT::v8i16,   1 },
2752     { ISD::SMIN,       MVT::v8i16,   1 },
2753     { ISD::SSUBSAT,    MVT::v8i16,   1 },
2754     { ISD::SSUBSAT,    MVT::v16i8,   1 },
2755     { ISD::UADDSAT,    MVT::v8i16,   1 },
2756     { ISD::UADDSAT,    MVT::v16i8,   1 },
2757     { ISD::UMAX,       MVT::v8i16,   2 },
2758     { ISD::UMAX,       MVT::v16i8,   1 },
2759     { ISD::UMIN,       MVT::v8i16,   2 },
2760     { ISD::UMIN,       MVT::v16i8,   1 },
2761     { ISD::USUBSAT,    MVT::v8i16,   1 },
2762     { ISD::USUBSAT,    MVT::v16i8,   1 },
2763     { ISD::FMAXNUM,    MVT::f64,     4 },
2764     { ISD::FMAXNUM,    MVT::v2f64,   4 },
2765     { ISD::FSQRT,      MVT::f64,    32 }, // Nehalem from http://www.agner.org/
2766     { ISD::FSQRT,      MVT::v2f64,  32 }, // Nehalem from http://www.agner.org/
2767   };
2768   static const CostTblEntry SSE1CostTbl[] = {
2769     { ISD::FMAXNUM,    MVT::f32,     4 },
2770     { ISD::FMAXNUM,    MVT::v4f32,   4 },
2771     { ISD::FSQRT,      MVT::f32,    28 }, // Pentium III from http://www.agner.org/
2772     { ISD::FSQRT,      MVT::v4f32,  56 }, // Pentium III from http://www.agner.org/
2773   };
2774   static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets
2775     { ISD::CTTZ,       MVT::i64,     1 },
2776   };
2777   static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets
2778     { ISD::CTTZ,       MVT::i32,     1 },
2779     { ISD::CTTZ,       MVT::i16,     1 },
2780     { ISD::CTTZ,       MVT::i8,      1 },
2781   };
2782   static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets
2783     { ISD::CTLZ,       MVT::i64,     1 },
2784   };
2785   static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets
2786     { ISD::CTLZ,       MVT::i32,     1 },
2787     { ISD::CTLZ,       MVT::i16,     1 },
2788     { ISD::CTLZ,       MVT::i8,      1 },
2789   };
2790   static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets
2791     { ISD::CTPOP,      MVT::i64,     1 },
2792   };
2793   static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets
2794     { ISD::CTPOP,      MVT::i32,     1 },
2795     { ISD::CTPOP,      MVT::i16,     1 },
2796     { ISD::CTPOP,      MVT::i8,      1 },
2797   };
2798   static const CostTblEntry X64CostTbl[] = { // 64-bit targets
2799     { ISD::ABS,        MVT::i64,     2 }, // SUB+CMOV
2800     { ISD::BITREVERSE, MVT::i64,    14 },
2801     { ISD::BSWAP,      MVT::i64,     1 },
2802     { ISD::CTLZ,       MVT::i64,     4 }, // BSR+XOR or BSR+XOR+CMOV
2803     { ISD::CTTZ,       MVT::i64,     3 }, // TEST+BSF+CMOV/BRANCH
2804     { ISD::CTPOP,      MVT::i64,    10 },
2805     { ISD::SADDO,      MVT::i64,     1 },
2806     { ISD::UADDO,      MVT::i64,     1 },
2807     { ISD::UMULO,      MVT::i64,     2 }, // mulq + seto
2808   };
2809   static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets
2810     { ISD::ABS,        MVT::i32,     2 }, // SUB+CMOV
2811     { ISD::ABS,        MVT::i16,     2 }, // SUB+CMOV
2812     { ISD::BITREVERSE, MVT::i32,    14 },
2813     { ISD::BITREVERSE, MVT::i16,    14 },
2814     { ISD::BITREVERSE, MVT::i8,     11 },
2815     { ISD::BSWAP,      MVT::i32,     1 },
2816     { ISD::BSWAP,      MVT::i16,     1 }, // ROL
2817     { ISD::CTLZ,       MVT::i32,     4 }, // BSR+XOR or BSR+XOR+CMOV
2818     { ISD::CTLZ,       MVT::i16,     4 }, // BSR+XOR or BSR+XOR+CMOV
2819     { ISD::CTLZ,       MVT::i8,      4 }, // BSR+XOR or BSR+XOR+CMOV
2820     { ISD::CTTZ,       MVT::i32,     3 }, // TEST+BSF+CMOV/BRANCH
2821     { ISD::CTTZ,       MVT::i16,     3 }, // TEST+BSF+CMOV/BRANCH
2822     { ISD::CTTZ,       MVT::i8,      3 }, // TEST+BSF+CMOV/BRANCH
2823     { ISD::CTPOP,      MVT::i32,     8 },
2824     { ISD::CTPOP,      MVT::i16,     9 },
2825     { ISD::CTPOP,      MVT::i8,      7 },
2826     { ISD::SADDO,      MVT::i32,     1 },
2827     { ISD::SADDO,      MVT::i16,     1 },
2828     { ISD::SADDO,      MVT::i8,      1 },
2829     { ISD::UADDO,      MVT::i32,     1 },
2830     { ISD::UADDO,      MVT::i16,     1 },
2831     { ISD::UADDO,      MVT::i8,      1 },
2832     { ISD::UMULO,      MVT::i32,     2 }, // mul + seto
2833     { ISD::UMULO,      MVT::i16,     2 },
2834     { ISD::UMULO,      MVT::i8,      2 },
2835   };
2836 
2837   Type *RetTy = ICA.getReturnType();
2838   Type *OpTy = RetTy;
2839   Intrinsic::ID IID = ICA.getID();
2840   unsigned ISD = ISD::DELETED_NODE;
2841   switch (IID) {
2842   default:
2843     break;
2844   case Intrinsic::abs:
2845     ISD = ISD::ABS;
2846     break;
2847   case Intrinsic::bitreverse:
2848     ISD = ISD::BITREVERSE;
2849     break;
2850   case Intrinsic::bswap:
2851     ISD = ISD::BSWAP;
2852     break;
2853   case Intrinsic::ctlz:
2854     ISD = ISD::CTLZ;
2855     break;
2856   case Intrinsic::ctpop:
2857     ISD = ISD::CTPOP;
2858     break;
2859   case Intrinsic::cttz:
2860     ISD = ISD::CTTZ;
2861     break;
2862   case Intrinsic::maxnum:
2863   case Intrinsic::minnum:
2864     // FMINNUM has same costs so don't duplicate.
2865     ISD = ISD::FMAXNUM;
2866     break;
2867   case Intrinsic::sadd_sat:
2868     ISD = ISD::SADDSAT;
2869     break;
2870   case Intrinsic::smax:
2871     ISD = ISD::SMAX;
2872     break;
2873   case Intrinsic::smin:
2874     ISD = ISD::SMIN;
2875     break;
2876   case Intrinsic::ssub_sat:
2877     ISD = ISD::SSUBSAT;
2878     break;
2879   case Intrinsic::uadd_sat:
2880     ISD = ISD::UADDSAT;
2881     break;
2882   case Intrinsic::umax:
2883     ISD = ISD::UMAX;
2884     break;
2885   case Intrinsic::umin:
2886     ISD = ISD::UMIN;
2887     break;
2888   case Intrinsic::usub_sat:
2889     ISD = ISD::USUBSAT;
2890     break;
2891   case Intrinsic::sqrt:
2892     ISD = ISD::FSQRT;
2893     break;
2894   case Intrinsic::sadd_with_overflow:
2895   case Intrinsic::ssub_with_overflow:
2896     // SSUBO has same costs so don't duplicate.
2897     ISD = ISD::SADDO;
2898     OpTy = RetTy->getContainedType(0);
2899     break;
2900   case Intrinsic::uadd_with_overflow:
2901   case Intrinsic::usub_with_overflow:
2902     // USUBO has same costs so don't duplicate.
2903     ISD = ISD::UADDO;
2904     OpTy = RetTy->getContainedType(0);
2905     break;
2906   case Intrinsic::umul_with_overflow:
2907   case Intrinsic::smul_with_overflow:
2908     // SMULO has same costs so don't duplicate.
2909     ISD = ISD::UMULO;
2910     OpTy = RetTy->getContainedType(0);
2911     break;
2912   }
2913 
2914   if (ISD != ISD::DELETED_NODE) {
2915     // Legalize the type.
2916     std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy);
2917     MVT MTy = LT.second;
2918 
2919     // Attempt to lookup cost.
2920     if (ISD == ISD::BITREVERSE && ST->hasGFNI() && ST->hasSSSE3() &&
2921         MTy.isVector()) {
2922       // With PSHUFB the code is very similar for all types. If we have integer
2923       // byte operations, we just need a GF2P8AFFINEQB for vXi8. For other types
2924       // we also need a PSHUFB.
2925       unsigned Cost = MTy.getVectorElementType() == MVT::i8 ? 1 : 2;
2926 
2927       // Without byte operations, we need twice as many GF2P8AFFINEQB and PSHUFB
2928       // instructions. We also need an extract and an insert.
2929       if (!(MTy.is128BitVector() || (ST->hasAVX2() && MTy.is256BitVector()) ||
2930             (ST->hasBWI() && MTy.is512BitVector())))
2931         Cost = Cost * 2 + 2;
2932 
2933       return LT.first * Cost;
2934     }
2935 
2936     auto adjustTableCost = [](const CostTblEntry &Entry,
2937                               InstructionCost LegalizationCost,
2938                               FastMathFlags FMF) {
2939       // If there are no NANs to deal with, then these are reduced to a
2940       // single MIN** or MAX** instruction instead of the MIN/CMP/SELECT that we
2941       // assume is used in the non-fast case.
2942       if (Entry.ISD == ISD::FMAXNUM || Entry.ISD == ISD::FMINNUM) {
2943         if (FMF.noNaNs())
2944           return LegalizationCost * 1;
2945       }
2946       return LegalizationCost * (int)Entry.Cost;
2947     };
2948 
2949     if (ST->useGLMDivSqrtCosts())
2950       if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy))
2951         return adjustTableCost(*Entry, LT.first, ICA.getFlags());
2952 
2953     if (ST->isSLM())
2954       if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy))
2955         return adjustTableCost(*Entry, LT.first, ICA.getFlags());
2956 
2957     if (ST->hasCDI())
2958       if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy))
2959         return adjustTableCost(*Entry, LT.first, ICA.getFlags());
2960 
2961     if (ST->hasBWI())
2962       if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
2963         return adjustTableCost(*Entry, LT.first, ICA.getFlags());
2964 
2965     if (ST->hasAVX512())
2966       if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy))
2967         return adjustTableCost(*Entry, LT.first, ICA.getFlags());
2968 
2969     if (ST->hasXOP())
2970       if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy))
2971         return adjustTableCost(*Entry, LT.first, ICA.getFlags());
2972 
2973     if (ST->hasAVX2())
2974       if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy))
2975         return adjustTableCost(*Entry, LT.first, ICA.getFlags());
2976 
2977     if (ST->hasAVX())
2978       if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
2979         return adjustTableCost(*Entry, LT.first, ICA.getFlags());
2980 
2981     if (ST->hasSSE42())
2982       if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy))
2983         return adjustTableCost(*Entry, LT.first, ICA.getFlags());
2984 
2985     if (ST->hasSSE41())
2986       if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy))
2987         return adjustTableCost(*Entry, LT.first, ICA.getFlags());
2988 
2989     if (ST->hasSSSE3())
2990       if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy))
2991         return adjustTableCost(*Entry, LT.first, ICA.getFlags());
2992 
2993     if (ST->hasSSE2())
2994       if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
2995         return adjustTableCost(*Entry, LT.first, ICA.getFlags());
2996 
2997     if (ST->hasSSE1())
2998       if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy))
2999         return adjustTableCost(*Entry, LT.first, ICA.getFlags());
3000 
3001     if (ST->hasBMI()) {
3002       if (ST->is64Bit())
3003         if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy))
3004           return adjustTableCost(*Entry, LT.first, ICA.getFlags());
3005 
3006       if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy))
3007         return adjustTableCost(*Entry, LT.first, ICA.getFlags());
3008     }
3009 
3010     if (ST->hasLZCNT()) {
3011       if (ST->is64Bit())
3012         if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy))
3013           return adjustTableCost(*Entry, LT.first, ICA.getFlags());
3014 
3015       if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy))
3016         return adjustTableCost(*Entry, LT.first, ICA.getFlags());
3017     }
3018 
3019     if (ST->hasPOPCNT()) {
3020       if (ST->is64Bit())
3021         if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy))
3022           return adjustTableCost(*Entry, LT.first, ICA.getFlags());
3023 
3024       if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy))
3025         return adjustTableCost(*Entry, LT.first, ICA.getFlags());
3026     }
3027 
3028     if (ISD == ISD::BSWAP && ST->hasMOVBE() && ST->hasFastMOVBE()) {
3029       if (const Instruction *II = ICA.getInst()) {
3030         if (II->hasOneUse() && isa<StoreInst>(II->user_back()))
3031           return TTI::TCC_Free;
3032         if (auto *LI = dyn_cast<LoadInst>(II->getOperand(0))) {
3033           if (LI->hasOneUse())
3034             return TTI::TCC_Free;
3035         }
3036       }
3037     }
3038 
3039     // TODO - add BMI (TZCNT) scalar handling
3040 
3041     if (ST->is64Bit())
3042       if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy))
3043         return adjustTableCost(*Entry, LT.first, ICA.getFlags());
3044 
3045     if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy))
3046       return adjustTableCost(*Entry, LT.first, ICA.getFlags());
3047   }
3048 
3049   return BaseT::getIntrinsicInstrCost(ICA, CostKind);
3050 }
3051 
3052 InstructionCost
3053 X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
3054                                   TTI::TargetCostKind CostKind) {
3055   if (ICA.isTypeBasedOnly())
3056     return getTypeBasedIntrinsicInstrCost(ICA, CostKind);
3057 
3058   static const CostTblEntry AVX512CostTbl[] = {
3059     { ISD::ROTL,       MVT::v8i64,   1 },
3060     { ISD::ROTL,       MVT::v4i64,   1 },
3061     { ISD::ROTL,       MVT::v2i64,   1 },
3062     { ISD::ROTL,       MVT::v16i32,  1 },
3063     { ISD::ROTL,       MVT::v8i32,   1 },
3064     { ISD::ROTL,       MVT::v4i32,   1 },
3065     { ISD::ROTR,       MVT::v8i64,   1 },
3066     { ISD::ROTR,       MVT::v4i64,   1 },
3067     { ISD::ROTR,       MVT::v2i64,   1 },
3068     { ISD::ROTR,       MVT::v16i32,  1 },
3069     { ISD::ROTR,       MVT::v8i32,   1 },
3070     { ISD::ROTR,       MVT::v4i32,   1 }
3071   };
3072   // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y))
3073   static const CostTblEntry XOPCostTbl[] = {
3074     { ISD::ROTL,       MVT::v4i64,   4 },
3075     { ISD::ROTL,       MVT::v8i32,   4 },
3076     { ISD::ROTL,       MVT::v16i16,  4 },
3077     { ISD::ROTL,       MVT::v32i8,   4 },
3078     { ISD::ROTL,       MVT::v2i64,   1 },
3079     { ISD::ROTL,       MVT::v4i32,   1 },
3080     { ISD::ROTL,       MVT::v8i16,   1 },
3081     { ISD::ROTL,       MVT::v16i8,   1 },
3082     { ISD::ROTR,       MVT::v4i64,   6 },
3083     { ISD::ROTR,       MVT::v8i32,   6 },
3084     { ISD::ROTR,       MVT::v16i16,  6 },
3085     { ISD::ROTR,       MVT::v32i8,   6 },
3086     { ISD::ROTR,       MVT::v2i64,   2 },
3087     { ISD::ROTR,       MVT::v4i32,   2 },
3088     { ISD::ROTR,       MVT::v8i16,   2 },
3089     { ISD::ROTR,       MVT::v16i8,   2 }
3090   };
3091   static const CostTblEntry X64CostTbl[] = { // 64-bit targets
3092     { ISD::ROTL,       MVT::i64,     1 },
3093     { ISD::ROTR,       MVT::i64,     1 },
3094     { ISD::FSHL,       MVT::i64,     4 }
3095   };
3096   static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets
3097     { ISD::ROTL,       MVT::i32,     1 },
3098     { ISD::ROTL,       MVT::i16,     1 },
3099     { ISD::ROTL,       MVT::i8,      1 },
3100     { ISD::ROTR,       MVT::i32,     1 },
3101     { ISD::ROTR,       MVT::i16,     1 },
3102     { ISD::ROTR,       MVT::i8,      1 },
3103     { ISD::FSHL,       MVT::i32,     4 },
3104     { ISD::FSHL,       MVT::i16,     4 },
3105     { ISD::FSHL,       MVT::i8,      4 }
3106   };
3107 
3108   Intrinsic::ID IID = ICA.getID();
3109   Type *RetTy = ICA.getReturnType();
3110   const SmallVectorImpl<const Value *> &Args = ICA.getArgs();
3111   unsigned ISD = ISD::DELETED_NODE;
3112   switch (IID) {
3113   default:
3114     break;
3115   case Intrinsic::fshl:
3116     ISD = ISD::FSHL;
3117     if (Args[0] == Args[1])
3118       ISD = ISD::ROTL;
3119     break;
3120   case Intrinsic::fshr:
3121     // FSHR has same costs so don't duplicate.
3122     ISD = ISD::FSHL;
3123     if (Args[0] == Args[1])
3124       ISD = ISD::ROTR;
3125     break;
3126   }
3127 
3128   if (ISD != ISD::DELETED_NODE) {
3129     // Legalize the type.
3130     std::pair<InstructionCost, MVT> LT =
3131         TLI->getTypeLegalizationCost(DL, RetTy);
3132     MVT MTy = LT.second;
3133 
3134     // Attempt to lookup cost.
3135     if (ST->hasAVX512())
3136       if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy))
3137         return LT.first * Entry->Cost;
3138 
3139     if (ST->hasXOP())
3140       if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy))
3141         return LT.first * Entry->Cost;
3142 
3143     if (ST->is64Bit())
3144       if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy))
3145         return LT.first * Entry->Cost;
3146 
3147     if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy))
3148       return LT.first * Entry->Cost;
3149   }
3150 
3151   return BaseT::getIntrinsicInstrCost(ICA, CostKind);
3152 }
3153 
3154 InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
3155                                                unsigned Index) {
3156   static const CostTblEntry SLMCostTbl[] = {
3157      { ISD::EXTRACT_VECTOR_ELT,       MVT::i8,      4 },
3158      { ISD::EXTRACT_VECTOR_ELT,       MVT::i16,     4 },
3159      { ISD::EXTRACT_VECTOR_ELT,       MVT::i32,     4 },
3160      { ISD::EXTRACT_VECTOR_ELT,       MVT::i64,     7 }
3161    };
3162 
3163   assert(Val->isVectorTy() && "This must be a vector type");
3164   Type *ScalarType = Val->getScalarType();
3165   int RegisterFileMoveCost = 0;
3166 
3167   if (Index != -1U && (Opcode == Instruction::ExtractElement ||
3168                        Opcode == Instruction::InsertElement)) {
3169     // Legalize the type.
3170     std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Val);
3171 
3172     // This type is legalized to a scalar type.
3173     if (!LT.second.isVector())
3174       return 0;
3175 
3176     // The type may be split. Normalize the index to the new type.
3177     unsigned NumElts = LT.second.getVectorNumElements();
3178     unsigned SubNumElts = NumElts;
3179     Index = Index % NumElts;
3180 
3181     // For >128-bit vectors, we need to extract higher 128-bit subvectors.
3182     // For inserts, we also need to insert the subvector back.
3183     if (LT.second.getSizeInBits() > 128) {
3184       assert((LT.second.getSizeInBits() % 128) == 0 && "Illegal vector");
3185       unsigned NumSubVecs = LT.second.getSizeInBits() / 128;
3186       SubNumElts = NumElts / NumSubVecs;
3187       if (SubNumElts <= Index) {
3188         RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1);
3189         Index %= SubNumElts;
3190       }
3191     }
3192 
3193     if (Index == 0) {
3194       // Floating point scalars are already located in index #0.
3195       // Many insertions to #0 can fold away for scalar fp-ops, so let's assume
3196       // true for all.
3197       if (ScalarType->isFloatingPointTy())
3198         return RegisterFileMoveCost;
3199 
3200       // Assume movd/movq XMM -> GPR is relatively cheap on all targets.
3201       if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement)
3202         return 1 + RegisterFileMoveCost;
3203     }
3204 
3205     int ISD = TLI->InstructionOpcodeToISD(Opcode);
3206     assert(ISD && "Unexpected vector opcode");
3207     MVT MScalarTy = LT.second.getScalarType();
3208     if (ST->isSLM())
3209       if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy))
3210         return Entry->Cost + RegisterFileMoveCost;
3211 
3212     // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets.
3213     if ((MScalarTy == MVT::i16 && ST->hasSSE2()) ||
3214         (MScalarTy.isInteger() && ST->hasSSE41()))
3215       return 1 + RegisterFileMoveCost;
3216 
3217     // Assume insertps is relatively cheap on all targets.
3218     if (MScalarTy == MVT::f32 && ST->hasSSE41() &&
3219         Opcode == Instruction::InsertElement)
3220       return 1 + RegisterFileMoveCost;
3221 
3222     // For extractions we just need to shuffle the element to index 0, which
3223     // should be very cheap (assume cost = 1). For insertions we need to shuffle
3224     // the elements to its destination. In both cases we must handle the
3225     // subvector move(s).
3226     // If the vector type is already less than 128-bits then don't reduce it.
3227     // TODO: Under what circumstances should we shuffle using the full width?
3228     InstructionCost ShuffleCost = 1;
3229     if (Opcode == Instruction::InsertElement) {
3230       auto *SubTy = cast<VectorType>(Val);
3231       EVT VT = TLI->getValueType(DL, Val);
3232       if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128)
3233         SubTy = FixedVectorType::get(ScalarType, SubNumElts);
3234       ShuffleCost =
3235           getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, None, 0, SubTy);
3236     }
3237     int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1;
3238     return ShuffleCost + IntOrFpCost + RegisterFileMoveCost;
3239   }
3240 
3241   // Add to the base cost if we know that the extracted element of a vector is
3242   // destined to be moved to and used in the integer register file.
3243   if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy())
3244     RegisterFileMoveCost += 1;
3245 
3246   return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost;
3247 }
3248 
3249 InstructionCost X86TTIImpl::getScalarizationOverhead(VectorType *Ty,
3250                                                      const APInt &DemandedElts,
3251                                                      bool Insert,
3252                                                      bool Extract) {
3253   InstructionCost Cost = 0;
3254 
3255   // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much
3256   // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT.
3257   if (Insert) {
3258     std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
3259     MVT MScalarTy = LT.second.getScalarType();
3260 
3261     if ((MScalarTy == MVT::i16 && ST->hasSSE2()) ||
3262         (MScalarTy.isInteger() && ST->hasSSE41()) ||
3263         (MScalarTy == MVT::f32 && ST->hasSSE41())) {
3264       // For types we can insert directly, insertion into 128-bit sub vectors is
3265       // cheap, followed by a cheap chain of concatenations.
3266       if (LT.second.getSizeInBits() <= 128) {
3267         Cost +=
3268             BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, false);
3269       } else {
3270         // In each 128-lane, if at least one index is demanded but not all
3271         // indices are demanded and this 128-lane is not the first 128-lane of
3272         // the legalized-vector, then this 128-lane needs a extracti128; If in
3273         // each 128-lane, there is at least one demanded index, this 128-lane
3274         // needs a inserti128.
3275 
3276         // The following cases will help you build a better understanding:
3277         // Assume we insert several elements into a v8i32 vector in avx2,
3278         // Case#1: inserting into 1th index needs vpinsrd + inserti128.
3279         // Case#2: inserting into 5th index needs extracti128 + vpinsrd +
3280         // inserti128.
3281         // Case#3: inserting into 4,5,6,7 index needs 4*vpinsrd + inserti128.
3282         const int CostValue = *LT.first.getValue();
3283         assert(CostValue >= 0 && "Negative cost!");
3284         unsigned Num128Lanes = LT.second.getSizeInBits() / 128 * CostValue;
3285         unsigned NumElts = LT.second.getVectorNumElements() * CostValue;
3286         APInt WidenedDemandedElts = DemandedElts.zextOrSelf(NumElts);
3287         unsigned Scale = NumElts / Num128Lanes;
3288         // We iterate each 128-lane, and check if we need a
3289         // extracti128/inserti128 for this 128-lane.
3290         for (unsigned I = 0; I < NumElts; I += Scale) {
3291           APInt Mask = WidenedDemandedElts.getBitsSet(NumElts, I, I + Scale);
3292           APInt MaskedDE = Mask & WidenedDemandedElts;
3293           unsigned Population = MaskedDE.countPopulation();
3294           Cost += (Population > 0 && Population != Scale &&
3295                    I % LT.second.getVectorNumElements() != 0);
3296           Cost += Population > 0;
3297         }
3298         Cost += DemandedElts.countPopulation();
3299 
3300         // For vXf32 cases, insertion into the 0'th index in each v4f32
3301         // 128-bit vector is free.
3302         // NOTE: This assumes legalization widens vXf32 vectors.
3303         if (MScalarTy == MVT::f32)
3304           for (unsigned i = 0, e = cast<FixedVectorType>(Ty)->getNumElements();
3305                i < e; i += 4)
3306             if (DemandedElts[i])
3307               Cost--;
3308       }
3309     } else if (LT.second.isVector()) {
3310       // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded
3311       // integer element as a SCALAR_TO_VECTOR, then we build the vector as a
3312       // series of UNPCK followed by CONCAT_VECTORS - all of these can be
3313       // considered cheap.
3314       if (Ty->isIntOrIntVectorTy())
3315         Cost += DemandedElts.countPopulation();
3316 
3317       // Get the smaller of the legalized or original pow2-extended number of
3318       // vector elements, which represents the number of unpacks we'll end up
3319       // performing.
3320       unsigned NumElts = LT.second.getVectorNumElements();
3321       unsigned Pow2Elts =
3322           PowerOf2Ceil(cast<FixedVectorType>(Ty)->getNumElements());
3323       Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first;
3324     }
3325   }
3326 
3327   // TODO: Use default extraction for now, but we should investigate extending this
3328   // to handle repeated subvector extraction.
3329   if (Extract)
3330     Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, false, Extract);
3331 
3332   return Cost;
3333 }
3334 
3335 InstructionCost X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
3336                                             MaybeAlign Alignment,
3337                                             unsigned AddressSpace,
3338                                             TTI::TargetCostKind CostKind,
3339                                             const Instruction *I) {
3340   // TODO: Handle other cost kinds.
3341   if (CostKind != TTI::TCK_RecipThroughput) {
3342     if (auto *SI = dyn_cast_or_null<StoreInst>(I)) {
3343       // Store instruction with index and scale costs 2 Uops.
3344       // Check the preceding GEP to identify non-const indices.
3345       if (auto *GEP = dyn_cast<GetElementPtrInst>(SI->getPointerOperand())) {
3346         if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); }))
3347           return TTI::TCC_Basic * 2;
3348       }
3349     }
3350     return TTI::TCC_Basic;
3351   }
3352 
3353   assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
3354          "Invalid Opcode");
3355   // Type legalization can't handle structs
3356   if (TLI->getValueType(DL, Src, true) == MVT::Other)
3357     return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
3358                                   CostKind);
3359 
3360   // Legalize the type.
3361   std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Src);
3362 
3363   auto *VTy = dyn_cast<FixedVectorType>(Src);
3364 
3365   // Handle the simple case of non-vectors.
3366   // NOTE: this assumes that legalization never creates vector from scalars!
3367   if (!VTy || !LT.second.isVector())
3368     // Each load/store unit costs 1.
3369     return LT.first * 1;
3370 
3371   bool IsLoad = Opcode == Instruction::Load;
3372 
3373   Type *EltTy = VTy->getElementType();
3374 
3375   const int EltTyBits = DL.getTypeSizeInBits(EltTy);
3376 
3377   InstructionCost Cost = 0;
3378 
3379   // Source of truth: how many elements were there in the original IR vector?
3380   const unsigned SrcNumElt = VTy->getNumElements();
3381 
3382   // How far have we gotten?
3383   int NumEltRemaining = SrcNumElt;
3384   // Note that we intentionally capture by-reference, NumEltRemaining changes.
3385   auto NumEltDone = [&]() { return SrcNumElt - NumEltRemaining; };
3386 
3387   const int MaxLegalOpSizeBytes = divideCeil(LT.second.getSizeInBits(), 8);
3388 
3389   // Note that even if we can store 64 bits of an XMM, we still operate on XMM.
3390   const unsigned XMMBits = 128;
3391   if (XMMBits % EltTyBits != 0)
3392     // Vector size must be a multiple of the element size. I.e. no padding.
3393     return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
3394                                   CostKind);
3395   const int NumEltPerXMM = XMMBits / EltTyBits;
3396 
3397   auto *XMMVecTy = FixedVectorType::get(EltTy, NumEltPerXMM);
3398 
3399   for (int CurrOpSizeBytes = MaxLegalOpSizeBytes, SubVecEltsLeft = 0;
3400        NumEltRemaining > 0; CurrOpSizeBytes /= 2) {
3401     // How many elements would a single op deal with at once?
3402     if ((8 * CurrOpSizeBytes) % EltTyBits != 0)
3403       // Vector size must be a multiple of the element size. I.e. no padding.
3404       return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
3405                                     CostKind);
3406     int CurrNumEltPerOp = (8 * CurrOpSizeBytes) / EltTyBits;
3407 
3408     assert(CurrOpSizeBytes > 0 && CurrNumEltPerOp > 0 && "How'd we get here?");
3409     assert((((NumEltRemaining * EltTyBits) < (2 * 8 * CurrOpSizeBytes)) ||
3410             (CurrOpSizeBytes == MaxLegalOpSizeBytes)) &&
3411            "Unless we haven't halved the op size yet, "
3412            "we have less than two op's sized units of work left.");
3413 
3414     auto *CurrVecTy = CurrNumEltPerOp > NumEltPerXMM
3415                           ? FixedVectorType::get(EltTy, CurrNumEltPerOp)
3416                           : XMMVecTy;
3417 
3418     assert(CurrVecTy->getNumElements() % CurrNumEltPerOp == 0 &&
3419            "After halving sizes, the vector elt count is no longer a multiple "
3420            "of number of elements per operation?");
3421     auto *CoalescedVecTy =
3422         CurrNumEltPerOp == 1
3423             ? CurrVecTy
3424             : FixedVectorType::get(
3425                   IntegerType::get(Src->getContext(),
3426                                    EltTyBits * CurrNumEltPerOp),
3427                   CurrVecTy->getNumElements() / CurrNumEltPerOp);
3428     assert(DL.getTypeSizeInBits(CoalescedVecTy) ==
3429                DL.getTypeSizeInBits(CurrVecTy) &&
3430            "coalesciing elements doesn't change vector width.");
3431 
3432     while (NumEltRemaining > 0) {
3433       assert(SubVecEltsLeft >= 0 && "Subreg element count overconsumtion?");
3434 
3435       // Can we use this vector size, as per the remaining element count?
3436       // Iff the vector is naturally aligned, we can do a wide load regardless.
3437       if (NumEltRemaining < CurrNumEltPerOp &&
3438           (!IsLoad || Alignment.valueOrOne() < CurrOpSizeBytes) &&
3439           CurrOpSizeBytes != 1)
3440         break; // Try smalled vector size.
3441 
3442       bool Is0thSubVec = (NumEltDone() % LT.second.getVectorNumElements()) == 0;
3443 
3444       // If we have fully processed the previous reg, we need to replenish it.
3445       if (SubVecEltsLeft == 0) {
3446         SubVecEltsLeft += CurrVecTy->getNumElements();
3447         // And that's free only for the 0'th subvector of a legalized vector.
3448         if (!Is0thSubVec)
3449           Cost += getShuffleCost(IsLoad ? TTI::ShuffleKind::SK_InsertSubvector
3450                                         : TTI::ShuffleKind::SK_ExtractSubvector,
3451                                  VTy, None, NumEltDone(), CurrVecTy);
3452       }
3453 
3454       // While we can directly load/store ZMM, YMM, and 64-bit halves of XMM,
3455       // for smaller widths (32/16/8) we have to insert/extract them separately.
3456       // Again, it's free for the 0'th subreg (if op is 32/64 bit wide,
3457       // but let's pretend that it is also true for 16/8 bit wide ops...)
3458       if (CurrOpSizeBytes <= 32 / 8 && !Is0thSubVec) {
3459         int NumEltDoneInCurrXMM = NumEltDone() % NumEltPerXMM;
3460         assert(NumEltDoneInCurrXMM % CurrNumEltPerOp == 0 && "");
3461         int CoalescedVecEltIdx = NumEltDoneInCurrXMM / CurrNumEltPerOp;
3462         APInt DemandedElts =
3463             APInt::getBitsSet(CoalescedVecTy->getNumElements(),
3464                               CoalescedVecEltIdx, CoalescedVecEltIdx + 1);
3465         assert(DemandedElts.countPopulation() == 1 && "Inserting single value");
3466         Cost += getScalarizationOverhead(CoalescedVecTy, DemandedElts, IsLoad,
3467                                          !IsLoad);
3468       }
3469 
3470       // This isn't exactly right. We're using slow unaligned 32-byte accesses
3471       // as a proxy for a double-pumped AVX memory interface such as on
3472       // Sandybridge.
3473       if (CurrOpSizeBytes == 32 && ST->isUnalignedMem32Slow())
3474         Cost += 2;
3475       else
3476         Cost += 1;
3477 
3478       SubVecEltsLeft -= CurrNumEltPerOp;
3479       NumEltRemaining -= CurrNumEltPerOp;
3480       Alignment = commonAlignment(Alignment.valueOrOne(), CurrOpSizeBytes);
3481     }
3482   }
3483 
3484   assert(NumEltRemaining <= 0 && "Should have processed all the elements.");
3485 
3486   return Cost;
3487 }
3488 
3489 InstructionCost
3490 X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, Align Alignment,
3491                                   unsigned AddressSpace,
3492                                   TTI::TargetCostKind CostKind) {
3493   bool IsLoad = (Instruction::Load == Opcode);
3494   bool IsStore = (Instruction::Store == Opcode);
3495 
3496   auto *SrcVTy = dyn_cast<FixedVectorType>(SrcTy);
3497   if (!SrcVTy)
3498     // To calculate scalar take the regular cost, without mask
3499     return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace, CostKind);
3500 
3501   unsigned NumElem = SrcVTy->getNumElements();
3502   auto *MaskTy =
3503       FixedVectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem);
3504   if ((IsLoad && !isLegalMaskedLoad(SrcVTy, Alignment)) ||
3505       (IsStore && !isLegalMaskedStore(SrcVTy, Alignment))) {
3506     // Scalarization
3507     APInt DemandedElts = APInt::getAllOnesValue(NumElem);
3508     InstructionCost MaskSplitCost =
3509         getScalarizationOverhead(MaskTy, DemandedElts, false, true);
3510     InstructionCost ScalarCompareCost = getCmpSelInstrCost(
3511         Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr,
3512         CmpInst::BAD_ICMP_PREDICATE, CostKind);
3513     InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind);
3514     InstructionCost MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost);
3515     InstructionCost ValueSplitCost =
3516         getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore);
3517     InstructionCost MemopCost =
3518         NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(),
3519                                          Alignment, AddressSpace, CostKind);
3520     return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost;
3521   }
3522 
3523   // Legalize the type.
3524   std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy);
3525   auto VT = TLI->getValueType(DL, SrcVTy);
3526   InstructionCost Cost = 0;
3527   if (VT.isSimple() && LT.second != VT.getSimpleVT() &&
3528       LT.second.getVectorNumElements() == NumElem)
3529     // Promotion requires extend/truncate for data and a shuffle for mask.
3530     Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, None, 0, nullptr) +
3531             getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, None, 0, nullptr);
3532 
3533   else if (LT.first * LT.second.getVectorNumElements() > NumElem) {
3534     auto *NewMaskTy = FixedVectorType::get(MaskTy->getElementType(),
3535                                            LT.second.getVectorNumElements());
3536     // Expanding requires fill mask with zeroes
3537     Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, None, 0, MaskTy);
3538   }
3539 
3540   // Pre-AVX512 - each maskmov load costs 2 + store costs ~8.
3541   if (!ST->hasAVX512())
3542     return Cost + LT.first * (IsLoad ? 2 : 8);
3543 
3544   // AVX-512 masked load/store is cheapper
3545   return Cost + LT.first;
3546 }
3547 
3548 InstructionCost X86TTIImpl::getAddressComputationCost(Type *Ty,
3549                                                       ScalarEvolution *SE,
3550                                                       const SCEV *Ptr) {
3551   // Address computations in vectorized code with non-consecutive addresses will
3552   // likely result in more instructions compared to scalar code where the
3553   // computation can more often be merged into the index mode. The resulting
3554   // extra micro-ops can significantly decrease throughput.
3555   const unsigned NumVectorInstToHideOverhead = 10;
3556 
3557   // Cost modeling of Strided Access Computation is hidden by the indexing
3558   // modes of X86 regardless of the stride value. We dont believe that there
3559   // is a difference between constant strided access in gerenal and constant
3560   // strided value which is less than or equal to 64.
3561   // Even in the case of (loop invariant) stride whose value is not known at
3562   // compile time, the address computation will not incur more than one extra
3563   // ADD instruction.
3564   if (Ty->isVectorTy() && SE) {
3565     if (!BaseT::isStridedAccess(Ptr))
3566       return NumVectorInstToHideOverhead;
3567     if (!BaseT::getConstantStrideStep(SE, Ptr))
3568       return 1;
3569   }
3570 
3571   return BaseT::getAddressComputationCost(Ty, SE, Ptr);
3572 }
3573 
3574 InstructionCost
3575 X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy,
3576                                        bool IsPairwise,
3577                                        TTI::TargetCostKind CostKind) {
3578   // Just use the default implementation for pair reductions.
3579   if (IsPairwise)
3580     return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise, CostKind);
3581 
3582   // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput
3583   // and make it as the cost.
3584 
3585   static const CostTblEntry SLMCostTblNoPairWise[] = {
3586     { ISD::FADD,  MVT::v2f64,   3 },
3587     { ISD::ADD,   MVT::v2i64,   5 },
3588   };
3589 
3590   static const CostTblEntry SSE2CostTblNoPairWise[] = {
3591     { ISD::FADD,  MVT::v2f64,   2 },
3592     { ISD::FADD,  MVT::v2f32,   2 },
3593     { ISD::FADD,  MVT::v4f32,   4 },
3594     { ISD::ADD,   MVT::v2i64,   2 },      // The data reported by the IACA tool is "1.6".
3595     { ISD::ADD,   MVT::v2i32,   2 }, // FIXME: chosen to be less than v4i32
3596     { ISD::ADD,   MVT::v4i32,   3 },      // The data reported by the IACA tool is "3.3".
3597     { ISD::ADD,   MVT::v2i16,   2 },      // The data reported by the IACA tool is "4.3".
3598     { ISD::ADD,   MVT::v4i16,   3 },      // The data reported by the IACA tool is "4.3".
3599     { ISD::ADD,   MVT::v8i16,   4 },      // The data reported by the IACA tool is "4.3".
3600     { ISD::ADD,   MVT::v2i8,    2 },
3601     { ISD::ADD,   MVT::v4i8,    2 },
3602     { ISD::ADD,   MVT::v8i8,    2 },
3603     { ISD::ADD,   MVT::v16i8,   3 },
3604   };
3605 
3606   static const CostTblEntry AVX1CostTblNoPairWise[] = {
3607     { ISD::FADD,  MVT::v4f64,   3 },
3608     { ISD::FADD,  MVT::v4f32,   3 },
3609     { ISD::FADD,  MVT::v8f32,   4 },
3610     { ISD::ADD,   MVT::v2i64,   1 },      // The data reported by the IACA tool is "1.5".
3611     { ISD::ADD,   MVT::v4i64,   3 },
3612     { ISD::ADD,   MVT::v8i32,   5 },
3613     { ISD::ADD,   MVT::v16i16,  5 },
3614     { ISD::ADD,   MVT::v32i8,   4 },
3615   };
3616 
3617   int ISD = TLI->InstructionOpcodeToISD(Opcode);
3618   assert(ISD && "Invalid opcode");
3619 
3620   // Before legalizing the type, give a chance to look up illegal narrow types
3621   // in the table.
3622   // FIXME: Is there a better way to do this?
3623   EVT VT = TLI->getValueType(DL, ValTy);
3624   if (VT.isSimple()) {
3625     MVT MTy = VT.getSimpleVT();
3626     if (ST->isSLM())
3627       if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy))
3628         return Entry->Cost;
3629 
3630     if (ST->hasAVX())
3631       if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy))
3632         return Entry->Cost;
3633 
3634     if (ST->hasSSE2())
3635       if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy))
3636         return Entry->Cost;
3637   }
3638 
3639   std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
3640 
3641   MVT MTy = LT.second;
3642 
3643   auto *ValVTy = cast<FixedVectorType>(ValTy);
3644 
3645   // Special case: vXi8 mul reductions are performed as vXi16.
3646   if (ISD == ISD::MUL && MTy.getScalarType() == MVT::i8) {
3647     auto *WideSclTy = IntegerType::get(ValVTy->getContext(), 16);
3648     auto *WideVecTy = FixedVectorType::get(WideSclTy, ValVTy->getNumElements());
3649     return getCastInstrCost(Instruction::ZExt, WideVecTy, ValTy,
3650                             TargetTransformInfo::CastContextHint::None,
3651                             CostKind) +
3652            getArithmeticReductionCost(Opcode, WideVecTy, IsPairwise, CostKind);
3653   }
3654 
3655   InstructionCost ArithmeticCost = 0;
3656   if (LT.first != 1 && MTy.isVector() &&
3657       MTy.getVectorNumElements() < ValVTy->getNumElements()) {
3658     // Type needs to be split. We need LT.first - 1 arithmetic ops.
3659     auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(),
3660                                             MTy.getVectorNumElements());
3661     ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind);
3662     ArithmeticCost *= LT.first - 1;
3663   }
3664 
3665   if (ST->isSLM())
3666     if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy))
3667       return ArithmeticCost + Entry->Cost;
3668 
3669   if (ST->hasAVX())
3670     if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy))
3671       return ArithmeticCost + Entry->Cost;
3672 
3673   if (ST->hasSSE2())
3674     if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy))
3675       return ArithmeticCost + Entry->Cost;
3676 
3677   // FIXME: These assume a naive kshift+binop lowering, which is probably
3678   // conservative in most cases.
3679   static const CostTblEntry AVX512BoolReduction[] = {
3680     { ISD::AND,  MVT::v2i1,   3 },
3681     { ISD::AND,  MVT::v4i1,   5 },
3682     { ISD::AND,  MVT::v8i1,   7 },
3683     { ISD::AND,  MVT::v16i1,  9 },
3684     { ISD::AND,  MVT::v32i1, 11 },
3685     { ISD::AND,  MVT::v64i1, 13 },
3686     { ISD::OR,   MVT::v2i1,   3 },
3687     { ISD::OR,   MVT::v4i1,   5 },
3688     { ISD::OR,   MVT::v8i1,   7 },
3689     { ISD::OR,   MVT::v16i1,  9 },
3690     { ISD::OR,   MVT::v32i1, 11 },
3691     { ISD::OR,   MVT::v64i1, 13 },
3692   };
3693 
3694   static const CostTblEntry AVX2BoolReduction[] = {
3695     { ISD::AND,  MVT::v16i16,  2 }, // vpmovmskb + cmp
3696     { ISD::AND,  MVT::v32i8,   2 }, // vpmovmskb + cmp
3697     { ISD::OR,   MVT::v16i16,  2 }, // vpmovmskb + cmp
3698     { ISD::OR,   MVT::v32i8,   2 }, // vpmovmskb + cmp
3699   };
3700 
3701   static const CostTblEntry AVX1BoolReduction[] = {
3702     { ISD::AND,  MVT::v4i64,   2 }, // vmovmskpd + cmp
3703     { ISD::AND,  MVT::v8i32,   2 }, // vmovmskps + cmp
3704     { ISD::AND,  MVT::v16i16,  4 }, // vextractf128 + vpand + vpmovmskb + cmp
3705     { ISD::AND,  MVT::v32i8,   4 }, // vextractf128 + vpand + vpmovmskb + cmp
3706     { ISD::OR,   MVT::v4i64,   2 }, // vmovmskpd + cmp
3707     { ISD::OR,   MVT::v8i32,   2 }, // vmovmskps + cmp
3708     { ISD::OR,   MVT::v16i16,  4 }, // vextractf128 + vpor + vpmovmskb + cmp
3709     { ISD::OR,   MVT::v32i8,   4 }, // vextractf128 + vpor + vpmovmskb + cmp
3710   };
3711 
3712   static const CostTblEntry SSE2BoolReduction[] = {
3713     { ISD::AND,  MVT::v2i64,   2 }, // movmskpd + cmp
3714     { ISD::AND,  MVT::v4i32,   2 }, // movmskps + cmp
3715     { ISD::AND,  MVT::v8i16,   2 }, // pmovmskb + cmp
3716     { ISD::AND,  MVT::v16i8,   2 }, // pmovmskb + cmp
3717     { ISD::OR,   MVT::v2i64,   2 }, // movmskpd + cmp
3718     { ISD::OR,   MVT::v4i32,   2 }, // movmskps + cmp
3719     { ISD::OR,   MVT::v8i16,   2 }, // pmovmskb + cmp
3720     { ISD::OR,   MVT::v16i8,   2 }, // pmovmskb + cmp
3721   };
3722 
3723   // Handle bool allof/anyof patterns.
3724   if (ValVTy->getElementType()->isIntegerTy(1)) {
3725     InstructionCost ArithmeticCost = 0;
3726     if (LT.first != 1 && MTy.isVector() &&
3727         MTy.getVectorNumElements() < ValVTy->getNumElements()) {
3728       // Type needs to be split. We need LT.first - 1 arithmetic ops.
3729       auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(),
3730                                               MTy.getVectorNumElements());
3731       ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind);
3732       ArithmeticCost *= LT.first - 1;
3733     }
3734 
3735     if (ST->hasAVX512())
3736       if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy))
3737         return ArithmeticCost + Entry->Cost;
3738     if (ST->hasAVX2())
3739       if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy))
3740         return ArithmeticCost + Entry->Cost;
3741     if (ST->hasAVX())
3742       if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy))
3743         return ArithmeticCost + Entry->Cost;
3744     if (ST->hasSSE2())
3745       if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy))
3746         return ArithmeticCost + Entry->Cost;
3747 
3748     return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise,
3749                                              CostKind);
3750   }
3751 
3752   unsigned NumVecElts = ValVTy->getNumElements();
3753   unsigned ScalarSize = ValVTy->getScalarSizeInBits();
3754 
3755   // Special case power of 2 reductions where the scalar type isn't changed
3756   // by type legalization.
3757   if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits())
3758     return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise,
3759                                              CostKind);
3760 
3761   InstructionCost ReductionCost = 0;
3762 
3763   auto *Ty = ValVTy;
3764   if (LT.first != 1 && MTy.isVector() &&
3765       MTy.getVectorNumElements() < ValVTy->getNumElements()) {
3766     // Type needs to be split. We need LT.first - 1 arithmetic ops.
3767     Ty = FixedVectorType::get(ValVTy->getElementType(),
3768                               MTy.getVectorNumElements());
3769     ReductionCost = getArithmeticInstrCost(Opcode, Ty, CostKind);
3770     ReductionCost *= LT.first - 1;
3771     NumVecElts = MTy.getVectorNumElements();
3772   }
3773 
3774   // Now handle reduction with the legal type, taking into account size changes
3775   // at each level.
3776   while (NumVecElts > 1) {
3777     // Determine the size of the remaining vector we need to reduce.
3778     unsigned Size = NumVecElts * ScalarSize;
3779     NumVecElts /= 2;
3780     // If we're reducing from 256/512 bits, use an extract_subvector.
3781     if (Size > 128) {
3782       auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts);
3783       ReductionCost +=
3784           getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy);
3785       Ty = SubTy;
3786     } else if (Size == 128) {
3787       // Reducing from 128 bits is a permute of v2f64/v2i64.
3788       FixedVectorType *ShufTy;
3789       if (ValVTy->isFloatingPointTy())
3790         ShufTy =
3791             FixedVectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2);
3792       else
3793         ShufTy =
3794             FixedVectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2);
3795       ReductionCost +=
3796           getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr);
3797     } else if (Size == 64) {
3798       // Reducing from 64 bits is a shuffle of v4f32/v4i32.
3799       FixedVectorType *ShufTy;
3800       if (ValVTy->isFloatingPointTy())
3801         ShufTy =
3802             FixedVectorType::get(Type::getFloatTy(ValVTy->getContext()), 4);
3803       else
3804         ShufTy =
3805             FixedVectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4);
3806       ReductionCost +=
3807           getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr);
3808     } else {
3809       // Reducing from smaller size is a shift by immediate.
3810       auto *ShiftTy = FixedVectorType::get(
3811           Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size);
3812       ReductionCost += getArithmeticInstrCost(
3813           Instruction::LShr, ShiftTy, CostKind,
3814           TargetTransformInfo::OK_AnyValue,
3815           TargetTransformInfo::OK_UniformConstantValue,
3816           TargetTransformInfo::OP_None, TargetTransformInfo::OP_None);
3817     }
3818 
3819     // Add the arithmetic op for this level.
3820     ReductionCost += getArithmeticInstrCost(Opcode, Ty, CostKind);
3821   }
3822 
3823   // Add the final extract element to the cost.
3824   return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0);
3825 }
3826 
3827 InstructionCost X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy,
3828                                           bool IsUnsigned) {
3829   std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
3830 
3831   MVT MTy = LT.second;
3832 
3833   int ISD;
3834   if (Ty->isIntOrIntVectorTy()) {
3835     ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN;
3836   } else {
3837     assert(Ty->isFPOrFPVectorTy() &&
3838            "Expected float point or integer vector type.");
3839     ISD = ISD::FMINNUM;
3840   }
3841 
3842   static const CostTblEntry SSE1CostTbl[] = {
3843     {ISD::FMINNUM, MVT::v4f32, 1},
3844   };
3845 
3846   static const CostTblEntry SSE2CostTbl[] = {
3847     {ISD::FMINNUM, MVT::v2f64, 1},
3848     {ISD::SMIN,    MVT::v8i16, 1},
3849     {ISD::UMIN,    MVT::v16i8, 1},
3850   };
3851 
3852   static const CostTblEntry SSE41CostTbl[] = {
3853     {ISD::SMIN,    MVT::v4i32, 1},
3854     {ISD::UMIN,    MVT::v4i32, 1},
3855     {ISD::UMIN,    MVT::v8i16, 1},
3856     {ISD::SMIN,    MVT::v16i8, 1},
3857   };
3858 
3859   static const CostTblEntry SSE42CostTbl[] = {
3860     {ISD::UMIN,    MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd
3861   };
3862 
3863   static const CostTblEntry AVX1CostTbl[] = {
3864     {ISD::FMINNUM, MVT::v8f32,  1},
3865     {ISD::FMINNUM, MVT::v4f64,  1},
3866     {ISD::SMIN,    MVT::v8i32,  3},
3867     {ISD::UMIN,    MVT::v8i32,  3},
3868     {ISD::SMIN,    MVT::v16i16, 3},
3869     {ISD::UMIN,    MVT::v16i16, 3},
3870     {ISD::SMIN,    MVT::v32i8,  3},
3871     {ISD::UMIN,    MVT::v32i8,  3},
3872   };
3873 
3874   static const CostTblEntry AVX2CostTbl[] = {
3875     {ISD::SMIN,    MVT::v8i32,  1},
3876     {ISD::UMIN,    MVT::v8i32,  1},
3877     {ISD::SMIN,    MVT::v16i16, 1},
3878     {ISD::UMIN,    MVT::v16i16, 1},
3879     {ISD::SMIN,    MVT::v32i8,  1},
3880     {ISD::UMIN,    MVT::v32i8,  1},
3881   };
3882 
3883   static const CostTblEntry AVX512CostTbl[] = {
3884     {ISD::FMINNUM, MVT::v16f32, 1},
3885     {ISD::FMINNUM, MVT::v8f64,  1},
3886     {ISD::SMIN,    MVT::v2i64,  1},
3887     {ISD::UMIN,    MVT::v2i64,  1},
3888     {ISD::SMIN,    MVT::v4i64,  1},
3889     {ISD::UMIN,    MVT::v4i64,  1},
3890     {ISD::SMIN,    MVT::v8i64,  1},
3891     {ISD::UMIN,    MVT::v8i64,  1},
3892     {ISD::SMIN,    MVT::v16i32, 1},
3893     {ISD::UMIN,    MVT::v16i32, 1},
3894   };
3895 
3896   static const CostTblEntry AVX512BWCostTbl[] = {
3897     {ISD::SMIN,    MVT::v32i16, 1},
3898     {ISD::UMIN,    MVT::v32i16, 1},
3899     {ISD::SMIN,    MVT::v64i8,  1},
3900     {ISD::UMIN,    MVT::v64i8,  1},
3901   };
3902 
3903   // If we have a native MIN/MAX instruction for this type, use it.
3904   if (ST->hasBWI())
3905     if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy))
3906       return LT.first * Entry->Cost;
3907 
3908   if (ST->hasAVX512())
3909     if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy))
3910       return LT.first * Entry->Cost;
3911 
3912   if (ST->hasAVX2())
3913     if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy))
3914       return LT.first * Entry->Cost;
3915 
3916   if (ST->hasAVX())
3917     if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy))
3918       return LT.first * Entry->Cost;
3919 
3920   if (ST->hasSSE42())
3921     if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy))
3922       return LT.first * Entry->Cost;
3923 
3924   if (ST->hasSSE41())
3925     if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy))
3926       return LT.first * Entry->Cost;
3927 
3928   if (ST->hasSSE2())
3929     if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy))
3930       return LT.first * Entry->Cost;
3931 
3932   if (ST->hasSSE1())
3933     if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy))
3934       return LT.first * Entry->Cost;
3935 
3936   unsigned CmpOpcode;
3937   if (Ty->isFPOrFPVectorTy()) {
3938     CmpOpcode = Instruction::FCmp;
3939   } else {
3940     assert(Ty->isIntOrIntVectorTy() &&
3941            "expecting floating point or integer type for min/max reduction");
3942     CmpOpcode = Instruction::ICmp;
3943   }
3944 
3945   TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput;
3946   // Otherwise fall back to cmp+select.
3947   InstructionCost Result =
3948       getCmpSelInstrCost(CmpOpcode, Ty, CondTy, CmpInst::BAD_ICMP_PREDICATE,
3949                          CostKind) +
3950       getCmpSelInstrCost(Instruction::Select, Ty, CondTy,
3951                          CmpInst::BAD_ICMP_PREDICATE, CostKind);
3952   return Result;
3953 }
3954 
3955 InstructionCost
3956 X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy,
3957                                    bool IsPairwise, bool IsUnsigned,
3958                                    TTI::TargetCostKind CostKind) {
3959   // Just use the default implementation for pair reductions.
3960   if (IsPairwise)
3961     return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned,
3962                                          CostKind);
3963 
3964   std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
3965 
3966   MVT MTy = LT.second;
3967 
3968   int ISD;
3969   if (ValTy->isIntOrIntVectorTy()) {
3970     ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN;
3971   } else {
3972     assert(ValTy->isFPOrFPVectorTy() &&
3973            "Expected float point or integer vector type.");
3974     ISD = ISD::FMINNUM;
3975   }
3976 
3977   // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput
3978   // and make it as the cost.
3979 
3980   static const CostTblEntry SSE2CostTblNoPairWise[] = {
3981       {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw
3982       {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw
3983       {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw
3984   };
3985 
3986   static const CostTblEntry SSE41CostTblNoPairWise[] = {
3987       {ISD::SMIN, MVT::v2i16, 3}, // same as sse2
3988       {ISD::SMIN, MVT::v4i16, 5}, // same as sse2
3989       {ISD::UMIN, MVT::v2i16, 5}, // same as sse2
3990       {ISD::UMIN, MVT::v4i16, 7}, // same as sse2
3991       {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor
3992       {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax
3993       {ISD::SMIN, MVT::v2i8,  3}, // pminsb
3994       {ISD::SMIN, MVT::v4i8,  5}, // pminsb
3995       {ISD::SMIN, MVT::v8i8,  7}, // pminsb
3996       {ISD::SMIN, MVT::v16i8, 6},
3997       {ISD::UMIN, MVT::v2i8,  3}, // same as sse2
3998       {ISD::UMIN, MVT::v4i8,  5}, // same as sse2
3999       {ISD::UMIN, MVT::v8i8,  7}, // same as sse2
4000       {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax
4001   };
4002 
4003   static const CostTblEntry AVX1CostTblNoPairWise[] = {
4004       {ISD::SMIN, MVT::v16i16, 6},
4005       {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax
4006       {ISD::SMIN, MVT::v32i8, 8},
4007       {ISD::UMIN, MVT::v32i8, 8},
4008   };
4009 
4010   static const CostTblEntry AVX512BWCostTblNoPairWise[] = {
4011       {ISD::SMIN, MVT::v32i16, 8},
4012       {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax
4013       {ISD::SMIN, MVT::v64i8, 10},
4014       {ISD::UMIN, MVT::v64i8, 10},
4015   };
4016 
4017   // Before legalizing the type, give a chance to look up illegal narrow types
4018   // in the table.
4019   // FIXME: Is there a better way to do this?
4020   EVT VT = TLI->getValueType(DL, ValTy);
4021   if (VT.isSimple()) {
4022     MVT MTy = VT.getSimpleVT();
4023     if (ST->hasBWI())
4024       if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy))
4025         return Entry->Cost;
4026 
4027     if (ST->hasAVX())
4028       if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy))
4029         return Entry->Cost;
4030 
4031     if (ST->hasSSE41())
4032       if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy))
4033         return Entry->Cost;
4034 
4035     if (ST->hasSSE2())
4036       if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy))
4037         return Entry->Cost;
4038   }
4039 
4040   auto *ValVTy = cast<FixedVectorType>(ValTy);
4041   unsigned NumVecElts = ValVTy->getNumElements();
4042 
4043   auto *Ty = ValVTy;
4044   InstructionCost MinMaxCost = 0;
4045   if (LT.first != 1 && MTy.isVector() &&
4046       MTy.getVectorNumElements() < ValVTy->getNumElements()) {
4047     // Type needs to be split. We need LT.first - 1 operations ops.
4048     Ty = FixedVectorType::get(ValVTy->getElementType(),
4049                               MTy.getVectorNumElements());
4050     auto *SubCondTy = FixedVectorType::get(CondTy->getElementType(),
4051                                            MTy.getVectorNumElements());
4052     MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned);
4053     MinMaxCost *= LT.first - 1;
4054     NumVecElts = MTy.getVectorNumElements();
4055   }
4056 
4057   if (ST->hasBWI())
4058     if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy))
4059       return MinMaxCost + Entry->Cost;
4060 
4061   if (ST->hasAVX())
4062     if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy))
4063       return MinMaxCost + Entry->Cost;
4064 
4065   if (ST->hasSSE41())
4066     if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy))
4067       return MinMaxCost + Entry->Cost;
4068 
4069   if (ST->hasSSE2())
4070     if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy))
4071       return MinMaxCost + Entry->Cost;
4072 
4073   unsigned ScalarSize = ValTy->getScalarSizeInBits();
4074 
4075   // Special case power of 2 reductions where the scalar type isn't changed
4076   // by type legalization.
4077   if (!isPowerOf2_32(ValVTy->getNumElements()) ||
4078       ScalarSize != MTy.getScalarSizeInBits())
4079     return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned,
4080                                          CostKind);
4081 
4082   // Now handle reduction with the legal type, taking into account size changes
4083   // at each level.
4084   while (NumVecElts > 1) {
4085     // Determine the size of the remaining vector we need to reduce.
4086     unsigned Size = NumVecElts * ScalarSize;
4087     NumVecElts /= 2;
4088     // If we're reducing from 256/512 bits, use an extract_subvector.
4089     if (Size > 128) {
4090       auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts);
4091       MinMaxCost +=
4092           getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy);
4093       Ty = SubTy;
4094     } else if (Size == 128) {
4095       // Reducing from 128 bits is a permute of v2f64/v2i64.
4096       VectorType *ShufTy;
4097       if (ValTy->isFloatingPointTy())
4098         ShufTy =
4099             FixedVectorType::get(Type::getDoubleTy(ValTy->getContext()), 2);
4100       else
4101         ShufTy = FixedVectorType::get(Type::getInt64Ty(ValTy->getContext()), 2);
4102       MinMaxCost +=
4103           getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr);
4104     } else if (Size == 64) {
4105       // Reducing from 64 bits is a shuffle of v4f32/v4i32.
4106       FixedVectorType *ShufTy;
4107       if (ValTy->isFloatingPointTy())
4108         ShufTy = FixedVectorType::get(Type::getFloatTy(ValTy->getContext()), 4);
4109       else
4110         ShufTy = FixedVectorType::get(Type::getInt32Ty(ValTy->getContext()), 4);
4111       MinMaxCost +=
4112           getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr);
4113     } else {
4114       // Reducing from smaller size is a shift by immediate.
4115       auto *ShiftTy = FixedVectorType::get(
4116           Type::getIntNTy(ValTy->getContext(), Size), 128 / Size);
4117       MinMaxCost += getArithmeticInstrCost(
4118           Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput,
4119           TargetTransformInfo::OK_AnyValue,
4120           TargetTransformInfo::OK_UniformConstantValue,
4121           TargetTransformInfo::OP_None, TargetTransformInfo::OP_None);
4122     }
4123 
4124     // Add the arithmetic op for this level.
4125     auto *SubCondTy =
4126         FixedVectorType::get(CondTy->getElementType(), Ty->getNumElements());
4127     MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned);
4128   }
4129 
4130   // Add the final extract element to the cost.
4131   return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0);
4132 }
4133 
4134 /// Calculate the cost of materializing a 64-bit value. This helper
4135 /// method might only calculate a fraction of a larger immediate. Therefore it
4136 /// is valid to return a cost of ZERO.
4137 InstructionCost X86TTIImpl::getIntImmCost(int64_t Val) {
4138   if (Val == 0)
4139     return TTI::TCC_Free;
4140 
4141   if (isInt<32>(Val))
4142     return TTI::TCC_Basic;
4143 
4144   return 2 * TTI::TCC_Basic;
4145 }
4146 
4147 InstructionCost X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty,
4148                                           TTI::TargetCostKind CostKind) {
4149   assert(Ty->isIntegerTy());
4150 
4151   unsigned BitSize = Ty->getPrimitiveSizeInBits();
4152   if (BitSize == 0)
4153     return ~0U;
4154 
4155   // Never hoist constants larger than 128bit, because this might lead to
4156   // incorrect code generation or assertions in codegen.
4157   // Fixme: Create a cost model for types larger than i128 once the codegen
4158   // issues have been fixed.
4159   if (BitSize > 128)
4160     return TTI::TCC_Free;
4161 
4162   if (Imm == 0)
4163     return TTI::TCC_Free;
4164 
4165   // Sign-extend all constants to a multiple of 64-bit.
4166   APInt ImmVal = Imm;
4167   if (BitSize % 64 != 0)
4168     ImmVal = Imm.sext(alignTo(BitSize, 64));
4169 
4170   // Split the constant into 64-bit chunks and calculate the cost for each
4171   // chunk.
4172   InstructionCost Cost = 0;
4173   for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) {
4174     APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64);
4175     int64_t Val = Tmp.getSExtValue();
4176     Cost += getIntImmCost(Val);
4177   }
4178   // We need at least one instruction to materialize the constant.
4179   return std::max<InstructionCost>(1, Cost);
4180 }
4181 
4182 InstructionCost X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
4183                                               const APInt &Imm, Type *Ty,
4184                                               TTI::TargetCostKind CostKind,
4185                                               Instruction *Inst) {
4186   assert(Ty->isIntegerTy());
4187 
4188   unsigned BitSize = Ty->getPrimitiveSizeInBits();
4189   // There is no cost model for constants with a bit size of 0. Return TCC_Free
4190   // here, so that constant hoisting will ignore this constant.
4191   if (BitSize == 0)
4192     return TTI::TCC_Free;
4193 
4194   unsigned ImmIdx = ~0U;
4195   switch (Opcode) {
4196   default:
4197     return TTI::TCC_Free;
4198   case Instruction::GetElementPtr:
4199     // Always hoist the base address of a GetElementPtr. This prevents the
4200     // creation of new constants for every base constant that gets constant
4201     // folded with the offset.
4202     if (Idx == 0)
4203       return 2 * TTI::TCC_Basic;
4204     return TTI::TCC_Free;
4205   case Instruction::Store:
4206     ImmIdx = 0;
4207     break;
4208   case Instruction::ICmp:
4209     // This is an imperfect hack to prevent constant hoisting of
4210     // compares that might be trying to check if a 64-bit value fits in
4211     // 32-bits. The backend can optimize these cases using a right shift by 32.
4212     // Ideally we would check the compare predicate here. There also other
4213     // similar immediates the backend can use shifts for.
4214     if (Idx == 1 && Imm.getBitWidth() == 64) {
4215       uint64_t ImmVal = Imm.getZExtValue();
4216       if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff)
4217         return TTI::TCC_Free;
4218     }
4219     ImmIdx = 1;
4220     break;
4221   case Instruction::And:
4222     // We support 64-bit ANDs with immediates with 32-bits of leading zeroes
4223     // by using a 32-bit operation with implicit zero extension. Detect such
4224     // immediates here as the normal path expects bit 31 to be sign extended.
4225     if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue()))
4226       return TTI::TCC_Free;
4227     ImmIdx = 1;
4228     break;
4229   case Instruction::Add:
4230   case Instruction::Sub:
4231     // For add/sub, we can use the opposite instruction for INT32_MIN.
4232     if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000)
4233       return TTI::TCC_Free;
4234     ImmIdx = 1;
4235     break;
4236   case Instruction::UDiv:
4237   case Instruction::SDiv:
4238   case Instruction::URem:
4239   case Instruction::SRem:
4240     // Division by constant is typically expanded later into a different
4241     // instruction sequence. This completely changes the constants.
4242     // Report them as "free" to stop ConstantHoist from marking them as opaque.
4243     return TTI::TCC_Free;
4244   case Instruction::Mul:
4245   case Instruction::Or:
4246   case Instruction::Xor:
4247     ImmIdx = 1;
4248     break;
4249   // Always return TCC_Free for the shift value of a shift instruction.
4250   case Instruction::Shl:
4251   case Instruction::LShr:
4252   case Instruction::AShr:
4253     if (Idx == 1)
4254       return TTI::TCC_Free;
4255     break;
4256   case Instruction::Trunc:
4257   case Instruction::ZExt:
4258   case Instruction::SExt:
4259   case Instruction::IntToPtr:
4260   case Instruction::PtrToInt:
4261   case Instruction::BitCast:
4262   case Instruction::PHI:
4263   case Instruction::Call:
4264   case Instruction::Select:
4265   case Instruction::Ret:
4266   case Instruction::Load:
4267     break;
4268   }
4269 
4270   if (Idx == ImmIdx) {
4271     int NumConstants = divideCeil(BitSize, 64);
4272     InstructionCost Cost = X86TTIImpl::getIntImmCost(Imm, Ty, CostKind);
4273     return (Cost <= NumConstants * TTI::TCC_Basic)
4274                ? static_cast<int>(TTI::TCC_Free)
4275                : Cost;
4276   }
4277 
4278   return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind);
4279 }
4280 
4281 InstructionCost X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
4282                                                 const APInt &Imm, Type *Ty,
4283                                                 TTI::TargetCostKind CostKind) {
4284   assert(Ty->isIntegerTy());
4285 
4286   unsigned BitSize = Ty->getPrimitiveSizeInBits();
4287   // There is no cost model for constants with a bit size of 0. Return TCC_Free
4288   // here, so that constant hoisting will ignore this constant.
4289   if (BitSize == 0)
4290     return TTI::TCC_Free;
4291 
4292   switch (IID) {
4293   default:
4294     return TTI::TCC_Free;
4295   case Intrinsic::sadd_with_overflow:
4296   case Intrinsic::uadd_with_overflow:
4297   case Intrinsic::ssub_with_overflow:
4298   case Intrinsic::usub_with_overflow:
4299   case Intrinsic::smul_with_overflow:
4300   case Intrinsic::umul_with_overflow:
4301     if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue()))
4302       return TTI::TCC_Free;
4303     break;
4304   case Intrinsic::experimental_stackmap:
4305     if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
4306       return TTI::TCC_Free;
4307     break;
4308   case Intrinsic::experimental_patchpoint_void:
4309   case Intrinsic::experimental_patchpoint_i64:
4310     if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
4311       return TTI::TCC_Free;
4312     break;
4313   }
4314   return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind);
4315 }
4316 
4317 InstructionCost X86TTIImpl::getCFInstrCost(unsigned Opcode,
4318                                            TTI::TargetCostKind CostKind,
4319                                            const Instruction *I) {
4320   if (CostKind != TTI::TCK_RecipThroughput)
4321     return Opcode == Instruction::PHI ? 0 : 1;
4322   // Branches are assumed to be predicted.
4323   return 0;
4324 }
4325 
4326 int X86TTIImpl::getGatherOverhead() const {
4327   // Some CPUs have more overhead for gather. The specified overhead is relative
4328   // to the Load operation. "2" is the number provided by Intel architects. This
4329   // parameter is used for cost estimation of Gather Op and comparison with
4330   // other alternatives.
4331   // TODO: Remove the explicit hasAVX512()?, That would mean we would only
4332   // enable gather with a -march.
4333   if (ST->hasAVX512() || (ST->hasAVX2() && ST->hasFastGather()))
4334     return 2;
4335 
4336   return 1024;
4337 }
4338 
4339 int X86TTIImpl::getScatterOverhead() const {
4340   if (ST->hasAVX512())
4341     return 2;
4342 
4343   return 1024;
4344 }
4345 
4346 // Return an average cost of Gather / Scatter instruction, maybe improved later.
4347 // FIXME: Add TargetCostKind support.
4348 InstructionCost X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy,
4349                                             const Value *Ptr, Align Alignment,
4350                                             unsigned AddressSpace) {
4351 
4352   assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost");
4353   unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements();
4354 
4355   // Try to reduce index size from 64 bit (default for GEP)
4356   // to 32. It is essential for VF 16. If the index can't be reduced to 32, the
4357   // operation will use 16 x 64 indices which do not fit in a zmm and needs
4358   // to split. Also check that the base pointer is the same for all lanes,
4359   // and that there's at most one variable index.
4360   auto getIndexSizeInBits = [](const Value *Ptr, const DataLayout &DL) {
4361     unsigned IndexSize = DL.getPointerSizeInBits();
4362     const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
4363     if (IndexSize < 64 || !GEP)
4364       return IndexSize;
4365 
4366     unsigned NumOfVarIndices = 0;
4367     const Value *Ptrs = GEP->getPointerOperand();
4368     if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs))
4369       return IndexSize;
4370     for (unsigned i = 1; i < GEP->getNumOperands(); ++i) {
4371       if (isa<Constant>(GEP->getOperand(i)))
4372         continue;
4373       Type *IndxTy = GEP->getOperand(i)->getType();
4374       if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy))
4375         IndxTy = IndexVTy->getElementType();
4376       if ((IndxTy->getPrimitiveSizeInBits() == 64 &&
4377           !isa<SExtInst>(GEP->getOperand(i))) ||
4378          ++NumOfVarIndices > 1)
4379         return IndexSize; // 64
4380     }
4381     return (unsigned)32;
4382   };
4383 
4384   // Trying to reduce IndexSize to 32 bits for vector 16.
4385   // By default the IndexSize is equal to pointer size.
4386   unsigned IndexSize = (ST->hasAVX512() && VF >= 16)
4387                            ? getIndexSizeInBits(Ptr, DL)
4388                            : DL.getPointerSizeInBits();
4389 
4390   auto *IndexVTy = FixedVectorType::get(
4391       IntegerType::get(SrcVTy->getContext(), IndexSize), VF);
4392   std::pair<InstructionCost, MVT> IdxsLT =
4393       TLI->getTypeLegalizationCost(DL, IndexVTy);
4394   std::pair<InstructionCost, MVT> SrcLT =
4395       TLI->getTypeLegalizationCost(DL, SrcVTy);
4396   InstructionCost::CostType SplitFactor =
4397       *std::max(IdxsLT.first, SrcLT.first).getValue();
4398   if (SplitFactor > 1) {
4399     // Handle splitting of vector of pointers
4400     auto *SplitSrcTy =
4401         FixedVectorType::get(SrcVTy->getScalarType(), VF / SplitFactor);
4402     return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment,
4403                                          AddressSpace);
4404   }
4405 
4406   // The gather / scatter cost is given by Intel architects. It is a rough
4407   // number since we are looking at one instruction in a time.
4408   const int GSOverhead = (Opcode == Instruction::Load)
4409                              ? getGatherOverhead()
4410                              : getScatterOverhead();
4411   return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(),
4412                                            MaybeAlign(Alignment), AddressSpace,
4413                                            TTI::TCK_RecipThroughput);
4414 }
4415 
4416 /// Return the cost of full scalarization of gather / scatter operation.
4417 ///
4418 /// Opcode - Load or Store instruction.
4419 /// SrcVTy - The type of the data vector that should be gathered or scattered.
4420 /// VariableMask - The mask is non-constant at compile time.
4421 /// Alignment - Alignment for one element.
4422 /// AddressSpace - pointer[s] address space.
4423 ///
4424 /// FIXME: Add TargetCostKind support.
4425 InstructionCost X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy,
4426                                             bool VariableMask, Align Alignment,
4427                                             unsigned AddressSpace) {
4428   unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements();
4429   APInt DemandedElts = APInt::getAllOnesValue(VF);
4430   TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput;
4431 
4432   InstructionCost MaskUnpackCost = 0;
4433   if (VariableMask) {
4434     auto *MaskTy =
4435         FixedVectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF);
4436     MaskUnpackCost =
4437         getScalarizationOverhead(MaskTy, DemandedElts, false, true);
4438     InstructionCost ScalarCompareCost = getCmpSelInstrCost(
4439         Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), nullptr,
4440         CmpInst::BAD_ICMP_PREDICATE, CostKind);
4441     InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind);
4442     MaskUnpackCost += VF * (BranchCost + ScalarCompareCost);
4443   }
4444 
4445   // The cost of the scalar loads/stores.
4446   InstructionCost MemoryOpCost =
4447       VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(),
4448                            MaybeAlign(Alignment), AddressSpace, CostKind);
4449 
4450   InstructionCost InsertExtractCost = 0;
4451   if (Opcode == Instruction::Load)
4452     for (unsigned i = 0; i < VF; ++i)
4453       // Add the cost of inserting each scalar load into the vector
4454       InsertExtractCost +=
4455         getVectorInstrCost(Instruction::InsertElement, SrcVTy, i);
4456   else
4457     for (unsigned i = 0; i < VF; ++i)
4458       // Add the cost of extracting each element out of the data vector
4459       InsertExtractCost +=
4460         getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i);
4461 
4462   return MemoryOpCost + MaskUnpackCost + InsertExtractCost;
4463 }
4464 
4465 /// Calculate the cost of Gather / Scatter operation
4466 InstructionCost X86TTIImpl::getGatherScatterOpCost(
4467     unsigned Opcode, Type *SrcVTy, const Value *Ptr, bool VariableMask,
4468     Align Alignment, TTI::TargetCostKind CostKind,
4469     const Instruction *I = nullptr) {
4470   if (CostKind != TTI::TCK_RecipThroughput) {
4471     if ((Opcode == Instruction::Load &&
4472          isLegalMaskedGather(SrcVTy, Align(Alignment))) ||
4473         (Opcode == Instruction::Store &&
4474          isLegalMaskedScatter(SrcVTy, Align(Alignment))))
4475       return 1;
4476     return BaseT::getGatherScatterOpCost(Opcode, SrcVTy, Ptr, VariableMask,
4477                                          Alignment, CostKind, I);
4478   }
4479 
4480   assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter");
4481   unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements();
4482   PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType());
4483   if (!PtrTy && Ptr->getType()->isVectorTy())
4484     PtrTy = dyn_cast<PointerType>(
4485         cast<VectorType>(Ptr->getType())->getElementType());
4486   assert(PtrTy && "Unexpected type for Ptr argument");
4487   unsigned AddressSpace = PtrTy->getAddressSpace();
4488 
4489   bool Scalarize = false;
4490   if ((Opcode == Instruction::Load &&
4491        !isLegalMaskedGather(SrcVTy, Align(Alignment))) ||
4492       (Opcode == Instruction::Store &&
4493        !isLegalMaskedScatter(SrcVTy, Align(Alignment))))
4494     Scalarize = true;
4495   // Gather / Scatter for vector 2 is not profitable on KNL / SKX
4496   // Vector-4 of gather/scatter instruction does not exist on KNL.
4497   // We can extend it to 8 elements, but zeroing upper bits of
4498   // the mask vector will add more instructions. Right now we give the scalar
4499   // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction
4500   // is better in the VariableMask case.
4501   if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX())))
4502     Scalarize = true;
4503 
4504   if (Scalarize)
4505     return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment,
4506                            AddressSpace);
4507 
4508   return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace);
4509 }
4510 
4511 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1,
4512                                TargetTransformInfo::LSRCost &C2) {
4513     // X86 specific here are "instruction number 1st priority".
4514     return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost,
4515                     C1.NumIVMuls, C1.NumBaseAdds,
4516                     C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
4517            std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost,
4518                     C2.NumIVMuls, C2.NumBaseAdds,
4519                     C2.ScaleCost, C2.ImmCost, C2.SetupCost);
4520 }
4521 
4522 bool X86TTIImpl::canMacroFuseCmp() {
4523   return ST->hasMacroFusion() || ST->hasBranchFusion();
4524 }
4525 
4526 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, Align Alignment) {
4527   if (!ST->hasAVX())
4528     return false;
4529 
4530   // The backend can't handle a single element vector.
4531   if (isa<VectorType>(DataTy) &&
4532       cast<FixedVectorType>(DataTy)->getNumElements() == 1)
4533     return false;
4534   Type *ScalarTy = DataTy->getScalarType();
4535 
4536   if (ScalarTy->isPointerTy())
4537     return true;
4538 
4539   if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy())
4540     return true;
4541 
4542   if (!ScalarTy->isIntegerTy())
4543     return false;
4544 
4545   unsigned IntWidth = ScalarTy->getIntegerBitWidth();
4546   return IntWidth == 32 || IntWidth == 64 ||
4547          ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI());
4548 }
4549 
4550 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, Align Alignment) {
4551   return isLegalMaskedLoad(DataType, Alignment);
4552 }
4553 
4554 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) {
4555   unsigned DataSize = DL.getTypeStoreSize(DataType);
4556   // The only supported nontemporal loads are for aligned vectors of 16 or 32
4557   // bytes.  Note that 32-byte nontemporal vector loads are supported by AVX2
4558   // (the equivalent stores only require AVX).
4559   if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32))
4560     return DataSize == 16 ?  ST->hasSSE1() : ST->hasAVX2();
4561 
4562   return false;
4563 }
4564 
4565 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) {
4566   unsigned DataSize = DL.getTypeStoreSize(DataType);
4567 
4568   // SSE4A supports nontemporal stores of float and double at arbitrary
4569   // alignment.
4570   if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy()))
4571     return true;
4572 
4573   // Besides the SSE4A subtarget exception above, only aligned stores are
4574   // available nontemporaly on any other subtarget.  And only stores with a size
4575   // of 4..32 bytes (powers of 2, only) are permitted.
4576   if (Alignment < DataSize || DataSize < 4 || DataSize > 32 ||
4577       !isPowerOf2_32(DataSize))
4578     return false;
4579 
4580   // 32-byte vector nontemporal stores are supported by AVX (the equivalent
4581   // loads require AVX2).
4582   if (DataSize == 32)
4583     return ST->hasAVX();
4584   else if (DataSize == 16)
4585     return ST->hasSSE1();
4586   return true;
4587 }
4588 
4589 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) {
4590   if (!isa<VectorType>(DataTy))
4591     return false;
4592 
4593   if (!ST->hasAVX512())
4594     return false;
4595 
4596   // The backend can't handle a single element vector.
4597   if (cast<FixedVectorType>(DataTy)->getNumElements() == 1)
4598     return false;
4599 
4600   Type *ScalarTy = cast<VectorType>(DataTy)->getElementType();
4601 
4602   if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy())
4603     return true;
4604 
4605   if (!ScalarTy->isIntegerTy())
4606     return false;
4607 
4608   unsigned IntWidth = ScalarTy->getIntegerBitWidth();
4609   return IntWidth == 32 || IntWidth == 64 ||
4610          ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2());
4611 }
4612 
4613 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) {
4614   return isLegalMaskedExpandLoad(DataTy);
4615 }
4616 
4617 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, Align Alignment) {
4618   // Some CPUs have better gather performance than others.
4619   // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only
4620   // enable gather with a -march.
4621   if (!(ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2())))
4622     return false;
4623 
4624   // This function is called now in two cases: from the Loop Vectorizer
4625   // and from the Scalarizer.
4626   // When the Loop Vectorizer asks about legality of the feature,
4627   // the vectorization factor is not calculated yet. The Loop Vectorizer
4628   // sends a scalar type and the decision is based on the width of the
4629   // scalar element.
4630   // Later on, the cost model will estimate usage this intrinsic based on
4631   // the vector type.
4632   // The Scalarizer asks again about legality. It sends a vector type.
4633   // In this case we can reject non-power-of-2 vectors.
4634   // We also reject single element vectors as the type legalizer can't
4635   // scalarize it.
4636   if (auto *DataVTy = dyn_cast<FixedVectorType>(DataTy)) {
4637     unsigned NumElts = DataVTy->getNumElements();
4638     if (NumElts == 1)
4639       return false;
4640   }
4641   Type *ScalarTy = DataTy->getScalarType();
4642   if (ScalarTy->isPointerTy())
4643     return true;
4644 
4645   if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy())
4646     return true;
4647 
4648   if (!ScalarTy->isIntegerTy())
4649     return false;
4650 
4651   unsigned IntWidth = ScalarTy->getIntegerBitWidth();
4652   return IntWidth == 32 || IntWidth == 64;
4653 }
4654 
4655 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, Align Alignment) {
4656   // AVX2 doesn't support scatter
4657   if (!ST->hasAVX512())
4658     return false;
4659   return isLegalMaskedGather(DataType, Alignment);
4660 }
4661 
4662 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) {
4663   EVT VT = TLI->getValueType(DL, DataType);
4664   return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT);
4665 }
4666 
4667 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) {
4668   return false;
4669 }
4670 
4671 bool X86TTIImpl::areInlineCompatible(const Function *Caller,
4672                                      const Function *Callee) const {
4673   const TargetMachine &TM = getTLI()->getTargetMachine();
4674 
4675   // Work this as a subsetting of subtarget features.
4676   const FeatureBitset &CallerBits =
4677       TM.getSubtargetImpl(*Caller)->getFeatureBits();
4678   const FeatureBitset &CalleeBits =
4679       TM.getSubtargetImpl(*Callee)->getFeatureBits();
4680 
4681   FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList;
4682   FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList;
4683   return (RealCallerBits & RealCalleeBits) == RealCalleeBits;
4684 }
4685 
4686 bool X86TTIImpl::areFunctionArgsABICompatible(
4687     const Function *Caller, const Function *Callee,
4688     SmallPtrSetImpl<Argument *> &Args) const {
4689   if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args))
4690     return false;
4691 
4692   // If we get here, we know the target features match. If one function
4693   // considers 512-bit vectors legal and the other does not, consider them
4694   // incompatible.
4695   const TargetMachine &TM = getTLI()->getTargetMachine();
4696 
4697   if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() ==
4698       TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs())
4699     return true;
4700 
4701   // Consider the arguments compatible if they aren't vectors or aggregates.
4702   // FIXME: Look at the size of vectors.
4703   // FIXME: Look at the element types of aggregates to see if there are vectors.
4704   // FIXME: The API of this function seems intended to allow arguments
4705   // to be removed from the set, but the caller doesn't check if the set
4706   // becomes empty so that may not work in practice.
4707   return llvm::none_of(Args, [](Argument *A) {
4708     auto *EltTy = cast<PointerType>(A->getType())->getElementType();
4709     return EltTy->isVectorTy() || EltTy->isAggregateType();
4710   });
4711 }
4712 
4713 X86TTIImpl::TTI::MemCmpExpansionOptions
4714 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
4715   TTI::MemCmpExpansionOptions Options;
4716   Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize);
4717   Options.NumLoadsPerBlock = 2;
4718   // All GPR and vector loads can be unaligned.
4719   Options.AllowOverlappingLoads = true;
4720   if (IsZeroCmp) {
4721     // Only enable vector loads for equality comparison. Right now the vector
4722     // version is not as fast for three way compare (see #33329).
4723     const unsigned PreferredWidth = ST->getPreferVectorWidth();
4724     if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64);
4725     if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32);
4726     if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16);
4727   }
4728   if (ST->is64Bit()) {
4729     Options.LoadSizes.push_back(8);
4730   }
4731   Options.LoadSizes.push_back(4);
4732   Options.LoadSizes.push_back(2);
4733   Options.LoadSizes.push_back(1);
4734   return Options;
4735 }
4736 
4737 bool X86TTIImpl::enableInterleavedAccessVectorization() {
4738   // TODO: We expect this to be beneficial regardless of arch,
4739   // but there are currently some unexplained performance artifacts on Atom.
4740   // As a temporary solution, disable on Atom.
4741   return !(ST->isAtom());
4742 }
4743 
4744 // Get estimation for interleaved load/store operations for AVX2.
4745 // \p Factor is the interleaved-access factor (stride) - number of
4746 // (interleaved) elements in the group.
4747 // \p Indices contains the indices for a strided load: when the
4748 // interleaved load has gaps they indicate which elements are used.
4749 // If Indices is empty (or if the number of indices is equal to the size
4750 // of the interleaved-access as given in \p Factor) the access has no gaps.
4751 //
4752 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow
4753 // computing the cost using a generic formula as a function of generic
4754 // shuffles. We therefore use a lookup table instead, filled according to
4755 // the instruction sequences that codegen currently generates.
4756 InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2(
4757     unsigned Opcode, FixedVectorType *VecTy, unsigned Factor,
4758     ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace,
4759     TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) {
4760 
4761   if (UseMaskForCond || UseMaskForGaps)
4762     return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
4763                                              Alignment, AddressSpace, CostKind,
4764                                              UseMaskForCond, UseMaskForGaps);
4765 
4766   // We currently Support only fully-interleaved groups, with no gaps.
4767   // TODO: Support also strided loads (interleaved-groups with gaps).
4768   if (Indices.size() && Indices.size() != Factor)
4769     return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
4770                                              Alignment, AddressSpace, CostKind);
4771 
4772   // VecTy for interleave memop is <VF*Factor x Elt>.
4773   // So, for VF=4, Interleave Factor = 3, Element type = i32 we have
4774   // VecTy = <12 x i32>.
4775   MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second;
4776 
4777   // This function can be called with VecTy=<6xi128>, Factor=3, in which case
4778   // the VF=2, while v2i128 is an unsupported MVT vector type
4779   // (see MachineValueType.h::getVectorVT()).
4780   if (!LegalVT.isVector())
4781     return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
4782                                              Alignment, AddressSpace, CostKind);
4783 
4784   unsigned VF = VecTy->getNumElements() / Factor;
4785   Type *ScalarTy = VecTy->getElementType();
4786   // Deduplicate entries, model floats/pointers as appropriately-sized integers.
4787   if (!ScalarTy->isIntegerTy())
4788     ScalarTy =
4789         Type::getIntNTy(ScalarTy->getContext(), DL.getTypeSizeInBits(ScalarTy));
4790 
4791   // Get the cost of all the memory operations.
4792   InstructionCost MemOpCosts = getMemoryOpCost(
4793       Opcode, VecTy, MaybeAlign(Alignment), AddressSpace, CostKind);
4794 
4795   auto *VT = FixedVectorType::get(ScalarTy, VF);
4796   EVT ETy = TLI->getValueType(DL, VT);
4797   if (!ETy.isSimple())
4798     return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
4799                                              Alignment, AddressSpace, CostKind);
4800 
4801   // TODO: Complete for other data-types and strides.
4802   // Each combination of Stride, element bit width and VF results in a different
4803   // sequence; The cost tables are therefore accessed with:
4804   // Factor (stride) and VectorType=VFxiN.
4805   // The Cost accounts only for the shuffle sequence;
4806   // The cost of the loads/stores is accounted for separately.
4807   //
4808   static const CostTblEntry AVX2InterleavedLoadTbl[] = {
4809       {2, MVT::v4i64, 6}, // (load 8i64 and) deinterleave into 2 x 4i64
4810 
4811       {3, MVT::v2i8, 10},  // (load 6i8 and) deinterleave into 3 x 2i8
4812       {3, MVT::v4i8, 4},   // (load 12i8 and) deinterleave into 3 x 4i8
4813       {3, MVT::v8i8, 9},   // (load 24i8 and) deinterleave into 3 x 8i8
4814       {3, MVT::v16i8, 11}, // (load 48i8 and) deinterleave into 3 x 16i8
4815       {3, MVT::v32i8, 13}, // (load 96i8 and) deinterleave into 3 x 32i8
4816 
4817       {3, MVT::v8i32, 17}, // (load 24i32 and) deinterleave into 3 x 8i32
4818 
4819       {4, MVT::v2i8, 12},  // (load 8i8 and) deinterleave into 4 x 2i8
4820       {4, MVT::v4i8, 4},   // (load 16i8 and) deinterleave into 4 x 4i8
4821       {4, MVT::v8i8, 20},  // (load 32i8 and) deinterleave into 4 x 8i8
4822       {4, MVT::v16i8, 39}, // (load 64i8 and) deinterleave into 4 x 16i8
4823       {4, MVT::v32i8, 80}, // (load 128i8 and) deinterleave into 4 x 32i8
4824 
4825       {8, MVT::v8i32, 40} // (load 64i32 and) deinterleave into 8 x 8i32
4826   };
4827 
4828   static const CostTblEntry AVX2InterleavedStoreTbl[] = {
4829       {2, MVT::v4i64, 6}, // interleave 2 x 4i64 into 8i64 (and store)
4830 
4831       {3, MVT::v2i8, 7},   // interleave 3 x 2i8 into 6i8 (and store)
4832       {3, MVT::v4i8, 8},   // interleave 3 x 4i8 into 12i8 (and store)
4833       {3, MVT::v8i8, 11},  // interleave 3 x 8i8 into 24i8 (and store)
4834       {3, MVT::v16i8, 11}, // interleave 3 x 16i8 into 48i8 (and store)
4835       {3, MVT::v32i8, 13}, // interleave 3 x 32i8 into 96i8 (and store)
4836 
4837       {4, MVT::v2i8, 12},  // interleave 4 x 2i8 into 8i8 (and store)
4838       {4, MVT::v4i8, 9},   // interleave 4 x 4i8 into 16i8 (and store)
4839       {4, MVT::v8i8, 10},  // interleave 4 x 8i8 into 32i8 (and store)
4840       {4, MVT::v16i8, 10}, // interleave 4 x 16i8 into 64i8 (and store)
4841       {4, MVT::v32i8, 12}  // interleave 4 x 32i8 into 128i8 (and store)
4842   };
4843 
4844   if (Opcode == Instruction::Load) {
4845     if (const auto *Entry =
4846             CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT()))
4847       return MemOpCosts + Entry->Cost;
4848   } else {
4849     assert(Opcode == Instruction::Store &&
4850            "Expected Store Instruction at this  point");
4851     if (const auto *Entry =
4852             CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT()))
4853       return MemOpCosts + Entry->Cost;
4854   }
4855 
4856   return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
4857                                            Alignment, AddressSpace, CostKind);
4858 }
4859 
4860 // Get estimation for interleaved load/store operations and strided load.
4861 // \p Indices contains indices for strided load.
4862 // \p Factor - the factor of interleaving.
4863 // AVX-512 provides 3-src shuffles that significantly reduces the cost.
4864 InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX512(
4865     unsigned Opcode, FixedVectorType *VecTy, unsigned Factor,
4866     ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace,
4867     TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) {
4868 
4869   if (UseMaskForCond || UseMaskForGaps)
4870     return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
4871                                              Alignment, AddressSpace, CostKind,
4872                                              UseMaskForCond, UseMaskForGaps);
4873 
4874   // VecTy for interleave memop is <VF*Factor x Elt>.
4875   // So, for VF=4, Interleave Factor = 3, Element type = i32 we have
4876   // VecTy = <12 x i32>.
4877 
4878   // Calculate the number of memory operations (NumOfMemOps), required
4879   // for load/store the VecTy.
4880   MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second;
4881   unsigned VecTySize = DL.getTypeStoreSize(VecTy);
4882   unsigned LegalVTSize = LegalVT.getStoreSize();
4883   unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize;
4884 
4885   // Get the cost of one memory operation.
4886   auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(),
4887                                              LegalVT.getVectorNumElements());
4888   InstructionCost MemOpCost = getMemoryOpCost(
4889       Opcode, SingleMemOpTy, MaybeAlign(Alignment), AddressSpace, CostKind);
4890 
4891   unsigned VF = VecTy->getNumElements() / Factor;
4892   MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF);
4893 
4894   if (Opcode == Instruction::Load) {
4895     // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl)
4896     // contain the cost of the optimized shuffle sequence that the
4897     // X86InterleavedAccess pass will generate.
4898     // The cost of loads and stores are computed separately from the table.
4899 
4900     // X86InterleavedAccess support only the following interleaved-access group.
4901     static const CostTblEntry AVX512InterleavedLoadTbl[] = {
4902         {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8
4903         {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8
4904         {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8
4905     };
4906 
4907     if (const auto *Entry =
4908             CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT))
4909       return NumOfMemOps * MemOpCost + Entry->Cost;
4910     //If an entry does not exist, fallback to the default implementation.
4911 
4912     // Kind of shuffle depends on number of loaded values.
4913     // If we load the entire data in one register, we can use a 1-src shuffle.
4914     // Otherwise, we'll merge 2 sources in each operation.
4915     TTI::ShuffleKind ShuffleKind =
4916         (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc;
4917 
4918     InstructionCost ShuffleCost =
4919         getShuffleCost(ShuffleKind, SingleMemOpTy, None, 0, nullptr);
4920 
4921     unsigned NumOfLoadsInInterleaveGrp =
4922         Indices.size() ? Indices.size() : Factor;
4923     auto *ResultTy = FixedVectorType::get(VecTy->getElementType(),
4924                                           VecTy->getNumElements() / Factor);
4925     InstructionCost NumOfResults =
4926         getTLI()->getTypeLegalizationCost(DL, ResultTy).first *
4927         NumOfLoadsInInterleaveGrp;
4928 
4929     // About a half of the loads may be folded in shuffles when we have only
4930     // one result. If we have more than one result, we do not fold loads at all.
4931     unsigned NumOfUnfoldedLoads =
4932         NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2;
4933 
4934     // Get a number of shuffle operations per result.
4935     unsigned NumOfShufflesPerResult =
4936         std::max((unsigned)1, (unsigned)(NumOfMemOps - 1));
4937 
4938     // The SK_MergeTwoSrc shuffle clobbers one of src operands.
4939     // When we have more than one destination, we need additional instructions
4940     // to keep sources.
4941     InstructionCost NumOfMoves = 0;
4942     if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc)
4943       NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2;
4944 
4945     InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost +
4946                            NumOfUnfoldedLoads * MemOpCost + NumOfMoves;
4947 
4948     return Cost;
4949   }
4950 
4951   // Store.
4952   assert(Opcode == Instruction::Store &&
4953          "Expected Store Instruction at this  point");
4954   // X86InterleavedAccess support only the following interleaved-access group.
4955   static const CostTblEntry AVX512InterleavedStoreTbl[] = {
4956       {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store)
4957       {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store)
4958       {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store)
4959 
4960       {4, MVT::v8i8, 10},  // interleave 4 x 8i8  into 32i8  (and store)
4961       {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8  (and store)
4962       {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store)
4963       {4, MVT::v64i8, 24}  // interleave 4 x 32i8 into 256i8 (and store)
4964   };
4965 
4966   if (const auto *Entry =
4967           CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT))
4968     return NumOfMemOps * MemOpCost + Entry->Cost;
4969   //If an entry does not exist, fallback to the default implementation.
4970 
4971   // There is no strided stores meanwhile. And store can't be folded in
4972   // shuffle.
4973   unsigned NumOfSources = Factor; // The number of values to be merged.
4974   InstructionCost ShuffleCost =
4975       getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, None, 0, nullptr);
4976   unsigned NumOfShufflesPerStore = NumOfSources - 1;
4977 
4978   // The SK_MergeTwoSrc shuffle clobbers one of src operands.
4979   // We need additional instructions to keep sources.
4980   unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2;
4981   InstructionCost Cost =
4982       NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) +
4983       NumOfMoves;
4984   return Cost;
4985 }
4986 
4987 InstructionCost X86TTIImpl::getInterleavedMemoryOpCost(
4988     unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
4989     Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
4990     bool UseMaskForCond, bool UseMaskForGaps) {
4991   auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) {
4992     Type *EltTy = cast<VectorType>(VecTy)->getElementType();
4993     if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) ||
4994         EltTy->isIntegerTy(32) || EltTy->isPointerTy())
4995       return true;
4996     if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8))
4997       return HasBW;
4998     return false;
4999   };
5000   if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI()))
5001     return getInterleavedMemoryOpCostAVX512(
5002         Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment,
5003         AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps);
5004   if (ST->hasAVX2())
5005     return getInterleavedMemoryOpCostAVX2(
5006         Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment,
5007         AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps);
5008 
5009   return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
5010                                            Alignment, AddressSpace, CostKind,
5011                                            UseMaskForCond, UseMaskForGaps);
5012 }
5013