1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// \file 10 /// This file implements a TargetTransformInfo analysis pass specific to the 11 /// X86 target machine. It uses the target's detailed information to provide 12 /// more precise answers to certain TTI queries, while letting the target 13 /// independent and default TTI implementations handle the rest. 14 /// 15 //===----------------------------------------------------------------------===// 16 /// About Cost Model numbers used below it's necessary to say the following: 17 /// the numbers correspond to some "generic" X86 CPU instead of usage of 18 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 19 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 20 /// the lookups below the cost is based on Nehalem as that was the first CPU 21 /// to support that feature level and thus has most likely the worst case cost. 22 /// Some examples of other technologies/CPUs: 23 /// SSE 3 - Pentium4 / Athlon64 24 /// SSE 4.1 - Penryn 25 /// SSE 4.2 - Nehalem 26 /// AVX - Sandy Bridge 27 /// AVX2 - Haswell 28 /// AVX-512 - Xeon Phi / Skylake 29 /// And some examples of instruction target dependent costs (latency) 30 /// divss sqrtss rsqrtss 31 /// AMD K7 11-16 19 3 32 /// Piledriver 9-24 13-15 5 33 /// Jaguar 14 16 2 34 /// Pentium II,III 18 30 2 35 /// Nehalem 7-14 7-18 3 36 /// Haswell 10-13 11 5 37 /// TODO: Develop and implement the target dependent cost model and 38 /// specialize cost numbers for different Cost Model Targets such as throughput, 39 /// code size, latency and uop count. 40 //===----------------------------------------------------------------------===// 41 42 #include "X86TargetTransformInfo.h" 43 #include "llvm/Analysis/TargetTransformInfo.h" 44 #include "llvm/CodeGen/BasicTTIImpl.h" 45 #include "llvm/CodeGen/CostTable.h" 46 #include "llvm/CodeGen/TargetLowering.h" 47 #include "llvm/IR/IntrinsicInst.h" 48 #include "llvm/Support/Debug.h" 49 50 using namespace llvm; 51 52 #define DEBUG_TYPE "x86tti" 53 54 //===----------------------------------------------------------------------===// 55 // 56 // X86 cost model. 57 // 58 //===----------------------------------------------------------------------===// 59 60 TargetTransformInfo::PopcntSupportKind 61 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 62 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 63 // TODO: Currently the __builtin_popcount() implementation using SSE3 64 // instructions is inefficient. Once the problem is fixed, we should 65 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 66 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 67 } 68 69 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 70 TargetTransformInfo::CacheLevel Level) const { 71 switch (Level) { 72 case TargetTransformInfo::CacheLevel::L1D: 73 // - Penryn 74 // - Nehalem 75 // - Westmere 76 // - Sandy Bridge 77 // - Ivy Bridge 78 // - Haswell 79 // - Broadwell 80 // - Skylake 81 // - Kabylake 82 return 32 * 1024; // 32 KByte 83 case TargetTransformInfo::CacheLevel::L2D: 84 // - Penryn 85 // - Nehalem 86 // - Westmere 87 // - Sandy Bridge 88 // - Ivy Bridge 89 // - Haswell 90 // - Broadwell 91 // - Skylake 92 // - Kabylake 93 return 256 * 1024; // 256 KByte 94 } 95 96 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 97 } 98 99 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 100 TargetTransformInfo::CacheLevel Level) const { 101 // - Penryn 102 // - Nehalem 103 // - Westmere 104 // - Sandy Bridge 105 // - Ivy Bridge 106 // - Haswell 107 // - Broadwell 108 // - Skylake 109 // - Kabylake 110 switch (Level) { 111 case TargetTransformInfo::CacheLevel::L1D: 112 LLVM_FALLTHROUGH; 113 case TargetTransformInfo::CacheLevel::L2D: 114 return 8; 115 } 116 117 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 118 } 119 120 unsigned X86TTIImpl::getNumberOfRegisters(bool Vector) { 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const { 133 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 134 if (Vector) { 135 if (ST->hasAVX512() && PreferVectorWidth >= 512) 136 return 512; 137 if (ST->hasAVX() && PreferVectorWidth >= 256) 138 return 256; 139 if (ST->hasSSE1() && PreferVectorWidth >= 128) 140 return 128; 141 return 0; 142 } 143 144 if (ST->is64Bit()) 145 return 64; 146 147 return 32; 148 } 149 150 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 151 return getRegisterBitWidth(true); 152 } 153 154 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 155 // If the loop will not be vectorized, don't interleave the loop. 156 // Let regular unroll to unroll the loop, which saves the overflow 157 // check and memory check cost. 158 if (VF == 1) 159 return 1; 160 161 if (ST->isAtom()) 162 return 1; 163 164 // Sandybridge and Haswell have multiple execution ports and pipelined 165 // vector units. 166 if (ST->hasAVX()) 167 return 4; 168 169 return 2; 170 } 171 172 int X86TTIImpl::getArithmeticInstrCost( 173 unsigned Opcode, Type *Ty, 174 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 175 TTI::OperandValueProperties Opd1PropInfo, 176 TTI::OperandValueProperties Opd2PropInfo, 177 ArrayRef<const Value *> Args) { 178 // Legalize the type. 179 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 180 181 int ISD = TLI->InstructionOpcodeToISD(Opcode); 182 assert(ISD && "Invalid opcode"); 183 184 static const CostTblEntry GLMCostTable[] = { 185 { ISD::FDIV, MVT::f32, 18 }, // divss 186 { ISD::FDIV, MVT::v4f32, 35 }, // divps 187 { ISD::FDIV, MVT::f64, 33 }, // divsd 188 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 189 }; 190 191 if (ST->isGLM()) 192 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 193 LT.second)) 194 return LT.first * Entry->Cost; 195 196 static const CostTblEntry SLMCostTable[] = { 197 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 198 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 199 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. 200 { ISD::FMUL, MVT::f64, 2 }, // mulsd 201 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 202 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 203 { ISD::FDIV, MVT::f32, 17 }, // divss 204 { ISD::FDIV, MVT::v4f32, 39 }, // divps 205 { ISD::FDIV, MVT::f64, 32 }, // divsd 206 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 207 { ISD::FADD, MVT::v2f64, 2 }, // addpd 208 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 209 // v2i64/v4i64 mul is custom lowered as a series of long: 210 // multiplies(3), shifts(3) and adds(2) 211 // slm muldq version throughput is 2 and addq throughput 4 212 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 213 // 3X4 (addq throughput) = 17 214 { ISD::MUL, MVT::v2i64, 17 }, 215 // slm addq\subq throughput is 4 216 { ISD::ADD, MVT::v2i64, 4 }, 217 { ISD::SUB, MVT::v2i64, 4 }, 218 }; 219 220 if (ST->isSLM()) { 221 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 222 // Check if the operands can be shrinked into a smaller datatype. 223 bool Op1Signed = false; 224 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 225 bool Op2Signed = false; 226 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 227 228 bool signedMode = Op1Signed | Op2Signed; 229 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 230 231 if (OpMinSize <= 7) 232 return LT.first * 3; // pmullw/sext 233 if (!signedMode && OpMinSize <= 8) 234 return LT.first * 3; // pmullw/zext 235 if (OpMinSize <= 15) 236 return LT.first * 5; // pmullw/pmulhw/pshuf 237 if (!signedMode && OpMinSize <= 16) 238 return LT.first * 5; // pmullw/pmulhw/pshuf 239 } 240 241 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 242 LT.second)) { 243 return LT.first * Entry->Cost; 244 } 245 } 246 247 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 248 ISD == ISD::UREM) && 249 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 250 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 251 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 252 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 253 // On X86, vector signed division by constants power-of-two are 254 // normally expanded to the sequence SRA + SRL + ADD + SRA. 255 // The OperandValue properties may not be the same as that of the previous 256 // operation; conservatively assume OP_None. 257 int Cost = 258 2 * getArithmeticInstrCost(Instruction::AShr, Ty, Op1Info, Op2Info, 259 TargetTransformInfo::OP_None, 260 TargetTransformInfo::OP_None); 261 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 262 TargetTransformInfo::OP_None, 263 TargetTransformInfo::OP_None); 264 Cost += getArithmeticInstrCost(Instruction::Add, Ty, Op1Info, Op2Info, 265 TargetTransformInfo::OP_None, 266 TargetTransformInfo::OP_None); 267 268 if (ISD == ISD::SREM) { 269 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 270 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info); 271 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, Op1Info, Op2Info); 272 } 273 274 return Cost; 275 } 276 277 // Vector unsigned division/remainder will be simplified to shifts/masks. 278 if (ISD == ISD::UDIV) 279 return getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 280 TargetTransformInfo::OP_None, 281 TargetTransformInfo::OP_None); 282 283 if (ISD == ISD::UREM) 284 return getArithmeticInstrCost(Instruction::And, Ty, Op1Info, Op2Info, 285 TargetTransformInfo::OP_None, 286 TargetTransformInfo::OP_None); 287 } 288 289 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 290 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 291 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 292 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 293 }; 294 295 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 296 ST->hasBWI()) { 297 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 298 LT.second)) 299 return LT.first * Entry->Cost; 300 } 301 302 static const CostTblEntry AVX512UniformConstCostTable[] = { 303 { ISD::SRA, MVT::v2i64, 1 }, 304 { ISD::SRA, MVT::v4i64, 1 }, 305 { ISD::SRA, MVT::v8i64, 1 }, 306 }; 307 308 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 309 ST->hasAVX512()) { 310 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 311 LT.second)) 312 return LT.first * Entry->Cost; 313 } 314 315 static const CostTblEntry AVX2UniformConstCostTable[] = { 316 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 317 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 318 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 319 320 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 321 }; 322 323 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 324 ST->hasAVX2()) { 325 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 326 LT.second)) 327 return LT.first * Entry->Cost; 328 } 329 330 static const CostTblEntry SSE2UniformConstCostTable[] = { 331 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 332 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 333 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 334 335 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 336 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 337 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 338 }; 339 340 // XOP has faster vXi8 shifts. 341 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 342 ST->hasSSE2() && !ST->hasXOP()) { 343 if (const auto *Entry = 344 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 345 return LT.first * Entry->Cost; 346 } 347 348 static const CostTblEntry AVX512BWConstCostTable[] = { 349 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 350 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 351 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 352 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 353 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 354 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 355 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 356 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 357 }; 358 359 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 360 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 361 ST->hasBWI()) { 362 if (const auto *Entry = 363 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 364 return LT.first * Entry->Cost; 365 } 366 367 static const CostTblEntry AVX512ConstCostTable[] = { 368 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 369 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 370 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 371 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 372 }; 373 374 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 375 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 376 ST->hasAVX512()) { 377 if (const auto *Entry = 378 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 379 return LT.first * Entry->Cost; 380 } 381 382 static const CostTblEntry AVX2ConstCostTable[] = { 383 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 384 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 385 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 386 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 387 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 388 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 389 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 390 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 391 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 392 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 393 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 394 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 395 }; 396 397 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 398 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 399 ST->hasAVX2()) { 400 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 401 return LT.first * Entry->Cost; 402 } 403 404 static const CostTblEntry SSE2ConstCostTable[] = { 405 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 406 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 407 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 408 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 409 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 410 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 411 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 412 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 413 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 414 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 415 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 416 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 417 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 418 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 419 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 420 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 421 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 422 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 423 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 424 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 425 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 426 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 427 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 428 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 429 }; 430 431 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 432 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 433 ST->hasSSE2()) { 434 // pmuldq sequence. 435 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 436 return LT.first * 32; 437 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 438 return LT.first * 38; 439 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 440 return LT.first * 15; 441 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 442 return LT.first * 20; 443 444 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 445 return LT.first * Entry->Cost; 446 } 447 448 static const CostTblEntry AVX2UniformCostTable[] = { 449 // Uniform splats are cheaper for the following instructions. 450 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 451 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 452 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 453 }; 454 455 if (ST->hasAVX2() && 456 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 457 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 458 if (const auto *Entry = 459 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 460 return LT.first * Entry->Cost; 461 } 462 463 static const CostTblEntry SSE2UniformCostTable[] = { 464 // Uniform splats are cheaper for the following instructions. 465 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 466 { ISD::SHL, MVT::v4i32, 1 }, // pslld 467 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 468 469 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 470 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 471 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 472 473 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 474 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 475 }; 476 477 if (ST->hasSSE2() && 478 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 479 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 480 if (const auto *Entry = 481 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 482 return LT.first * Entry->Cost; 483 } 484 485 static const CostTblEntry AVX512DQCostTable[] = { 486 { ISD::MUL, MVT::v2i64, 1 }, 487 { ISD::MUL, MVT::v4i64, 1 }, 488 { ISD::MUL, MVT::v8i64, 1 } 489 }; 490 491 // Look for AVX512DQ lowering tricks for custom cases. 492 if (ST->hasDQI()) 493 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 494 return LT.first * Entry->Cost; 495 496 static const CostTblEntry AVX512BWCostTable[] = { 497 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 498 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 499 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 500 501 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 502 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 503 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 504 505 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 506 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 507 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 508 509 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 510 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 511 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 512 513 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence. 514 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence. 515 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence. 516 }; 517 518 // Look for AVX512BW lowering tricks for custom cases. 519 if (ST->hasBWI()) 520 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 521 return LT.first * Entry->Cost; 522 523 static const CostTblEntry AVX512CostTable[] = { 524 { ISD::SHL, MVT::v16i32, 1 }, 525 { ISD::SRL, MVT::v16i32, 1 }, 526 { ISD::SRA, MVT::v16i32, 1 }, 527 528 { ISD::SHL, MVT::v8i64, 1 }, 529 { ISD::SRL, MVT::v8i64, 1 }, 530 531 { ISD::SRA, MVT::v2i64, 1 }, 532 { ISD::SRA, MVT::v4i64, 1 }, 533 { ISD::SRA, MVT::v8i64, 1 }, 534 535 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence. 536 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence. 537 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 538 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 539 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 540 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add 541 542 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 543 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 544 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 545 546 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 547 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 548 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 549 }; 550 551 if (ST->hasAVX512()) 552 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 553 return LT.first * Entry->Cost; 554 555 static const CostTblEntry AVX2ShiftCostTable[] = { 556 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 557 // customize them to detect the cases where shift amount is a scalar one. 558 { ISD::SHL, MVT::v4i32, 1 }, 559 { ISD::SRL, MVT::v4i32, 1 }, 560 { ISD::SRA, MVT::v4i32, 1 }, 561 { ISD::SHL, MVT::v8i32, 1 }, 562 { ISD::SRL, MVT::v8i32, 1 }, 563 { ISD::SRA, MVT::v8i32, 1 }, 564 { ISD::SHL, MVT::v2i64, 1 }, 565 { ISD::SRL, MVT::v2i64, 1 }, 566 { ISD::SHL, MVT::v4i64, 1 }, 567 { ISD::SRL, MVT::v4i64, 1 }, 568 }; 569 570 // Look for AVX2 lowering tricks. 571 if (ST->hasAVX2()) { 572 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 573 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 574 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 575 // On AVX2, a packed v16i16 shift left by a constant build_vector 576 // is lowered into a vector multiply (vpmullw). 577 return getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info, 578 TargetTransformInfo::OP_None, 579 TargetTransformInfo::OP_None); 580 581 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 582 return LT.first * Entry->Cost; 583 } 584 585 static const CostTblEntry XOPShiftCostTable[] = { 586 // 128bit shifts take 1cy, but right shifts require negation beforehand. 587 { ISD::SHL, MVT::v16i8, 1 }, 588 { ISD::SRL, MVT::v16i8, 2 }, 589 { ISD::SRA, MVT::v16i8, 2 }, 590 { ISD::SHL, MVT::v8i16, 1 }, 591 { ISD::SRL, MVT::v8i16, 2 }, 592 { ISD::SRA, MVT::v8i16, 2 }, 593 { ISD::SHL, MVT::v4i32, 1 }, 594 { ISD::SRL, MVT::v4i32, 2 }, 595 { ISD::SRA, MVT::v4i32, 2 }, 596 { ISD::SHL, MVT::v2i64, 1 }, 597 { ISD::SRL, MVT::v2i64, 2 }, 598 { ISD::SRA, MVT::v2i64, 2 }, 599 // 256bit shifts require splitting if AVX2 didn't catch them above. 600 { ISD::SHL, MVT::v32i8, 2+2 }, 601 { ISD::SRL, MVT::v32i8, 4+2 }, 602 { ISD::SRA, MVT::v32i8, 4+2 }, 603 { ISD::SHL, MVT::v16i16, 2+2 }, 604 { ISD::SRL, MVT::v16i16, 4+2 }, 605 { ISD::SRA, MVT::v16i16, 4+2 }, 606 { ISD::SHL, MVT::v8i32, 2+2 }, 607 { ISD::SRL, MVT::v8i32, 4+2 }, 608 { ISD::SRA, MVT::v8i32, 4+2 }, 609 { ISD::SHL, MVT::v4i64, 2+2 }, 610 { ISD::SRL, MVT::v4i64, 4+2 }, 611 { ISD::SRA, MVT::v4i64, 4+2 }, 612 }; 613 614 // Look for XOP lowering tricks. 615 if (ST->hasXOP()) { 616 // If the right shift is constant then we'll fold the negation so 617 // it's as cheap as a left shift. 618 int ShiftISD = ISD; 619 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 620 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 621 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 622 ShiftISD = ISD::SHL; 623 if (const auto *Entry = 624 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 625 return LT.first * Entry->Cost; 626 } 627 628 static const CostTblEntry SSE2UniformShiftCostTable[] = { 629 // Uniform splats are cheaper for the following instructions. 630 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 631 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 632 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 633 634 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 635 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 636 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 637 638 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 639 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 640 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 641 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 642 }; 643 644 if (ST->hasSSE2() && 645 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 646 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 647 648 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 649 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 650 return LT.first * 4; // 2*psrad + shuffle. 651 652 if (const auto *Entry = 653 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 654 return LT.first * Entry->Cost; 655 } 656 657 if (ISD == ISD::SHL && 658 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 659 MVT VT = LT.second; 660 // Vector shift left by non uniform constant can be lowered 661 // into vector multiply. 662 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 663 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 664 ISD = ISD::MUL; 665 } 666 667 static const CostTblEntry AVX2CostTable[] = { 668 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. 669 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 670 671 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. 672 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 673 674 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. 675 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. 676 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. 677 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 678 679 { ISD::SUB, MVT::v32i8, 1 }, // psubb 680 { ISD::ADD, MVT::v32i8, 1 }, // paddb 681 { ISD::SUB, MVT::v16i16, 1 }, // psubw 682 { ISD::ADD, MVT::v16i16, 1 }, // paddw 683 { ISD::SUB, MVT::v8i32, 1 }, // psubd 684 { ISD::ADD, MVT::v8i32, 1 }, // paddd 685 { ISD::SUB, MVT::v4i64, 1 }, // psubq 686 { ISD::ADD, MVT::v4i64, 1 }, // paddq 687 688 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence. 689 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence. 690 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 691 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 692 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add 693 694 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 695 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 696 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 697 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 698 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 699 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 700 701 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 702 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 703 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 704 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 705 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 706 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 707 }; 708 709 // Look for AVX2 lowering tricks for custom cases. 710 if (ST->hasAVX2()) 711 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 712 return LT.first * Entry->Cost; 713 714 static const CostTblEntry AVX1CostTable[] = { 715 // We don't have to scalarize unsupported ops. We can issue two half-sized 716 // operations and we only need to extract the upper YMM half. 717 // Two ops + 1 extract + 1 insert = 4. 718 { ISD::MUL, MVT::v16i16, 4 }, 719 { ISD::MUL, MVT::v8i32, 4 }, 720 { ISD::SUB, MVT::v32i8, 4 }, 721 { ISD::ADD, MVT::v32i8, 4 }, 722 { ISD::SUB, MVT::v16i16, 4 }, 723 { ISD::ADD, MVT::v16i16, 4 }, 724 { ISD::SUB, MVT::v8i32, 4 }, 725 { ISD::ADD, MVT::v8i32, 4 }, 726 { ISD::SUB, MVT::v4i64, 4 }, 727 { ISD::ADD, MVT::v4i64, 4 }, 728 729 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 730 // are lowered as a series of long multiplies(3), shifts(3) and adds(2) 731 // Because we believe v4i64 to be a legal type, we must also include the 732 // extract+insert in the cost table. Therefore, the cost here is 18 733 // instead of 8. 734 { ISD::MUL, MVT::v4i64, 18 }, 735 736 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence. 737 738 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 739 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 740 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 741 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 742 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 743 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 744 }; 745 746 if (ST->hasAVX()) 747 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 748 return LT.first * Entry->Cost; 749 750 static const CostTblEntry SSE42CostTable[] = { 751 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 752 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 753 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 754 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 755 756 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 757 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 758 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 759 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 760 761 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 762 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 763 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 764 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 765 766 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 767 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 768 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 769 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 770 }; 771 772 if (ST->hasSSE42()) 773 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 774 return LT.first * Entry->Cost; 775 776 static const CostTblEntry SSE41CostTable[] = { 777 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 778 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split. 779 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 780 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 781 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 782 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split 783 784 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 785 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split. 786 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 787 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 788 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 789 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split. 790 791 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 792 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split. 793 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 794 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 795 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 796 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split. 797 798 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 799 }; 800 801 if (ST->hasSSE41()) 802 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 803 return LT.first * Entry->Cost; 804 805 static const CostTblEntry SSE2CostTable[] = { 806 // We don't correctly identify costs of casts because they are marked as 807 // custom. 808 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 809 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 810 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 811 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 812 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 813 814 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 815 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 816 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 817 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 818 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 819 820 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 821 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 822 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 823 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 824 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split. 825 826 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence. 827 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 828 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 829 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 830 831 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 832 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 833 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 834 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 835 }; 836 837 if (ST->hasSSE2()) 838 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 839 return LT.first * Entry->Cost; 840 841 static const CostTblEntry SSE1CostTable[] = { 842 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 843 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 844 }; 845 846 if (ST->hasSSE1()) 847 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 848 return LT.first * Entry->Cost; 849 850 // It is not a good idea to vectorize division. We have to scalarize it and 851 // in the process we will often end up having to spilling regular 852 // registers. The overhead of division is going to dominate most kernels 853 // anyways so try hard to prevent vectorization of division - it is 854 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 855 // to hide "20 cycles" for each lane. 856 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 857 ISD == ISD::UDIV || ISD == ISD::UREM)) { 858 int ScalarCost = getArithmeticInstrCost( 859 Opcode, Ty->getScalarType(), Op1Info, Op2Info, 860 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 861 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 862 } 863 864 // Fallback to the default implementation. 865 return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info); 866 } 867 868 int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, 869 Type *SubTp) { 870 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 871 // 64-bit packed integer vectors (v2i32) are promoted to type v2i64. 872 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp); 873 874 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 875 if (Kind == TTI::SK_Transpose) 876 Kind = TTI::SK_PermuteTwoSrc; 877 878 // For Broadcasts we are splatting the first element from the first input 879 // register, so only need to reference that input and all the output 880 // registers are the same. 881 if (Kind == TTI::SK_Broadcast) 882 LT.first = 1; 883 884 // Subvector extractions are free if they start at the beginning of a 885 // vector and cheap if the subvectors are aligned. 886 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 887 int NumElts = LT.second.getVectorNumElements(); 888 if ((Index % NumElts) == 0) 889 return 0; 890 std::pair<int, MVT> SubLT = TLI->getTypeLegalizationCost(DL, SubTp); 891 if (SubLT.second.isVector()) { 892 int NumSubElts = SubLT.second.getVectorNumElements(); 893 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 894 return SubLT.first; 895 } 896 } 897 898 // We are going to permute multiple sources and the result will be in multiple 899 // destinations. Providing an accurate cost only for splits where the element 900 // type remains the same. 901 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 902 MVT LegalVT = LT.second; 903 if (LegalVT.isVector() && 904 LegalVT.getVectorElementType().getSizeInBits() == 905 Tp->getVectorElementType()->getPrimitiveSizeInBits() && 906 LegalVT.getVectorNumElements() < Tp->getVectorNumElements()) { 907 908 unsigned VecTySize = DL.getTypeStoreSize(Tp); 909 unsigned LegalVTSize = LegalVT.getStoreSize(); 910 // Number of source vectors after legalization: 911 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 912 // Number of destination vectors after legalization: 913 unsigned NumOfDests = LT.first; 914 915 Type *SingleOpTy = VectorType::get(Tp->getVectorElementType(), 916 LegalVT.getVectorNumElements()); 917 918 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 919 return NumOfShuffles * 920 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 0, nullptr); 921 } 922 923 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 924 } 925 926 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 927 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 928 // We assume that source and destination have the same vector type. 929 int NumOfDests = LT.first; 930 int NumOfShufflesPerDest = LT.first * 2 - 1; 931 LT.first = NumOfDests * NumOfShufflesPerDest; 932 } 933 934 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 935 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 936 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 937 938 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 939 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 940 941 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 1}, // vpermt2b 942 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 1}, // vpermt2b 943 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1} // vpermt2b 944 }; 945 946 if (ST->hasVBMI()) 947 if (const auto *Entry = 948 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 949 return LT.first * Entry->Cost; 950 951 static const CostTblEntry AVX512BWShuffleTbl[] = { 952 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 953 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 954 955 {TTI::SK_Reverse, MVT::v32i16, 1}, // vpermw 956 {TTI::SK_Reverse, MVT::v16i16, 1}, // vpermw 957 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 958 959 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 1}, // vpermw 960 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 1}, // vpermw 961 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // vpermw 962 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 963 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 3}, // vpermw + zext/trunc 964 965 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 1}, // vpermt2w 966 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 1}, // vpermt2w 967 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpermt2w 968 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 3}, // zext + vpermt2w + trunc 969 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 970 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3} // zext + vpermt2w + trunc 971 }; 972 973 if (ST->hasBWI()) 974 if (const auto *Entry = 975 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 976 return LT.first * Entry->Cost; 977 978 static const CostTblEntry AVX512ShuffleTbl[] = { 979 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 980 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 981 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 982 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 983 984 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 985 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 986 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 987 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 988 989 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 990 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 991 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 992 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 993 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 994 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 995 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 996 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 997 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 998 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 999 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1000 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1001 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1002 1003 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1004 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1005 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1006 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1007 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1008 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1009 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1010 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1011 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1012 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1013 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1014 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1} // vpermt2d 1015 }; 1016 1017 if (ST->hasAVX512()) 1018 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1019 return LT.first * Entry->Cost; 1020 1021 static const CostTblEntry AVX2ShuffleTbl[] = { 1022 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1023 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1024 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1025 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1026 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1027 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1028 1029 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1030 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1031 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1032 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1033 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1034 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1035 1036 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1037 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1038 1039 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1040 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1041 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1042 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1043 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1044 // + vpblendvb 1045 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1046 // + vpblendvb 1047 1048 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1049 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1050 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1051 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1052 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1053 // + vpblendvb 1054 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1055 // + vpblendvb 1056 }; 1057 1058 if (ST->hasAVX2()) 1059 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1060 return LT.first * Entry->Cost; 1061 1062 static const CostTblEntry XOPShuffleTbl[] = { 1063 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1064 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1065 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1066 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1067 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1068 // + vinsertf128 1069 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1070 // + vinsertf128 1071 1072 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1073 // + vinsertf128 1074 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1075 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1076 // + vinsertf128 1077 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1078 }; 1079 1080 if (ST->hasXOP()) 1081 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1082 return LT.first * Entry->Cost; 1083 1084 static const CostTblEntry AVX1ShuffleTbl[] = { 1085 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1086 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1087 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1088 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1089 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1090 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1091 1092 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1093 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1094 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1095 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1096 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1097 // + vinsertf128 1098 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1099 // + vinsertf128 1100 1101 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1102 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1103 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1104 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1105 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1106 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1107 1108 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1109 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1110 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1111 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1112 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1113 // + 2*por + vinsertf128 1114 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1115 // + 2*por + vinsertf128 1116 1117 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1118 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1119 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1120 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1121 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1122 // + 4*por + vinsertf128 1123 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1124 // + 4*por + vinsertf128 1125 }; 1126 1127 if (ST->hasAVX()) 1128 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1129 return LT.first * Entry->Cost; 1130 1131 static const CostTblEntry SSE41ShuffleTbl[] = { 1132 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1133 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1134 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1135 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1136 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1137 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1138 }; 1139 1140 if (ST->hasSSE41()) 1141 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1142 return LT.first * Entry->Cost; 1143 1144 static const CostTblEntry SSSE3ShuffleTbl[] = { 1145 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1146 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1147 1148 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1149 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1150 1151 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1152 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1153 1154 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1155 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1156 1157 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1158 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1159 }; 1160 1161 if (ST->hasSSSE3()) 1162 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1163 return LT.first * Entry->Cost; 1164 1165 static const CostTblEntry SSE2ShuffleTbl[] = { 1166 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1167 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1168 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1169 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1170 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1171 1172 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1173 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1174 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1175 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1176 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1177 // + 2*pshufd + 2*unpck + packus 1178 1179 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1180 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1181 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1182 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1183 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1184 1185 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1186 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1187 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1188 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1189 // + pshufd/unpck 1190 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1191 // + 2*pshufd + 2*unpck + 2*packus 1192 1193 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1194 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1195 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1196 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1197 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1198 }; 1199 1200 if (ST->hasSSE2()) 1201 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1202 return LT.first * Entry->Cost; 1203 1204 static const CostTblEntry SSE1ShuffleTbl[] = { 1205 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1206 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1207 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1208 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1209 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1210 }; 1211 1212 if (ST->hasSSE1()) 1213 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1214 return LT.first * Entry->Cost; 1215 1216 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 1217 } 1218 1219 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 1220 const Instruction *I) { 1221 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1222 assert(ISD && "Invalid opcode"); 1223 1224 // FIXME: Need a better design of the cost table to handle non-simple types of 1225 // potential massive combinations (elem_num x src_type x dst_type). 1226 1227 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1228 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1229 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1230 1231 // Mask sign extend has an instruction. 1232 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1233 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1234 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1235 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1236 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1237 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1238 1239 // Mask zero extend is a load + broadcast. 1240 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1241 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1242 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1243 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1244 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1245 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1246 }; 1247 1248 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1249 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1250 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1251 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1252 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1253 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1254 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1255 1256 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1257 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1258 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1259 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1260 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1261 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1262 1263 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1264 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1265 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1266 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1267 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1268 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1269 1270 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1271 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1272 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1273 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1274 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1275 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1276 }; 1277 1278 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1279 // 256-bit wide vectors. 1280 1281 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1282 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1283 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1284 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1285 1286 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 }, 1287 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 }, 1288 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 }, 1289 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 1290 1291 // v16i1 -> v16i32 - load + broadcast 1292 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1293 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1294 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1295 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1296 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1297 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1298 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1299 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1300 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1301 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1302 1303 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1304 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1305 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1306 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1307 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1308 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1309 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1310 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1311 1312 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1313 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1314 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1315 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1316 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1317 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1318 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1319 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1320 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1321 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1322 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1323 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1324 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1325 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1326 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1327 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1328 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1329 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1330 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1331 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1332 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1333 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1334 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1335 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1336 1337 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1338 1339 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1340 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1341 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1342 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1343 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 2 }, 1344 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 2 }, 1345 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1346 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 2 }, 1347 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 2 }, 1348 }; 1349 1350 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1351 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1352 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1353 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1354 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1355 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 1356 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 1357 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 1358 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 1359 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1360 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1361 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1362 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1363 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1364 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1365 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1366 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1367 1368 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 1369 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 1370 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1371 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 1372 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1373 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 }, 1374 1375 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1376 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1377 1378 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1379 }; 1380 1381 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1382 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1383 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1384 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1385 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1386 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 }, 1387 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1388 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 7 }, 1389 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1390 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1391 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1392 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 }, 1393 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1394 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1395 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1396 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1397 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1398 1399 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 1400 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1401 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1402 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1403 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 1404 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 }, 1405 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 }, 1406 1407 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1408 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1409 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1410 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1411 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1412 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1413 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1414 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1415 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1416 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1417 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1418 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1419 1420 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1421 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1422 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1423 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1424 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1425 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1426 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1427 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1428 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1429 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 }, 1430 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 1431 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1432 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 1433 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1434 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1435 // The generic code to compute the scalar overhead is currently broken. 1436 // Workaround this limitation by estimating the scalarization overhead 1437 // here. We have roughly 10 instructions per scalar element. 1438 // Multiply that by the vector width. 1439 // FIXME: remove that when PR19268 is fixed. 1440 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1441 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1442 1443 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 }, 1444 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 }, 1445 // This node is expanded into scalarized operations but BasicTTI is overly 1446 // optimistic estimating its cost. It computes 3 per element (one 1447 // vector-extract, one scalar conversion and one vector-insert). The 1448 // problem is that the inserts form a read-modify-write chain so latency 1449 // should be factored in too. Inflating the cost per element by 1. 1450 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, 1451 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 1452 1453 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 1454 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 1455 }; 1456 1457 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 1458 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1459 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1460 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1461 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1462 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1463 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1464 1465 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1466 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 }, 1467 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1468 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1469 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1470 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1471 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1472 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1473 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1474 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1475 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1476 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1477 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1478 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1479 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1480 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1481 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1482 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1483 1484 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, 1485 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 1486 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 1487 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 1488 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 1489 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 1490 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 1491 1492 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 1493 }; 1494 1495 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 1496 // These are somewhat magic numbers justified by looking at the output of 1497 // Intel's IACA, running some kernels and making sure when we take 1498 // legalization into account the throughput will be overestimated. 1499 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1500 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1501 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1502 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1503 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1504 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1505 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1506 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 1507 1508 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1509 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1510 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1511 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1512 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1513 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, 1514 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 }, 1515 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1516 1517 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 3 }, 1518 1519 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 }, 1520 1521 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1522 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 1523 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 1524 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 1525 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1526 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 1527 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1528 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 1529 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1530 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1531 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1532 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1533 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 1534 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 1535 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1536 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 1537 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1538 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 1539 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1540 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1541 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 1542 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 1543 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1544 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 1545 1546 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 4 }, 1547 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, 1548 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 1549 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 1550 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 1551 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1552 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 1553 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1554 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 1555 }; 1556 1557 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 1558 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst); 1559 1560 if (ST->hasSSE2() && !ST->hasAVX()) { 1561 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1562 LTDest.second, LTSrc.second)) 1563 return LTSrc.first * Entry->Cost; 1564 } 1565 1566 EVT SrcTy = TLI->getValueType(DL, Src); 1567 EVT DstTy = TLI->getValueType(DL, Dst); 1568 1569 // The function getSimpleVT only handles simple value types. 1570 if (!SrcTy.isSimple() || !DstTy.isSimple()) 1571 return BaseT::getCastInstrCost(Opcode, Dst, Src); 1572 1573 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 1574 MVT SimpleDstTy = DstTy.getSimpleVT(); 1575 1576 // Make sure that neither type is going to be split before using the 1577 // AVX512 tables. This handles -mprefer-vector-width=256 1578 // with -min-legal-vector-width<=256 1579 if (TLI->getTypeAction(SimpleSrcTy) != TargetLowering::TypeSplitVector && 1580 TLI->getTypeAction(SimpleDstTy) != TargetLowering::TypeSplitVector) { 1581 if (ST->hasBWI()) 1582 if (const auto *Entry = ConvertCostTableLookup(AVX512BWConversionTbl, ISD, 1583 SimpleDstTy, SimpleSrcTy)) 1584 return Entry->Cost; 1585 1586 if (ST->hasDQI()) 1587 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 1588 SimpleDstTy, SimpleSrcTy)) 1589 return Entry->Cost; 1590 1591 if (ST->hasAVX512()) 1592 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 1593 SimpleDstTy, SimpleSrcTy)) 1594 return Entry->Cost; 1595 } 1596 1597 if (ST->hasAVX2()) { 1598 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 1599 SimpleDstTy, SimpleSrcTy)) 1600 return Entry->Cost; 1601 } 1602 1603 if (ST->hasAVX()) { 1604 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 1605 SimpleDstTy, SimpleSrcTy)) 1606 return Entry->Cost; 1607 } 1608 1609 if (ST->hasSSE41()) { 1610 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 1611 SimpleDstTy, SimpleSrcTy)) 1612 return Entry->Cost; 1613 } 1614 1615 if (ST->hasSSE2()) { 1616 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1617 SimpleDstTy, SimpleSrcTy)) 1618 return Entry->Cost; 1619 } 1620 1621 return BaseT::getCastInstrCost(Opcode, Dst, Src, I); 1622 } 1623 1624 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 1625 const Instruction *I) { 1626 // Legalize the type. 1627 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 1628 1629 MVT MTy = LT.second; 1630 1631 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1632 assert(ISD && "Invalid opcode"); 1633 1634 static const CostTblEntry SSE2CostTbl[] = { 1635 { ISD::SETCC, MVT::v2i64, 8 }, 1636 { ISD::SETCC, MVT::v4i32, 1 }, 1637 { ISD::SETCC, MVT::v8i16, 1 }, 1638 { ISD::SETCC, MVT::v16i8, 1 }, 1639 }; 1640 1641 static const CostTblEntry SSE42CostTbl[] = { 1642 { ISD::SETCC, MVT::v2f64, 1 }, 1643 { ISD::SETCC, MVT::v4f32, 1 }, 1644 { ISD::SETCC, MVT::v2i64, 1 }, 1645 }; 1646 1647 static const CostTblEntry AVX1CostTbl[] = { 1648 { ISD::SETCC, MVT::v4f64, 1 }, 1649 { ISD::SETCC, MVT::v8f32, 1 }, 1650 // AVX1 does not support 8-wide integer compare. 1651 { ISD::SETCC, MVT::v4i64, 4 }, 1652 { ISD::SETCC, MVT::v8i32, 4 }, 1653 { ISD::SETCC, MVT::v16i16, 4 }, 1654 { ISD::SETCC, MVT::v32i8, 4 }, 1655 }; 1656 1657 static const CostTblEntry AVX2CostTbl[] = { 1658 { ISD::SETCC, MVT::v4i64, 1 }, 1659 { ISD::SETCC, MVT::v8i32, 1 }, 1660 { ISD::SETCC, MVT::v16i16, 1 }, 1661 { ISD::SETCC, MVT::v32i8, 1 }, 1662 }; 1663 1664 static const CostTblEntry AVX512CostTbl[] = { 1665 { ISD::SETCC, MVT::v8i64, 1 }, 1666 { ISD::SETCC, MVT::v16i32, 1 }, 1667 { ISD::SETCC, MVT::v8f64, 1 }, 1668 { ISD::SETCC, MVT::v16f32, 1 }, 1669 }; 1670 1671 static const CostTblEntry AVX512BWCostTbl[] = { 1672 { ISD::SETCC, MVT::v32i16, 1 }, 1673 { ISD::SETCC, MVT::v64i8, 1 }, 1674 }; 1675 1676 if (ST->hasBWI()) 1677 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 1678 return LT.first * Entry->Cost; 1679 1680 if (ST->hasAVX512()) 1681 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 1682 return LT.first * Entry->Cost; 1683 1684 if (ST->hasAVX2()) 1685 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 1686 return LT.first * Entry->Cost; 1687 1688 if (ST->hasAVX()) 1689 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 1690 return LT.first * Entry->Cost; 1691 1692 if (ST->hasSSE42()) 1693 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 1694 return LT.first * Entry->Cost; 1695 1696 if (ST->hasSSE2()) 1697 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 1698 return LT.first * Entry->Cost; 1699 1700 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I); 1701 } 1702 1703 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 1704 1705 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 1706 ArrayRef<Type *> Tys, FastMathFlags FMF, 1707 unsigned ScalarizationCostPassed) { 1708 // Costs should match the codegen from: 1709 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 1710 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 1711 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 1712 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 1713 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 1714 static const CostTblEntry AVX512CDCostTbl[] = { 1715 { ISD::CTLZ, MVT::v8i64, 1 }, 1716 { ISD::CTLZ, MVT::v16i32, 1 }, 1717 { ISD::CTLZ, MVT::v32i16, 8 }, 1718 { ISD::CTLZ, MVT::v64i8, 20 }, 1719 { ISD::CTLZ, MVT::v4i64, 1 }, 1720 { ISD::CTLZ, MVT::v8i32, 1 }, 1721 { ISD::CTLZ, MVT::v16i16, 4 }, 1722 { ISD::CTLZ, MVT::v32i8, 10 }, 1723 { ISD::CTLZ, MVT::v2i64, 1 }, 1724 { ISD::CTLZ, MVT::v4i32, 1 }, 1725 { ISD::CTLZ, MVT::v8i16, 4 }, 1726 { ISD::CTLZ, MVT::v16i8, 4 }, 1727 }; 1728 static const CostTblEntry AVX512BWCostTbl[] = { 1729 { ISD::BITREVERSE, MVT::v8i64, 5 }, 1730 { ISD::BITREVERSE, MVT::v16i32, 5 }, 1731 { ISD::BITREVERSE, MVT::v32i16, 5 }, 1732 { ISD::BITREVERSE, MVT::v64i8, 5 }, 1733 { ISD::CTLZ, MVT::v8i64, 23 }, 1734 { ISD::CTLZ, MVT::v16i32, 22 }, 1735 { ISD::CTLZ, MVT::v32i16, 18 }, 1736 { ISD::CTLZ, MVT::v64i8, 17 }, 1737 { ISD::CTPOP, MVT::v8i64, 7 }, 1738 { ISD::CTPOP, MVT::v16i32, 11 }, 1739 { ISD::CTPOP, MVT::v32i16, 9 }, 1740 { ISD::CTPOP, MVT::v64i8, 6 }, 1741 { ISD::CTTZ, MVT::v8i64, 10 }, 1742 { ISD::CTTZ, MVT::v16i32, 14 }, 1743 { ISD::CTTZ, MVT::v32i16, 12 }, 1744 { ISD::CTTZ, MVT::v64i8, 9 }, 1745 { ISD::SADDSAT, MVT::v32i16, 1 }, 1746 { ISD::SADDSAT, MVT::v64i8, 1 }, 1747 { ISD::SSUBSAT, MVT::v32i16, 1 }, 1748 { ISD::SSUBSAT, MVT::v64i8, 1 }, 1749 { ISD::UADDSAT, MVT::v32i16, 1 }, 1750 { ISD::UADDSAT, MVT::v64i8, 1 }, 1751 { ISD::USUBSAT, MVT::v32i16, 1 }, 1752 { ISD::USUBSAT, MVT::v64i8, 1 }, 1753 }; 1754 static const CostTblEntry AVX512CostTbl[] = { 1755 { ISD::BITREVERSE, MVT::v8i64, 36 }, 1756 { ISD::BITREVERSE, MVT::v16i32, 24 }, 1757 { ISD::CTLZ, MVT::v8i64, 29 }, 1758 { ISD::CTLZ, MVT::v16i32, 35 }, 1759 { ISD::CTPOP, MVT::v8i64, 16 }, 1760 { ISD::CTPOP, MVT::v16i32, 24 }, 1761 { ISD::CTTZ, MVT::v8i64, 20 }, 1762 { ISD::CTTZ, MVT::v16i32, 28 }, 1763 }; 1764 static const CostTblEntry XOPCostTbl[] = { 1765 { ISD::BITREVERSE, MVT::v4i64, 4 }, 1766 { ISD::BITREVERSE, MVT::v8i32, 4 }, 1767 { ISD::BITREVERSE, MVT::v16i16, 4 }, 1768 { ISD::BITREVERSE, MVT::v32i8, 4 }, 1769 { ISD::BITREVERSE, MVT::v2i64, 1 }, 1770 { ISD::BITREVERSE, MVT::v4i32, 1 }, 1771 { ISD::BITREVERSE, MVT::v8i16, 1 }, 1772 { ISD::BITREVERSE, MVT::v16i8, 1 }, 1773 { ISD::BITREVERSE, MVT::i64, 3 }, 1774 { ISD::BITREVERSE, MVT::i32, 3 }, 1775 { ISD::BITREVERSE, MVT::i16, 3 }, 1776 { ISD::BITREVERSE, MVT::i8, 3 } 1777 }; 1778 static const CostTblEntry AVX2CostTbl[] = { 1779 { ISD::BITREVERSE, MVT::v4i64, 5 }, 1780 { ISD::BITREVERSE, MVT::v8i32, 5 }, 1781 { ISD::BITREVERSE, MVT::v16i16, 5 }, 1782 { ISD::BITREVERSE, MVT::v32i8, 5 }, 1783 { ISD::BSWAP, MVT::v4i64, 1 }, 1784 { ISD::BSWAP, MVT::v8i32, 1 }, 1785 { ISD::BSWAP, MVT::v16i16, 1 }, 1786 { ISD::CTLZ, MVT::v4i64, 23 }, 1787 { ISD::CTLZ, MVT::v8i32, 18 }, 1788 { ISD::CTLZ, MVT::v16i16, 14 }, 1789 { ISD::CTLZ, MVT::v32i8, 9 }, 1790 { ISD::CTPOP, MVT::v4i64, 7 }, 1791 { ISD::CTPOP, MVT::v8i32, 11 }, 1792 { ISD::CTPOP, MVT::v16i16, 9 }, 1793 { ISD::CTPOP, MVT::v32i8, 6 }, 1794 { ISD::CTTZ, MVT::v4i64, 10 }, 1795 { ISD::CTTZ, MVT::v8i32, 14 }, 1796 { ISD::CTTZ, MVT::v16i16, 12 }, 1797 { ISD::CTTZ, MVT::v32i8, 9 }, 1798 { ISD::SADDSAT, MVT::v16i16, 1 }, 1799 { ISD::SADDSAT, MVT::v32i8, 1 }, 1800 { ISD::SSUBSAT, MVT::v16i16, 1 }, 1801 { ISD::SSUBSAT, MVT::v32i8, 1 }, 1802 { ISD::UADDSAT, MVT::v16i16, 1 }, 1803 { ISD::UADDSAT, MVT::v32i8, 1 }, 1804 { ISD::USUBSAT, MVT::v16i16, 1 }, 1805 { ISD::USUBSAT, MVT::v32i8, 1 }, 1806 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 1807 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 1808 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 1809 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 1810 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 1811 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 1812 }; 1813 static const CostTblEntry AVX1CostTbl[] = { 1814 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 1815 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 1816 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 1817 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 1818 { ISD::BSWAP, MVT::v4i64, 4 }, 1819 { ISD::BSWAP, MVT::v8i32, 4 }, 1820 { ISD::BSWAP, MVT::v16i16, 4 }, 1821 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 1822 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 1823 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 1824 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 1825 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 1826 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 1827 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 1828 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 1829 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 1830 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 1831 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 1832 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 1833 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 1834 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 1835 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 1836 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 1837 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 1838 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 1839 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 1840 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 1841 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 1842 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 1843 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 1844 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 1845 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 1846 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 1847 }; 1848 static const CostTblEntry GLMCostTbl[] = { 1849 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 1850 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 1851 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 1852 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 1853 }; 1854 static const CostTblEntry SLMCostTbl[] = { 1855 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 1856 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 1857 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 1858 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 1859 }; 1860 static const CostTblEntry SSE42CostTbl[] = { 1861 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 1862 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 1863 }; 1864 static const CostTblEntry SSSE3CostTbl[] = { 1865 { ISD::BITREVERSE, MVT::v2i64, 5 }, 1866 { ISD::BITREVERSE, MVT::v4i32, 5 }, 1867 { ISD::BITREVERSE, MVT::v8i16, 5 }, 1868 { ISD::BITREVERSE, MVT::v16i8, 5 }, 1869 { ISD::BSWAP, MVT::v2i64, 1 }, 1870 { ISD::BSWAP, MVT::v4i32, 1 }, 1871 { ISD::BSWAP, MVT::v8i16, 1 }, 1872 { ISD::CTLZ, MVT::v2i64, 23 }, 1873 { ISD::CTLZ, MVT::v4i32, 18 }, 1874 { ISD::CTLZ, MVT::v8i16, 14 }, 1875 { ISD::CTLZ, MVT::v16i8, 9 }, 1876 { ISD::CTPOP, MVT::v2i64, 7 }, 1877 { ISD::CTPOP, MVT::v4i32, 11 }, 1878 { ISD::CTPOP, MVT::v8i16, 9 }, 1879 { ISD::CTPOP, MVT::v16i8, 6 }, 1880 { ISD::CTTZ, MVT::v2i64, 10 }, 1881 { ISD::CTTZ, MVT::v4i32, 14 }, 1882 { ISD::CTTZ, MVT::v8i16, 12 }, 1883 { ISD::CTTZ, MVT::v16i8, 9 } 1884 }; 1885 static const CostTblEntry SSE2CostTbl[] = { 1886 { ISD::BITREVERSE, MVT::v2i64, 29 }, 1887 { ISD::BITREVERSE, MVT::v4i32, 27 }, 1888 { ISD::BITREVERSE, MVT::v8i16, 27 }, 1889 { ISD::BITREVERSE, MVT::v16i8, 20 }, 1890 { ISD::BSWAP, MVT::v2i64, 7 }, 1891 { ISD::BSWAP, MVT::v4i32, 7 }, 1892 { ISD::BSWAP, MVT::v8i16, 7 }, 1893 { ISD::CTLZ, MVT::v2i64, 25 }, 1894 { ISD::CTLZ, MVT::v4i32, 26 }, 1895 { ISD::CTLZ, MVT::v8i16, 20 }, 1896 { ISD::CTLZ, MVT::v16i8, 17 }, 1897 { ISD::CTPOP, MVT::v2i64, 12 }, 1898 { ISD::CTPOP, MVT::v4i32, 15 }, 1899 { ISD::CTPOP, MVT::v8i16, 13 }, 1900 { ISD::CTPOP, MVT::v16i8, 10 }, 1901 { ISD::CTTZ, MVT::v2i64, 14 }, 1902 { ISD::CTTZ, MVT::v4i32, 18 }, 1903 { ISD::CTTZ, MVT::v8i16, 16 }, 1904 { ISD::CTTZ, MVT::v16i8, 13 }, 1905 { ISD::SADDSAT, MVT::v8i16, 1 }, 1906 { ISD::SADDSAT, MVT::v16i8, 1 }, 1907 { ISD::SSUBSAT, MVT::v8i16, 1 }, 1908 { ISD::SSUBSAT, MVT::v16i8, 1 }, 1909 { ISD::UADDSAT, MVT::v8i16, 1 }, 1910 { ISD::UADDSAT, MVT::v16i8, 1 }, 1911 { ISD::USUBSAT, MVT::v8i16, 1 }, 1912 { ISD::USUBSAT, MVT::v16i8, 1 }, 1913 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 1914 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 1915 }; 1916 static const CostTblEntry SSE1CostTbl[] = { 1917 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 1918 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 1919 }; 1920 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 1921 { ISD::BITREVERSE, MVT::i64, 14 } 1922 }; 1923 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 1924 { ISD::BITREVERSE, MVT::i32, 14 }, 1925 { ISD::BITREVERSE, MVT::i16, 14 }, 1926 { ISD::BITREVERSE, MVT::i8, 11 } 1927 }; 1928 1929 unsigned ISD = ISD::DELETED_NODE; 1930 switch (IID) { 1931 default: 1932 break; 1933 case Intrinsic::bitreverse: 1934 ISD = ISD::BITREVERSE; 1935 break; 1936 case Intrinsic::bswap: 1937 ISD = ISD::BSWAP; 1938 break; 1939 case Intrinsic::ctlz: 1940 ISD = ISD::CTLZ; 1941 break; 1942 case Intrinsic::ctpop: 1943 ISD = ISD::CTPOP; 1944 break; 1945 case Intrinsic::cttz: 1946 ISD = ISD::CTTZ; 1947 break; 1948 case Intrinsic::sadd_sat: 1949 ISD = ISD::SADDSAT; 1950 break; 1951 case Intrinsic::ssub_sat: 1952 ISD = ISD::SSUBSAT; 1953 break; 1954 case Intrinsic::uadd_sat: 1955 ISD = ISD::UADDSAT; 1956 break; 1957 case Intrinsic::usub_sat: 1958 ISD = ISD::USUBSAT; 1959 break; 1960 case Intrinsic::sqrt: 1961 ISD = ISD::FSQRT; 1962 break; 1963 } 1964 1965 if (ISD != ISD::DELETED_NODE) { 1966 // Legalize the type. 1967 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 1968 MVT MTy = LT.second; 1969 1970 // Attempt to lookup cost. 1971 if (ST->isGLM()) 1972 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 1973 return LT.first * Entry->Cost; 1974 1975 if (ST->isSLM()) 1976 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 1977 return LT.first * Entry->Cost; 1978 1979 if (ST->hasCDI()) 1980 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 1981 return LT.first * Entry->Cost; 1982 1983 if (ST->hasBWI()) 1984 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 1985 return LT.first * Entry->Cost; 1986 1987 if (ST->hasAVX512()) 1988 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 1989 return LT.first * Entry->Cost; 1990 1991 if (ST->hasXOP()) 1992 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 1993 return LT.first * Entry->Cost; 1994 1995 if (ST->hasAVX2()) 1996 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 1997 return LT.first * Entry->Cost; 1998 1999 if (ST->hasAVX()) 2000 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2001 return LT.first * Entry->Cost; 2002 2003 if (ST->hasSSE42()) 2004 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2005 return LT.first * Entry->Cost; 2006 2007 if (ST->hasSSSE3()) 2008 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 2009 return LT.first * Entry->Cost; 2010 2011 if (ST->hasSSE2()) 2012 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2013 return LT.first * Entry->Cost; 2014 2015 if (ST->hasSSE1()) 2016 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2017 return LT.first * Entry->Cost; 2018 2019 if (ST->is64Bit()) 2020 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2021 return LT.first * Entry->Cost; 2022 2023 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2024 return LT.first * Entry->Cost; 2025 } 2026 2027 return BaseT::getIntrinsicInstrCost(IID, RetTy, Tys, FMF, ScalarizationCostPassed); 2028 } 2029 2030 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 2031 ArrayRef<Value *> Args, FastMathFlags FMF, 2032 unsigned VF) { 2033 static const CostTblEntry AVX512CostTbl[] = { 2034 { ISD::ROTL, MVT::v8i64, 1 }, 2035 { ISD::ROTL, MVT::v4i64, 1 }, 2036 { ISD::ROTL, MVT::v2i64, 1 }, 2037 { ISD::ROTL, MVT::v16i32, 1 }, 2038 { ISD::ROTL, MVT::v8i32, 1 }, 2039 { ISD::ROTL, MVT::v4i32, 1 }, 2040 { ISD::ROTR, MVT::v8i64, 1 }, 2041 { ISD::ROTR, MVT::v4i64, 1 }, 2042 { ISD::ROTR, MVT::v2i64, 1 }, 2043 { ISD::ROTR, MVT::v16i32, 1 }, 2044 { ISD::ROTR, MVT::v8i32, 1 }, 2045 { ISD::ROTR, MVT::v4i32, 1 } 2046 }; 2047 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 2048 static const CostTblEntry XOPCostTbl[] = { 2049 { ISD::ROTL, MVT::v4i64, 4 }, 2050 { ISD::ROTL, MVT::v8i32, 4 }, 2051 { ISD::ROTL, MVT::v16i16, 4 }, 2052 { ISD::ROTL, MVT::v32i8, 4 }, 2053 { ISD::ROTL, MVT::v2i64, 1 }, 2054 { ISD::ROTL, MVT::v4i32, 1 }, 2055 { ISD::ROTL, MVT::v8i16, 1 }, 2056 { ISD::ROTL, MVT::v16i8, 1 }, 2057 { ISD::ROTR, MVT::v4i64, 6 }, 2058 { ISD::ROTR, MVT::v8i32, 6 }, 2059 { ISD::ROTR, MVT::v16i16, 6 }, 2060 { ISD::ROTR, MVT::v32i8, 6 }, 2061 { ISD::ROTR, MVT::v2i64, 2 }, 2062 { ISD::ROTR, MVT::v4i32, 2 }, 2063 { ISD::ROTR, MVT::v8i16, 2 }, 2064 { ISD::ROTR, MVT::v16i8, 2 } 2065 }; 2066 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2067 { ISD::ROTL, MVT::i64, 1 }, 2068 { ISD::ROTR, MVT::i64, 1 }, 2069 { ISD::FSHL, MVT::i64, 4 } 2070 }; 2071 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2072 { ISD::ROTL, MVT::i32, 1 }, 2073 { ISD::ROTL, MVT::i16, 1 }, 2074 { ISD::ROTL, MVT::i8, 1 }, 2075 { ISD::ROTR, MVT::i32, 1 }, 2076 { ISD::ROTR, MVT::i16, 1 }, 2077 { ISD::ROTR, MVT::i8, 1 }, 2078 { ISD::FSHL, MVT::i32, 4 }, 2079 { ISD::FSHL, MVT::i16, 4 }, 2080 { ISD::FSHL, MVT::i8, 4 } 2081 }; 2082 2083 unsigned ISD = ISD::DELETED_NODE; 2084 switch (IID) { 2085 default: 2086 break; 2087 case Intrinsic::fshl: 2088 ISD = ISD::FSHL; 2089 if (Args[0] == Args[1]) 2090 ISD = ISD::ROTL; 2091 break; 2092 case Intrinsic::fshr: 2093 // FSHR has same costs so don't duplicate. 2094 ISD = ISD::FSHL; 2095 if (Args[0] == Args[1]) 2096 ISD = ISD::ROTR; 2097 break; 2098 } 2099 2100 if (ISD != ISD::DELETED_NODE) { 2101 // Legalize the type. 2102 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 2103 MVT MTy = LT.second; 2104 2105 // Attempt to lookup cost. 2106 if (ST->hasAVX512()) 2107 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2108 return LT.first * Entry->Cost; 2109 2110 if (ST->hasXOP()) 2111 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2112 return LT.first * Entry->Cost; 2113 2114 if (ST->is64Bit()) 2115 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2116 return LT.first * Entry->Cost; 2117 2118 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2119 return LT.first * Entry->Cost; 2120 } 2121 2122 return BaseT::getIntrinsicInstrCost(IID, RetTy, Args, FMF, VF); 2123 } 2124 2125 int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { 2126 assert(Val->isVectorTy() && "This must be a vector type"); 2127 2128 Type *ScalarType = Val->getScalarType(); 2129 2130 if (Index != -1U) { 2131 // Legalize the type. 2132 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 2133 2134 // This type is legalized to a scalar type. 2135 if (!LT.second.isVector()) 2136 return 0; 2137 2138 // The type may be split. Normalize the index to the new type. 2139 unsigned Width = LT.second.getVectorNumElements(); 2140 Index = Index % Width; 2141 2142 // Floating point scalars are already located in index #0. 2143 if (ScalarType->isFloatingPointTy() && Index == 0) 2144 return 0; 2145 } 2146 2147 // Add to the base cost if we know that the extracted element of a vector is 2148 // destined to be moved to and used in the integer register file. 2149 int RegisterFileMoveCost = 0; 2150 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 2151 RegisterFileMoveCost = 1; 2152 2153 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 2154 } 2155 2156 int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, 2157 unsigned AddressSpace, const Instruction *I) { 2158 // Handle non-power-of-two vectors such as <3 x float> 2159 if (VectorType *VTy = dyn_cast<VectorType>(Src)) { 2160 unsigned NumElem = VTy->getVectorNumElements(); 2161 2162 // Handle a few common cases: 2163 // <3 x float> 2164 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 2165 // Cost = 64 bit store + extract + 32 bit store. 2166 return 3; 2167 2168 // <3 x double> 2169 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 2170 // Cost = 128 bit store + unpack + 64 bit store. 2171 return 3; 2172 2173 // Assume that all other non-power-of-two numbers are scalarized. 2174 if (!isPowerOf2_32(NumElem)) { 2175 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment, 2176 AddressSpace); 2177 int SplitCost = getScalarizationOverhead(Src, Opcode == Instruction::Load, 2178 Opcode == Instruction::Store); 2179 return NumElem * Cost + SplitCost; 2180 } 2181 } 2182 2183 // Legalize the type. 2184 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 2185 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 2186 "Invalid Opcode"); 2187 2188 // Each load/store unit costs 1. 2189 int Cost = LT.first * 1; 2190 2191 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a 2192 // proxy for a double-pumped AVX memory interface such as on Sandybridge. 2193 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow()) 2194 Cost *= 2; 2195 2196 return Cost; 2197 } 2198 2199 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, 2200 unsigned Alignment, 2201 unsigned AddressSpace) { 2202 VectorType *SrcVTy = dyn_cast<VectorType>(SrcTy); 2203 if (!SrcVTy) 2204 // To calculate scalar take the regular cost, without mask 2205 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace); 2206 2207 unsigned NumElem = SrcVTy->getVectorNumElements(); 2208 VectorType *MaskTy = 2209 VectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 2210 if ((Opcode == Instruction::Load && !isLegalMaskedLoad(SrcVTy)) || 2211 (Opcode == Instruction::Store && !isLegalMaskedStore(SrcVTy)) || 2212 !isPowerOf2_32(NumElem)) { 2213 // Scalarization 2214 int MaskSplitCost = getScalarizationOverhead(MaskTy, false, true); 2215 int ScalarCompareCost = getCmpSelInstrCost( 2216 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr); 2217 int BranchCost = getCFInstrCost(Instruction::Br); 2218 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 2219 2220 int ValueSplitCost = getScalarizationOverhead( 2221 SrcVTy, Opcode == Instruction::Load, Opcode == Instruction::Store); 2222 int MemopCost = 2223 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2224 Alignment, AddressSpace); 2225 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 2226 } 2227 2228 // Legalize the type. 2229 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 2230 auto VT = TLI->getValueType(DL, SrcVTy); 2231 int Cost = 0; 2232 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 2233 LT.second.getVectorNumElements() == NumElem) 2234 // Promotion requires expand/truncate for data and a shuffle for mask. 2235 Cost += getShuffleCost(TTI::SK_Select, SrcVTy, 0, nullptr) + 2236 getShuffleCost(TTI::SK_Select, MaskTy, 0, nullptr); 2237 2238 else if (LT.second.getVectorNumElements() > NumElem) { 2239 VectorType *NewMaskTy = VectorType::get(MaskTy->getVectorElementType(), 2240 LT.second.getVectorNumElements()); 2241 // Expanding requires fill mask with zeroes 2242 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, 0, MaskTy); 2243 } 2244 if (!ST->hasAVX512()) 2245 return Cost + LT.first*4; // Each maskmov costs 4 2246 2247 // AVX-512 masked load/store is cheapper 2248 return Cost+LT.first; 2249 } 2250 2251 int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE, 2252 const SCEV *Ptr) { 2253 // Address computations in vectorized code with non-consecutive addresses will 2254 // likely result in more instructions compared to scalar code where the 2255 // computation can more often be merged into the index mode. The resulting 2256 // extra micro-ops can significantly decrease throughput. 2257 unsigned NumVectorInstToHideOverhead = 10; 2258 2259 // Cost modeling of Strided Access Computation is hidden by the indexing 2260 // modes of X86 regardless of the stride value. We dont believe that there 2261 // is a difference between constant strided access in gerenal and constant 2262 // strided value which is less than or equal to 64. 2263 // Even in the case of (loop invariant) stride whose value is not known at 2264 // compile time, the address computation will not incur more than one extra 2265 // ADD instruction. 2266 if (Ty->isVectorTy() && SE) { 2267 if (!BaseT::isStridedAccess(Ptr)) 2268 return NumVectorInstToHideOverhead; 2269 if (!BaseT::getConstantStrideStep(SE, Ptr)) 2270 return 1; 2271 } 2272 2273 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 2274 } 2275 2276 int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, Type *ValTy, 2277 bool IsPairwise) { 2278 2279 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2280 2281 MVT MTy = LT.second; 2282 2283 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2284 assert(ISD && "Invalid opcode"); 2285 2286 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 2287 // and make it as the cost. 2288 2289 static const CostTblEntry SSE42CostTblPairWise[] = { 2290 { ISD::FADD, MVT::v2f64, 2 }, 2291 { ISD::FADD, MVT::v4f32, 4 }, 2292 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 2293 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5". 2294 { ISD::ADD, MVT::v8i16, 5 }, 2295 }; 2296 2297 static const CostTblEntry AVX1CostTblPairWise[] = { 2298 { ISD::FADD, MVT::v4f32, 4 }, 2299 { ISD::FADD, MVT::v4f64, 5 }, 2300 { ISD::FADD, MVT::v8f32, 7 }, 2301 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 2302 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5". 2303 { ISD::ADD, MVT::v4i64, 5 }, // The data reported by the IACA tool is "4.8". 2304 { ISD::ADD, MVT::v8i16, 5 }, 2305 { ISD::ADD, MVT::v8i32, 5 }, 2306 }; 2307 2308 static const CostTblEntry SSE42CostTblNoPairWise[] = { 2309 { ISD::FADD, MVT::v2f64, 2 }, 2310 { ISD::FADD, MVT::v4f32, 4 }, 2311 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 2312 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 2313 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 2314 }; 2315 2316 static const CostTblEntry AVX1CostTblNoPairWise[] = { 2317 { ISD::FADD, MVT::v4f32, 3 }, 2318 { ISD::FADD, MVT::v4f64, 3 }, 2319 { ISD::FADD, MVT::v8f32, 4 }, 2320 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 2321 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "2.8". 2322 { ISD::ADD, MVT::v4i64, 3 }, 2323 { ISD::ADD, MVT::v8i16, 4 }, 2324 { ISD::ADD, MVT::v8i32, 5 }, 2325 }; 2326 2327 if (IsPairwise) { 2328 if (ST->hasAVX()) 2329 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy)) 2330 return LT.first * Entry->Cost; 2331 2332 if (ST->hasSSE42()) 2333 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy)) 2334 return LT.first * Entry->Cost; 2335 } else { 2336 if (ST->hasAVX()) 2337 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 2338 return LT.first * Entry->Cost; 2339 2340 if (ST->hasSSE42()) 2341 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy)) 2342 return LT.first * Entry->Cost; 2343 } 2344 2345 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise); 2346 } 2347 2348 int X86TTIImpl::getMinMaxReductionCost(Type *ValTy, Type *CondTy, 2349 bool IsPairwise, bool IsUnsigned) { 2350 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2351 2352 MVT MTy = LT.second; 2353 2354 int ISD; 2355 if (ValTy->isIntOrIntVectorTy()) { 2356 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 2357 } else { 2358 assert(ValTy->isFPOrFPVectorTy() && 2359 "Expected float point or integer vector type."); 2360 ISD = ISD::FMINNUM; 2361 } 2362 2363 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 2364 // and make it as the cost. 2365 2366 static const CostTblEntry SSE42CostTblPairWise[] = { 2367 {ISD::FMINNUM, MVT::v2f64, 3}, 2368 {ISD::FMINNUM, MVT::v4f32, 2}, 2369 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8" 2370 {ISD::UMIN, MVT::v2i64, 8}, // The data reported by the IACA is "8.6" 2371 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5" 2372 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8" 2373 {ISD::SMIN, MVT::v8i16, 2}, 2374 {ISD::UMIN, MVT::v8i16, 2}, 2375 }; 2376 2377 static const CostTblEntry AVX1CostTblPairWise[] = { 2378 {ISD::FMINNUM, MVT::v4f32, 1}, 2379 {ISD::FMINNUM, MVT::v4f64, 1}, 2380 {ISD::FMINNUM, MVT::v8f32, 2}, 2381 {ISD::SMIN, MVT::v2i64, 3}, 2382 {ISD::UMIN, MVT::v2i64, 3}, 2383 {ISD::SMIN, MVT::v4i32, 1}, 2384 {ISD::UMIN, MVT::v4i32, 1}, 2385 {ISD::SMIN, MVT::v8i16, 1}, 2386 {ISD::UMIN, MVT::v8i16, 1}, 2387 {ISD::SMIN, MVT::v8i32, 3}, 2388 {ISD::UMIN, MVT::v8i32, 3}, 2389 }; 2390 2391 static const CostTblEntry AVX2CostTblPairWise[] = { 2392 {ISD::SMIN, MVT::v4i64, 2}, 2393 {ISD::UMIN, MVT::v4i64, 2}, 2394 {ISD::SMIN, MVT::v8i32, 1}, 2395 {ISD::UMIN, MVT::v8i32, 1}, 2396 {ISD::SMIN, MVT::v16i16, 1}, 2397 {ISD::UMIN, MVT::v16i16, 1}, 2398 {ISD::SMIN, MVT::v32i8, 2}, 2399 {ISD::UMIN, MVT::v32i8, 2}, 2400 }; 2401 2402 static const CostTblEntry AVX512CostTblPairWise[] = { 2403 {ISD::FMINNUM, MVT::v8f64, 1}, 2404 {ISD::FMINNUM, MVT::v16f32, 2}, 2405 {ISD::SMIN, MVT::v8i64, 2}, 2406 {ISD::UMIN, MVT::v8i64, 2}, 2407 {ISD::SMIN, MVT::v16i32, 1}, 2408 {ISD::UMIN, MVT::v16i32, 1}, 2409 }; 2410 2411 static const CostTblEntry SSE42CostTblNoPairWise[] = { 2412 {ISD::FMINNUM, MVT::v2f64, 3}, 2413 {ISD::FMINNUM, MVT::v4f32, 3}, 2414 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8" 2415 {ISD::UMIN, MVT::v2i64, 9}, // The data reported by the IACA is "8.6" 2416 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5" 2417 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8" 2418 {ISD::SMIN, MVT::v8i16, 1}, // The data reported by the IACA is "1.5" 2419 {ISD::UMIN, MVT::v8i16, 2}, // The data reported by the IACA is "1.8" 2420 }; 2421 2422 static const CostTblEntry AVX1CostTblNoPairWise[] = { 2423 {ISD::FMINNUM, MVT::v4f32, 1}, 2424 {ISD::FMINNUM, MVT::v4f64, 1}, 2425 {ISD::FMINNUM, MVT::v8f32, 1}, 2426 {ISD::SMIN, MVT::v2i64, 3}, 2427 {ISD::UMIN, MVT::v2i64, 3}, 2428 {ISD::SMIN, MVT::v4i32, 1}, 2429 {ISD::UMIN, MVT::v4i32, 1}, 2430 {ISD::SMIN, MVT::v8i16, 1}, 2431 {ISD::UMIN, MVT::v8i16, 1}, 2432 {ISD::SMIN, MVT::v8i32, 2}, 2433 {ISD::UMIN, MVT::v8i32, 2}, 2434 }; 2435 2436 static const CostTblEntry AVX2CostTblNoPairWise[] = { 2437 {ISD::SMIN, MVT::v4i64, 1}, 2438 {ISD::UMIN, MVT::v4i64, 1}, 2439 {ISD::SMIN, MVT::v8i32, 1}, 2440 {ISD::UMIN, MVT::v8i32, 1}, 2441 {ISD::SMIN, MVT::v16i16, 1}, 2442 {ISD::UMIN, MVT::v16i16, 1}, 2443 {ISD::SMIN, MVT::v32i8, 1}, 2444 {ISD::UMIN, MVT::v32i8, 1}, 2445 }; 2446 2447 static const CostTblEntry AVX512CostTblNoPairWise[] = { 2448 {ISD::FMINNUM, MVT::v8f64, 1}, 2449 {ISD::FMINNUM, MVT::v16f32, 2}, 2450 {ISD::SMIN, MVT::v8i64, 1}, 2451 {ISD::UMIN, MVT::v8i64, 1}, 2452 {ISD::SMIN, MVT::v16i32, 1}, 2453 {ISD::UMIN, MVT::v16i32, 1}, 2454 }; 2455 2456 if (IsPairwise) { 2457 if (ST->hasAVX512()) 2458 if (const auto *Entry = CostTableLookup(AVX512CostTblPairWise, ISD, MTy)) 2459 return LT.first * Entry->Cost; 2460 2461 if (ST->hasAVX2()) 2462 if (const auto *Entry = CostTableLookup(AVX2CostTblPairWise, ISD, MTy)) 2463 return LT.first * Entry->Cost; 2464 2465 if (ST->hasAVX()) 2466 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy)) 2467 return LT.first * Entry->Cost; 2468 2469 if (ST->hasSSE42()) 2470 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy)) 2471 return LT.first * Entry->Cost; 2472 } else { 2473 if (ST->hasAVX512()) 2474 if (const auto *Entry = 2475 CostTableLookup(AVX512CostTblNoPairWise, ISD, MTy)) 2476 return LT.first * Entry->Cost; 2477 2478 if (ST->hasAVX2()) 2479 if (const auto *Entry = CostTableLookup(AVX2CostTblNoPairWise, ISD, MTy)) 2480 return LT.first * Entry->Cost; 2481 2482 if (ST->hasAVX()) 2483 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 2484 return LT.first * Entry->Cost; 2485 2486 if (ST->hasSSE42()) 2487 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy)) 2488 return LT.first * Entry->Cost; 2489 } 2490 2491 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned); 2492 } 2493 2494 /// Calculate the cost of materializing a 64-bit value. This helper 2495 /// method might only calculate a fraction of a larger immediate. Therefore it 2496 /// is valid to return a cost of ZERO. 2497 int X86TTIImpl::getIntImmCost(int64_t Val) { 2498 if (Val == 0) 2499 return TTI::TCC_Free; 2500 2501 if (isInt<32>(Val)) 2502 return TTI::TCC_Basic; 2503 2504 return 2 * TTI::TCC_Basic; 2505 } 2506 2507 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { 2508 assert(Ty->isIntegerTy()); 2509 2510 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 2511 if (BitSize == 0) 2512 return ~0U; 2513 2514 // Never hoist constants larger than 128bit, because this might lead to 2515 // incorrect code generation or assertions in codegen. 2516 // Fixme: Create a cost model for types larger than i128 once the codegen 2517 // issues have been fixed. 2518 if (BitSize > 128) 2519 return TTI::TCC_Free; 2520 2521 if (Imm == 0) 2522 return TTI::TCC_Free; 2523 2524 // Sign-extend all constants to a multiple of 64-bit. 2525 APInt ImmVal = Imm; 2526 if (BitSize % 64 != 0) 2527 ImmVal = Imm.sext(alignTo(BitSize, 64)); 2528 2529 // Split the constant into 64-bit chunks and calculate the cost for each 2530 // chunk. 2531 int Cost = 0; 2532 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 2533 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 2534 int64_t Val = Tmp.getSExtValue(); 2535 Cost += getIntImmCost(Val); 2536 } 2537 // We need at least one instruction to materialize the constant. 2538 return std::max(1, Cost); 2539 } 2540 2541 int X86TTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, 2542 Type *Ty) { 2543 assert(Ty->isIntegerTy()); 2544 2545 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 2546 // There is no cost model for constants with a bit size of 0. Return TCC_Free 2547 // here, so that constant hoisting will ignore this constant. 2548 if (BitSize == 0) 2549 return TTI::TCC_Free; 2550 2551 unsigned ImmIdx = ~0U; 2552 switch (Opcode) { 2553 default: 2554 return TTI::TCC_Free; 2555 case Instruction::GetElementPtr: 2556 // Always hoist the base address of a GetElementPtr. This prevents the 2557 // creation of new constants for every base constant that gets constant 2558 // folded with the offset. 2559 if (Idx == 0) 2560 return 2 * TTI::TCC_Basic; 2561 return TTI::TCC_Free; 2562 case Instruction::Store: 2563 ImmIdx = 0; 2564 break; 2565 case Instruction::ICmp: 2566 // This is an imperfect hack to prevent constant hoisting of 2567 // compares that might be trying to check if a 64-bit value fits in 2568 // 32-bits. The backend can optimize these cases using a right shift by 32. 2569 // Ideally we would check the compare predicate here. There also other 2570 // similar immediates the backend can use shifts for. 2571 if (Idx == 1 && Imm.getBitWidth() == 64) { 2572 uint64_t ImmVal = Imm.getZExtValue(); 2573 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 2574 return TTI::TCC_Free; 2575 } 2576 ImmIdx = 1; 2577 break; 2578 case Instruction::And: 2579 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 2580 // by using a 32-bit operation with implicit zero extension. Detect such 2581 // immediates here as the normal path expects bit 31 to be sign extended. 2582 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 2583 return TTI::TCC_Free; 2584 ImmIdx = 1; 2585 break; 2586 case Instruction::Add: 2587 case Instruction::Sub: 2588 // For add/sub, we can use the opposite instruction for INT32_MIN. 2589 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 2590 return TTI::TCC_Free; 2591 ImmIdx = 1; 2592 break; 2593 case Instruction::UDiv: 2594 case Instruction::SDiv: 2595 case Instruction::URem: 2596 case Instruction::SRem: 2597 // Division by constant is typically expanded later into a different 2598 // instruction sequence. This completely changes the constants. 2599 // Report them as "free" to stop ConstantHoist from marking them as opaque. 2600 return TTI::TCC_Free; 2601 case Instruction::Mul: 2602 case Instruction::Or: 2603 case Instruction::Xor: 2604 ImmIdx = 1; 2605 break; 2606 // Always return TCC_Free for the shift value of a shift instruction. 2607 case Instruction::Shl: 2608 case Instruction::LShr: 2609 case Instruction::AShr: 2610 if (Idx == 1) 2611 return TTI::TCC_Free; 2612 break; 2613 case Instruction::Trunc: 2614 case Instruction::ZExt: 2615 case Instruction::SExt: 2616 case Instruction::IntToPtr: 2617 case Instruction::PtrToInt: 2618 case Instruction::BitCast: 2619 case Instruction::PHI: 2620 case Instruction::Call: 2621 case Instruction::Select: 2622 case Instruction::Ret: 2623 case Instruction::Load: 2624 break; 2625 } 2626 2627 if (Idx == ImmIdx) { 2628 int NumConstants = divideCeil(BitSize, 64); 2629 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty); 2630 return (Cost <= NumConstants * TTI::TCC_Basic) 2631 ? static_cast<int>(TTI::TCC_Free) 2632 : Cost; 2633 } 2634 2635 return X86TTIImpl::getIntImmCost(Imm, Ty); 2636 } 2637 2638 int X86TTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, 2639 Type *Ty) { 2640 assert(Ty->isIntegerTy()); 2641 2642 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 2643 // There is no cost model for constants with a bit size of 0. Return TCC_Free 2644 // here, so that constant hoisting will ignore this constant. 2645 if (BitSize == 0) 2646 return TTI::TCC_Free; 2647 2648 switch (IID) { 2649 default: 2650 return TTI::TCC_Free; 2651 case Intrinsic::sadd_with_overflow: 2652 case Intrinsic::uadd_with_overflow: 2653 case Intrinsic::ssub_with_overflow: 2654 case Intrinsic::usub_with_overflow: 2655 case Intrinsic::smul_with_overflow: 2656 case Intrinsic::umul_with_overflow: 2657 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 2658 return TTI::TCC_Free; 2659 break; 2660 case Intrinsic::experimental_stackmap: 2661 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 2662 return TTI::TCC_Free; 2663 break; 2664 case Intrinsic::experimental_patchpoint_void: 2665 case Intrinsic::experimental_patchpoint_i64: 2666 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 2667 return TTI::TCC_Free; 2668 break; 2669 } 2670 return X86TTIImpl::getIntImmCost(Imm, Ty); 2671 } 2672 2673 unsigned X86TTIImpl::getUserCost(const User *U, 2674 ArrayRef<const Value *> Operands) { 2675 if (isa<StoreInst>(U)) { 2676 Value *Ptr = U->getOperand(1); 2677 // Store instruction with index and scale costs 2 Uops. 2678 // Check the preceding GEP to identify non-const indices. 2679 if (auto GEP = dyn_cast<GetElementPtrInst>(Ptr)) { 2680 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 2681 return TTI::TCC_Basic * 2; 2682 } 2683 return TTI::TCC_Basic; 2684 } 2685 return BaseT::getUserCost(U, Operands); 2686 } 2687 2688 // Return an average cost of Gather / Scatter instruction, maybe improved later 2689 int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, Value *Ptr, 2690 unsigned Alignment, unsigned AddressSpace) { 2691 2692 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 2693 unsigned VF = SrcVTy->getVectorNumElements(); 2694 2695 // Try to reduce index size from 64 bit (default for GEP) 2696 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 2697 // operation will use 16 x 64 indices which do not fit in a zmm and needs 2698 // to split. Also check that the base pointer is the same for all lanes, 2699 // and that there's at most one variable index. 2700 auto getIndexSizeInBits = [](Value *Ptr, const DataLayout& DL) { 2701 unsigned IndexSize = DL.getPointerSizeInBits(); 2702 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 2703 if (IndexSize < 64 || !GEP) 2704 return IndexSize; 2705 2706 unsigned NumOfVarIndices = 0; 2707 Value *Ptrs = GEP->getPointerOperand(); 2708 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 2709 return IndexSize; 2710 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 2711 if (isa<Constant>(GEP->getOperand(i))) 2712 continue; 2713 Type *IndxTy = GEP->getOperand(i)->getType(); 2714 if (IndxTy->isVectorTy()) 2715 IndxTy = IndxTy->getVectorElementType(); 2716 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 2717 !isa<SExtInst>(GEP->getOperand(i))) || 2718 ++NumOfVarIndices > 1) 2719 return IndexSize; // 64 2720 } 2721 return (unsigned)32; 2722 }; 2723 2724 2725 // Trying to reduce IndexSize to 32 bits for vector 16. 2726 // By default the IndexSize is equal to pointer size. 2727 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 2728 ? getIndexSizeInBits(Ptr, DL) 2729 : DL.getPointerSizeInBits(); 2730 2731 Type *IndexVTy = VectorType::get(IntegerType::get(SrcVTy->getContext(), 2732 IndexSize), VF); 2733 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy); 2734 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy); 2735 int SplitFactor = std::max(IdxsLT.first, SrcLT.first); 2736 if (SplitFactor > 1) { 2737 // Handle splitting of vector of pointers 2738 Type *SplitSrcTy = VectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 2739 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 2740 AddressSpace); 2741 } 2742 2743 // The gather / scatter cost is given by Intel architects. It is a rough 2744 // number since we are looking at one instruction in a time. 2745 const int GSOverhead = (Opcode == Instruction::Load) 2746 ? ST->getGatherOverhead() 2747 : ST->getScatterOverhead(); 2748 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2749 Alignment, AddressSpace); 2750 } 2751 2752 /// Return the cost of full scalarization of gather / scatter operation. 2753 /// 2754 /// Opcode - Load or Store instruction. 2755 /// SrcVTy - The type of the data vector that should be gathered or scattered. 2756 /// VariableMask - The mask is non-constant at compile time. 2757 /// Alignment - Alignment for one element. 2758 /// AddressSpace - pointer[s] address space. 2759 /// 2760 int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 2761 bool VariableMask, unsigned Alignment, 2762 unsigned AddressSpace) { 2763 unsigned VF = SrcVTy->getVectorNumElements(); 2764 2765 int MaskUnpackCost = 0; 2766 if (VariableMask) { 2767 VectorType *MaskTy = 2768 VectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 2769 MaskUnpackCost = getScalarizationOverhead(MaskTy, false, true); 2770 int ScalarCompareCost = 2771 getCmpSelInstrCost(Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), 2772 nullptr); 2773 int BranchCost = getCFInstrCost(Instruction::Br); 2774 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 2775 } 2776 2777 // The cost of the scalar loads/stores. 2778 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2779 Alignment, AddressSpace); 2780 2781 int InsertExtractCost = 0; 2782 if (Opcode == Instruction::Load) 2783 for (unsigned i = 0; i < VF; ++i) 2784 // Add the cost of inserting each scalar load into the vector 2785 InsertExtractCost += 2786 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 2787 else 2788 for (unsigned i = 0; i < VF; ++i) 2789 // Add the cost of extracting each element out of the data vector 2790 InsertExtractCost += 2791 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 2792 2793 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 2794 } 2795 2796 /// Calculate the cost of Gather / Scatter operation 2797 int X86TTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *SrcVTy, 2798 Value *Ptr, bool VariableMask, 2799 unsigned Alignment) { 2800 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 2801 unsigned VF = SrcVTy->getVectorNumElements(); 2802 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 2803 if (!PtrTy && Ptr->getType()->isVectorTy()) 2804 PtrTy = dyn_cast<PointerType>(Ptr->getType()->getVectorElementType()); 2805 assert(PtrTy && "Unexpected type for Ptr argument"); 2806 unsigned AddressSpace = PtrTy->getAddressSpace(); 2807 2808 bool Scalarize = false; 2809 if ((Opcode == Instruction::Load && !isLegalMaskedGather(SrcVTy)) || 2810 (Opcode == Instruction::Store && !isLegalMaskedScatter(SrcVTy))) 2811 Scalarize = true; 2812 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 2813 // Vector-4 of gather/scatter instruction does not exist on KNL. 2814 // We can extend it to 8 elements, but zeroing upper bits of 2815 // the mask vector will add more instructions. Right now we give the scalar 2816 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 2817 // is better in the VariableMask case. 2818 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 2819 Scalarize = true; 2820 2821 if (Scalarize) 2822 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 2823 AddressSpace); 2824 2825 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 2826 } 2827 2828 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 2829 TargetTransformInfo::LSRCost &C2) { 2830 // X86 specific here are "instruction number 1st priority". 2831 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 2832 C1.NumIVMuls, C1.NumBaseAdds, 2833 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 2834 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 2835 C2.NumIVMuls, C2.NumBaseAdds, 2836 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 2837 } 2838 2839 bool X86TTIImpl::canMacroFuseCmp() { 2840 return ST->hasMacroFusion(); 2841 } 2842 2843 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy) { 2844 // The backend can't handle a single element vector. 2845 if (isa<VectorType>(DataTy) && DataTy->getVectorNumElements() == 1) 2846 return false; 2847 Type *ScalarTy = DataTy->getScalarType(); 2848 int DataWidth = isa<PointerType>(ScalarTy) ? 2849 DL.getPointerSizeInBits() : ScalarTy->getPrimitiveSizeInBits(); 2850 2851 return ((DataWidth == 32 || DataWidth == 64) && ST->hasAVX()) || 2852 ((DataWidth == 8 || DataWidth == 16) && ST->hasBWI()); 2853 } 2854 2855 bool X86TTIImpl::isLegalMaskedStore(Type *DataType) { 2856 return isLegalMaskedLoad(DataType); 2857 } 2858 2859 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy) { 2860 // This function is called now in two cases: from the Loop Vectorizer 2861 // and from the Scalarizer. 2862 // When the Loop Vectorizer asks about legality of the feature, 2863 // the vectorization factor is not calculated yet. The Loop Vectorizer 2864 // sends a scalar type and the decision is based on the width of the 2865 // scalar element. 2866 // Later on, the cost model will estimate usage this intrinsic based on 2867 // the vector type. 2868 // The Scalarizer asks again about legality. It sends a vector type. 2869 // In this case we can reject non-power-of-2 vectors. 2870 // We also reject single element vectors as the type legalizer can't 2871 // scalarize it. 2872 if (isa<VectorType>(DataTy)) { 2873 unsigned NumElts = DataTy->getVectorNumElements(); 2874 if (NumElts == 1 || !isPowerOf2_32(NumElts)) 2875 return false; 2876 } 2877 Type *ScalarTy = DataTy->getScalarType(); 2878 int DataWidth = isa<PointerType>(ScalarTy) ? 2879 DL.getPointerSizeInBits() : ScalarTy->getPrimitiveSizeInBits(); 2880 2881 // Some CPUs have better gather performance than others. 2882 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 2883 // enable gather with a -march. 2884 return (DataWidth == 32 || DataWidth == 64) && 2885 (ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2())); 2886 } 2887 2888 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType) { 2889 // AVX2 doesn't support scatter 2890 if (!ST->hasAVX512()) 2891 return false; 2892 return isLegalMaskedGather(DataType); 2893 } 2894 2895 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 2896 EVT VT = TLI->getValueType(DL, DataType); 2897 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 2898 } 2899 2900 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 2901 return false; 2902 } 2903 2904 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 2905 const Function *Callee) const { 2906 const TargetMachine &TM = getTLI()->getTargetMachine(); 2907 2908 // Work this as a subsetting of subtarget features. 2909 const FeatureBitset &CallerBits = 2910 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 2911 const FeatureBitset &CalleeBits = 2912 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 2913 2914 // FIXME: This is likely too limiting as it will include subtarget features 2915 // that we might not care about for inlining, but it is conservatively 2916 // correct. 2917 return (CallerBits & CalleeBits) == CalleeBits; 2918 } 2919 2920 const X86TTIImpl::TTI::MemCmpExpansionOptions * 2921 X86TTIImpl::enableMemCmpExpansion(bool IsZeroCmp) const { 2922 // Only enable vector loads for equality comparison. 2923 // Right now the vector version is not as fast, see #33329. 2924 static const auto ThreeWayOptions = [this]() { 2925 TTI::MemCmpExpansionOptions Options; 2926 if (ST->is64Bit()) { 2927 Options.LoadSizes.push_back(8); 2928 } 2929 Options.LoadSizes.push_back(4); 2930 Options.LoadSizes.push_back(2); 2931 Options.LoadSizes.push_back(1); 2932 return Options; 2933 }(); 2934 static const auto EqZeroOptions = [this]() { 2935 TTI::MemCmpExpansionOptions Options; 2936 // TODO: enable AVX512 when the DAG is ready. 2937 // if (ST->hasAVX512()) Options.LoadSizes.push_back(64); 2938 if (ST->hasAVX2()) Options.LoadSizes.push_back(32); 2939 if (ST->hasSSE2()) Options.LoadSizes.push_back(16); 2940 if (ST->is64Bit()) { 2941 Options.LoadSizes.push_back(8); 2942 } 2943 Options.LoadSizes.push_back(4); 2944 Options.LoadSizes.push_back(2); 2945 Options.LoadSizes.push_back(1); 2946 // All GPR and vector loads can be unaligned. SIMD compare requires integer 2947 // vectors (SSE2/AVX2). 2948 Options.AllowOverlappingLoads = true; 2949 return Options; 2950 }(); 2951 return IsZeroCmp ? &EqZeroOptions : &ThreeWayOptions; 2952 } 2953 2954 bool X86TTIImpl::enableInterleavedAccessVectorization() { 2955 // TODO: We expect this to be beneficial regardless of arch, 2956 // but there are currently some unexplained performance artifacts on Atom. 2957 // As a temporary solution, disable on Atom. 2958 return !(ST->isAtom()); 2959 } 2960 2961 // Get estimation for interleaved load/store operations for AVX2. 2962 // \p Factor is the interleaved-access factor (stride) - number of 2963 // (interleaved) elements in the group. 2964 // \p Indices contains the indices for a strided load: when the 2965 // interleaved load has gaps they indicate which elements are used. 2966 // If Indices is empty (or if the number of indices is equal to the size 2967 // of the interleaved-access as given in \p Factor) the access has no gaps. 2968 // 2969 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 2970 // computing the cost using a generic formula as a function of generic 2971 // shuffles. We therefore use a lookup table instead, filled according to 2972 // the instruction sequences that codegen currently generates. 2973 int X86TTIImpl::getInterleavedMemoryOpCostAVX2(unsigned Opcode, Type *VecTy, 2974 unsigned Factor, 2975 ArrayRef<unsigned> Indices, 2976 unsigned Alignment, 2977 unsigned AddressSpace, 2978 bool UseMaskForCond, 2979 bool UseMaskForGaps) { 2980 2981 if (UseMaskForCond || UseMaskForGaps) 2982 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 2983 Alignment, AddressSpace, 2984 UseMaskForCond, UseMaskForGaps); 2985 2986 // We currently Support only fully-interleaved groups, with no gaps. 2987 // TODO: Support also strided loads (interleaved-groups with gaps). 2988 if (Indices.size() && Indices.size() != Factor) 2989 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 2990 Alignment, AddressSpace); 2991 2992 // VecTy for interleave memop is <VF*Factor x Elt>. 2993 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 2994 // VecTy = <12 x i32>. 2995 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 2996 2997 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 2998 // the VF=2, while v2i128 is an unsupported MVT vector type 2999 // (see MachineValueType.h::getVectorVT()). 3000 if (!LegalVT.isVector()) 3001 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3002 Alignment, AddressSpace); 3003 3004 unsigned VF = VecTy->getVectorNumElements() / Factor; 3005 Type *ScalarTy = VecTy->getVectorElementType(); 3006 3007 // Calculate the number of memory operations (NumOfMemOps), required 3008 // for load/store the VecTy. 3009 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 3010 unsigned LegalVTSize = LegalVT.getStoreSize(); 3011 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 3012 3013 // Get the cost of one memory operation. 3014 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(), 3015 LegalVT.getVectorNumElements()); 3016 unsigned MemOpCost = 3017 getMemoryOpCost(Opcode, SingleMemOpTy, Alignment, AddressSpace); 3018 3019 VectorType *VT = VectorType::get(ScalarTy, VF); 3020 EVT ETy = TLI->getValueType(DL, VT); 3021 if (!ETy.isSimple()) 3022 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3023 Alignment, AddressSpace); 3024 3025 // TODO: Complete for other data-types and strides. 3026 // Each combination of Stride, ElementTy and VF results in a different 3027 // sequence; The cost tables are therefore accessed with: 3028 // Factor (stride) and VectorType=VFxElemType. 3029 // The Cost accounts only for the shuffle sequence; 3030 // The cost of the loads/stores is accounted for separately. 3031 // 3032 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 3033 { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64 3034 { 2, MVT::v4f64, 6 }, //(load 8f64 and) deinterleave into 2 x 4f64 3035 3036 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8 3037 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8 3038 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8 3039 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8 3040 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8 3041 { 3, MVT::v8f32, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32 3042 3043 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8 3044 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8 3045 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8 3046 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8 3047 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8 3048 3049 { 8, MVT::v8f32, 40 } //(load 64f32 and)deinterleave into 8 x 8f32 3050 }; 3051 3052 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 3053 { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store) 3054 { 2, MVT::v4f64, 6 }, //interleave into 2 x 4f64 into 8f64 (and store) 3055 3056 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store) 3057 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store) 3058 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store) 3059 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store) 3060 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store) 3061 3062 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store) 3063 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store) 3064 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store) 3065 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store) 3066 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store) 3067 }; 3068 3069 if (Opcode == Instruction::Load) { 3070 if (const auto *Entry = 3071 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 3072 return NumOfMemOps * MemOpCost + Entry->Cost; 3073 } else { 3074 assert(Opcode == Instruction::Store && 3075 "Expected Store Instruction at this point"); 3076 if (const auto *Entry = 3077 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 3078 return NumOfMemOps * MemOpCost + Entry->Cost; 3079 } 3080 3081 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3082 Alignment, AddressSpace); 3083 } 3084 3085 // Get estimation for interleaved load/store operations and strided load. 3086 // \p Indices contains indices for strided load. 3087 // \p Factor - the factor of interleaving. 3088 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 3089 int X86TTIImpl::getInterleavedMemoryOpCostAVX512(unsigned Opcode, Type *VecTy, 3090 unsigned Factor, 3091 ArrayRef<unsigned> Indices, 3092 unsigned Alignment, 3093 unsigned AddressSpace, 3094 bool UseMaskForCond, 3095 bool UseMaskForGaps) { 3096 3097 if (UseMaskForCond || UseMaskForGaps) 3098 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3099 Alignment, AddressSpace, 3100 UseMaskForCond, UseMaskForGaps); 3101 3102 // VecTy for interleave memop is <VF*Factor x Elt>. 3103 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 3104 // VecTy = <12 x i32>. 3105 3106 // Calculate the number of memory operations (NumOfMemOps), required 3107 // for load/store the VecTy. 3108 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 3109 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 3110 unsigned LegalVTSize = LegalVT.getStoreSize(); 3111 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 3112 3113 // Get the cost of one memory operation. 3114 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(), 3115 LegalVT.getVectorNumElements()); 3116 unsigned MemOpCost = 3117 getMemoryOpCost(Opcode, SingleMemOpTy, Alignment, AddressSpace); 3118 3119 unsigned VF = VecTy->getVectorNumElements() / Factor; 3120 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 3121 3122 if (Opcode == Instruction::Load) { 3123 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 3124 // contain the cost of the optimized shuffle sequence that the 3125 // X86InterleavedAccess pass will generate. 3126 // The cost of loads and stores are computed separately from the table. 3127 3128 // X86InterleavedAccess support only the following interleaved-access group. 3129 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 3130 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 3131 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 3132 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 3133 }; 3134 3135 if (const auto *Entry = 3136 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 3137 return NumOfMemOps * MemOpCost + Entry->Cost; 3138 //If an entry does not exist, fallback to the default implementation. 3139 3140 // Kind of shuffle depends on number of loaded values. 3141 // If we load the entire data in one register, we can use a 1-src shuffle. 3142 // Otherwise, we'll merge 2 sources in each operation. 3143 TTI::ShuffleKind ShuffleKind = 3144 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 3145 3146 unsigned ShuffleCost = 3147 getShuffleCost(ShuffleKind, SingleMemOpTy, 0, nullptr); 3148 3149 unsigned NumOfLoadsInInterleaveGrp = 3150 Indices.size() ? Indices.size() : Factor; 3151 Type *ResultTy = VectorType::get(VecTy->getVectorElementType(), 3152 VecTy->getVectorNumElements() / Factor); 3153 unsigned NumOfResults = 3154 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 3155 NumOfLoadsInInterleaveGrp; 3156 3157 // About a half of the loads may be folded in shuffles when we have only 3158 // one result. If we have more than one result, we do not fold loads at all. 3159 unsigned NumOfUnfoldedLoads = 3160 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 3161 3162 // Get a number of shuffle operations per result. 3163 unsigned NumOfShufflesPerResult = 3164 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 3165 3166 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 3167 // When we have more than one destination, we need additional instructions 3168 // to keep sources. 3169 unsigned NumOfMoves = 0; 3170 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 3171 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 3172 3173 int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 3174 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 3175 3176 return Cost; 3177 } 3178 3179 // Store. 3180 assert(Opcode == Instruction::Store && 3181 "Expected Store Instruction at this point"); 3182 // X86InterleavedAccess support only the following interleaved-access group. 3183 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 3184 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 3185 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 3186 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 3187 3188 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 3189 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 3190 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 3191 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 3192 }; 3193 3194 if (const auto *Entry = 3195 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 3196 return NumOfMemOps * MemOpCost + Entry->Cost; 3197 //If an entry does not exist, fallback to the default implementation. 3198 3199 // There is no strided stores meanwhile. And store can't be folded in 3200 // shuffle. 3201 unsigned NumOfSources = Factor; // The number of values to be merged. 3202 unsigned ShuffleCost = 3203 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, 0, nullptr); 3204 unsigned NumOfShufflesPerStore = NumOfSources - 1; 3205 3206 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 3207 // We need additional instructions to keep sources. 3208 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 3209 int Cost = NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 3210 NumOfMoves; 3211 return Cost; 3212 } 3213 3214 int X86TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, 3215 unsigned Factor, 3216 ArrayRef<unsigned> Indices, 3217 unsigned Alignment, 3218 unsigned AddressSpace, 3219 bool UseMaskForCond, 3220 bool UseMaskForGaps) { 3221 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 3222 Type *EltTy = VecTy->getVectorElementType(); 3223 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 3224 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 3225 return true; 3226 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 3227 return HasBW; 3228 return false; 3229 }; 3230 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 3231 return getInterleavedMemoryOpCostAVX512(Opcode, VecTy, Factor, Indices, 3232 Alignment, AddressSpace, 3233 UseMaskForCond, UseMaskForGaps); 3234 if (ST->hasAVX2()) 3235 return getInterleavedMemoryOpCostAVX2(Opcode, VecTy, Factor, Indices, 3236 Alignment, AddressSpace, 3237 UseMaskForCond, UseMaskForGaps); 3238 3239 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3240 Alignment, AddressSpace, 3241 UseMaskForCond, UseMaskForGaps); 3242 } 3243