1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/InstIterator.h" 47 #include "llvm/IR/IntrinsicInst.h" 48 #include "llvm/Support/Debug.h" 49 50 using namespace llvm; 51 52 #define DEBUG_TYPE "x86tti" 53 54 //===----------------------------------------------------------------------===// 55 // 56 // X86 cost model. 57 // 58 //===----------------------------------------------------------------------===// 59 60 TargetTransformInfo::PopcntSupportKind 61 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 62 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 63 // TODO: Currently the __builtin_popcount() implementation using SSE3 64 // instructions is inefficient. Once the problem is fixed, we should 65 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 66 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 67 } 68 69 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 70 TargetTransformInfo::CacheLevel Level) const { 71 switch (Level) { 72 case TargetTransformInfo::CacheLevel::L1D: 73 // - Penryn 74 // - Nehalem 75 // - Westmere 76 // - Sandy Bridge 77 // - Ivy Bridge 78 // - Haswell 79 // - Broadwell 80 // - Skylake 81 // - Kabylake 82 return 32 * 1024; // 32 KByte 83 case TargetTransformInfo::CacheLevel::L2D: 84 // - Penryn 85 // - Nehalem 86 // - Westmere 87 // - Sandy Bridge 88 // - Ivy Bridge 89 // - Haswell 90 // - Broadwell 91 // - Skylake 92 // - Kabylake 93 return 256 * 1024; // 256 KByte 94 } 95 96 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 97 } 98 99 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 100 TargetTransformInfo::CacheLevel Level) const { 101 // - Penryn 102 // - Nehalem 103 // - Westmere 104 // - Sandy Bridge 105 // - Ivy Bridge 106 // - Haswell 107 // - Broadwell 108 // - Skylake 109 // - Kabylake 110 switch (Level) { 111 case TargetTransformInfo::CacheLevel::L1D: 112 LLVM_FALLTHROUGH; 113 case TargetTransformInfo::CacheLevel::L2D: 114 return 8; 115 } 116 117 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 118 } 119 120 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 121 bool Vector = (ClassID == 1); 122 if (Vector && !ST->hasSSE1()) 123 return 0; 124 125 if (ST->is64Bit()) { 126 if (Vector && ST->hasAVX512()) 127 return 32; 128 return 16; 129 } 130 return 8; 131 } 132 133 TypeSize 134 X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { 135 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 136 switch (K) { 137 case TargetTransformInfo::RGK_Scalar: 138 return TypeSize::getFixed(ST->is64Bit() ? 64 : 32); 139 case TargetTransformInfo::RGK_FixedWidthVector: 140 if (ST->hasAVX512() && PreferVectorWidth >= 512) 141 return TypeSize::getFixed(512); 142 if (ST->hasAVX() && PreferVectorWidth >= 256) 143 return TypeSize::getFixed(256); 144 if (ST->hasSSE1() && PreferVectorWidth >= 128) 145 return TypeSize::getFixed(128); 146 return TypeSize::getFixed(0); 147 case TargetTransformInfo::RGK_ScalableVector: 148 return TypeSize::getScalable(0); 149 } 150 151 llvm_unreachable("Unsupported register kind"); 152 } 153 154 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 155 return getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector) 156 .getFixedSize(); 157 } 158 159 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 160 // If the loop will not be vectorized, don't interleave the loop. 161 // Let regular unroll to unroll the loop, which saves the overflow 162 // check and memory check cost. 163 if (VF == 1) 164 return 1; 165 166 if (ST->isAtom()) 167 return 1; 168 169 // Sandybridge and Haswell have multiple execution ports and pipelined 170 // vector units. 171 if (ST->hasAVX()) 172 return 4; 173 174 return 2; 175 } 176 177 InstructionCost X86TTIImpl::getArithmeticInstrCost( 178 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, 179 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 180 TTI::OperandValueProperties Opd1PropInfo, 181 TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, 182 const Instruction *CxtI) { 183 // TODO: Handle more cost kinds. 184 if (CostKind != TTI::TCK_RecipThroughput) 185 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, 186 Op2Info, Opd1PropInfo, 187 Opd2PropInfo, Args, CxtI); 188 189 // vXi8 multiplications are always promoted to vXi16. 190 if (Opcode == Instruction::Mul && Ty->isVectorTy() && 191 Ty->getScalarSizeInBits() == 8) { 192 Type *WideVecTy = 193 VectorType::getExtendedElementVectorType(cast<VectorType>(Ty)); 194 return getCastInstrCost(Instruction::ZExt, WideVecTy, Ty, 195 TargetTransformInfo::CastContextHint::None, 196 CostKind) + 197 getCastInstrCost(Instruction::Trunc, Ty, WideVecTy, 198 TargetTransformInfo::CastContextHint::None, 199 CostKind) + 200 getArithmeticInstrCost(Opcode, WideVecTy, CostKind, Op1Info, Op2Info, 201 Opd1PropInfo, Opd2PropInfo); 202 } 203 204 // Legalize the type. 205 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 206 207 int ISD = TLI->InstructionOpcodeToISD(Opcode); 208 assert(ISD && "Invalid opcode"); 209 210 if (ISD == ISD::MUL && Args.size() == 2 && LT.second.isVector() && 211 LT.second.getScalarType() == MVT::i32) { 212 // Check if the operands can be represented as a smaller datatype. 213 bool Op1Signed = false, Op2Signed = false; 214 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 215 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 216 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 217 218 // If both are representable as i15 and at least one is constant, 219 // zero-extended, or sign-extended from vXi16 (or less pre-SSE41) then we 220 // can treat this as PMADDWD which has the same costs as a vXi16 multiply. 221 if (OpMinSize <= 15 && !ST->isPMADDWDSlow()) { 222 bool Op1Constant = 223 isa<ConstantDataVector>(Args[0]) || isa<ConstantVector>(Args[0]); 224 bool Op2Constant = 225 isa<ConstantDataVector>(Args[1]) || isa<ConstantVector>(Args[1]); 226 bool Op1Sext = isa<SExtInst>(Args[0]) && 227 (Op1MinSize == 15 || (Op1MinSize < 15 && !ST->hasSSE41())); 228 bool Op2Sext = isa<SExtInst>(Args[1]) && 229 (Op2MinSize == 15 || (Op2MinSize < 15 && !ST->hasSSE41())); 230 231 bool IsZeroExtended = !Op1Signed || !Op2Signed; 232 bool IsConstant = Op1Constant || Op2Constant; 233 bool IsSext = Op1Sext || Op2Sext; 234 if (IsConstant || IsZeroExtended || IsSext) 235 LT.second = 236 MVT::getVectorVT(MVT::i16, 2 * LT.second.getVectorNumElements()); 237 } 238 } 239 240 // Vector multiply by pow2 will be simplified to shifts. 241 if (ISD == ISD::MUL && 242 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 243 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 244 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) 245 return getArithmeticInstrCost(Instruction::Shl, Ty, CostKind, Op1Info, 246 Op2Info, TargetTransformInfo::OP_None, 247 TargetTransformInfo::OP_None); 248 249 // On X86, vector signed division by constants power-of-two are 250 // normally expanded to the sequence SRA + SRL + ADD + SRA. 251 // The OperandValue properties may not be the same as that of the previous 252 // operation; conservatively assume OP_None. 253 if ((ISD == ISD::SDIV || ISD == ISD::SREM) && 254 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 255 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 256 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 257 InstructionCost Cost = 258 2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Op1Info, 259 Op2Info, TargetTransformInfo::OP_None, 260 TargetTransformInfo::OP_None); 261 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 262 Op2Info, TargetTransformInfo::OP_None, 263 TargetTransformInfo::OP_None); 264 Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind, Op1Info, 265 Op2Info, TargetTransformInfo::OP_None, 266 TargetTransformInfo::OP_None); 267 268 if (ISD == ISD::SREM) { 269 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 270 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info, 271 Op2Info); 272 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info, 273 Op2Info); 274 } 275 276 return Cost; 277 } 278 279 // Vector unsigned division/remainder will be simplified to shifts/masks. 280 if ((ISD == ISD::UDIV || ISD == ISD::UREM) && 281 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 282 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 283 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 284 if (ISD == ISD::UDIV) 285 return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 286 Op2Info, TargetTransformInfo::OP_None, 287 TargetTransformInfo::OP_None); 288 // UREM 289 return getArithmeticInstrCost(Instruction::And, Ty, CostKind, Op1Info, 290 Op2Info, TargetTransformInfo::OP_None, 291 TargetTransformInfo::OP_None); 292 } 293 294 static const CostTblEntry GLMCostTable[] = { 295 { ISD::FDIV, MVT::f32, 18 }, // divss 296 { ISD::FDIV, MVT::v4f32, 35 }, // divps 297 { ISD::FDIV, MVT::f64, 33 }, // divsd 298 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 299 }; 300 301 if (ST->useGLMDivSqrtCosts()) 302 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 303 LT.second)) 304 return LT.first * Entry->Cost; 305 306 static const CostTblEntry SLMCostTable[] = { 307 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 308 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 309 { ISD::FMUL, MVT::f64, 2 }, // mulsd 310 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 311 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 312 { ISD::FDIV, MVT::f32, 17 }, // divss 313 { ISD::FDIV, MVT::v4f32, 39 }, // divps 314 { ISD::FDIV, MVT::f64, 32 }, // divsd 315 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 316 { ISD::FADD, MVT::v2f64, 2 }, // addpd 317 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 318 // v2i64/v4i64 mul is custom lowered as a series of long: 319 // multiplies(3), shifts(3) and adds(2) 320 // slm muldq version throughput is 2 and addq throughput 4 321 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 322 // 3X4 (addq throughput) = 17 323 { ISD::MUL, MVT::v2i64, 17 }, 324 // slm addq\subq throughput is 4 325 { ISD::ADD, MVT::v2i64, 4 }, 326 { ISD::SUB, MVT::v2i64, 4 }, 327 }; 328 329 if (ST->useSLMArithCosts()) { 330 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 331 // Check if the operands can be shrinked into a smaller datatype. 332 // TODO: Merge this into generiic vXi32 MUL patterns above. 333 bool Op1Signed = false; 334 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 335 bool Op2Signed = false; 336 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 337 338 bool SignedMode = Op1Signed || Op2Signed; 339 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 340 341 if (OpMinSize <= 7) 342 return LT.first * 3; // pmullw/sext 343 if (!SignedMode && OpMinSize <= 8) 344 return LT.first * 3; // pmullw/zext 345 if (OpMinSize <= 15) 346 return LT.first * 5; // pmullw/pmulhw/pshuf 347 if (!SignedMode && OpMinSize <= 16) 348 return LT.first * 5; // pmullw/pmulhw/pshuf 349 } 350 351 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 352 LT.second)) { 353 return LT.first * Entry->Cost; 354 } 355 } 356 357 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 358 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 359 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 360 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 361 }; 362 363 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 364 ST->hasBWI()) { 365 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 366 LT.second)) 367 return LT.first * Entry->Cost; 368 } 369 370 static const CostTblEntry AVX512UniformConstCostTable[] = { 371 { ISD::SRA, MVT::v2i64, 1 }, 372 { ISD::SRA, MVT::v4i64, 1 }, 373 { ISD::SRA, MVT::v8i64, 1 }, 374 375 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 376 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 377 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 378 379 { ISD::SDIV, MVT::v16i32, 6 }, // pmuludq sequence 380 { ISD::SREM, MVT::v16i32, 8 }, // pmuludq+mul+sub sequence 381 { ISD::UDIV, MVT::v16i32, 5 }, // pmuludq sequence 382 { ISD::UREM, MVT::v16i32, 7 }, // pmuludq+mul+sub sequence 383 }; 384 385 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 386 ST->hasAVX512()) { 387 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 388 LT.second)) 389 return LT.first * Entry->Cost; 390 } 391 392 static const CostTblEntry AVX2UniformConstCostTable[] = { 393 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 394 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 395 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 396 397 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 398 399 { ISD::SDIV, MVT::v8i32, 6 }, // pmuludq sequence 400 { ISD::SREM, MVT::v8i32, 8 }, // pmuludq+mul+sub sequence 401 { ISD::UDIV, MVT::v8i32, 5 }, // pmuludq sequence 402 { ISD::UREM, MVT::v8i32, 7 }, // pmuludq+mul+sub sequence 403 }; 404 405 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 406 ST->hasAVX2()) { 407 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 408 LT.second)) 409 return LT.first * Entry->Cost; 410 } 411 412 static const CostTblEntry SSE2UniformConstCostTable[] = { 413 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 414 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 415 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 416 417 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 418 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 419 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 420 421 { ISD::SDIV, MVT::v8i32, 12+2 }, // 2*pmuludq sequence + split. 422 { ISD::SREM, MVT::v8i32, 16+2 }, // 2*pmuludq+mul+sub sequence + split. 423 { ISD::SDIV, MVT::v4i32, 6 }, // pmuludq sequence 424 { ISD::SREM, MVT::v4i32, 8 }, // pmuludq+mul+sub sequence 425 { ISD::UDIV, MVT::v8i32, 10+2 }, // 2*pmuludq sequence + split. 426 { ISD::UREM, MVT::v8i32, 14+2 }, // 2*pmuludq+mul+sub sequence + split. 427 { ISD::UDIV, MVT::v4i32, 5 }, // pmuludq sequence 428 { ISD::UREM, MVT::v4i32, 7 }, // pmuludq+mul+sub sequence 429 }; 430 431 // XOP has faster vXi8 shifts. 432 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 433 ST->hasSSE2() && !ST->hasXOP()) { 434 if (const auto *Entry = 435 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 436 return LT.first * Entry->Cost; 437 } 438 439 static const CostTblEntry AVX512BWConstCostTable[] = { 440 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 441 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 442 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 443 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 444 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 445 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 446 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 447 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 448 }; 449 450 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 451 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 452 ST->hasBWI()) { 453 if (const auto *Entry = 454 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 455 return LT.first * Entry->Cost; 456 } 457 458 static const CostTblEntry AVX512ConstCostTable[] = { 459 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 460 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 461 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 462 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 463 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 464 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 465 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 466 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 467 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 468 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 469 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 470 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 471 }; 472 473 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 474 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 475 ST->hasAVX512()) { 476 if (const auto *Entry = 477 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 478 return LT.first * Entry->Cost; 479 } 480 481 static const CostTblEntry AVX2ConstCostTable[] = { 482 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 483 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 484 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 485 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 486 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 487 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 488 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 489 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 490 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 491 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 492 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 493 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 494 }; 495 496 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 497 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 498 ST->hasAVX2()) { 499 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 500 return LT.first * Entry->Cost; 501 } 502 503 static const CostTblEntry SSE2ConstCostTable[] = { 504 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 505 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 506 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 507 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 508 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 509 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 510 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 511 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 512 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 513 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 514 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 515 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 516 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 517 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 518 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 519 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 520 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 521 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 522 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 523 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 524 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 525 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 526 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 527 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 528 }; 529 530 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 531 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 532 ST->hasSSE2()) { 533 // pmuldq sequence. 534 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 535 return LT.first * 32; 536 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 537 return LT.first * 38; 538 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 539 return LT.first * 15; 540 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 541 return LT.first * 20; 542 543 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 544 return LT.first * Entry->Cost; 545 } 546 547 static const CostTblEntry AVX512BWShiftCostTable[] = { 548 { ISD::SHL, MVT::v16i8, 4 }, // extend/vpsllvw/pack sequence. 549 { ISD::SRL, MVT::v16i8, 4 }, // extend/vpsrlvw/pack sequence. 550 { ISD::SRA, MVT::v16i8, 4 }, // extend/vpsravw/pack sequence. 551 { ISD::SHL, MVT::v32i8, 4 }, // extend/vpsllvw/pack sequence. 552 { ISD::SRL, MVT::v32i8, 4 }, // extend/vpsrlvw/pack sequence. 553 { ISD::SRA, MVT::v32i8, 6 }, // extend/vpsravw/pack sequence. 554 { ISD::SHL, MVT::v64i8, 6 }, // extend/vpsllvw/pack sequence. 555 { ISD::SRL, MVT::v64i8, 7 }, // extend/vpsrlvw/pack sequence. 556 { ISD::SRA, MVT::v64i8, 15 }, // extend/vpsravw/pack sequence. 557 558 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 559 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 560 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 561 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 562 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 563 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 564 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 565 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 566 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 567 }; 568 569 if (ST->hasBWI()) 570 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 571 return LT.first * Entry->Cost; 572 573 static const CostTblEntry AVX2UniformCostTable[] = { 574 // Uniform splats are cheaper for the following instructions. 575 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 576 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 577 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 578 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 579 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 580 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 581 582 { ISD::SHL, MVT::v8i32, 1 }, // pslld 583 { ISD::SRL, MVT::v8i32, 1 }, // psrld 584 { ISD::SRA, MVT::v8i32, 1 }, // psrad 585 { ISD::SHL, MVT::v4i64, 1 }, // psllq 586 { ISD::SRL, MVT::v4i64, 1 }, // psrlq 587 }; 588 589 if (ST->hasAVX2() && 590 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 591 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 592 if (const auto *Entry = 593 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 594 return LT.first * Entry->Cost; 595 } 596 597 static const CostTblEntry SSE2UniformCostTable[] = { 598 // Uniform splats are cheaper for the following instructions. 599 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 600 { ISD::SHL, MVT::v4i32, 1 }, // pslld 601 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 602 603 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 604 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 605 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 606 607 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 608 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 609 }; 610 611 if (ST->hasSSE2() && 612 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 613 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 614 if (const auto *Entry = 615 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 616 return LT.first * Entry->Cost; 617 } 618 619 static const CostTblEntry AVX512DQCostTable[] = { 620 { ISD::MUL, MVT::v2i64, 2 }, // pmullq 621 { ISD::MUL, MVT::v4i64, 2 }, // pmullq 622 { ISD::MUL, MVT::v8i64, 2 } // pmullq 623 }; 624 625 // Look for AVX512DQ lowering tricks for custom cases. 626 if (ST->hasDQI()) 627 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 628 return LT.first * Entry->Cost; 629 630 static const CostTblEntry AVX512BWCostTable[] = { 631 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 632 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 633 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 634 }; 635 636 // Look for AVX512BW lowering tricks for custom cases. 637 if (ST->hasBWI()) 638 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 639 return LT.first * Entry->Cost; 640 641 static const CostTblEntry AVX512CostTable[] = { 642 { ISD::SHL, MVT::v4i32, 1 }, 643 { ISD::SRL, MVT::v4i32, 1 }, 644 { ISD::SRA, MVT::v4i32, 1 }, 645 { ISD::SHL, MVT::v8i32, 1 }, 646 { ISD::SRL, MVT::v8i32, 1 }, 647 { ISD::SRA, MVT::v8i32, 1 }, 648 { ISD::SHL, MVT::v16i32, 1 }, 649 { ISD::SRL, MVT::v16i32, 1 }, 650 { ISD::SRA, MVT::v16i32, 1 }, 651 652 { ISD::SHL, MVT::v2i64, 1 }, 653 { ISD::SRL, MVT::v2i64, 1 }, 654 { ISD::SHL, MVT::v4i64, 1 }, 655 { ISD::SRL, MVT::v4i64, 1 }, 656 { ISD::SHL, MVT::v8i64, 1 }, 657 { ISD::SRL, MVT::v8i64, 1 }, 658 659 { ISD::SRA, MVT::v2i64, 1 }, 660 { ISD::SRA, MVT::v4i64, 1 }, 661 { ISD::SRA, MVT::v8i64, 1 }, 662 663 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 664 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 665 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 666 { ISD::MUL, MVT::v8i64, 6 }, // 3*pmuludq/3*shift/2*add 667 { ISD::MUL, MVT::i64, 1 }, // Skylake from http://www.agner.org/ 668 669 { ISD::FNEG, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 670 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 671 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 672 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 673 { ISD::FDIV, MVT::f64, 4 }, // Skylake from http://www.agner.org/ 674 { ISD::FDIV, MVT::v2f64, 4 }, // Skylake from http://www.agner.org/ 675 { ISD::FDIV, MVT::v4f64, 8 }, // Skylake from http://www.agner.org/ 676 { ISD::FDIV, MVT::v8f64, 16 }, // Skylake from http://www.agner.org/ 677 678 { ISD::FNEG, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 679 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 680 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 681 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 682 { ISD::FDIV, MVT::f32, 3 }, // Skylake from http://www.agner.org/ 683 { ISD::FDIV, MVT::v4f32, 3 }, // Skylake from http://www.agner.org/ 684 { ISD::FDIV, MVT::v8f32, 5 }, // Skylake from http://www.agner.org/ 685 { ISD::FDIV, MVT::v16f32, 10 }, // Skylake from http://www.agner.org/ 686 }; 687 688 if (ST->hasAVX512()) 689 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 690 return LT.first * Entry->Cost; 691 692 static const CostTblEntry AVX2ShiftCostTable[] = { 693 // Shifts on vXi64/vXi32 on AVX2 is legal even though we declare to 694 // customize them to detect the cases where shift amount is a scalar one. 695 { ISD::SHL, MVT::v4i32, 2 }, // vpsllvd (Haswell from agner.org) 696 { ISD::SRL, MVT::v4i32, 2 }, // vpsrlvd (Haswell from agner.org) 697 { ISD::SRA, MVT::v4i32, 2 }, // vpsravd (Haswell from agner.org) 698 { ISD::SHL, MVT::v8i32, 2 }, // vpsllvd (Haswell from agner.org) 699 { ISD::SRL, MVT::v8i32, 2 }, // vpsrlvd (Haswell from agner.org) 700 { ISD::SRA, MVT::v8i32, 2 }, // vpsravd (Haswell from agner.org) 701 { ISD::SHL, MVT::v2i64, 1 }, // vpsllvq (Haswell from agner.org) 702 { ISD::SRL, MVT::v2i64, 1 }, // vpsrlvq (Haswell from agner.org) 703 { ISD::SHL, MVT::v4i64, 1 }, // vpsllvq (Haswell from agner.org) 704 { ISD::SRL, MVT::v4i64, 1 }, // vpsrlvq (Haswell from agner.org) 705 }; 706 707 if (ST->hasAVX512()) { 708 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 709 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 710 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 711 // On AVX512, a packed v32i16 shift left by a constant build_vector 712 // is lowered into a vector multiply (vpmullw). 713 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 714 Op1Info, Op2Info, 715 TargetTransformInfo::OP_None, 716 TargetTransformInfo::OP_None); 717 } 718 719 // Look for AVX2 lowering tricks (XOP is always better at v4i32 shifts). 720 if (ST->hasAVX2() && !(ST->hasXOP() && LT.second == MVT::v4i32)) { 721 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 722 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 723 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 724 // On AVX2, a packed v16i16 shift left by a constant build_vector 725 // is lowered into a vector multiply (vpmullw). 726 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 727 Op1Info, Op2Info, 728 TargetTransformInfo::OP_None, 729 TargetTransformInfo::OP_None); 730 731 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 732 return LT.first * Entry->Cost; 733 } 734 735 static const CostTblEntry XOPShiftCostTable[] = { 736 // 128bit shifts take 1cy, but right shifts require negation beforehand. 737 { ISD::SHL, MVT::v16i8, 1 }, 738 { ISD::SRL, MVT::v16i8, 2 }, 739 { ISD::SRA, MVT::v16i8, 2 }, 740 { ISD::SHL, MVT::v8i16, 1 }, 741 { ISD::SRL, MVT::v8i16, 2 }, 742 { ISD::SRA, MVT::v8i16, 2 }, 743 { ISD::SHL, MVT::v4i32, 1 }, 744 { ISD::SRL, MVT::v4i32, 2 }, 745 { ISD::SRA, MVT::v4i32, 2 }, 746 { ISD::SHL, MVT::v2i64, 1 }, 747 { ISD::SRL, MVT::v2i64, 2 }, 748 { ISD::SRA, MVT::v2i64, 2 }, 749 // 256bit shifts require splitting if AVX2 didn't catch them above. 750 { ISD::SHL, MVT::v32i8, 2+2 }, 751 { ISD::SRL, MVT::v32i8, 4+2 }, 752 { ISD::SRA, MVT::v32i8, 4+2 }, 753 { ISD::SHL, MVT::v16i16, 2+2 }, 754 { ISD::SRL, MVT::v16i16, 4+2 }, 755 { ISD::SRA, MVT::v16i16, 4+2 }, 756 { ISD::SHL, MVT::v8i32, 2+2 }, 757 { ISD::SRL, MVT::v8i32, 4+2 }, 758 { ISD::SRA, MVT::v8i32, 4+2 }, 759 { ISD::SHL, MVT::v4i64, 2+2 }, 760 { ISD::SRL, MVT::v4i64, 4+2 }, 761 { ISD::SRA, MVT::v4i64, 4+2 }, 762 }; 763 764 // Look for XOP lowering tricks. 765 if (ST->hasXOP()) { 766 // If the right shift is constant then we'll fold the negation so 767 // it's as cheap as a left shift. 768 int ShiftISD = ISD; 769 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 770 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 771 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 772 ShiftISD = ISD::SHL; 773 if (const auto *Entry = 774 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 775 return LT.first * Entry->Cost; 776 } 777 778 static const CostTblEntry SSE2UniformShiftCostTable[] = { 779 // Uniform splats are cheaper for the following instructions. 780 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 781 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 782 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 783 784 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 785 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 786 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 787 788 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 789 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 790 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 791 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 792 }; 793 794 if (ST->hasSSE2() && 795 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 796 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 797 798 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 799 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 800 return LT.first * 4; // 2*psrad + shuffle. 801 802 if (const auto *Entry = 803 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 804 return LT.first * Entry->Cost; 805 } 806 807 if (ISD == ISD::SHL && 808 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 809 MVT VT = LT.second; 810 // Vector shift left by non uniform constant can be lowered 811 // into vector multiply. 812 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 813 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 814 ISD = ISD::MUL; 815 } 816 817 static const CostTblEntry AVX2CostTable[] = { 818 { ISD::SHL, MVT::v16i8, 6 }, // vpblendvb sequence. 819 { ISD::SHL, MVT::v32i8, 6 }, // vpblendvb sequence. 820 { ISD::SHL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 821 { ISD::SHL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 822 { ISD::SHL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 823 { ISD::SHL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 824 825 { ISD::SRL, MVT::v16i8, 6 }, // vpblendvb sequence. 826 { ISD::SRL, MVT::v32i8, 6 }, // vpblendvb sequence. 827 { ISD::SRL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 828 { ISD::SRL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 829 { ISD::SRL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 830 { ISD::SRL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 831 832 { ISD::SRA, MVT::v16i8, 17 }, // vpblendvb sequence. 833 { ISD::SRA, MVT::v32i8, 17 }, // vpblendvb sequence. 834 { ISD::SRA, MVT::v64i8, 34 }, // 2*vpblendvb sequence. 835 { ISD::SRA, MVT::v8i16, 5 }, // extend/vpsravd/pack sequence. 836 { ISD::SRA, MVT::v16i16, 7 }, // extend/vpsravd/pack sequence. 837 { ISD::SRA, MVT::v32i16, 14 }, // 2*extend/vpsravd/pack sequence. 838 { ISD::SRA, MVT::v2i64, 2 }, // srl/xor/sub sequence. 839 { ISD::SRA, MVT::v4i64, 2 }, // srl/xor/sub sequence. 840 841 { ISD::SUB, MVT::v32i8, 1 }, // psubb 842 { ISD::ADD, MVT::v32i8, 1 }, // paddb 843 { ISD::SUB, MVT::v16i16, 1 }, // psubw 844 { ISD::ADD, MVT::v16i16, 1 }, // paddw 845 { ISD::SUB, MVT::v8i32, 1 }, // psubd 846 { ISD::ADD, MVT::v8i32, 1 }, // paddd 847 { ISD::SUB, MVT::v4i64, 1 }, // psubq 848 { ISD::ADD, MVT::v4i64, 1 }, // paddq 849 850 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 851 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 852 { ISD::MUL, MVT::v4i64, 6 }, // 3*pmuludq/3*shift/2*add 853 854 { ISD::FNEG, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 855 { ISD::FNEG, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 856 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 857 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 858 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 859 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 860 { ISD::FMUL, MVT::f64, 1 }, // Haswell from http://www.agner.org/ 861 { ISD::FMUL, MVT::v2f64, 1 }, // Haswell from http://www.agner.org/ 862 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 863 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 864 865 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 866 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 867 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 868 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 869 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 870 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 871 }; 872 873 // Look for AVX2 lowering tricks for custom cases. 874 if (ST->hasAVX2()) 875 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 876 return LT.first * Entry->Cost; 877 878 static const CostTblEntry AVX1CostTable[] = { 879 // We don't have to scalarize unsupported ops. We can issue two half-sized 880 // operations and we only need to extract the upper YMM half. 881 // Two ops + 1 extract + 1 insert = 4. 882 { ISD::MUL, MVT::v16i16, 4 }, 883 { ISD::MUL, MVT::v8i32, 5 }, // BTVER2 from http://www.agner.org/ 884 { ISD::MUL, MVT::v4i64, 12 }, 885 886 { ISD::SUB, MVT::v32i8, 4 }, 887 { ISD::ADD, MVT::v32i8, 4 }, 888 { ISD::SUB, MVT::v16i16, 4 }, 889 { ISD::ADD, MVT::v16i16, 4 }, 890 { ISD::SUB, MVT::v8i32, 4 }, 891 { ISD::ADD, MVT::v8i32, 4 }, 892 { ISD::SUB, MVT::v4i64, 4 }, 893 { ISD::ADD, MVT::v4i64, 4 }, 894 895 { ISD::SHL, MVT::v32i8, 22 }, // pblendvb sequence + split. 896 { ISD::SHL, MVT::v8i16, 6 }, // pblendvb sequence. 897 { ISD::SHL, MVT::v16i16, 13 }, // pblendvb sequence + split. 898 { ISD::SHL, MVT::v4i32, 3 }, // pslld/paddd/cvttps2dq/pmulld 899 { ISD::SHL, MVT::v8i32, 9 }, // pslld/paddd/cvttps2dq/pmulld + split 900 { ISD::SHL, MVT::v2i64, 2 }, // Shift each lane + blend. 901 { ISD::SHL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 902 903 { ISD::SRL, MVT::v32i8, 23 }, // pblendvb sequence + split. 904 { ISD::SRL, MVT::v16i16, 28 }, // pblendvb sequence + split. 905 { ISD::SRL, MVT::v4i32, 6 }, // Shift each lane + blend. 906 { ISD::SRL, MVT::v8i32, 14 }, // Shift each lane + blend + split. 907 { ISD::SRL, MVT::v2i64, 2 }, // Shift each lane + blend. 908 { ISD::SRL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 909 910 { ISD::SRA, MVT::v32i8, 44 }, // pblendvb sequence + split. 911 { ISD::SRA, MVT::v16i16, 28 }, // pblendvb sequence + split. 912 { ISD::SRA, MVT::v4i32, 6 }, // Shift each lane + blend. 913 { ISD::SRA, MVT::v8i32, 14 }, // Shift each lane + blend + split. 914 { ISD::SRA, MVT::v2i64, 5 }, // Shift each lane + blend. 915 { ISD::SRA, MVT::v4i64, 12 }, // Shift each lane + blend + split. 916 917 { ISD::FNEG, MVT::v4f64, 2 }, // BTVER2 from http://www.agner.org/ 918 { ISD::FNEG, MVT::v8f32, 2 }, // BTVER2 from http://www.agner.org/ 919 920 { ISD::FMUL, MVT::f64, 2 }, // BTVER2 from http://www.agner.org/ 921 { ISD::FMUL, MVT::v2f64, 2 }, // BTVER2 from http://www.agner.org/ 922 { ISD::FMUL, MVT::v4f64, 4 }, // BTVER2 from http://www.agner.org/ 923 924 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 925 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 926 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 927 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 928 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 929 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 930 }; 931 932 if (ST->hasAVX()) 933 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 934 return LT.first * Entry->Cost; 935 936 static const CostTblEntry SSE42CostTable[] = { 937 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 938 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 939 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 940 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 941 942 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 943 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 944 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 945 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 946 947 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 948 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 949 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 950 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 951 952 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 953 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 954 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 955 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 956 957 { ISD::MUL, MVT::v2i64, 6 } // 3*pmuludq/3*shift/2*add 958 }; 959 960 if (ST->hasSSE42()) 961 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 962 return LT.first * Entry->Cost; 963 964 static const CostTblEntry SSE41CostTable[] = { 965 { ISD::SHL, MVT::v16i8, 10 }, // pblendvb sequence. 966 { ISD::SHL, MVT::v8i16, 11 }, // pblendvb sequence. 967 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 968 969 { ISD::SRL, MVT::v16i8, 11 }, // pblendvb sequence. 970 { ISD::SRL, MVT::v8i16, 13 }, // pblendvb sequence. 971 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 972 973 { ISD::SRA, MVT::v16i8, 21 }, // pblendvb sequence. 974 { ISD::SRA, MVT::v8i16, 13 }, // pblendvb sequence. 975 976 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 977 }; 978 979 if (ST->hasSSE41()) 980 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 981 return LT.first * Entry->Cost; 982 983 static const CostTblEntry SSE2CostTable[] = { 984 // We don't correctly identify costs of casts because they are marked as 985 // custom. 986 { ISD::SHL, MVT::v16i8, 13 }, // cmpgtb sequence. 987 { ISD::SHL, MVT::v8i16, 25 }, // cmpgtw sequence. 988 { ISD::SHL, MVT::v4i32, 16 }, // pslld/paddd/cvttps2dq/pmuludq. 989 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 990 991 { ISD::SRL, MVT::v16i8, 14 }, // cmpgtb sequence. 992 { ISD::SRL, MVT::v8i16, 16 }, // cmpgtw sequence. 993 { ISD::SRL, MVT::v4i32, 12 }, // Shift each lane + blend. 994 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 995 996 { ISD::SRA, MVT::v16i8, 27 }, // unpacked cmpgtb sequence. 997 { ISD::SRA, MVT::v8i16, 16 }, // cmpgtw sequence. 998 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 999 { ISD::SRA, MVT::v2i64, 8 }, // srl/xor/sub splat+shuffle sequence. 1000 1001 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 1002 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 1003 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 1004 1005 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 1006 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 1007 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 1008 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 1009 1010 { ISD::FNEG, MVT::f32, 1 }, // Pentium IV from http://www.agner.org/ 1011 { ISD::FNEG, MVT::f64, 1 }, // Pentium IV from http://www.agner.org/ 1012 { ISD::FNEG, MVT::v4f32, 1 }, // Pentium IV from http://www.agner.org/ 1013 { ISD::FNEG, MVT::v2f64, 1 }, // Pentium IV from http://www.agner.org/ 1014 1015 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 1016 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 1017 1018 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 1019 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 1020 }; 1021 1022 if (ST->hasSSE2()) 1023 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 1024 return LT.first * Entry->Cost; 1025 1026 static const CostTblEntry SSE1CostTable[] = { 1027 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 1028 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 1029 1030 { ISD::FNEG, MVT::f32, 2 }, // Pentium III from http://www.agner.org/ 1031 { ISD::FNEG, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1032 1033 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1034 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1035 1036 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1037 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1038 }; 1039 1040 if (ST->hasSSE1()) 1041 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 1042 return LT.first * Entry->Cost; 1043 1044 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 1045 { ISD::ADD, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1046 { ISD::SUB, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1047 { ISD::MUL, MVT::i64, 2 }, // Nehalem from http://www.agner.org/ 1048 }; 1049 1050 if (ST->is64Bit()) 1051 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, LT.second)) 1052 return LT.first * Entry->Cost; 1053 1054 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 1055 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1056 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1057 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1058 1059 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1060 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1061 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1062 }; 1063 1064 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, LT.second)) 1065 return LT.first * Entry->Cost; 1066 1067 // It is not a good idea to vectorize division. We have to scalarize it and 1068 // in the process we will often end up having to spilling regular 1069 // registers. The overhead of division is going to dominate most kernels 1070 // anyways so try hard to prevent vectorization of division - it is 1071 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 1072 // to hide "20 cycles" for each lane. 1073 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 1074 ISD == ISD::UDIV || ISD == ISD::UREM)) { 1075 InstructionCost ScalarCost = getArithmeticInstrCost( 1076 Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info, 1077 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 1078 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 1079 } 1080 1081 // Fallback to the default implementation. 1082 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info); 1083 } 1084 1085 InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, 1086 VectorType *BaseTp, 1087 ArrayRef<int> Mask, int Index, 1088 VectorType *SubTp, 1089 ArrayRef<const Value *> Args) { 1090 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 1091 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 1092 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 1093 1094 Kind = improveShuffleKindFromMask(Kind, Mask); 1095 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 1096 if (Kind == TTI::SK_Transpose) 1097 Kind = TTI::SK_PermuteTwoSrc; 1098 1099 // For Broadcasts we are splatting the first element from the first input 1100 // register, so only need to reference that input and all the output 1101 // registers are the same. 1102 if (Kind == TTI::SK_Broadcast) 1103 LT.first = 1; 1104 1105 // Subvector extractions are free if they start at the beginning of a 1106 // vector and cheap if the subvectors are aligned. 1107 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 1108 int NumElts = LT.second.getVectorNumElements(); 1109 if ((Index % NumElts) == 0) 1110 return 0; 1111 std::pair<InstructionCost, MVT> SubLT = 1112 TLI->getTypeLegalizationCost(DL, SubTp); 1113 if (SubLT.second.isVector()) { 1114 int NumSubElts = SubLT.second.getVectorNumElements(); 1115 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1116 return SubLT.first; 1117 // Handle some cases for widening legalization. For now we only handle 1118 // cases where the original subvector was naturally aligned and evenly 1119 // fit in its legalized subvector type. 1120 // FIXME: Remove some of the alignment restrictions. 1121 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 1122 // vectors. 1123 int OrigSubElts = cast<FixedVectorType>(SubTp)->getNumElements(); 1124 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 1125 (NumSubElts % OrigSubElts) == 0 && 1126 LT.second.getVectorElementType() == 1127 SubLT.second.getVectorElementType() && 1128 LT.second.getVectorElementType().getSizeInBits() == 1129 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 1130 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 1131 "Unexpected number of elements!"); 1132 auto *VecTy = FixedVectorType::get(BaseTp->getElementType(), 1133 LT.second.getVectorNumElements()); 1134 auto *SubTy = FixedVectorType::get(BaseTp->getElementType(), 1135 SubLT.second.getVectorNumElements()); 1136 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 1137 InstructionCost ExtractCost = getShuffleCost( 1138 TTI::SK_ExtractSubvector, VecTy, None, ExtractIndex, SubTy); 1139 1140 // If the original size is 32-bits or more, we can use pshufd. Otherwise 1141 // if we have SSSE3 we can use pshufb. 1142 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 1143 return ExtractCost + 1; // pshufd or pshufb 1144 1145 assert(SubTp->getPrimitiveSizeInBits() == 16 && 1146 "Unexpected vector size"); 1147 1148 return ExtractCost + 2; // worst case pshufhw + pshufd 1149 } 1150 } 1151 } 1152 1153 // Subvector insertions are cheap if the subvectors are aligned. 1154 // Note that in general, the insertion starting at the beginning of a vector 1155 // isn't free, because we need to preserve the rest of the wide vector. 1156 if (Kind == TTI::SK_InsertSubvector && LT.second.isVector()) { 1157 int NumElts = LT.second.getVectorNumElements(); 1158 std::pair<InstructionCost, MVT> SubLT = 1159 TLI->getTypeLegalizationCost(DL, SubTp); 1160 if (SubLT.second.isVector()) { 1161 int NumSubElts = SubLT.second.getVectorNumElements(); 1162 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1163 return SubLT.first; 1164 } 1165 1166 // If the insertion isn't aligned, treat it like a 2-op shuffle. 1167 Kind = TTI::SK_PermuteTwoSrc; 1168 } 1169 1170 // Handle some common (illegal) sub-vector types as they are often very cheap 1171 // to shuffle even on targets without PSHUFB. 1172 EVT VT = TLI->getValueType(DL, BaseTp); 1173 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 1174 !ST->hasSSSE3()) { 1175 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 1176 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 1177 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1178 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1179 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1180 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1181 1182 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1183 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1184 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1185 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1186 1187 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1188 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1189 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1190 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1191 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1192 1193 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1194 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1195 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1196 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1197 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1198 }; 1199 1200 if (ST->hasSSE2()) 1201 if (const auto *Entry = 1202 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1203 return Entry->Cost; 1204 } 1205 1206 // We are going to permute multiple sources and the result will be in multiple 1207 // destinations. Providing an accurate cost only for splits where the element 1208 // type remains the same. 1209 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1210 MVT LegalVT = LT.second; 1211 if (LegalVT.isVector() && 1212 LegalVT.getVectorElementType().getSizeInBits() == 1213 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1214 LegalVT.getVectorNumElements() < 1215 cast<FixedVectorType>(BaseTp)->getNumElements()) { 1216 1217 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1218 unsigned LegalVTSize = LegalVT.getStoreSize(); 1219 // Number of source vectors after legalization: 1220 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1221 // Number of destination vectors after legalization: 1222 InstructionCost NumOfDests = LT.first; 1223 1224 auto *SingleOpTy = FixedVectorType::get(BaseTp->getElementType(), 1225 LegalVT.getVectorNumElements()); 1226 1227 if (!Mask.empty() && NumOfDests.isValid()) { 1228 // Try to perform better estimation of the permutation. 1229 // 1. Split the source/destination vectors into real registers. 1230 // 2. Do the mask analysis to identify which real registers are 1231 // permuted. If more than 1 source registers are used for the 1232 // destination register building, the cost for this destination register 1233 // is (Number_of_source_register - 1) * Cost_PermuteTwoSrc. If only one 1234 // source register is used, build mask and calculate the cost as a cost 1235 // of PermuteSingleSrc. 1236 // Also, for the single register permute we try to identify if the 1237 // destination register is just a copy of the source register or the 1238 // copy of the previous destination register (the cost is 1239 // TTI::TCC_Basic). If the source register is just reused, the cost for 1240 // this operation is 0. 1241 unsigned E = *NumOfDests.getValue(); 1242 unsigned NormalizedVF = 1243 LegalVT.getVectorNumElements() * std::max(NumOfSrcs, E); 1244 unsigned NumOfSrcRegs = NormalizedVF / LegalVT.getVectorNumElements(); 1245 unsigned NumOfDestRegs = NormalizedVF / LegalVT.getVectorNumElements(); 1246 SmallVector<int> NormalizedMask(NormalizedVF, UndefMaskElem); 1247 copy(Mask, NormalizedMask.begin()); 1248 unsigned PrevSrcReg = 0; 1249 ArrayRef<int> PrevRegMask; 1250 InstructionCost Cost = 0; 1251 processShuffleMasks( 1252 NormalizedMask, NumOfSrcRegs, NumOfDestRegs, NumOfDestRegs, []() {}, 1253 [this, SingleOpTy, &PrevSrcReg, &PrevRegMask, 1254 &Cost](ArrayRef<int> RegMask, unsigned SrcReg, unsigned DestReg) { 1255 if (!ShuffleVectorInst::isIdentityMask(RegMask)) { 1256 // Check if the previous register can be just copied to the next 1257 // one. 1258 if (PrevRegMask.empty() || PrevSrcReg != SrcReg || 1259 PrevRegMask != RegMask) 1260 Cost += getShuffleCost(TTI::SK_PermuteSingleSrc, SingleOpTy, 1261 RegMask, 0, nullptr); 1262 else 1263 // Just a copy of previous destination register. 1264 Cost += TTI::TCC_Basic; 1265 return; 1266 } 1267 if (SrcReg != DestReg && 1268 any_of(RegMask, [](int I) { return I != UndefMaskElem; })) { 1269 // Just a copy of the source register. 1270 Cost += TTI::TCC_Basic; 1271 } 1272 PrevSrcReg = SrcReg; 1273 PrevRegMask = RegMask; 1274 }, 1275 [this, SingleOpTy, &Cost](ArrayRef<int> RegMask, 1276 unsigned /*Unused*/, 1277 unsigned /*Unused*/) { 1278 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, RegMask, 1279 0, nullptr); 1280 }); 1281 return Cost; 1282 } 1283 1284 InstructionCost NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1285 return NumOfShuffles * getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 1286 None, 0, nullptr); 1287 } 1288 1289 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1290 } 1291 1292 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1293 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1294 // We assume that source and destination have the same vector type. 1295 InstructionCost NumOfDests = LT.first; 1296 InstructionCost NumOfShufflesPerDest = LT.first * 2 - 1; 1297 LT.first = NumOfDests * NumOfShufflesPerDest; 1298 } 1299 1300 static const CostTblEntry AVX512FP16ShuffleTbl[] = { 1301 {TTI::SK_Broadcast, MVT::v32f16, 1}, // vpbroadcastw 1302 {TTI::SK_Broadcast, MVT::v16f16, 1}, // vpbroadcastw 1303 {TTI::SK_Broadcast, MVT::v8f16, 1}, // vpbroadcastw 1304 1305 {TTI::SK_Reverse, MVT::v32f16, 2}, // vpermw 1306 {TTI::SK_Reverse, MVT::v16f16, 2}, // vpermw 1307 {TTI::SK_Reverse, MVT::v8f16, 1}, // vpshufb 1308 1309 {TTI::SK_PermuteSingleSrc, MVT::v32f16, 2}, // vpermw 1310 {TTI::SK_PermuteSingleSrc, MVT::v16f16, 2}, // vpermw 1311 {TTI::SK_PermuteSingleSrc, MVT::v8f16, 1}, // vpshufb 1312 1313 {TTI::SK_PermuteTwoSrc, MVT::v32f16, 2}, // vpermt2w 1314 {TTI::SK_PermuteTwoSrc, MVT::v16f16, 2}, // vpermt2w 1315 {TTI::SK_PermuteTwoSrc, MVT::v8f16, 2} // vpermt2w 1316 }; 1317 1318 if (!ST->useSoftFloat() && ST->hasFP16()) 1319 if (const auto *Entry = 1320 CostTableLookup(AVX512FP16ShuffleTbl, Kind, LT.second)) 1321 return LT.first * Entry->Cost; 1322 1323 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1324 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1325 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1326 1327 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1328 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1329 1330 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b 1331 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b 1332 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2} // vpermt2b 1333 }; 1334 1335 if (ST->hasVBMI()) 1336 if (const auto *Entry = 1337 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1338 return LT.first * Entry->Cost; 1339 1340 static const CostTblEntry AVX512BWShuffleTbl[] = { 1341 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1342 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1343 1344 {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw 1345 {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw 1346 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1347 1348 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw 1349 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw 1350 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1351 1352 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w 1353 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w 1354 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2}, // vpermt2w 1355 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1356 1357 {TTI::SK_Select, MVT::v32i16, 1}, // vblendmw 1358 {TTI::SK_Select, MVT::v64i8, 1}, // vblendmb 1359 }; 1360 1361 if (ST->hasBWI()) 1362 if (const auto *Entry = 1363 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1364 return LT.first * Entry->Cost; 1365 1366 static const CostTblEntry AVX512ShuffleTbl[] = { 1367 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1368 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1369 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1370 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1371 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1372 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1373 1374 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1375 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1376 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1377 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1378 {TTI::SK_Reverse, MVT::v32i16, 7}, // per mca 1379 {TTI::SK_Reverse, MVT::v64i8, 7}, // per mca 1380 1381 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1382 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1383 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1384 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1385 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1386 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1387 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1388 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1389 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1390 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1391 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1392 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1393 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1394 1395 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1396 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1397 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1398 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1399 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1400 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1401 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1402 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1403 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1404 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1405 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1406 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1407 1408 // FIXME: This just applies the type legalization cost rules above 1409 // assuming these completely split. 1410 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1411 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1412 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1413 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1414 1415 {TTI::SK_Select, MVT::v32i16, 1}, // vpternlogq 1416 {TTI::SK_Select, MVT::v64i8, 1}, // vpternlogq 1417 {TTI::SK_Select, MVT::v8f64, 1}, // vblendmpd 1418 {TTI::SK_Select, MVT::v16f32, 1}, // vblendmps 1419 {TTI::SK_Select, MVT::v8i64, 1}, // vblendmq 1420 {TTI::SK_Select, MVT::v16i32, 1}, // vblendmd 1421 }; 1422 1423 if (ST->hasAVX512()) 1424 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1425 return LT.first * Entry->Cost; 1426 1427 static const CostTblEntry AVX2ShuffleTbl[] = { 1428 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1429 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1430 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1431 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1432 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1433 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1434 1435 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1436 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1437 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1438 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1439 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1440 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1441 1442 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1443 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1444 1445 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1446 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1447 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1448 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1449 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1450 // + vpblendvb 1451 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1452 // + vpblendvb 1453 1454 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1455 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1456 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1457 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1458 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1459 // + vpblendvb 1460 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1461 // + vpblendvb 1462 }; 1463 1464 if (ST->hasAVX2()) 1465 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1466 return LT.first * Entry->Cost; 1467 1468 static const CostTblEntry XOPShuffleTbl[] = { 1469 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1470 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1471 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1472 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1473 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1474 // + vinsertf128 1475 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1476 // + vinsertf128 1477 1478 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1479 // + vinsertf128 1480 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1481 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1482 // + vinsertf128 1483 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1484 }; 1485 1486 if (ST->hasXOP()) 1487 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1488 return LT.first * Entry->Cost; 1489 1490 static const CostTblEntry AVX1ShuffleTbl[] = { 1491 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1492 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1493 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1494 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1495 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1496 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1497 1498 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1499 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1500 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1501 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1502 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1503 // + vinsertf128 1504 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1505 // + vinsertf128 1506 1507 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1508 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1509 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1510 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1511 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1512 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1513 1514 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1515 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1516 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1517 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1518 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1519 // + 2*por + vinsertf128 1520 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1521 // + 2*por + vinsertf128 1522 1523 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1524 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1525 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1526 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1527 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1528 // + 4*por + vinsertf128 1529 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1530 // + 4*por + vinsertf128 1531 }; 1532 1533 if (ST->hasAVX()) 1534 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1535 return LT.first * Entry->Cost; 1536 1537 static const CostTblEntry SSE41ShuffleTbl[] = { 1538 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1539 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1540 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1541 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1542 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1543 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1544 }; 1545 1546 if (ST->hasSSE41()) 1547 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1548 return LT.first * Entry->Cost; 1549 1550 static const CostTblEntry SSSE3ShuffleTbl[] = { 1551 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1552 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1553 1554 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1555 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1556 1557 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1558 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1559 1560 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1561 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1562 1563 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1564 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1565 }; 1566 1567 if (ST->hasSSSE3()) 1568 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1569 return LT.first * Entry->Cost; 1570 1571 static const CostTblEntry SSE2ShuffleTbl[] = { 1572 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1573 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1574 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1575 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1576 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1577 1578 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1579 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1580 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1581 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1582 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1583 // + 2*pshufd + 2*unpck + packus 1584 1585 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1586 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1587 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1588 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1589 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1590 1591 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1592 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1593 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1594 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1595 // + pshufd/unpck 1596 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1597 // + 2*pshufd + 2*unpck + 2*packus 1598 1599 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1600 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1601 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1602 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1603 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1604 }; 1605 1606 static const CostTblEntry SSE3BroadcastLoadTbl[] = { 1607 {TTI::SK_Broadcast, MVT::v2f64, 0}, // broadcast handled by movddup 1608 }; 1609 1610 if (ST->hasSSE2()) { 1611 bool IsLoad = 1612 llvm::any_of(Args, [](const auto &V) { return isa<LoadInst>(V); }); 1613 if (ST->hasSSE3() && IsLoad) 1614 if (const auto *Entry = 1615 CostTableLookup(SSE3BroadcastLoadTbl, Kind, LT.second)) { 1616 assert(isLegalBroadcastLoad(BaseTp->getElementType(), 1617 LT.second.getVectorElementCount()) && 1618 "Table entry missing from isLegalBroadcastLoad()"); 1619 return LT.first * Entry->Cost; 1620 } 1621 1622 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1623 return LT.first * Entry->Cost; 1624 } 1625 1626 static const CostTblEntry SSE1ShuffleTbl[] = { 1627 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1628 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1629 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1630 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1631 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1632 }; 1633 1634 if (ST->hasSSE1()) 1635 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1636 return LT.first * Entry->Cost; 1637 1638 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1639 } 1640 1641 InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, 1642 Type *Src, 1643 TTI::CastContextHint CCH, 1644 TTI::TargetCostKind CostKind, 1645 const Instruction *I) { 1646 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1647 assert(ISD && "Invalid opcode"); 1648 1649 // TODO: Allow non-throughput costs that aren't binary. 1650 auto AdjustCost = [&CostKind](InstructionCost Cost) -> InstructionCost { 1651 if (CostKind != TTI::TCK_RecipThroughput) 1652 return Cost == 0 ? 0 : 1; 1653 return Cost; 1654 }; 1655 1656 // The cost tables include both specific, custom (non-legal) src/dst type 1657 // conversions and generic, legalized types. We test for customs first, before 1658 // falling back to legalization. 1659 // FIXME: Need a better design of the cost table to handle non-simple types of 1660 // potential massive combinations (elem_num x src_type x dst_type). 1661 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1662 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1663 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1664 1665 // Mask sign extend has an instruction. 1666 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1667 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v2i1, 1 }, 1668 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1669 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v2i1, 1 }, 1670 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1671 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v4i1, 1 }, 1672 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1673 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v4i1, 1 }, 1674 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1675 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v8i1, 1 }, 1676 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1677 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1678 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1679 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1680 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1681 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1682 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v64i1, 1 }, 1683 1684 // Mask zero extend is a sext + shift. 1685 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1686 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v2i1, 2 }, 1687 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1688 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v2i1, 2 }, 1689 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1690 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v4i1, 2 }, 1691 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1692 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v4i1, 2 }, 1693 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1694 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v8i1, 2 }, 1695 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1696 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1697 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1698 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1699 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1700 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1701 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v64i1, 2 }, 1702 1703 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, 1704 { ISD::TRUNCATE, MVT::v2i1, MVT::v16i8, 2 }, 1705 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, 1706 { ISD::TRUNCATE, MVT::v2i1, MVT::v8i16, 2 }, 1707 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, 1708 { ISD::TRUNCATE, MVT::v4i1, MVT::v16i8, 2 }, 1709 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, 1710 { ISD::TRUNCATE, MVT::v4i1, MVT::v8i16, 2 }, 1711 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, 1712 { ISD::TRUNCATE, MVT::v8i1, MVT::v16i8, 2 }, 1713 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, 1714 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, 1715 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, 1716 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, 1717 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, 1718 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, 1719 { ISD::TRUNCATE, MVT::v64i1, MVT::v32i16, 2 }, 1720 1721 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, 1722 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm 1723 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // vpmovwb 1724 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // vpmovwb 1725 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // vpmovwb 1726 }; 1727 1728 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1729 // Mask sign extend has an instruction. 1730 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, 1731 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v2i1, 1 }, 1732 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, 1733 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, 1734 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, 1735 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v16i1, 1 }, 1736 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, 1737 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, 1738 1739 // Mask zero extend is a sext + shift. 1740 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, 1741 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v2i1, 2 }, 1742 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, 1743 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, 1744 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, 1745 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v16i1, 2 }, 1746 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, 1747 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1748 1749 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, 1750 { ISD::TRUNCATE, MVT::v2i1, MVT::v4i32, 2 }, 1751 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, 1752 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, 1753 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1754 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, 1755 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, 1756 { ISD::TRUNCATE, MVT::v16i1, MVT::v8i64, 2 }, 1757 1758 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1759 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1760 1761 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1762 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1763 1764 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1765 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1766 1767 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1768 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1769 }; 1770 1771 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1772 // 256-bit wide vectors. 1773 1774 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1775 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1776 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1777 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1778 1779 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1780 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1781 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1782 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd 1783 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1784 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1785 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1786 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd 1787 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd 1788 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd 1789 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd 1790 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd 1791 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq 1792 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq 1793 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq 1794 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 2 }, // vpmovdb 1795 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 2 }, // vpmovdb 1796 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, // vpmovdb 1797 { ISD::TRUNCATE, MVT::v32i8, MVT::v16i32, 2 }, // vpmovdb 1798 { ISD::TRUNCATE, MVT::v64i8, MVT::v16i32, 2 }, // vpmovdb 1799 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, // vpmovdw 1800 { ISD::TRUNCATE, MVT::v32i16, MVT::v16i32, 2 }, // vpmovdw 1801 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 2 }, // vpmovqb 1802 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 1 }, // vpshufb 1803 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, // vpmovqb 1804 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i64, 2 }, // vpmovqb 1805 { ISD::TRUNCATE, MVT::v32i8, MVT::v8i64, 2 }, // vpmovqb 1806 { ISD::TRUNCATE, MVT::v64i8, MVT::v8i64, 2 }, // vpmovqb 1807 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, // vpmovqw 1808 { ISD::TRUNCATE, MVT::v16i16, MVT::v8i64, 2 }, // vpmovqw 1809 { ISD::TRUNCATE, MVT::v32i16, MVT::v8i64, 2 }, // vpmovqw 1810 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, // vpmovqd 1811 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd 1812 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb 1813 1814 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32 1815 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, 1816 { ISD::TRUNCATE, MVT::v64i8, MVT::v32i16, 8 }, 1817 1818 // Sign extend is zmm vpternlogd+vptruncdb. 1819 // Zero extend is zmm broadcast load+vptruncdw. 1820 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 }, 1821 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 }, 1822 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, 1823 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, 1824 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, 1825 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, 1826 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 }, 1827 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 }, 1828 1829 // Sign extend is zmm vpternlogd+vptruncdw. 1830 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw. 1831 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 }, 1832 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1833 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 }, 1834 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1835 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 }, 1836 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1837 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 }, 1838 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1839 1840 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd 1841 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld 1842 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd 1843 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld 1844 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd 1845 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld 1846 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq 1847 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq 1848 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq 1849 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq 1850 1851 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd 1852 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld 1853 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq 1854 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq 1855 1856 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1857 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1858 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1859 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1860 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1861 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1862 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1863 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1864 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1865 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1866 1867 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1868 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1869 1870 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1871 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1872 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, 1873 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, 1874 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1875 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, 1876 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1877 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1878 1879 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1880 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1881 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, 1882 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, 1883 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1884 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, 1885 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1886 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1887 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1888 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1889 1890 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2 }, 1891 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f64, 7 }, 1892 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f64,15 }, 1893 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f32,11 }, 1894 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f64,31 }, 1895 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, 1896 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f64, 7 }, 1897 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f32, 5 }, 1898 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f64,15 }, 1899 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 1 }, 1900 { ISD::FP_TO_SINT, MVT::v16i32, MVT::v16f64, 3 }, 1901 1902 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1903 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, 1904 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, 1905 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1906 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, 1907 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, 1908 }; 1909 1910 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1911 // Mask sign extend has an instruction. 1912 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1913 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v2i1, 1 }, 1914 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1915 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v2i1, 1 }, 1916 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1917 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v4i1, 1 }, 1918 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1919 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v4i1, 1 }, 1920 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1921 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v8i1, 1 }, 1922 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1923 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1924 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1925 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1926 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v32i1, 1 }, 1927 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v64i1, 1 }, 1928 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v64i1, 1 }, 1929 1930 // Mask zero extend is a sext + shift. 1931 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1932 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v2i1, 2 }, 1933 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1934 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v2i1, 2 }, 1935 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1936 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v4i1, 2 }, 1937 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1938 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v4i1, 2 }, 1939 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1940 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v8i1, 2 }, 1941 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1942 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1943 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1944 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1945 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v32i1, 2 }, 1946 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v64i1, 2 }, 1947 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v64i1, 2 }, 1948 1949 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, 1950 { ISD::TRUNCATE, MVT::v2i1, MVT::v16i8, 2 }, 1951 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, 1952 { ISD::TRUNCATE, MVT::v2i1, MVT::v8i16, 2 }, 1953 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, 1954 { ISD::TRUNCATE, MVT::v4i1, MVT::v16i8, 2 }, 1955 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, 1956 { ISD::TRUNCATE, MVT::v4i1, MVT::v8i16, 2 }, 1957 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, 1958 { ISD::TRUNCATE, MVT::v8i1, MVT::v16i8, 2 }, 1959 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, 1960 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, 1961 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, 1962 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, 1963 { ISD::TRUNCATE, MVT::v32i1, MVT::v16i16, 2 }, 1964 { ISD::TRUNCATE, MVT::v64i1, MVT::v32i8, 2 }, 1965 { ISD::TRUNCATE, MVT::v64i1, MVT::v16i16, 2 }, 1966 1967 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, 1968 }; 1969 1970 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1971 // Mask sign extend has an instruction. 1972 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, 1973 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v2i1, 1 }, 1974 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, 1975 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i1, 1 }, 1976 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, 1977 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i1, 1 }, 1978 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i1, 1 }, 1979 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, 1980 1981 // Mask zero extend is a sext + shift. 1982 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, 1983 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v2i1, 2 }, 1984 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, 1985 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i1, 2 }, 1986 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, 1987 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i1, 2 }, 1988 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i1, 2 }, 1989 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, 1990 1991 { ISD::TRUNCATE, MVT::v16i1, MVT::v4i64, 2 }, 1992 { ISD::TRUNCATE, MVT::v16i1, MVT::v8i32, 2 }, 1993 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, 1994 { ISD::TRUNCATE, MVT::v2i1, MVT::v4i32, 2 }, 1995 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, 1996 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, 1997 { ISD::TRUNCATE, MVT::v8i1, MVT::v4i64, 2 }, 1998 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1999 2000 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 2001 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 2002 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 2003 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 2004 2005 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 2006 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 2007 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 2008 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 2009 2010 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v4f32, 1 }, 2011 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 2012 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 2013 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 2014 2015 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v4f32, 1 }, 2016 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 2017 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 2018 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 2019 }; 2020 2021 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 2022 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 2023 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 2024 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 2025 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 8 }, // split+2*v8i8 2026 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 2027 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 2028 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 2029 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16 2030 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // vpslld+vptestmd 2031 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd 2032 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // vpslld+vptestmd 2033 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // vpsllq+vptestmq 2034 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // vpsllq+vptestmq 2035 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // vpmovqd 2036 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, // vpmovqb 2037 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, // vpmovqw 2038 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, // vpmovwb 2039 2040 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb 2041 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb 2042 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 }, 2043 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 }, 2044 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 }, 2045 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 }, 2046 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 }, 2047 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 }, 2048 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 }, 2049 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 }, 2050 2051 // sign extend is vpcmpeq+maskedmove+vpmovdw 2052 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw 2053 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 2054 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 }, 2055 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 2056 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 }, 2057 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 2058 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 }, 2059 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 }, 2060 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 }, 2061 2062 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd 2063 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld 2064 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd 2065 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld 2066 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd 2067 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld 2068 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq 2069 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq 2070 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq 2071 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq 2072 2073 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 1 }, 2074 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 1 }, 2075 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 1 }, 2076 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 1 }, 2077 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 2078 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 2079 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 1 }, 2080 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 1 }, 2081 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 2082 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 2083 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 2084 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 2085 2086 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2087 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 1 }, 2088 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2089 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 1 }, 2090 2091 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 2092 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 2093 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2094 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 1 }, 2095 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2096 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 1 }, 2097 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 2098 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 2099 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 2100 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 2101 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 2102 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 2103 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 2104 2105 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v8f32, 2 }, 2106 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2 }, 2107 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f32, 5 }, 2108 2109 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 2110 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 2111 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 2112 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 1 }, 2113 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 2114 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 2115 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 2116 }; 2117 2118 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 2119 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 2120 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 2121 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 2122 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 2123 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 2124 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 2125 2126 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 2 }, 2127 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 2 }, 2128 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 2 }, 2129 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 2 }, 2130 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 2131 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 2132 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 2 }, 2133 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 2 }, 2134 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 2135 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 2136 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 2137 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 2138 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 2139 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 2140 2141 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 2142 2143 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 4 }, 2144 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 4 }, 2145 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i16, 1 }, 2146 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 1 }, 2147 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 1 }, 2148 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i32, 4 }, 2149 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i64, 4 }, 2150 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 1 }, 2151 { ISD::TRUNCATE, MVT::v8i16, MVT::v2i64, 1 }, 2152 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i64, 5 }, 2153 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, 2154 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 2155 2156 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 2157 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 2158 2159 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v8f32, 1 }, 2160 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 1 }, 2161 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 1 }, 2162 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 3 }, 2163 2164 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 3 }, 2165 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 3 }, 2166 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v8f32, 1 }, 2167 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 3 }, 2168 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 2169 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4 }, 2170 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 3 }, 2171 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v4f64, 4 }, 2172 2173 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 2 }, 2174 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 2 }, 2175 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 2 }, 2176 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 2177 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 2178 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 2179 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 3 }, 2180 2181 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 2 }, 2182 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 2 }, 2183 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 2 }, 2184 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 2185 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 2186 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 2187 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 2 }, 2188 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2189 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 2190 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 }, 2191 }; 2192 2193 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 2194 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 2195 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 2196 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 2197 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 2198 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 2199 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 2200 2201 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 3 }, 2202 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 3 }, 2203 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 3 }, 2204 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 3 }, 2205 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 2206 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 2207 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 3 }, 2208 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 3 }, 2209 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 2210 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 2211 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 2212 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 2213 2214 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 4 }, 2215 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 5 }, 2216 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 4 }, 2217 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 9 }, 2218 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, 11 }, 2219 2220 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 2221 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, 2222 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // and+extract+packuswb 2223 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i32, 5 }, 2224 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2225 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i64, 5 }, 2226 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i64, 3 }, // and+extract+2*packusdw 2227 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 2228 2229 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 2230 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 2231 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 2232 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 4 }, 2233 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v16i8, 2 }, 2234 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 2235 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v8i16, 2 }, 2236 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2237 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 2238 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 }, 2239 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 5 }, 2240 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 8 }, 2241 2242 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 2243 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 2244 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 2245 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 4 }, 2246 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v16i8, 2 }, 2247 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 2248 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v8i16, 2 }, 2249 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 4 }, 2250 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 4 }, 2251 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 2252 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 2253 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 2254 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 10 }, 2255 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 10 }, 2256 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 18 }, 2257 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 2258 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 10 }, 2259 2260 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v8f32, 2 }, 2261 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f64, 2 }, 2262 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v8f32, 2 }, 2263 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v4f64, 2 }, 2264 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 2 }, 2265 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f64, 2 }, 2266 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v8f32, 2 }, 2267 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v4f64, 2 }, 2268 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 2 }, 2269 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 2 }, 2270 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 5 }, 2271 2272 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v8f32, 2 }, 2273 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f64, 2 }, 2274 { ISD::FP_TO_UINT, MVT::v32i8, MVT::v8f32, 2 }, 2275 { ISD::FP_TO_UINT, MVT::v32i8, MVT::v4f64, 2 }, 2276 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 2 }, 2277 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f64, 2 }, 2278 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v8f32, 2 }, 2279 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v4f64, 2 }, 2280 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 3 }, 2281 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 2282 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 6 }, 2283 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 7 }, 2284 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v4f64, 7 }, 2285 2286 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 2287 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 2288 }; 2289 2290 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 2291 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8, 1 }, 2292 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8, 1 }, 2293 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8, 1 }, 2294 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8, 1 }, 2295 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2296 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2297 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16, 1 }, 2298 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16, 1 }, 2299 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2300 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2301 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2302 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2303 2304 // These truncates end up widening elements. 2305 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 1 }, // PMOVXZBQ 2306 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 1 }, // PMOVXZWQ 2307 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 1 }, // PMOVXZBD 2308 2309 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 2 }, 2310 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 2 }, 2311 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 2 }, 2312 2313 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 1 }, 2314 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 1 }, 2315 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 1 }, 2316 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 1 }, 2317 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 1 }, 2318 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2319 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 1 }, 2320 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2321 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 2322 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 1 }, 2323 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2324 2325 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 1 }, 2326 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 1 }, 2327 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 2328 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 2329 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 1 }, 2330 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2331 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 1 }, 2332 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2333 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 3 }, 2334 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 3 }, 2335 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 2 }, 2336 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 12 }, 2337 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 22 }, 2338 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 4 }, 2339 2340 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 1 }, 2341 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 1 }, 2342 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 1 }, 2343 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 1 }, 2344 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f32, 2 }, 2345 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v2f64, 2 }, 2346 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f32, 1 }, 2347 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v2f64, 1 }, 2348 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, 2349 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v2f64, 1 }, 2350 2351 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 1 }, 2352 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 2353 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 1 }, 2354 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 2355 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f32, 2 }, 2356 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v2f64, 2 }, 2357 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f32, 1 }, 2358 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v2f64, 1 }, 2359 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 4 }, 2360 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 2361 }; 2362 2363 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 2364 // These are somewhat magic numbers justified by comparing the 2365 // output of llvm-mca for our various supported scheduler models 2366 // and basing it off the worst case scenario. 2367 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 3 }, 2368 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 3 }, 2369 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 3 }, 2370 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 3 }, 2371 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 3 }, 2372 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 4 }, 2373 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 3 }, 2374 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 4 }, 2375 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 3 }, 2376 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4 }, 2377 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 8 }, 2378 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 8 }, 2379 2380 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 3 }, 2381 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 3 }, 2382 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 8 }, 2383 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 9 }, 2384 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 4 }, 2385 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 4 }, 2386 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 4 }, 2387 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 4 }, 2388 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 7 }, 2389 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 7 }, 2390 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 2391 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 15 }, 2392 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 18 }, 2393 2394 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 4 }, 2395 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 4 }, 2396 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 4 }, 2397 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 4 }, 2398 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f32, 6 }, 2399 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v2f64, 6 }, 2400 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f32, 5 }, 2401 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v2f64, 5 }, 2402 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 4 }, 2403 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v2f64, 4 }, 2404 2405 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 4 }, 2406 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 2407 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 4 }, 2408 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 15 }, 2409 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f32, 6 }, 2410 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v2f64, 6 }, 2411 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f32, 5 }, 2412 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v2f64, 5 }, 2413 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 8 }, 2414 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 8 }, 2415 2416 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8, 4 }, 2417 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8, 4 }, 2418 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8, 2 }, 2419 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8, 3 }, 2420 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2421 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8, 2 }, 2422 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16, 2 }, 2423 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16, 3 }, 2424 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2425 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16, 2 }, 2426 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2427 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32, 2 }, 2428 2429 // These truncates are really widening elements. 2430 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 1 }, // PSHUFD 2431 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // PUNPCKLWD+DQ 2432 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // PUNPCKLBW+WD+PSHUFD 2433 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 1 }, // PUNPCKLWD 2434 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // PUNPCKLBW+WD 2435 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 1 }, // PUNPCKLBW 2436 2437 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i16, 2 }, // PAND+PACKUSWB 2438 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 2439 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 3 }, // PAND+2*PACKUSWB 2440 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 2441 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 2442 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 3 }, 2443 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2444 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32,10 }, 2445 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 2446 { ISD::TRUNCATE, MVT::v8i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 2447 { ISD::TRUNCATE, MVT::v4i32, MVT::v2i64, 1 }, // PSHUFD 2448 }; 2449 2450 // Attempt to map directly to (simple) MVT types to let us match custom entries. 2451 EVT SrcTy = TLI->getValueType(DL, Src); 2452 EVT DstTy = TLI->getValueType(DL, Dst); 2453 2454 // The function getSimpleVT only handles simple value types. 2455 if (SrcTy.isSimple() && DstTy.isSimple()) { 2456 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 2457 MVT SimpleDstTy = DstTy.getSimpleVT(); 2458 2459 if (ST->useAVX512Regs()) { 2460 if (ST->hasBWI()) 2461 if (const auto *Entry = ConvertCostTableLookup( 2462 AVX512BWConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2463 return AdjustCost(Entry->Cost); 2464 2465 if (ST->hasDQI()) 2466 if (const auto *Entry = ConvertCostTableLookup( 2467 AVX512DQConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2468 return AdjustCost(Entry->Cost); 2469 2470 if (ST->hasAVX512()) 2471 if (const auto *Entry = ConvertCostTableLookup( 2472 AVX512FConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2473 return AdjustCost(Entry->Cost); 2474 } 2475 2476 if (ST->hasBWI()) 2477 if (const auto *Entry = ConvertCostTableLookup( 2478 AVX512BWVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2479 return AdjustCost(Entry->Cost); 2480 2481 if (ST->hasDQI()) 2482 if (const auto *Entry = ConvertCostTableLookup( 2483 AVX512DQVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2484 return AdjustCost(Entry->Cost); 2485 2486 if (ST->hasAVX512()) 2487 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2488 SimpleDstTy, SimpleSrcTy)) 2489 return AdjustCost(Entry->Cost); 2490 2491 if (ST->hasAVX2()) { 2492 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2493 SimpleDstTy, SimpleSrcTy)) 2494 return AdjustCost(Entry->Cost); 2495 } 2496 2497 if (ST->hasAVX()) { 2498 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2499 SimpleDstTy, SimpleSrcTy)) 2500 return AdjustCost(Entry->Cost); 2501 } 2502 2503 if (ST->hasSSE41()) { 2504 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2505 SimpleDstTy, SimpleSrcTy)) 2506 return AdjustCost(Entry->Cost); 2507 } 2508 2509 if (ST->hasSSE2()) { 2510 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2511 SimpleDstTy, SimpleSrcTy)) 2512 return AdjustCost(Entry->Cost); 2513 } 2514 } 2515 2516 // Fall back to legalized types. 2517 std::pair<InstructionCost, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 2518 std::pair<InstructionCost, MVT> LTDest = 2519 TLI->getTypeLegalizationCost(DL, Dst); 2520 2521 // If we're truncating to the same legalized type - just assume its free. 2522 if (ISD == ISD::TRUNCATE && LTSrc.second == LTDest.second) 2523 return TTI::TCC_Free; 2524 2525 if (ST->useAVX512Regs()) { 2526 if (ST->hasBWI()) 2527 if (const auto *Entry = ConvertCostTableLookup( 2528 AVX512BWConversionTbl, ISD, LTDest.second, LTSrc.second)) 2529 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2530 2531 if (ST->hasDQI()) 2532 if (const auto *Entry = ConvertCostTableLookup( 2533 AVX512DQConversionTbl, ISD, LTDest.second, LTSrc.second)) 2534 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2535 2536 if (ST->hasAVX512()) 2537 if (const auto *Entry = ConvertCostTableLookup( 2538 AVX512FConversionTbl, ISD, LTDest.second, LTSrc.second)) 2539 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2540 } 2541 2542 if (ST->hasBWI()) 2543 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 2544 LTDest.second, LTSrc.second)) 2545 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2546 2547 if (ST->hasDQI()) 2548 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 2549 LTDest.second, LTSrc.second)) 2550 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2551 2552 if (ST->hasAVX512()) 2553 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2554 LTDest.second, LTSrc.second)) 2555 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2556 2557 if (ST->hasAVX2()) 2558 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2559 LTDest.second, LTSrc.second)) 2560 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2561 2562 if (ST->hasAVX()) 2563 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2564 LTDest.second, LTSrc.second)) 2565 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2566 2567 if (ST->hasSSE41()) 2568 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2569 LTDest.second, LTSrc.second)) 2570 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2571 2572 if (ST->hasSSE2()) 2573 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2574 LTDest.second, LTSrc.second)) 2575 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2576 2577 // Fallback, for i8/i16 sitofp/uitofp cases we need to extend to i32 for 2578 // sitofp. 2579 if ((ISD == ISD::SINT_TO_FP || ISD == ISD::UINT_TO_FP) && 2580 1 < Src->getScalarSizeInBits() && Src->getScalarSizeInBits() < 32) { 2581 Type *ExtSrc = Src->getWithNewBitWidth(32); 2582 unsigned ExtOpc = 2583 (ISD == ISD::SINT_TO_FP) ? Instruction::SExt : Instruction::ZExt; 2584 2585 // For scalar loads the extend would be free. 2586 InstructionCost ExtCost = 0; 2587 if (!(Src->isIntegerTy() && I && isa<LoadInst>(I->getOperand(0)))) 2588 ExtCost = getCastInstrCost(ExtOpc, ExtSrc, Src, CCH, CostKind); 2589 2590 return ExtCost + getCastInstrCost(Instruction::SIToFP, Dst, ExtSrc, 2591 TTI::CastContextHint::None, CostKind); 2592 } 2593 2594 // Fallback for fptosi/fptoui i8/i16 cases we need to truncate from fptosi 2595 // i32. 2596 if ((ISD == ISD::FP_TO_SINT || ISD == ISD::FP_TO_UINT) && 2597 1 < Dst->getScalarSizeInBits() && Dst->getScalarSizeInBits() < 32) { 2598 Type *TruncDst = Dst->getWithNewBitWidth(32); 2599 return getCastInstrCost(Instruction::FPToSI, TruncDst, Src, CCH, CostKind) + 2600 getCastInstrCost(Instruction::Trunc, Dst, TruncDst, 2601 TTI::CastContextHint::None, CostKind); 2602 } 2603 2604 return AdjustCost( 2605 BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I)); 2606 } 2607 2608 InstructionCost X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 2609 Type *CondTy, 2610 CmpInst::Predicate VecPred, 2611 TTI::TargetCostKind CostKind, 2612 const Instruction *I) { 2613 // TODO: Handle other cost kinds. 2614 if (CostKind != TTI::TCK_RecipThroughput) 2615 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, 2616 I); 2617 2618 // Legalize the type. 2619 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2620 2621 MVT MTy = LT.second; 2622 2623 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2624 assert(ISD && "Invalid opcode"); 2625 2626 unsigned ExtraCost = 0; 2627 if (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp) { 2628 // Some vector comparison predicates cost extra instructions. 2629 // TODO: Should we invert this and assume worst case cmp costs 2630 // and reduce for particular predicates? 2631 if (MTy.isVector() && 2632 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 2633 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 2634 ST->hasBWI())) { 2635 // Fallback to I if a specific predicate wasn't specified. 2636 CmpInst::Predicate Pred = VecPred; 2637 if (I && (Pred == CmpInst::BAD_ICMP_PREDICATE || 2638 Pred == CmpInst::BAD_FCMP_PREDICATE)) 2639 Pred = cast<CmpInst>(I)->getPredicate(); 2640 2641 switch (Pred) { 2642 case CmpInst::Predicate::ICMP_NE: 2643 // xor(cmpeq(x,y),-1) 2644 ExtraCost = 1; 2645 break; 2646 case CmpInst::Predicate::ICMP_SGE: 2647 case CmpInst::Predicate::ICMP_SLE: 2648 // xor(cmpgt(x,y),-1) 2649 ExtraCost = 1; 2650 break; 2651 case CmpInst::Predicate::ICMP_ULT: 2652 case CmpInst::Predicate::ICMP_UGT: 2653 // cmpgt(xor(x,signbit),xor(y,signbit)) 2654 // xor(cmpeq(pmaxu(x,y),x),-1) 2655 ExtraCost = 2; 2656 break; 2657 case CmpInst::Predicate::ICMP_ULE: 2658 case CmpInst::Predicate::ICMP_UGE: 2659 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 2660 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 2661 // cmpeq(psubus(x,y),0) 2662 // cmpeq(pminu(x,y),x) 2663 ExtraCost = 1; 2664 } else { 2665 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 2666 ExtraCost = 3; 2667 } 2668 break; 2669 case CmpInst::Predicate::BAD_ICMP_PREDICATE: 2670 case CmpInst::Predicate::BAD_FCMP_PREDICATE: 2671 // Assume worst case scenario and add the maximum extra cost. 2672 ExtraCost = 3; 2673 break; 2674 default: 2675 break; 2676 } 2677 } 2678 } 2679 2680 static const CostTblEntry SLMCostTbl[] = { 2681 // slm pcmpeq/pcmpgt throughput is 2 2682 { ISD::SETCC, MVT::v2i64, 2 }, 2683 }; 2684 2685 static const CostTblEntry AVX512BWCostTbl[] = { 2686 { ISD::SETCC, MVT::v32i16, 1 }, 2687 { ISD::SETCC, MVT::v64i8, 1 }, 2688 2689 { ISD::SELECT, MVT::v32i16, 1 }, 2690 { ISD::SELECT, MVT::v64i8, 1 }, 2691 }; 2692 2693 static const CostTblEntry AVX512CostTbl[] = { 2694 { ISD::SETCC, MVT::v8i64, 1 }, 2695 { ISD::SETCC, MVT::v16i32, 1 }, 2696 { ISD::SETCC, MVT::v8f64, 1 }, 2697 { ISD::SETCC, MVT::v16f32, 1 }, 2698 2699 { ISD::SELECT, MVT::v8i64, 1 }, 2700 { ISD::SELECT, MVT::v16i32, 1 }, 2701 { ISD::SELECT, MVT::v8f64, 1 }, 2702 { ISD::SELECT, MVT::v16f32, 1 }, 2703 2704 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 2705 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 2706 2707 { ISD::SELECT, MVT::v32i16, 2 }, 2708 { ISD::SELECT, MVT::v64i8, 2 }, 2709 }; 2710 2711 static const CostTblEntry AVX2CostTbl[] = { 2712 { ISD::SETCC, MVT::v4i64, 1 }, 2713 { ISD::SETCC, MVT::v8i32, 1 }, 2714 { ISD::SETCC, MVT::v16i16, 1 }, 2715 { ISD::SETCC, MVT::v32i8, 1 }, 2716 2717 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 2718 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 2719 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 2720 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 2721 }; 2722 2723 static const CostTblEntry AVX1CostTbl[] = { 2724 { ISD::SETCC, MVT::v4f64, 1 }, 2725 { ISD::SETCC, MVT::v8f32, 1 }, 2726 // AVX1 does not support 8-wide integer compare. 2727 { ISD::SETCC, MVT::v4i64, 4 }, 2728 { ISD::SETCC, MVT::v8i32, 4 }, 2729 { ISD::SETCC, MVT::v16i16, 4 }, 2730 { ISD::SETCC, MVT::v32i8, 4 }, 2731 2732 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 2733 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 2734 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 2735 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 2736 { ISD::SELECT, MVT::v16i16, 2 }, // vandps + vandnps + vorps 2737 { ISD::SELECT, MVT::v32i8, 2 }, // vandps + vandnps + vorps 2738 }; 2739 2740 static const CostTblEntry SSE42CostTbl[] = { 2741 { ISD::SETCC, MVT::v2f64, 1 }, 2742 { ISD::SETCC, MVT::v4f32, 1 }, 2743 { ISD::SETCC, MVT::v2i64, 1 }, 2744 }; 2745 2746 static const CostTblEntry SSE41CostTbl[] = { 2747 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 2748 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 2749 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 2750 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 2751 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 2752 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 2753 }; 2754 2755 static const CostTblEntry SSE2CostTbl[] = { 2756 { ISD::SETCC, MVT::v2f64, 2 }, 2757 { ISD::SETCC, MVT::f64, 1 }, 2758 { ISD::SETCC, MVT::v2i64, 5 }, // pcmpeqd/pcmpgtd expansion 2759 { ISD::SETCC, MVT::v4i32, 1 }, 2760 { ISD::SETCC, MVT::v8i16, 1 }, 2761 { ISD::SETCC, MVT::v16i8, 1 }, 2762 2763 { ISD::SELECT, MVT::v2f64, 2 }, // andpd + andnpd + orpd 2764 { ISD::SELECT, MVT::v2i64, 2 }, // pand + pandn + por 2765 { ISD::SELECT, MVT::v4i32, 2 }, // pand + pandn + por 2766 { ISD::SELECT, MVT::v8i16, 2 }, // pand + pandn + por 2767 { ISD::SELECT, MVT::v16i8, 2 }, // pand + pandn + por 2768 }; 2769 2770 static const CostTblEntry SSE1CostTbl[] = { 2771 { ISD::SETCC, MVT::v4f32, 2 }, 2772 { ISD::SETCC, MVT::f32, 1 }, 2773 2774 { ISD::SELECT, MVT::v4f32, 2 }, // andps + andnps + orps 2775 }; 2776 2777 if (ST->useSLMArithCosts()) 2778 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2779 return LT.first * (ExtraCost + Entry->Cost); 2780 2781 if (ST->hasBWI()) 2782 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2783 return LT.first * (ExtraCost + Entry->Cost); 2784 2785 if (ST->hasAVX512()) 2786 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2787 return LT.first * (ExtraCost + Entry->Cost); 2788 2789 if (ST->hasAVX2()) 2790 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2791 return LT.first * (ExtraCost + Entry->Cost); 2792 2793 if (ST->hasAVX()) 2794 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2795 return LT.first * (ExtraCost + Entry->Cost); 2796 2797 if (ST->hasSSE42()) 2798 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2799 return LT.first * (ExtraCost + Entry->Cost); 2800 2801 if (ST->hasSSE41()) 2802 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2803 return LT.first * (ExtraCost + Entry->Cost); 2804 2805 if (ST->hasSSE2()) 2806 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2807 return LT.first * (ExtraCost + Entry->Cost); 2808 2809 if (ST->hasSSE1()) 2810 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2811 return LT.first * (ExtraCost + Entry->Cost); 2812 2813 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I); 2814 } 2815 2816 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2817 2818 InstructionCost 2819 X86TTIImpl::getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 2820 TTI::TargetCostKind CostKind) { 2821 2822 // Costs should match the codegen from: 2823 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2824 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2825 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2826 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2827 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2828 2829 // TODO: Overflow intrinsics (*ADDO, *SUBO, *MULO) with vector types are not 2830 // specialized in these tables yet. 2831 static const CostTblEntry AVX512BITALGCostTbl[] = { 2832 { ISD::CTPOP, MVT::v32i16, 1 }, 2833 { ISD::CTPOP, MVT::v64i8, 1 }, 2834 { ISD::CTPOP, MVT::v16i16, 1 }, 2835 { ISD::CTPOP, MVT::v32i8, 1 }, 2836 { ISD::CTPOP, MVT::v8i16, 1 }, 2837 { ISD::CTPOP, MVT::v16i8, 1 }, 2838 }; 2839 static const CostTblEntry AVX512VPOPCNTDQCostTbl[] = { 2840 { ISD::CTPOP, MVT::v8i64, 1 }, 2841 { ISD::CTPOP, MVT::v16i32, 1 }, 2842 { ISD::CTPOP, MVT::v4i64, 1 }, 2843 { ISD::CTPOP, MVT::v8i32, 1 }, 2844 { ISD::CTPOP, MVT::v2i64, 1 }, 2845 { ISD::CTPOP, MVT::v4i32, 1 }, 2846 }; 2847 static const CostTblEntry AVX512CDCostTbl[] = { 2848 { ISD::CTLZ, MVT::v8i64, 1 }, 2849 { ISD::CTLZ, MVT::v16i32, 1 }, 2850 { ISD::CTLZ, MVT::v32i16, 8 }, 2851 { ISD::CTLZ, MVT::v64i8, 20 }, 2852 { ISD::CTLZ, MVT::v4i64, 1 }, 2853 { ISD::CTLZ, MVT::v8i32, 1 }, 2854 { ISD::CTLZ, MVT::v16i16, 4 }, 2855 { ISD::CTLZ, MVT::v32i8, 10 }, 2856 { ISD::CTLZ, MVT::v2i64, 1 }, 2857 { ISD::CTLZ, MVT::v4i32, 1 }, 2858 { ISD::CTLZ, MVT::v8i16, 4 }, 2859 { ISD::CTLZ, MVT::v16i8, 4 }, 2860 }; 2861 static const CostTblEntry AVX512BWCostTbl[] = { 2862 { ISD::ABS, MVT::v32i16, 1 }, 2863 { ISD::ABS, MVT::v64i8, 1 }, 2864 { ISD::BITREVERSE, MVT::v8i64, 3 }, 2865 { ISD::BITREVERSE, MVT::v16i32, 3 }, 2866 { ISD::BITREVERSE, MVT::v32i16, 3 }, 2867 { ISD::BITREVERSE, MVT::v64i8, 2 }, 2868 { ISD::BSWAP, MVT::v8i64, 1 }, 2869 { ISD::BSWAP, MVT::v16i32, 1 }, 2870 { ISD::BSWAP, MVT::v32i16, 1 }, 2871 { ISD::CTLZ, MVT::v8i64, 23 }, 2872 { ISD::CTLZ, MVT::v16i32, 22 }, 2873 { ISD::CTLZ, MVT::v32i16, 18 }, 2874 { ISD::CTLZ, MVT::v64i8, 17 }, 2875 { ISD::CTPOP, MVT::v8i64, 7 }, 2876 { ISD::CTPOP, MVT::v16i32, 11 }, 2877 { ISD::CTPOP, MVT::v32i16, 9 }, 2878 { ISD::CTPOP, MVT::v64i8, 6 }, 2879 { ISD::CTTZ, MVT::v8i64, 10 }, 2880 { ISD::CTTZ, MVT::v16i32, 14 }, 2881 { ISD::CTTZ, MVT::v32i16, 12 }, 2882 { ISD::CTTZ, MVT::v64i8, 9 }, 2883 { ISD::SADDSAT, MVT::v32i16, 1 }, 2884 { ISD::SADDSAT, MVT::v64i8, 1 }, 2885 { ISD::SMAX, MVT::v32i16, 1 }, 2886 { ISD::SMAX, MVT::v64i8, 1 }, 2887 { ISD::SMIN, MVT::v32i16, 1 }, 2888 { ISD::SMIN, MVT::v64i8, 1 }, 2889 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2890 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2891 { ISD::UADDSAT, MVT::v32i16, 1 }, 2892 { ISD::UADDSAT, MVT::v64i8, 1 }, 2893 { ISD::UMAX, MVT::v32i16, 1 }, 2894 { ISD::UMAX, MVT::v64i8, 1 }, 2895 { ISD::UMIN, MVT::v32i16, 1 }, 2896 { ISD::UMIN, MVT::v64i8, 1 }, 2897 { ISD::USUBSAT, MVT::v32i16, 1 }, 2898 { ISD::USUBSAT, MVT::v64i8, 1 }, 2899 }; 2900 static const CostTblEntry AVX512CostTbl[] = { 2901 { ISD::ABS, MVT::v8i64, 1 }, 2902 { ISD::ABS, MVT::v16i32, 1 }, 2903 { ISD::ABS, MVT::v32i16, 2 }, 2904 { ISD::ABS, MVT::v64i8, 2 }, 2905 { ISD::ABS, MVT::v4i64, 1 }, 2906 { ISD::ABS, MVT::v2i64, 1 }, 2907 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2908 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2909 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2910 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2911 { ISD::BSWAP, MVT::v8i64, 4 }, 2912 { ISD::BSWAP, MVT::v16i32, 4 }, 2913 { ISD::BSWAP, MVT::v32i16, 4 }, 2914 { ISD::CTLZ, MVT::v8i64, 29 }, 2915 { ISD::CTLZ, MVT::v16i32, 35 }, 2916 { ISD::CTLZ, MVT::v32i16, 28 }, 2917 { ISD::CTLZ, MVT::v64i8, 18 }, 2918 { ISD::CTPOP, MVT::v8i64, 16 }, 2919 { ISD::CTPOP, MVT::v16i32, 24 }, 2920 { ISD::CTPOP, MVT::v32i16, 18 }, 2921 { ISD::CTPOP, MVT::v64i8, 12 }, 2922 { ISD::CTTZ, MVT::v8i64, 20 }, 2923 { ISD::CTTZ, MVT::v16i32, 28 }, 2924 { ISD::CTTZ, MVT::v32i16, 24 }, 2925 { ISD::CTTZ, MVT::v64i8, 18 }, 2926 { ISD::SMAX, MVT::v8i64, 1 }, 2927 { ISD::SMAX, MVT::v16i32, 1 }, 2928 { ISD::SMAX, MVT::v32i16, 2 }, 2929 { ISD::SMAX, MVT::v64i8, 2 }, 2930 { ISD::SMAX, MVT::v4i64, 1 }, 2931 { ISD::SMAX, MVT::v2i64, 1 }, 2932 { ISD::SMIN, MVT::v8i64, 1 }, 2933 { ISD::SMIN, MVT::v16i32, 1 }, 2934 { ISD::SMIN, MVT::v32i16, 2 }, 2935 { ISD::SMIN, MVT::v64i8, 2 }, 2936 { ISD::SMIN, MVT::v4i64, 1 }, 2937 { ISD::SMIN, MVT::v2i64, 1 }, 2938 { ISD::UMAX, MVT::v8i64, 1 }, 2939 { ISD::UMAX, MVT::v16i32, 1 }, 2940 { ISD::UMAX, MVT::v32i16, 2 }, 2941 { ISD::UMAX, MVT::v64i8, 2 }, 2942 { ISD::UMAX, MVT::v4i64, 1 }, 2943 { ISD::UMAX, MVT::v2i64, 1 }, 2944 { ISD::UMIN, MVT::v8i64, 1 }, 2945 { ISD::UMIN, MVT::v16i32, 1 }, 2946 { ISD::UMIN, MVT::v32i16, 2 }, 2947 { ISD::UMIN, MVT::v64i8, 2 }, 2948 { ISD::UMIN, MVT::v4i64, 1 }, 2949 { ISD::UMIN, MVT::v2i64, 1 }, 2950 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2951 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2952 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2953 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2954 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2955 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2956 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2957 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2958 { ISD::SADDSAT, MVT::v32i16, 2 }, 2959 { ISD::SADDSAT, MVT::v64i8, 2 }, 2960 { ISD::SSUBSAT, MVT::v32i16, 2 }, 2961 { ISD::SSUBSAT, MVT::v64i8, 2 }, 2962 { ISD::UADDSAT, MVT::v32i16, 2 }, 2963 { ISD::UADDSAT, MVT::v64i8, 2 }, 2964 { ISD::USUBSAT, MVT::v32i16, 2 }, 2965 { ISD::USUBSAT, MVT::v64i8, 2 }, 2966 { ISD::FMAXNUM, MVT::f32, 2 }, 2967 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2968 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2969 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2970 { ISD::FMAXNUM, MVT::f64, 2 }, 2971 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2972 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2973 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2974 }; 2975 static const CostTblEntry XOPCostTbl[] = { 2976 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2977 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2978 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2979 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2980 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2981 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2982 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2983 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2984 { ISD::BITREVERSE, MVT::i64, 3 }, 2985 { ISD::BITREVERSE, MVT::i32, 3 }, 2986 { ISD::BITREVERSE, MVT::i16, 3 }, 2987 { ISD::BITREVERSE, MVT::i8, 3 } 2988 }; 2989 static const CostTblEntry AVX2CostTbl[] = { 2990 { ISD::ABS, MVT::v4i64, 2 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2991 { ISD::ABS, MVT::v8i32, 1 }, 2992 { ISD::ABS, MVT::v16i16, 1 }, 2993 { ISD::ABS, MVT::v32i8, 1 }, 2994 { ISD::BITREVERSE, MVT::v2i64, 3 }, 2995 { ISD::BITREVERSE, MVT::v4i64, 3 }, 2996 { ISD::BITREVERSE, MVT::v4i32, 3 }, 2997 { ISD::BITREVERSE, MVT::v8i32, 3 }, 2998 { ISD::BITREVERSE, MVT::v8i16, 3 }, 2999 { ISD::BITREVERSE, MVT::v16i16, 3 }, 3000 { ISD::BITREVERSE, MVT::v16i8, 3 }, 3001 { ISD::BITREVERSE, MVT::v32i8, 3 }, 3002 { ISD::BSWAP, MVT::v4i64, 1 }, 3003 { ISD::BSWAP, MVT::v8i32, 1 }, 3004 { ISD::BSWAP, MVT::v16i16, 1 }, 3005 { ISD::CTLZ, MVT::v2i64, 7 }, 3006 { ISD::CTLZ, MVT::v4i64, 7 }, 3007 { ISD::CTLZ, MVT::v4i32, 5 }, 3008 { ISD::CTLZ, MVT::v8i32, 5 }, 3009 { ISD::CTLZ, MVT::v8i16, 4 }, 3010 { ISD::CTLZ, MVT::v16i16, 4 }, 3011 { ISD::CTLZ, MVT::v16i8, 3 }, 3012 { ISD::CTLZ, MVT::v32i8, 3 }, 3013 { ISD::CTPOP, MVT::v2i64, 3 }, 3014 { ISD::CTPOP, MVT::v4i64, 3 }, 3015 { ISD::CTPOP, MVT::v4i32, 7 }, 3016 { ISD::CTPOP, MVT::v8i32, 7 }, 3017 { ISD::CTPOP, MVT::v8i16, 3 }, 3018 { ISD::CTPOP, MVT::v16i16, 3 }, 3019 { ISD::CTPOP, MVT::v16i8, 2 }, 3020 { ISD::CTPOP, MVT::v32i8, 2 }, 3021 { ISD::CTTZ, MVT::v2i64, 4 }, 3022 { ISD::CTTZ, MVT::v4i64, 4 }, 3023 { ISD::CTTZ, MVT::v4i32, 7 }, 3024 { ISD::CTTZ, MVT::v8i32, 7 }, 3025 { ISD::CTTZ, MVT::v8i16, 4 }, 3026 { ISD::CTTZ, MVT::v16i16, 4 }, 3027 { ISD::CTTZ, MVT::v16i8, 3 }, 3028 { ISD::CTTZ, MVT::v32i8, 3 }, 3029 { ISD::SADDSAT, MVT::v16i16, 1 }, 3030 { ISD::SADDSAT, MVT::v32i8, 1 }, 3031 { ISD::SMAX, MVT::v8i32, 1 }, 3032 { ISD::SMAX, MVT::v16i16, 1 }, 3033 { ISD::SMAX, MVT::v32i8, 1 }, 3034 { ISD::SMIN, MVT::v8i32, 1 }, 3035 { ISD::SMIN, MVT::v16i16, 1 }, 3036 { ISD::SMIN, MVT::v32i8, 1 }, 3037 { ISD::SSUBSAT, MVT::v16i16, 1 }, 3038 { ISD::SSUBSAT, MVT::v32i8, 1 }, 3039 { ISD::UADDSAT, MVT::v16i16, 1 }, 3040 { ISD::UADDSAT, MVT::v32i8, 1 }, 3041 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 3042 { ISD::UMAX, MVT::v8i32, 1 }, 3043 { ISD::UMAX, MVT::v16i16, 1 }, 3044 { ISD::UMAX, MVT::v32i8, 1 }, 3045 { ISD::UMIN, MVT::v8i32, 1 }, 3046 { ISD::UMIN, MVT::v16i16, 1 }, 3047 { ISD::UMIN, MVT::v32i8, 1 }, 3048 { ISD::USUBSAT, MVT::v16i16, 1 }, 3049 { ISD::USUBSAT, MVT::v32i8, 1 }, 3050 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 3051 { ISD::FMAXNUM, MVT::v8f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 3052 { ISD::FMAXNUM, MVT::v4f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 3053 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 3054 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 3055 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 3056 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 3057 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 3058 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 3059 }; 3060 static const CostTblEntry AVX1CostTbl[] = { 3061 { ISD::ABS, MVT::v4i64, 5 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 3062 { ISD::ABS, MVT::v8i32, 3 }, 3063 { ISD::ABS, MVT::v16i16, 3 }, 3064 { ISD::ABS, MVT::v32i8, 3 }, 3065 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 3066 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 3067 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 3068 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 3069 { ISD::BSWAP, MVT::v4i64, 4 }, 3070 { ISD::BSWAP, MVT::v8i32, 4 }, 3071 { ISD::BSWAP, MVT::v16i16, 4 }, 3072 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 3073 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 3074 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 3075 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 3076 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 3077 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 3078 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 3079 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 3080 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 3081 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 3082 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 3083 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 3084 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3085 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3086 { ISD::SMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3087 { ISD::SMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3088 { ISD::SMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3089 { ISD::SMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3090 { ISD::SMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3091 { ISD::SMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3092 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3093 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3094 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3095 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3096 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 3097 { ISD::UMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3098 { ISD::UMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3099 { ISD::UMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3100 { ISD::UMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3101 { ISD::UMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3102 { ISD::UMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3103 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3104 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3105 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 3106 { ISD::FMAXNUM, MVT::f32, 3 }, // MAXSS + CMPUNORDSS + BLENDVPS 3107 { ISD::FMAXNUM, MVT::v4f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 3108 { ISD::FMAXNUM, MVT::v8f32, 5 }, // MAXPS + CMPUNORDPS + BLENDVPS + ? 3109 { ISD::FMAXNUM, MVT::f64, 3 }, // MAXSD + CMPUNORDSD + BLENDVPD 3110 { ISD::FMAXNUM, MVT::v2f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 3111 { ISD::FMAXNUM, MVT::v4f64, 5 }, // MAXPD + CMPUNORDPD + BLENDVPD + ? 3112 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 3113 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 3114 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 3115 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 3116 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 3117 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 3118 }; 3119 static const CostTblEntry GLMCostTbl[] = { 3120 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 3121 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 3122 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 3123 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 3124 }; 3125 static const CostTblEntry SLMCostTbl[] = { 3126 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 3127 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 3128 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 3129 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 3130 }; 3131 static const CostTblEntry SSE42CostTbl[] = { 3132 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 3133 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 3134 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 3135 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 3136 }; 3137 static const CostTblEntry SSE41CostTbl[] = { 3138 { ISD::ABS, MVT::v2i64, 2 }, // BLENDVPD(X,PSUBQ(0,X),X) 3139 { ISD::SMAX, MVT::v4i32, 1 }, 3140 { ISD::SMAX, MVT::v16i8, 1 }, 3141 { ISD::SMIN, MVT::v4i32, 1 }, 3142 { ISD::SMIN, MVT::v16i8, 1 }, 3143 { ISD::UMAX, MVT::v4i32, 1 }, 3144 { ISD::UMAX, MVT::v8i16, 1 }, 3145 { ISD::UMIN, MVT::v4i32, 1 }, 3146 { ISD::UMIN, MVT::v8i16, 1 }, 3147 }; 3148 static const CostTblEntry SSSE3CostTbl[] = { 3149 { ISD::ABS, MVT::v4i32, 1 }, 3150 { ISD::ABS, MVT::v8i16, 1 }, 3151 { ISD::ABS, MVT::v16i8, 1 }, 3152 { ISD::BITREVERSE, MVT::v2i64, 5 }, 3153 { ISD::BITREVERSE, MVT::v4i32, 5 }, 3154 { ISD::BITREVERSE, MVT::v8i16, 5 }, 3155 { ISD::BITREVERSE, MVT::v16i8, 5 }, 3156 { ISD::BSWAP, MVT::v2i64, 1 }, 3157 { ISD::BSWAP, MVT::v4i32, 1 }, 3158 { ISD::BSWAP, MVT::v8i16, 1 }, 3159 { ISD::CTLZ, MVT::v2i64, 23 }, 3160 { ISD::CTLZ, MVT::v4i32, 18 }, 3161 { ISD::CTLZ, MVT::v8i16, 14 }, 3162 { ISD::CTLZ, MVT::v16i8, 9 }, 3163 { ISD::CTPOP, MVT::v2i64, 7 }, 3164 { ISD::CTPOP, MVT::v4i32, 11 }, 3165 { ISD::CTPOP, MVT::v8i16, 9 }, 3166 { ISD::CTPOP, MVT::v16i8, 6 }, 3167 { ISD::CTTZ, MVT::v2i64, 10 }, 3168 { ISD::CTTZ, MVT::v4i32, 14 }, 3169 { ISD::CTTZ, MVT::v8i16, 12 }, 3170 { ISD::CTTZ, MVT::v16i8, 9 } 3171 }; 3172 static const CostTblEntry SSE2CostTbl[] = { 3173 { ISD::ABS, MVT::v2i64, 4 }, 3174 { ISD::ABS, MVT::v4i32, 3 }, 3175 { ISD::ABS, MVT::v8i16, 2 }, 3176 { ISD::ABS, MVT::v16i8, 2 }, 3177 { ISD::BITREVERSE, MVT::v2i64, 29 }, 3178 { ISD::BITREVERSE, MVT::v4i32, 27 }, 3179 { ISD::BITREVERSE, MVT::v8i16, 27 }, 3180 { ISD::BITREVERSE, MVT::v16i8, 20 }, 3181 { ISD::BSWAP, MVT::v2i64, 7 }, 3182 { ISD::BSWAP, MVT::v4i32, 7 }, 3183 { ISD::BSWAP, MVT::v8i16, 7 }, 3184 { ISD::CTLZ, MVT::v2i64, 25 }, 3185 { ISD::CTLZ, MVT::v4i32, 26 }, 3186 { ISD::CTLZ, MVT::v8i16, 20 }, 3187 { ISD::CTLZ, MVT::v16i8, 17 }, 3188 { ISD::CTPOP, MVT::v2i64, 12 }, 3189 { ISD::CTPOP, MVT::v4i32, 15 }, 3190 { ISD::CTPOP, MVT::v8i16, 13 }, 3191 { ISD::CTPOP, MVT::v16i8, 10 }, 3192 { ISD::CTTZ, MVT::v2i64, 14 }, 3193 { ISD::CTTZ, MVT::v4i32, 18 }, 3194 { ISD::CTTZ, MVT::v8i16, 16 }, 3195 { ISD::CTTZ, MVT::v16i8, 13 }, 3196 { ISD::SADDSAT, MVT::v8i16, 1 }, 3197 { ISD::SADDSAT, MVT::v16i8, 1 }, 3198 { ISD::SMAX, MVT::v8i16, 1 }, 3199 { ISD::SMIN, MVT::v8i16, 1 }, 3200 { ISD::SSUBSAT, MVT::v8i16, 1 }, 3201 { ISD::SSUBSAT, MVT::v16i8, 1 }, 3202 { ISD::UADDSAT, MVT::v8i16, 1 }, 3203 { ISD::UADDSAT, MVT::v16i8, 1 }, 3204 { ISD::UMAX, MVT::v8i16, 2 }, 3205 { ISD::UMAX, MVT::v16i8, 1 }, 3206 { ISD::UMIN, MVT::v8i16, 2 }, 3207 { ISD::UMIN, MVT::v16i8, 1 }, 3208 { ISD::USUBSAT, MVT::v8i16, 1 }, 3209 { ISD::USUBSAT, MVT::v16i8, 1 }, 3210 { ISD::FMAXNUM, MVT::f64, 4 }, 3211 { ISD::FMAXNUM, MVT::v2f64, 4 }, 3212 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 3213 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 3214 }; 3215 static const CostTblEntry SSE1CostTbl[] = { 3216 { ISD::FMAXNUM, MVT::f32, 4 }, 3217 { ISD::FMAXNUM, MVT::v4f32, 4 }, 3218 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 3219 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 3220 }; 3221 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 3222 { ISD::CTTZ, MVT::i64, 1 }, 3223 }; 3224 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 3225 { ISD::CTTZ, MVT::i32, 1 }, 3226 { ISD::CTTZ, MVT::i16, 1 }, 3227 { ISD::CTTZ, MVT::i8, 1 }, 3228 }; 3229 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 3230 { ISD::CTLZ, MVT::i64, 1 }, 3231 }; 3232 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 3233 { ISD::CTLZ, MVT::i32, 1 }, 3234 { ISD::CTLZ, MVT::i16, 1 }, 3235 { ISD::CTLZ, MVT::i8, 1 }, 3236 }; 3237 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 3238 { ISD::CTPOP, MVT::i64, 1 }, 3239 }; 3240 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 3241 { ISD::CTPOP, MVT::i32, 1 }, 3242 { ISD::CTPOP, MVT::i16, 1 }, 3243 { ISD::CTPOP, MVT::i8, 1 }, 3244 }; 3245 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 3246 { ISD::ABS, MVT::i64, 2 }, // SUB+CMOV 3247 { ISD::BITREVERSE, MVT::i64, 14 }, 3248 { ISD::BSWAP, MVT::i64, 1 }, 3249 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 3250 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 3251 { ISD::CTPOP, MVT::i64, 10 }, 3252 { ISD::SADDO, MVT::i64, 1 }, 3253 { ISD::UADDO, MVT::i64, 1 }, 3254 { ISD::UMULO, MVT::i64, 2 }, // mulq + seto 3255 }; 3256 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 3257 { ISD::ABS, MVT::i32, 2 }, // SUB+CMOV 3258 { ISD::ABS, MVT::i16, 2 }, // SUB+CMOV 3259 { ISD::BITREVERSE, MVT::i32, 14 }, 3260 { ISD::BITREVERSE, MVT::i16, 14 }, 3261 { ISD::BITREVERSE, MVT::i8, 11 }, 3262 { ISD::BSWAP, MVT::i32, 1 }, 3263 { ISD::BSWAP, MVT::i16, 1 }, // ROL 3264 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 3265 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 3266 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 3267 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 3268 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 3269 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 3270 { ISD::CTPOP, MVT::i32, 8 }, 3271 { ISD::CTPOP, MVT::i16, 9 }, 3272 { ISD::CTPOP, MVT::i8, 7 }, 3273 { ISD::SADDO, MVT::i32, 1 }, 3274 { ISD::SADDO, MVT::i16, 1 }, 3275 { ISD::SADDO, MVT::i8, 1 }, 3276 { ISD::UADDO, MVT::i32, 1 }, 3277 { ISD::UADDO, MVT::i16, 1 }, 3278 { ISD::UADDO, MVT::i8, 1 }, 3279 { ISD::UMULO, MVT::i32, 2 }, // mul + seto 3280 { ISD::UMULO, MVT::i16, 2 }, 3281 { ISD::UMULO, MVT::i8, 2 }, 3282 }; 3283 3284 Type *RetTy = ICA.getReturnType(); 3285 Type *OpTy = RetTy; 3286 Intrinsic::ID IID = ICA.getID(); 3287 unsigned ISD = ISD::DELETED_NODE; 3288 switch (IID) { 3289 default: 3290 break; 3291 case Intrinsic::abs: 3292 ISD = ISD::ABS; 3293 break; 3294 case Intrinsic::bitreverse: 3295 ISD = ISD::BITREVERSE; 3296 break; 3297 case Intrinsic::bswap: 3298 ISD = ISD::BSWAP; 3299 break; 3300 case Intrinsic::ctlz: 3301 ISD = ISD::CTLZ; 3302 break; 3303 case Intrinsic::ctpop: 3304 ISD = ISD::CTPOP; 3305 break; 3306 case Intrinsic::cttz: 3307 ISD = ISD::CTTZ; 3308 break; 3309 case Intrinsic::maxnum: 3310 case Intrinsic::minnum: 3311 // FMINNUM has same costs so don't duplicate. 3312 ISD = ISD::FMAXNUM; 3313 break; 3314 case Intrinsic::sadd_sat: 3315 ISD = ISD::SADDSAT; 3316 break; 3317 case Intrinsic::smax: 3318 ISD = ISD::SMAX; 3319 break; 3320 case Intrinsic::smin: 3321 ISD = ISD::SMIN; 3322 break; 3323 case Intrinsic::ssub_sat: 3324 ISD = ISD::SSUBSAT; 3325 break; 3326 case Intrinsic::uadd_sat: 3327 ISD = ISD::UADDSAT; 3328 break; 3329 case Intrinsic::umax: 3330 ISD = ISD::UMAX; 3331 break; 3332 case Intrinsic::umin: 3333 ISD = ISD::UMIN; 3334 break; 3335 case Intrinsic::usub_sat: 3336 ISD = ISD::USUBSAT; 3337 break; 3338 case Intrinsic::sqrt: 3339 ISD = ISD::FSQRT; 3340 break; 3341 case Intrinsic::sadd_with_overflow: 3342 case Intrinsic::ssub_with_overflow: 3343 // SSUBO has same costs so don't duplicate. 3344 ISD = ISD::SADDO; 3345 OpTy = RetTy->getContainedType(0); 3346 break; 3347 case Intrinsic::uadd_with_overflow: 3348 case Intrinsic::usub_with_overflow: 3349 // USUBO has same costs so don't duplicate. 3350 ISD = ISD::UADDO; 3351 OpTy = RetTy->getContainedType(0); 3352 break; 3353 case Intrinsic::umul_with_overflow: 3354 case Intrinsic::smul_with_overflow: 3355 // SMULO has same costs so don't duplicate. 3356 ISD = ISD::UMULO; 3357 OpTy = RetTy->getContainedType(0); 3358 break; 3359 } 3360 3361 if (ISD != ISD::DELETED_NODE) { 3362 // Legalize the type. 3363 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 3364 MVT MTy = LT.second; 3365 3366 // Attempt to lookup cost. 3367 if (ISD == ISD::BITREVERSE && ST->hasGFNI() && ST->hasSSSE3() && 3368 MTy.isVector()) { 3369 // With PSHUFB the code is very similar for all types. If we have integer 3370 // byte operations, we just need a GF2P8AFFINEQB for vXi8. For other types 3371 // we also need a PSHUFB. 3372 unsigned Cost = MTy.getVectorElementType() == MVT::i8 ? 1 : 2; 3373 3374 // Without byte operations, we need twice as many GF2P8AFFINEQB and PSHUFB 3375 // instructions. We also need an extract and an insert. 3376 if (!(MTy.is128BitVector() || (ST->hasAVX2() && MTy.is256BitVector()) || 3377 (ST->hasBWI() && MTy.is512BitVector()))) 3378 Cost = Cost * 2 + 2; 3379 3380 return LT.first * Cost; 3381 } 3382 3383 auto adjustTableCost = [](const CostTblEntry &Entry, 3384 InstructionCost LegalizationCost, 3385 FastMathFlags FMF) { 3386 // If there are no NANs to deal with, then these are reduced to a 3387 // single MIN** or MAX** instruction instead of the MIN/CMP/SELECT that we 3388 // assume is used in the non-fast case. 3389 if (Entry.ISD == ISD::FMAXNUM || Entry.ISD == ISD::FMINNUM) { 3390 if (FMF.noNaNs()) 3391 return LegalizationCost * 1; 3392 } 3393 return LegalizationCost * (int)Entry.Cost; 3394 }; 3395 3396 if (ST->useGLMDivSqrtCosts()) 3397 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 3398 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3399 3400 if (ST->useSLMArithCosts()) 3401 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 3402 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3403 3404 if (ST->hasBITALG()) 3405 if (const auto *Entry = CostTableLookup(AVX512BITALGCostTbl, ISD, MTy)) 3406 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3407 3408 if (ST->hasVPOPCNTDQ()) 3409 if (const auto *Entry = CostTableLookup(AVX512VPOPCNTDQCostTbl, ISD, MTy)) 3410 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3411 3412 if (ST->hasCDI()) 3413 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 3414 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3415 3416 if (ST->hasBWI()) 3417 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3418 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3419 3420 if (ST->hasAVX512()) 3421 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3422 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3423 3424 if (ST->hasXOP()) 3425 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3426 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3427 3428 if (ST->hasAVX2()) 3429 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3430 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3431 3432 if (ST->hasAVX()) 3433 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3434 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3435 3436 if (ST->hasSSE42()) 3437 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3438 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3439 3440 if (ST->hasSSE41()) 3441 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3442 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3443 3444 if (ST->hasSSSE3()) 3445 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 3446 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3447 3448 if (ST->hasSSE2()) 3449 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3450 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3451 3452 if (ST->hasSSE1()) 3453 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3454 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3455 3456 if (ST->hasBMI()) { 3457 if (ST->is64Bit()) 3458 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 3459 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3460 3461 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 3462 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3463 } 3464 3465 if (ST->hasLZCNT()) { 3466 if (ST->is64Bit()) 3467 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 3468 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3469 3470 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 3471 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3472 } 3473 3474 if (ST->hasPOPCNT()) { 3475 if (ST->is64Bit()) 3476 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 3477 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3478 3479 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 3480 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3481 } 3482 3483 if (ISD == ISD::BSWAP && ST->hasMOVBE() && ST->hasFastMOVBE()) { 3484 if (const Instruction *II = ICA.getInst()) { 3485 if (II->hasOneUse() && isa<StoreInst>(II->user_back())) 3486 return TTI::TCC_Free; 3487 if (auto *LI = dyn_cast<LoadInst>(II->getOperand(0))) { 3488 if (LI->hasOneUse()) 3489 return TTI::TCC_Free; 3490 } 3491 } 3492 } 3493 3494 if (ST->is64Bit()) 3495 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3496 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3497 3498 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3499 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3500 } 3501 3502 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3503 } 3504 3505 InstructionCost 3506 X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 3507 TTI::TargetCostKind CostKind) { 3508 if (ICA.isTypeBasedOnly()) 3509 return getTypeBasedIntrinsicInstrCost(ICA, CostKind); 3510 3511 static const CostTblEntry AVX512BWCostTbl[] = { 3512 { ISD::ROTL, MVT::v32i16, 2 }, 3513 { ISD::ROTL, MVT::v16i16, 2 }, 3514 { ISD::ROTL, MVT::v8i16, 2 }, 3515 { ISD::ROTL, MVT::v64i8, 5 }, 3516 { ISD::ROTL, MVT::v32i8, 5 }, 3517 { ISD::ROTL, MVT::v16i8, 5 }, 3518 { ISD::ROTR, MVT::v32i16, 2 }, 3519 { ISD::ROTR, MVT::v16i16, 2 }, 3520 { ISD::ROTR, MVT::v8i16, 2 }, 3521 { ISD::ROTR, MVT::v64i8, 5 }, 3522 { ISD::ROTR, MVT::v32i8, 5 }, 3523 { ISD::ROTR, MVT::v16i8, 5 } 3524 }; 3525 static const CostTblEntry AVX512CostTbl[] = { 3526 { ISD::ROTL, MVT::v8i64, 1 }, 3527 { ISD::ROTL, MVT::v4i64, 1 }, 3528 { ISD::ROTL, MVT::v2i64, 1 }, 3529 { ISD::ROTL, MVT::v16i32, 1 }, 3530 { ISD::ROTL, MVT::v8i32, 1 }, 3531 { ISD::ROTL, MVT::v4i32, 1 }, 3532 { ISD::ROTR, MVT::v8i64, 1 }, 3533 { ISD::ROTR, MVT::v4i64, 1 }, 3534 { ISD::ROTR, MVT::v2i64, 1 }, 3535 { ISD::ROTR, MVT::v16i32, 1 }, 3536 { ISD::ROTR, MVT::v8i32, 1 }, 3537 { ISD::ROTR, MVT::v4i32, 1 } 3538 }; 3539 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 3540 static const CostTblEntry XOPCostTbl[] = { 3541 { ISD::ROTL, MVT::v4i64, 4 }, 3542 { ISD::ROTL, MVT::v8i32, 4 }, 3543 { ISD::ROTL, MVT::v16i16, 4 }, 3544 { ISD::ROTL, MVT::v32i8, 4 }, 3545 { ISD::ROTL, MVT::v2i64, 1 }, 3546 { ISD::ROTL, MVT::v4i32, 1 }, 3547 { ISD::ROTL, MVT::v8i16, 1 }, 3548 { ISD::ROTL, MVT::v16i8, 1 }, 3549 { ISD::ROTR, MVT::v4i64, 6 }, 3550 { ISD::ROTR, MVT::v8i32, 6 }, 3551 { ISD::ROTR, MVT::v16i16, 6 }, 3552 { ISD::ROTR, MVT::v32i8, 6 }, 3553 { ISD::ROTR, MVT::v2i64, 2 }, 3554 { ISD::ROTR, MVT::v4i32, 2 }, 3555 { ISD::ROTR, MVT::v8i16, 2 }, 3556 { ISD::ROTR, MVT::v16i8, 2 } 3557 }; 3558 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 3559 { ISD::ROTL, MVT::i64, 1 }, 3560 { ISD::ROTR, MVT::i64, 1 }, 3561 { ISD::FSHL, MVT::i64, 4 } 3562 }; 3563 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 3564 { ISD::ROTL, MVT::i32, 1 }, 3565 { ISD::ROTL, MVT::i16, 1 }, 3566 { ISD::ROTL, MVT::i8, 1 }, 3567 { ISD::ROTR, MVT::i32, 1 }, 3568 { ISD::ROTR, MVT::i16, 1 }, 3569 { ISD::ROTR, MVT::i8, 1 }, 3570 { ISD::FSHL, MVT::i32, 4 }, 3571 { ISD::FSHL, MVT::i16, 4 }, 3572 { ISD::FSHL, MVT::i8, 4 } 3573 }; 3574 3575 Intrinsic::ID IID = ICA.getID(); 3576 Type *RetTy = ICA.getReturnType(); 3577 const SmallVectorImpl<const Value *> &Args = ICA.getArgs(); 3578 unsigned ISD = ISD::DELETED_NODE; 3579 switch (IID) { 3580 default: 3581 break; 3582 case Intrinsic::fshl: 3583 ISD = ISD::FSHL; 3584 if (Args[0] == Args[1]) 3585 ISD = ISD::ROTL; 3586 break; 3587 case Intrinsic::fshr: 3588 // FSHR has same costs so don't duplicate. 3589 ISD = ISD::FSHL; 3590 if (Args[0] == Args[1]) 3591 ISD = ISD::ROTR; 3592 break; 3593 } 3594 3595 if (ISD != ISD::DELETED_NODE) { 3596 // Legalize the type. 3597 std::pair<InstructionCost, MVT> LT = 3598 TLI->getTypeLegalizationCost(DL, RetTy); 3599 MVT MTy = LT.second; 3600 3601 // Attempt to lookup cost. 3602 if (ST->hasBWI()) 3603 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3604 return LT.first * Entry->Cost; 3605 3606 if (ST->hasAVX512()) 3607 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3608 return LT.first * Entry->Cost; 3609 3610 if (ST->hasXOP()) 3611 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3612 return LT.first * Entry->Cost; 3613 3614 if (ST->is64Bit()) 3615 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3616 return LT.first * Entry->Cost; 3617 3618 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3619 return LT.first * Entry->Cost; 3620 } 3621 3622 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3623 } 3624 3625 InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, 3626 unsigned Index) { 3627 static const CostTblEntry SLMCostTbl[] = { 3628 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 3629 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 3630 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 3631 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 3632 }; 3633 3634 assert(Val->isVectorTy() && "This must be a vector type"); 3635 Type *ScalarType = Val->getScalarType(); 3636 int RegisterFileMoveCost = 0; 3637 3638 // Non-immediate extraction/insertion can be handled as a sequence of 3639 // aliased loads+stores via the stack. 3640 if (Index == -1U && (Opcode == Instruction::ExtractElement || 3641 Opcode == Instruction::InsertElement)) { 3642 // TODO: On some SSE41+ targets, we expand to cmp+splat+select patterns: 3643 // inselt N0, N1, N2 --> select (SplatN2 == {0,1,2...}) ? SplatN1 : N0. 3644 3645 // TODO: Move this to BasicTTIImpl.h? We'd need better gep + index handling. 3646 assert(isa<FixedVectorType>(Val) && "Fixed vector type expected"); 3647 Align VecAlign = DL.getPrefTypeAlign(Val); 3648 Align SclAlign = DL.getPrefTypeAlign(ScalarType); 3649 3650 // Extract - store vector to stack, load scalar. 3651 if (Opcode == Instruction::ExtractElement) { 3652 return getMemoryOpCost(Instruction::Store, Val, VecAlign, 0, 3653 TTI::TargetCostKind::TCK_RecipThroughput) + 3654 getMemoryOpCost(Instruction::Load, ScalarType, SclAlign, 0, 3655 TTI::TargetCostKind::TCK_RecipThroughput); 3656 } 3657 // Insert - store vector to stack, store scalar, load vector. 3658 if (Opcode == Instruction::InsertElement) { 3659 return getMemoryOpCost(Instruction::Store, Val, VecAlign, 0, 3660 TTI::TargetCostKind::TCK_RecipThroughput) + 3661 getMemoryOpCost(Instruction::Store, ScalarType, SclAlign, 0, 3662 TTI::TargetCostKind::TCK_RecipThroughput) + 3663 getMemoryOpCost(Instruction::Load, Val, VecAlign, 0, 3664 TTI::TargetCostKind::TCK_RecipThroughput); 3665 } 3666 } 3667 3668 if (Index != -1U && (Opcode == Instruction::ExtractElement || 3669 Opcode == Instruction::InsertElement)) { 3670 // Extraction of vXi1 elements are now efficiently handled by MOVMSK. 3671 if (Opcode == Instruction::ExtractElement && 3672 ScalarType->getScalarSizeInBits() == 1 && 3673 cast<FixedVectorType>(Val)->getNumElements() > 1) 3674 return 1; 3675 3676 // Legalize the type. 3677 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 3678 3679 // This type is legalized to a scalar type. 3680 if (!LT.second.isVector()) 3681 return 0; 3682 3683 // The type may be split. Normalize the index to the new type. 3684 unsigned SizeInBits = LT.second.getSizeInBits(); 3685 unsigned NumElts = LT.second.getVectorNumElements(); 3686 unsigned SubNumElts = NumElts; 3687 Index = Index % NumElts; 3688 3689 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 3690 // For inserts, we also need to insert the subvector back. 3691 if (SizeInBits > 128) { 3692 assert((SizeInBits % 128) == 0 && "Illegal vector"); 3693 unsigned NumSubVecs = SizeInBits / 128; 3694 SubNumElts = NumElts / NumSubVecs; 3695 if (SubNumElts <= Index) { 3696 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 3697 Index %= SubNumElts; 3698 } 3699 } 3700 3701 if (Index == 0) { 3702 // Floating point scalars are already located in index #0. 3703 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 3704 // true for all. 3705 if (ScalarType->isFloatingPointTy()) 3706 return RegisterFileMoveCost; 3707 3708 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 3709 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 3710 return 1 + RegisterFileMoveCost; 3711 } 3712 3713 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3714 assert(ISD && "Unexpected vector opcode"); 3715 MVT MScalarTy = LT.second.getScalarType(); 3716 if (ST->useSLMArithCosts()) 3717 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 3718 return Entry->Cost + RegisterFileMoveCost; 3719 3720 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 3721 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3722 (MScalarTy.isInteger() && ST->hasSSE41())) 3723 return 1 + RegisterFileMoveCost; 3724 3725 // Assume insertps is relatively cheap on all targets. 3726 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 3727 Opcode == Instruction::InsertElement) 3728 return 1 + RegisterFileMoveCost; 3729 3730 // For extractions we just need to shuffle the element to index 0, which 3731 // should be very cheap (assume cost = 1). For insertions we need to shuffle 3732 // the elements to its destination. In both cases we must handle the 3733 // subvector move(s). 3734 // If the vector type is already less than 128-bits then don't reduce it. 3735 // TODO: Under what circumstances should we shuffle using the full width? 3736 InstructionCost ShuffleCost = 1; 3737 if (Opcode == Instruction::InsertElement) { 3738 auto *SubTy = cast<VectorType>(Val); 3739 EVT VT = TLI->getValueType(DL, Val); 3740 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 3741 SubTy = FixedVectorType::get(ScalarType, SubNumElts); 3742 ShuffleCost = 3743 getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, None, 0, SubTy); 3744 } 3745 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 3746 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 3747 } 3748 3749 // Add to the base cost if we know that the extracted element of a vector is 3750 // destined to be moved to and used in the integer register file. 3751 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 3752 RegisterFileMoveCost += 1; 3753 3754 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 3755 } 3756 3757 InstructionCost X86TTIImpl::getScalarizationOverhead(VectorType *Ty, 3758 const APInt &DemandedElts, 3759 bool Insert, 3760 bool Extract) { 3761 InstructionCost Cost = 0; 3762 3763 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much 3764 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT. 3765 if (Insert) { 3766 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3767 MVT MScalarTy = LT.second.getScalarType(); 3768 unsigned SizeInBits = LT.second.getSizeInBits(); 3769 3770 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3771 (MScalarTy.isInteger() && ST->hasSSE41()) || 3772 (MScalarTy == MVT::f32 && ST->hasSSE41())) { 3773 // For types we can insert directly, insertion into 128-bit sub vectors is 3774 // cheap, followed by a cheap chain of concatenations. 3775 if (SizeInBits <= 128) { 3776 Cost += 3777 BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, false); 3778 } else { 3779 // In each 128-lane, if at least one index is demanded but not all 3780 // indices are demanded and this 128-lane is not the first 128-lane of 3781 // the legalized-vector, then this 128-lane needs a extracti128; If in 3782 // each 128-lane, there is at least one demanded index, this 128-lane 3783 // needs a inserti128. 3784 3785 // The following cases will help you build a better understanding: 3786 // Assume we insert several elements into a v8i32 vector in avx2, 3787 // Case#1: inserting into 1th index needs vpinsrd + inserti128. 3788 // Case#2: inserting into 5th index needs extracti128 + vpinsrd + 3789 // inserti128. 3790 // Case#3: inserting into 4,5,6,7 index needs 4*vpinsrd + inserti128. 3791 const int CostValue = *LT.first.getValue(); 3792 assert(CostValue >= 0 && "Negative cost!"); 3793 unsigned Num128Lanes = SizeInBits / 128 * CostValue; 3794 unsigned NumElts = LT.second.getVectorNumElements() * CostValue; 3795 APInt WidenedDemandedElts = DemandedElts.zextOrSelf(NumElts); 3796 unsigned Scale = NumElts / Num128Lanes; 3797 // We iterate each 128-lane, and check if we need a 3798 // extracti128/inserti128 for this 128-lane. 3799 for (unsigned I = 0; I < NumElts; I += Scale) { 3800 APInt Mask = WidenedDemandedElts.getBitsSet(NumElts, I, I + Scale); 3801 APInt MaskedDE = Mask & WidenedDemandedElts; 3802 unsigned Population = MaskedDE.countPopulation(); 3803 Cost += (Population > 0 && Population != Scale && 3804 I % LT.second.getVectorNumElements() != 0); 3805 Cost += Population > 0; 3806 } 3807 Cost += DemandedElts.countPopulation(); 3808 3809 // For vXf32 cases, insertion into the 0'th index in each v4f32 3810 // 128-bit vector is free. 3811 // NOTE: This assumes legalization widens vXf32 vectors. 3812 if (MScalarTy == MVT::f32) 3813 for (unsigned i = 0, e = cast<FixedVectorType>(Ty)->getNumElements(); 3814 i < e; i += 4) 3815 if (DemandedElts[i]) 3816 Cost--; 3817 } 3818 } else if (LT.second.isVector()) { 3819 // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded 3820 // integer element as a SCALAR_TO_VECTOR, then we build the vector as a 3821 // series of UNPCK followed by CONCAT_VECTORS - all of these can be 3822 // considered cheap. 3823 if (Ty->isIntOrIntVectorTy()) 3824 Cost += DemandedElts.countPopulation(); 3825 3826 // Get the smaller of the legalized or original pow2-extended number of 3827 // vector elements, which represents the number of unpacks we'll end up 3828 // performing. 3829 unsigned NumElts = LT.second.getVectorNumElements(); 3830 unsigned Pow2Elts = 3831 PowerOf2Ceil(cast<FixedVectorType>(Ty)->getNumElements()); 3832 Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first; 3833 } 3834 } 3835 3836 // TODO: Use default extraction for now, but we should investigate extending this 3837 // to handle repeated subvector extraction. 3838 if (Extract) 3839 Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, false, Extract); 3840 3841 return Cost; 3842 } 3843 3844 InstructionCost 3845 X86TTIImpl::getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, 3846 int VF, const APInt &DemandedDstElts, 3847 TTI::TargetCostKind CostKind) { 3848 const unsigned EltTyBits = DL.getTypeSizeInBits(EltTy); 3849 // We don't differentiate element types here, only element bit width. 3850 EltTy = IntegerType::getIntNTy(EltTy->getContext(), EltTyBits); 3851 3852 auto bailout = [&]() { 3853 return BaseT::getReplicationShuffleCost(EltTy, ReplicationFactor, VF, 3854 DemandedDstElts, CostKind); 3855 }; 3856 3857 // For now, only deal with AVX512 cases. 3858 if (!ST->hasAVX512()) 3859 return bailout(); 3860 3861 // Do we have a native shuffle for this element type, or should we promote? 3862 unsigned PromEltTyBits = EltTyBits; 3863 switch (EltTyBits) { 3864 case 32: 3865 case 64: 3866 break; // AVX512F. 3867 case 16: 3868 if (!ST->hasBWI()) 3869 PromEltTyBits = 32; // promote to i32, AVX512F. 3870 break; // AVX512BW 3871 case 8: 3872 if (!ST->hasVBMI()) 3873 PromEltTyBits = 32; // promote to i32, AVX512F. 3874 break; // AVX512VBMI 3875 case 1: 3876 // There is no support for shuffling i1 elements. We *must* promote. 3877 if (ST->hasBWI()) { 3878 if (ST->hasVBMI()) 3879 PromEltTyBits = 8; // promote to i8, AVX512VBMI. 3880 else 3881 PromEltTyBits = 16; // promote to i16, AVX512BW. 3882 break; 3883 } 3884 if (ST->hasDQI()) { 3885 PromEltTyBits = 32; // promote to i32, AVX512F. 3886 break; 3887 } 3888 return bailout(); 3889 default: 3890 return bailout(); 3891 } 3892 auto *PromEltTy = IntegerType::getIntNTy(EltTy->getContext(), PromEltTyBits); 3893 3894 auto *SrcVecTy = FixedVectorType::get(EltTy, VF); 3895 auto *PromSrcVecTy = FixedVectorType::get(PromEltTy, VF); 3896 3897 int NumDstElements = VF * ReplicationFactor; 3898 auto *PromDstVecTy = FixedVectorType::get(PromEltTy, NumDstElements); 3899 auto *DstVecTy = FixedVectorType::get(EltTy, NumDstElements); 3900 3901 // Legalize the types. 3902 MVT LegalSrcVecTy = TLI->getTypeLegalizationCost(DL, SrcVecTy).second; 3903 MVT LegalPromSrcVecTy = TLI->getTypeLegalizationCost(DL, PromSrcVecTy).second; 3904 MVT LegalPromDstVecTy = TLI->getTypeLegalizationCost(DL, PromDstVecTy).second; 3905 MVT LegalDstVecTy = TLI->getTypeLegalizationCost(DL, DstVecTy).second; 3906 // They should have legalized into vector types. 3907 if (!LegalSrcVecTy.isVector() || !LegalPromSrcVecTy.isVector() || 3908 !LegalPromDstVecTy.isVector() || !LegalDstVecTy.isVector()) 3909 return bailout(); 3910 3911 if (PromEltTyBits != EltTyBits) { 3912 // If we have to perform the shuffle with wider elt type than our data type, 3913 // then we will first need to anyext (we don't care about the new bits) 3914 // the source elements, and then truncate Dst elements. 3915 InstructionCost PromotionCost; 3916 PromotionCost += getCastInstrCost( 3917 Instruction::SExt, /*Dst=*/PromSrcVecTy, /*Src=*/SrcVecTy, 3918 TargetTransformInfo::CastContextHint::None, CostKind); 3919 PromotionCost += 3920 getCastInstrCost(Instruction::Trunc, /*Dst=*/DstVecTy, 3921 /*Src=*/PromDstVecTy, 3922 TargetTransformInfo::CastContextHint::None, CostKind); 3923 return PromotionCost + getReplicationShuffleCost(PromEltTy, 3924 ReplicationFactor, VF, 3925 DemandedDstElts, CostKind); 3926 } 3927 3928 assert(LegalSrcVecTy.getScalarSizeInBits() == EltTyBits && 3929 LegalSrcVecTy.getScalarType() == LegalDstVecTy.getScalarType() && 3930 "We expect that the legalization doesn't affect the element width, " 3931 "doesn't coalesce/split elements."); 3932 3933 unsigned NumEltsPerDstVec = LegalDstVecTy.getVectorNumElements(); 3934 unsigned NumDstVectors = 3935 divideCeil(DstVecTy->getNumElements(), NumEltsPerDstVec); 3936 3937 auto *SingleDstVecTy = FixedVectorType::get(EltTy, NumEltsPerDstVec); 3938 3939 // Not all the produced Dst elements may be demanded. In our case, 3940 // given that a single Dst vector is formed by a single shuffle, 3941 // if all elements that will form a single Dst vector aren't demanded, 3942 // then we won't need to do that shuffle, so adjust the cost accordingly. 3943 APInt DemandedDstVectors = APIntOps::ScaleBitMask( 3944 DemandedDstElts.zextOrSelf(NumDstVectors * NumEltsPerDstVec), 3945 NumDstVectors); 3946 unsigned NumDstVectorsDemanded = DemandedDstVectors.countPopulation(); 3947 3948 InstructionCost SingleShuffleCost = 3949 getShuffleCost(TTI::SK_PermuteSingleSrc, SingleDstVecTy, 3950 /*Mask=*/None, /*Index=*/0, /*SubTp=*/nullptr); 3951 return NumDstVectorsDemanded * SingleShuffleCost; 3952 } 3953 3954 InstructionCost X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 3955 MaybeAlign Alignment, 3956 unsigned AddressSpace, 3957 TTI::TargetCostKind CostKind, 3958 const Instruction *I) { 3959 // TODO: Handle other cost kinds. 3960 if (CostKind != TTI::TCK_RecipThroughput) { 3961 if (auto *SI = dyn_cast_or_null<StoreInst>(I)) { 3962 // Store instruction with index and scale costs 2 Uops. 3963 // Check the preceding GEP to identify non-const indices. 3964 if (auto *GEP = dyn_cast<GetElementPtrInst>(SI->getPointerOperand())) { 3965 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3966 return TTI::TCC_Basic * 2; 3967 } 3968 } 3969 return TTI::TCC_Basic; 3970 } 3971 3972 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 3973 "Invalid Opcode"); 3974 // Type legalization can't handle structs 3975 if (TLI->getValueType(DL, Src, true) == MVT::Other) 3976 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3977 CostKind); 3978 3979 // Legalize the type. 3980 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 3981 3982 auto *VTy = dyn_cast<FixedVectorType>(Src); 3983 3984 // Handle the simple case of non-vectors. 3985 // NOTE: this assumes that legalization never creates vector from scalars! 3986 if (!VTy || !LT.second.isVector()) 3987 // Each load/store unit costs 1. 3988 return LT.first * 1; 3989 3990 bool IsLoad = Opcode == Instruction::Load; 3991 3992 Type *EltTy = VTy->getElementType(); 3993 3994 const int EltTyBits = DL.getTypeSizeInBits(EltTy); 3995 3996 InstructionCost Cost = 0; 3997 3998 // Source of truth: how many elements were there in the original IR vector? 3999 const unsigned SrcNumElt = VTy->getNumElements(); 4000 4001 // How far have we gotten? 4002 int NumEltRemaining = SrcNumElt; 4003 // Note that we intentionally capture by-reference, NumEltRemaining changes. 4004 auto NumEltDone = [&]() { return SrcNumElt - NumEltRemaining; }; 4005 4006 const int MaxLegalOpSizeBytes = divideCeil(LT.second.getSizeInBits(), 8); 4007 4008 // Note that even if we can store 64 bits of an XMM, we still operate on XMM. 4009 const unsigned XMMBits = 128; 4010 if (XMMBits % EltTyBits != 0) 4011 // Vector size must be a multiple of the element size. I.e. no padding. 4012 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 4013 CostKind); 4014 const int NumEltPerXMM = XMMBits / EltTyBits; 4015 4016 auto *XMMVecTy = FixedVectorType::get(EltTy, NumEltPerXMM); 4017 4018 for (int CurrOpSizeBytes = MaxLegalOpSizeBytes, SubVecEltsLeft = 0; 4019 NumEltRemaining > 0; CurrOpSizeBytes /= 2) { 4020 // How many elements would a single op deal with at once? 4021 if ((8 * CurrOpSizeBytes) % EltTyBits != 0) 4022 // Vector size must be a multiple of the element size. I.e. no padding. 4023 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 4024 CostKind); 4025 int CurrNumEltPerOp = (8 * CurrOpSizeBytes) / EltTyBits; 4026 4027 assert(CurrOpSizeBytes > 0 && CurrNumEltPerOp > 0 && "How'd we get here?"); 4028 assert((((NumEltRemaining * EltTyBits) < (2 * 8 * CurrOpSizeBytes)) || 4029 (CurrOpSizeBytes == MaxLegalOpSizeBytes)) && 4030 "Unless we haven't halved the op size yet, " 4031 "we have less than two op's sized units of work left."); 4032 4033 auto *CurrVecTy = CurrNumEltPerOp > NumEltPerXMM 4034 ? FixedVectorType::get(EltTy, CurrNumEltPerOp) 4035 : XMMVecTy; 4036 4037 assert(CurrVecTy->getNumElements() % CurrNumEltPerOp == 0 && 4038 "After halving sizes, the vector elt count is no longer a multiple " 4039 "of number of elements per operation?"); 4040 auto *CoalescedVecTy = 4041 CurrNumEltPerOp == 1 4042 ? CurrVecTy 4043 : FixedVectorType::get( 4044 IntegerType::get(Src->getContext(), 4045 EltTyBits * CurrNumEltPerOp), 4046 CurrVecTy->getNumElements() / CurrNumEltPerOp); 4047 assert(DL.getTypeSizeInBits(CoalescedVecTy) == 4048 DL.getTypeSizeInBits(CurrVecTy) && 4049 "coalesciing elements doesn't change vector width."); 4050 4051 while (NumEltRemaining > 0) { 4052 assert(SubVecEltsLeft >= 0 && "Subreg element count overconsumtion?"); 4053 4054 // Can we use this vector size, as per the remaining element count? 4055 // Iff the vector is naturally aligned, we can do a wide load regardless. 4056 if (NumEltRemaining < CurrNumEltPerOp && 4057 (!IsLoad || Alignment.valueOrOne() < CurrOpSizeBytes) && 4058 CurrOpSizeBytes != 1) 4059 break; // Try smalled vector size. 4060 4061 bool Is0thSubVec = (NumEltDone() % LT.second.getVectorNumElements()) == 0; 4062 4063 // If we have fully processed the previous reg, we need to replenish it. 4064 if (SubVecEltsLeft == 0) { 4065 SubVecEltsLeft += CurrVecTy->getNumElements(); 4066 // And that's free only for the 0'th subvector of a legalized vector. 4067 if (!Is0thSubVec) 4068 Cost += getShuffleCost(IsLoad ? TTI::ShuffleKind::SK_InsertSubvector 4069 : TTI::ShuffleKind::SK_ExtractSubvector, 4070 VTy, None, NumEltDone(), CurrVecTy); 4071 } 4072 4073 // While we can directly load/store ZMM, YMM, and 64-bit halves of XMM, 4074 // for smaller widths (32/16/8) we have to insert/extract them separately. 4075 // Again, it's free for the 0'th subreg (if op is 32/64 bit wide, 4076 // but let's pretend that it is also true for 16/8 bit wide ops...) 4077 if (CurrOpSizeBytes <= 32 / 8 && !Is0thSubVec) { 4078 int NumEltDoneInCurrXMM = NumEltDone() % NumEltPerXMM; 4079 assert(NumEltDoneInCurrXMM % CurrNumEltPerOp == 0 && ""); 4080 int CoalescedVecEltIdx = NumEltDoneInCurrXMM / CurrNumEltPerOp; 4081 APInt DemandedElts = 4082 APInt::getBitsSet(CoalescedVecTy->getNumElements(), 4083 CoalescedVecEltIdx, CoalescedVecEltIdx + 1); 4084 assert(DemandedElts.countPopulation() == 1 && "Inserting single value"); 4085 Cost += getScalarizationOverhead(CoalescedVecTy, DemandedElts, IsLoad, 4086 !IsLoad); 4087 } 4088 4089 // This isn't exactly right. We're using slow unaligned 32-byte accesses 4090 // as a proxy for a double-pumped AVX memory interface such as on 4091 // Sandybridge. 4092 if (CurrOpSizeBytes == 32 && ST->isUnalignedMem32Slow()) 4093 Cost += 2; 4094 else 4095 Cost += 1; 4096 4097 SubVecEltsLeft -= CurrNumEltPerOp; 4098 NumEltRemaining -= CurrNumEltPerOp; 4099 Alignment = commonAlignment(Alignment.valueOrOne(), CurrOpSizeBytes); 4100 } 4101 } 4102 4103 assert(NumEltRemaining <= 0 && "Should have processed all the elements."); 4104 4105 return Cost; 4106 } 4107 4108 InstructionCost 4109 X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, Align Alignment, 4110 unsigned AddressSpace, 4111 TTI::TargetCostKind CostKind) { 4112 bool IsLoad = (Instruction::Load == Opcode); 4113 bool IsStore = (Instruction::Store == Opcode); 4114 4115 auto *SrcVTy = dyn_cast<FixedVectorType>(SrcTy); 4116 if (!SrcVTy) 4117 // To calculate scalar take the regular cost, without mask 4118 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace, CostKind); 4119 4120 unsigned NumElem = SrcVTy->getNumElements(); 4121 auto *MaskTy = 4122 FixedVectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 4123 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, Alignment)) || 4124 (IsStore && !isLegalMaskedStore(SrcVTy, Alignment))) { 4125 // Scalarization 4126 APInt DemandedElts = APInt::getAllOnes(NumElem); 4127 InstructionCost MaskSplitCost = 4128 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 4129 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 4130 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr, 4131 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4132 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 4133 InstructionCost MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 4134 InstructionCost ValueSplitCost = 4135 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore); 4136 InstructionCost MemopCost = 4137 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4138 Alignment, AddressSpace, CostKind); 4139 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 4140 } 4141 4142 // Legalize the type. 4143 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 4144 auto VT = TLI->getValueType(DL, SrcVTy); 4145 InstructionCost Cost = 0; 4146 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 4147 LT.second.getVectorNumElements() == NumElem) 4148 // Promotion requires extend/truncate for data and a shuffle for mask. 4149 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, None, 0, nullptr) + 4150 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, None, 0, nullptr); 4151 4152 else if (LT.first * LT.second.getVectorNumElements() > NumElem) { 4153 auto *NewMaskTy = FixedVectorType::get(MaskTy->getElementType(), 4154 LT.second.getVectorNumElements()); 4155 // Expanding requires fill mask with zeroes 4156 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, None, 0, MaskTy); 4157 } 4158 4159 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 4160 if (!ST->hasAVX512()) 4161 return Cost + LT.first * (IsLoad ? 2 : 8); 4162 4163 // AVX-512 masked load/store is cheapper 4164 return Cost + LT.first; 4165 } 4166 4167 InstructionCost X86TTIImpl::getAddressComputationCost(Type *Ty, 4168 ScalarEvolution *SE, 4169 const SCEV *Ptr) { 4170 // Address computations in vectorized code with non-consecutive addresses will 4171 // likely result in more instructions compared to scalar code where the 4172 // computation can more often be merged into the index mode. The resulting 4173 // extra micro-ops can significantly decrease throughput. 4174 const unsigned NumVectorInstToHideOverhead = 10; 4175 4176 // Cost modeling of Strided Access Computation is hidden by the indexing 4177 // modes of X86 regardless of the stride value. We dont believe that there 4178 // is a difference between constant strided access in gerenal and constant 4179 // strided value which is less than or equal to 64. 4180 // Even in the case of (loop invariant) stride whose value is not known at 4181 // compile time, the address computation will not incur more than one extra 4182 // ADD instruction. 4183 if (Ty->isVectorTy() && SE && !ST->hasAVX2()) { 4184 // TODO: AVX2 is the current cut-off because we don't have correct 4185 // interleaving costs for prior ISA's. 4186 if (!BaseT::isStridedAccess(Ptr)) 4187 return NumVectorInstToHideOverhead; 4188 if (!BaseT::getConstantStrideStep(SE, Ptr)) 4189 return 1; 4190 } 4191 4192 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 4193 } 4194 4195 InstructionCost 4196 X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 4197 Optional<FastMathFlags> FMF, 4198 TTI::TargetCostKind CostKind) { 4199 if (TTI::requiresOrderedReduction(FMF)) 4200 return BaseT::getArithmeticReductionCost(Opcode, ValTy, FMF, CostKind); 4201 4202 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 4203 // and make it as the cost. 4204 4205 static const CostTblEntry SLMCostTblNoPairWise[] = { 4206 { ISD::FADD, MVT::v2f64, 3 }, 4207 { ISD::ADD, MVT::v2i64, 5 }, 4208 }; 4209 4210 static const CostTblEntry SSE2CostTblNoPairWise[] = { 4211 { ISD::FADD, MVT::v2f64, 2 }, 4212 { ISD::FADD, MVT::v2f32, 2 }, 4213 { ISD::FADD, MVT::v4f32, 4 }, 4214 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 4215 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 4216 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 4217 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 4218 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 4219 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 4220 { ISD::ADD, MVT::v2i8, 2 }, 4221 { ISD::ADD, MVT::v4i8, 2 }, 4222 { ISD::ADD, MVT::v8i8, 2 }, 4223 { ISD::ADD, MVT::v16i8, 3 }, 4224 }; 4225 4226 static const CostTblEntry AVX1CostTblNoPairWise[] = { 4227 { ISD::FADD, MVT::v4f64, 3 }, 4228 { ISD::FADD, MVT::v4f32, 3 }, 4229 { ISD::FADD, MVT::v8f32, 4 }, 4230 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 4231 { ISD::ADD, MVT::v4i64, 3 }, 4232 { ISD::ADD, MVT::v8i32, 5 }, 4233 { ISD::ADD, MVT::v16i16, 5 }, 4234 { ISD::ADD, MVT::v32i8, 4 }, 4235 }; 4236 4237 int ISD = TLI->InstructionOpcodeToISD(Opcode); 4238 assert(ISD && "Invalid opcode"); 4239 4240 // Before legalizing the type, give a chance to look up illegal narrow types 4241 // in the table. 4242 // FIXME: Is there a better way to do this? 4243 EVT VT = TLI->getValueType(DL, ValTy); 4244 if (VT.isSimple()) { 4245 MVT MTy = VT.getSimpleVT(); 4246 if (ST->useSLMArithCosts()) 4247 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 4248 return Entry->Cost; 4249 4250 if (ST->hasAVX()) 4251 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4252 return Entry->Cost; 4253 4254 if (ST->hasSSE2()) 4255 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4256 return Entry->Cost; 4257 } 4258 4259 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 4260 4261 MVT MTy = LT.second; 4262 4263 auto *ValVTy = cast<FixedVectorType>(ValTy); 4264 4265 // Special case: vXi8 mul reductions are performed as vXi16. 4266 if (ISD == ISD::MUL && MTy.getScalarType() == MVT::i8) { 4267 auto *WideSclTy = IntegerType::get(ValVTy->getContext(), 16); 4268 auto *WideVecTy = FixedVectorType::get(WideSclTy, ValVTy->getNumElements()); 4269 return getCastInstrCost(Instruction::ZExt, WideVecTy, ValTy, 4270 TargetTransformInfo::CastContextHint::None, 4271 CostKind) + 4272 getArithmeticReductionCost(Opcode, WideVecTy, FMF, CostKind); 4273 } 4274 4275 InstructionCost ArithmeticCost = 0; 4276 if (LT.first != 1 && MTy.isVector() && 4277 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4278 // Type needs to be split. We need LT.first - 1 arithmetic ops. 4279 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 4280 MTy.getVectorNumElements()); 4281 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 4282 ArithmeticCost *= LT.first - 1; 4283 } 4284 4285 if (ST->useSLMArithCosts()) 4286 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 4287 return ArithmeticCost + Entry->Cost; 4288 4289 if (ST->hasAVX()) 4290 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4291 return ArithmeticCost + Entry->Cost; 4292 4293 if (ST->hasSSE2()) 4294 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4295 return ArithmeticCost + Entry->Cost; 4296 4297 // FIXME: These assume a naive kshift+binop lowering, which is probably 4298 // conservative in most cases. 4299 static const CostTblEntry AVX512BoolReduction[] = { 4300 { ISD::AND, MVT::v2i1, 3 }, 4301 { ISD::AND, MVT::v4i1, 5 }, 4302 { ISD::AND, MVT::v8i1, 7 }, 4303 { ISD::AND, MVT::v16i1, 9 }, 4304 { ISD::AND, MVT::v32i1, 11 }, 4305 { ISD::AND, MVT::v64i1, 13 }, 4306 { ISD::OR, MVT::v2i1, 3 }, 4307 { ISD::OR, MVT::v4i1, 5 }, 4308 { ISD::OR, MVT::v8i1, 7 }, 4309 { ISD::OR, MVT::v16i1, 9 }, 4310 { ISD::OR, MVT::v32i1, 11 }, 4311 { ISD::OR, MVT::v64i1, 13 }, 4312 }; 4313 4314 static const CostTblEntry AVX2BoolReduction[] = { 4315 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 4316 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 4317 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 4318 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 4319 }; 4320 4321 static const CostTblEntry AVX1BoolReduction[] = { 4322 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 4323 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 4324 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 4325 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 4326 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 4327 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 4328 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 4329 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 4330 }; 4331 4332 static const CostTblEntry SSE2BoolReduction[] = { 4333 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 4334 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 4335 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 4336 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 4337 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 4338 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 4339 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 4340 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 4341 }; 4342 4343 // Handle bool allof/anyof patterns. 4344 if (ValVTy->getElementType()->isIntegerTy(1)) { 4345 InstructionCost ArithmeticCost = 0; 4346 if (LT.first != 1 && MTy.isVector() && 4347 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4348 // Type needs to be split. We need LT.first - 1 arithmetic ops. 4349 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 4350 MTy.getVectorNumElements()); 4351 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 4352 ArithmeticCost *= LT.first - 1; 4353 } 4354 4355 if (ST->hasAVX512()) 4356 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 4357 return ArithmeticCost + Entry->Cost; 4358 if (ST->hasAVX2()) 4359 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 4360 return ArithmeticCost + Entry->Cost; 4361 if (ST->hasAVX()) 4362 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 4363 return ArithmeticCost + Entry->Cost; 4364 if (ST->hasSSE2()) 4365 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 4366 return ArithmeticCost + Entry->Cost; 4367 4368 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, FMF, CostKind); 4369 } 4370 4371 unsigned NumVecElts = ValVTy->getNumElements(); 4372 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 4373 4374 // Special case power of 2 reductions where the scalar type isn't changed 4375 // by type legalization. 4376 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 4377 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, FMF, CostKind); 4378 4379 InstructionCost ReductionCost = 0; 4380 4381 auto *Ty = ValVTy; 4382 if (LT.first != 1 && MTy.isVector() && 4383 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4384 // Type needs to be split. We need LT.first - 1 arithmetic ops. 4385 Ty = FixedVectorType::get(ValVTy->getElementType(), 4386 MTy.getVectorNumElements()); 4387 ReductionCost = getArithmeticInstrCost(Opcode, Ty, CostKind); 4388 ReductionCost *= LT.first - 1; 4389 NumVecElts = MTy.getVectorNumElements(); 4390 } 4391 4392 // Now handle reduction with the legal type, taking into account size changes 4393 // at each level. 4394 while (NumVecElts > 1) { 4395 // Determine the size of the remaining vector we need to reduce. 4396 unsigned Size = NumVecElts * ScalarSize; 4397 NumVecElts /= 2; 4398 // If we're reducing from 256/512 bits, use an extract_subvector. 4399 if (Size > 128) { 4400 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 4401 ReductionCost += 4402 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 4403 Ty = SubTy; 4404 } else if (Size == 128) { 4405 // Reducing from 128 bits is a permute of v2f64/v2i64. 4406 FixedVectorType *ShufTy; 4407 if (ValVTy->isFloatingPointTy()) 4408 ShufTy = 4409 FixedVectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 4410 else 4411 ShufTy = 4412 FixedVectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 4413 ReductionCost += 4414 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4415 } else if (Size == 64) { 4416 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 4417 FixedVectorType *ShufTy; 4418 if (ValVTy->isFloatingPointTy()) 4419 ShufTy = 4420 FixedVectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 4421 else 4422 ShufTy = 4423 FixedVectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 4424 ReductionCost += 4425 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4426 } else { 4427 // Reducing from smaller size is a shift by immediate. 4428 auto *ShiftTy = FixedVectorType::get( 4429 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 4430 ReductionCost += getArithmeticInstrCost( 4431 Instruction::LShr, ShiftTy, CostKind, 4432 TargetTransformInfo::OK_AnyValue, 4433 TargetTransformInfo::OK_UniformConstantValue, 4434 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 4435 } 4436 4437 // Add the arithmetic op for this level. 4438 ReductionCost += getArithmeticInstrCost(Opcode, Ty, CostKind); 4439 } 4440 4441 // Add the final extract element to the cost. 4442 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 4443 } 4444 4445 InstructionCost X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, 4446 bool IsUnsigned) { 4447 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 4448 4449 MVT MTy = LT.second; 4450 4451 int ISD; 4452 if (Ty->isIntOrIntVectorTy()) { 4453 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 4454 } else { 4455 assert(Ty->isFPOrFPVectorTy() && 4456 "Expected float point or integer vector type."); 4457 ISD = ISD::FMINNUM; 4458 } 4459 4460 static const CostTblEntry SSE1CostTbl[] = { 4461 {ISD::FMINNUM, MVT::v4f32, 1}, 4462 }; 4463 4464 static const CostTblEntry SSE2CostTbl[] = { 4465 {ISD::FMINNUM, MVT::v2f64, 1}, 4466 {ISD::SMIN, MVT::v8i16, 1}, 4467 {ISD::UMIN, MVT::v16i8, 1}, 4468 }; 4469 4470 static const CostTblEntry SSE41CostTbl[] = { 4471 {ISD::SMIN, MVT::v4i32, 1}, 4472 {ISD::UMIN, MVT::v4i32, 1}, 4473 {ISD::UMIN, MVT::v8i16, 1}, 4474 {ISD::SMIN, MVT::v16i8, 1}, 4475 }; 4476 4477 static const CostTblEntry SSE42CostTbl[] = { 4478 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 4479 }; 4480 4481 static const CostTblEntry AVX1CostTbl[] = { 4482 {ISD::FMINNUM, MVT::v8f32, 1}, 4483 {ISD::FMINNUM, MVT::v4f64, 1}, 4484 {ISD::SMIN, MVT::v8i32, 3}, 4485 {ISD::UMIN, MVT::v8i32, 3}, 4486 {ISD::SMIN, MVT::v16i16, 3}, 4487 {ISD::UMIN, MVT::v16i16, 3}, 4488 {ISD::SMIN, MVT::v32i8, 3}, 4489 {ISD::UMIN, MVT::v32i8, 3}, 4490 }; 4491 4492 static const CostTblEntry AVX2CostTbl[] = { 4493 {ISD::SMIN, MVT::v8i32, 1}, 4494 {ISD::UMIN, MVT::v8i32, 1}, 4495 {ISD::SMIN, MVT::v16i16, 1}, 4496 {ISD::UMIN, MVT::v16i16, 1}, 4497 {ISD::SMIN, MVT::v32i8, 1}, 4498 {ISD::UMIN, MVT::v32i8, 1}, 4499 }; 4500 4501 static const CostTblEntry AVX512CostTbl[] = { 4502 {ISD::FMINNUM, MVT::v16f32, 1}, 4503 {ISD::FMINNUM, MVT::v8f64, 1}, 4504 {ISD::SMIN, MVT::v2i64, 1}, 4505 {ISD::UMIN, MVT::v2i64, 1}, 4506 {ISD::SMIN, MVT::v4i64, 1}, 4507 {ISD::UMIN, MVT::v4i64, 1}, 4508 {ISD::SMIN, MVT::v8i64, 1}, 4509 {ISD::UMIN, MVT::v8i64, 1}, 4510 {ISD::SMIN, MVT::v16i32, 1}, 4511 {ISD::UMIN, MVT::v16i32, 1}, 4512 }; 4513 4514 static const CostTblEntry AVX512BWCostTbl[] = { 4515 {ISD::SMIN, MVT::v32i16, 1}, 4516 {ISD::UMIN, MVT::v32i16, 1}, 4517 {ISD::SMIN, MVT::v64i8, 1}, 4518 {ISD::UMIN, MVT::v64i8, 1}, 4519 }; 4520 4521 // If we have a native MIN/MAX instruction for this type, use it. 4522 if (ST->hasBWI()) 4523 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 4524 return LT.first * Entry->Cost; 4525 4526 if (ST->hasAVX512()) 4527 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 4528 return LT.first * Entry->Cost; 4529 4530 if (ST->hasAVX2()) 4531 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 4532 return LT.first * Entry->Cost; 4533 4534 if (ST->hasAVX()) 4535 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 4536 return LT.first * Entry->Cost; 4537 4538 if (ST->hasSSE42()) 4539 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 4540 return LT.first * Entry->Cost; 4541 4542 if (ST->hasSSE41()) 4543 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 4544 return LT.first * Entry->Cost; 4545 4546 if (ST->hasSSE2()) 4547 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 4548 return LT.first * Entry->Cost; 4549 4550 if (ST->hasSSE1()) 4551 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 4552 return LT.first * Entry->Cost; 4553 4554 unsigned CmpOpcode; 4555 if (Ty->isFPOrFPVectorTy()) { 4556 CmpOpcode = Instruction::FCmp; 4557 } else { 4558 assert(Ty->isIntOrIntVectorTy() && 4559 "expecting floating point or integer type for min/max reduction"); 4560 CmpOpcode = Instruction::ICmp; 4561 } 4562 4563 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4564 // Otherwise fall back to cmp+select. 4565 InstructionCost Result = 4566 getCmpSelInstrCost(CmpOpcode, Ty, CondTy, CmpInst::BAD_ICMP_PREDICATE, 4567 CostKind) + 4568 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, 4569 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4570 return Result; 4571 } 4572 4573 InstructionCost 4574 X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 4575 bool IsUnsigned, 4576 TTI::TargetCostKind CostKind) { 4577 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 4578 4579 MVT MTy = LT.second; 4580 4581 int ISD; 4582 if (ValTy->isIntOrIntVectorTy()) { 4583 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 4584 } else { 4585 assert(ValTy->isFPOrFPVectorTy() && 4586 "Expected float point or integer vector type."); 4587 ISD = ISD::FMINNUM; 4588 } 4589 4590 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 4591 // and make it as the cost. 4592 4593 static const CostTblEntry SSE2CostTblNoPairWise[] = { 4594 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 4595 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 4596 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 4597 }; 4598 4599 static const CostTblEntry SSE41CostTblNoPairWise[] = { 4600 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 4601 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 4602 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 4603 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 4604 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 4605 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 4606 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 4607 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 4608 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 4609 {ISD::SMIN, MVT::v16i8, 6}, 4610 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 4611 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 4612 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 4613 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 4614 }; 4615 4616 static const CostTblEntry AVX1CostTblNoPairWise[] = { 4617 {ISD::SMIN, MVT::v16i16, 6}, 4618 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 4619 {ISD::SMIN, MVT::v32i8, 8}, 4620 {ISD::UMIN, MVT::v32i8, 8}, 4621 }; 4622 4623 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 4624 {ISD::SMIN, MVT::v32i16, 8}, 4625 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 4626 {ISD::SMIN, MVT::v64i8, 10}, 4627 {ISD::UMIN, MVT::v64i8, 10}, 4628 }; 4629 4630 // Before legalizing the type, give a chance to look up illegal narrow types 4631 // in the table. 4632 // FIXME: Is there a better way to do this? 4633 EVT VT = TLI->getValueType(DL, ValTy); 4634 if (VT.isSimple()) { 4635 MVT MTy = VT.getSimpleVT(); 4636 if (ST->hasBWI()) 4637 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4638 return Entry->Cost; 4639 4640 if (ST->hasAVX()) 4641 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4642 return Entry->Cost; 4643 4644 if (ST->hasSSE41()) 4645 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4646 return Entry->Cost; 4647 4648 if (ST->hasSSE2()) 4649 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4650 return Entry->Cost; 4651 } 4652 4653 auto *ValVTy = cast<FixedVectorType>(ValTy); 4654 unsigned NumVecElts = ValVTy->getNumElements(); 4655 4656 auto *Ty = ValVTy; 4657 InstructionCost MinMaxCost = 0; 4658 if (LT.first != 1 && MTy.isVector() && 4659 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4660 // Type needs to be split. We need LT.first - 1 operations ops. 4661 Ty = FixedVectorType::get(ValVTy->getElementType(), 4662 MTy.getVectorNumElements()); 4663 auto *SubCondTy = FixedVectorType::get(CondTy->getElementType(), 4664 MTy.getVectorNumElements()); 4665 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4666 MinMaxCost *= LT.first - 1; 4667 NumVecElts = MTy.getVectorNumElements(); 4668 } 4669 4670 if (ST->hasBWI()) 4671 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4672 return MinMaxCost + Entry->Cost; 4673 4674 if (ST->hasAVX()) 4675 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4676 return MinMaxCost + Entry->Cost; 4677 4678 if (ST->hasSSE41()) 4679 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4680 return MinMaxCost + Entry->Cost; 4681 4682 if (ST->hasSSE2()) 4683 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4684 return MinMaxCost + Entry->Cost; 4685 4686 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 4687 4688 // Special case power of 2 reductions where the scalar type isn't changed 4689 // by type legalization. 4690 if (!isPowerOf2_32(ValVTy->getNumElements()) || 4691 ScalarSize != MTy.getScalarSizeInBits()) 4692 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsUnsigned, CostKind); 4693 4694 // Now handle reduction with the legal type, taking into account size changes 4695 // at each level. 4696 while (NumVecElts > 1) { 4697 // Determine the size of the remaining vector we need to reduce. 4698 unsigned Size = NumVecElts * ScalarSize; 4699 NumVecElts /= 2; 4700 // If we're reducing from 256/512 bits, use an extract_subvector. 4701 if (Size > 128) { 4702 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 4703 MinMaxCost += 4704 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 4705 Ty = SubTy; 4706 } else if (Size == 128) { 4707 // Reducing from 128 bits is a permute of v2f64/v2i64. 4708 VectorType *ShufTy; 4709 if (ValTy->isFloatingPointTy()) 4710 ShufTy = 4711 FixedVectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 4712 else 4713 ShufTy = FixedVectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 4714 MinMaxCost += 4715 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4716 } else if (Size == 64) { 4717 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 4718 FixedVectorType *ShufTy; 4719 if (ValTy->isFloatingPointTy()) 4720 ShufTy = FixedVectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 4721 else 4722 ShufTy = FixedVectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 4723 MinMaxCost += 4724 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4725 } else { 4726 // Reducing from smaller size is a shift by immediate. 4727 auto *ShiftTy = FixedVectorType::get( 4728 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 4729 MinMaxCost += getArithmeticInstrCost( 4730 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, 4731 TargetTransformInfo::OK_AnyValue, 4732 TargetTransformInfo::OK_UniformConstantValue, 4733 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 4734 } 4735 4736 // Add the arithmetic op for this level. 4737 auto *SubCondTy = 4738 FixedVectorType::get(CondTy->getElementType(), Ty->getNumElements()); 4739 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4740 } 4741 4742 // Add the final extract element to the cost. 4743 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 4744 } 4745 4746 /// Calculate the cost of materializing a 64-bit value. This helper 4747 /// method might only calculate a fraction of a larger immediate. Therefore it 4748 /// is valid to return a cost of ZERO. 4749 InstructionCost X86TTIImpl::getIntImmCost(int64_t Val) { 4750 if (Val == 0) 4751 return TTI::TCC_Free; 4752 4753 if (isInt<32>(Val)) 4754 return TTI::TCC_Basic; 4755 4756 return 2 * TTI::TCC_Basic; 4757 } 4758 4759 InstructionCost X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 4760 TTI::TargetCostKind CostKind) { 4761 assert(Ty->isIntegerTy()); 4762 4763 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4764 if (BitSize == 0) 4765 return ~0U; 4766 4767 // Never hoist constants larger than 128bit, because this might lead to 4768 // incorrect code generation or assertions in codegen. 4769 // Fixme: Create a cost model for types larger than i128 once the codegen 4770 // issues have been fixed. 4771 if (BitSize > 128) 4772 return TTI::TCC_Free; 4773 4774 if (Imm == 0) 4775 return TTI::TCC_Free; 4776 4777 // Sign-extend all constants to a multiple of 64-bit. 4778 APInt ImmVal = Imm; 4779 if (BitSize % 64 != 0) 4780 ImmVal = Imm.sext(alignTo(BitSize, 64)); 4781 4782 // Split the constant into 64-bit chunks and calculate the cost for each 4783 // chunk. 4784 InstructionCost Cost = 0; 4785 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 4786 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 4787 int64_t Val = Tmp.getSExtValue(); 4788 Cost += getIntImmCost(Val); 4789 } 4790 // We need at least one instruction to materialize the constant. 4791 return std::max<InstructionCost>(1, Cost); 4792 } 4793 4794 InstructionCost X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, 4795 const APInt &Imm, Type *Ty, 4796 TTI::TargetCostKind CostKind, 4797 Instruction *Inst) { 4798 assert(Ty->isIntegerTy()); 4799 4800 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4801 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4802 // here, so that constant hoisting will ignore this constant. 4803 if (BitSize == 0) 4804 return TTI::TCC_Free; 4805 4806 unsigned ImmIdx = ~0U; 4807 switch (Opcode) { 4808 default: 4809 return TTI::TCC_Free; 4810 case Instruction::GetElementPtr: 4811 // Always hoist the base address of a GetElementPtr. This prevents the 4812 // creation of new constants for every base constant that gets constant 4813 // folded with the offset. 4814 if (Idx == 0) 4815 return 2 * TTI::TCC_Basic; 4816 return TTI::TCC_Free; 4817 case Instruction::Store: 4818 ImmIdx = 0; 4819 break; 4820 case Instruction::ICmp: 4821 // This is an imperfect hack to prevent constant hoisting of 4822 // compares that might be trying to check if a 64-bit value fits in 4823 // 32-bits. The backend can optimize these cases using a right shift by 32. 4824 // Ideally we would check the compare predicate here. There also other 4825 // similar immediates the backend can use shifts for. 4826 if (Idx == 1 && Imm.getBitWidth() == 64) { 4827 uint64_t ImmVal = Imm.getZExtValue(); 4828 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 4829 return TTI::TCC_Free; 4830 } 4831 ImmIdx = 1; 4832 break; 4833 case Instruction::And: 4834 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 4835 // by using a 32-bit operation with implicit zero extension. Detect such 4836 // immediates here as the normal path expects bit 31 to be sign extended. 4837 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 4838 return TTI::TCC_Free; 4839 ImmIdx = 1; 4840 break; 4841 case Instruction::Add: 4842 case Instruction::Sub: 4843 // For add/sub, we can use the opposite instruction for INT32_MIN. 4844 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 4845 return TTI::TCC_Free; 4846 ImmIdx = 1; 4847 break; 4848 case Instruction::UDiv: 4849 case Instruction::SDiv: 4850 case Instruction::URem: 4851 case Instruction::SRem: 4852 // Division by constant is typically expanded later into a different 4853 // instruction sequence. This completely changes the constants. 4854 // Report them as "free" to stop ConstantHoist from marking them as opaque. 4855 return TTI::TCC_Free; 4856 case Instruction::Mul: 4857 case Instruction::Or: 4858 case Instruction::Xor: 4859 ImmIdx = 1; 4860 break; 4861 // Always return TCC_Free for the shift value of a shift instruction. 4862 case Instruction::Shl: 4863 case Instruction::LShr: 4864 case Instruction::AShr: 4865 if (Idx == 1) 4866 return TTI::TCC_Free; 4867 break; 4868 case Instruction::Trunc: 4869 case Instruction::ZExt: 4870 case Instruction::SExt: 4871 case Instruction::IntToPtr: 4872 case Instruction::PtrToInt: 4873 case Instruction::BitCast: 4874 case Instruction::PHI: 4875 case Instruction::Call: 4876 case Instruction::Select: 4877 case Instruction::Ret: 4878 case Instruction::Load: 4879 break; 4880 } 4881 4882 if (Idx == ImmIdx) { 4883 int NumConstants = divideCeil(BitSize, 64); 4884 InstructionCost Cost = X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4885 return (Cost <= NumConstants * TTI::TCC_Basic) 4886 ? static_cast<int>(TTI::TCC_Free) 4887 : Cost; 4888 } 4889 4890 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4891 } 4892 4893 InstructionCost X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 4894 const APInt &Imm, Type *Ty, 4895 TTI::TargetCostKind CostKind) { 4896 assert(Ty->isIntegerTy()); 4897 4898 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4899 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4900 // here, so that constant hoisting will ignore this constant. 4901 if (BitSize == 0) 4902 return TTI::TCC_Free; 4903 4904 switch (IID) { 4905 default: 4906 return TTI::TCC_Free; 4907 case Intrinsic::sadd_with_overflow: 4908 case Intrinsic::uadd_with_overflow: 4909 case Intrinsic::ssub_with_overflow: 4910 case Intrinsic::usub_with_overflow: 4911 case Intrinsic::smul_with_overflow: 4912 case Intrinsic::umul_with_overflow: 4913 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 4914 return TTI::TCC_Free; 4915 break; 4916 case Intrinsic::experimental_stackmap: 4917 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4918 return TTI::TCC_Free; 4919 break; 4920 case Intrinsic::experimental_patchpoint_void: 4921 case Intrinsic::experimental_patchpoint_i64: 4922 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4923 return TTI::TCC_Free; 4924 break; 4925 } 4926 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4927 } 4928 4929 InstructionCost X86TTIImpl::getCFInstrCost(unsigned Opcode, 4930 TTI::TargetCostKind CostKind, 4931 const Instruction *I) { 4932 if (CostKind != TTI::TCK_RecipThroughput) 4933 return Opcode == Instruction::PHI ? 0 : 1; 4934 // Branches are assumed to be predicted. 4935 return 0; 4936 } 4937 4938 int X86TTIImpl::getGatherOverhead() const { 4939 // Some CPUs have more overhead for gather. The specified overhead is relative 4940 // to the Load operation. "2" is the number provided by Intel architects. This 4941 // parameter is used for cost estimation of Gather Op and comparison with 4942 // other alternatives. 4943 // TODO: Remove the explicit hasAVX512()?, That would mean we would only 4944 // enable gather with a -march. 4945 if (ST->hasAVX512() || (ST->hasAVX2() && ST->hasFastGather())) 4946 return 2; 4947 4948 return 1024; 4949 } 4950 4951 int X86TTIImpl::getScatterOverhead() const { 4952 if (ST->hasAVX512()) 4953 return 2; 4954 4955 return 1024; 4956 } 4957 4958 // Return an average cost of Gather / Scatter instruction, maybe improved later. 4959 // FIXME: Add TargetCostKind support. 4960 InstructionCost X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, 4961 const Value *Ptr, Align Alignment, 4962 unsigned AddressSpace) { 4963 4964 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 4965 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4966 4967 // Try to reduce index size from 64 bit (default for GEP) 4968 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 4969 // operation will use 16 x 64 indices which do not fit in a zmm and needs 4970 // to split. Also check that the base pointer is the same for all lanes, 4971 // and that there's at most one variable index. 4972 auto getIndexSizeInBits = [](const Value *Ptr, const DataLayout &DL) { 4973 unsigned IndexSize = DL.getPointerSizeInBits(); 4974 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 4975 if (IndexSize < 64 || !GEP) 4976 return IndexSize; 4977 4978 unsigned NumOfVarIndices = 0; 4979 const Value *Ptrs = GEP->getPointerOperand(); 4980 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 4981 return IndexSize; 4982 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 4983 if (isa<Constant>(GEP->getOperand(i))) 4984 continue; 4985 Type *IndxTy = GEP->getOperand(i)->getType(); 4986 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 4987 IndxTy = IndexVTy->getElementType(); 4988 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 4989 !isa<SExtInst>(GEP->getOperand(i))) || 4990 ++NumOfVarIndices > 1) 4991 return IndexSize; // 64 4992 } 4993 return (unsigned)32; 4994 }; 4995 4996 // Trying to reduce IndexSize to 32 bits for vector 16. 4997 // By default the IndexSize is equal to pointer size. 4998 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 4999 ? getIndexSizeInBits(Ptr, DL) 5000 : DL.getPointerSizeInBits(); 5001 5002 auto *IndexVTy = FixedVectorType::get( 5003 IntegerType::get(SrcVTy->getContext(), IndexSize), VF); 5004 std::pair<InstructionCost, MVT> IdxsLT = 5005 TLI->getTypeLegalizationCost(DL, IndexVTy); 5006 std::pair<InstructionCost, MVT> SrcLT = 5007 TLI->getTypeLegalizationCost(DL, SrcVTy); 5008 InstructionCost::CostType SplitFactor = 5009 *std::max(IdxsLT.first, SrcLT.first).getValue(); 5010 if (SplitFactor > 1) { 5011 // Handle splitting of vector of pointers 5012 auto *SplitSrcTy = 5013 FixedVectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 5014 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 5015 AddressSpace); 5016 } 5017 5018 // The gather / scatter cost is given by Intel architects. It is a rough 5019 // number since we are looking at one instruction in a time. 5020 const int GSOverhead = (Opcode == Instruction::Load) 5021 ? getGatherOverhead() 5022 : getScatterOverhead(); 5023 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 5024 MaybeAlign(Alignment), AddressSpace, 5025 TTI::TCK_RecipThroughput); 5026 } 5027 5028 /// Return the cost of full scalarization of gather / scatter operation. 5029 /// 5030 /// Opcode - Load or Store instruction. 5031 /// SrcVTy - The type of the data vector that should be gathered or scattered. 5032 /// VariableMask - The mask is non-constant at compile time. 5033 /// Alignment - Alignment for one element. 5034 /// AddressSpace - pointer[s] address space. 5035 /// 5036 /// FIXME: Add TargetCostKind support. 5037 InstructionCost X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 5038 bool VariableMask, Align Alignment, 5039 unsigned AddressSpace) { 5040 Type *ScalarTy = SrcVTy->getScalarType(); 5041 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 5042 APInt DemandedElts = APInt::getAllOnes(VF); 5043 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 5044 5045 InstructionCost MaskUnpackCost = 0; 5046 if (VariableMask) { 5047 auto *MaskTy = 5048 FixedVectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 5049 MaskUnpackCost = getScalarizationOverhead( 5050 MaskTy, DemandedElts, /*Insert=*/false, /*Extract=*/true); 5051 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 5052 Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), nullptr, 5053 CmpInst::BAD_ICMP_PREDICATE, CostKind); 5054 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 5055 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 5056 } 5057 5058 InstructionCost AddressUnpackCost = getScalarizationOverhead( 5059 FixedVectorType::get(ScalarTy->getPointerTo(), VF), DemandedElts, 5060 /*Insert=*/false, /*Extract=*/true); 5061 5062 // The cost of the scalar loads/stores. 5063 InstructionCost MemoryOpCost = 5064 VF * getMemoryOpCost(Opcode, ScalarTy, MaybeAlign(Alignment), 5065 AddressSpace, CostKind); 5066 5067 // The cost of forming the vector from loaded scalars/ 5068 // scalarizing the vector to perform scalar stores. 5069 InstructionCost InsertExtractCost = 5070 getScalarizationOverhead(cast<FixedVectorType>(SrcVTy), DemandedElts, 5071 /*Insert=*/Opcode == Instruction::Load, 5072 /*Extract=*/Opcode == Instruction::Store); 5073 5074 return AddressUnpackCost + MemoryOpCost + MaskUnpackCost + InsertExtractCost; 5075 } 5076 5077 /// Calculate the cost of Gather / Scatter operation 5078 InstructionCost X86TTIImpl::getGatherScatterOpCost( 5079 unsigned Opcode, Type *SrcVTy, const Value *Ptr, bool VariableMask, 5080 Align Alignment, TTI::TargetCostKind CostKind, 5081 const Instruction *I = nullptr) { 5082 if (CostKind != TTI::TCK_RecipThroughput) { 5083 if ((Opcode == Instruction::Load && 5084 isLegalMaskedGather(SrcVTy, Align(Alignment)) && 5085 !forceScalarizeMaskedGather(cast<VectorType>(SrcVTy), 5086 Align(Alignment))) || 5087 (Opcode == Instruction::Store && 5088 isLegalMaskedScatter(SrcVTy, Align(Alignment)) && 5089 !forceScalarizeMaskedScatter(cast<VectorType>(SrcVTy), 5090 Align(Alignment)))) 5091 return 1; 5092 return BaseT::getGatherScatterOpCost(Opcode, SrcVTy, Ptr, VariableMask, 5093 Alignment, CostKind, I); 5094 } 5095 5096 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 5097 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 5098 if (!PtrTy && Ptr->getType()->isVectorTy()) 5099 PtrTy = dyn_cast<PointerType>( 5100 cast<VectorType>(Ptr->getType())->getElementType()); 5101 assert(PtrTy && "Unexpected type for Ptr argument"); 5102 unsigned AddressSpace = PtrTy->getAddressSpace(); 5103 5104 if ((Opcode == Instruction::Load && 5105 (!isLegalMaskedGather(SrcVTy, Align(Alignment)) || 5106 forceScalarizeMaskedGather(cast<VectorType>(SrcVTy), 5107 Align(Alignment)))) || 5108 (Opcode == Instruction::Store && 5109 (!isLegalMaskedScatter(SrcVTy, Align(Alignment)) || 5110 forceScalarizeMaskedScatter(cast<VectorType>(SrcVTy), 5111 Align(Alignment))))) 5112 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 5113 AddressSpace); 5114 5115 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 5116 } 5117 5118 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 5119 TargetTransformInfo::LSRCost &C2) { 5120 // X86 specific here are "instruction number 1st priority". 5121 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 5122 C1.NumIVMuls, C1.NumBaseAdds, 5123 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 5124 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 5125 C2.NumIVMuls, C2.NumBaseAdds, 5126 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 5127 } 5128 5129 bool X86TTIImpl::canMacroFuseCmp() { 5130 return ST->hasMacroFusion() || ST->hasBranchFusion(); 5131 } 5132 5133 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, Align Alignment) { 5134 if (!ST->hasAVX()) 5135 return false; 5136 5137 // The backend can't handle a single element vector. 5138 if (isa<VectorType>(DataTy) && 5139 cast<FixedVectorType>(DataTy)->getNumElements() == 1) 5140 return false; 5141 Type *ScalarTy = DataTy->getScalarType(); 5142 5143 if (ScalarTy->isPointerTy()) 5144 return true; 5145 5146 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 5147 return true; 5148 5149 if (ScalarTy->isHalfTy() && ST->hasBWI() && ST->hasFP16()) 5150 return true; 5151 5152 if (!ScalarTy->isIntegerTy()) 5153 return false; 5154 5155 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 5156 return IntWidth == 32 || IntWidth == 64 || 5157 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 5158 } 5159 5160 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, Align Alignment) { 5161 return isLegalMaskedLoad(DataType, Alignment); 5162 } 5163 5164 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 5165 unsigned DataSize = DL.getTypeStoreSize(DataType); 5166 // The only supported nontemporal loads are for aligned vectors of 16 or 32 5167 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 5168 // (the equivalent stores only require AVX). 5169 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 5170 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 5171 5172 return false; 5173 } 5174 5175 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 5176 unsigned DataSize = DL.getTypeStoreSize(DataType); 5177 5178 // SSE4A supports nontemporal stores of float and double at arbitrary 5179 // alignment. 5180 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 5181 return true; 5182 5183 // Besides the SSE4A subtarget exception above, only aligned stores are 5184 // available nontemporaly on any other subtarget. And only stores with a size 5185 // of 4..32 bytes (powers of 2, only) are permitted. 5186 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 5187 !isPowerOf2_32(DataSize)) 5188 return false; 5189 5190 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 5191 // loads require AVX2). 5192 if (DataSize == 32) 5193 return ST->hasAVX(); 5194 if (DataSize == 16) 5195 return ST->hasSSE1(); 5196 return true; 5197 } 5198 5199 bool X86TTIImpl::isLegalBroadcastLoad(Type *ElementTy, 5200 ElementCount NumElements) const { 5201 // movddup 5202 return ST->hasSSE3() && !NumElements.isScalable() && 5203 NumElements.getFixedValue() == 2 && 5204 ElementTy == Type::getDoubleTy(ElementTy->getContext()); 5205 } 5206 5207 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 5208 if (!isa<VectorType>(DataTy)) 5209 return false; 5210 5211 if (!ST->hasAVX512()) 5212 return false; 5213 5214 // The backend can't handle a single element vector. 5215 if (cast<FixedVectorType>(DataTy)->getNumElements() == 1) 5216 return false; 5217 5218 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 5219 5220 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 5221 return true; 5222 5223 if (!ScalarTy->isIntegerTy()) 5224 return false; 5225 5226 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 5227 return IntWidth == 32 || IntWidth == 64 || 5228 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 5229 } 5230 5231 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 5232 return isLegalMaskedExpandLoad(DataTy); 5233 } 5234 5235 bool X86TTIImpl::supportsGather() const { 5236 // Some CPUs have better gather performance than others. 5237 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 5238 // enable gather with a -march. 5239 return ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()); 5240 } 5241 5242 bool X86TTIImpl::forceScalarizeMaskedGather(VectorType *VTy, Align Alignment) { 5243 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 5244 // Vector-4 of gather/scatter instruction does not exist on KNL. We can extend 5245 // it to 8 elements, but zeroing upper bits of the mask vector will add more 5246 // instructions. Right now we give the scalar cost of vector-4 for KNL. TODO: 5247 // Check, maybe the gather/scatter instruction is better in the VariableMask 5248 // case. 5249 unsigned NumElts = cast<FixedVectorType>(VTy)->getNumElements(); 5250 return NumElts == 1 || 5251 (ST->hasAVX512() && (NumElts == 2 || (NumElts == 4 && !ST->hasVLX()))); 5252 } 5253 5254 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, Align Alignment) { 5255 if (!supportsGather()) 5256 return false; 5257 Type *ScalarTy = DataTy->getScalarType(); 5258 if (ScalarTy->isPointerTy()) 5259 return true; 5260 5261 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 5262 return true; 5263 5264 if (!ScalarTy->isIntegerTy()) 5265 return false; 5266 5267 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 5268 return IntWidth == 32 || IntWidth == 64; 5269 } 5270 5271 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, Align Alignment) { 5272 // AVX2 doesn't support scatter 5273 if (!ST->hasAVX512()) 5274 return false; 5275 return isLegalMaskedGather(DataType, Alignment); 5276 } 5277 5278 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 5279 EVT VT = TLI->getValueType(DL, DataType); 5280 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 5281 } 5282 5283 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 5284 return false; 5285 } 5286 5287 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 5288 const Function *Callee) const { 5289 const TargetMachine &TM = getTLI()->getTargetMachine(); 5290 5291 // Work this as a subsetting of subtarget features. 5292 const FeatureBitset &CallerBits = 5293 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 5294 const FeatureBitset &CalleeBits = 5295 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 5296 5297 // Check whether features are the same (apart from the ignore list). 5298 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 5299 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 5300 if (RealCallerBits == RealCalleeBits) 5301 return true; 5302 5303 // If the features are a subset, we need to additionally check for calls 5304 // that may become ABI-incompatible as a result of inlining. 5305 if ((RealCallerBits & RealCalleeBits) != RealCalleeBits) 5306 return false; 5307 5308 for (const Instruction &I : instructions(Callee)) { 5309 if (const auto *CB = dyn_cast<CallBase>(&I)) { 5310 SmallVector<Type *, 8> Types; 5311 for (Value *Arg : CB->args()) 5312 Types.push_back(Arg->getType()); 5313 if (!CB->getType()->isVoidTy()) 5314 Types.push_back(CB->getType()); 5315 5316 // Simple types are always ABI compatible. 5317 auto IsSimpleTy = [](Type *Ty) { 5318 return !Ty->isVectorTy() && !Ty->isAggregateType(); 5319 }; 5320 if (all_of(Types, IsSimpleTy)) 5321 continue; 5322 5323 if (Function *NestedCallee = CB->getCalledFunction()) { 5324 // Assume that intrinsics are always ABI compatible. 5325 if (NestedCallee->isIntrinsic()) 5326 continue; 5327 5328 // Do a precise compatibility check. 5329 if (!areTypesABICompatible(Caller, NestedCallee, Types)) 5330 return false; 5331 } else { 5332 // We don't know the target features of the callee, 5333 // assume it is incompatible. 5334 return false; 5335 } 5336 } 5337 } 5338 return true; 5339 } 5340 5341 bool X86TTIImpl::areTypesABICompatible(const Function *Caller, 5342 const Function *Callee, 5343 const ArrayRef<Type *> &Types) const { 5344 if (!BaseT::areTypesABICompatible(Caller, Callee, Types)) 5345 return false; 5346 5347 // If we get here, we know the target features match. If one function 5348 // considers 512-bit vectors legal and the other does not, consider them 5349 // incompatible. 5350 const TargetMachine &TM = getTLI()->getTargetMachine(); 5351 5352 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 5353 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs()) 5354 return true; 5355 5356 // Consider the arguments compatible if they aren't vectors or aggregates. 5357 // FIXME: Look at the size of vectors. 5358 // FIXME: Look at the element types of aggregates to see if there are vectors. 5359 return llvm::none_of(Types, 5360 [](Type *T) { return T->isVectorTy() || T->isAggregateType(); }); 5361 } 5362 5363 X86TTIImpl::TTI::MemCmpExpansionOptions 5364 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 5365 TTI::MemCmpExpansionOptions Options; 5366 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 5367 Options.NumLoadsPerBlock = 2; 5368 // All GPR and vector loads can be unaligned. 5369 Options.AllowOverlappingLoads = true; 5370 if (IsZeroCmp) { 5371 // Only enable vector loads for equality comparison. Right now the vector 5372 // version is not as fast for three way compare (see #33329). 5373 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 5374 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 5375 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 5376 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 5377 } 5378 if (ST->is64Bit()) { 5379 Options.LoadSizes.push_back(8); 5380 } 5381 Options.LoadSizes.push_back(4); 5382 Options.LoadSizes.push_back(2); 5383 Options.LoadSizes.push_back(1); 5384 return Options; 5385 } 5386 5387 bool X86TTIImpl::prefersVectorizedAddressing() const { 5388 return supportsGather(); 5389 } 5390 5391 bool X86TTIImpl::supportsEfficientVectorElementLoadStore() const { 5392 return false; 5393 } 5394 5395 bool X86TTIImpl::enableInterleavedAccessVectorization() { 5396 // TODO: We expect this to be beneficial regardless of arch, 5397 // but there are currently some unexplained performance artifacts on Atom. 5398 // As a temporary solution, disable on Atom. 5399 return !(ST->isAtom()); 5400 } 5401 5402 // Get estimation for interleaved load/store operations and strided load. 5403 // \p Indices contains indices for strided load. 5404 // \p Factor - the factor of interleaving. 5405 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 5406 InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX512( 5407 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 5408 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 5409 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 5410 // VecTy for interleave memop is <VF*Factor x Elt>. 5411 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 5412 // VecTy = <12 x i32>. 5413 5414 // Calculate the number of memory operations (NumOfMemOps), required 5415 // for load/store the VecTy. 5416 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 5417 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 5418 unsigned LegalVTSize = LegalVT.getStoreSize(); 5419 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 5420 5421 // Get the cost of one memory operation. 5422 auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(), 5423 LegalVT.getVectorNumElements()); 5424 InstructionCost MemOpCost; 5425 bool UseMaskedMemOp = UseMaskForCond || UseMaskForGaps; 5426 if (UseMaskedMemOp) 5427 MemOpCost = getMaskedMemoryOpCost(Opcode, SingleMemOpTy, Alignment, 5428 AddressSpace, CostKind); 5429 else 5430 MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, MaybeAlign(Alignment), 5431 AddressSpace, CostKind); 5432 5433 unsigned VF = VecTy->getNumElements() / Factor; 5434 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 5435 5436 InstructionCost MaskCost; 5437 if (UseMaskedMemOp) { 5438 APInt DemandedLoadStoreElts = APInt::getZero(VecTy->getNumElements()); 5439 for (unsigned Index : Indices) { 5440 assert(Index < Factor && "Invalid index for interleaved memory op"); 5441 for (unsigned Elm = 0; Elm < VF; Elm++) 5442 DemandedLoadStoreElts.setBit(Index + Elm * Factor); 5443 } 5444 5445 Type *I1Type = Type::getInt1Ty(VecTy->getContext()); 5446 5447 MaskCost = getReplicationShuffleCost( 5448 I1Type, Factor, VF, 5449 UseMaskForGaps ? DemandedLoadStoreElts 5450 : APInt::getAllOnes(VecTy->getNumElements()), 5451 CostKind); 5452 5453 // The Gaps mask is invariant and created outside the loop, therefore the 5454 // cost of creating it is not accounted for here. However if we have both 5455 // a MaskForGaps and some other mask that guards the execution of the 5456 // memory access, we need to account for the cost of And-ing the two masks 5457 // inside the loop. 5458 if (UseMaskForGaps) { 5459 auto *MaskVT = FixedVectorType::get(I1Type, VecTy->getNumElements()); 5460 MaskCost += getArithmeticInstrCost(BinaryOperator::And, MaskVT, CostKind); 5461 } 5462 } 5463 5464 if (Opcode == Instruction::Load) { 5465 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 5466 // contain the cost of the optimized shuffle sequence that the 5467 // X86InterleavedAccess pass will generate. 5468 // The cost of loads and stores are computed separately from the table. 5469 5470 // X86InterleavedAccess support only the following interleaved-access group. 5471 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 5472 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 5473 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 5474 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 5475 }; 5476 5477 if (const auto *Entry = 5478 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 5479 return MaskCost + NumOfMemOps * MemOpCost + Entry->Cost; 5480 //If an entry does not exist, fallback to the default implementation. 5481 5482 // Kind of shuffle depends on number of loaded values. 5483 // If we load the entire data in one register, we can use a 1-src shuffle. 5484 // Otherwise, we'll merge 2 sources in each operation. 5485 TTI::ShuffleKind ShuffleKind = 5486 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 5487 5488 InstructionCost ShuffleCost = 5489 getShuffleCost(ShuffleKind, SingleMemOpTy, None, 0, nullptr); 5490 5491 unsigned NumOfLoadsInInterleaveGrp = 5492 Indices.size() ? Indices.size() : Factor; 5493 auto *ResultTy = FixedVectorType::get(VecTy->getElementType(), 5494 VecTy->getNumElements() / Factor); 5495 InstructionCost NumOfResults = 5496 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 5497 NumOfLoadsInInterleaveGrp; 5498 5499 // About a half of the loads may be folded in shuffles when we have only 5500 // one result. If we have more than one result, or the loads are masked, 5501 // we do not fold loads at all. 5502 unsigned NumOfUnfoldedLoads = 5503 UseMaskedMemOp || NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 5504 5505 // Get a number of shuffle operations per result. 5506 unsigned NumOfShufflesPerResult = 5507 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 5508 5509 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 5510 // When we have more than one destination, we need additional instructions 5511 // to keep sources. 5512 InstructionCost NumOfMoves = 0; 5513 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 5514 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 5515 5516 InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 5517 MaskCost + NumOfUnfoldedLoads * MemOpCost + 5518 NumOfMoves; 5519 5520 return Cost; 5521 } 5522 5523 // Store. 5524 assert(Opcode == Instruction::Store && 5525 "Expected Store Instruction at this point"); 5526 // X86InterleavedAccess support only the following interleaved-access group. 5527 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 5528 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 5529 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 5530 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 5531 5532 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 5533 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 5534 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 5535 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 5536 }; 5537 5538 if (const auto *Entry = 5539 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 5540 return MaskCost + NumOfMemOps * MemOpCost + Entry->Cost; 5541 //If an entry does not exist, fallback to the default implementation. 5542 5543 // There is no strided stores meanwhile. And store can't be folded in 5544 // shuffle. 5545 unsigned NumOfSources = Factor; // The number of values to be merged. 5546 InstructionCost ShuffleCost = 5547 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, None, 0, nullptr); 5548 unsigned NumOfShufflesPerStore = NumOfSources - 1; 5549 5550 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 5551 // We need additional instructions to keep sources. 5552 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 5553 InstructionCost Cost = 5554 MaskCost + 5555 NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 5556 NumOfMoves; 5557 return Cost; 5558 } 5559 5560 InstructionCost X86TTIImpl::getInterleavedMemoryOpCost( 5561 unsigned Opcode, Type *BaseTy, unsigned Factor, ArrayRef<unsigned> Indices, 5562 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, 5563 bool UseMaskForCond, bool UseMaskForGaps) { 5564 auto *VecTy = cast<FixedVectorType>(BaseTy); 5565 5566 auto isSupportedOnAVX512 = [&](Type *VecTy, bool HasBW) { 5567 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 5568 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 5569 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 5570 return true; 5571 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8) || 5572 (!ST->useSoftFloat() && ST->hasFP16() && EltTy->isHalfTy())) 5573 return HasBW; 5574 return false; 5575 }; 5576 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 5577 return getInterleavedMemoryOpCostAVX512( 5578 Opcode, VecTy, Factor, Indices, Alignment, 5579 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 5580 5581 if (UseMaskForCond || UseMaskForGaps) 5582 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5583 Alignment, AddressSpace, CostKind, 5584 UseMaskForCond, UseMaskForGaps); 5585 5586 // Get estimation for interleaved load/store operations for SSE-AVX2. 5587 // As opposed to AVX-512, SSE-AVX2 do not have generic shuffles that allow 5588 // computing the cost using a generic formula as a function of generic 5589 // shuffles. We therefore use a lookup table instead, filled according to 5590 // the instruction sequences that codegen currently generates. 5591 5592 // VecTy for interleave memop is <VF*Factor x Elt>. 5593 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 5594 // VecTy = <12 x i32>. 5595 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 5596 5597 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 5598 // the VF=2, while v2i128 is an unsupported MVT vector type 5599 // (see MachineValueType.h::getVectorVT()). 5600 if (!LegalVT.isVector()) 5601 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5602 Alignment, AddressSpace, CostKind); 5603 5604 unsigned VF = VecTy->getNumElements() / Factor; 5605 Type *ScalarTy = VecTy->getElementType(); 5606 // Deduplicate entries, model floats/pointers as appropriately-sized integers. 5607 if (!ScalarTy->isIntegerTy()) 5608 ScalarTy = 5609 Type::getIntNTy(ScalarTy->getContext(), DL.getTypeSizeInBits(ScalarTy)); 5610 5611 // Get the cost of all the memory operations. 5612 // FIXME: discount dead loads. 5613 InstructionCost MemOpCosts = getMemoryOpCost( 5614 Opcode, VecTy, MaybeAlign(Alignment), AddressSpace, CostKind); 5615 5616 auto *VT = FixedVectorType::get(ScalarTy, VF); 5617 EVT ETy = TLI->getValueType(DL, VT); 5618 if (!ETy.isSimple()) 5619 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5620 Alignment, AddressSpace, CostKind); 5621 5622 // TODO: Complete for other data-types and strides. 5623 // Each combination of Stride, element bit width and VF results in a different 5624 // sequence; The cost tables are therefore accessed with: 5625 // Factor (stride) and VectorType=VFxiN. 5626 // The Cost accounts only for the shuffle sequence; 5627 // The cost of the loads/stores is accounted for separately. 5628 // 5629 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 5630 {2, MVT::v2i8, 2}, // (load 4i8 and) deinterleave into 2 x 2i8 5631 {2, MVT::v4i8, 2}, // (load 8i8 and) deinterleave into 2 x 4i8 5632 {2, MVT::v8i8, 2}, // (load 16i8 and) deinterleave into 2 x 8i8 5633 {2, MVT::v16i8, 4}, // (load 32i8 and) deinterleave into 2 x 16i8 5634 {2, MVT::v32i8, 6}, // (load 64i8 and) deinterleave into 2 x 32i8 5635 5636 {2, MVT::v8i16, 6}, // (load 16i16 and) deinterleave into 2 x 8i16 5637 {2, MVT::v16i16, 9}, // (load 32i16 and) deinterleave into 2 x 16i16 5638 {2, MVT::v32i16, 18}, // (load 64i16 and) deinterleave into 2 x 32i16 5639 5640 {2, MVT::v8i32, 4}, // (load 16i32 and) deinterleave into 2 x 8i32 5641 {2, MVT::v16i32, 8}, // (load 32i32 and) deinterleave into 2 x 16i32 5642 {2, MVT::v32i32, 16}, // (load 64i32 and) deinterleave into 2 x 32i32 5643 5644 {2, MVT::v4i64, 4}, // (load 8i64 and) deinterleave into 2 x 4i64 5645 {2, MVT::v8i64, 8}, // (load 16i64 and) deinterleave into 2 x 8i64 5646 {2, MVT::v16i64, 16}, // (load 32i64 and) deinterleave into 2 x 16i64 5647 {2, MVT::v32i64, 32}, // (load 64i64 and) deinterleave into 2 x 32i64 5648 5649 {3, MVT::v2i8, 3}, // (load 6i8 and) deinterleave into 3 x 2i8 5650 {3, MVT::v4i8, 3}, // (load 12i8 and) deinterleave into 3 x 4i8 5651 {3, MVT::v8i8, 6}, // (load 24i8 and) deinterleave into 3 x 8i8 5652 {3, MVT::v16i8, 11}, // (load 48i8 and) deinterleave into 3 x 16i8 5653 {3, MVT::v32i8, 14}, // (load 96i8 and) deinterleave into 3 x 32i8 5654 5655 {3, MVT::v2i16, 5}, // (load 6i16 and) deinterleave into 3 x 2i16 5656 {3, MVT::v4i16, 7}, // (load 12i16 and) deinterleave into 3 x 4i16 5657 {3, MVT::v8i16, 9}, // (load 24i16 and) deinterleave into 3 x 8i16 5658 {3, MVT::v16i16, 28}, // (load 48i16 and) deinterleave into 3 x 16i16 5659 {3, MVT::v32i16, 56}, // (load 96i16 and) deinterleave into 3 x 32i16 5660 5661 {3, MVT::v2i32, 3}, // (load 6i32 and) deinterleave into 3 x 2i32 5662 {3, MVT::v4i32, 3}, // (load 12i32 and) deinterleave into 3 x 4i32 5663 {3, MVT::v8i32, 7}, // (load 24i32 and) deinterleave into 3 x 8i32 5664 {3, MVT::v16i32, 14}, // (load 48i32 and) deinterleave into 3 x 16i32 5665 {3, MVT::v32i32, 32}, // (load 96i32 and) deinterleave into 3 x 32i32 5666 5667 {3, MVT::v2i64, 1}, // (load 6i64 and) deinterleave into 3 x 2i64 5668 {3, MVT::v4i64, 5}, // (load 12i64 and) deinterleave into 3 x 4i64 5669 {3, MVT::v8i64, 10}, // (load 24i64 and) deinterleave into 3 x 8i64 5670 {3, MVT::v16i64, 20}, // (load 48i64 and) deinterleave into 3 x 16i64 5671 5672 {4, MVT::v2i8, 4}, // (load 8i8 and) deinterleave into 4 x 2i8 5673 {4, MVT::v4i8, 4}, // (load 16i8 and) deinterleave into 4 x 4i8 5674 {4, MVT::v8i8, 12}, // (load 32i8 and) deinterleave into 4 x 8i8 5675 {4, MVT::v16i8, 24}, // (load 64i8 and) deinterleave into 4 x 16i8 5676 {4, MVT::v32i8, 56}, // (load 128i8 and) deinterleave into 4 x 32i8 5677 5678 {4, MVT::v2i16, 6}, // (load 8i16 and) deinterleave into 4 x 2i16 5679 {4, MVT::v4i16, 17}, // (load 16i16 and) deinterleave into 4 x 4i16 5680 {4, MVT::v8i16, 33}, // (load 32i16 and) deinterleave into 4 x 8i16 5681 {4, MVT::v16i16, 75}, // (load 64i16 and) deinterleave into 4 x 16i16 5682 {4, MVT::v32i16, 150}, // (load 128i16 and) deinterleave into 4 x 32i16 5683 5684 {4, MVT::v2i32, 4}, // (load 8i32 and) deinterleave into 4 x 2i32 5685 {4, MVT::v4i32, 8}, // (load 16i32 and) deinterleave into 4 x 4i32 5686 {4, MVT::v8i32, 16}, // (load 32i32 and) deinterleave into 4 x 8i32 5687 {4, MVT::v16i32, 32}, // (load 64i32 and) deinterleave into 4 x 16i32 5688 {4, MVT::v32i32, 68}, // (load 128i32 and) deinterleave into 4 x 32i32 5689 5690 {4, MVT::v2i64, 6}, // (load 8i64 and) deinterleave into 4 x 2i64 5691 {4, MVT::v4i64, 8}, // (load 16i64 and) deinterleave into 4 x 4i64 5692 {4, MVT::v8i64, 20}, // (load 32i64 and) deinterleave into 4 x 8i64 5693 {4, MVT::v16i64, 40}, // (load 64i64 and) deinterleave into 4 x 16i64 5694 5695 {6, MVT::v2i8, 6}, // (load 12i8 and) deinterleave into 6 x 2i8 5696 {6, MVT::v4i8, 14}, // (load 24i8 and) deinterleave into 6 x 4i8 5697 {6, MVT::v8i8, 18}, // (load 48i8 and) deinterleave into 6 x 8i8 5698 {6, MVT::v16i8, 43}, // (load 96i8 and) deinterleave into 6 x 16i8 5699 {6, MVT::v32i8, 82}, // (load 192i8 and) deinterleave into 6 x 32i8 5700 5701 {6, MVT::v2i16, 13}, // (load 12i16 and) deinterleave into 6 x 2i16 5702 {6, MVT::v4i16, 9}, // (load 24i16 and) deinterleave into 6 x 4i16 5703 {6, MVT::v8i16, 39}, // (load 48i16 and) deinterleave into 6 x 8i16 5704 {6, MVT::v16i16, 106}, // (load 96i16 and) deinterleave into 6 x 16i16 5705 {6, MVT::v32i16, 212}, // (load 192i16 and) deinterleave into 6 x 32i16 5706 5707 {6, MVT::v2i32, 6}, // (load 12i32 and) deinterleave into 6 x 2i32 5708 {6, MVT::v4i32, 15}, // (load 24i32 and) deinterleave into 6 x 4i32 5709 {6, MVT::v8i32, 31}, // (load 48i32 and) deinterleave into 6 x 8i32 5710 {6, MVT::v16i32, 64}, // (load 96i32 and) deinterleave into 6 x 16i32 5711 5712 {6, MVT::v2i64, 6}, // (load 12i64 and) deinterleave into 6 x 2i64 5713 {6, MVT::v4i64, 18}, // (load 24i64 and) deinterleave into 6 x 4i64 5714 {6, MVT::v8i64, 36}, // (load 48i64 and) deinterleave into 6 x 8i64 5715 5716 {8, MVT::v8i32, 40} // (load 64i32 and) deinterleave into 8 x 8i32 5717 }; 5718 5719 static const CostTblEntry SSSE3InterleavedLoadTbl[] = { 5720 {2, MVT::v4i16, 2}, // (load 8i16 and) deinterleave into 2 x 4i16 5721 }; 5722 5723 static const CostTblEntry SSE2InterleavedLoadTbl[] = { 5724 {2, MVT::v2i16, 2}, // (load 4i16 and) deinterleave into 2 x 2i16 5725 {2, MVT::v4i16, 7}, // (load 8i16 and) deinterleave into 2 x 4i16 5726 5727 {2, MVT::v2i32, 2}, // (load 4i32 and) deinterleave into 2 x 2i32 5728 {2, MVT::v4i32, 2}, // (load 8i32 and) deinterleave into 2 x 4i32 5729 5730 {2, MVT::v2i64, 2}, // (load 4i64 and) deinterleave into 2 x 2i64 5731 }; 5732 5733 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 5734 {2, MVT::v16i8, 3}, // interleave 2 x 16i8 into 32i8 (and store) 5735 {2, MVT::v32i8, 4}, // interleave 2 x 32i8 into 64i8 (and store) 5736 5737 {2, MVT::v8i16, 3}, // interleave 2 x 8i16 into 16i16 (and store) 5738 {2, MVT::v16i16, 4}, // interleave 2 x 16i16 into 32i16 (and store) 5739 {2, MVT::v32i16, 8}, // interleave 2 x 32i16 into 64i16 (and store) 5740 5741 {2, MVT::v4i32, 2}, // interleave 2 x 4i32 into 8i32 (and store) 5742 {2, MVT::v8i32, 4}, // interleave 2 x 8i32 into 16i32 (and store) 5743 {2, MVT::v16i32, 8}, // interleave 2 x 16i32 into 32i32 (and store) 5744 {2, MVT::v32i32, 16}, // interleave 2 x 32i32 into 64i32 (and store) 5745 5746 {2, MVT::v2i64, 2}, // interleave 2 x 2i64 into 4i64 (and store) 5747 {2, MVT::v4i64, 4}, // interleave 2 x 4i64 into 8i64 (and store) 5748 {2, MVT::v8i64, 8}, // interleave 2 x 8i64 into 16i64 (and store) 5749 {2, MVT::v16i64, 16}, // interleave 2 x 16i64 into 32i64 (and store) 5750 {2, MVT::v32i64, 32}, // interleave 2 x 32i64 into 64i64 (and store) 5751 5752 {3, MVT::v2i8, 4}, // interleave 3 x 2i8 into 6i8 (and store) 5753 {3, MVT::v4i8, 4}, // interleave 3 x 4i8 into 12i8 (and store) 5754 {3, MVT::v8i8, 6}, // interleave 3 x 8i8 into 24i8 (and store) 5755 {3, MVT::v16i8, 11}, // interleave 3 x 16i8 into 48i8 (and store) 5756 {3, MVT::v32i8, 13}, // interleave 3 x 32i8 into 96i8 (and store) 5757 5758 {3, MVT::v2i16, 4}, // interleave 3 x 2i16 into 6i16 (and store) 5759 {3, MVT::v4i16, 6}, // interleave 3 x 4i16 into 12i16 (and store) 5760 {3, MVT::v8i16, 12}, // interleave 3 x 8i16 into 24i16 (and store) 5761 {3, MVT::v16i16, 27}, // interleave 3 x 16i16 into 48i16 (and store) 5762 {3, MVT::v32i16, 54}, // interleave 3 x 32i16 into 96i16 (and store) 5763 5764 {3, MVT::v2i32, 4}, // interleave 3 x 2i32 into 6i32 (and store) 5765 {3, MVT::v4i32, 5}, // interleave 3 x 4i32 into 12i32 (and store) 5766 {3, MVT::v8i32, 11}, // interleave 3 x 8i32 into 24i32 (and store) 5767 {3, MVT::v16i32, 22}, // interleave 3 x 16i32 into 48i32 (and store) 5768 {3, MVT::v32i32, 48}, // interleave 3 x 32i32 into 96i32 (and store) 5769 5770 {3, MVT::v2i64, 4}, // interleave 3 x 2i64 into 6i64 (and store) 5771 {3, MVT::v4i64, 6}, // interleave 3 x 4i64 into 12i64 (and store) 5772 {3, MVT::v8i64, 12}, // interleave 3 x 8i64 into 24i64 (and store) 5773 {3, MVT::v16i64, 24}, // interleave 3 x 16i64 into 48i64 (and store) 5774 5775 {4, MVT::v2i8, 4}, // interleave 4 x 2i8 into 8i8 (and store) 5776 {4, MVT::v4i8, 4}, // interleave 4 x 4i8 into 16i8 (and store) 5777 {4, MVT::v8i8, 4}, // interleave 4 x 8i8 into 32i8 (and store) 5778 {4, MVT::v16i8, 8}, // interleave 4 x 16i8 into 64i8 (and store) 5779 {4, MVT::v32i8, 12}, // interleave 4 x 32i8 into 128i8 (and store) 5780 5781 {4, MVT::v2i16, 2}, // interleave 4 x 2i16 into 8i16 (and store) 5782 {4, MVT::v4i16, 6}, // interleave 4 x 4i16 into 16i16 (and store) 5783 {4, MVT::v8i16, 10}, // interleave 4 x 8i16 into 32i16 (and store) 5784 {4, MVT::v16i16, 32}, // interleave 4 x 16i16 into 64i16 (and store) 5785 {4, MVT::v32i16, 64}, // interleave 4 x 32i16 into 128i16 (and store) 5786 5787 {4, MVT::v2i32, 5}, // interleave 4 x 2i32 into 8i32 (and store) 5788 {4, MVT::v4i32, 6}, // interleave 4 x 4i32 into 16i32 (and store) 5789 {4, MVT::v8i32, 16}, // interleave 4 x 8i32 into 32i32 (and store) 5790 {4, MVT::v16i32, 32}, // interleave 4 x 16i32 into 64i32 (and store) 5791 {4, MVT::v32i32, 64}, // interleave 4 x 32i32 into 128i32 (and store) 5792 5793 {4, MVT::v2i64, 6}, // interleave 4 x 2i64 into 8i64 (and store) 5794 {4, MVT::v4i64, 8}, // interleave 4 x 4i64 into 16i64 (and store) 5795 {4, MVT::v8i64, 20}, // interleave 4 x 8i64 into 32i64 (and store) 5796 {4, MVT::v16i64, 40}, // interleave 4 x 16i64 into 64i64 (and store) 5797 5798 {6, MVT::v2i8, 7}, // interleave 6 x 2i8 into 12i8 (and store) 5799 {6, MVT::v4i8, 9}, // interleave 6 x 4i8 into 24i8 (and store) 5800 {6, MVT::v8i8, 16}, // interleave 6 x 8i8 into 48i8 (and store) 5801 {6, MVT::v16i8, 27}, // interleave 6 x 16i8 into 96i8 (and store) 5802 {6, MVT::v32i8, 90}, // interleave 6 x 32i8 into 192i8 (and store) 5803 5804 {6, MVT::v2i16, 10}, // interleave 6 x 2i16 into 12i16 (and store) 5805 {6, MVT::v4i16, 15}, // interleave 6 x 4i16 into 24i16 (and store) 5806 {6, MVT::v8i16, 21}, // interleave 6 x 8i16 into 48i16 (and store) 5807 {6, MVT::v16i16, 58}, // interleave 6 x 16i16 into 96i16 (and store) 5808 {6, MVT::v32i16, 90}, // interleave 6 x 32i16 into 192i16 (and store) 5809 5810 {6, MVT::v2i32, 9}, // interleave 6 x 2i32 into 12i32 (and store) 5811 {6, MVT::v4i32, 12}, // interleave 6 x 4i32 into 24i32 (and store) 5812 {6, MVT::v8i32, 33}, // interleave 6 x 8i32 into 48i32 (and store) 5813 {6, MVT::v16i32, 66}, // interleave 6 x 16i32 into 96i32 (and store) 5814 5815 {6, MVT::v2i64, 8}, // interleave 6 x 2i64 into 12i64 (and store) 5816 {6, MVT::v4i64, 15}, // interleave 6 x 4i64 into 24i64 (and store) 5817 {6, MVT::v8i64, 30}, // interleave 6 x 8i64 into 48i64 (and store) 5818 }; 5819 5820 static const CostTblEntry SSE2InterleavedStoreTbl[] = { 5821 {2, MVT::v2i8, 1}, // interleave 2 x 2i8 into 4i8 (and store) 5822 {2, MVT::v4i8, 1}, // interleave 2 x 4i8 into 8i8 (and store) 5823 {2, MVT::v8i8, 1}, // interleave 2 x 8i8 into 16i8 (and store) 5824 5825 {2, MVT::v2i16, 1}, // interleave 2 x 2i16 into 4i16 (and store) 5826 {2, MVT::v4i16, 1}, // interleave 2 x 4i16 into 8i16 (and store) 5827 5828 {2, MVT::v2i32, 1}, // interleave 2 x 2i32 into 4i32 (and store) 5829 }; 5830 5831 if (Opcode == Instruction::Load) { 5832 auto GetDiscountedCost = [Factor, NumMembers = Indices.size(), 5833 MemOpCosts](const CostTblEntry *Entry) { 5834 // NOTE: this is just an approximation! 5835 // It can over/under -estimate the cost! 5836 return MemOpCosts + divideCeil(NumMembers * Entry->Cost, Factor); 5837 }; 5838 5839 if (ST->hasAVX2()) 5840 if (const auto *Entry = CostTableLookup(AVX2InterleavedLoadTbl, Factor, 5841 ETy.getSimpleVT())) 5842 return GetDiscountedCost(Entry); 5843 5844 if (ST->hasSSSE3()) 5845 if (const auto *Entry = CostTableLookup(SSSE3InterleavedLoadTbl, Factor, 5846 ETy.getSimpleVT())) 5847 return GetDiscountedCost(Entry); 5848 5849 if (ST->hasSSE2()) 5850 if (const auto *Entry = CostTableLookup(SSE2InterleavedLoadTbl, Factor, 5851 ETy.getSimpleVT())) 5852 return GetDiscountedCost(Entry); 5853 } else { 5854 assert(Opcode == Instruction::Store && 5855 "Expected Store Instruction at this point"); 5856 assert((!Indices.size() || Indices.size() == Factor) && 5857 "Interleaved store only supports fully-interleaved groups."); 5858 if (ST->hasAVX2()) 5859 if (const auto *Entry = CostTableLookup(AVX2InterleavedStoreTbl, Factor, 5860 ETy.getSimpleVT())) 5861 return MemOpCosts + Entry->Cost; 5862 5863 if (ST->hasSSE2()) 5864 if (const auto *Entry = CostTableLookup(SSE2InterleavedStoreTbl, Factor, 5865 ETy.getSimpleVT())) 5866 return MemOpCosts + Entry->Cost; 5867 } 5868 5869 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5870 Alignment, AddressSpace, CostKind, 5871 UseMaskForCond, UseMaskForGaps); 5872 } 5873