1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // X86 cost model. 56 // 57 //===----------------------------------------------------------------------===// 58 59 TargetTransformInfo::PopcntSupportKind 60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 61 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 62 // TODO: Currently the __builtin_popcount() implementation using SSE3 63 // instructions is inefficient. Once the problem is fixed, we should 64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 66 } 67 68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 69 TargetTransformInfo::CacheLevel Level) const { 70 switch (Level) { 71 case TargetTransformInfo::CacheLevel::L1D: 72 // - Penryn 73 // - Nehalem 74 // - Westmere 75 // - Sandy Bridge 76 // - Ivy Bridge 77 // - Haswell 78 // - Broadwell 79 // - Skylake 80 // - Kabylake 81 return 32 * 1024; // 32 KByte 82 case TargetTransformInfo::CacheLevel::L2D: 83 // - Penryn 84 // - Nehalem 85 // - Westmere 86 // - Sandy Bridge 87 // - Ivy Bridge 88 // - Haswell 89 // - Broadwell 90 // - Skylake 91 // - Kabylake 92 return 256 * 1024; // 256 KByte 93 } 94 95 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 96 } 97 98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 99 TargetTransformInfo::CacheLevel Level) const { 100 // - Penryn 101 // - Nehalem 102 // - Westmere 103 // - Sandy Bridge 104 // - Ivy Bridge 105 // - Haswell 106 // - Broadwell 107 // - Skylake 108 // - Kabylake 109 switch (Level) { 110 case TargetTransformInfo::CacheLevel::L1D: 111 LLVM_FALLTHROUGH; 112 case TargetTransformInfo::CacheLevel::L2D: 113 return 8; 114 } 115 116 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 117 } 118 119 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 120 bool Vector = (ClassID == 1); 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const { 133 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 134 if (Vector) { 135 if (ST->hasAVX512() && PreferVectorWidth >= 512) 136 return 512; 137 if (ST->hasAVX() && PreferVectorWidth >= 256) 138 return 256; 139 if (ST->hasSSE1() && PreferVectorWidth >= 128) 140 return 128; 141 return 0; 142 } 143 144 if (ST->is64Bit()) 145 return 64; 146 147 return 32; 148 } 149 150 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 151 return getRegisterBitWidth(true); 152 } 153 154 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 155 // If the loop will not be vectorized, don't interleave the loop. 156 // Let regular unroll to unroll the loop, which saves the overflow 157 // check and memory check cost. 158 if (VF == 1) 159 return 1; 160 161 if (ST->isAtom()) 162 return 1; 163 164 // Sandybridge and Haswell have multiple execution ports and pipelined 165 // vector units. 166 if (ST->hasAVX()) 167 return 4; 168 169 return 2; 170 } 171 172 int X86TTIImpl::getArithmeticInstrCost( 173 unsigned Opcode, Type *Ty, 174 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 175 TTI::OperandValueProperties Opd1PropInfo, 176 TTI::OperandValueProperties Opd2PropInfo, 177 ArrayRef<const Value *> Args) { 178 // Legalize the type. 179 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 180 181 int ISD = TLI->InstructionOpcodeToISD(Opcode); 182 assert(ISD && "Invalid opcode"); 183 184 static const CostTblEntry GLMCostTable[] = { 185 { ISD::FDIV, MVT::f32, 18 }, // divss 186 { ISD::FDIV, MVT::v4f32, 35 }, // divps 187 { ISD::FDIV, MVT::f64, 33 }, // divsd 188 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 189 }; 190 191 if (ST->isGLM()) 192 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 193 LT.second)) 194 return LT.first * Entry->Cost; 195 196 static const CostTblEntry SLMCostTable[] = { 197 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 198 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 199 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. 200 { ISD::FMUL, MVT::f64, 2 }, // mulsd 201 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 202 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 203 { ISD::FDIV, MVT::f32, 17 }, // divss 204 { ISD::FDIV, MVT::v4f32, 39 }, // divps 205 { ISD::FDIV, MVT::f64, 32 }, // divsd 206 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 207 { ISD::FADD, MVT::v2f64, 2 }, // addpd 208 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 209 // v2i64/v4i64 mul is custom lowered as a series of long: 210 // multiplies(3), shifts(3) and adds(2) 211 // slm muldq version throughput is 2 and addq throughput 4 212 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 213 // 3X4 (addq throughput) = 17 214 { ISD::MUL, MVT::v2i64, 17 }, 215 // slm addq\subq throughput is 4 216 { ISD::ADD, MVT::v2i64, 4 }, 217 { ISD::SUB, MVT::v2i64, 4 }, 218 }; 219 220 if (ST->isSLM()) { 221 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 222 // Check if the operands can be shrinked into a smaller datatype. 223 bool Op1Signed = false; 224 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 225 bool Op2Signed = false; 226 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 227 228 bool signedMode = Op1Signed | Op2Signed; 229 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 230 231 if (OpMinSize <= 7) 232 return LT.first * 3; // pmullw/sext 233 if (!signedMode && OpMinSize <= 8) 234 return LT.first * 3; // pmullw/zext 235 if (OpMinSize <= 15) 236 return LT.first * 5; // pmullw/pmulhw/pshuf 237 if (!signedMode && OpMinSize <= 16) 238 return LT.first * 5; // pmullw/pmulhw/pshuf 239 } 240 241 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 242 LT.second)) { 243 return LT.first * Entry->Cost; 244 } 245 } 246 247 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 248 ISD == ISD::UREM) && 249 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 250 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 251 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 252 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 253 // On X86, vector signed division by constants power-of-two are 254 // normally expanded to the sequence SRA + SRL + ADD + SRA. 255 // The OperandValue properties may not be the same as that of the previous 256 // operation; conservatively assume OP_None. 257 int Cost = 258 2 * getArithmeticInstrCost(Instruction::AShr, Ty, Op1Info, Op2Info, 259 TargetTransformInfo::OP_None, 260 TargetTransformInfo::OP_None); 261 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 262 TargetTransformInfo::OP_None, 263 TargetTransformInfo::OP_None); 264 Cost += getArithmeticInstrCost(Instruction::Add, Ty, Op1Info, Op2Info, 265 TargetTransformInfo::OP_None, 266 TargetTransformInfo::OP_None); 267 268 if (ISD == ISD::SREM) { 269 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 270 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info); 271 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, Op1Info, Op2Info); 272 } 273 274 return Cost; 275 } 276 277 // Vector unsigned division/remainder will be simplified to shifts/masks. 278 if (ISD == ISD::UDIV) 279 return getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 280 TargetTransformInfo::OP_None, 281 TargetTransformInfo::OP_None); 282 283 else // UREM 284 return getArithmeticInstrCost(Instruction::And, Ty, Op1Info, Op2Info, 285 TargetTransformInfo::OP_None, 286 TargetTransformInfo::OP_None); 287 } 288 289 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 290 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 291 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 292 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 293 }; 294 295 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 296 ST->hasBWI()) { 297 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 298 LT.second)) 299 return LT.first * Entry->Cost; 300 } 301 302 static const CostTblEntry AVX512UniformConstCostTable[] = { 303 { ISD::SRA, MVT::v2i64, 1 }, 304 { ISD::SRA, MVT::v4i64, 1 }, 305 { ISD::SRA, MVT::v8i64, 1 }, 306 }; 307 308 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 309 ST->hasAVX512()) { 310 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 311 LT.second)) 312 return LT.first * Entry->Cost; 313 } 314 315 static const CostTblEntry AVX2UniformConstCostTable[] = { 316 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 317 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 318 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 319 320 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 321 }; 322 323 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 324 ST->hasAVX2()) { 325 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 326 LT.second)) 327 return LT.first * Entry->Cost; 328 } 329 330 static const CostTblEntry SSE2UniformConstCostTable[] = { 331 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 332 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 333 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 334 335 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 336 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 337 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 338 }; 339 340 // XOP has faster vXi8 shifts. 341 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 342 ST->hasSSE2() && !ST->hasXOP()) { 343 if (const auto *Entry = 344 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 345 return LT.first * Entry->Cost; 346 } 347 348 static const CostTblEntry AVX512BWConstCostTable[] = { 349 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 350 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 351 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 352 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 353 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 354 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 355 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 356 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 357 }; 358 359 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 360 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 361 ST->hasBWI()) { 362 if (const auto *Entry = 363 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 364 return LT.first * Entry->Cost; 365 } 366 367 static const CostTblEntry AVX512ConstCostTable[] = { 368 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 369 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 370 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 371 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 372 }; 373 374 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 375 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 376 ST->hasAVX512()) { 377 if (const auto *Entry = 378 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 379 return LT.first * Entry->Cost; 380 } 381 382 static const CostTblEntry AVX2ConstCostTable[] = { 383 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 384 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 385 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 386 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 387 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 388 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 389 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 390 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 391 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 392 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 393 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 394 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 395 }; 396 397 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 398 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 399 ST->hasAVX2()) { 400 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 401 return LT.first * Entry->Cost; 402 } 403 404 static const CostTblEntry SSE2ConstCostTable[] = { 405 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 406 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 407 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 408 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 409 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 410 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 411 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 412 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 413 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 414 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 415 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 416 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 417 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 418 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 419 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 420 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 421 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 422 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 423 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 424 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 425 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 426 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 427 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 428 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 429 }; 430 431 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 432 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 433 ST->hasSSE2()) { 434 // pmuldq sequence. 435 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 436 return LT.first * 32; 437 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 438 return LT.first * 38; 439 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 440 return LT.first * 15; 441 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 442 return LT.first * 20; 443 444 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 445 return LT.first * Entry->Cost; 446 } 447 448 static const CostTblEntry AVX2UniformCostTable[] = { 449 // Uniform splats are cheaper for the following instructions. 450 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 451 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 452 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 453 }; 454 455 if (ST->hasAVX2() && 456 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 457 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 458 if (const auto *Entry = 459 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 460 return LT.first * Entry->Cost; 461 } 462 463 static const CostTblEntry SSE2UniformCostTable[] = { 464 // Uniform splats are cheaper for the following instructions. 465 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 466 { ISD::SHL, MVT::v4i32, 1 }, // pslld 467 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 468 469 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 470 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 471 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 472 473 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 474 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 475 }; 476 477 if (ST->hasSSE2() && 478 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 479 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 480 if (const auto *Entry = 481 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 482 return LT.first * Entry->Cost; 483 } 484 485 static const CostTblEntry AVX512DQCostTable[] = { 486 { ISD::MUL, MVT::v2i64, 1 }, 487 { ISD::MUL, MVT::v4i64, 1 }, 488 { ISD::MUL, MVT::v8i64, 1 } 489 }; 490 491 // Look for AVX512DQ lowering tricks for custom cases. 492 if (ST->hasDQI()) 493 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 494 return LT.first * Entry->Cost; 495 496 static const CostTblEntry AVX512BWCostTable[] = { 497 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 498 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 499 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 500 501 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 502 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 503 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 504 505 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 506 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 507 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 508 509 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 510 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 511 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 512 513 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence. 514 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence. 515 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence. 516 }; 517 518 // Look for AVX512BW lowering tricks for custom cases. 519 if (ST->hasBWI()) 520 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 521 return LT.first * Entry->Cost; 522 523 static const CostTblEntry AVX512CostTable[] = { 524 { ISD::SHL, MVT::v16i32, 1 }, 525 { ISD::SRL, MVT::v16i32, 1 }, 526 { ISD::SRA, MVT::v16i32, 1 }, 527 528 { ISD::SHL, MVT::v8i64, 1 }, 529 { ISD::SRL, MVT::v8i64, 1 }, 530 531 { ISD::SRA, MVT::v2i64, 1 }, 532 { ISD::SRA, MVT::v4i64, 1 }, 533 { ISD::SRA, MVT::v8i64, 1 }, 534 535 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence. 536 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence. 537 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 538 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 539 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 540 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add 541 542 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 543 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 544 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 545 546 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 547 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 548 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 549 }; 550 551 if (ST->hasAVX512()) 552 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 553 return LT.first * Entry->Cost; 554 555 static const CostTblEntry AVX2ShiftCostTable[] = { 556 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 557 // customize them to detect the cases where shift amount is a scalar one. 558 { ISD::SHL, MVT::v4i32, 1 }, 559 { ISD::SRL, MVT::v4i32, 1 }, 560 { ISD::SRA, MVT::v4i32, 1 }, 561 { ISD::SHL, MVT::v8i32, 1 }, 562 { ISD::SRL, MVT::v8i32, 1 }, 563 { ISD::SRA, MVT::v8i32, 1 }, 564 { ISD::SHL, MVT::v2i64, 1 }, 565 { ISD::SRL, MVT::v2i64, 1 }, 566 { ISD::SHL, MVT::v4i64, 1 }, 567 { ISD::SRL, MVT::v4i64, 1 }, 568 }; 569 570 // Look for AVX2 lowering tricks. 571 if (ST->hasAVX2()) { 572 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 573 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 574 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 575 // On AVX2, a packed v16i16 shift left by a constant build_vector 576 // is lowered into a vector multiply (vpmullw). 577 return getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info, 578 TargetTransformInfo::OP_None, 579 TargetTransformInfo::OP_None); 580 581 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 582 return LT.first * Entry->Cost; 583 } 584 585 static const CostTblEntry XOPShiftCostTable[] = { 586 // 128bit shifts take 1cy, but right shifts require negation beforehand. 587 { ISD::SHL, MVT::v16i8, 1 }, 588 { ISD::SRL, MVT::v16i8, 2 }, 589 { ISD::SRA, MVT::v16i8, 2 }, 590 { ISD::SHL, MVT::v8i16, 1 }, 591 { ISD::SRL, MVT::v8i16, 2 }, 592 { ISD::SRA, MVT::v8i16, 2 }, 593 { ISD::SHL, MVT::v4i32, 1 }, 594 { ISD::SRL, MVT::v4i32, 2 }, 595 { ISD::SRA, MVT::v4i32, 2 }, 596 { ISD::SHL, MVT::v2i64, 1 }, 597 { ISD::SRL, MVT::v2i64, 2 }, 598 { ISD::SRA, MVT::v2i64, 2 }, 599 // 256bit shifts require splitting if AVX2 didn't catch them above. 600 { ISD::SHL, MVT::v32i8, 2+2 }, 601 { ISD::SRL, MVT::v32i8, 4+2 }, 602 { ISD::SRA, MVT::v32i8, 4+2 }, 603 { ISD::SHL, MVT::v16i16, 2+2 }, 604 { ISD::SRL, MVT::v16i16, 4+2 }, 605 { ISD::SRA, MVT::v16i16, 4+2 }, 606 { ISD::SHL, MVT::v8i32, 2+2 }, 607 { ISD::SRL, MVT::v8i32, 4+2 }, 608 { ISD::SRA, MVT::v8i32, 4+2 }, 609 { ISD::SHL, MVT::v4i64, 2+2 }, 610 { ISD::SRL, MVT::v4i64, 4+2 }, 611 { ISD::SRA, MVT::v4i64, 4+2 }, 612 }; 613 614 // Look for XOP lowering tricks. 615 if (ST->hasXOP()) { 616 // If the right shift is constant then we'll fold the negation so 617 // it's as cheap as a left shift. 618 int ShiftISD = ISD; 619 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 620 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 621 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 622 ShiftISD = ISD::SHL; 623 if (const auto *Entry = 624 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 625 return LT.first * Entry->Cost; 626 } 627 628 static const CostTblEntry SSE2UniformShiftCostTable[] = { 629 // Uniform splats are cheaper for the following instructions. 630 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 631 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 632 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 633 634 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 635 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 636 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 637 638 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 639 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 640 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 641 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 642 }; 643 644 if (ST->hasSSE2() && 645 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 646 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 647 648 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 649 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 650 return LT.first * 4; // 2*psrad + shuffle. 651 652 if (const auto *Entry = 653 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 654 return LT.first * Entry->Cost; 655 } 656 657 if (ISD == ISD::SHL && 658 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 659 MVT VT = LT.second; 660 // Vector shift left by non uniform constant can be lowered 661 // into vector multiply. 662 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 663 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 664 ISD = ISD::MUL; 665 } 666 667 static const CostTblEntry AVX2CostTable[] = { 668 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. 669 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 670 671 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. 672 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 673 674 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. 675 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. 676 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. 677 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 678 679 { ISD::SUB, MVT::v32i8, 1 }, // psubb 680 { ISD::ADD, MVT::v32i8, 1 }, // paddb 681 { ISD::SUB, MVT::v16i16, 1 }, // psubw 682 { ISD::ADD, MVT::v16i16, 1 }, // paddw 683 { ISD::SUB, MVT::v8i32, 1 }, // psubd 684 { ISD::ADD, MVT::v8i32, 1 }, // paddd 685 { ISD::SUB, MVT::v4i64, 1 }, // psubq 686 { ISD::ADD, MVT::v4i64, 1 }, // paddq 687 688 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence. 689 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence. 690 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 691 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 692 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add 693 694 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 695 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 696 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 697 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 698 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 699 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 700 701 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 702 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 703 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 704 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 705 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 706 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 707 }; 708 709 // Look for AVX2 lowering tricks for custom cases. 710 if (ST->hasAVX2()) 711 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 712 return LT.first * Entry->Cost; 713 714 static const CostTblEntry AVX1CostTable[] = { 715 // We don't have to scalarize unsupported ops. We can issue two half-sized 716 // operations and we only need to extract the upper YMM half. 717 // Two ops + 1 extract + 1 insert = 4. 718 { ISD::MUL, MVT::v16i16, 4 }, 719 { ISD::MUL, MVT::v8i32, 4 }, 720 { ISD::SUB, MVT::v32i8, 4 }, 721 { ISD::ADD, MVT::v32i8, 4 }, 722 { ISD::SUB, MVT::v16i16, 4 }, 723 { ISD::ADD, MVT::v16i16, 4 }, 724 { ISD::SUB, MVT::v8i32, 4 }, 725 { ISD::ADD, MVT::v8i32, 4 }, 726 { ISD::SUB, MVT::v4i64, 4 }, 727 { ISD::ADD, MVT::v4i64, 4 }, 728 729 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 730 // are lowered as a series of long multiplies(3), shifts(3) and adds(2) 731 // Because we believe v4i64 to be a legal type, we must also include the 732 // extract+insert in the cost table. Therefore, the cost here is 18 733 // instead of 8. 734 { ISD::MUL, MVT::v4i64, 18 }, 735 736 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence. 737 738 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 739 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 740 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 741 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 742 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 743 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 744 }; 745 746 if (ST->hasAVX()) 747 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 748 return LT.first * Entry->Cost; 749 750 static const CostTblEntry SSE42CostTable[] = { 751 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 752 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 753 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 754 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 755 756 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 757 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 758 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 759 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 760 761 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 762 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 763 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 764 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 765 766 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 767 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 768 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 769 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 770 }; 771 772 if (ST->hasSSE42()) 773 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 774 return LT.first * Entry->Cost; 775 776 static const CostTblEntry SSE41CostTable[] = { 777 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 778 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split. 779 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 780 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 781 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 782 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split 783 784 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 785 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split. 786 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 787 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 788 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 789 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split. 790 791 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 792 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split. 793 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 794 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 795 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 796 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split. 797 798 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 799 }; 800 801 if (ST->hasSSE41()) 802 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 803 return LT.first * Entry->Cost; 804 805 static const CostTblEntry SSE2CostTable[] = { 806 // We don't correctly identify costs of casts because they are marked as 807 // custom. 808 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 809 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 810 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 811 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 812 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 813 814 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 815 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 816 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 817 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 818 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 819 820 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 821 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 822 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 823 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 824 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split. 825 826 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence. 827 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 828 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 829 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 830 831 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 832 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 833 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 834 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 835 836 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 837 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 838 839 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 840 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 841 }; 842 843 if (ST->hasSSE2()) 844 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 845 return LT.first * Entry->Cost; 846 847 static const CostTblEntry SSE1CostTable[] = { 848 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 849 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 850 851 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 852 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 853 854 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 855 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 856 857 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 858 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 859 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 860 861 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 862 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 863 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 864 }; 865 866 if (ST->hasSSE1()) 867 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 868 return LT.first * Entry->Cost; 869 870 // It is not a good idea to vectorize division. We have to scalarize it and 871 // in the process we will often end up having to spilling regular 872 // registers. The overhead of division is going to dominate most kernels 873 // anyways so try hard to prevent vectorization of division - it is 874 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 875 // to hide "20 cycles" for each lane. 876 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 877 ISD == ISD::UDIV || ISD == ISD::UREM)) { 878 int ScalarCost = getArithmeticInstrCost( 879 Opcode, Ty->getScalarType(), Op1Info, Op2Info, 880 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 881 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 882 } 883 884 // Fallback to the default implementation. 885 return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info); 886 } 887 888 int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, 889 Type *SubTp) { 890 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 891 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 892 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp); 893 894 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 895 if (Kind == TTI::SK_Transpose) 896 Kind = TTI::SK_PermuteTwoSrc; 897 898 // For Broadcasts we are splatting the first element from the first input 899 // register, so only need to reference that input and all the output 900 // registers are the same. 901 if (Kind == TTI::SK_Broadcast) 902 LT.first = 1; 903 904 // Subvector extractions are free if they start at the beginning of a 905 // vector and cheap if the subvectors are aligned. 906 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 907 int NumElts = LT.second.getVectorNumElements(); 908 if ((Index % NumElts) == 0) 909 return 0; 910 std::pair<int, MVT> SubLT = TLI->getTypeLegalizationCost(DL, SubTp); 911 if (SubLT.second.isVector()) { 912 int NumSubElts = SubLT.second.getVectorNumElements(); 913 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 914 return SubLT.first; 915 // Handle some cases for widening legalization. For now we only handle 916 // cases where the original subvector was naturally aligned and evenly 917 // fit in its legalized subvector type. 918 // FIXME: Remove some of the alignment restrictions. 919 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 920 // vectors. 921 int OrigSubElts = SubTp->getVectorNumElements(); 922 if (NumSubElts > OrigSubElts && 923 (Index % OrigSubElts) == 0 && (NumSubElts % OrigSubElts) == 0 && 924 LT.second.getVectorElementType() == 925 SubLT.second.getVectorElementType() && 926 LT.second.getVectorElementType().getSizeInBits() == 927 Tp->getVectorElementType()->getPrimitiveSizeInBits()) { 928 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 929 "Unexpected number of elements!"); 930 Type *VecTy = VectorType::get(Tp->getVectorElementType(), 931 LT.second.getVectorNumElements()); 932 Type *SubTy = VectorType::get(Tp->getVectorElementType(), 933 SubLT.second.getVectorNumElements()); 934 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 935 int ExtractCost = getShuffleCost(TTI::SK_ExtractSubvector, VecTy, 936 ExtractIndex, SubTy); 937 938 // If the original size is 32-bits or more, we can use pshufd. Otherwise 939 // if we have SSSE3 we can use pshufb. 940 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 941 return ExtractCost + 1; // pshufd or pshufb 942 943 assert(SubTp->getPrimitiveSizeInBits() == 16 && 944 "Unexpected vector size"); 945 946 return ExtractCost + 2; // worst case pshufhw + pshufd 947 } 948 } 949 } 950 951 // We are going to permute multiple sources and the result will be in multiple 952 // destinations. Providing an accurate cost only for splits where the element 953 // type remains the same. 954 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 955 MVT LegalVT = LT.second; 956 if (LegalVT.isVector() && 957 LegalVT.getVectorElementType().getSizeInBits() == 958 Tp->getVectorElementType()->getPrimitiveSizeInBits() && 959 LegalVT.getVectorNumElements() < Tp->getVectorNumElements()) { 960 961 unsigned VecTySize = DL.getTypeStoreSize(Tp); 962 unsigned LegalVTSize = LegalVT.getStoreSize(); 963 // Number of source vectors after legalization: 964 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 965 // Number of destination vectors after legalization: 966 unsigned NumOfDests = LT.first; 967 968 Type *SingleOpTy = VectorType::get(Tp->getVectorElementType(), 969 LegalVT.getVectorNumElements()); 970 971 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 972 return NumOfShuffles * 973 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 0, nullptr); 974 } 975 976 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 977 } 978 979 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 980 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 981 // We assume that source and destination have the same vector type. 982 int NumOfDests = LT.first; 983 int NumOfShufflesPerDest = LT.first * 2 - 1; 984 LT.first = NumOfDests * NumOfShufflesPerDest; 985 } 986 987 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 988 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 989 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 990 991 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 992 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 993 994 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 1}, // vpermt2b 995 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 1}, // vpermt2b 996 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1} // vpermt2b 997 }; 998 999 if (ST->hasVBMI()) 1000 if (const auto *Entry = 1001 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1002 return LT.first * Entry->Cost; 1003 1004 static const CostTblEntry AVX512BWShuffleTbl[] = { 1005 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1006 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1007 1008 {TTI::SK_Reverse, MVT::v32i16, 1}, // vpermw 1009 {TTI::SK_Reverse, MVT::v16i16, 1}, // vpermw 1010 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1011 1012 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 1}, // vpermw 1013 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 1}, // vpermw 1014 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // vpermw 1015 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1016 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 3}, // vpermw + zext/trunc 1017 1018 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 1}, // vpermt2w 1019 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 1}, // vpermt2w 1020 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpermt2w 1021 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 3}, // zext + vpermt2w + trunc 1022 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1023 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3} // zext + vpermt2w + trunc 1024 }; 1025 1026 if (ST->hasBWI()) 1027 if (const auto *Entry = 1028 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1029 return LT.first * Entry->Cost; 1030 1031 static const CostTblEntry AVX512ShuffleTbl[] = { 1032 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1033 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1034 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1035 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1036 1037 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1038 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1039 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1040 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1041 1042 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1043 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1044 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1045 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1046 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1047 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1048 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1049 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1050 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1051 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1052 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1053 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1054 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1055 1056 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1057 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1058 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1059 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1060 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1061 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1062 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1063 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1064 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1065 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1066 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1067 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1} // vpermt2d 1068 }; 1069 1070 if (ST->hasAVX512()) 1071 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1072 return LT.first * Entry->Cost; 1073 1074 static const CostTblEntry AVX2ShuffleTbl[] = { 1075 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1076 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1077 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1078 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1079 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1080 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1081 1082 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1083 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1084 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1085 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1086 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1087 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1088 1089 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1090 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1091 1092 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1093 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1094 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1095 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1096 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1097 // + vpblendvb 1098 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1099 // + vpblendvb 1100 1101 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1102 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1103 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1104 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1105 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1106 // + vpblendvb 1107 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1108 // + vpblendvb 1109 }; 1110 1111 if (ST->hasAVX2()) 1112 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1113 return LT.first * Entry->Cost; 1114 1115 static const CostTblEntry XOPShuffleTbl[] = { 1116 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1117 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1118 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1119 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1120 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1121 // + vinsertf128 1122 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1123 // + vinsertf128 1124 1125 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1126 // + vinsertf128 1127 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1128 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1129 // + vinsertf128 1130 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1131 }; 1132 1133 if (ST->hasXOP()) 1134 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1135 return LT.first * Entry->Cost; 1136 1137 static const CostTblEntry AVX1ShuffleTbl[] = { 1138 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1139 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1140 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1141 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1142 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1143 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1144 1145 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1146 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1147 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1148 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1149 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1150 // + vinsertf128 1151 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1152 // + vinsertf128 1153 1154 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1155 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1156 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1157 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1158 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1159 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1160 1161 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1162 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1163 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1164 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1165 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1166 // + 2*por + vinsertf128 1167 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1168 // + 2*por + vinsertf128 1169 1170 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1171 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1172 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1173 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1174 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1175 // + 4*por + vinsertf128 1176 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1177 // + 4*por + vinsertf128 1178 }; 1179 1180 if (ST->hasAVX()) 1181 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1182 return LT.first * Entry->Cost; 1183 1184 static const CostTblEntry SSE41ShuffleTbl[] = { 1185 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1186 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1187 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1188 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1189 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1190 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1191 }; 1192 1193 if (ST->hasSSE41()) 1194 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1195 return LT.first * Entry->Cost; 1196 1197 static const CostTblEntry SSSE3ShuffleTbl[] = { 1198 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1199 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1200 1201 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1202 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1203 1204 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1205 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1206 1207 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1208 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1209 1210 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1211 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1212 }; 1213 1214 if (ST->hasSSSE3()) 1215 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1216 return LT.first * Entry->Cost; 1217 1218 static const CostTblEntry SSE2ShuffleTbl[] = { 1219 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1220 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1221 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1222 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1223 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1224 1225 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1226 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1227 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1228 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1229 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1230 // + 2*pshufd + 2*unpck + packus 1231 1232 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1233 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1234 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1235 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1236 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1237 1238 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1239 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1240 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1241 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1242 // + pshufd/unpck 1243 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1244 // + 2*pshufd + 2*unpck + 2*packus 1245 1246 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1247 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1248 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1249 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1250 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1251 }; 1252 1253 if (ST->hasSSE2()) 1254 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1255 return LT.first * Entry->Cost; 1256 1257 static const CostTblEntry SSE1ShuffleTbl[] = { 1258 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1259 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1260 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1261 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1262 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1263 }; 1264 1265 if (ST->hasSSE1()) 1266 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1267 return LT.first * Entry->Cost; 1268 1269 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 1270 } 1271 1272 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 1273 const Instruction *I) { 1274 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1275 assert(ISD && "Invalid opcode"); 1276 1277 // FIXME: Need a better design of the cost table to handle non-simple types of 1278 // potential massive combinations (elem_num x src_type x dst_type). 1279 1280 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1281 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1282 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1283 1284 // Mask sign extend has an instruction. 1285 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1286 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1287 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1288 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1289 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1290 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1291 1292 // Mask zero extend is a load + broadcast. 1293 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1294 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1295 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1296 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1297 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1298 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1299 }; 1300 1301 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1302 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1303 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1304 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1305 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1306 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1307 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1308 1309 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1310 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1311 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1312 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1313 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1314 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1315 1316 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1317 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1318 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1319 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1320 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1321 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1322 1323 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1324 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1325 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1326 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1327 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1328 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1329 }; 1330 1331 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1332 // 256-bit wide vectors. 1333 1334 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1335 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1336 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1337 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1338 1339 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 }, 1340 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 }, 1341 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 }, 1342 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 1343 1344 // v16i1 -> v16i32 - load + broadcast 1345 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1346 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1347 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1348 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1349 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1350 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1351 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1352 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1353 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1354 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1355 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1356 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1357 1358 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1359 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1360 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1361 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1362 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1363 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1364 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1365 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1366 1367 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1368 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1369 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1370 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1371 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1372 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1373 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1374 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1375 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1376 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1377 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1378 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1379 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1380 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1381 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1382 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1383 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1384 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1385 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1386 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1387 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1388 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1389 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1390 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1391 1392 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1393 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 1394 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 1395 1396 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1397 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1398 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1399 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1400 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 2 }, 1401 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 2 }, 1402 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1403 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 2 }, 1404 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 2 }, 1405 }; 1406 1407 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1408 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1409 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1410 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1411 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1412 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1413 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1414 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1415 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1416 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1417 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1418 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1419 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1420 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1421 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1422 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1423 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1424 1425 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 1426 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 1427 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1428 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 1429 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1430 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 }, 1431 1432 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1433 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1434 1435 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1436 }; 1437 1438 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1439 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1440 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1441 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1442 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1443 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1444 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1445 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1446 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1447 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1448 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1449 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 4 }, 1450 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1451 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1452 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1453 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1454 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1455 1456 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 1457 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1458 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1459 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1460 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 1461 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 }, 1462 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 11 }, 1463 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 9 }, 1464 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 }, 1465 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 11 }, 1466 1467 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1468 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1469 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1470 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1471 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1472 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1473 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1474 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1475 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1476 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1477 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1478 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1479 1480 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1481 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1482 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1483 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1484 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1485 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1486 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1487 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1488 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1489 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 }, 1490 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 1491 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1492 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 1493 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1494 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1495 // The generic code to compute the scalar overhead is currently broken. 1496 // Workaround this limitation by estimating the scalarization overhead 1497 // here. We have roughly 10 instructions per scalar element. 1498 // Multiply that by the vector width. 1499 // FIXME: remove that when PR19268 is fixed. 1500 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1501 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1502 1503 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 }, 1504 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 }, 1505 // This node is expanded into scalarized operations but BasicTTI is overly 1506 // optimistic estimating its cost. It computes 3 per element (one 1507 // vector-extract, one scalar conversion and one vector-insert). The 1508 // problem is that the inserts form a read-modify-write chain so latency 1509 // should be factored in too. Inflating the cost per element by 1. 1510 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, 1511 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 1512 1513 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 1514 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 1515 }; 1516 1517 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 1518 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1519 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1520 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1521 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1522 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1523 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1524 1525 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1526 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 }, 1527 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1528 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1529 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1530 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1531 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1532 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1533 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1534 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1535 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1536 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1537 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1538 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1539 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1540 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1541 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1542 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1543 1544 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, 1545 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 1546 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 1547 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 1548 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 1549 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 1550 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 1551 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 1 }, // PSHUFB 1552 1553 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 1554 }; 1555 1556 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 1557 // These are somewhat magic numbers justified by looking at the output of 1558 // Intel's IACA, running some kernels and making sure when we take 1559 // legalization into account the throughput will be overestimated. 1560 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1561 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1562 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1563 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1564 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1565 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 2*10 }, 1566 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2*10 }, 1567 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1568 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 1569 1570 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1571 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1572 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1573 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1574 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1575 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, 1576 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 }, 1577 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1578 1579 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, 1580 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, 1581 1582 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 3 }, 1583 1584 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 }, 1585 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 1586 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 1587 1588 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1589 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 1590 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 1591 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 1592 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1593 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 1594 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1595 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 1596 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1597 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1598 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1599 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1600 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 1601 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 1602 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1603 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 1604 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1605 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 1606 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1607 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1608 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 1609 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 1610 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1611 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 1612 1613 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // PAND+PACKUSWB 1614 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 4 }, 1615 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, 1616 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 1617 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 3 }, // PAND+3*PACKUSWB 1618 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 1619 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 1620 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 1621 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1622 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 1623 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1624 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 1625 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 1626 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 1627 { ISD::TRUNCATE, MVT::v2i32, MVT::v2i64, 1 }, // PSHUFD 1628 }; 1629 1630 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 1631 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst); 1632 1633 if (ST->hasSSE2() && !ST->hasAVX()) { 1634 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1635 LTDest.second, LTSrc.second)) 1636 return LTSrc.first * Entry->Cost; 1637 } 1638 1639 EVT SrcTy = TLI->getValueType(DL, Src); 1640 EVT DstTy = TLI->getValueType(DL, Dst); 1641 1642 // The function getSimpleVT only handles simple value types. 1643 if (!SrcTy.isSimple() || !DstTy.isSimple()) 1644 return BaseT::getCastInstrCost(Opcode, Dst, Src); 1645 1646 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 1647 MVT SimpleDstTy = DstTy.getSimpleVT(); 1648 1649 // Make sure that neither type is going to be split before using the 1650 // AVX512 tables. This handles -mprefer-vector-width=256 1651 // with -min-legal-vector-width<=256 1652 if (TLI->getTypeAction(SimpleSrcTy) != TargetLowering::TypeSplitVector && 1653 TLI->getTypeAction(SimpleDstTy) != TargetLowering::TypeSplitVector) { 1654 if (ST->hasBWI()) 1655 if (const auto *Entry = ConvertCostTableLookup(AVX512BWConversionTbl, ISD, 1656 SimpleDstTy, SimpleSrcTy)) 1657 return Entry->Cost; 1658 1659 if (ST->hasDQI()) 1660 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 1661 SimpleDstTy, SimpleSrcTy)) 1662 return Entry->Cost; 1663 1664 if (ST->hasAVX512()) 1665 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 1666 SimpleDstTy, SimpleSrcTy)) 1667 return Entry->Cost; 1668 } 1669 1670 if (ST->hasAVX2()) { 1671 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 1672 SimpleDstTy, SimpleSrcTy)) 1673 return Entry->Cost; 1674 } 1675 1676 if (ST->hasAVX()) { 1677 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 1678 SimpleDstTy, SimpleSrcTy)) 1679 return Entry->Cost; 1680 } 1681 1682 if (ST->hasSSE41()) { 1683 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 1684 SimpleDstTy, SimpleSrcTy)) 1685 return Entry->Cost; 1686 } 1687 1688 if (ST->hasSSE2()) { 1689 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1690 SimpleDstTy, SimpleSrcTy)) 1691 return Entry->Cost; 1692 } 1693 1694 return BaseT::getCastInstrCost(Opcode, Dst, Src, I); 1695 } 1696 1697 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 1698 const Instruction *I) { 1699 // Legalize the type. 1700 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 1701 1702 MVT MTy = LT.second; 1703 1704 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1705 assert(ISD && "Invalid opcode"); 1706 1707 unsigned ExtraCost = 0; 1708 if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) { 1709 // Some vector comparison predicates cost extra instructions. 1710 if (MTy.isVector() && 1711 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 1712 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 1713 ST->hasBWI())) { 1714 switch (cast<CmpInst>(I)->getPredicate()) { 1715 case CmpInst::Predicate::ICMP_NE: 1716 // xor(cmpeq(x,y),-1) 1717 ExtraCost = 1; 1718 break; 1719 case CmpInst::Predicate::ICMP_SGE: 1720 case CmpInst::Predicate::ICMP_SLE: 1721 // xor(cmpgt(x,y),-1) 1722 ExtraCost = 1; 1723 break; 1724 case CmpInst::Predicate::ICMP_ULT: 1725 case CmpInst::Predicate::ICMP_UGT: 1726 // cmpgt(xor(x,signbit),xor(y,signbit)) 1727 // xor(cmpeq(pmaxu(x,y),x),-1) 1728 ExtraCost = 2; 1729 break; 1730 case CmpInst::Predicate::ICMP_ULE: 1731 case CmpInst::Predicate::ICMP_UGE: 1732 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 1733 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 1734 // cmpeq(psubus(x,y),0) 1735 // cmpeq(pminu(x,y),x) 1736 ExtraCost = 1; 1737 } else { 1738 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 1739 ExtraCost = 3; 1740 } 1741 break; 1742 default: 1743 break; 1744 } 1745 } 1746 } 1747 1748 static const CostTblEntry SLMCostTbl[] = { 1749 // slm pcmpeq/pcmpgt throughput is 2 1750 { ISD::SETCC, MVT::v2i64, 2 }, 1751 }; 1752 1753 static const CostTblEntry AVX512BWCostTbl[] = { 1754 { ISD::SETCC, MVT::v32i16, 1 }, 1755 { ISD::SETCC, MVT::v64i8, 1 }, 1756 1757 { ISD::SELECT, MVT::v32i16, 1 }, 1758 { ISD::SELECT, MVT::v64i8, 1 }, 1759 }; 1760 1761 static const CostTblEntry AVX512CostTbl[] = { 1762 { ISD::SETCC, MVT::v8i64, 1 }, 1763 { ISD::SETCC, MVT::v16i32, 1 }, 1764 { ISD::SETCC, MVT::v8f64, 1 }, 1765 { ISD::SETCC, MVT::v16f32, 1 }, 1766 1767 { ISD::SELECT, MVT::v8i64, 1 }, 1768 { ISD::SELECT, MVT::v16i32, 1 }, 1769 { ISD::SELECT, MVT::v8f64, 1 }, 1770 { ISD::SELECT, MVT::v16f32, 1 }, 1771 }; 1772 1773 static const CostTblEntry AVX2CostTbl[] = { 1774 { ISD::SETCC, MVT::v4i64, 1 }, 1775 { ISD::SETCC, MVT::v8i32, 1 }, 1776 { ISD::SETCC, MVT::v16i16, 1 }, 1777 { ISD::SETCC, MVT::v32i8, 1 }, 1778 1779 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 1780 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 1781 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 1782 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 1783 }; 1784 1785 static const CostTblEntry AVX1CostTbl[] = { 1786 { ISD::SETCC, MVT::v4f64, 1 }, 1787 { ISD::SETCC, MVT::v8f32, 1 }, 1788 // AVX1 does not support 8-wide integer compare. 1789 { ISD::SETCC, MVT::v4i64, 4 }, 1790 { ISD::SETCC, MVT::v8i32, 4 }, 1791 { ISD::SETCC, MVT::v16i16, 4 }, 1792 { ISD::SETCC, MVT::v32i8, 4 }, 1793 1794 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 1795 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 1796 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 1797 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 1798 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 1799 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 1800 }; 1801 1802 static const CostTblEntry SSE42CostTbl[] = { 1803 { ISD::SETCC, MVT::v2f64, 1 }, 1804 { ISD::SETCC, MVT::v4f32, 1 }, 1805 { ISD::SETCC, MVT::v2i64, 1 }, 1806 }; 1807 1808 static const CostTblEntry SSE41CostTbl[] = { 1809 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 1810 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 1811 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 1812 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 1813 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 1814 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 1815 }; 1816 1817 static const CostTblEntry SSE2CostTbl[] = { 1818 { ISD::SETCC, MVT::v2f64, 2 }, 1819 { ISD::SETCC, MVT::f64, 1 }, 1820 { ISD::SETCC, MVT::v2i64, 8 }, 1821 { ISD::SETCC, MVT::v4i32, 1 }, 1822 { ISD::SETCC, MVT::v8i16, 1 }, 1823 { ISD::SETCC, MVT::v16i8, 1 }, 1824 1825 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 1826 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 1827 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 1828 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 1829 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 1830 }; 1831 1832 static const CostTblEntry SSE1CostTbl[] = { 1833 { ISD::SETCC, MVT::v4f32, 2 }, 1834 { ISD::SETCC, MVT::f32, 1 }, 1835 1836 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 1837 }; 1838 1839 if (ST->isSLM()) 1840 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 1841 return LT.first * (ExtraCost + Entry->Cost); 1842 1843 if (ST->hasBWI()) 1844 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 1845 return LT.first * (ExtraCost + Entry->Cost); 1846 1847 if (ST->hasAVX512()) 1848 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 1849 return LT.first * (ExtraCost + Entry->Cost); 1850 1851 if (ST->hasAVX2()) 1852 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 1853 return LT.first * (ExtraCost + Entry->Cost); 1854 1855 if (ST->hasAVX()) 1856 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 1857 return LT.first * (ExtraCost + Entry->Cost); 1858 1859 if (ST->hasSSE42()) 1860 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 1861 return LT.first * (ExtraCost + Entry->Cost); 1862 1863 if (ST->hasSSE41()) 1864 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 1865 return LT.first * (ExtraCost + Entry->Cost); 1866 1867 if (ST->hasSSE2()) 1868 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 1869 return LT.first * (ExtraCost + Entry->Cost); 1870 1871 if (ST->hasSSE1()) 1872 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 1873 return LT.first * (ExtraCost + Entry->Cost); 1874 1875 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I); 1876 } 1877 1878 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 1879 1880 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 1881 ArrayRef<Type *> Tys, FastMathFlags FMF, 1882 unsigned ScalarizationCostPassed) { 1883 // Costs should match the codegen from: 1884 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 1885 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 1886 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 1887 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 1888 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 1889 static const CostTblEntry AVX512CDCostTbl[] = { 1890 { ISD::CTLZ, MVT::v8i64, 1 }, 1891 { ISD::CTLZ, MVT::v16i32, 1 }, 1892 { ISD::CTLZ, MVT::v32i16, 8 }, 1893 { ISD::CTLZ, MVT::v64i8, 20 }, 1894 { ISD::CTLZ, MVT::v4i64, 1 }, 1895 { ISD::CTLZ, MVT::v8i32, 1 }, 1896 { ISD::CTLZ, MVT::v16i16, 4 }, 1897 { ISD::CTLZ, MVT::v32i8, 10 }, 1898 { ISD::CTLZ, MVT::v2i64, 1 }, 1899 { ISD::CTLZ, MVT::v4i32, 1 }, 1900 { ISD::CTLZ, MVT::v8i16, 4 }, 1901 { ISD::CTLZ, MVT::v16i8, 4 }, 1902 }; 1903 static const CostTblEntry AVX512BWCostTbl[] = { 1904 { ISD::BITREVERSE, MVT::v8i64, 5 }, 1905 { ISD::BITREVERSE, MVT::v16i32, 5 }, 1906 { ISD::BITREVERSE, MVT::v32i16, 5 }, 1907 { ISD::BITREVERSE, MVT::v64i8, 5 }, 1908 { ISD::CTLZ, MVT::v8i64, 23 }, 1909 { ISD::CTLZ, MVT::v16i32, 22 }, 1910 { ISD::CTLZ, MVT::v32i16, 18 }, 1911 { ISD::CTLZ, MVT::v64i8, 17 }, 1912 { ISD::CTPOP, MVT::v8i64, 7 }, 1913 { ISD::CTPOP, MVT::v16i32, 11 }, 1914 { ISD::CTPOP, MVT::v32i16, 9 }, 1915 { ISD::CTPOP, MVT::v64i8, 6 }, 1916 { ISD::CTTZ, MVT::v8i64, 10 }, 1917 { ISD::CTTZ, MVT::v16i32, 14 }, 1918 { ISD::CTTZ, MVT::v32i16, 12 }, 1919 { ISD::CTTZ, MVT::v64i8, 9 }, 1920 { ISD::SADDSAT, MVT::v32i16, 1 }, 1921 { ISD::SADDSAT, MVT::v64i8, 1 }, 1922 { ISD::SSUBSAT, MVT::v32i16, 1 }, 1923 { ISD::SSUBSAT, MVT::v64i8, 1 }, 1924 { ISD::UADDSAT, MVT::v32i16, 1 }, 1925 { ISD::UADDSAT, MVT::v64i8, 1 }, 1926 { ISD::USUBSAT, MVT::v32i16, 1 }, 1927 { ISD::USUBSAT, MVT::v64i8, 1 }, 1928 }; 1929 static const CostTblEntry AVX512CostTbl[] = { 1930 { ISD::BITREVERSE, MVT::v8i64, 36 }, 1931 { ISD::BITREVERSE, MVT::v16i32, 24 }, 1932 { ISD::CTLZ, MVT::v8i64, 29 }, 1933 { ISD::CTLZ, MVT::v16i32, 35 }, 1934 { ISD::CTPOP, MVT::v8i64, 16 }, 1935 { ISD::CTPOP, MVT::v16i32, 24 }, 1936 { ISD::CTTZ, MVT::v8i64, 20 }, 1937 { ISD::CTTZ, MVT::v16i32, 28 }, 1938 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 1939 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 1940 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 1941 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 1942 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 1943 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 1944 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 1945 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 1946 }; 1947 static const CostTblEntry XOPCostTbl[] = { 1948 { ISD::BITREVERSE, MVT::v4i64, 4 }, 1949 { ISD::BITREVERSE, MVT::v8i32, 4 }, 1950 { ISD::BITREVERSE, MVT::v16i16, 4 }, 1951 { ISD::BITREVERSE, MVT::v32i8, 4 }, 1952 { ISD::BITREVERSE, MVT::v2i64, 1 }, 1953 { ISD::BITREVERSE, MVT::v4i32, 1 }, 1954 { ISD::BITREVERSE, MVT::v8i16, 1 }, 1955 { ISD::BITREVERSE, MVT::v16i8, 1 }, 1956 { ISD::BITREVERSE, MVT::i64, 3 }, 1957 { ISD::BITREVERSE, MVT::i32, 3 }, 1958 { ISD::BITREVERSE, MVT::i16, 3 }, 1959 { ISD::BITREVERSE, MVT::i8, 3 } 1960 }; 1961 static const CostTblEntry AVX2CostTbl[] = { 1962 { ISD::BITREVERSE, MVT::v4i64, 5 }, 1963 { ISD::BITREVERSE, MVT::v8i32, 5 }, 1964 { ISD::BITREVERSE, MVT::v16i16, 5 }, 1965 { ISD::BITREVERSE, MVT::v32i8, 5 }, 1966 { ISD::BSWAP, MVT::v4i64, 1 }, 1967 { ISD::BSWAP, MVT::v8i32, 1 }, 1968 { ISD::BSWAP, MVT::v16i16, 1 }, 1969 { ISD::CTLZ, MVT::v4i64, 23 }, 1970 { ISD::CTLZ, MVT::v8i32, 18 }, 1971 { ISD::CTLZ, MVT::v16i16, 14 }, 1972 { ISD::CTLZ, MVT::v32i8, 9 }, 1973 { ISD::CTPOP, MVT::v4i64, 7 }, 1974 { ISD::CTPOP, MVT::v8i32, 11 }, 1975 { ISD::CTPOP, MVT::v16i16, 9 }, 1976 { ISD::CTPOP, MVT::v32i8, 6 }, 1977 { ISD::CTTZ, MVT::v4i64, 10 }, 1978 { ISD::CTTZ, MVT::v8i32, 14 }, 1979 { ISD::CTTZ, MVT::v16i16, 12 }, 1980 { ISD::CTTZ, MVT::v32i8, 9 }, 1981 { ISD::SADDSAT, MVT::v16i16, 1 }, 1982 { ISD::SADDSAT, MVT::v32i8, 1 }, 1983 { ISD::SSUBSAT, MVT::v16i16, 1 }, 1984 { ISD::SSUBSAT, MVT::v32i8, 1 }, 1985 { ISD::UADDSAT, MVT::v16i16, 1 }, 1986 { ISD::UADDSAT, MVT::v32i8, 1 }, 1987 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 1988 { ISD::USUBSAT, MVT::v16i16, 1 }, 1989 { ISD::USUBSAT, MVT::v32i8, 1 }, 1990 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 1991 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 1992 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 1993 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 1994 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 1995 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 1996 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 1997 }; 1998 static const CostTblEntry AVX1CostTbl[] = { 1999 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 2000 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 2001 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 2002 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 2003 { ISD::BSWAP, MVT::v4i64, 4 }, 2004 { ISD::BSWAP, MVT::v8i32, 4 }, 2005 { ISD::BSWAP, MVT::v16i16, 4 }, 2006 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 2007 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 2008 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 2009 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2010 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 2011 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 2012 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 2013 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 2014 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 2015 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 2016 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 2017 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2018 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2019 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2020 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2021 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2022 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2023 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2024 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 2025 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2026 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2027 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 2028 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 2029 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 2030 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 2031 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 2032 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 2033 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 2034 }; 2035 static const CostTblEntry GLMCostTbl[] = { 2036 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 2037 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 2038 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 2039 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 2040 }; 2041 static const CostTblEntry SLMCostTbl[] = { 2042 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 2043 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 2044 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 2045 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 2046 }; 2047 static const CostTblEntry SSE42CostTbl[] = { 2048 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 2049 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 2050 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 2051 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 2052 }; 2053 static const CostTblEntry SSSE3CostTbl[] = { 2054 { ISD::BITREVERSE, MVT::v2i64, 5 }, 2055 { ISD::BITREVERSE, MVT::v4i32, 5 }, 2056 { ISD::BITREVERSE, MVT::v8i16, 5 }, 2057 { ISD::BITREVERSE, MVT::v16i8, 5 }, 2058 { ISD::BSWAP, MVT::v2i64, 1 }, 2059 { ISD::BSWAP, MVT::v4i32, 1 }, 2060 { ISD::BSWAP, MVT::v8i16, 1 }, 2061 { ISD::CTLZ, MVT::v2i64, 23 }, 2062 { ISD::CTLZ, MVT::v4i32, 18 }, 2063 { ISD::CTLZ, MVT::v8i16, 14 }, 2064 { ISD::CTLZ, MVT::v16i8, 9 }, 2065 { ISD::CTPOP, MVT::v2i64, 7 }, 2066 { ISD::CTPOP, MVT::v4i32, 11 }, 2067 { ISD::CTPOP, MVT::v8i16, 9 }, 2068 { ISD::CTPOP, MVT::v16i8, 6 }, 2069 { ISD::CTTZ, MVT::v2i64, 10 }, 2070 { ISD::CTTZ, MVT::v4i32, 14 }, 2071 { ISD::CTTZ, MVT::v8i16, 12 }, 2072 { ISD::CTTZ, MVT::v16i8, 9 } 2073 }; 2074 static const CostTblEntry SSE2CostTbl[] = { 2075 { ISD::BITREVERSE, MVT::v2i64, 29 }, 2076 { ISD::BITREVERSE, MVT::v4i32, 27 }, 2077 { ISD::BITREVERSE, MVT::v8i16, 27 }, 2078 { ISD::BITREVERSE, MVT::v16i8, 20 }, 2079 { ISD::BSWAP, MVT::v2i64, 7 }, 2080 { ISD::BSWAP, MVT::v4i32, 7 }, 2081 { ISD::BSWAP, MVT::v8i16, 7 }, 2082 { ISD::CTLZ, MVT::v2i64, 25 }, 2083 { ISD::CTLZ, MVT::v4i32, 26 }, 2084 { ISD::CTLZ, MVT::v8i16, 20 }, 2085 { ISD::CTLZ, MVT::v16i8, 17 }, 2086 { ISD::CTPOP, MVT::v2i64, 12 }, 2087 { ISD::CTPOP, MVT::v4i32, 15 }, 2088 { ISD::CTPOP, MVT::v8i16, 13 }, 2089 { ISD::CTPOP, MVT::v16i8, 10 }, 2090 { ISD::CTTZ, MVT::v2i64, 14 }, 2091 { ISD::CTTZ, MVT::v4i32, 18 }, 2092 { ISD::CTTZ, MVT::v8i16, 16 }, 2093 { ISD::CTTZ, MVT::v16i8, 13 }, 2094 { ISD::SADDSAT, MVT::v8i16, 1 }, 2095 { ISD::SADDSAT, MVT::v16i8, 1 }, 2096 { ISD::SSUBSAT, MVT::v8i16, 1 }, 2097 { ISD::SSUBSAT, MVT::v16i8, 1 }, 2098 { ISD::UADDSAT, MVT::v8i16, 1 }, 2099 { ISD::UADDSAT, MVT::v16i8, 1 }, 2100 { ISD::USUBSAT, MVT::v8i16, 1 }, 2101 { ISD::USUBSAT, MVT::v16i8, 1 }, 2102 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 2103 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 2104 }; 2105 static const CostTblEntry SSE1CostTbl[] = { 2106 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 2107 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 2108 }; 2109 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 2110 { ISD::CTLZ, MVT::i64, 1 }, 2111 }; 2112 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 2113 { ISD::CTLZ, MVT::i32, 1 }, 2114 { ISD::CTLZ, MVT::i16, 1 }, 2115 { ISD::CTLZ, MVT::i8, 1 }, 2116 }; 2117 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 2118 { ISD::CTPOP, MVT::i64, 1 }, 2119 }; 2120 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 2121 { ISD::CTPOP, MVT::i32, 1 }, 2122 { ISD::CTPOP, MVT::i16, 1 }, 2123 { ISD::CTPOP, MVT::i8, 1 }, 2124 }; 2125 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2126 { ISD::BITREVERSE, MVT::i64, 14 }, 2127 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 2128 { ISD::CTPOP, MVT::i64, 10 }, 2129 { ISD::SADDO, MVT::i64, 1 }, 2130 { ISD::UADDO, MVT::i64, 1 }, 2131 }; 2132 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2133 { ISD::BITREVERSE, MVT::i32, 14 }, 2134 { ISD::BITREVERSE, MVT::i16, 14 }, 2135 { ISD::BITREVERSE, MVT::i8, 11 }, 2136 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 2137 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 2138 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 2139 { ISD::CTPOP, MVT::i32, 8 }, 2140 { ISD::CTPOP, MVT::i16, 9 }, 2141 { ISD::CTPOP, MVT::i8, 7 }, 2142 { ISD::SADDO, MVT::i32, 1 }, 2143 { ISD::SADDO, MVT::i16, 1 }, 2144 { ISD::SADDO, MVT::i8, 1 }, 2145 { ISD::UADDO, MVT::i32, 1 }, 2146 { ISD::UADDO, MVT::i16, 1 }, 2147 { ISD::UADDO, MVT::i8, 1 }, 2148 }; 2149 2150 Type *OpTy = RetTy; 2151 unsigned ISD = ISD::DELETED_NODE; 2152 switch (IID) { 2153 default: 2154 break; 2155 case Intrinsic::bitreverse: 2156 ISD = ISD::BITREVERSE; 2157 break; 2158 case Intrinsic::bswap: 2159 ISD = ISD::BSWAP; 2160 break; 2161 case Intrinsic::ctlz: 2162 ISD = ISD::CTLZ; 2163 break; 2164 case Intrinsic::ctpop: 2165 ISD = ISD::CTPOP; 2166 break; 2167 case Intrinsic::cttz: 2168 ISD = ISD::CTTZ; 2169 break; 2170 case Intrinsic::sadd_sat: 2171 ISD = ISD::SADDSAT; 2172 break; 2173 case Intrinsic::ssub_sat: 2174 ISD = ISD::SSUBSAT; 2175 break; 2176 case Intrinsic::uadd_sat: 2177 ISD = ISD::UADDSAT; 2178 break; 2179 case Intrinsic::usub_sat: 2180 ISD = ISD::USUBSAT; 2181 break; 2182 case Intrinsic::sqrt: 2183 ISD = ISD::FSQRT; 2184 break; 2185 case Intrinsic::sadd_with_overflow: 2186 case Intrinsic::ssub_with_overflow: 2187 // SSUBO has same costs so don't duplicate. 2188 ISD = ISD::SADDO; 2189 OpTy = RetTy->getContainedType(0); 2190 break; 2191 case Intrinsic::uadd_with_overflow: 2192 case Intrinsic::usub_with_overflow: 2193 // USUBO has same costs so don't duplicate. 2194 ISD = ISD::UADDO; 2195 OpTy = RetTy->getContainedType(0); 2196 break; 2197 } 2198 2199 if (ISD != ISD::DELETED_NODE) { 2200 // Legalize the type. 2201 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 2202 MVT MTy = LT.second; 2203 2204 // Attempt to lookup cost. 2205 if (ST->isGLM()) 2206 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 2207 return LT.first * Entry->Cost; 2208 2209 if (ST->isSLM()) 2210 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2211 return LT.first * Entry->Cost; 2212 2213 if (ST->hasCDI()) 2214 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 2215 return LT.first * Entry->Cost; 2216 2217 if (ST->hasBWI()) 2218 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2219 return LT.first * Entry->Cost; 2220 2221 if (ST->hasAVX512()) 2222 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2223 return LT.first * Entry->Cost; 2224 2225 if (ST->hasXOP()) 2226 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2227 return LT.first * Entry->Cost; 2228 2229 if (ST->hasAVX2()) 2230 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2231 return LT.first * Entry->Cost; 2232 2233 if (ST->hasAVX()) 2234 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2235 return LT.first * Entry->Cost; 2236 2237 if (ST->hasSSE42()) 2238 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2239 return LT.first * Entry->Cost; 2240 2241 if (ST->hasSSSE3()) 2242 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 2243 return LT.first * Entry->Cost; 2244 2245 if (ST->hasSSE2()) 2246 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2247 return LT.first * Entry->Cost; 2248 2249 if (ST->hasSSE1()) 2250 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2251 return LT.first * Entry->Cost; 2252 2253 if (ST->hasLZCNT()) { 2254 if (ST->is64Bit()) 2255 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 2256 return LT.first * Entry->Cost; 2257 2258 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 2259 return LT.first * Entry->Cost; 2260 } 2261 2262 if (ST->hasPOPCNT()) { 2263 if (ST->is64Bit()) 2264 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 2265 return LT.first * Entry->Cost; 2266 2267 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 2268 return LT.first * Entry->Cost; 2269 } 2270 2271 // TODO - add BMI (TZCNT) scalar handling 2272 2273 if (ST->is64Bit()) 2274 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2275 return LT.first * Entry->Cost; 2276 2277 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2278 return LT.first * Entry->Cost; 2279 } 2280 2281 return BaseT::getIntrinsicInstrCost(IID, RetTy, Tys, FMF, ScalarizationCostPassed); 2282 } 2283 2284 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 2285 ArrayRef<Value *> Args, FastMathFlags FMF, 2286 unsigned VF) { 2287 static const CostTblEntry AVX512CostTbl[] = { 2288 { ISD::ROTL, MVT::v8i64, 1 }, 2289 { ISD::ROTL, MVT::v4i64, 1 }, 2290 { ISD::ROTL, MVT::v2i64, 1 }, 2291 { ISD::ROTL, MVT::v16i32, 1 }, 2292 { ISD::ROTL, MVT::v8i32, 1 }, 2293 { ISD::ROTL, MVT::v4i32, 1 }, 2294 { ISD::ROTR, MVT::v8i64, 1 }, 2295 { ISD::ROTR, MVT::v4i64, 1 }, 2296 { ISD::ROTR, MVT::v2i64, 1 }, 2297 { ISD::ROTR, MVT::v16i32, 1 }, 2298 { ISD::ROTR, MVT::v8i32, 1 }, 2299 { ISD::ROTR, MVT::v4i32, 1 } 2300 }; 2301 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 2302 static const CostTblEntry XOPCostTbl[] = { 2303 { ISD::ROTL, MVT::v4i64, 4 }, 2304 { ISD::ROTL, MVT::v8i32, 4 }, 2305 { ISD::ROTL, MVT::v16i16, 4 }, 2306 { ISD::ROTL, MVT::v32i8, 4 }, 2307 { ISD::ROTL, MVT::v2i64, 1 }, 2308 { ISD::ROTL, MVT::v4i32, 1 }, 2309 { ISD::ROTL, MVT::v8i16, 1 }, 2310 { ISD::ROTL, MVT::v16i8, 1 }, 2311 { ISD::ROTR, MVT::v4i64, 6 }, 2312 { ISD::ROTR, MVT::v8i32, 6 }, 2313 { ISD::ROTR, MVT::v16i16, 6 }, 2314 { ISD::ROTR, MVT::v32i8, 6 }, 2315 { ISD::ROTR, MVT::v2i64, 2 }, 2316 { ISD::ROTR, MVT::v4i32, 2 }, 2317 { ISD::ROTR, MVT::v8i16, 2 }, 2318 { ISD::ROTR, MVT::v16i8, 2 } 2319 }; 2320 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2321 { ISD::ROTL, MVT::i64, 1 }, 2322 { ISD::ROTR, MVT::i64, 1 }, 2323 { ISD::FSHL, MVT::i64, 4 } 2324 }; 2325 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2326 { ISD::ROTL, MVT::i32, 1 }, 2327 { ISD::ROTL, MVT::i16, 1 }, 2328 { ISD::ROTL, MVT::i8, 1 }, 2329 { ISD::ROTR, MVT::i32, 1 }, 2330 { ISD::ROTR, MVT::i16, 1 }, 2331 { ISD::ROTR, MVT::i8, 1 }, 2332 { ISD::FSHL, MVT::i32, 4 }, 2333 { ISD::FSHL, MVT::i16, 4 }, 2334 { ISD::FSHL, MVT::i8, 4 } 2335 }; 2336 2337 unsigned ISD = ISD::DELETED_NODE; 2338 switch (IID) { 2339 default: 2340 break; 2341 case Intrinsic::fshl: 2342 ISD = ISD::FSHL; 2343 if (Args[0] == Args[1]) 2344 ISD = ISD::ROTL; 2345 break; 2346 case Intrinsic::fshr: 2347 // FSHR has same costs so don't duplicate. 2348 ISD = ISD::FSHL; 2349 if (Args[0] == Args[1]) 2350 ISD = ISD::ROTR; 2351 break; 2352 } 2353 2354 if (ISD != ISD::DELETED_NODE) { 2355 // Legalize the type. 2356 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 2357 MVT MTy = LT.second; 2358 2359 // Attempt to lookup cost. 2360 if (ST->hasAVX512()) 2361 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2362 return LT.first * Entry->Cost; 2363 2364 if (ST->hasXOP()) 2365 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2366 return LT.first * Entry->Cost; 2367 2368 if (ST->is64Bit()) 2369 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2370 return LT.first * Entry->Cost; 2371 2372 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2373 return LT.first * Entry->Cost; 2374 } 2375 2376 return BaseT::getIntrinsicInstrCost(IID, RetTy, Args, FMF, VF); 2377 } 2378 2379 int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { 2380 assert(Val->isVectorTy() && "This must be a vector type"); 2381 2382 Type *ScalarType = Val->getScalarType(); 2383 2384 if (Index != -1U) { 2385 // Legalize the type. 2386 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 2387 2388 // This type is legalized to a scalar type. 2389 if (!LT.second.isVector()) 2390 return 0; 2391 2392 // The type may be split. Normalize the index to the new type. 2393 unsigned Width = LT.second.getVectorNumElements(); 2394 Index = Index % Width; 2395 2396 // Floating point scalars are already located in index #0. 2397 if (ScalarType->isFloatingPointTy() && Index == 0) 2398 return 0; 2399 } 2400 2401 // Add to the base cost if we know that the extracted element of a vector is 2402 // destined to be moved to and used in the integer register file. 2403 int RegisterFileMoveCost = 0; 2404 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 2405 RegisterFileMoveCost = 1; 2406 2407 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 2408 } 2409 2410 int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 2411 MaybeAlign Alignment, unsigned AddressSpace, 2412 const Instruction *I) { 2413 // Handle non-power-of-two vectors such as <3 x float> 2414 if (VectorType *VTy = dyn_cast<VectorType>(Src)) { 2415 unsigned NumElem = VTy->getVectorNumElements(); 2416 2417 // Handle a few common cases: 2418 // <3 x float> 2419 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 2420 // Cost = 64 bit store + extract + 32 bit store. 2421 return 3; 2422 2423 // <3 x double> 2424 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 2425 // Cost = 128 bit store + unpack + 64 bit store. 2426 return 3; 2427 2428 // Assume that all other non-power-of-two numbers are scalarized. 2429 if (!isPowerOf2_32(NumElem)) { 2430 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment, 2431 AddressSpace); 2432 int SplitCost = getScalarizationOverhead(Src, Opcode == Instruction::Load, 2433 Opcode == Instruction::Store); 2434 return NumElem * Cost + SplitCost; 2435 } 2436 } 2437 2438 // Legalize the type. 2439 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 2440 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 2441 "Invalid Opcode"); 2442 2443 // Each load/store unit costs 1. 2444 int Cost = LT.first * 1; 2445 2446 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a 2447 // proxy for a double-pumped AVX memory interface such as on Sandybridge. 2448 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow()) 2449 Cost *= 2; 2450 2451 return Cost; 2452 } 2453 2454 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, 2455 unsigned Alignment, 2456 unsigned AddressSpace) { 2457 bool IsLoad = (Instruction::Load == Opcode); 2458 bool IsStore = (Instruction::Store == Opcode); 2459 2460 VectorType *SrcVTy = dyn_cast<VectorType>(SrcTy); 2461 if (!SrcVTy) 2462 // To calculate scalar take the regular cost, without mask 2463 return getMemoryOpCost(Opcode, SrcTy, MaybeAlign(Alignment), AddressSpace); 2464 2465 unsigned NumElem = SrcVTy->getVectorNumElements(); 2466 VectorType *MaskTy = 2467 VectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 2468 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, MaybeAlign(Alignment))) || 2469 (IsStore && !isLegalMaskedStore(SrcVTy, MaybeAlign(Alignment))) || 2470 !isPowerOf2_32(NumElem)) { 2471 // Scalarization 2472 int MaskSplitCost = getScalarizationOverhead(MaskTy, false, true); 2473 int ScalarCompareCost = getCmpSelInstrCost( 2474 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr); 2475 int BranchCost = getCFInstrCost(Instruction::Br); 2476 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 2477 2478 int ValueSplitCost = getScalarizationOverhead(SrcVTy, IsLoad, IsStore); 2479 int MemopCost = 2480 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2481 MaybeAlign(Alignment), AddressSpace); 2482 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 2483 } 2484 2485 // Legalize the type. 2486 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 2487 auto VT = TLI->getValueType(DL, SrcVTy); 2488 int Cost = 0; 2489 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 2490 LT.second.getVectorNumElements() == NumElem) 2491 // Promotion requires expand/truncate for data and a shuffle for mask. 2492 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, 0, nullptr) + 2493 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, 0, nullptr); 2494 2495 else if (LT.second.getVectorNumElements() > NumElem) { 2496 VectorType *NewMaskTy = VectorType::get(MaskTy->getVectorElementType(), 2497 LT.second.getVectorNumElements()); 2498 // Expanding requires fill mask with zeroes 2499 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, 0, MaskTy); 2500 } 2501 2502 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 2503 if (!ST->hasAVX512()) 2504 return Cost + LT.first * (IsLoad ? 2 : 8); 2505 2506 // AVX-512 masked load/store is cheapper 2507 return Cost + LT.first; 2508 } 2509 2510 int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE, 2511 const SCEV *Ptr) { 2512 // Address computations in vectorized code with non-consecutive addresses will 2513 // likely result in more instructions compared to scalar code where the 2514 // computation can more often be merged into the index mode. The resulting 2515 // extra micro-ops can significantly decrease throughput. 2516 const unsigned NumVectorInstToHideOverhead = 10; 2517 2518 // Cost modeling of Strided Access Computation is hidden by the indexing 2519 // modes of X86 regardless of the stride value. We dont believe that there 2520 // is a difference between constant strided access in gerenal and constant 2521 // strided value which is less than or equal to 64. 2522 // Even in the case of (loop invariant) stride whose value is not known at 2523 // compile time, the address computation will not incur more than one extra 2524 // ADD instruction. 2525 if (Ty->isVectorTy() && SE) { 2526 if (!BaseT::isStridedAccess(Ptr)) 2527 return NumVectorInstToHideOverhead; 2528 if (!BaseT::getConstantStrideStep(SE, Ptr)) 2529 return 1; 2530 } 2531 2532 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 2533 } 2534 2535 int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, Type *ValTy, 2536 bool IsPairwise) { 2537 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 2538 // and make it as the cost. 2539 2540 static const CostTblEntry SLMCostTblPairWise[] = { 2541 { ISD::FADD, MVT::v2f64, 3 }, 2542 { ISD::ADD, MVT::v2i64, 5 }, 2543 }; 2544 2545 static const CostTblEntry SSE2CostTblPairWise[] = { 2546 { ISD::FADD, MVT::v2f64, 2 }, 2547 { ISD::FADD, MVT::v4f32, 4 }, 2548 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 2549 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32. 2550 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5". 2551 { ISD::ADD, MVT::v2i16, 3 }, // FIXME: chosen to be less than v4i16 2552 { ISD::ADD, MVT::v4i16, 4 }, // FIXME: chosen to be less than v8i16 2553 { ISD::ADD, MVT::v8i16, 5 }, 2554 { ISD::ADD, MVT::v2i8, 2 }, 2555 { ISD::ADD, MVT::v4i8, 2 }, 2556 { ISD::ADD, MVT::v8i8, 2 }, 2557 { ISD::ADD, MVT::v16i8, 3 }, 2558 }; 2559 2560 static const CostTblEntry AVX1CostTblPairWise[] = { 2561 { ISD::FADD, MVT::v4f64, 5 }, 2562 { ISD::FADD, MVT::v8f32, 7 }, 2563 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 2564 { ISD::ADD, MVT::v4i64, 5 }, // The data reported by the IACA tool is "4.8". 2565 { ISD::ADD, MVT::v8i32, 5 }, 2566 { ISD::ADD, MVT::v16i16, 6 }, 2567 { ISD::ADD, MVT::v32i8, 4 }, 2568 }; 2569 2570 static const CostTblEntry SLMCostTblNoPairWise[] = { 2571 { ISD::FADD, MVT::v2f64, 3 }, 2572 { ISD::ADD, MVT::v2i64, 5 }, 2573 }; 2574 2575 static const CostTblEntry SSE2CostTblNoPairWise[] = { 2576 { ISD::FADD, MVT::v2f64, 2 }, 2577 { ISD::FADD, MVT::v4f32, 4 }, 2578 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 2579 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 2580 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 2581 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 2582 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 2583 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 2584 { ISD::ADD, MVT::v2i8, 2 }, 2585 { ISD::ADD, MVT::v4i8, 2 }, 2586 { ISD::ADD, MVT::v8i8, 2 }, 2587 { ISD::ADD, MVT::v16i8, 3 }, 2588 }; 2589 2590 static const CostTblEntry AVX1CostTblNoPairWise[] = { 2591 { ISD::FADD, MVT::v4f64, 3 }, 2592 { ISD::FADD, MVT::v4f32, 3 }, 2593 { ISD::FADD, MVT::v8f32, 4 }, 2594 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 2595 { ISD::ADD, MVT::v4i64, 3 }, 2596 { ISD::ADD, MVT::v8i32, 5 }, 2597 { ISD::ADD, MVT::v16i16, 5 }, 2598 { ISD::ADD, MVT::v32i8, 4 }, 2599 }; 2600 2601 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2602 assert(ISD && "Invalid opcode"); 2603 2604 // Before legalizing the type, give a chance to look up illegal narrow types 2605 // in the table. 2606 // FIXME: Is there a better way to do this? 2607 EVT VT = TLI->getValueType(DL, ValTy); 2608 if (VT.isSimple()) { 2609 MVT MTy = VT.getSimpleVT(); 2610 if (IsPairwise) { 2611 if (ST->isSLM()) 2612 if (const auto *Entry = CostTableLookup(SLMCostTblPairWise, ISD, MTy)) 2613 return Entry->Cost; 2614 2615 if (ST->hasAVX()) 2616 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy)) 2617 return Entry->Cost; 2618 2619 if (ST->hasSSE2()) 2620 if (const auto *Entry = CostTableLookup(SSE2CostTblPairWise, ISD, MTy)) 2621 return Entry->Cost; 2622 } else { 2623 if (ST->isSLM()) 2624 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 2625 return Entry->Cost; 2626 2627 if (ST->hasAVX()) 2628 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 2629 return Entry->Cost; 2630 2631 if (ST->hasSSE2()) 2632 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 2633 return Entry->Cost; 2634 } 2635 } 2636 2637 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2638 2639 MVT MTy = LT.second; 2640 2641 if (IsPairwise) { 2642 if (ST->isSLM()) 2643 if (const auto *Entry = CostTableLookup(SLMCostTblPairWise, ISD, MTy)) 2644 return LT.first * Entry->Cost; 2645 2646 if (ST->hasAVX()) 2647 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy)) 2648 return LT.first * Entry->Cost; 2649 2650 if (ST->hasSSE2()) 2651 if (const auto *Entry = CostTableLookup(SSE2CostTblPairWise, ISD, MTy)) 2652 return LT.first * Entry->Cost; 2653 } else { 2654 if (ST->isSLM()) 2655 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 2656 return LT.first * Entry->Cost; 2657 2658 if (ST->hasAVX()) 2659 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 2660 return LT.first * Entry->Cost; 2661 2662 if (ST->hasSSE2()) 2663 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 2664 return LT.first * Entry->Cost; 2665 } 2666 2667 // FIXME: These assume a naive kshift+binop lowering, which is probably 2668 // conservative in most cases. 2669 // FIXME: This doesn't cost large types like v128i1 correctly. 2670 static const CostTblEntry AVX512BoolReduction[] = { 2671 { ISD::AND, MVT::v2i1, 3 }, 2672 { ISD::AND, MVT::v4i1, 5 }, 2673 { ISD::AND, MVT::v8i1, 7 }, 2674 { ISD::AND, MVT::v16i1, 9 }, 2675 { ISD::AND, MVT::v32i1, 11 }, 2676 { ISD::AND, MVT::v64i1, 13 }, 2677 { ISD::OR, MVT::v2i1, 3 }, 2678 { ISD::OR, MVT::v4i1, 5 }, 2679 { ISD::OR, MVT::v8i1, 7 }, 2680 { ISD::OR, MVT::v16i1, 9 }, 2681 { ISD::OR, MVT::v32i1, 11 }, 2682 { ISD::OR, MVT::v64i1, 13 }, 2683 }; 2684 2685 static const CostTblEntry AVX2BoolReduction[] = { 2686 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 2687 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 2688 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 2689 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 2690 }; 2691 2692 static const CostTblEntry AVX1BoolReduction[] = { 2693 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 2694 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 2695 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 2696 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 2697 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 2698 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 2699 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 2700 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 2701 }; 2702 2703 static const CostTblEntry SSE2BoolReduction[] = { 2704 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 2705 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 2706 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 2707 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 2708 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 2709 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 2710 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 2711 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 2712 }; 2713 2714 // Handle bool allof/anyof patterns. 2715 if (!IsPairwise && ValTy->getVectorElementType()->isIntegerTy(1)) { 2716 if (ST->hasAVX512()) 2717 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 2718 return LT.first * Entry->Cost; 2719 if (ST->hasAVX2()) 2720 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 2721 return LT.first * Entry->Cost; 2722 if (ST->hasAVX()) 2723 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 2724 return LT.first * Entry->Cost; 2725 if (ST->hasSSE2()) 2726 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 2727 return LT.first * Entry->Cost; 2728 } 2729 2730 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise); 2731 } 2732 2733 int X86TTIImpl::getMinMaxReductionCost(Type *ValTy, Type *CondTy, 2734 bool IsPairwise, bool IsUnsigned) { 2735 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2736 2737 MVT MTy = LT.second; 2738 2739 int ISD; 2740 if (ValTy->isIntOrIntVectorTy()) { 2741 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 2742 } else { 2743 assert(ValTy->isFPOrFPVectorTy() && 2744 "Expected float point or integer vector type."); 2745 ISD = ISD::FMINNUM; 2746 } 2747 2748 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 2749 // and make it as the cost. 2750 2751 static const CostTblEntry SSE1CostTblPairWise[] = { 2752 {ISD::FMINNUM, MVT::v4f32, 4}, 2753 }; 2754 2755 static const CostTblEntry SSE2CostTblPairWise[] = { 2756 {ISD::FMINNUM, MVT::v2f64, 3}, 2757 {ISD::SMIN, MVT::v2i64, 6}, 2758 {ISD::UMIN, MVT::v2i64, 8}, 2759 {ISD::SMIN, MVT::v4i32, 6}, 2760 {ISD::UMIN, MVT::v4i32, 8}, 2761 {ISD::SMIN, MVT::v8i16, 4}, 2762 {ISD::UMIN, MVT::v8i16, 6}, 2763 {ISD::SMIN, MVT::v16i8, 8}, 2764 {ISD::UMIN, MVT::v16i8, 6}, 2765 }; 2766 2767 static const CostTblEntry SSE41CostTblPairWise[] = { 2768 {ISD::FMINNUM, MVT::v4f32, 2}, 2769 {ISD::SMIN, MVT::v2i64, 9}, 2770 {ISD::UMIN, MVT::v2i64,10}, 2771 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5" 2772 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8" 2773 {ISD::SMIN, MVT::v8i16, 2}, 2774 {ISD::UMIN, MVT::v8i16, 2}, 2775 {ISD::SMIN, MVT::v16i8, 3}, 2776 {ISD::UMIN, MVT::v16i8, 3}, 2777 }; 2778 2779 static const CostTblEntry SSE42CostTblPairWise[] = { 2780 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8" 2781 {ISD::UMIN, MVT::v2i64, 8}, // The data reported by the IACA is "8.6" 2782 }; 2783 2784 static const CostTblEntry AVX1CostTblPairWise[] = { 2785 {ISD::FMINNUM, MVT::v4f32, 1}, 2786 {ISD::FMINNUM, MVT::v4f64, 1}, 2787 {ISD::FMINNUM, MVT::v8f32, 2}, 2788 {ISD::SMIN, MVT::v2i64, 3}, 2789 {ISD::UMIN, MVT::v2i64, 3}, 2790 {ISD::SMIN, MVT::v4i32, 1}, 2791 {ISD::UMIN, MVT::v4i32, 1}, 2792 {ISD::SMIN, MVT::v8i16, 1}, 2793 {ISD::UMIN, MVT::v8i16, 1}, 2794 {ISD::SMIN, MVT::v16i8, 2}, 2795 {ISD::UMIN, MVT::v16i8, 2}, 2796 {ISD::SMIN, MVT::v4i64, 7}, 2797 {ISD::UMIN, MVT::v4i64, 7}, 2798 {ISD::SMIN, MVT::v8i32, 3}, 2799 {ISD::UMIN, MVT::v8i32, 3}, 2800 {ISD::SMIN, MVT::v16i16, 3}, 2801 {ISD::UMIN, MVT::v16i16, 3}, 2802 {ISD::SMIN, MVT::v32i8, 3}, 2803 {ISD::UMIN, MVT::v32i8, 3}, 2804 }; 2805 2806 static const CostTblEntry AVX2CostTblPairWise[] = { 2807 {ISD::SMIN, MVT::v4i64, 2}, 2808 {ISD::UMIN, MVT::v4i64, 2}, 2809 {ISD::SMIN, MVT::v8i32, 1}, 2810 {ISD::UMIN, MVT::v8i32, 1}, 2811 {ISD::SMIN, MVT::v16i16, 1}, 2812 {ISD::UMIN, MVT::v16i16, 1}, 2813 {ISD::SMIN, MVT::v32i8, 2}, 2814 {ISD::UMIN, MVT::v32i8, 2}, 2815 }; 2816 2817 static const CostTblEntry AVX512CostTblPairWise[] = { 2818 {ISD::FMINNUM, MVT::v8f64, 1}, 2819 {ISD::FMINNUM, MVT::v16f32, 2}, 2820 {ISD::SMIN, MVT::v8i64, 2}, 2821 {ISD::UMIN, MVT::v8i64, 2}, 2822 {ISD::SMIN, MVT::v16i32, 1}, 2823 {ISD::UMIN, MVT::v16i32, 1}, 2824 }; 2825 2826 static const CostTblEntry SSE1CostTblNoPairWise[] = { 2827 {ISD::FMINNUM, MVT::v4f32, 4}, 2828 }; 2829 2830 static const CostTblEntry SSE2CostTblNoPairWise[] = { 2831 {ISD::FMINNUM, MVT::v2f64, 3}, 2832 {ISD::SMIN, MVT::v2i64, 6}, 2833 {ISD::UMIN, MVT::v2i64, 8}, 2834 {ISD::SMIN, MVT::v4i32, 6}, 2835 {ISD::UMIN, MVT::v4i32, 8}, 2836 {ISD::SMIN, MVT::v8i16, 4}, 2837 {ISD::UMIN, MVT::v8i16, 6}, 2838 {ISD::SMIN, MVT::v16i8, 8}, 2839 {ISD::UMIN, MVT::v16i8, 6}, 2840 }; 2841 2842 static const CostTblEntry SSE41CostTblNoPairWise[] = { 2843 {ISD::FMINNUM, MVT::v4f32, 3}, 2844 {ISD::SMIN, MVT::v2i64, 9}, 2845 {ISD::UMIN, MVT::v2i64,11}, 2846 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5" 2847 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8" 2848 {ISD::SMIN, MVT::v8i16, 1}, // The data reported by the IACA is "1.5" 2849 {ISD::UMIN, MVT::v8i16, 2}, // The data reported by the IACA is "1.8" 2850 {ISD::SMIN, MVT::v16i8, 3}, 2851 {ISD::UMIN, MVT::v16i8, 3}, 2852 }; 2853 2854 static const CostTblEntry SSE42CostTblNoPairWise[] = { 2855 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8" 2856 {ISD::UMIN, MVT::v2i64, 9}, // The data reported by the IACA is "8.6" 2857 }; 2858 2859 static const CostTblEntry AVX1CostTblNoPairWise[] = { 2860 {ISD::FMINNUM, MVT::v4f32, 1}, 2861 {ISD::FMINNUM, MVT::v4f64, 1}, 2862 {ISD::FMINNUM, MVT::v8f32, 1}, 2863 {ISD::SMIN, MVT::v2i64, 3}, 2864 {ISD::UMIN, MVT::v2i64, 3}, 2865 {ISD::SMIN, MVT::v4i32, 1}, 2866 {ISD::UMIN, MVT::v4i32, 1}, 2867 {ISD::SMIN, MVT::v8i16, 1}, 2868 {ISD::UMIN, MVT::v8i16, 1}, 2869 {ISD::SMIN, MVT::v16i8, 2}, 2870 {ISD::UMIN, MVT::v16i8, 2}, 2871 {ISD::SMIN, MVT::v4i64, 7}, 2872 {ISD::UMIN, MVT::v4i64, 7}, 2873 {ISD::SMIN, MVT::v8i32, 2}, 2874 {ISD::UMIN, MVT::v8i32, 2}, 2875 {ISD::SMIN, MVT::v16i16, 2}, 2876 {ISD::UMIN, MVT::v16i16, 2}, 2877 {ISD::SMIN, MVT::v32i8, 2}, 2878 {ISD::UMIN, MVT::v32i8, 2}, 2879 }; 2880 2881 static const CostTblEntry AVX2CostTblNoPairWise[] = { 2882 {ISD::SMIN, MVT::v4i64, 1}, 2883 {ISD::UMIN, MVT::v4i64, 1}, 2884 {ISD::SMIN, MVT::v8i32, 1}, 2885 {ISD::UMIN, MVT::v8i32, 1}, 2886 {ISD::SMIN, MVT::v16i16, 1}, 2887 {ISD::UMIN, MVT::v16i16, 1}, 2888 {ISD::SMIN, MVT::v32i8, 1}, 2889 {ISD::UMIN, MVT::v32i8, 1}, 2890 }; 2891 2892 static const CostTblEntry AVX512CostTblNoPairWise[] = { 2893 {ISD::FMINNUM, MVT::v8f64, 1}, 2894 {ISD::FMINNUM, MVT::v16f32, 2}, 2895 {ISD::SMIN, MVT::v8i64, 1}, 2896 {ISD::UMIN, MVT::v8i64, 1}, 2897 {ISD::SMIN, MVT::v16i32, 1}, 2898 {ISD::UMIN, MVT::v16i32, 1}, 2899 }; 2900 2901 if (IsPairwise) { 2902 if (ST->hasAVX512()) 2903 if (const auto *Entry = CostTableLookup(AVX512CostTblPairWise, ISD, MTy)) 2904 return LT.first * Entry->Cost; 2905 2906 if (ST->hasAVX2()) 2907 if (const auto *Entry = CostTableLookup(AVX2CostTblPairWise, ISD, MTy)) 2908 return LT.first * Entry->Cost; 2909 2910 if (ST->hasAVX()) 2911 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy)) 2912 return LT.first * Entry->Cost; 2913 2914 if (ST->hasSSE42()) 2915 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy)) 2916 return LT.first * Entry->Cost; 2917 2918 if (ST->hasSSE41()) 2919 if (const auto *Entry = CostTableLookup(SSE41CostTblPairWise, ISD, MTy)) 2920 return LT.first * Entry->Cost; 2921 2922 if (ST->hasSSE2()) 2923 if (const auto *Entry = CostTableLookup(SSE2CostTblPairWise, ISD, MTy)) 2924 return LT.first * Entry->Cost; 2925 2926 if (ST->hasSSE1()) 2927 if (const auto *Entry = CostTableLookup(SSE1CostTblPairWise, ISD, MTy)) 2928 return LT.first * Entry->Cost; 2929 } else { 2930 if (ST->hasAVX512()) 2931 if (const auto *Entry = 2932 CostTableLookup(AVX512CostTblNoPairWise, ISD, MTy)) 2933 return LT.first * Entry->Cost; 2934 2935 if (ST->hasAVX2()) 2936 if (const auto *Entry = CostTableLookup(AVX2CostTblNoPairWise, ISD, MTy)) 2937 return LT.first * Entry->Cost; 2938 2939 if (ST->hasAVX()) 2940 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 2941 return LT.first * Entry->Cost; 2942 2943 if (ST->hasSSE42()) 2944 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy)) 2945 return LT.first * Entry->Cost; 2946 2947 if (ST->hasSSE41()) 2948 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 2949 return LT.first * Entry->Cost; 2950 2951 if (ST->hasSSE2()) 2952 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 2953 return LT.first * Entry->Cost; 2954 2955 if (ST->hasSSE1()) 2956 if (const auto *Entry = CostTableLookup(SSE1CostTblNoPairWise, ISD, MTy)) 2957 return LT.first * Entry->Cost; 2958 } 2959 2960 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned); 2961 } 2962 2963 /// Calculate the cost of materializing a 64-bit value. This helper 2964 /// method might only calculate a fraction of a larger immediate. Therefore it 2965 /// is valid to return a cost of ZERO. 2966 int X86TTIImpl::getIntImmCost(int64_t Val) { 2967 if (Val == 0) 2968 return TTI::TCC_Free; 2969 2970 if (isInt<32>(Val)) 2971 return TTI::TCC_Basic; 2972 2973 return 2 * TTI::TCC_Basic; 2974 } 2975 2976 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { 2977 assert(Ty->isIntegerTy()); 2978 2979 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 2980 if (BitSize == 0) 2981 return ~0U; 2982 2983 // Never hoist constants larger than 128bit, because this might lead to 2984 // incorrect code generation or assertions in codegen. 2985 // Fixme: Create a cost model for types larger than i128 once the codegen 2986 // issues have been fixed. 2987 if (BitSize > 128) 2988 return TTI::TCC_Free; 2989 2990 if (Imm == 0) 2991 return TTI::TCC_Free; 2992 2993 // Sign-extend all constants to a multiple of 64-bit. 2994 APInt ImmVal = Imm; 2995 if (BitSize % 64 != 0) 2996 ImmVal = Imm.sext(alignTo(BitSize, 64)); 2997 2998 // Split the constant into 64-bit chunks and calculate the cost for each 2999 // chunk. 3000 int Cost = 0; 3001 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 3002 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 3003 int64_t Val = Tmp.getSExtValue(); 3004 Cost += getIntImmCost(Val); 3005 } 3006 // We need at least one instruction to materialize the constant. 3007 return std::max(1, Cost); 3008 } 3009 3010 int X86TTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, 3011 Type *Ty) { 3012 assert(Ty->isIntegerTy()); 3013 3014 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3015 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3016 // here, so that constant hoisting will ignore this constant. 3017 if (BitSize == 0) 3018 return TTI::TCC_Free; 3019 3020 unsigned ImmIdx = ~0U; 3021 switch (Opcode) { 3022 default: 3023 return TTI::TCC_Free; 3024 case Instruction::GetElementPtr: 3025 // Always hoist the base address of a GetElementPtr. This prevents the 3026 // creation of new constants for every base constant that gets constant 3027 // folded with the offset. 3028 if (Idx == 0) 3029 return 2 * TTI::TCC_Basic; 3030 return TTI::TCC_Free; 3031 case Instruction::Store: 3032 ImmIdx = 0; 3033 break; 3034 case Instruction::ICmp: 3035 // This is an imperfect hack to prevent constant hoisting of 3036 // compares that might be trying to check if a 64-bit value fits in 3037 // 32-bits. The backend can optimize these cases using a right shift by 32. 3038 // Ideally we would check the compare predicate here. There also other 3039 // similar immediates the backend can use shifts for. 3040 if (Idx == 1 && Imm.getBitWidth() == 64) { 3041 uint64_t ImmVal = Imm.getZExtValue(); 3042 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 3043 return TTI::TCC_Free; 3044 } 3045 ImmIdx = 1; 3046 break; 3047 case Instruction::And: 3048 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 3049 // by using a 32-bit operation with implicit zero extension. Detect such 3050 // immediates here as the normal path expects bit 31 to be sign extended. 3051 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 3052 return TTI::TCC_Free; 3053 ImmIdx = 1; 3054 break; 3055 case Instruction::Add: 3056 case Instruction::Sub: 3057 // For add/sub, we can use the opposite instruction for INT32_MIN. 3058 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 3059 return TTI::TCC_Free; 3060 ImmIdx = 1; 3061 break; 3062 case Instruction::UDiv: 3063 case Instruction::SDiv: 3064 case Instruction::URem: 3065 case Instruction::SRem: 3066 // Division by constant is typically expanded later into a different 3067 // instruction sequence. This completely changes the constants. 3068 // Report them as "free" to stop ConstantHoist from marking them as opaque. 3069 return TTI::TCC_Free; 3070 case Instruction::Mul: 3071 case Instruction::Or: 3072 case Instruction::Xor: 3073 ImmIdx = 1; 3074 break; 3075 // Always return TCC_Free for the shift value of a shift instruction. 3076 case Instruction::Shl: 3077 case Instruction::LShr: 3078 case Instruction::AShr: 3079 if (Idx == 1) 3080 return TTI::TCC_Free; 3081 break; 3082 case Instruction::Trunc: 3083 case Instruction::ZExt: 3084 case Instruction::SExt: 3085 case Instruction::IntToPtr: 3086 case Instruction::PtrToInt: 3087 case Instruction::BitCast: 3088 case Instruction::PHI: 3089 case Instruction::Call: 3090 case Instruction::Select: 3091 case Instruction::Ret: 3092 case Instruction::Load: 3093 break; 3094 } 3095 3096 if (Idx == ImmIdx) { 3097 int NumConstants = divideCeil(BitSize, 64); 3098 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty); 3099 return (Cost <= NumConstants * TTI::TCC_Basic) 3100 ? static_cast<int>(TTI::TCC_Free) 3101 : Cost; 3102 } 3103 3104 return X86TTIImpl::getIntImmCost(Imm, Ty); 3105 } 3106 3107 int X86TTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, 3108 Type *Ty) { 3109 assert(Ty->isIntegerTy()); 3110 3111 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3112 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3113 // here, so that constant hoisting will ignore this constant. 3114 if (BitSize == 0) 3115 return TTI::TCC_Free; 3116 3117 switch (IID) { 3118 default: 3119 return TTI::TCC_Free; 3120 case Intrinsic::sadd_with_overflow: 3121 case Intrinsic::uadd_with_overflow: 3122 case Intrinsic::ssub_with_overflow: 3123 case Intrinsic::usub_with_overflow: 3124 case Intrinsic::smul_with_overflow: 3125 case Intrinsic::umul_with_overflow: 3126 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 3127 return TTI::TCC_Free; 3128 break; 3129 case Intrinsic::experimental_stackmap: 3130 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 3131 return TTI::TCC_Free; 3132 break; 3133 case Intrinsic::experimental_patchpoint_void: 3134 case Intrinsic::experimental_patchpoint_i64: 3135 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 3136 return TTI::TCC_Free; 3137 break; 3138 } 3139 return X86TTIImpl::getIntImmCost(Imm, Ty); 3140 } 3141 3142 unsigned X86TTIImpl::getUserCost(const User *U, 3143 ArrayRef<const Value *> Operands) { 3144 if (isa<StoreInst>(U)) { 3145 Value *Ptr = U->getOperand(1); 3146 // Store instruction with index and scale costs 2 Uops. 3147 // Check the preceding GEP to identify non-const indices. 3148 if (auto GEP = dyn_cast<GetElementPtrInst>(Ptr)) { 3149 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3150 return TTI::TCC_Basic * 2; 3151 } 3152 return TTI::TCC_Basic; 3153 } 3154 return BaseT::getUserCost(U, Operands); 3155 } 3156 3157 // Return an average cost of Gather / Scatter instruction, maybe improved later 3158 int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, Value *Ptr, 3159 unsigned Alignment, unsigned AddressSpace) { 3160 3161 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 3162 unsigned VF = SrcVTy->getVectorNumElements(); 3163 3164 // Try to reduce index size from 64 bit (default for GEP) 3165 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 3166 // operation will use 16 x 64 indices which do not fit in a zmm and needs 3167 // to split. Also check that the base pointer is the same for all lanes, 3168 // and that there's at most one variable index. 3169 auto getIndexSizeInBits = [](Value *Ptr, const DataLayout& DL) { 3170 unsigned IndexSize = DL.getPointerSizeInBits(); 3171 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 3172 if (IndexSize < 64 || !GEP) 3173 return IndexSize; 3174 3175 unsigned NumOfVarIndices = 0; 3176 Value *Ptrs = GEP->getPointerOperand(); 3177 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 3178 return IndexSize; 3179 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 3180 if (isa<Constant>(GEP->getOperand(i))) 3181 continue; 3182 Type *IndxTy = GEP->getOperand(i)->getType(); 3183 if (IndxTy->isVectorTy()) 3184 IndxTy = IndxTy->getVectorElementType(); 3185 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 3186 !isa<SExtInst>(GEP->getOperand(i))) || 3187 ++NumOfVarIndices > 1) 3188 return IndexSize; // 64 3189 } 3190 return (unsigned)32; 3191 }; 3192 3193 3194 // Trying to reduce IndexSize to 32 bits for vector 16. 3195 // By default the IndexSize is equal to pointer size. 3196 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 3197 ? getIndexSizeInBits(Ptr, DL) 3198 : DL.getPointerSizeInBits(); 3199 3200 Type *IndexVTy = VectorType::get(IntegerType::get(SrcVTy->getContext(), 3201 IndexSize), VF); 3202 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy); 3203 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3204 int SplitFactor = std::max(IdxsLT.first, SrcLT.first); 3205 if (SplitFactor > 1) { 3206 // Handle splitting of vector of pointers 3207 Type *SplitSrcTy = VectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 3208 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 3209 AddressSpace); 3210 } 3211 3212 // The gather / scatter cost is given by Intel architects. It is a rough 3213 // number since we are looking at one instruction in a time. 3214 const int GSOverhead = (Opcode == Instruction::Load) 3215 ? ST->getGatherOverhead() 3216 : ST->getScatterOverhead(); 3217 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3218 MaybeAlign(Alignment), AddressSpace); 3219 } 3220 3221 /// Return the cost of full scalarization of gather / scatter operation. 3222 /// 3223 /// Opcode - Load or Store instruction. 3224 /// SrcVTy - The type of the data vector that should be gathered or scattered. 3225 /// VariableMask - The mask is non-constant at compile time. 3226 /// Alignment - Alignment for one element. 3227 /// AddressSpace - pointer[s] address space. 3228 /// 3229 int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 3230 bool VariableMask, unsigned Alignment, 3231 unsigned AddressSpace) { 3232 unsigned VF = SrcVTy->getVectorNumElements(); 3233 3234 int MaskUnpackCost = 0; 3235 if (VariableMask) { 3236 VectorType *MaskTy = 3237 VectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 3238 MaskUnpackCost = getScalarizationOverhead(MaskTy, false, true); 3239 int ScalarCompareCost = 3240 getCmpSelInstrCost(Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), 3241 nullptr); 3242 int BranchCost = getCFInstrCost(Instruction::Br); 3243 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 3244 } 3245 3246 // The cost of the scalar loads/stores. 3247 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3248 MaybeAlign(Alignment), AddressSpace); 3249 3250 int InsertExtractCost = 0; 3251 if (Opcode == Instruction::Load) 3252 for (unsigned i = 0; i < VF; ++i) 3253 // Add the cost of inserting each scalar load into the vector 3254 InsertExtractCost += 3255 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 3256 else 3257 for (unsigned i = 0; i < VF; ++i) 3258 // Add the cost of extracting each element out of the data vector 3259 InsertExtractCost += 3260 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 3261 3262 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 3263 } 3264 3265 /// Calculate the cost of Gather / Scatter operation 3266 int X86TTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *SrcVTy, 3267 Value *Ptr, bool VariableMask, 3268 unsigned Alignment) { 3269 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 3270 unsigned VF = SrcVTy->getVectorNumElements(); 3271 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 3272 if (!PtrTy && Ptr->getType()->isVectorTy()) 3273 PtrTy = dyn_cast<PointerType>(Ptr->getType()->getVectorElementType()); 3274 assert(PtrTy && "Unexpected type for Ptr argument"); 3275 unsigned AddressSpace = PtrTy->getAddressSpace(); 3276 3277 bool Scalarize = false; 3278 if ((Opcode == Instruction::Load && !isLegalMaskedGather(SrcVTy)) || 3279 (Opcode == Instruction::Store && !isLegalMaskedScatter(SrcVTy))) 3280 Scalarize = true; 3281 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 3282 // Vector-4 of gather/scatter instruction does not exist on KNL. 3283 // We can extend it to 8 elements, but zeroing upper bits of 3284 // the mask vector will add more instructions. Right now we give the scalar 3285 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 3286 // is better in the VariableMask case. 3287 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 3288 Scalarize = true; 3289 3290 if (Scalarize) 3291 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 3292 AddressSpace); 3293 3294 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 3295 } 3296 3297 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 3298 TargetTransformInfo::LSRCost &C2) { 3299 // X86 specific here are "instruction number 1st priority". 3300 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 3301 C1.NumIVMuls, C1.NumBaseAdds, 3302 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 3303 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 3304 C2.NumIVMuls, C2.NumBaseAdds, 3305 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 3306 } 3307 3308 bool X86TTIImpl::canMacroFuseCmp() { 3309 return ST->hasMacroFusion() || ST->hasBranchFusion(); 3310 } 3311 3312 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, MaybeAlign Alignment) { 3313 if (!ST->hasAVX()) 3314 return false; 3315 3316 // The backend can't handle a single element vector. 3317 if (isa<VectorType>(DataTy) && DataTy->getVectorNumElements() == 1) 3318 return false; 3319 Type *ScalarTy = DataTy->getScalarType(); 3320 3321 if (ScalarTy->isPointerTy()) 3322 return true; 3323 3324 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 3325 return true; 3326 3327 if (!ScalarTy->isIntegerTy()) 3328 return false; 3329 3330 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 3331 return IntWidth == 32 || IntWidth == 64 || 3332 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 3333 } 3334 3335 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, MaybeAlign Alignment) { 3336 return isLegalMaskedLoad(DataType, Alignment); 3337 } 3338 3339 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 3340 unsigned DataSize = DL.getTypeStoreSize(DataType); 3341 // The only supported nontemporal loads are for aligned vectors of 16 or 32 3342 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 3343 // (the equivalent stores only require AVX). 3344 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 3345 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 3346 3347 return false; 3348 } 3349 3350 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 3351 unsigned DataSize = DL.getTypeStoreSize(DataType); 3352 3353 // SSE4A supports nontemporal stores of float and double at arbitrary 3354 // alignment. 3355 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 3356 return true; 3357 3358 // Besides the SSE4A subtarget exception above, only aligned stores are 3359 // available nontemporaly on any other subtarget. And only stores with a size 3360 // of 4..32 bytes (powers of 2, only) are permitted. 3361 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 3362 !isPowerOf2_32(DataSize)) 3363 return false; 3364 3365 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 3366 // loads require AVX2). 3367 if (DataSize == 32) 3368 return ST->hasAVX(); 3369 else if (DataSize == 16) 3370 return ST->hasSSE1(); 3371 return true; 3372 } 3373 3374 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 3375 if (!isa<VectorType>(DataTy)) 3376 return false; 3377 3378 if (!ST->hasAVX512()) 3379 return false; 3380 3381 // The backend can't handle a single element vector. 3382 if (DataTy->getVectorNumElements() == 1) 3383 return false; 3384 3385 Type *ScalarTy = DataTy->getVectorElementType(); 3386 3387 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 3388 return true; 3389 3390 if (!ScalarTy->isIntegerTy()) 3391 return false; 3392 3393 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 3394 return IntWidth == 32 || IntWidth == 64 || 3395 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 3396 } 3397 3398 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 3399 return isLegalMaskedExpandLoad(DataTy); 3400 } 3401 3402 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy) { 3403 // Some CPUs have better gather performance than others. 3404 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 3405 // enable gather with a -march. 3406 if (!(ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()))) 3407 return false; 3408 3409 // This function is called now in two cases: from the Loop Vectorizer 3410 // and from the Scalarizer. 3411 // When the Loop Vectorizer asks about legality of the feature, 3412 // the vectorization factor is not calculated yet. The Loop Vectorizer 3413 // sends a scalar type and the decision is based on the width of the 3414 // scalar element. 3415 // Later on, the cost model will estimate usage this intrinsic based on 3416 // the vector type. 3417 // The Scalarizer asks again about legality. It sends a vector type. 3418 // In this case we can reject non-power-of-2 vectors. 3419 // We also reject single element vectors as the type legalizer can't 3420 // scalarize it. 3421 if (isa<VectorType>(DataTy)) { 3422 unsigned NumElts = DataTy->getVectorNumElements(); 3423 if (NumElts == 1 || !isPowerOf2_32(NumElts)) 3424 return false; 3425 } 3426 Type *ScalarTy = DataTy->getScalarType(); 3427 if (ScalarTy->isPointerTy()) 3428 return true; 3429 3430 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 3431 return true; 3432 3433 if (!ScalarTy->isIntegerTy()) 3434 return false; 3435 3436 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 3437 return IntWidth == 32 || IntWidth == 64; 3438 } 3439 3440 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType) { 3441 // AVX2 doesn't support scatter 3442 if (!ST->hasAVX512()) 3443 return false; 3444 return isLegalMaskedGather(DataType); 3445 } 3446 3447 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 3448 EVT VT = TLI->getValueType(DL, DataType); 3449 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 3450 } 3451 3452 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 3453 return false; 3454 } 3455 3456 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 3457 const Function *Callee) const { 3458 const TargetMachine &TM = getTLI()->getTargetMachine(); 3459 3460 // Work this as a subsetting of subtarget features. 3461 const FeatureBitset &CallerBits = 3462 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 3463 const FeatureBitset &CalleeBits = 3464 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 3465 3466 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 3467 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 3468 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 3469 } 3470 3471 bool X86TTIImpl::areFunctionArgsABICompatible( 3472 const Function *Caller, const Function *Callee, 3473 SmallPtrSetImpl<Argument *> &Args) const { 3474 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args)) 3475 return false; 3476 3477 // If we get here, we know the target features match. If one function 3478 // considers 512-bit vectors legal and the other does not, consider them 3479 // incompatible. 3480 // FIXME Look at the arguments and only consider 512 bit or larger vectors? 3481 const TargetMachine &TM = getTLI()->getTargetMachine(); 3482 3483 return TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 3484 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs(); 3485 } 3486 3487 X86TTIImpl::TTI::MemCmpExpansionOptions 3488 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 3489 TTI::MemCmpExpansionOptions Options; 3490 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 3491 Options.NumLoadsPerBlock = 2; 3492 if (IsZeroCmp) { 3493 // Only enable vector loads for equality comparison. Right now the vector 3494 // version is not as fast for three way compare (see #33329). 3495 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 3496 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 3497 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 3498 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 3499 // All GPR and vector loads can be unaligned. 3500 Options.AllowOverlappingLoads = true; 3501 } 3502 if (ST->is64Bit()) { 3503 Options.LoadSizes.push_back(8); 3504 } 3505 Options.LoadSizes.push_back(4); 3506 Options.LoadSizes.push_back(2); 3507 Options.LoadSizes.push_back(1); 3508 return Options; 3509 } 3510 3511 bool X86TTIImpl::enableInterleavedAccessVectorization() { 3512 // TODO: We expect this to be beneficial regardless of arch, 3513 // but there are currently some unexplained performance artifacts on Atom. 3514 // As a temporary solution, disable on Atom. 3515 return !(ST->isAtom()); 3516 } 3517 3518 // Get estimation for interleaved load/store operations for AVX2. 3519 // \p Factor is the interleaved-access factor (stride) - number of 3520 // (interleaved) elements in the group. 3521 // \p Indices contains the indices for a strided load: when the 3522 // interleaved load has gaps they indicate which elements are used. 3523 // If Indices is empty (or if the number of indices is equal to the size 3524 // of the interleaved-access as given in \p Factor) the access has no gaps. 3525 // 3526 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 3527 // computing the cost using a generic formula as a function of generic 3528 // shuffles. We therefore use a lookup table instead, filled according to 3529 // the instruction sequences that codegen currently generates. 3530 int X86TTIImpl::getInterleavedMemoryOpCostAVX2(unsigned Opcode, Type *VecTy, 3531 unsigned Factor, 3532 ArrayRef<unsigned> Indices, 3533 unsigned Alignment, 3534 unsigned AddressSpace, 3535 bool UseMaskForCond, 3536 bool UseMaskForGaps) { 3537 3538 if (UseMaskForCond || UseMaskForGaps) 3539 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3540 Alignment, AddressSpace, 3541 UseMaskForCond, UseMaskForGaps); 3542 3543 // We currently Support only fully-interleaved groups, with no gaps. 3544 // TODO: Support also strided loads (interleaved-groups with gaps). 3545 if (Indices.size() && Indices.size() != Factor) 3546 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3547 Alignment, AddressSpace); 3548 3549 // VecTy for interleave memop is <VF*Factor x Elt>. 3550 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 3551 // VecTy = <12 x i32>. 3552 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 3553 3554 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 3555 // the VF=2, while v2i128 is an unsupported MVT vector type 3556 // (see MachineValueType.h::getVectorVT()). 3557 if (!LegalVT.isVector()) 3558 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3559 Alignment, AddressSpace); 3560 3561 unsigned VF = VecTy->getVectorNumElements() / Factor; 3562 Type *ScalarTy = VecTy->getVectorElementType(); 3563 3564 // Calculate the number of memory operations (NumOfMemOps), required 3565 // for load/store the VecTy. 3566 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 3567 unsigned LegalVTSize = LegalVT.getStoreSize(); 3568 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 3569 3570 // Get the cost of one memory operation. 3571 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(), 3572 LegalVT.getVectorNumElements()); 3573 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 3574 MaybeAlign(Alignment), AddressSpace); 3575 3576 VectorType *VT = VectorType::get(ScalarTy, VF); 3577 EVT ETy = TLI->getValueType(DL, VT); 3578 if (!ETy.isSimple()) 3579 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3580 Alignment, AddressSpace); 3581 3582 // TODO: Complete for other data-types and strides. 3583 // Each combination of Stride, ElementTy and VF results in a different 3584 // sequence; The cost tables are therefore accessed with: 3585 // Factor (stride) and VectorType=VFxElemType. 3586 // The Cost accounts only for the shuffle sequence; 3587 // The cost of the loads/stores is accounted for separately. 3588 // 3589 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 3590 { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64 3591 { 2, MVT::v4f64, 6 }, //(load 8f64 and) deinterleave into 2 x 4f64 3592 3593 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8 3594 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8 3595 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8 3596 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8 3597 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8 3598 { 3, MVT::v8f32, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32 3599 3600 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8 3601 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8 3602 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8 3603 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8 3604 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8 3605 3606 { 8, MVT::v8f32, 40 } //(load 64f32 and)deinterleave into 8 x 8f32 3607 }; 3608 3609 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 3610 { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store) 3611 { 2, MVT::v4f64, 6 }, //interleave into 2 x 4f64 into 8f64 (and store) 3612 3613 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store) 3614 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store) 3615 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store) 3616 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store) 3617 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store) 3618 3619 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store) 3620 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store) 3621 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store) 3622 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store) 3623 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store) 3624 }; 3625 3626 if (Opcode == Instruction::Load) { 3627 if (const auto *Entry = 3628 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 3629 return NumOfMemOps * MemOpCost + Entry->Cost; 3630 } else { 3631 assert(Opcode == Instruction::Store && 3632 "Expected Store Instruction at this point"); 3633 if (const auto *Entry = 3634 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 3635 return NumOfMemOps * MemOpCost + Entry->Cost; 3636 } 3637 3638 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3639 Alignment, AddressSpace); 3640 } 3641 3642 // Get estimation for interleaved load/store operations and strided load. 3643 // \p Indices contains indices for strided load. 3644 // \p Factor - the factor of interleaving. 3645 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 3646 int X86TTIImpl::getInterleavedMemoryOpCostAVX512(unsigned Opcode, Type *VecTy, 3647 unsigned Factor, 3648 ArrayRef<unsigned> Indices, 3649 unsigned Alignment, 3650 unsigned AddressSpace, 3651 bool UseMaskForCond, 3652 bool UseMaskForGaps) { 3653 3654 if (UseMaskForCond || UseMaskForGaps) 3655 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3656 Alignment, AddressSpace, 3657 UseMaskForCond, UseMaskForGaps); 3658 3659 // VecTy for interleave memop is <VF*Factor x Elt>. 3660 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 3661 // VecTy = <12 x i32>. 3662 3663 // Calculate the number of memory operations (NumOfMemOps), required 3664 // for load/store the VecTy. 3665 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 3666 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 3667 unsigned LegalVTSize = LegalVT.getStoreSize(); 3668 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 3669 3670 // Get the cost of one memory operation. 3671 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(), 3672 LegalVT.getVectorNumElements()); 3673 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 3674 MaybeAlign(Alignment), AddressSpace); 3675 3676 unsigned VF = VecTy->getVectorNumElements() / Factor; 3677 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 3678 3679 if (Opcode == Instruction::Load) { 3680 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 3681 // contain the cost of the optimized shuffle sequence that the 3682 // X86InterleavedAccess pass will generate. 3683 // The cost of loads and stores are computed separately from the table. 3684 3685 // X86InterleavedAccess support only the following interleaved-access group. 3686 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 3687 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 3688 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 3689 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 3690 }; 3691 3692 if (const auto *Entry = 3693 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 3694 return NumOfMemOps * MemOpCost + Entry->Cost; 3695 //If an entry does not exist, fallback to the default implementation. 3696 3697 // Kind of shuffle depends on number of loaded values. 3698 // If we load the entire data in one register, we can use a 1-src shuffle. 3699 // Otherwise, we'll merge 2 sources in each operation. 3700 TTI::ShuffleKind ShuffleKind = 3701 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 3702 3703 unsigned ShuffleCost = 3704 getShuffleCost(ShuffleKind, SingleMemOpTy, 0, nullptr); 3705 3706 unsigned NumOfLoadsInInterleaveGrp = 3707 Indices.size() ? Indices.size() : Factor; 3708 Type *ResultTy = VectorType::get(VecTy->getVectorElementType(), 3709 VecTy->getVectorNumElements() / Factor); 3710 unsigned NumOfResults = 3711 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 3712 NumOfLoadsInInterleaveGrp; 3713 3714 // About a half of the loads may be folded in shuffles when we have only 3715 // one result. If we have more than one result, we do not fold loads at all. 3716 unsigned NumOfUnfoldedLoads = 3717 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 3718 3719 // Get a number of shuffle operations per result. 3720 unsigned NumOfShufflesPerResult = 3721 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 3722 3723 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 3724 // When we have more than one destination, we need additional instructions 3725 // to keep sources. 3726 unsigned NumOfMoves = 0; 3727 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 3728 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 3729 3730 int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 3731 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 3732 3733 return Cost; 3734 } 3735 3736 // Store. 3737 assert(Opcode == Instruction::Store && 3738 "Expected Store Instruction at this point"); 3739 // X86InterleavedAccess support only the following interleaved-access group. 3740 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 3741 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 3742 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 3743 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 3744 3745 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 3746 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 3747 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 3748 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 3749 }; 3750 3751 if (const auto *Entry = 3752 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 3753 return NumOfMemOps * MemOpCost + Entry->Cost; 3754 //If an entry does not exist, fallback to the default implementation. 3755 3756 // There is no strided stores meanwhile. And store can't be folded in 3757 // shuffle. 3758 unsigned NumOfSources = Factor; // The number of values to be merged. 3759 unsigned ShuffleCost = 3760 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, 0, nullptr); 3761 unsigned NumOfShufflesPerStore = NumOfSources - 1; 3762 3763 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 3764 // We need additional instructions to keep sources. 3765 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 3766 int Cost = NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 3767 NumOfMoves; 3768 return Cost; 3769 } 3770 3771 int X86TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, 3772 unsigned Factor, 3773 ArrayRef<unsigned> Indices, 3774 unsigned Alignment, 3775 unsigned AddressSpace, 3776 bool UseMaskForCond, 3777 bool UseMaskForGaps) { 3778 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 3779 Type *EltTy = VecTy->getVectorElementType(); 3780 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 3781 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 3782 return true; 3783 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 3784 return HasBW; 3785 return false; 3786 }; 3787 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 3788 return getInterleavedMemoryOpCostAVX512(Opcode, VecTy, Factor, Indices, 3789 Alignment, AddressSpace, 3790 UseMaskForCond, UseMaskForGaps); 3791 if (ST->hasAVX2()) 3792 return getInterleavedMemoryOpCostAVX2(Opcode, VecTy, Factor, Indices, 3793 Alignment, AddressSpace, 3794 UseMaskForCond, UseMaskForGaps); 3795 3796 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3797 Alignment, AddressSpace, 3798 UseMaskForCond, UseMaskForGaps); 3799 } 3800