1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// \file 10 /// This file implements a TargetTransformInfo analysis pass specific to the 11 /// X86 target machine. It uses the target's detailed information to provide 12 /// more precise answers to certain TTI queries, while letting the target 13 /// independent and default TTI implementations handle the rest. 14 /// 15 //===----------------------------------------------------------------------===// 16 /// About Cost Model numbers used below it's necessary to say the following: 17 /// the numbers correspond to some "generic" X86 CPU instead of usage of 18 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 19 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 20 /// the lookups below the cost is based on Nehalem as that was the first CPU 21 /// to support that feature level and thus has most likely the worst case cost. 22 /// Some examples of other technologies/CPUs: 23 /// SSE 3 - Pentium4 / Athlon64 24 /// SSE 4.1 - Penryn 25 /// SSE 4.2 - Nehalem 26 /// AVX - Sandy Bridge 27 /// AVX2 - Haswell 28 /// AVX-512 - Xeon Phi / Skylake 29 /// And some examples of instruction target dependent costs (latency) 30 /// divss sqrtss rsqrtss 31 /// AMD K7 11-16 19 3 32 /// Piledriver 9-24 13-15 5 33 /// Jaguar 14 16 2 34 /// Pentium II,III 18 30 2 35 /// Nehalem 7-14 7-18 3 36 /// Haswell 10-13 11 5 37 /// TODO: Develop and implement the target dependent cost model and 38 /// specialize cost numbers for different Cost Model Targets such as throughput, 39 /// code size, latency and uop count. 40 //===----------------------------------------------------------------------===// 41 42 #include "X86TargetTransformInfo.h" 43 #include "llvm/Analysis/TargetTransformInfo.h" 44 #include "llvm/CodeGen/BasicTTIImpl.h" 45 #include "llvm/CodeGen/CostTable.h" 46 #include "llvm/CodeGen/TargetLowering.h" 47 #include "llvm/IR/IntrinsicInst.h" 48 #include "llvm/Support/Debug.h" 49 50 using namespace llvm; 51 52 #define DEBUG_TYPE "x86tti" 53 54 //===----------------------------------------------------------------------===// 55 // 56 // X86 cost model. 57 // 58 //===----------------------------------------------------------------------===// 59 60 TargetTransformInfo::PopcntSupportKind 61 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 62 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 63 // TODO: Currently the __builtin_popcount() implementation using SSE3 64 // instructions is inefficient. Once the problem is fixed, we should 65 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 66 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 67 } 68 69 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 70 TargetTransformInfo::CacheLevel Level) const { 71 switch (Level) { 72 case TargetTransformInfo::CacheLevel::L1D: 73 // - Penryn 74 // - Nehalem 75 // - Westmere 76 // - Sandy Bridge 77 // - Ivy Bridge 78 // - Haswell 79 // - Broadwell 80 // - Skylake 81 // - Kabylake 82 return 32 * 1024; // 32 KByte 83 case TargetTransformInfo::CacheLevel::L2D: 84 // - Penryn 85 // - Nehalem 86 // - Westmere 87 // - Sandy Bridge 88 // - Ivy Bridge 89 // - Haswell 90 // - Broadwell 91 // - Skylake 92 // - Kabylake 93 return 256 * 1024; // 256 KByte 94 } 95 96 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 97 } 98 99 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 100 TargetTransformInfo::CacheLevel Level) const { 101 // - Penryn 102 // - Nehalem 103 // - Westmere 104 // - Sandy Bridge 105 // - Ivy Bridge 106 // - Haswell 107 // - Broadwell 108 // - Skylake 109 // - Kabylake 110 switch (Level) { 111 case TargetTransformInfo::CacheLevel::L1D: 112 LLVM_FALLTHROUGH; 113 case TargetTransformInfo::CacheLevel::L2D: 114 return 8; 115 } 116 117 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 118 } 119 120 unsigned X86TTIImpl::getNumberOfRegisters(bool Vector) { 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const { 133 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 134 if (Vector) { 135 if (ST->hasAVX512() && PreferVectorWidth >= 512) 136 return 512; 137 if (ST->hasAVX() && PreferVectorWidth >= 256) 138 return 256; 139 if (ST->hasSSE1() && PreferVectorWidth >= 128) 140 return 128; 141 return 0; 142 } 143 144 if (ST->is64Bit()) 145 return 64; 146 147 return 32; 148 } 149 150 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 151 return getRegisterBitWidth(true); 152 } 153 154 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 155 // If the loop will not be vectorized, don't interleave the loop. 156 // Let regular unroll to unroll the loop, which saves the overflow 157 // check and memory check cost. 158 if (VF == 1) 159 return 1; 160 161 if (ST->isAtom()) 162 return 1; 163 164 // Sandybridge and Haswell have multiple execution ports and pipelined 165 // vector units. 166 if (ST->hasAVX()) 167 return 4; 168 169 return 2; 170 } 171 172 int X86TTIImpl::getArithmeticInstrCost( 173 unsigned Opcode, Type *Ty, 174 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 175 TTI::OperandValueProperties Opd1PropInfo, 176 TTI::OperandValueProperties Opd2PropInfo, 177 ArrayRef<const Value *> Args) { 178 // Legalize the type. 179 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 180 181 int ISD = TLI->InstructionOpcodeToISD(Opcode); 182 assert(ISD && "Invalid opcode"); 183 184 static const CostTblEntry GLMCostTable[] = { 185 { ISD::FDIV, MVT::f32, 18 }, // divss 186 { ISD::FDIV, MVT::v4f32, 35 }, // divps 187 { ISD::FDIV, MVT::f64, 33 }, // divsd 188 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 189 }; 190 191 if (ST->isGLM()) 192 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 193 LT.second)) 194 return LT.first * Entry->Cost; 195 196 static const CostTblEntry SLMCostTable[] = { 197 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 198 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 199 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. 200 { ISD::FMUL, MVT::f64, 2 }, // mulsd 201 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 202 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 203 { ISD::FDIV, MVT::f32, 17 }, // divss 204 { ISD::FDIV, MVT::v4f32, 39 }, // divps 205 { ISD::FDIV, MVT::f64, 32 }, // divsd 206 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 207 { ISD::FADD, MVT::v2f64, 2 }, // addpd 208 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 209 // v2i64/v4i64 mul is custom lowered as a series of long: 210 // multiplies(3), shifts(3) and adds(2) 211 // slm muldq version throughput is 2 and addq throughput 4 212 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 213 // 3X4 (addq throughput) = 17 214 { ISD::MUL, MVT::v2i64, 17 }, 215 // slm addq\subq throughput is 4 216 { ISD::ADD, MVT::v2i64, 4 }, 217 { ISD::SUB, MVT::v2i64, 4 }, 218 }; 219 220 if (ST->isSLM()) { 221 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 222 // Check if the operands can be shrinked into a smaller datatype. 223 bool Op1Signed = false; 224 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 225 bool Op2Signed = false; 226 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 227 228 bool signedMode = Op1Signed | Op2Signed; 229 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 230 231 if (OpMinSize <= 7) 232 return LT.first * 3; // pmullw/sext 233 if (!signedMode && OpMinSize <= 8) 234 return LT.first * 3; // pmullw/zext 235 if (OpMinSize <= 15) 236 return LT.first * 5; // pmullw/pmulhw/pshuf 237 if (!signedMode && OpMinSize <= 16) 238 return LT.first * 5; // pmullw/pmulhw/pshuf 239 } 240 241 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 242 LT.second)) { 243 return LT.first * Entry->Cost; 244 } 245 } 246 247 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 248 ISD == ISD::UREM) && 249 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 250 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 251 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 252 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 253 // On X86, vector signed division by constants power-of-two are 254 // normally expanded to the sequence SRA + SRL + ADD + SRA. 255 // The OperandValue properties may not be the same as that of the previous 256 // operation; conservatively assume OP_None. 257 int Cost = 258 2 * getArithmeticInstrCost(Instruction::AShr, Ty, Op1Info, Op2Info, 259 TargetTransformInfo::OP_None, 260 TargetTransformInfo::OP_None); 261 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 262 TargetTransformInfo::OP_None, 263 TargetTransformInfo::OP_None); 264 Cost += getArithmeticInstrCost(Instruction::Add, Ty, Op1Info, Op2Info, 265 TargetTransformInfo::OP_None, 266 TargetTransformInfo::OP_None); 267 268 if (ISD == ISD::SREM) { 269 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 270 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info); 271 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, Op1Info, Op2Info); 272 } 273 274 return Cost; 275 } 276 277 // Vector unsigned division/remainder will be simplified to shifts/masks. 278 if (ISD == ISD::UDIV) 279 return getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 280 TargetTransformInfo::OP_None, 281 TargetTransformInfo::OP_None); 282 283 if (ISD == ISD::UREM) 284 return getArithmeticInstrCost(Instruction::And, Ty, Op1Info, Op2Info, 285 TargetTransformInfo::OP_None, 286 TargetTransformInfo::OP_None); 287 } 288 289 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 290 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 291 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 292 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 293 }; 294 295 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 296 ST->hasBWI()) { 297 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 298 LT.second)) 299 return LT.first * Entry->Cost; 300 } 301 302 static const CostTblEntry AVX512UniformConstCostTable[] = { 303 { ISD::SRA, MVT::v2i64, 1 }, 304 { ISD::SRA, MVT::v4i64, 1 }, 305 { ISD::SRA, MVT::v8i64, 1 }, 306 }; 307 308 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 309 ST->hasAVX512()) { 310 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 311 LT.second)) 312 return LT.first * Entry->Cost; 313 } 314 315 static const CostTblEntry AVX2UniformConstCostTable[] = { 316 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 317 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 318 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 319 320 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 321 }; 322 323 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 324 ST->hasAVX2()) { 325 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 326 LT.second)) 327 return LT.first * Entry->Cost; 328 } 329 330 static const CostTblEntry SSE2UniformConstCostTable[] = { 331 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 332 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 333 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 334 335 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 336 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 337 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 338 }; 339 340 // XOP has faster vXi8 shifts. 341 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 342 ST->hasSSE2() && !ST->hasXOP()) { 343 if (const auto *Entry = 344 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 345 return LT.first * Entry->Cost; 346 } 347 348 static const CostTblEntry AVX512BWConstCostTable[] = { 349 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 350 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 351 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 352 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 353 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 354 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 355 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 356 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 357 }; 358 359 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 360 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 361 ST->hasBWI()) { 362 if (const auto *Entry = 363 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 364 return LT.first * Entry->Cost; 365 } 366 367 static const CostTblEntry AVX512ConstCostTable[] = { 368 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 369 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 370 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 371 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 372 }; 373 374 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 375 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 376 ST->hasAVX512()) { 377 if (const auto *Entry = 378 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 379 return LT.first * Entry->Cost; 380 } 381 382 static const CostTblEntry AVX2ConstCostTable[] = { 383 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 384 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 385 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 386 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 387 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 388 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 389 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 390 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 391 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 392 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 393 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 394 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 395 }; 396 397 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 398 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 399 ST->hasAVX2()) { 400 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 401 return LT.first * Entry->Cost; 402 } 403 404 static const CostTblEntry SSE2ConstCostTable[] = { 405 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 406 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 407 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 408 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 409 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 410 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 411 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 412 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 413 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 414 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 415 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 416 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 417 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 418 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 419 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 420 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 421 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 422 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 423 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 424 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 425 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 426 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 427 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 428 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 429 }; 430 431 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 432 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 433 ST->hasSSE2()) { 434 // pmuldq sequence. 435 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 436 return LT.first * 32; 437 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 438 return LT.first * 38; 439 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 440 return LT.first * 15; 441 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 442 return LT.first * 20; 443 444 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 445 return LT.first * Entry->Cost; 446 } 447 448 static const CostTblEntry AVX2UniformCostTable[] = { 449 // Uniform splats are cheaper for the following instructions. 450 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 451 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 452 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 453 }; 454 455 if (ST->hasAVX2() && 456 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 457 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 458 if (const auto *Entry = 459 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 460 return LT.first * Entry->Cost; 461 } 462 463 static const CostTblEntry SSE2UniformCostTable[] = { 464 // Uniform splats are cheaper for the following instructions. 465 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 466 { ISD::SHL, MVT::v4i32, 1 }, // pslld 467 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 468 469 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 470 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 471 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 472 473 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 474 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 475 }; 476 477 if (ST->hasSSE2() && 478 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 479 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 480 if (const auto *Entry = 481 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 482 return LT.first * Entry->Cost; 483 } 484 485 static const CostTblEntry AVX512DQCostTable[] = { 486 { ISD::MUL, MVT::v2i64, 1 }, 487 { ISD::MUL, MVT::v4i64, 1 }, 488 { ISD::MUL, MVT::v8i64, 1 } 489 }; 490 491 // Look for AVX512DQ lowering tricks for custom cases. 492 if (ST->hasDQI()) 493 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 494 return LT.first * Entry->Cost; 495 496 static const CostTblEntry AVX512BWCostTable[] = { 497 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 498 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 499 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 500 501 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 502 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 503 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 504 505 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 506 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 507 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 508 509 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 510 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 511 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 512 513 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence. 514 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence. 515 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence. 516 }; 517 518 // Look for AVX512BW lowering tricks for custom cases. 519 if (ST->hasBWI()) 520 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 521 return LT.first * Entry->Cost; 522 523 static const CostTblEntry AVX512CostTable[] = { 524 { ISD::SHL, MVT::v16i32, 1 }, 525 { ISD::SRL, MVT::v16i32, 1 }, 526 { ISD::SRA, MVT::v16i32, 1 }, 527 528 { ISD::SHL, MVT::v8i64, 1 }, 529 { ISD::SRL, MVT::v8i64, 1 }, 530 531 { ISD::SRA, MVT::v2i64, 1 }, 532 { ISD::SRA, MVT::v4i64, 1 }, 533 { ISD::SRA, MVT::v8i64, 1 }, 534 535 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence. 536 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence. 537 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 538 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 539 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 540 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add 541 542 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 543 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 544 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 545 546 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 547 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 548 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 549 }; 550 551 if (ST->hasAVX512()) 552 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 553 return LT.first * Entry->Cost; 554 555 static const CostTblEntry AVX2ShiftCostTable[] = { 556 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 557 // customize them to detect the cases where shift amount is a scalar one. 558 { ISD::SHL, MVT::v4i32, 1 }, 559 { ISD::SRL, MVT::v4i32, 1 }, 560 { ISD::SRA, MVT::v4i32, 1 }, 561 { ISD::SHL, MVT::v8i32, 1 }, 562 { ISD::SRL, MVT::v8i32, 1 }, 563 { ISD::SRA, MVT::v8i32, 1 }, 564 { ISD::SHL, MVT::v2i64, 1 }, 565 { ISD::SRL, MVT::v2i64, 1 }, 566 { ISD::SHL, MVT::v4i64, 1 }, 567 { ISD::SRL, MVT::v4i64, 1 }, 568 }; 569 570 // Look for AVX2 lowering tricks. 571 if (ST->hasAVX2()) { 572 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 573 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 574 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 575 // On AVX2, a packed v16i16 shift left by a constant build_vector 576 // is lowered into a vector multiply (vpmullw). 577 return getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info, 578 TargetTransformInfo::OP_None, 579 TargetTransformInfo::OP_None); 580 581 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 582 return LT.first * Entry->Cost; 583 } 584 585 static const CostTblEntry XOPShiftCostTable[] = { 586 // 128bit shifts take 1cy, but right shifts require negation beforehand. 587 { ISD::SHL, MVT::v16i8, 1 }, 588 { ISD::SRL, MVT::v16i8, 2 }, 589 { ISD::SRA, MVT::v16i8, 2 }, 590 { ISD::SHL, MVT::v8i16, 1 }, 591 { ISD::SRL, MVT::v8i16, 2 }, 592 { ISD::SRA, MVT::v8i16, 2 }, 593 { ISD::SHL, MVT::v4i32, 1 }, 594 { ISD::SRL, MVT::v4i32, 2 }, 595 { ISD::SRA, MVT::v4i32, 2 }, 596 { ISD::SHL, MVT::v2i64, 1 }, 597 { ISD::SRL, MVT::v2i64, 2 }, 598 { ISD::SRA, MVT::v2i64, 2 }, 599 // 256bit shifts require splitting if AVX2 didn't catch them above. 600 { ISD::SHL, MVT::v32i8, 2+2 }, 601 { ISD::SRL, MVT::v32i8, 4+2 }, 602 { ISD::SRA, MVT::v32i8, 4+2 }, 603 { ISD::SHL, MVT::v16i16, 2+2 }, 604 { ISD::SRL, MVT::v16i16, 4+2 }, 605 { ISD::SRA, MVT::v16i16, 4+2 }, 606 { ISD::SHL, MVT::v8i32, 2+2 }, 607 { ISD::SRL, MVT::v8i32, 4+2 }, 608 { ISD::SRA, MVT::v8i32, 4+2 }, 609 { ISD::SHL, MVT::v4i64, 2+2 }, 610 { ISD::SRL, MVT::v4i64, 4+2 }, 611 { ISD::SRA, MVT::v4i64, 4+2 }, 612 }; 613 614 // Look for XOP lowering tricks. 615 if (ST->hasXOP()) 616 if (const auto *Entry = CostTableLookup(XOPShiftCostTable, ISD, LT.second)) 617 return LT.first * Entry->Cost; 618 619 static const CostTblEntry SSE2UniformShiftCostTable[] = { 620 // Uniform splats are cheaper for the following instructions. 621 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 622 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 623 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 624 625 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 626 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 627 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 628 629 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 630 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 631 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 632 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 633 }; 634 635 if (ST->hasSSE2() && 636 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 637 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 638 639 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 640 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 641 return LT.first * 4; // 2*psrad + shuffle. 642 643 if (const auto *Entry = 644 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 645 return LT.first * Entry->Cost; 646 } 647 648 if (ISD == ISD::SHL && 649 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 650 MVT VT = LT.second; 651 // Vector shift left by non uniform constant can be lowered 652 // into vector multiply. 653 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 654 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 655 ISD = ISD::MUL; 656 } 657 658 static const CostTblEntry AVX2CostTable[] = { 659 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. 660 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 661 662 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. 663 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 664 665 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. 666 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. 667 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. 668 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 669 670 { ISD::SUB, MVT::v32i8, 1 }, // psubb 671 { ISD::ADD, MVT::v32i8, 1 }, // paddb 672 { ISD::SUB, MVT::v16i16, 1 }, // psubw 673 { ISD::ADD, MVT::v16i16, 1 }, // paddw 674 { ISD::SUB, MVT::v8i32, 1 }, // psubd 675 { ISD::ADD, MVT::v8i32, 1 }, // paddd 676 { ISD::SUB, MVT::v4i64, 1 }, // psubq 677 { ISD::ADD, MVT::v4i64, 1 }, // paddq 678 679 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence. 680 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence. 681 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 682 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 683 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add 684 685 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 686 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 687 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 688 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 689 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 690 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 691 692 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 693 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 694 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 695 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 696 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 697 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 698 }; 699 700 // Look for AVX2 lowering tricks for custom cases. 701 if (ST->hasAVX2()) 702 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 703 return LT.first * Entry->Cost; 704 705 static const CostTblEntry AVX1CostTable[] = { 706 // We don't have to scalarize unsupported ops. We can issue two half-sized 707 // operations and we only need to extract the upper YMM half. 708 // Two ops + 1 extract + 1 insert = 4. 709 { ISD::MUL, MVT::v16i16, 4 }, 710 { ISD::MUL, MVT::v8i32, 4 }, 711 { ISD::SUB, MVT::v32i8, 4 }, 712 { ISD::ADD, MVT::v32i8, 4 }, 713 { ISD::SUB, MVT::v16i16, 4 }, 714 { ISD::ADD, MVT::v16i16, 4 }, 715 { ISD::SUB, MVT::v8i32, 4 }, 716 { ISD::ADD, MVT::v8i32, 4 }, 717 { ISD::SUB, MVT::v4i64, 4 }, 718 { ISD::ADD, MVT::v4i64, 4 }, 719 720 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 721 // are lowered as a series of long multiplies(3), shifts(3) and adds(2) 722 // Because we believe v4i64 to be a legal type, we must also include the 723 // extract+insert in the cost table. Therefore, the cost here is 18 724 // instead of 8. 725 { ISD::MUL, MVT::v4i64, 18 }, 726 727 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence. 728 729 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 730 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 731 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 732 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 733 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 734 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 735 }; 736 737 if (ST->hasAVX()) 738 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 739 return LT.first * Entry->Cost; 740 741 static const CostTblEntry SSE42CostTable[] = { 742 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 743 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 744 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 745 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 746 747 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 748 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 749 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 750 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 751 752 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 753 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 754 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 755 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 756 757 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 758 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 759 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 760 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 761 }; 762 763 if (ST->hasSSE42()) 764 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 765 return LT.first * Entry->Cost; 766 767 static const CostTblEntry SSE41CostTable[] = { 768 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 769 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split. 770 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 771 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 772 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 773 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split 774 775 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 776 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split. 777 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 778 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 779 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 780 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split. 781 782 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 783 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split. 784 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 785 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 786 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 787 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split. 788 789 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 790 }; 791 792 if (ST->hasSSE41()) 793 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 794 return LT.first * Entry->Cost; 795 796 static const CostTblEntry SSE2CostTable[] = { 797 // We don't correctly identify costs of casts because they are marked as 798 // custom. 799 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 800 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 801 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 802 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 803 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 804 805 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 806 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 807 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 808 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 809 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 810 811 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 812 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 813 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 814 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 815 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split. 816 817 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence. 818 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 819 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 820 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 821 822 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 823 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 824 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 825 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 826 }; 827 828 if (ST->hasSSE2()) 829 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 830 return LT.first * Entry->Cost; 831 832 static const CostTblEntry SSE1CostTable[] = { 833 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 834 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 835 }; 836 837 if (ST->hasSSE1()) 838 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 839 return LT.first * Entry->Cost; 840 841 // It is not a good idea to vectorize division. We have to scalarize it and 842 // in the process we will often end up having to spilling regular 843 // registers. The overhead of division is going to dominate most kernels 844 // anyways so try hard to prevent vectorization of division - it is 845 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 846 // to hide "20 cycles" for each lane. 847 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 848 ISD == ISD::UDIV || ISD == ISD::UREM)) { 849 int ScalarCost = getArithmeticInstrCost( 850 Opcode, Ty->getScalarType(), Op1Info, Op2Info, 851 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 852 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 853 } 854 855 // Fallback to the default implementation. 856 return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info); 857 } 858 859 int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, 860 Type *SubTp) { 861 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 862 // 64-bit packed integer vectors (v2i32) are promoted to type v2i64. 863 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp); 864 865 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 866 if (Kind == TTI::SK_Transpose) 867 Kind = TTI::SK_PermuteTwoSrc; 868 869 // For Broadcasts we are splatting the first element from the first input 870 // register, so only need to reference that input and all the output 871 // registers are the same. 872 if (Kind == TTI::SK_Broadcast) 873 LT.first = 1; 874 875 // Subvector extractions are free if they start at the beginning of a 876 // vector and cheap if the subvectors are aligned. 877 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 878 int NumElts = LT.second.getVectorNumElements(); 879 if ((Index % NumElts) == 0) 880 return 0; 881 std::pair<int, MVT> SubLT = TLI->getTypeLegalizationCost(DL, SubTp); 882 if (SubLT.second.isVector()) { 883 int NumSubElts = SubLT.second.getVectorNumElements(); 884 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 885 return SubLT.first; 886 } 887 } 888 889 // We are going to permute multiple sources and the result will be in multiple 890 // destinations. Providing an accurate cost only for splits where the element 891 // type remains the same. 892 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 893 MVT LegalVT = LT.second; 894 if (LegalVT.isVector() && 895 LegalVT.getVectorElementType().getSizeInBits() == 896 Tp->getVectorElementType()->getPrimitiveSizeInBits() && 897 LegalVT.getVectorNumElements() < Tp->getVectorNumElements()) { 898 899 unsigned VecTySize = DL.getTypeStoreSize(Tp); 900 unsigned LegalVTSize = LegalVT.getStoreSize(); 901 // Number of source vectors after legalization: 902 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 903 // Number of destination vectors after legalization: 904 unsigned NumOfDests = LT.first; 905 906 Type *SingleOpTy = VectorType::get(Tp->getVectorElementType(), 907 LegalVT.getVectorNumElements()); 908 909 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 910 return NumOfShuffles * 911 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 0, nullptr); 912 } 913 914 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 915 } 916 917 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 918 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 919 // We assume that source and destination have the same vector type. 920 int NumOfDests = LT.first; 921 int NumOfShufflesPerDest = LT.first * 2 - 1; 922 LT.first = NumOfDests * NumOfShufflesPerDest; 923 } 924 925 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 926 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 927 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 928 929 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 930 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 931 932 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 1}, // vpermt2b 933 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 1}, // vpermt2b 934 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1} // vpermt2b 935 }; 936 937 if (ST->hasVBMI()) 938 if (const auto *Entry = 939 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 940 return LT.first * Entry->Cost; 941 942 static const CostTblEntry AVX512BWShuffleTbl[] = { 943 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 944 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 945 946 {TTI::SK_Reverse, MVT::v32i16, 1}, // vpermw 947 {TTI::SK_Reverse, MVT::v16i16, 1}, // vpermw 948 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 949 950 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 1}, // vpermw 951 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 1}, // vpermw 952 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // vpermw 953 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 954 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 3}, // vpermw + zext/trunc 955 956 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 1}, // vpermt2w 957 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 1}, // vpermt2w 958 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpermt2w 959 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 3}, // zext + vpermt2w + trunc 960 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 961 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3} // zext + vpermt2w + trunc 962 }; 963 964 if (ST->hasBWI()) 965 if (const auto *Entry = 966 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 967 return LT.first * Entry->Cost; 968 969 static const CostTblEntry AVX512ShuffleTbl[] = { 970 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 971 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 972 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 973 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 974 975 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 976 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 977 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 978 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 979 980 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 981 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 982 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 983 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 984 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 985 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 986 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 987 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 988 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 989 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 990 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 991 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 992 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 993 994 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 995 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 996 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 997 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 998 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 999 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1000 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1001 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1002 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1003 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1004 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1005 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1} // vpermt2d 1006 }; 1007 1008 if (ST->hasAVX512()) 1009 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1010 return LT.first * Entry->Cost; 1011 1012 static const CostTblEntry AVX2ShuffleTbl[] = { 1013 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1014 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1015 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1016 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1017 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1018 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1019 1020 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1021 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1022 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1023 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1024 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1025 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1026 1027 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1028 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1029 1030 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1031 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1032 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1033 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1034 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1035 // + vpblendvb 1036 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1037 // + vpblendvb 1038 1039 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1040 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1041 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1042 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1043 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1044 // + vpblendvb 1045 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1046 // + vpblendvb 1047 }; 1048 1049 if (ST->hasAVX2()) 1050 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1051 return LT.first * Entry->Cost; 1052 1053 static const CostTblEntry XOPShuffleTbl[] = { 1054 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1055 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1056 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1057 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1058 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1059 // + vinsertf128 1060 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1061 // + vinsertf128 1062 1063 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1064 // + vinsertf128 1065 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1066 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1067 // + vinsertf128 1068 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1069 }; 1070 1071 if (ST->hasXOP()) 1072 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1073 return LT.first * Entry->Cost; 1074 1075 static const CostTblEntry AVX1ShuffleTbl[] = { 1076 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1077 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1078 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1079 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1080 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1081 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1082 1083 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1084 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1085 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1086 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1087 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1088 // + vinsertf128 1089 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1090 // + vinsertf128 1091 1092 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1093 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1094 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1095 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1096 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1097 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1098 1099 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1100 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1101 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1102 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1103 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1104 // + 2*por + vinsertf128 1105 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1106 // + 2*por + vinsertf128 1107 1108 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1109 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1110 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1111 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1112 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1113 // + 4*por + vinsertf128 1114 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1115 // + 4*por + vinsertf128 1116 }; 1117 1118 if (ST->hasAVX()) 1119 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1120 return LT.first * Entry->Cost; 1121 1122 static const CostTblEntry SSE41ShuffleTbl[] = { 1123 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1124 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1125 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1126 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1127 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1128 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1129 }; 1130 1131 if (ST->hasSSE41()) 1132 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1133 return LT.first * Entry->Cost; 1134 1135 static const CostTblEntry SSSE3ShuffleTbl[] = { 1136 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1137 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1138 1139 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1140 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1141 1142 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1143 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1144 1145 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1146 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1147 1148 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1149 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1150 }; 1151 1152 if (ST->hasSSSE3()) 1153 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1154 return LT.first * Entry->Cost; 1155 1156 static const CostTblEntry SSE2ShuffleTbl[] = { 1157 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1158 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1159 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1160 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1161 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1162 1163 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1164 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1165 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1166 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1167 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1168 // + 2*pshufd + 2*unpck + packus 1169 1170 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1171 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1172 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1173 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1174 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1175 1176 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1177 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1178 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1179 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1180 // + pshufd/unpck 1181 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1182 // + 2*pshufd + 2*unpck + 2*packus 1183 1184 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1185 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1186 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1187 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1188 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1189 }; 1190 1191 if (ST->hasSSE2()) 1192 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1193 return LT.first * Entry->Cost; 1194 1195 static const CostTblEntry SSE1ShuffleTbl[] = { 1196 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1197 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1198 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1199 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1200 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1201 }; 1202 1203 if (ST->hasSSE1()) 1204 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1205 return LT.first * Entry->Cost; 1206 1207 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 1208 } 1209 1210 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 1211 const Instruction *I) { 1212 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1213 assert(ISD && "Invalid opcode"); 1214 1215 // FIXME: Need a better design of the cost table to handle non-simple types of 1216 // potential massive combinations (elem_num x src_type x dst_type). 1217 1218 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1219 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1220 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1221 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1222 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1223 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1224 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1225 1226 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1227 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1228 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1229 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1230 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1231 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1232 1233 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1234 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1235 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1236 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1237 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1238 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1239 1240 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1241 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1242 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1243 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1244 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1245 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1246 }; 1247 1248 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1249 // 256-bit wide vectors. 1250 1251 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1252 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1253 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1254 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1255 1256 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 }, 1257 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 }, 1258 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 }, 1259 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 1260 1261 // v16i1 -> v16i32 - load + broadcast 1262 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1263 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1264 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1265 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1266 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1267 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1268 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1269 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1270 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1271 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1272 1273 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1274 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1275 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1276 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1277 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1278 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1279 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1280 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1281 1282 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1283 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1284 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1285 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1286 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1287 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1288 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1289 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1290 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1291 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1292 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1293 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1294 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1295 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1296 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1297 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1298 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1299 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1300 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1301 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1302 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1303 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1304 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1305 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1306 1307 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1308 1309 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1310 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1311 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1312 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1313 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 2 }, 1314 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 2 }, 1315 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1316 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 2 }, 1317 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 2 }, 1318 }; 1319 1320 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1321 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1322 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1323 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1324 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1325 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 1326 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 1327 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 1328 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 1329 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1330 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1331 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1332 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1333 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1334 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1335 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1336 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1337 1338 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 1339 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 1340 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1341 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 1342 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1343 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 }, 1344 1345 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1346 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1347 1348 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1349 }; 1350 1351 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1352 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1353 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1354 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1355 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1356 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 }, 1357 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1358 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 7 }, 1359 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1360 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1361 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1362 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 }, 1363 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1364 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1365 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1366 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1367 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1368 1369 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 1370 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1371 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1372 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1373 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 1374 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 }, 1375 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 }, 1376 1377 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1378 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1379 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1380 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1381 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1382 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1383 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1384 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1385 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1386 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1387 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1388 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1389 1390 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1391 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1392 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1393 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1394 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1395 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1396 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1397 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1398 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1399 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 }, 1400 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 1401 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1402 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 1403 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1404 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1405 // The generic code to compute the scalar overhead is currently broken. 1406 // Workaround this limitation by estimating the scalarization overhead 1407 // here. We have roughly 10 instructions per scalar element. 1408 // Multiply that by the vector width. 1409 // FIXME: remove that when PR19268 is fixed. 1410 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1411 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1412 1413 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 }, 1414 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 }, 1415 // This node is expanded into scalarized operations but BasicTTI is overly 1416 // optimistic estimating its cost. It computes 3 per element (one 1417 // vector-extract, one scalar conversion and one vector-insert). The 1418 // problem is that the inserts form a read-modify-write chain so latency 1419 // should be factored in too. Inflating the cost per element by 1. 1420 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, 1421 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 1422 1423 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 1424 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 1425 }; 1426 1427 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 1428 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1429 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1430 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1431 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1432 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1433 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1434 1435 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1436 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 }, 1437 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1438 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1439 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1440 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1441 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1442 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1443 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1444 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1445 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1446 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1447 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1448 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1449 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1450 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1451 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1452 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1453 1454 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, 1455 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 1456 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 1457 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 1458 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 1459 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 1460 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 1461 1462 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 1463 }; 1464 1465 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 1466 // These are somewhat magic numbers justified by looking at the output of 1467 // Intel's IACA, running some kernels and making sure when we take 1468 // legalization into account the throughput will be overestimated. 1469 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1470 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1471 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1472 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1473 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1474 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1475 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1476 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 1477 1478 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1479 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1480 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1481 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1482 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1483 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, 1484 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 }, 1485 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1486 1487 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 3 }, 1488 1489 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 }, 1490 1491 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1492 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 1493 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 1494 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 1495 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1496 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 1497 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1498 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 1499 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1500 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1501 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1502 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1503 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 1504 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 1505 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1506 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 1507 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1508 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 1509 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1510 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1511 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 1512 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 1513 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1514 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 1515 1516 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 4 }, 1517 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, 1518 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 1519 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 1520 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 1521 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1522 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 1523 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1524 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 1525 }; 1526 1527 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 1528 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst); 1529 1530 if (ST->hasSSE2() && !ST->hasAVX()) { 1531 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1532 LTDest.second, LTSrc.second)) 1533 return LTSrc.first * Entry->Cost; 1534 } 1535 1536 EVT SrcTy = TLI->getValueType(DL, Src); 1537 EVT DstTy = TLI->getValueType(DL, Dst); 1538 1539 // The function getSimpleVT only handles simple value types. 1540 if (!SrcTy.isSimple() || !DstTy.isSimple()) 1541 return BaseT::getCastInstrCost(Opcode, Dst, Src); 1542 1543 if (ST->hasDQI()) 1544 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 1545 DstTy.getSimpleVT(), 1546 SrcTy.getSimpleVT())) 1547 return Entry->Cost; 1548 1549 if (ST->hasAVX512()) 1550 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 1551 DstTy.getSimpleVT(), 1552 SrcTy.getSimpleVT())) 1553 return Entry->Cost; 1554 1555 if (ST->hasAVX2()) { 1556 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 1557 DstTy.getSimpleVT(), 1558 SrcTy.getSimpleVT())) 1559 return Entry->Cost; 1560 } 1561 1562 if (ST->hasAVX()) { 1563 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 1564 DstTy.getSimpleVT(), 1565 SrcTy.getSimpleVT())) 1566 return Entry->Cost; 1567 } 1568 1569 if (ST->hasSSE41()) { 1570 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 1571 DstTy.getSimpleVT(), 1572 SrcTy.getSimpleVT())) 1573 return Entry->Cost; 1574 } 1575 1576 if (ST->hasSSE2()) { 1577 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1578 DstTy.getSimpleVT(), 1579 SrcTy.getSimpleVT())) 1580 return Entry->Cost; 1581 } 1582 1583 return BaseT::getCastInstrCost(Opcode, Dst, Src, I); 1584 } 1585 1586 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 1587 const Instruction *I) { 1588 // Legalize the type. 1589 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 1590 1591 MVT MTy = LT.second; 1592 1593 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1594 assert(ISD && "Invalid opcode"); 1595 1596 static const CostTblEntry SSE2CostTbl[] = { 1597 { ISD::SETCC, MVT::v2i64, 8 }, 1598 { ISD::SETCC, MVT::v4i32, 1 }, 1599 { ISD::SETCC, MVT::v8i16, 1 }, 1600 { ISD::SETCC, MVT::v16i8, 1 }, 1601 }; 1602 1603 static const CostTblEntry SSE42CostTbl[] = { 1604 { ISD::SETCC, MVT::v2f64, 1 }, 1605 { ISD::SETCC, MVT::v4f32, 1 }, 1606 { ISD::SETCC, MVT::v2i64, 1 }, 1607 }; 1608 1609 static const CostTblEntry AVX1CostTbl[] = { 1610 { ISD::SETCC, MVT::v4f64, 1 }, 1611 { ISD::SETCC, MVT::v8f32, 1 }, 1612 // AVX1 does not support 8-wide integer compare. 1613 { ISD::SETCC, MVT::v4i64, 4 }, 1614 { ISD::SETCC, MVT::v8i32, 4 }, 1615 { ISD::SETCC, MVT::v16i16, 4 }, 1616 { ISD::SETCC, MVT::v32i8, 4 }, 1617 }; 1618 1619 static const CostTblEntry AVX2CostTbl[] = { 1620 { ISD::SETCC, MVT::v4i64, 1 }, 1621 { ISD::SETCC, MVT::v8i32, 1 }, 1622 { ISD::SETCC, MVT::v16i16, 1 }, 1623 { ISD::SETCC, MVT::v32i8, 1 }, 1624 }; 1625 1626 static const CostTblEntry AVX512CostTbl[] = { 1627 { ISD::SETCC, MVT::v8i64, 1 }, 1628 { ISD::SETCC, MVT::v16i32, 1 }, 1629 { ISD::SETCC, MVT::v8f64, 1 }, 1630 { ISD::SETCC, MVT::v16f32, 1 }, 1631 }; 1632 1633 static const CostTblEntry AVX512BWCostTbl[] = { 1634 { ISD::SETCC, MVT::v32i16, 1 }, 1635 { ISD::SETCC, MVT::v64i8, 1 }, 1636 }; 1637 1638 if (ST->hasBWI()) 1639 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 1640 return LT.first * Entry->Cost; 1641 1642 if (ST->hasAVX512()) 1643 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 1644 return LT.first * Entry->Cost; 1645 1646 if (ST->hasAVX2()) 1647 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 1648 return LT.first * Entry->Cost; 1649 1650 if (ST->hasAVX()) 1651 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 1652 return LT.first * Entry->Cost; 1653 1654 if (ST->hasSSE42()) 1655 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 1656 return LT.first * Entry->Cost; 1657 1658 if (ST->hasSSE2()) 1659 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 1660 return LT.first * Entry->Cost; 1661 1662 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I); 1663 } 1664 1665 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 1666 1667 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 1668 ArrayRef<Type *> Tys, FastMathFlags FMF, 1669 unsigned ScalarizationCostPassed) { 1670 // Costs should match the codegen from: 1671 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 1672 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 1673 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 1674 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 1675 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 1676 static const CostTblEntry AVX512CDCostTbl[] = { 1677 { ISD::CTLZ, MVT::v8i64, 1 }, 1678 { ISD::CTLZ, MVT::v16i32, 1 }, 1679 { ISD::CTLZ, MVT::v32i16, 8 }, 1680 { ISD::CTLZ, MVT::v64i8, 20 }, 1681 { ISD::CTLZ, MVT::v4i64, 1 }, 1682 { ISD::CTLZ, MVT::v8i32, 1 }, 1683 { ISD::CTLZ, MVT::v16i16, 4 }, 1684 { ISD::CTLZ, MVT::v32i8, 10 }, 1685 { ISD::CTLZ, MVT::v2i64, 1 }, 1686 { ISD::CTLZ, MVT::v4i32, 1 }, 1687 { ISD::CTLZ, MVT::v8i16, 4 }, 1688 { ISD::CTLZ, MVT::v16i8, 4 }, 1689 }; 1690 static const CostTblEntry AVX512BWCostTbl[] = { 1691 { ISD::BITREVERSE, MVT::v8i64, 5 }, 1692 { ISD::BITREVERSE, MVT::v16i32, 5 }, 1693 { ISD::BITREVERSE, MVT::v32i16, 5 }, 1694 { ISD::BITREVERSE, MVT::v64i8, 5 }, 1695 { ISD::CTLZ, MVT::v8i64, 23 }, 1696 { ISD::CTLZ, MVT::v16i32, 22 }, 1697 { ISD::CTLZ, MVT::v32i16, 18 }, 1698 { ISD::CTLZ, MVT::v64i8, 17 }, 1699 { ISD::CTPOP, MVT::v8i64, 7 }, 1700 { ISD::CTPOP, MVT::v16i32, 11 }, 1701 { ISD::CTPOP, MVT::v32i16, 9 }, 1702 { ISD::CTPOP, MVT::v64i8, 6 }, 1703 { ISD::CTTZ, MVT::v8i64, 10 }, 1704 { ISD::CTTZ, MVT::v16i32, 14 }, 1705 { ISD::CTTZ, MVT::v32i16, 12 }, 1706 { ISD::CTTZ, MVT::v64i8, 9 }, 1707 }; 1708 static const CostTblEntry AVX512CostTbl[] = { 1709 { ISD::BITREVERSE, MVT::v8i64, 36 }, 1710 { ISD::BITREVERSE, MVT::v16i32, 24 }, 1711 { ISD::CTLZ, MVT::v8i64, 29 }, 1712 { ISD::CTLZ, MVT::v16i32, 35 }, 1713 { ISD::CTPOP, MVT::v8i64, 16 }, 1714 { ISD::CTPOP, MVT::v16i32, 24 }, 1715 { ISD::CTTZ, MVT::v8i64, 20 }, 1716 { ISD::CTTZ, MVT::v16i32, 28 }, 1717 }; 1718 static const CostTblEntry XOPCostTbl[] = { 1719 { ISD::BITREVERSE, MVT::v4i64, 4 }, 1720 { ISD::BITREVERSE, MVT::v8i32, 4 }, 1721 { ISD::BITREVERSE, MVT::v16i16, 4 }, 1722 { ISD::BITREVERSE, MVT::v32i8, 4 }, 1723 { ISD::BITREVERSE, MVT::v2i64, 1 }, 1724 { ISD::BITREVERSE, MVT::v4i32, 1 }, 1725 { ISD::BITREVERSE, MVT::v8i16, 1 }, 1726 { ISD::BITREVERSE, MVT::v16i8, 1 }, 1727 { ISD::BITREVERSE, MVT::i64, 3 }, 1728 { ISD::BITREVERSE, MVT::i32, 3 }, 1729 { ISD::BITREVERSE, MVT::i16, 3 }, 1730 { ISD::BITREVERSE, MVT::i8, 3 } 1731 }; 1732 static const CostTblEntry AVX2CostTbl[] = { 1733 { ISD::BITREVERSE, MVT::v4i64, 5 }, 1734 { ISD::BITREVERSE, MVT::v8i32, 5 }, 1735 { ISD::BITREVERSE, MVT::v16i16, 5 }, 1736 { ISD::BITREVERSE, MVT::v32i8, 5 }, 1737 { ISD::BSWAP, MVT::v4i64, 1 }, 1738 { ISD::BSWAP, MVT::v8i32, 1 }, 1739 { ISD::BSWAP, MVT::v16i16, 1 }, 1740 { ISD::CTLZ, MVT::v4i64, 23 }, 1741 { ISD::CTLZ, MVT::v8i32, 18 }, 1742 { ISD::CTLZ, MVT::v16i16, 14 }, 1743 { ISD::CTLZ, MVT::v32i8, 9 }, 1744 { ISD::CTPOP, MVT::v4i64, 7 }, 1745 { ISD::CTPOP, MVT::v8i32, 11 }, 1746 { ISD::CTPOP, MVT::v16i16, 9 }, 1747 { ISD::CTPOP, MVT::v32i8, 6 }, 1748 { ISD::CTTZ, MVT::v4i64, 10 }, 1749 { ISD::CTTZ, MVT::v8i32, 14 }, 1750 { ISD::CTTZ, MVT::v16i16, 12 }, 1751 { ISD::CTTZ, MVT::v32i8, 9 }, 1752 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 1753 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 1754 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 1755 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 1756 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 1757 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 1758 }; 1759 static const CostTblEntry AVX1CostTbl[] = { 1760 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 1761 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 1762 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 1763 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 1764 { ISD::BSWAP, MVT::v4i64, 4 }, 1765 { ISD::BSWAP, MVT::v8i32, 4 }, 1766 { ISD::BSWAP, MVT::v16i16, 4 }, 1767 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 1768 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 1769 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 1770 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 1771 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 1772 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 1773 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 1774 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 1775 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 1776 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 1777 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 1778 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 1779 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 1780 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 1781 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 1782 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 1783 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 1784 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 1785 }; 1786 static const CostTblEntry GLMCostTbl[] = { 1787 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 1788 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 1789 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 1790 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 1791 }; 1792 static const CostTblEntry SLMCostTbl[] = { 1793 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 1794 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 1795 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 1796 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 1797 }; 1798 static const CostTblEntry SSE42CostTbl[] = { 1799 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 1800 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 1801 }; 1802 static const CostTblEntry SSSE3CostTbl[] = { 1803 { ISD::BITREVERSE, MVT::v2i64, 5 }, 1804 { ISD::BITREVERSE, MVT::v4i32, 5 }, 1805 { ISD::BITREVERSE, MVT::v8i16, 5 }, 1806 { ISD::BITREVERSE, MVT::v16i8, 5 }, 1807 { ISD::BSWAP, MVT::v2i64, 1 }, 1808 { ISD::BSWAP, MVT::v4i32, 1 }, 1809 { ISD::BSWAP, MVT::v8i16, 1 }, 1810 { ISD::CTLZ, MVT::v2i64, 23 }, 1811 { ISD::CTLZ, MVT::v4i32, 18 }, 1812 { ISD::CTLZ, MVT::v8i16, 14 }, 1813 { ISD::CTLZ, MVT::v16i8, 9 }, 1814 { ISD::CTPOP, MVT::v2i64, 7 }, 1815 { ISD::CTPOP, MVT::v4i32, 11 }, 1816 { ISD::CTPOP, MVT::v8i16, 9 }, 1817 { ISD::CTPOP, MVT::v16i8, 6 }, 1818 { ISD::CTTZ, MVT::v2i64, 10 }, 1819 { ISD::CTTZ, MVT::v4i32, 14 }, 1820 { ISD::CTTZ, MVT::v8i16, 12 }, 1821 { ISD::CTTZ, MVT::v16i8, 9 } 1822 }; 1823 static const CostTblEntry SSE2CostTbl[] = { 1824 { ISD::BITREVERSE, MVT::v2i64, 29 }, 1825 { ISD::BITREVERSE, MVT::v4i32, 27 }, 1826 { ISD::BITREVERSE, MVT::v8i16, 27 }, 1827 { ISD::BITREVERSE, MVT::v16i8, 20 }, 1828 { ISD::BSWAP, MVT::v2i64, 7 }, 1829 { ISD::BSWAP, MVT::v4i32, 7 }, 1830 { ISD::BSWAP, MVT::v8i16, 7 }, 1831 { ISD::CTLZ, MVT::v2i64, 25 }, 1832 { ISD::CTLZ, MVT::v4i32, 26 }, 1833 { ISD::CTLZ, MVT::v8i16, 20 }, 1834 { ISD::CTLZ, MVT::v16i8, 17 }, 1835 { ISD::CTPOP, MVT::v2i64, 12 }, 1836 { ISD::CTPOP, MVT::v4i32, 15 }, 1837 { ISD::CTPOP, MVT::v8i16, 13 }, 1838 { ISD::CTPOP, MVT::v16i8, 10 }, 1839 { ISD::CTTZ, MVT::v2i64, 14 }, 1840 { ISD::CTTZ, MVT::v4i32, 18 }, 1841 { ISD::CTTZ, MVT::v8i16, 16 }, 1842 { ISD::CTTZ, MVT::v16i8, 13 }, 1843 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 1844 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 1845 }; 1846 static const CostTblEntry SSE1CostTbl[] = { 1847 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 1848 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 1849 }; 1850 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 1851 { ISD::BITREVERSE, MVT::i64, 14 } 1852 }; 1853 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 1854 { ISD::BITREVERSE, MVT::i32, 14 }, 1855 { ISD::BITREVERSE, MVT::i16, 14 }, 1856 { ISD::BITREVERSE, MVT::i8, 11 } 1857 }; 1858 1859 unsigned ISD = ISD::DELETED_NODE; 1860 switch (IID) { 1861 default: 1862 break; 1863 case Intrinsic::bitreverse: 1864 ISD = ISD::BITREVERSE; 1865 break; 1866 case Intrinsic::bswap: 1867 ISD = ISD::BSWAP; 1868 break; 1869 case Intrinsic::ctlz: 1870 ISD = ISD::CTLZ; 1871 break; 1872 case Intrinsic::ctpop: 1873 ISD = ISD::CTPOP; 1874 break; 1875 case Intrinsic::cttz: 1876 ISD = ISD::CTTZ; 1877 break; 1878 case Intrinsic::sqrt: 1879 ISD = ISD::FSQRT; 1880 break; 1881 } 1882 1883 // Legalize the type. 1884 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 1885 MVT MTy = LT.second; 1886 1887 // Attempt to lookup cost. 1888 if (ST->isGLM()) 1889 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 1890 return LT.first * Entry->Cost; 1891 1892 if (ST->isSLM()) 1893 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 1894 return LT.first * Entry->Cost; 1895 1896 if (ST->hasCDI()) 1897 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 1898 return LT.first * Entry->Cost; 1899 1900 if (ST->hasBWI()) 1901 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 1902 return LT.first * Entry->Cost; 1903 1904 if (ST->hasAVX512()) 1905 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 1906 return LT.first * Entry->Cost; 1907 1908 if (ST->hasXOP()) 1909 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 1910 return LT.first * Entry->Cost; 1911 1912 if (ST->hasAVX2()) 1913 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 1914 return LT.first * Entry->Cost; 1915 1916 if (ST->hasAVX()) 1917 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 1918 return LT.first * Entry->Cost; 1919 1920 if (ST->hasSSE42()) 1921 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 1922 return LT.first * Entry->Cost; 1923 1924 if (ST->hasSSSE3()) 1925 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 1926 return LT.first * Entry->Cost; 1927 1928 if (ST->hasSSE2()) 1929 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 1930 return LT.first * Entry->Cost; 1931 1932 if (ST->hasSSE1()) 1933 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 1934 return LT.first * Entry->Cost; 1935 1936 if (ST->is64Bit()) 1937 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 1938 return LT.first * Entry->Cost; 1939 1940 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 1941 return LT.first * Entry->Cost; 1942 1943 return BaseT::getIntrinsicInstrCost(IID, RetTy, Tys, FMF, ScalarizationCostPassed); 1944 } 1945 1946 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 1947 ArrayRef<Value *> Args, FastMathFlags FMF, unsigned VF) { 1948 return BaseT::getIntrinsicInstrCost(IID, RetTy, Args, FMF, VF); 1949 } 1950 1951 int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { 1952 assert(Val->isVectorTy() && "This must be a vector type"); 1953 1954 Type *ScalarType = Val->getScalarType(); 1955 1956 if (Index != -1U) { 1957 // Legalize the type. 1958 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 1959 1960 // This type is legalized to a scalar type. 1961 if (!LT.second.isVector()) 1962 return 0; 1963 1964 // The type may be split. Normalize the index to the new type. 1965 unsigned Width = LT.second.getVectorNumElements(); 1966 Index = Index % Width; 1967 1968 // Floating point scalars are already located in index #0. 1969 if (ScalarType->isFloatingPointTy() && Index == 0) 1970 return 0; 1971 } 1972 1973 // Add to the base cost if we know that the extracted element of a vector is 1974 // destined to be moved to and used in the integer register file. 1975 int RegisterFileMoveCost = 0; 1976 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 1977 RegisterFileMoveCost = 1; 1978 1979 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 1980 } 1981 1982 int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, 1983 unsigned AddressSpace, const Instruction *I) { 1984 // Handle non-power-of-two vectors such as <3 x float> 1985 if (VectorType *VTy = dyn_cast<VectorType>(Src)) { 1986 unsigned NumElem = VTy->getVectorNumElements(); 1987 1988 // Handle a few common cases: 1989 // <3 x float> 1990 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 1991 // Cost = 64 bit store + extract + 32 bit store. 1992 return 3; 1993 1994 // <3 x double> 1995 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 1996 // Cost = 128 bit store + unpack + 64 bit store. 1997 return 3; 1998 1999 // Assume that all other non-power-of-two numbers are scalarized. 2000 if (!isPowerOf2_32(NumElem)) { 2001 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment, 2002 AddressSpace); 2003 int SplitCost = getScalarizationOverhead(Src, Opcode == Instruction::Load, 2004 Opcode == Instruction::Store); 2005 return NumElem * Cost + SplitCost; 2006 } 2007 } 2008 2009 // Legalize the type. 2010 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 2011 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 2012 "Invalid Opcode"); 2013 2014 // Each load/store unit costs 1. 2015 int Cost = LT.first * 1; 2016 2017 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a 2018 // proxy for a double-pumped AVX memory interface such as on Sandybridge. 2019 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow()) 2020 Cost *= 2; 2021 2022 return Cost; 2023 } 2024 2025 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, 2026 unsigned Alignment, 2027 unsigned AddressSpace) { 2028 VectorType *SrcVTy = dyn_cast<VectorType>(SrcTy); 2029 if (!SrcVTy) 2030 // To calculate scalar take the regular cost, without mask 2031 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace); 2032 2033 unsigned NumElem = SrcVTy->getVectorNumElements(); 2034 VectorType *MaskTy = 2035 VectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 2036 if ((Opcode == Instruction::Load && !isLegalMaskedLoad(SrcVTy)) || 2037 (Opcode == Instruction::Store && !isLegalMaskedStore(SrcVTy)) || 2038 !isPowerOf2_32(NumElem)) { 2039 // Scalarization 2040 int MaskSplitCost = getScalarizationOverhead(MaskTy, false, true); 2041 int ScalarCompareCost = getCmpSelInstrCost( 2042 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr); 2043 int BranchCost = getCFInstrCost(Instruction::Br); 2044 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 2045 2046 int ValueSplitCost = getScalarizationOverhead( 2047 SrcVTy, Opcode == Instruction::Load, Opcode == Instruction::Store); 2048 int MemopCost = 2049 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2050 Alignment, AddressSpace); 2051 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 2052 } 2053 2054 // Legalize the type. 2055 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 2056 auto VT = TLI->getValueType(DL, SrcVTy); 2057 int Cost = 0; 2058 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 2059 LT.second.getVectorNumElements() == NumElem) 2060 // Promotion requires expand/truncate for data and a shuffle for mask. 2061 Cost += getShuffleCost(TTI::SK_Select, SrcVTy, 0, nullptr) + 2062 getShuffleCost(TTI::SK_Select, MaskTy, 0, nullptr); 2063 2064 else if (LT.second.getVectorNumElements() > NumElem) { 2065 VectorType *NewMaskTy = VectorType::get(MaskTy->getVectorElementType(), 2066 LT.second.getVectorNumElements()); 2067 // Expanding requires fill mask with zeroes 2068 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, 0, MaskTy); 2069 } 2070 if (!ST->hasAVX512()) 2071 return Cost + LT.first*4; // Each maskmov costs 4 2072 2073 // AVX-512 masked load/store is cheapper 2074 return Cost+LT.first; 2075 } 2076 2077 int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE, 2078 const SCEV *Ptr) { 2079 // Address computations in vectorized code with non-consecutive addresses will 2080 // likely result in more instructions compared to scalar code where the 2081 // computation can more often be merged into the index mode. The resulting 2082 // extra micro-ops can significantly decrease throughput. 2083 unsigned NumVectorInstToHideOverhead = 10; 2084 2085 // Cost modeling of Strided Access Computation is hidden by the indexing 2086 // modes of X86 regardless of the stride value. We dont believe that there 2087 // is a difference between constant strided access in gerenal and constant 2088 // strided value which is less than or equal to 64. 2089 // Even in the case of (loop invariant) stride whose value is not known at 2090 // compile time, the address computation will not incur more than one extra 2091 // ADD instruction. 2092 if (Ty->isVectorTy() && SE) { 2093 if (!BaseT::isStridedAccess(Ptr)) 2094 return NumVectorInstToHideOverhead; 2095 if (!BaseT::getConstantStrideStep(SE, Ptr)) 2096 return 1; 2097 } 2098 2099 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 2100 } 2101 2102 int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, Type *ValTy, 2103 bool IsPairwise) { 2104 2105 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2106 2107 MVT MTy = LT.second; 2108 2109 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2110 assert(ISD && "Invalid opcode"); 2111 2112 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 2113 // and make it as the cost. 2114 2115 static const CostTblEntry SSE42CostTblPairWise[] = { 2116 { ISD::FADD, MVT::v2f64, 2 }, 2117 { ISD::FADD, MVT::v4f32, 4 }, 2118 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 2119 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5". 2120 { ISD::ADD, MVT::v8i16, 5 }, 2121 }; 2122 2123 static const CostTblEntry AVX1CostTblPairWise[] = { 2124 { ISD::FADD, MVT::v4f32, 4 }, 2125 { ISD::FADD, MVT::v4f64, 5 }, 2126 { ISD::FADD, MVT::v8f32, 7 }, 2127 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 2128 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5". 2129 { ISD::ADD, MVT::v4i64, 5 }, // The data reported by the IACA tool is "4.8". 2130 { ISD::ADD, MVT::v8i16, 5 }, 2131 { ISD::ADD, MVT::v8i32, 5 }, 2132 }; 2133 2134 static const CostTblEntry SSE42CostTblNoPairWise[] = { 2135 { ISD::FADD, MVT::v2f64, 2 }, 2136 { ISD::FADD, MVT::v4f32, 4 }, 2137 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 2138 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 2139 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 2140 }; 2141 2142 static const CostTblEntry AVX1CostTblNoPairWise[] = { 2143 { ISD::FADD, MVT::v4f32, 3 }, 2144 { ISD::FADD, MVT::v4f64, 3 }, 2145 { ISD::FADD, MVT::v8f32, 4 }, 2146 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 2147 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "2.8". 2148 { ISD::ADD, MVT::v4i64, 3 }, 2149 { ISD::ADD, MVT::v8i16, 4 }, 2150 { ISD::ADD, MVT::v8i32, 5 }, 2151 }; 2152 2153 if (IsPairwise) { 2154 if (ST->hasAVX()) 2155 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy)) 2156 return LT.first * Entry->Cost; 2157 2158 if (ST->hasSSE42()) 2159 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy)) 2160 return LT.first * Entry->Cost; 2161 } else { 2162 if (ST->hasAVX()) 2163 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 2164 return LT.first * Entry->Cost; 2165 2166 if (ST->hasSSE42()) 2167 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy)) 2168 return LT.first * Entry->Cost; 2169 } 2170 2171 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise); 2172 } 2173 2174 int X86TTIImpl::getMinMaxReductionCost(Type *ValTy, Type *CondTy, 2175 bool IsPairwise, bool IsUnsigned) { 2176 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2177 2178 MVT MTy = LT.second; 2179 2180 int ISD; 2181 if (ValTy->isIntOrIntVectorTy()) { 2182 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 2183 } else { 2184 assert(ValTy->isFPOrFPVectorTy() && 2185 "Expected float point or integer vector type."); 2186 ISD = ISD::FMINNUM; 2187 } 2188 2189 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 2190 // and make it as the cost. 2191 2192 static const CostTblEntry SSE42CostTblPairWise[] = { 2193 {ISD::FMINNUM, MVT::v2f64, 3}, 2194 {ISD::FMINNUM, MVT::v4f32, 2}, 2195 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8" 2196 {ISD::UMIN, MVT::v2i64, 8}, // The data reported by the IACA is "8.6" 2197 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5" 2198 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8" 2199 {ISD::SMIN, MVT::v8i16, 2}, 2200 {ISD::UMIN, MVT::v8i16, 2}, 2201 }; 2202 2203 static const CostTblEntry AVX1CostTblPairWise[] = { 2204 {ISD::FMINNUM, MVT::v4f32, 1}, 2205 {ISD::FMINNUM, MVT::v4f64, 1}, 2206 {ISD::FMINNUM, MVT::v8f32, 2}, 2207 {ISD::SMIN, MVT::v2i64, 3}, 2208 {ISD::UMIN, MVT::v2i64, 3}, 2209 {ISD::SMIN, MVT::v4i32, 1}, 2210 {ISD::UMIN, MVT::v4i32, 1}, 2211 {ISD::SMIN, MVT::v8i16, 1}, 2212 {ISD::UMIN, MVT::v8i16, 1}, 2213 {ISD::SMIN, MVT::v8i32, 3}, 2214 {ISD::UMIN, MVT::v8i32, 3}, 2215 }; 2216 2217 static const CostTblEntry AVX2CostTblPairWise[] = { 2218 {ISD::SMIN, MVT::v4i64, 2}, 2219 {ISD::UMIN, MVT::v4i64, 2}, 2220 {ISD::SMIN, MVT::v8i32, 1}, 2221 {ISD::UMIN, MVT::v8i32, 1}, 2222 {ISD::SMIN, MVT::v16i16, 1}, 2223 {ISD::UMIN, MVT::v16i16, 1}, 2224 {ISD::SMIN, MVT::v32i8, 2}, 2225 {ISD::UMIN, MVT::v32i8, 2}, 2226 }; 2227 2228 static const CostTblEntry AVX512CostTblPairWise[] = { 2229 {ISD::FMINNUM, MVT::v8f64, 1}, 2230 {ISD::FMINNUM, MVT::v16f32, 2}, 2231 {ISD::SMIN, MVT::v8i64, 2}, 2232 {ISD::UMIN, MVT::v8i64, 2}, 2233 {ISD::SMIN, MVT::v16i32, 1}, 2234 {ISD::UMIN, MVT::v16i32, 1}, 2235 }; 2236 2237 static const CostTblEntry SSE42CostTblNoPairWise[] = { 2238 {ISD::FMINNUM, MVT::v2f64, 3}, 2239 {ISD::FMINNUM, MVT::v4f32, 3}, 2240 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8" 2241 {ISD::UMIN, MVT::v2i64, 9}, // The data reported by the IACA is "8.6" 2242 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5" 2243 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8" 2244 {ISD::SMIN, MVT::v8i16, 1}, // The data reported by the IACA is "1.5" 2245 {ISD::UMIN, MVT::v8i16, 2}, // The data reported by the IACA is "1.8" 2246 }; 2247 2248 static const CostTblEntry AVX1CostTblNoPairWise[] = { 2249 {ISD::FMINNUM, MVT::v4f32, 1}, 2250 {ISD::FMINNUM, MVT::v4f64, 1}, 2251 {ISD::FMINNUM, MVT::v8f32, 1}, 2252 {ISD::SMIN, MVT::v2i64, 3}, 2253 {ISD::UMIN, MVT::v2i64, 3}, 2254 {ISD::SMIN, MVT::v4i32, 1}, 2255 {ISD::UMIN, MVT::v4i32, 1}, 2256 {ISD::SMIN, MVT::v8i16, 1}, 2257 {ISD::UMIN, MVT::v8i16, 1}, 2258 {ISD::SMIN, MVT::v8i32, 2}, 2259 {ISD::UMIN, MVT::v8i32, 2}, 2260 }; 2261 2262 static const CostTblEntry AVX2CostTblNoPairWise[] = { 2263 {ISD::SMIN, MVT::v4i64, 1}, 2264 {ISD::UMIN, MVT::v4i64, 1}, 2265 {ISD::SMIN, MVT::v8i32, 1}, 2266 {ISD::UMIN, MVT::v8i32, 1}, 2267 {ISD::SMIN, MVT::v16i16, 1}, 2268 {ISD::UMIN, MVT::v16i16, 1}, 2269 {ISD::SMIN, MVT::v32i8, 1}, 2270 {ISD::UMIN, MVT::v32i8, 1}, 2271 }; 2272 2273 static const CostTblEntry AVX512CostTblNoPairWise[] = { 2274 {ISD::FMINNUM, MVT::v8f64, 1}, 2275 {ISD::FMINNUM, MVT::v16f32, 2}, 2276 {ISD::SMIN, MVT::v8i64, 1}, 2277 {ISD::UMIN, MVT::v8i64, 1}, 2278 {ISD::SMIN, MVT::v16i32, 1}, 2279 {ISD::UMIN, MVT::v16i32, 1}, 2280 }; 2281 2282 if (IsPairwise) { 2283 if (ST->hasAVX512()) 2284 if (const auto *Entry = CostTableLookup(AVX512CostTblPairWise, ISD, MTy)) 2285 return LT.first * Entry->Cost; 2286 2287 if (ST->hasAVX2()) 2288 if (const auto *Entry = CostTableLookup(AVX2CostTblPairWise, ISD, MTy)) 2289 return LT.first * Entry->Cost; 2290 2291 if (ST->hasAVX()) 2292 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy)) 2293 return LT.first * Entry->Cost; 2294 2295 if (ST->hasSSE42()) 2296 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy)) 2297 return LT.first * Entry->Cost; 2298 } else { 2299 if (ST->hasAVX512()) 2300 if (const auto *Entry = 2301 CostTableLookup(AVX512CostTblNoPairWise, ISD, MTy)) 2302 return LT.first * Entry->Cost; 2303 2304 if (ST->hasAVX2()) 2305 if (const auto *Entry = CostTableLookup(AVX2CostTblNoPairWise, ISD, MTy)) 2306 return LT.first * Entry->Cost; 2307 2308 if (ST->hasAVX()) 2309 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 2310 return LT.first * Entry->Cost; 2311 2312 if (ST->hasSSE42()) 2313 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy)) 2314 return LT.first * Entry->Cost; 2315 } 2316 2317 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned); 2318 } 2319 2320 /// Calculate the cost of materializing a 64-bit value. This helper 2321 /// method might only calculate a fraction of a larger immediate. Therefore it 2322 /// is valid to return a cost of ZERO. 2323 int X86TTIImpl::getIntImmCost(int64_t Val) { 2324 if (Val == 0) 2325 return TTI::TCC_Free; 2326 2327 if (isInt<32>(Val)) 2328 return TTI::TCC_Basic; 2329 2330 return 2 * TTI::TCC_Basic; 2331 } 2332 2333 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { 2334 assert(Ty->isIntegerTy()); 2335 2336 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 2337 if (BitSize == 0) 2338 return ~0U; 2339 2340 // Never hoist constants larger than 128bit, because this might lead to 2341 // incorrect code generation or assertions in codegen. 2342 // Fixme: Create a cost model for types larger than i128 once the codegen 2343 // issues have been fixed. 2344 if (BitSize > 128) 2345 return TTI::TCC_Free; 2346 2347 if (Imm == 0) 2348 return TTI::TCC_Free; 2349 2350 // Sign-extend all constants to a multiple of 64-bit. 2351 APInt ImmVal = Imm; 2352 if (BitSize % 64 != 0) 2353 ImmVal = Imm.sext(alignTo(BitSize, 64)); 2354 2355 // Split the constant into 64-bit chunks and calculate the cost for each 2356 // chunk. 2357 int Cost = 0; 2358 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 2359 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 2360 int64_t Val = Tmp.getSExtValue(); 2361 Cost += getIntImmCost(Val); 2362 } 2363 // We need at least one instruction to materialize the constant. 2364 return std::max(1, Cost); 2365 } 2366 2367 int X86TTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, 2368 Type *Ty) { 2369 assert(Ty->isIntegerTy()); 2370 2371 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 2372 // There is no cost model for constants with a bit size of 0. Return TCC_Free 2373 // here, so that constant hoisting will ignore this constant. 2374 if (BitSize == 0) 2375 return TTI::TCC_Free; 2376 2377 unsigned ImmIdx = ~0U; 2378 switch (Opcode) { 2379 default: 2380 return TTI::TCC_Free; 2381 case Instruction::GetElementPtr: 2382 // Always hoist the base address of a GetElementPtr. This prevents the 2383 // creation of new constants for every base constant that gets constant 2384 // folded with the offset. 2385 if (Idx == 0) 2386 return 2 * TTI::TCC_Basic; 2387 return TTI::TCC_Free; 2388 case Instruction::Store: 2389 ImmIdx = 0; 2390 break; 2391 case Instruction::ICmp: 2392 // This is an imperfect hack to prevent constant hoisting of 2393 // compares that might be trying to check if a 64-bit value fits in 2394 // 32-bits. The backend can optimize these cases using a right shift by 32. 2395 // Ideally we would check the compare predicate here. There also other 2396 // similar immediates the backend can use shifts for. 2397 if (Idx == 1 && Imm.getBitWidth() == 64) { 2398 uint64_t ImmVal = Imm.getZExtValue(); 2399 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 2400 return TTI::TCC_Free; 2401 } 2402 ImmIdx = 1; 2403 break; 2404 case Instruction::And: 2405 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 2406 // by using a 32-bit operation with implicit zero extension. Detect such 2407 // immediates here as the normal path expects bit 31 to be sign extended. 2408 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 2409 return TTI::TCC_Free; 2410 ImmIdx = 1; 2411 break; 2412 case Instruction::Add: 2413 case Instruction::Sub: 2414 // For add/sub, we can use the opposite instruction for INT32_MIN. 2415 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 2416 return TTI::TCC_Free; 2417 ImmIdx = 1; 2418 break; 2419 case Instruction::UDiv: 2420 case Instruction::SDiv: 2421 case Instruction::URem: 2422 case Instruction::SRem: 2423 // Division by constant is typically expanded later into a different 2424 // instruction sequence. This completely changes the constants. 2425 // Report them as "free" to stop ConstantHoist from marking them as opaque. 2426 return TTI::TCC_Free; 2427 case Instruction::Mul: 2428 case Instruction::Or: 2429 case Instruction::Xor: 2430 ImmIdx = 1; 2431 break; 2432 // Always return TCC_Free for the shift value of a shift instruction. 2433 case Instruction::Shl: 2434 case Instruction::LShr: 2435 case Instruction::AShr: 2436 if (Idx == 1) 2437 return TTI::TCC_Free; 2438 break; 2439 case Instruction::Trunc: 2440 case Instruction::ZExt: 2441 case Instruction::SExt: 2442 case Instruction::IntToPtr: 2443 case Instruction::PtrToInt: 2444 case Instruction::BitCast: 2445 case Instruction::PHI: 2446 case Instruction::Call: 2447 case Instruction::Select: 2448 case Instruction::Ret: 2449 case Instruction::Load: 2450 break; 2451 } 2452 2453 if (Idx == ImmIdx) { 2454 int NumConstants = divideCeil(BitSize, 64); 2455 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty); 2456 return (Cost <= NumConstants * TTI::TCC_Basic) 2457 ? static_cast<int>(TTI::TCC_Free) 2458 : Cost; 2459 } 2460 2461 return X86TTIImpl::getIntImmCost(Imm, Ty); 2462 } 2463 2464 int X86TTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, 2465 Type *Ty) { 2466 assert(Ty->isIntegerTy()); 2467 2468 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 2469 // There is no cost model for constants with a bit size of 0. Return TCC_Free 2470 // here, so that constant hoisting will ignore this constant. 2471 if (BitSize == 0) 2472 return TTI::TCC_Free; 2473 2474 switch (IID) { 2475 default: 2476 return TTI::TCC_Free; 2477 case Intrinsic::sadd_with_overflow: 2478 case Intrinsic::uadd_with_overflow: 2479 case Intrinsic::ssub_with_overflow: 2480 case Intrinsic::usub_with_overflow: 2481 case Intrinsic::smul_with_overflow: 2482 case Intrinsic::umul_with_overflow: 2483 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 2484 return TTI::TCC_Free; 2485 break; 2486 case Intrinsic::experimental_stackmap: 2487 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 2488 return TTI::TCC_Free; 2489 break; 2490 case Intrinsic::experimental_patchpoint_void: 2491 case Intrinsic::experimental_patchpoint_i64: 2492 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 2493 return TTI::TCC_Free; 2494 break; 2495 } 2496 return X86TTIImpl::getIntImmCost(Imm, Ty); 2497 } 2498 2499 unsigned X86TTIImpl::getUserCost(const User *U, 2500 ArrayRef<const Value *> Operands) { 2501 if (isa<StoreInst>(U)) { 2502 Value *Ptr = U->getOperand(1); 2503 // Store instruction with index and scale costs 2 Uops. 2504 // Check the preceding GEP to identify non-const indices. 2505 if (auto GEP = dyn_cast<GetElementPtrInst>(Ptr)) { 2506 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 2507 return TTI::TCC_Basic * 2; 2508 } 2509 return TTI::TCC_Basic; 2510 } 2511 return BaseT::getUserCost(U, Operands); 2512 } 2513 2514 // Return an average cost of Gather / Scatter instruction, maybe improved later 2515 int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, Value *Ptr, 2516 unsigned Alignment, unsigned AddressSpace) { 2517 2518 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 2519 unsigned VF = SrcVTy->getVectorNumElements(); 2520 2521 // Try to reduce index size from 64 bit (default for GEP) 2522 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 2523 // operation will use 16 x 64 indices which do not fit in a zmm and needs 2524 // to split. Also check that the base pointer is the same for all lanes, 2525 // and that there's at most one variable index. 2526 auto getIndexSizeInBits = [](Value *Ptr, const DataLayout& DL) { 2527 unsigned IndexSize = DL.getPointerSizeInBits(); 2528 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 2529 if (IndexSize < 64 || !GEP) 2530 return IndexSize; 2531 2532 unsigned NumOfVarIndices = 0; 2533 Value *Ptrs = GEP->getPointerOperand(); 2534 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 2535 return IndexSize; 2536 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 2537 if (isa<Constant>(GEP->getOperand(i))) 2538 continue; 2539 Type *IndxTy = GEP->getOperand(i)->getType(); 2540 if (IndxTy->isVectorTy()) 2541 IndxTy = IndxTy->getVectorElementType(); 2542 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 2543 !isa<SExtInst>(GEP->getOperand(i))) || 2544 ++NumOfVarIndices > 1) 2545 return IndexSize; // 64 2546 } 2547 return (unsigned)32; 2548 }; 2549 2550 2551 // Trying to reduce IndexSize to 32 bits for vector 16. 2552 // By default the IndexSize is equal to pointer size. 2553 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 2554 ? getIndexSizeInBits(Ptr, DL) 2555 : DL.getPointerSizeInBits(); 2556 2557 Type *IndexVTy = VectorType::get(IntegerType::get(SrcVTy->getContext(), 2558 IndexSize), VF); 2559 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy); 2560 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy); 2561 int SplitFactor = std::max(IdxsLT.first, SrcLT.first); 2562 if (SplitFactor > 1) { 2563 // Handle splitting of vector of pointers 2564 Type *SplitSrcTy = VectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 2565 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 2566 AddressSpace); 2567 } 2568 2569 // The gather / scatter cost is given by Intel architects. It is a rough 2570 // number since we are looking at one instruction in a time. 2571 const int GSOverhead = (Opcode == Instruction::Load) 2572 ? ST->getGatherOverhead() 2573 : ST->getScatterOverhead(); 2574 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2575 Alignment, AddressSpace); 2576 } 2577 2578 /// Return the cost of full scalarization of gather / scatter operation. 2579 /// 2580 /// Opcode - Load or Store instruction. 2581 /// SrcVTy - The type of the data vector that should be gathered or scattered. 2582 /// VariableMask - The mask is non-constant at compile time. 2583 /// Alignment - Alignment for one element. 2584 /// AddressSpace - pointer[s] address space. 2585 /// 2586 int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 2587 bool VariableMask, unsigned Alignment, 2588 unsigned AddressSpace) { 2589 unsigned VF = SrcVTy->getVectorNumElements(); 2590 2591 int MaskUnpackCost = 0; 2592 if (VariableMask) { 2593 VectorType *MaskTy = 2594 VectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 2595 MaskUnpackCost = getScalarizationOverhead(MaskTy, false, true); 2596 int ScalarCompareCost = 2597 getCmpSelInstrCost(Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), 2598 nullptr); 2599 int BranchCost = getCFInstrCost(Instruction::Br); 2600 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 2601 } 2602 2603 // The cost of the scalar loads/stores. 2604 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2605 Alignment, AddressSpace); 2606 2607 int InsertExtractCost = 0; 2608 if (Opcode == Instruction::Load) 2609 for (unsigned i = 0; i < VF; ++i) 2610 // Add the cost of inserting each scalar load into the vector 2611 InsertExtractCost += 2612 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 2613 else 2614 for (unsigned i = 0; i < VF; ++i) 2615 // Add the cost of extracting each element out of the data vector 2616 InsertExtractCost += 2617 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 2618 2619 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 2620 } 2621 2622 /// Calculate the cost of Gather / Scatter operation 2623 int X86TTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *SrcVTy, 2624 Value *Ptr, bool VariableMask, 2625 unsigned Alignment) { 2626 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 2627 unsigned VF = SrcVTy->getVectorNumElements(); 2628 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 2629 if (!PtrTy && Ptr->getType()->isVectorTy()) 2630 PtrTy = dyn_cast<PointerType>(Ptr->getType()->getVectorElementType()); 2631 assert(PtrTy && "Unexpected type for Ptr argument"); 2632 unsigned AddressSpace = PtrTy->getAddressSpace(); 2633 2634 bool Scalarize = false; 2635 if ((Opcode == Instruction::Load && !isLegalMaskedGather(SrcVTy)) || 2636 (Opcode == Instruction::Store && !isLegalMaskedScatter(SrcVTy))) 2637 Scalarize = true; 2638 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 2639 // Vector-4 of gather/scatter instruction does not exist on KNL. 2640 // We can extend it to 8 elements, but zeroing upper bits of 2641 // the mask vector will add more instructions. Right now we give the scalar 2642 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 2643 // is better in the VariableMask case. 2644 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 2645 Scalarize = true; 2646 2647 if (Scalarize) 2648 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 2649 AddressSpace); 2650 2651 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 2652 } 2653 2654 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 2655 TargetTransformInfo::LSRCost &C2) { 2656 // X86 specific here are "instruction number 1st priority". 2657 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 2658 C1.NumIVMuls, C1.NumBaseAdds, 2659 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 2660 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 2661 C2.NumIVMuls, C2.NumBaseAdds, 2662 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 2663 } 2664 2665 bool X86TTIImpl::canMacroFuseCmp() { 2666 return ST->hasMacroFusion(); 2667 } 2668 2669 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy) { 2670 // The backend can't handle a single element vector. 2671 if (isa<VectorType>(DataTy) && DataTy->getVectorNumElements() == 1) 2672 return false; 2673 Type *ScalarTy = DataTy->getScalarType(); 2674 int DataWidth = isa<PointerType>(ScalarTy) ? 2675 DL.getPointerSizeInBits() : ScalarTy->getPrimitiveSizeInBits(); 2676 2677 return ((DataWidth == 32 || DataWidth == 64) && ST->hasAVX()) || 2678 ((DataWidth == 8 || DataWidth == 16) && ST->hasBWI()); 2679 } 2680 2681 bool X86TTIImpl::isLegalMaskedStore(Type *DataType) { 2682 return isLegalMaskedLoad(DataType); 2683 } 2684 2685 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy) { 2686 // This function is called now in two cases: from the Loop Vectorizer 2687 // and from the Scalarizer. 2688 // When the Loop Vectorizer asks about legality of the feature, 2689 // the vectorization factor is not calculated yet. The Loop Vectorizer 2690 // sends a scalar type and the decision is based on the width of the 2691 // scalar element. 2692 // Later on, the cost model will estimate usage this intrinsic based on 2693 // the vector type. 2694 // The Scalarizer asks again about legality. It sends a vector type. 2695 // In this case we can reject non-power-of-2 vectors. 2696 // We also reject single element vectors as the type legalizer can't 2697 // scalarize it. 2698 if (isa<VectorType>(DataTy)) { 2699 unsigned NumElts = DataTy->getVectorNumElements(); 2700 if (NumElts == 1 || !isPowerOf2_32(NumElts)) 2701 return false; 2702 } 2703 Type *ScalarTy = DataTy->getScalarType(); 2704 int DataWidth = isa<PointerType>(ScalarTy) ? 2705 DL.getPointerSizeInBits() : ScalarTy->getPrimitiveSizeInBits(); 2706 2707 // Some CPUs have better gather performance than others. 2708 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 2709 // enable gather with a -march. 2710 return (DataWidth == 32 || DataWidth == 64) && 2711 (ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2())); 2712 } 2713 2714 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType) { 2715 // AVX2 doesn't support scatter 2716 if (!ST->hasAVX512()) 2717 return false; 2718 return isLegalMaskedGather(DataType); 2719 } 2720 2721 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 2722 EVT VT = TLI->getValueType(DL, DataType); 2723 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 2724 } 2725 2726 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 2727 return false; 2728 } 2729 2730 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 2731 const Function *Callee) const { 2732 const TargetMachine &TM = getTLI()->getTargetMachine(); 2733 2734 // Work this as a subsetting of subtarget features. 2735 const FeatureBitset &CallerBits = 2736 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 2737 const FeatureBitset &CalleeBits = 2738 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 2739 2740 // FIXME: This is likely too limiting as it will include subtarget features 2741 // that we might not care about for inlining, but it is conservatively 2742 // correct. 2743 return (CallerBits & CalleeBits) == CalleeBits; 2744 } 2745 2746 const X86TTIImpl::TTI::MemCmpExpansionOptions * 2747 X86TTIImpl::enableMemCmpExpansion(bool IsZeroCmp) const { 2748 // Only enable vector loads for equality comparison. 2749 // Right now the vector version is not as fast, see #33329. 2750 static const auto ThreeWayOptions = [this]() { 2751 TTI::MemCmpExpansionOptions Options; 2752 if (ST->is64Bit()) { 2753 Options.LoadSizes.push_back(8); 2754 } 2755 Options.LoadSizes.push_back(4); 2756 Options.LoadSizes.push_back(2); 2757 Options.LoadSizes.push_back(1); 2758 return Options; 2759 }(); 2760 static const auto EqZeroOptions = [this]() { 2761 TTI::MemCmpExpansionOptions Options; 2762 // TODO: enable AVX512 when the DAG is ready. 2763 // if (ST->hasAVX512()) Options.LoadSizes.push_back(64); 2764 if (ST->hasAVX2()) Options.LoadSizes.push_back(32); 2765 if (ST->hasSSE2()) Options.LoadSizes.push_back(16); 2766 if (ST->is64Bit()) { 2767 Options.LoadSizes.push_back(8); 2768 } 2769 Options.LoadSizes.push_back(4); 2770 Options.LoadSizes.push_back(2); 2771 Options.LoadSizes.push_back(1); 2772 return Options; 2773 }(); 2774 return IsZeroCmp ? &EqZeroOptions : &ThreeWayOptions; 2775 } 2776 2777 bool X86TTIImpl::enableInterleavedAccessVectorization() { 2778 // TODO: We expect this to be beneficial regardless of arch, 2779 // but there are currently some unexplained performance artifacts on Atom. 2780 // As a temporary solution, disable on Atom. 2781 return !(ST->isAtom()); 2782 } 2783 2784 // Get estimation for interleaved load/store operations for AVX2. 2785 // \p Factor is the interleaved-access factor (stride) - number of 2786 // (interleaved) elements in the group. 2787 // \p Indices contains the indices for a strided load: when the 2788 // interleaved load has gaps they indicate which elements are used. 2789 // If Indices is empty (or if the number of indices is equal to the size 2790 // of the interleaved-access as given in \p Factor) the access has no gaps. 2791 // 2792 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 2793 // computing the cost using a generic formula as a function of generic 2794 // shuffles. We therefore use a lookup table instead, filled according to 2795 // the instruction sequences that codegen currently generates. 2796 int X86TTIImpl::getInterleavedMemoryOpCostAVX2(unsigned Opcode, Type *VecTy, 2797 unsigned Factor, 2798 ArrayRef<unsigned> Indices, 2799 unsigned Alignment, 2800 unsigned AddressSpace, 2801 bool UseMaskForCond, 2802 bool UseMaskForGaps) { 2803 2804 if (UseMaskForCond || UseMaskForGaps) 2805 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 2806 Alignment, AddressSpace, 2807 UseMaskForCond, UseMaskForGaps); 2808 2809 // We currently Support only fully-interleaved groups, with no gaps. 2810 // TODO: Support also strided loads (interleaved-groups with gaps). 2811 if (Indices.size() && Indices.size() != Factor) 2812 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 2813 Alignment, AddressSpace); 2814 2815 // VecTy for interleave memop is <VF*Factor x Elt>. 2816 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 2817 // VecTy = <12 x i32>. 2818 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 2819 2820 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 2821 // the VF=2, while v2i128 is an unsupported MVT vector type 2822 // (see MachineValueType.h::getVectorVT()). 2823 if (!LegalVT.isVector()) 2824 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 2825 Alignment, AddressSpace); 2826 2827 unsigned VF = VecTy->getVectorNumElements() / Factor; 2828 Type *ScalarTy = VecTy->getVectorElementType(); 2829 2830 // Calculate the number of memory operations (NumOfMemOps), required 2831 // for load/store the VecTy. 2832 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 2833 unsigned LegalVTSize = LegalVT.getStoreSize(); 2834 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 2835 2836 // Get the cost of one memory operation. 2837 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(), 2838 LegalVT.getVectorNumElements()); 2839 unsigned MemOpCost = 2840 getMemoryOpCost(Opcode, SingleMemOpTy, Alignment, AddressSpace); 2841 2842 VectorType *VT = VectorType::get(ScalarTy, VF); 2843 EVT ETy = TLI->getValueType(DL, VT); 2844 if (!ETy.isSimple()) 2845 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 2846 Alignment, AddressSpace); 2847 2848 // TODO: Complete for other data-types and strides. 2849 // Each combination of Stride, ElementTy and VF results in a different 2850 // sequence; The cost tables are therefore accessed with: 2851 // Factor (stride) and VectorType=VFxElemType. 2852 // The Cost accounts only for the shuffle sequence; 2853 // The cost of the loads/stores is accounted for separately. 2854 // 2855 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 2856 { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64 2857 { 2, MVT::v4f64, 6 }, //(load 8f64 and) deinterleave into 2 x 4f64 2858 2859 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8 2860 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8 2861 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8 2862 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8 2863 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8 2864 { 3, MVT::v8f32, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32 2865 2866 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8 2867 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8 2868 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8 2869 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8 2870 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8 2871 2872 { 8, MVT::v8f32, 40 } //(load 64f32 and)deinterleave into 8 x 8f32 2873 }; 2874 2875 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 2876 { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store) 2877 { 2, MVT::v4f64, 6 }, //interleave into 2 x 4f64 into 8f64 (and store) 2878 2879 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store) 2880 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store) 2881 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store) 2882 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store) 2883 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store) 2884 2885 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store) 2886 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store) 2887 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store) 2888 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store) 2889 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store) 2890 }; 2891 2892 if (Opcode == Instruction::Load) { 2893 if (const auto *Entry = 2894 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 2895 return NumOfMemOps * MemOpCost + Entry->Cost; 2896 } else { 2897 assert(Opcode == Instruction::Store && 2898 "Expected Store Instruction at this point"); 2899 if (const auto *Entry = 2900 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 2901 return NumOfMemOps * MemOpCost + Entry->Cost; 2902 } 2903 2904 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 2905 Alignment, AddressSpace); 2906 } 2907 2908 // Get estimation for interleaved load/store operations and strided load. 2909 // \p Indices contains indices for strided load. 2910 // \p Factor - the factor of interleaving. 2911 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 2912 int X86TTIImpl::getInterleavedMemoryOpCostAVX512(unsigned Opcode, Type *VecTy, 2913 unsigned Factor, 2914 ArrayRef<unsigned> Indices, 2915 unsigned Alignment, 2916 unsigned AddressSpace, 2917 bool UseMaskForCond, 2918 bool UseMaskForGaps) { 2919 2920 if (UseMaskForCond || UseMaskForGaps) 2921 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 2922 Alignment, AddressSpace, 2923 UseMaskForCond, UseMaskForGaps); 2924 2925 // VecTy for interleave memop is <VF*Factor x Elt>. 2926 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 2927 // VecTy = <12 x i32>. 2928 2929 // Calculate the number of memory operations (NumOfMemOps), required 2930 // for load/store the VecTy. 2931 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 2932 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 2933 unsigned LegalVTSize = LegalVT.getStoreSize(); 2934 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 2935 2936 // Get the cost of one memory operation. 2937 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(), 2938 LegalVT.getVectorNumElements()); 2939 unsigned MemOpCost = 2940 getMemoryOpCost(Opcode, SingleMemOpTy, Alignment, AddressSpace); 2941 2942 unsigned VF = VecTy->getVectorNumElements() / Factor; 2943 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 2944 2945 if (Opcode == Instruction::Load) { 2946 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 2947 // contain the cost of the optimized shuffle sequence that the 2948 // X86InterleavedAccess pass will generate. 2949 // The cost of loads and stores are computed separately from the table. 2950 2951 // X86InterleavedAccess support only the following interleaved-access group. 2952 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 2953 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 2954 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 2955 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 2956 }; 2957 2958 if (const auto *Entry = 2959 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 2960 return NumOfMemOps * MemOpCost + Entry->Cost; 2961 //If an entry does not exist, fallback to the default implementation. 2962 2963 // Kind of shuffle depends on number of loaded values. 2964 // If we load the entire data in one register, we can use a 1-src shuffle. 2965 // Otherwise, we'll merge 2 sources in each operation. 2966 TTI::ShuffleKind ShuffleKind = 2967 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 2968 2969 unsigned ShuffleCost = 2970 getShuffleCost(ShuffleKind, SingleMemOpTy, 0, nullptr); 2971 2972 unsigned NumOfLoadsInInterleaveGrp = 2973 Indices.size() ? Indices.size() : Factor; 2974 Type *ResultTy = VectorType::get(VecTy->getVectorElementType(), 2975 VecTy->getVectorNumElements() / Factor); 2976 unsigned NumOfResults = 2977 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 2978 NumOfLoadsInInterleaveGrp; 2979 2980 // About a half of the loads may be folded in shuffles when we have only 2981 // one result. If we have more than one result, we do not fold loads at all. 2982 unsigned NumOfUnfoldedLoads = 2983 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 2984 2985 // Get a number of shuffle operations per result. 2986 unsigned NumOfShufflesPerResult = 2987 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 2988 2989 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 2990 // When we have more than one destination, we need additional instructions 2991 // to keep sources. 2992 unsigned NumOfMoves = 0; 2993 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 2994 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 2995 2996 int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 2997 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 2998 2999 return Cost; 3000 } 3001 3002 // Store. 3003 assert(Opcode == Instruction::Store && 3004 "Expected Store Instruction at this point"); 3005 // X86InterleavedAccess support only the following interleaved-access group. 3006 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 3007 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 3008 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 3009 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 3010 3011 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 3012 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 3013 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 3014 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 3015 }; 3016 3017 if (const auto *Entry = 3018 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 3019 return NumOfMemOps * MemOpCost + Entry->Cost; 3020 //If an entry does not exist, fallback to the default implementation. 3021 3022 // There is no strided stores meanwhile. And store can't be folded in 3023 // shuffle. 3024 unsigned NumOfSources = Factor; // The number of values to be merged. 3025 unsigned ShuffleCost = 3026 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, 0, nullptr); 3027 unsigned NumOfShufflesPerStore = NumOfSources - 1; 3028 3029 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 3030 // We need additional instructions to keep sources. 3031 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 3032 int Cost = NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 3033 NumOfMoves; 3034 return Cost; 3035 } 3036 3037 int X86TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, 3038 unsigned Factor, 3039 ArrayRef<unsigned> Indices, 3040 unsigned Alignment, 3041 unsigned AddressSpace, 3042 bool UseMaskForCond, 3043 bool UseMaskForGaps) { 3044 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 3045 Type *EltTy = VecTy->getVectorElementType(); 3046 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 3047 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 3048 return true; 3049 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 3050 return HasBW; 3051 return false; 3052 }; 3053 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 3054 return getInterleavedMemoryOpCostAVX512(Opcode, VecTy, Factor, Indices, 3055 Alignment, AddressSpace, 3056 UseMaskForCond, UseMaskForGaps); 3057 if (ST->hasAVX2()) 3058 return getInterleavedMemoryOpCostAVX2(Opcode, VecTy, Factor, Indices, 3059 Alignment, AddressSpace, 3060 UseMaskForCond, UseMaskForGaps); 3061 3062 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3063 Alignment, AddressSpace, 3064 UseMaskForCond, UseMaskForGaps); 3065 } 3066