1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // X86 cost model. 56 // 57 //===----------------------------------------------------------------------===// 58 59 TargetTransformInfo::PopcntSupportKind 60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 61 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 62 // TODO: Currently the __builtin_popcount() implementation using SSE3 63 // instructions is inefficient. Once the problem is fixed, we should 64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 66 } 67 68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 69 TargetTransformInfo::CacheLevel Level) const { 70 switch (Level) { 71 case TargetTransformInfo::CacheLevel::L1D: 72 // - Penryn 73 // - Nehalem 74 // - Westmere 75 // - Sandy Bridge 76 // - Ivy Bridge 77 // - Haswell 78 // - Broadwell 79 // - Skylake 80 // - Kabylake 81 return 32 * 1024; // 32 KByte 82 case TargetTransformInfo::CacheLevel::L2D: 83 // - Penryn 84 // - Nehalem 85 // - Westmere 86 // - Sandy Bridge 87 // - Ivy Bridge 88 // - Haswell 89 // - Broadwell 90 // - Skylake 91 // - Kabylake 92 return 256 * 1024; // 256 KByte 93 } 94 95 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 96 } 97 98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 99 TargetTransformInfo::CacheLevel Level) const { 100 // - Penryn 101 // - Nehalem 102 // - Westmere 103 // - Sandy Bridge 104 // - Ivy Bridge 105 // - Haswell 106 // - Broadwell 107 // - Skylake 108 // - Kabylake 109 switch (Level) { 110 case TargetTransformInfo::CacheLevel::L1D: 111 LLVM_FALLTHROUGH; 112 case TargetTransformInfo::CacheLevel::L2D: 113 return 8; 114 } 115 116 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 117 } 118 119 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 120 bool Vector = (ClassID == 1); 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 TypeSize 133 X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { 134 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 135 switch (K) { 136 case TargetTransformInfo::RGK_Scalar: 137 return TypeSize::getFixed(ST->is64Bit() ? 64 : 32); 138 case TargetTransformInfo::RGK_FixedWidthVector: 139 if (ST->hasAVX512() && PreferVectorWidth >= 512) 140 return TypeSize::getFixed(512); 141 if (ST->hasAVX() && PreferVectorWidth >= 256) 142 return TypeSize::getFixed(256); 143 if (ST->hasSSE1() && PreferVectorWidth >= 128) 144 return TypeSize::getFixed(128); 145 return TypeSize::getFixed(0); 146 case TargetTransformInfo::RGK_ScalableVector: 147 return TypeSize::getScalable(0); 148 } 149 150 llvm_unreachable("Unsupported register kind"); 151 } 152 153 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 154 return getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector) 155 .getFixedSize(); 156 } 157 158 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 159 // If the loop will not be vectorized, don't interleave the loop. 160 // Let regular unroll to unroll the loop, which saves the overflow 161 // check and memory check cost. 162 if (VF == 1) 163 return 1; 164 165 if (ST->isAtom()) 166 return 1; 167 168 // Sandybridge and Haswell have multiple execution ports and pipelined 169 // vector units. 170 if (ST->hasAVX()) 171 return 4; 172 173 return 2; 174 } 175 176 InstructionCost X86TTIImpl::getArithmeticInstrCost( 177 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, 178 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 179 TTI::OperandValueProperties Opd1PropInfo, 180 TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, 181 const Instruction *CxtI) { 182 // TODO: Handle more cost kinds. 183 if (CostKind != TTI::TCK_RecipThroughput) 184 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, 185 Op2Info, Opd1PropInfo, 186 Opd2PropInfo, Args, CxtI); 187 188 // vXi8 multiplications are always promoted to vXi16. 189 if (Opcode == Instruction::Mul && Ty->isVectorTy() && 190 Ty->getScalarSizeInBits() == 8) { 191 Type *WideVecTy = 192 VectorType::getExtendedElementVectorType(cast<VectorType>(Ty)); 193 return getCastInstrCost(Instruction::ZExt, WideVecTy, Ty, 194 TargetTransformInfo::CastContextHint::None, 195 CostKind) + 196 getCastInstrCost(Instruction::Trunc, Ty, WideVecTy, 197 TargetTransformInfo::CastContextHint::None, 198 CostKind) + 199 getArithmeticInstrCost(Opcode, WideVecTy, CostKind, Op1Info, Op2Info, 200 Opd1PropInfo, Opd2PropInfo); 201 } 202 203 // Legalize the type. 204 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 205 206 int ISD = TLI->InstructionOpcodeToISD(Opcode); 207 assert(ISD && "Invalid opcode"); 208 209 static const CostTblEntry GLMCostTable[] = { 210 { ISD::FDIV, MVT::f32, 18 }, // divss 211 { ISD::FDIV, MVT::v4f32, 35 }, // divps 212 { ISD::FDIV, MVT::f64, 33 }, // divsd 213 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 214 }; 215 216 if (ST->useGLMDivSqrtCosts()) 217 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 218 LT.second)) 219 return LT.first * Entry->Cost; 220 221 static const CostTblEntry SLMCostTable[] = { 222 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 223 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 224 { ISD::FMUL, MVT::f64, 2 }, // mulsd 225 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 226 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 227 { ISD::FDIV, MVT::f32, 17 }, // divss 228 { ISD::FDIV, MVT::v4f32, 39 }, // divps 229 { ISD::FDIV, MVT::f64, 32 }, // divsd 230 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 231 { ISD::FADD, MVT::v2f64, 2 }, // addpd 232 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 233 // v2i64/v4i64 mul is custom lowered as a series of long: 234 // multiplies(3), shifts(3) and adds(2) 235 // slm muldq version throughput is 2 and addq throughput 4 236 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 237 // 3X4 (addq throughput) = 17 238 { ISD::MUL, MVT::v2i64, 17 }, 239 // slm addq\subq throughput is 4 240 { ISD::ADD, MVT::v2i64, 4 }, 241 { ISD::SUB, MVT::v2i64, 4 }, 242 }; 243 244 if (ST->isSLM()) { 245 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 246 // Check if the operands can be shrinked into a smaller datatype. 247 bool Op1Signed = false; 248 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 249 bool Op2Signed = false; 250 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 251 252 bool SignedMode = Op1Signed || Op2Signed; 253 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 254 255 if (OpMinSize <= 7) 256 return LT.first * 3; // pmullw/sext 257 if (!SignedMode && OpMinSize <= 8) 258 return LT.first * 3; // pmullw/zext 259 if (OpMinSize <= 15) 260 return LT.first * 5; // pmullw/pmulhw/pshuf 261 if (!SignedMode && OpMinSize <= 16) 262 return LT.first * 5; // pmullw/pmulhw/pshuf 263 } 264 265 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 266 LT.second)) { 267 return LT.first * Entry->Cost; 268 } 269 } 270 271 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 272 ISD == ISD::UREM) && 273 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 274 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 275 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 276 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 277 // On X86, vector signed division by constants power-of-two are 278 // normally expanded to the sequence SRA + SRL + ADD + SRA. 279 // The OperandValue properties may not be the same as that of the previous 280 // operation; conservatively assume OP_None. 281 InstructionCost Cost = 282 2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Op1Info, 283 Op2Info, TargetTransformInfo::OP_None, 284 TargetTransformInfo::OP_None); 285 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 286 Op2Info, 287 TargetTransformInfo::OP_None, 288 TargetTransformInfo::OP_None); 289 Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind, Op1Info, 290 Op2Info, 291 TargetTransformInfo::OP_None, 292 TargetTransformInfo::OP_None); 293 294 if (ISD == ISD::SREM) { 295 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 296 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info, 297 Op2Info); 298 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info, 299 Op2Info); 300 } 301 302 return Cost; 303 } 304 305 // Vector unsigned division/remainder will be simplified to shifts/masks. 306 if (ISD == ISD::UDIV) 307 return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, 308 Op1Info, Op2Info, 309 TargetTransformInfo::OP_None, 310 TargetTransformInfo::OP_None); 311 312 else // UREM 313 return getArithmeticInstrCost(Instruction::And, Ty, CostKind, 314 Op1Info, Op2Info, 315 TargetTransformInfo::OP_None, 316 TargetTransformInfo::OP_None); 317 } 318 319 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 320 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 321 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 322 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 323 }; 324 325 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 326 ST->hasBWI()) { 327 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 328 LT.second)) 329 return LT.first * Entry->Cost; 330 } 331 332 static const CostTblEntry AVX512UniformConstCostTable[] = { 333 { ISD::SRA, MVT::v2i64, 1 }, 334 { ISD::SRA, MVT::v4i64, 1 }, 335 { ISD::SRA, MVT::v8i64, 1 }, 336 337 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 338 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 339 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 340 341 { ISD::SDIV, MVT::v16i32, 6 }, // pmuludq sequence 342 { ISD::SREM, MVT::v16i32, 8 }, // pmuludq+mul+sub sequence 343 { ISD::UDIV, MVT::v16i32, 5 }, // pmuludq sequence 344 { ISD::UREM, MVT::v16i32, 7 }, // pmuludq+mul+sub sequence 345 }; 346 347 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 348 ST->hasAVX512()) { 349 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 350 LT.second)) 351 return LT.first * Entry->Cost; 352 } 353 354 static const CostTblEntry AVX2UniformConstCostTable[] = { 355 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 356 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 357 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 358 359 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 360 361 { ISD::SDIV, MVT::v8i32, 6 }, // pmuludq sequence 362 { ISD::SREM, MVT::v8i32, 8 }, // pmuludq+mul+sub sequence 363 { ISD::UDIV, MVT::v8i32, 5 }, // pmuludq sequence 364 { ISD::UREM, MVT::v8i32, 7 }, // pmuludq+mul+sub sequence 365 }; 366 367 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 368 ST->hasAVX2()) { 369 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 370 LT.second)) 371 return LT.first * Entry->Cost; 372 } 373 374 static const CostTblEntry SSE2UniformConstCostTable[] = { 375 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 376 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 377 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 378 379 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 380 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 381 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 382 383 { ISD::SDIV, MVT::v8i32, 12+2 }, // 2*pmuludq sequence + split. 384 { ISD::SREM, MVT::v8i32, 16+2 }, // 2*pmuludq+mul+sub sequence + split. 385 { ISD::SDIV, MVT::v4i32, 6 }, // pmuludq sequence 386 { ISD::SREM, MVT::v4i32, 8 }, // pmuludq+mul+sub sequence 387 { ISD::UDIV, MVT::v8i32, 10+2 }, // 2*pmuludq sequence + split. 388 { ISD::UREM, MVT::v8i32, 14+2 }, // 2*pmuludq+mul+sub sequence + split. 389 { ISD::UDIV, MVT::v4i32, 5 }, // pmuludq sequence 390 { ISD::UREM, MVT::v4i32, 7 }, // pmuludq+mul+sub sequence 391 }; 392 393 // XOP has faster vXi8 shifts. 394 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 395 ST->hasSSE2() && !ST->hasXOP()) { 396 if (const auto *Entry = 397 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 398 return LT.first * Entry->Cost; 399 } 400 401 static const CostTblEntry AVX512BWConstCostTable[] = { 402 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 403 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 404 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 405 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 406 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 407 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 408 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 409 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 410 }; 411 412 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 413 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 414 ST->hasBWI()) { 415 if (const auto *Entry = 416 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 417 return LT.first * Entry->Cost; 418 } 419 420 static const CostTblEntry AVX512ConstCostTable[] = { 421 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 422 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 423 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 424 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 425 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 426 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 427 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 428 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 429 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 430 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 431 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 432 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 433 }; 434 435 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 436 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 437 ST->hasAVX512()) { 438 if (const auto *Entry = 439 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 440 return LT.first * Entry->Cost; 441 } 442 443 static const CostTblEntry AVX2ConstCostTable[] = { 444 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 445 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 446 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 447 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 448 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 449 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 450 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 451 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 452 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 453 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 454 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 455 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 456 }; 457 458 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 459 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 460 ST->hasAVX2()) { 461 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 462 return LT.first * Entry->Cost; 463 } 464 465 static const CostTblEntry SSE2ConstCostTable[] = { 466 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 467 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 468 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 469 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 470 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 471 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 472 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 473 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 474 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 475 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 476 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 477 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 478 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 479 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 480 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 481 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 482 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 483 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 484 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 485 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 486 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 487 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 488 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 489 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 490 }; 491 492 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 493 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 494 ST->hasSSE2()) { 495 // pmuldq sequence. 496 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 497 return LT.first * 32; 498 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 499 return LT.first * 38; 500 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 501 return LT.first * 15; 502 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 503 return LT.first * 20; 504 505 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 506 return LT.first * Entry->Cost; 507 } 508 509 static const CostTblEntry AVX512BWShiftCostTable[] = { 510 { ISD::SHL, MVT::v16i8, 4 }, // extend/vpsllvw/pack sequence. 511 { ISD::SRL, MVT::v16i8, 4 }, // extend/vpsrlvw/pack sequence. 512 { ISD::SRA, MVT::v16i8, 4 }, // extend/vpsravw/pack sequence. 513 { ISD::SHL, MVT::v32i8, 4 }, // extend/vpsllvw/pack sequence. 514 { ISD::SRL, MVT::v32i8, 4 }, // extend/vpsrlvw/pack sequence. 515 { ISD::SRA, MVT::v32i8, 6 }, // extend/vpsravw/pack sequence. 516 { ISD::SHL, MVT::v64i8, 6 }, // extend/vpsllvw/pack sequence. 517 { ISD::SRL, MVT::v64i8, 7 }, // extend/vpsrlvw/pack sequence. 518 { ISD::SRA, MVT::v64i8, 15 }, // extend/vpsravw/pack sequence. 519 520 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 521 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 522 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 523 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 524 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 525 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 526 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 527 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 528 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 529 }; 530 531 if (ST->hasBWI()) 532 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 533 return LT.first * Entry->Cost; 534 535 static const CostTblEntry AVX2UniformCostTable[] = { 536 // Uniform splats are cheaper for the following instructions. 537 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 538 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 539 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 540 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 541 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 542 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 543 544 { ISD::SHL, MVT::v8i32, 1 }, // pslld 545 { ISD::SRL, MVT::v8i32, 1 }, // psrld 546 { ISD::SRA, MVT::v8i32, 1 }, // psrad 547 { ISD::SHL, MVT::v4i64, 1 }, // psllq 548 { ISD::SRL, MVT::v4i64, 1 }, // psrlq 549 }; 550 551 if (ST->hasAVX2() && 552 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 553 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 554 if (const auto *Entry = 555 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 556 return LT.first * Entry->Cost; 557 } 558 559 static const CostTblEntry SSE2UniformCostTable[] = { 560 // Uniform splats are cheaper for the following instructions. 561 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 562 { ISD::SHL, MVT::v4i32, 1 }, // pslld 563 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 564 565 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 566 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 567 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 568 569 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 570 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 571 }; 572 573 if (ST->hasSSE2() && 574 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 575 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 576 if (const auto *Entry = 577 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 578 return LT.first * Entry->Cost; 579 } 580 581 static const CostTblEntry AVX512DQCostTable[] = { 582 { ISD::MUL, MVT::v2i64, 2 }, // pmullq 583 { ISD::MUL, MVT::v4i64, 2 }, // pmullq 584 { ISD::MUL, MVT::v8i64, 2 } // pmullq 585 }; 586 587 // Look for AVX512DQ lowering tricks for custom cases. 588 if (ST->hasDQI()) 589 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 590 return LT.first * Entry->Cost; 591 592 static const CostTblEntry AVX512BWCostTable[] = { 593 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 594 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 595 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 596 }; 597 598 // Look for AVX512BW lowering tricks for custom cases. 599 if (ST->hasBWI()) 600 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 601 return LT.first * Entry->Cost; 602 603 static const CostTblEntry AVX512CostTable[] = { 604 { ISD::SHL, MVT::v4i32, 1 }, 605 { ISD::SRL, MVT::v4i32, 1 }, 606 { ISD::SRA, MVT::v4i32, 1 }, 607 { ISD::SHL, MVT::v8i32, 1 }, 608 { ISD::SRL, MVT::v8i32, 1 }, 609 { ISD::SRA, MVT::v8i32, 1 }, 610 { ISD::SHL, MVT::v16i32, 1 }, 611 { ISD::SRL, MVT::v16i32, 1 }, 612 { ISD::SRA, MVT::v16i32, 1 }, 613 614 { ISD::SHL, MVT::v2i64, 1 }, 615 { ISD::SRL, MVT::v2i64, 1 }, 616 { ISD::SHL, MVT::v4i64, 1 }, 617 { ISD::SRL, MVT::v4i64, 1 }, 618 { ISD::SHL, MVT::v8i64, 1 }, 619 { ISD::SRL, MVT::v8i64, 1 }, 620 621 { ISD::SRA, MVT::v2i64, 1 }, 622 { ISD::SRA, MVT::v4i64, 1 }, 623 { ISD::SRA, MVT::v8i64, 1 }, 624 625 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 626 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 627 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 628 { ISD::MUL, MVT::v8i64, 6 }, // 3*pmuludq/3*shift/2*add 629 630 { ISD::FNEG, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 631 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 632 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 633 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 634 { ISD::FDIV, MVT::f64, 4 }, // Skylake from http://www.agner.org/ 635 { ISD::FDIV, MVT::v2f64, 4 }, // Skylake from http://www.agner.org/ 636 { ISD::FDIV, MVT::v4f64, 8 }, // Skylake from http://www.agner.org/ 637 { ISD::FDIV, MVT::v8f64, 16 }, // Skylake from http://www.agner.org/ 638 639 { ISD::FNEG, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 640 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 641 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 642 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 643 { ISD::FDIV, MVT::f32, 3 }, // Skylake from http://www.agner.org/ 644 { ISD::FDIV, MVT::v4f32, 3 }, // Skylake from http://www.agner.org/ 645 { ISD::FDIV, MVT::v8f32, 5 }, // Skylake from http://www.agner.org/ 646 { ISD::FDIV, MVT::v16f32, 10 }, // Skylake from http://www.agner.org/ 647 }; 648 649 if (ST->hasAVX512()) 650 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 651 return LT.first * Entry->Cost; 652 653 static const CostTblEntry AVX2ShiftCostTable[] = { 654 // Shifts on vXi64/vXi32 on AVX2 is legal even though we declare to 655 // customize them to detect the cases where shift amount is a scalar one. 656 { ISD::SHL, MVT::v4i32, 2 }, // vpsllvd (Haswell from agner.org) 657 { ISD::SRL, MVT::v4i32, 2 }, // vpsrlvd (Haswell from agner.org) 658 { ISD::SRA, MVT::v4i32, 2 }, // vpsravd (Haswell from agner.org) 659 { ISD::SHL, MVT::v8i32, 2 }, // vpsllvd (Haswell from agner.org) 660 { ISD::SRL, MVT::v8i32, 2 }, // vpsrlvd (Haswell from agner.org) 661 { ISD::SRA, MVT::v8i32, 2 }, // vpsravd (Haswell from agner.org) 662 { ISD::SHL, MVT::v2i64, 1 }, // vpsllvq (Haswell from agner.org) 663 { ISD::SRL, MVT::v2i64, 1 }, // vpsrlvq (Haswell from agner.org) 664 { ISD::SHL, MVT::v4i64, 1 }, // vpsllvq (Haswell from agner.org) 665 { ISD::SRL, MVT::v4i64, 1 }, // vpsrlvq (Haswell from agner.org) 666 }; 667 668 if (ST->hasAVX512()) { 669 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 670 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 671 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 672 // On AVX512, a packed v32i16 shift left by a constant build_vector 673 // is lowered into a vector multiply (vpmullw). 674 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 675 Op1Info, Op2Info, 676 TargetTransformInfo::OP_None, 677 TargetTransformInfo::OP_None); 678 } 679 680 // Look for AVX2 lowering tricks (XOP is always better at v4i32 shifts). 681 if (ST->hasAVX2() && !(ST->hasXOP() && LT.second == MVT::v4i32)) { 682 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 683 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 684 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 685 // On AVX2, a packed v16i16 shift left by a constant build_vector 686 // is lowered into a vector multiply (vpmullw). 687 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 688 Op1Info, Op2Info, 689 TargetTransformInfo::OP_None, 690 TargetTransformInfo::OP_None); 691 692 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 693 return LT.first * Entry->Cost; 694 } 695 696 static const CostTblEntry XOPShiftCostTable[] = { 697 // 128bit shifts take 1cy, but right shifts require negation beforehand. 698 { ISD::SHL, MVT::v16i8, 1 }, 699 { ISD::SRL, MVT::v16i8, 2 }, 700 { ISD::SRA, MVT::v16i8, 2 }, 701 { ISD::SHL, MVT::v8i16, 1 }, 702 { ISD::SRL, MVT::v8i16, 2 }, 703 { ISD::SRA, MVT::v8i16, 2 }, 704 { ISD::SHL, MVT::v4i32, 1 }, 705 { ISD::SRL, MVT::v4i32, 2 }, 706 { ISD::SRA, MVT::v4i32, 2 }, 707 { ISD::SHL, MVT::v2i64, 1 }, 708 { ISD::SRL, MVT::v2i64, 2 }, 709 { ISD::SRA, MVT::v2i64, 2 }, 710 // 256bit shifts require splitting if AVX2 didn't catch them above. 711 { ISD::SHL, MVT::v32i8, 2+2 }, 712 { ISD::SRL, MVT::v32i8, 4+2 }, 713 { ISD::SRA, MVT::v32i8, 4+2 }, 714 { ISD::SHL, MVT::v16i16, 2+2 }, 715 { ISD::SRL, MVT::v16i16, 4+2 }, 716 { ISD::SRA, MVT::v16i16, 4+2 }, 717 { ISD::SHL, MVT::v8i32, 2+2 }, 718 { ISD::SRL, MVT::v8i32, 4+2 }, 719 { ISD::SRA, MVT::v8i32, 4+2 }, 720 { ISD::SHL, MVT::v4i64, 2+2 }, 721 { ISD::SRL, MVT::v4i64, 4+2 }, 722 { ISD::SRA, MVT::v4i64, 4+2 }, 723 }; 724 725 // Look for XOP lowering tricks. 726 if (ST->hasXOP()) { 727 // If the right shift is constant then we'll fold the negation so 728 // it's as cheap as a left shift. 729 int ShiftISD = ISD; 730 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 731 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 732 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 733 ShiftISD = ISD::SHL; 734 if (const auto *Entry = 735 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 736 return LT.first * Entry->Cost; 737 } 738 739 static const CostTblEntry SSE2UniformShiftCostTable[] = { 740 // Uniform splats are cheaper for the following instructions. 741 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 742 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 743 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 744 745 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 746 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 747 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 748 749 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 750 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 751 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 752 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 753 }; 754 755 if (ST->hasSSE2() && 756 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 757 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 758 759 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 760 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 761 return LT.first * 4; // 2*psrad + shuffle. 762 763 if (const auto *Entry = 764 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 765 return LT.first * Entry->Cost; 766 } 767 768 if (ISD == ISD::SHL && 769 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 770 MVT VT = LT.second; 771 // Vector shift left by non uniform constant can be lowered 772 // into vector multiply. 773 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 774 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 775 ISD = ISD::MUL; 776 } 777 778 static const CostTblEntry AVX2CostTable[] = { 779 { ISD::SHL, MVT::v16i8, 6 }, // vpblendvb sequence. 780 { ISD::SHL, MVT::v32i8, 6 }, // vpblendvb sequence. 781 { ISD::SHL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 782 { ISD::SHL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 783 { ISD::SHL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 784 { ISD::SHL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 785 786 { ISD::SRL, MVT::v16i8, 6 }, // vpblendvb sequence. 787 { ISD::SRL, MVT::v32i8, 6 }, // vpblendvb sequence. 788 { ISD::SRL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 789 { ISD::SRL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 790 { ISD::SRL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 791 { ISD::SRL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 792 793 { ISD::SRA, MVT::v16i8, 17 }, // vpblendvb sequence. 794 { ISD::SRA, MVT::v32i8, 17 }, // vpblendvb sequence. 795 { ISD::SRA, MVT::v64i8, 34 }, // 2*vpblendvb sequence. 796 { ISD::SRA, MVT::v8i16, 5 }, // extend/vpsravd/pack sequence. 797 { ISD::SRA, MVT::v16i16, 7 }, // extend/vpsravd/pack sequence. 798 { ISD::SRA, MVT::v32i16, 14 }, // 2*extend/vpsravd/pack sequence. 799 { ISD::SRA, MVT::v2i64, 2 }, // srl/xor/sub sequence. 800 { ISD::SRA, MVT::v4i64, 2 }, // srl/xor/sub sequence. 801 802 { ISD::SUB, MVT::v32i8, 1 }, // psubb 803 { ISD::ADD, MVT::v32i8, 1 }, // paddb 804 { ISD::SUB, MVT::v16i16, 1 }, // psubw 805 { ISD::ADD, MVT::v16i16, 1 }, // paddw 806 { ISD::SUB, MVT::v8i32, 1 }, // psubd 807 { ISD::ADD, MVT::v8i32, 1 }, // paddd 808 { ISD::SUB, MVT::v4i64, 1 }, // psubq 809 { ISD::ADD, MVT::v4i64, 1 }, // paddq 810 811 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 812 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 813 { ISD::MUL, MVT::v4i64, 6 }, // 3*pmuludq/3*shift/2*add 814 815 { ISD::FNEG, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 816 { ISD::FNEG, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 817 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 818 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 819 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 820 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 821 { ISD::FMUL, MVT::f64, 1 }, // Haswell from http://www.agner.org/ 822 { ISD::FMUL, MVT::v2f64, 1 }, // Haswell from http://www.agner.org/ 823 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 824 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 825 826 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 827 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 828 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 829 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 830 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 831 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 832 }; 833 834 // Look for AVX2 lowering tricks for custom cases. 835 if (ST->hasAVX2()) 836 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 837 return LT.first * Entry->Cost; 838 839 static const CostTblEntry AVX1CostTable[] = { 840 // We don't have to scalarize unsupported ops. We can issue two half-sized 841 // operations and we only need to extract the upper YMM half. 842 // Two ops + 1 extract + 1 insert = 4. 843 { ISD::MUL, MVT::v16i16, 4 }, 844 { ISD::MUL, MVT::v8i32, 5 }, // BTVER2 from http://www.agner.org/ 845 { ISD::MUL, MVT::v4i64, 12 }, 846 847 { ISD::SUB, MVT::v32i8, 4 }, 848 { ISD::ADD, MVT::v32i8, 4 }, 849 { ISD::SUB, MVT::v16i16, 4 }, 850 { ISD::ADD, MVT::v16i16, 4 }, 851 { ISD::SUB, MVT::v8i32, 4 }, 852 { ISD::ADD, MVT::v8i32, 4 }, 853 { ISD::SUB, MVT::v4i64, 4 }, 854 { ISD::ADD, MVT::v4i64, 4 }, 855 856 { ISD::SHL, MVT::v16i8, 10 }, // pblendvb sequence . 857 { ISD::SHL, MVT::v32i8, 22 }, // pblendvb sequence + split. 858 { ISD::SHL, MVT::v8i16, 6 }, // pblendvb sequence. 859 { ISD::SHL, MVT::v16i16, 13 }, // pblendvb sequence + split. 860 { ISD::SHL, MVT::v4i32, 3 }, // pslld/paddd/cvttps2dq/pmulld 861 { ISD::SHL, MVT::v8i32, 9 }, // pslld/paddd/cvttps2dq/pmulld + split 862 { ISD::SHL, MVT::v2i64, 2 }, // Shift each lane + blend. 863 { ISD::SHL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 864 865 { ISD::SRL, MVT::v16i8, 11 }, // pblendvb sequence. 866 { ISD::SRL, MVT::v32i8, 23 }, // pblendvb sequence + split. 867 { ISD::SRL, MVT::v8i16, 13 }, // pblendvb sequence. 868 { ISD::SRL, MVT::v16i16, 28 }, // pblendvb sequence + split. 869 { ISD::SRL, MVT::v4i32, 6 }, // Shift each lane + blend. 870 { ISD::SRL, MVT::v8i32, 14 }, // Shift each lane + blend + split. 871 { ISD::SRL, MVT::v2i64, 2 }, // Shift each lane + blend. 872 { ISD::SRL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 873 874 { ISD::SRA, MVT::v16i8, 21 }, // pblendvb sequence. 875 { ISD::SRA, MVT::v32i8, 44 }, // pblendvb sequence + split. 876 { ISD::SRA, MVT::v8i16, 13 }, // pblendvb sequence. 877 { ISD::SRA, MVT::v16i16, 28 }, // pblendvb sequence + split. 878 { ISD::SRA, MVT::v4i32, 6 }, // Shift each lane + blend. 879 { ISD::SRA, MVT::v8i32, 14 }, // Shift each lane + blend + split. 880 { ISD::SRA, MVT::v2i64, 5 }, // Shift each lane + blend. 881 { ISD::SRA, MVT::v4i64, 12 }, // Shift each lane + blend + split. 882 883 { ISD::FNEG, MVT::v4f64, 2 }, // BTVER2 from http://www.agner.org/ 884 { ISD::FNEG, MVT::v8f32, 2 }, // BTVER2 from http://www.agner.org/ 885 886 { ISD::FMUL, MVT::f64, 2 }, // BTVER2 from http://www.agner.org/ 887 { ISD::FMUL, MVT::v2f64, 2 }, // BTVER2 from http://www.agner.org/ 888 { ISD::FMUL, MVT::v4f64, 4 }, // BTVER2 from http://www.agner.org/ 889 890 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 891 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 892 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 893 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 894 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 895 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 896 }; 897 898 if (ST->hasAVX()) 899 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 900 return LT.first * Entry->Cost; 901 902 static const CostTblEntry SSE42CostTable[] = { 903 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 904 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 905 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 906 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 907 908 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 909 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 910 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 911 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 912 913 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 914 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 915 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 916 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 917 918 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 919 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 920 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 921 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 922 923 { ISD::MUL, MVT::v2i64, 6 } // 3*pmuludq/3*shift/2*add 924 }; 925 926 if (ST->hasSSE42()) 927 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 928 return LT.first * Entry->Cost; 929 930 static const CostTblEntry SSE41CostTable[] = { 931 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 932 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 933 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 934 935 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 936 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 937 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 938 939 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 940 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 941 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 942 943 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 944 }; 945 946 if (ST->hasSSE41()) 947 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 948 return LT.first * Entry->Cost; 949 950 static const CostTblEntry SSE2CostTable[] = { 951 // We don't correctly identify costs of casts because they are marked as 952 // custom. 953 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 954 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 955 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 956 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 957 958 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 959 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 960 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 961 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 962 963 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 964 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 965 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 966 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 967 968 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 969 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 970 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 971 972 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 973 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 974 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 975 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 976 977 { ISD::FNEG, MVT::f32, 1 }, // Pentium IV from http://www.agner.org/ 978 { ISD::FNEG, MVT::f64, 1 }, // Pentium IV from http://www.agner.org/ 979 { ISD::FNEG, MVT::v4f32, 1 }, // Pentium IV from http://www.agner.org/ 980 { ISD::FNEG, MVT::v2f64, 1 }, // Pentium IV from http://www.agner.org/ 981 982 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 983 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 984 985 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 986 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 987 }; 988 989 if (ST->hasSSE2()) 990 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 991 return LT.first * Entry->Cost; 992 993 static const CostTblEntry SSE1CostTable[] = { 994 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 995 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 996 997 { ISD::FNEG, MVT::f32, 2 }, // Pentium III from http://www.agner.org/ 998 { ISD::FNEG, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 999 1000 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1001 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1002 1003 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1004 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1005 }; 1006 1007 if (ST->hasSSE1()) 1008 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 1009 return LT.first * Entry->Cost; 1010 1011 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 1012 { ISD::ADD, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1013 { ISD::SUB, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1014 }; 1015 1016 if (ST->is64Bit()) 1017 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, LT.second)) 1018 return LT.first * Entry->Cost; 1019 1020 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 1021 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1022 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1023 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1024 1025 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1026 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1027 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1028 }; 1029 1030 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, LT.second)) 1031 return LT.first * Entry->Cost; 1032 1033 // It is not a good idea to vectorize division. We have to scalarize it and 1034 // in the process we will often end up having to spilling regular 1035 // registers. The overhead of division is going to dominate most kernels 1036 // anyways so try hard to prevent vectorization of division - it is 1037 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 1038 // to hide "20 cycles" for each lane. 1039 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 1040 ISD == ISD::UDIV || ISD == ISD::UREM)) { 1041 InstructionCost ScalarCost = getArithmeticInstrCost( 1042 Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info, 1043 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 1044 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 1045 } 1046 1047 // Fallback to the default implementation. 1048 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info); 1049 } 1050 1051 InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, 1052 VectorType *BaseTp, 1053 ArrayRef<int> Mask, int Index, 1054 VectorType *SubTp) { 1055 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 1056 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 1057 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 1058 1059 Kind = improveShuffleKindFromMask(Kind, Mask); 1060 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 1061 if (Kind == TTI::SK_Transpose) 1062 Kind = TTI::SK_PermuteTwoSrc; 1063 1064 // For Broadcasts we are splatting the first element from the first input 1065 // register, so only need to reference that input and all the output 1066 // registers are the same. 1067 if (Kind == TTI::SK_Broadcast) 1068 LT.first = 1; 1069 1070 // Subvector extractions are free if they start at the beginning of a 1071 // vector and cheap if the subvectors are aligned. 1072 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 1073 int NumElts = LT.second.getVectorNumElements(); 1074 if ((Index % NumElts) == 0) 1075 return 0; 1076 std::pair<InstructionCost, MVT> SubLT = 1077 TLI->getTypeLegalizationCost(DL, SubTp); 1078 if (SubLT.second.isVector()) { 1079 int NumSubElts = SubLT.second.getVectorNumElements(); 1080 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1081 return SubLT.first; 1082 // Handle some cases for widening legalization. For now we only handle 1083 // cases where the original subvector was naturally aligned and evenly 1084 // fit in its legalized subvector type. 1085 // FIXME: Remove some of the alignment restrictions. 1086 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 1087 // vectors. 1088 int OrigSubElts = cast<FixedVectorType>(SubTp)->getNumElements(); 1089 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 1090 (NumSubElts % OrigSubElts) == 0 && 1091 LT.second.getVectorElementType() == 1092 SubLT.second.getVectorElementType() && 1093 LT.second.getVectorElementType().getSizeInBits() == 1094 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 1095 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 1096 "Unexpected number of elements!"); 1097 auto *VecTy = FixedVectorType::get(BaseTp->getElementType(), 1098 LT.second.getVectorNumElements()); 1099 auto *SubTy = FixedVectorType::get(BaseTp->getElementType(), 1100 SubLT.second.getVectorNumElements()); 1101 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 1102 InstructionCost ExtractCost = getShuffleCost( 1103 TTI::SK_ExtractSubvector, VecTy, None, ExtractIndex, SubTy); 1104 1105 // If the original size is 32-bits or more, we can use pshufd. Otherwise 1106 // if we have SSSE3 we can use pshufb. 1107 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 1108 return ExtractCost + 1; // pshufd or pshufb 1109 1110 assert(SubTp->getPrimitiveSizeInBits() == 16 && 1111 "Unexpected vector size"); 1112 1113 return ExtractCost + 2; // worst case pshufhw + pshufd 1114 } 1115 } 1116 } 1117 1118 // Subvector insertions are cheap if the subvectors are aligned. 1119 // Note that in general, the insertion starting at the beginning of a vector 1120 // isn't free, because we need to preserve the rest of the wide vector. 1121 if (Kind == TTI::SK_InsertSubvector && LT.second.isVector()) { 1122 int NumElts = LT.second.getVectorNumElements(); 1123 std::pair<InstructionCost, MVT> SubLT = 1124 TLI->getTypeLegalizationCost(DL, SubTp); 1125 if (SubLT.second.isVector()) { 1126 int NumSubElts = SubLT.second.getVectorNumElements(); 1127 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1128 return SubLT.first; 1129 } 1130 } 1131 1132 // Handle some common (illegal) sub-vector types as they are often very cheap 1133 // to shuffle even on targets without PSHUFB. 1134 EVT VT = TLI->getValueType(DL, BaseTp); 1135 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 1136 !ST->hasSSSE3()) { 1137 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 1138 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 1139 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1140 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1141 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1142 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1143 1144 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1145 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1146 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1147 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1148 1149 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1150 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1151 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1152 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1153 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1154 1155 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1156 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1157 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1158 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1159 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1160 }; 1161 1162 if (ST->hasSSE2()) 1163 if (const auto *Entry = 1164 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1165 return Entry->Cost; 1166 } 1167 1168 // We are going to permute multiple sources and the result will be in multiple 1169 // destinations. Providing an accurate cost only for splits where the element 1170 // type remains the same. 1171 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1172 MVT LegalVT = LT.second; 1173 if (LegalVT.isVector() && 1174 LegalVT.getVectorElementType().getSizeInBits() == 1175 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1176 LegalVT.getVectorNumElements() < 1177 cast<FixedVectorType>(BaseTp)->getNumElements()) { 1178 1179 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1180 unsigned LegalVTSize = LegalVT.getStoreSize(); 1181 // Number of source vectors after legalization: 1182 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1183 // Number of destination vectors after legalization: 1184 InstructionCost NumOfDests = LT.first; 1185 1186 auto *SingleOpTy = FixedVectorType::get(BaseTp->getElementType(), 1187 LegalVT.getVectorNumElements()); 1188 1189 InstructionCost NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1190 return NumOfShuffles * getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 1191 None, 0, nullptr); 1192 } 1193 1194 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1195 } 1196 1197 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1198 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1199 // We assume that source and destination have the same vector type. 1200 InstructionCost NumOfDests = LT.first; 1201 InstructionCost NumOfShufflesPerDest = LT.first * 2 - 1; 1202 LT.first = NumOfDests * NumOfShufflesPerDest; 1203 } 1204 1205 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1206 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1207 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1208 1209 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1210 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1211 1212 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b 1213 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b 1214 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2} // vpermt2b 1215 }; 1216 1217 if (ST->hasVBMI()) 1218 if (const auto *Entry = 1219 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1220 return LT.first * Entry->Cost; 1221 1222 static const CostTblEntry AVX512BWShuffleTbl[] = { 1223 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1224 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1225 1226 {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw 1227 {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw 1228 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1229 1230 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw 1231 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw 1232 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1233 1234 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w 1235 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w 1236 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2}, // vpermt2w 1237 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1238 1239 {TTI::SK_Select, MVT::v32i16, 1}, // vblendmw 1240 {TTI::SK_Select, MVT::v64i8, 1}, // vblendmb 1241 }; 1242 1243 if (ST->hasBWI()) 1244 if (const auto *Entry = 1245 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1246 return LT.first * Entry->Cost; 1247 1248 static const CostTblEntry AVX512ShuffleTbl[] = { 1249 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1250 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1251 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1252 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1253 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1254 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1255 1256 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1257 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1258 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1259 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1260 {TTI::SK_Reverse, MVT::v32i16, 7}, // per mca 1261 {TTI::SK_Reverse, MVT::v64i8, 7}, // per mca 1262 1263 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1264 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1265 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1266 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1267 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1268 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1269 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1270 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1271 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1272 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1273 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1274 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1275 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1276 1277 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1278 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1279 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1280 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1281 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1282 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1283 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1284 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1285 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1286 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1287 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1288 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1289 1290 // FIXME: This just applies the type legalization cost rules above 1291 // assuming these completely split. 1292 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1293 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1294 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1295 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1296 1297 {TTI::SK_Select, MVT::v32i16, 1}, // vpternlogq 1298 {TTI::SK_Select, MVT::v64i8, 1}, // vpternlogq 1299 {TTI::SK_Select, MVT::v8f64, 1}, // vblendmpd 1300 {TTI::SK_Select, MVT::v16f32, 1}, // vblendmps 1301 {TTI::SK_Select, MVT::v8i64, 1}, // vblendmq 1302 {TTI::SK_Select, MVT::v16i32, 1}, // vblendmd 1303 }; 1304 1305 if (ST->hasAVX512()) 1306 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1307 return LT.first * Entry->Cost; 1308 1309 static const CostTblEntry AVX2ShuffleTbl[] = { 1310 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1311 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1312 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1313 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1314 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1315 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1316 1317 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1318 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1319 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1320 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1321 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1322 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1323 1324 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1325 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1326 1327 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1328 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1329 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1330 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1331 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1332 // + vpblendvb 1333 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1334 // + vpblendvb 1335 1336 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1337 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1338 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1339 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1340 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1341 // + vpblendvb 1342 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1343 // + vpblendvb 1344 }; 1345 1346 if (ST->hasAVX2()) 1347 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1348 return LT.first * Entry->Cost; 1349 1350 static const CostTblEntry XOPShuffleTbl[] = { 1351 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1352 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1353 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1354 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1355 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1356 // + vinsertf128 1357 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1358 // + vinsertf128 1359 1360 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1361 // + vinsertf128 1362 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1363 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1364 // + vinsertf128 1365 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1366 }; 1367 1368 if (ST->hasXOP()) 1369 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1370 return LT.first * Entry->Cost; 1371 1372 static const CostTblEntry AVX1ShuffleTbl[] = { 1373 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1374 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1375 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1376 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1377 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1378 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1379 1380 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1381 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1382 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1383 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1384 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1385 // + vinsertf128 1386 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1387 // + vinsertf128 1388 1389 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1390 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1391 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1392 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1393 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1394 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1395 1396 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1397 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1398 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1399 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1400 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1401 // + 2*por + vinsertf128 1402 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1403 // + 2*por + vinsertf128 1404 1405 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1406 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1407 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1408 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1409 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1410 // + 4*por + vinsertf128 1411 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1412 // + 4*por + vinsertf128 1413 }; 1414 1415 if (ST->hasAVX()) 1416 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1417 return LT.first * Entry->Cost; 1418 1419 static const CostTblEntry SSE41ShuffleTbl[] = { 1420 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1421 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1422 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1423 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1424 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1425 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1426 }; 1427 1428 if (ST->hasSSE41()) 1429 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1430 return LT.first * Entry->Cost; 1431 1432 static const CostTblEntry SSSE3ShuffleTbl[] = { 1433 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1434 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1435 1436 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1437 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1438 1439 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1440 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1441 1442 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1443 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1444 1445 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1446 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1447 }; 1448 1449 if (ST->hasSSSE3()) 1450 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1451 return LT.first * Entry->Cost; 1452 1453 static const CostTblEntry SSE2ShuffleTbl[] = { 1454 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1455 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1456 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1457 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1458 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1459 1460 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1461 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1462 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1463 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1464 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1465 // + 2*pshufd + 2*unpck + packus 1466 1467 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1468 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1469 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1470 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1471 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1472 1473 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1474 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1475 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1476 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1477 // + pshufd/unpck 1478 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1479 // + 2*pshufd + 2*unpck + 2*packus 1480 1481 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1482 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1483 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1484 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1485 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1486 }; 1487 1488 if (ST->hasSSE2()) 1489 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1490 return LT.first * Entry->Cost; 1491 1492 static const CostTblEntry SSE1ShuffleTbl[] = { 1493 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1494 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1495 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1496 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1497 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1498 }; 1499 1500 if (ST->hasSSE1()) 1501 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1502 return LT.first * Entry->Cost; 1503 1504 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1505 } 1506 1507 InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, 1508 Type *Src, 1509 TTI::CastContextHint CCH, 1510 TTI::TargetCostKind CostKind, 1511 const Instruction *I) { 1512 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1513 assert(ISD && "Invalid opcode"); 1514 1515 // TODO: Allow non-throughput costs that aren't binary. 1516 auto AdjustCost = [&CostKind](InstructionCost Cost) -> InstructionCost { 1517 if (CostKind != TTI::TCK_RecipThroughput) 1518 return Cost == 0 ? 0 : 1; 1519 return Cost; 1520 }; 1521 1522 // The cost tables include both specific, custom (non-legal) src/dst type 1523 // conversions and generic, legalized types. We test for customs first, before 1524 // falling back to legalization. 1525 // FIXME: Need a better design of the cost table to handle non-simple types of 1526 // potential massive combinations (elem_num x src_type x dst_type). 1527 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1528 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1529 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1530 1531 // Mask sign extend has an instruction. 1532 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1533 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1534 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1535 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1536 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1537 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1538 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1539 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1540 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1541 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1542 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1543 1544 // Mask zero extend is a sext + shift. 1545 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1546 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1547 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1548 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1549 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1550 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1551 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1552 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1553 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1554 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1555 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1556 1557 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, 1558 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm 1559 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // widen to zmm 1560 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // widen to zmm 1561 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // vpmovwb 1562 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // widen to zmm 1563 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // widen to zmm 1564 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // vpmovwb 1565 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // widen to zmm 1566 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // widen to zmm 1567 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // vpmovwb 1568 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // widen to zmm 1569 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // widen to zmm 1570 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // widen to zmm 1571 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, 1572 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, 1573 }; 1574 1575 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1576 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1577 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1578 1579 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1580 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1581 1582 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1583 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1584 1585 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1586 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1587 }; 1588 1589 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1590 // 256-bit wide vectors. 1591 1592 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1593 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1594 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1595 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1596 1597 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1598 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1599 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1600 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd 1601 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1602 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1603 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1604 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd 1605 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd 1606 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd 1607 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd 1608 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd 1609 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq 1610 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq 1611 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq 1612 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 2 }, // vpmovdb 1613 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 2 }, // vpmovdb 1614 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, // vpmovdb 1615 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, // vpmovdb 1616 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 2 }, // vpmovqb 1617 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 1 }, // vpshufb 1618 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, // vpmovqb 1619 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, // vpmovqw 1620 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, // vpmovqd 1621 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd 1622 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb 1623 1624 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32 1625 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, 1626 1627 // Sign extend is zmm vpternlogd+vptruncdb. 1628 // Zero extend is zmm broadcast load+vptruncdw. 1629 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 }, 1630 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 }, 1631 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, 1632 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, 1633 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, 1634 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, 1635 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 }, 1636 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 }, 1637 1638 // Sign extend is zmm vpternlogd+vptruncdw. 1639 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw. 1640 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 }, 1641 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1642 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 }, 1643 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1644 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 }, 1645 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1646 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 }, 1647 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1648 1649 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd 1650 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld 1651 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd 1652 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld 1653 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd 1654 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld 1655 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq 1656 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq 1657 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq 1658 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq 1659 1660 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd 1661 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld 1662 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq 1663 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq 1664 1665 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1666 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1667 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1668 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1669 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1670 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1671 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1672 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1673 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1674 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1675 1676 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1677 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1678 1679 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1680 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1681 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1682 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1683 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1684 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1685 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1686 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1687 1688 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1689 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1690 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1691 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1692 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1693 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1694 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1695 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1696 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1697 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1698 1699 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f64, 3 }, 1700 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, 1701 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 1 }, 1702 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 3 }, 1703 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 3 }, 1704 { ISD::FP_TO_SINT, MVT::v16i32, MVT::v16f64, 3 }, 1705 1706 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1707 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, 1708 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, 1709 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1710 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, 1711 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, 1712 }; 1713 1714 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1715 // Mask sign extend has an instruction. 1716 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1717 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1718 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1719 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1720 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1721 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1722 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1723 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1724 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1725 1726 // Mask zero extend is a sext + shift. 1727 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1728 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1729 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1730 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1731 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1732 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1733 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1734 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1735 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1736 1737 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, 1738 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // vpsllw+vptestmb 1739 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // vpsllw+vptestmw 1740 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // vpsllw+vptestmb 1741 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // vpsllw+vptestmw 1742 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // vpsllw+vptestmb 1743 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // vpsllw+vptestmw 1744 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // vpsllw+vptestmb 1745 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // vpsllw+vptestmw 1746 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // vpsllw+vptestmb 1747 }; 1748 1749 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1750 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1751 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1752 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1753 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1754 1755 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1756 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1757 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1758 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1759 1760 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1761 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1762 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1763 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1764 1765 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1766 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1767 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1768 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1769 }; 1770 1771 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 1772 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1773 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1774 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1775 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 8 }, // split+2*v8i8 1776 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1777 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1778 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1779 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16 1780 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // vpslld+vptestmd 1781 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd 1782 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // vpslld+vptestmd 1783 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // vpsllq+vptestmq 1784 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // vpsllq+vptestmq 1785 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // vpmovqd 1786 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, // vpmovqb 1787 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, // vpmovqw 1788 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, // vpmovwb 1789 1790 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb 1791 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb 1792 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 }, 1793 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 }, 1794 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 }, 1795 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 }, 1796 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 }, 1797 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 }, 1798 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 }, 1799 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 }, 1800 1801 // sign extend is vpcmpeq+maskedmove+vpmovdw 1802 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw 1803 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1804 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 }, 1805 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1806 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 }, 1807 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1808 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 }, 1809 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 }, 1810 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 }, 1811 1812 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd 1813 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld 1814 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd 1815 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld 1816 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd 1817 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld 1818 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq 1819 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq 1820 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq 1821 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq 1822 1823 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1824 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1825 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1826 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1827 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1828 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1829 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 1830 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1831 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1832 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1833 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1834 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1835 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1836 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1837 1838 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 1839 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1840 1841 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 3 }, 1842 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 3 }, 1843 1844 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 1845 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 1846 1847 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1848 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1849 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 1 }, 1850 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1851 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1852 }; 1853 1854 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1855 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1856 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1857 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1858 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1859 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1860 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1861 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1862 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1863 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1864 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1865 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1866 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1867 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1868 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1869 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1870 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1871 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1872 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1873 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1874 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1875 1876 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 1 }, 1877 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 1 }, 1878 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, 1879 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1880 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1881 1882 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1883 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1884 1885 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 1 }, 1886 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 1 }, 1887 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 3 }, 1888 1889 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 4 }, 1890 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 7 }, 1891 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 4 }, 1892 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 7 }, 1893 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 4 }, 1894 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 15 }, 1895 1896 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1897 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1898 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 3 }, 1899 1900 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1901 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1902 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 2 }, 1903 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 1904 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 1905 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 }, 1906 }; 1907 1908 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1909 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1910 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1911 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1912 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1913 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 1914 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 1915 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 1916 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 1917 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1918 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1919 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1920 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1921 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1922 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1923 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1924 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1925 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1926 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1927 1928 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 4 }, 1929 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 5 }, 1930 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 4 }, 1931 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 9 }, 1932 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, 11 }, 1933 1934 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // and+extract+packuswb 1935 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 2 }, // and+packusdw+packuswb 1936 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1937 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1938 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1939 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 3 }, // and+extract+2*packusdw 1940 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1941 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 11 }, 1942 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 9 }, 1943 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 }, 1944 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 11 }, 1945 1946 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1947 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1948 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1949 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1950 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1951 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1952 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1953 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1954 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1955 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 1956 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 1957 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 }, 1958 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 5 }, 1959 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 8 }, 1960 1961 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1962 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1963 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1964 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1965 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1966 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1967 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1968 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1969 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1970 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 4 }, 1971 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 10 }, 1972 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1973 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1974 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 18 }, 1975 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 10 }, 1976 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1977 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 10 }, 1978 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1979 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1980 1981 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 4 }, 1982 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f64, 3 }, 1983 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f64, 2 }, 1984 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 2 }, 1985 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 3 }, 1986 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 2 }, 1987 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 5 }, 1988 1989 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 5 }, 1990 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 9 }, 1991 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 5 }, 1992 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f64, 3 }, 1993 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f64, 2 }, 1994 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 9 }, 1995 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 4 }, 1996 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 3 }, 1997 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 9 }, 1998 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 19 }, 1999 2000 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 2001 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 2002 }; 2003 2004 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 2005 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 2006 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 2007 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 2008 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 2009 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 2010 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 2011 2012 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i8, 1 }, 2013 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i8, 1 }, 2014 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i8, 1 }, 2015 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i8, 1 }, 2016 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i8, 1 }, 2017 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i8, 1 }, 2018 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 2019 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 2020 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 2021 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 2022 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 2023 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 2024 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 2025 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 2026 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 2027 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 2028 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 2029 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 2030 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i16, 1 }, 2031 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i16, 1 }, 2032 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i16, 1 }, 2033 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i16, 1 }, 2034 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 2035 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 2036 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 2037 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 2038 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 2039 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 2040 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, 2041 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, 2042 2043 // These truncates end up widening elements. 2044 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 1 }, // PMOVXZBQ 2045 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 1 }, // PMOVXZWQ 2046 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 1 }, // PMOVXZBD 2047 2048 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 1 }, 2049 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 1 }, 2050 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 2051 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 2052 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 2053 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 2054 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 2055 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 2056 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 1 }, // PSHUFB 2057 2058 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 2059 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 1 }, 2060 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2061 2062 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 2063 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 2064 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 12 }, 2065 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 22 }, 2066 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 4 }, 2067 2068 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 3 }, 2069 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 3 }, 2070 2071 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 3 }, 2072 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 3 }, 2073 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, 2074 }; 2075 2076 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 2077 // These are somewhat magic numbers justified by comparing the 2078 // output of llvm-mca for our various supported scheduler models 2079 // and basing it off the worst case scenario. 2080 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 3 }, 2081 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 4 }, 2082 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 3 }, 2083 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 4 }, 2084 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 3 }, 2085 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4 }, 2086 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 8 }, 2087 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 8 }, 2088 2089 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 8 }, 2090 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 9 }, 2091 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 4 }, 2092 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 4 }, 2093 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 4 }, 2094 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 4 }, 2095 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 7 }, 2096 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 2097 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 15 }, 2098 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 18 }, 2099 2100 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 4 }, 2101 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 2 }, 2102 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, 2103 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, 2104 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, 2105 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 4 }, 2106 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 1 }, 2107 2108 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 2109 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 15 }, 2110 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 4 }, 2111 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 4 }, 2112 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 }, 2113 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 2 }, 2114 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 }, 2115 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 4 }, 2116 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 8 }, 2117 2118 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 2119 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 2120 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 2121 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 2122 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 2123 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 2124 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 2125 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 2126 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 2127 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 2128 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 2129 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 2130 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 2131 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 2132 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 2133 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 2134 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 2135 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 2136 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 2137 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 2138 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 2139 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 2140 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 2141 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 2142 2143 // These truncates are really widening elements. 2144 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 1 }, // PSHUFD 2145 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // PUNPCKLWD+DQ 2146 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // PUNPCKLBW+WD+PSHUFD 2147 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 1 }, // PUNPCKLWD 2148 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // PUNPCKLBW+WD 2149 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 1 }, // PUNPCKLBW 2150 2151 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // PAND+PACKUSWB 2152 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // PAND+PACKUSWB 2153 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // PAND+PACKUSWB 2154 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 2155 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 3 }, // PAND+2*PACKUSWB 2156 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 2157 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 2158 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 2159 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 2160 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 2161 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2162 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 2163 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 2164 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 2165 { ISD::TRUNCATE, MVT::v2i32, MVT::v2i64, 1 }, // PSHUFD 2166 }; 2167 2168 // Attempt to map directly to (simple) MVT types to let us match custom entries. 2169 EVT SrcTy = TLI->getValueType(DL, Src); 2170 EVT DstTy = TLI->getValueType(DL, Dst); 2171 2172 // The function getSimpleVT only handles simple value types. 2173 if (SrcTy.isSimple() && DstTy.isSimple()) { 2174 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 2175 MVT SimpleDstTy = DstTy.getSimpleVT(); 2176 2177 if (ST->useAVX512Regs()) { 2178 if (ST->hasBWI()) 2179 if (const auto *Entry = ConvertCostTableLookup( 2180 AVX512BWConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2181 return AdjustCost(Entry->Cost); 2182 2183 if (ST->hasDQI()) 2184 if (const auto *Entry = ConvertCostTableLookup( 2185 AVX512DQConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2186 return AdjustCost(Entry->Cost); 2187 2188 if (ST->hasAVX512()) 2189 if (const auto *Entry = ConvertCostTableLookup( 2190 AVX512FConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2191 return AdjustCost(Entry->Cost); 2192 } 2193 2194 if (ST->hasBWI()) 2195 if (const auto *Entry = ConvertCostTableLookup( 2196 AVX512BWVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2197 return AdjustCost(Entry->Cost); 2198 2199 if (ST->hasDQI()) 2200 if (const auto *Entry = ConvertCostTableLookup( 2201 AVX512DQVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2202 return AdjustCost(Entry->Cost); 2203 2204 if (ST->hasAVX512()) 2205 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2206 SimpleDstTy, SimpleSrcTy)) 2207 return AdjustCost(Entry->Cost); 2208 2209 if (ST->hasAVX2()) { 2210 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2211 SimpleDstTy, SimpleSrcTy)) 2212 return AdjustCost(Entry->Cost); 2213 } 2214 2215 if (ST->hasAVX()) { 2216 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2217 SimpleDstTy, SimpleSrcTy)) 2218 return AdjustCost(Entry->Cost); 2219 } 2220 2221 if (ST->hasSSE41()) { 2222 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2223 SimpleDstTy, SimpleSrcTy)) 2224 return AdjustCost(Entry->Cost); 2225 } 2226 2227 if (ST->hasSSE2()) { 2228 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2229 SimpleDstTy, SimpleSrcTy)) 2230 return AdjustCost(Entry->Cost); 2231 } 2232 } 2233 2234 // Fall back to legalized types. 2235 std::pair<InstructionCost, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 2236 std::pair<InstructionCost, MVT> LTDest = 2237 TLI->getTypeLegalizationCost(DL, Dst); 2238 2239 if (ST->useAVX512Regs()) { 2240 if (ST->hasBWI()) 2241 if (const auto *Entry = ConvertCostTableLookup( 2242 AVX512BWConversionTbl, ISD, LTDest.second, LTSrc.second)) 2243 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2244 2245 if (ST->hasDQI()) 2246 if (const auto *Entry = ConvertCostTableLookup( 2247 AVX512DQConversionTbl, ISD, LTDest.second, LTSrc.second)) 2248 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2249 2250 if (ST->hasAVX512()) 2251 if (const auto *Entry = ConvertCostTableLookup( 2252 AVX512FConversionTbl, ISD, LTDest.second, LTSrc.second)) 2253 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2254 } 2255 2256 if (ST->hasBWI()) 2257 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 2258 LTDest.second, LTSrc.second)) 2259 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2260 2261 if (ST->hasDQI()) 2262 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 2263 LTDest.second, LTSrc.second)) 2264 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2265 2266 if (ST->hasAVX512()) 2267 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2268 LTDest.second, LTSrc.second)) 2269 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2270 2271 if (ST->hasAVX2()) 2272 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2273 LTDest.second, LTSrc.second)) 2274 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2275 2276 if (ST->hasAVX()) 2277 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2278 LTDest.second, LTSrc.second)) 2279 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2280 2281 if (ST->hasSSE41()) 2282 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2283 LTDest.second, LTSrc.second)) 2284 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2285 2286 if (ST->hasSSE2()) 2287 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2288 LTDest.second, LTSrc.second)) 2289 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2290 2291 return AdjustCost( 2292 BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I)); 2293 } 2294 2295 InstructionCost X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 2296 Type *CondTy, 2297 CmpInst::Predicate VecPred, 2298 TTI::TargetCostKind CostKind, 2299 const Instruction *I) { 2300 // TODO: Handle other cost kinds. 2301 if (CostKind != TTI::TCK_RecipThroughput) 2302 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, 2303 I); 2304 2305 // Legalize the type. 2306 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2307 2308 MVT MTy = LT.second; 2309 2310 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2311 assert(ISD && "Invalid opcode"); 2312 2313 unsigned ExtraCost = 0; 2314 if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) { 2315 // Some vector comparison predicates cost extra instructions. 2316 if (MTy.isVector() && 2317 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 2318 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 2319 ST->hasBWI())) { 2320 switch (cast<CmpInst>(I)->getPredicate()) { 2321 case CmpInst::Predicate::ICMP_NE: 2322 // xor(cmpeq(x,y),-1) 2323 ExtraCost = 1; 2324 break; 2325 case CmpInst::Predicate::ICMP_SGE: 2326 case CmpInst::Predicate::ICMP_SLE: 2327 // xor(cmpgt(x,y),-1) 2328 ExtraCost = 1; 2329 break; 2330 case CmpInst::Predicate::ICMP_ULT: 2331 case CmpInst::Predicate::ICMP_UGT: 2332 // cmpgt(xor(x,signbit),xor(y,signbit)) 2333 // xor(cmpeq(pmaxu(x,y),x),-1) 2334 ExtraCost = 2; 2335 break; 2336 case CmpInst::Predicate::ICMP_ULE: 2337 case CmpInst::Predicate::ICMP_UGE: 2338 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 2339 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 2340 // cmpeq(psubus(x,y),0) 2341 // cmpeq(pminu(x,y),x) 2342 ExtraCost = 1; 2343 } else { 2344 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 2345 ExtraCost = 3; 2346 } 2347 break; 2348 default: 2349 break; 2350 } 2351 } 2352 } 2353 2354 static const CostTblEntry SLMCostTbl[] = { 2355 // slm pcmpeq/pcmpgt throughput is 2 2356 { ISD::SETCC, MVT::v2i64, 2 }, 2357 }; 2358 2359 static const CostTblEntry AVX512BWCostTbl[] = { 2360 { ISD::SETCC, MVT::v32i16, 1 }, 2361 { ISD::SETCC, MVT::v64i8, 1 }, 2362 2363 { ISD::SELECT, MVT::v32i16, 1 }, 2364 { ISD::SELECT, MVT::v64i8, 1 }, 2365 }; 2366 2367 static const CostTblEntry AVX512CostTbl[] = { 2368 { ISD::SETCC, MVT::v8i64, 1 }, 2369 { ISD::SETCC, MVT::v16i32, 1 }, 2370 { ISD::SETCC, MVT::v8f64, 1 }, 2371 { ISD::SETCC, MVT::v16f32, 1 }, 2372 2373 { ISD::SELECT, MVT::v8i64, 1 }, 2374 { ISD::SELECT, MVT::v16i32, 1 }, 2375 { ISD::SELECT, MVT::v8f64, 1 }, 2376 { ISD::SELECT, MVT::v16f32, 1 }, 2377 2378 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 2379 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 2380 2381 { ISD::SELECT, MVT::v32i16, 2 }, // FIXME: should be 3 2382 { ISD::SELECT, MVT::v64i8, 2 }, // FIXME: should be 3 2383 }; 2384 2385 static const CostTblEntry AVX2CostTbl[] = { 2386 { ISD::SETCC, MVT::v4i64, 1 }, 2387 { ISD::SETCC, MVT::v8i32, 1 }, 2388 { ISD::SETCC, MVT::v16i16, 1 }, 2389 { ISD::SETCC, MVT::v32i8, 1 }, 2390 2391 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 2392 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 2393 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 2394 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 2395 }; 2396 2397 static const CostTblEntry AVX1CostTbl[] = { 2398 { ISD::SETCC, MVT::v4f64, 1 }, 2399 { ISD::SETCC, MVT::v8f32, 1 }, 2400 // AVX1 does not support 8-wide integer compare. 2401 { ISD::SETCC, MVT::v4i64, 4 }, 2402 { ISD::SETCC, MVT::v8i32, 4 }, 2403 { ISD::SETCC, MVT::v16i16, 4 }, 2404 { ISD::SETCC, MVT::v32i8, 4 }, 2405 2406 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 2407 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 2408 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 2409 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 2410 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 2411 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 2412 }; 2413 2414 static const CostTblEntry SSE42CostTbl[] = { 2415 { ISD::SETCC, MVT::v2f64, 1 }, 2416 { ISD::SETCC, MVT::v4f32, 1 }, 2417 { ISD::SETCC, MVT::v2i64, 1 }, 2418 }; 2419 2420 static const CostTblEntry SSE41CostTbl[] = { 2421 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 2422 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 2423 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 2424 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 2425 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 2426 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 2427 }; 2428 2429 static const CostTblEntry SSE2CostTbl[] = { 2430 { ISD::SETCC, MVT::v2f64, 2 }, 2431 { ISD::SETCC, MVT::f64, 1 }, 2432 { ISD::SETCC, MVT::v2i64, 8 }, 2433 { ISD::SETCC, MVT::v4i32, 1 }, 2434 { ISD::SETCC, MVT::v8i16, 1 }, 2435 { ISD::SETCC, MVT::v16i8, 1 }, 2436 2437 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 2438 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 2439 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 2440 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 2441 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 2442 }; 2443 2444 static const CostTblEntry SSE1CostTbl[] = { 2445 { ISD::SETCC, MVT::v4f32, 2 }, 2446 { ISD::SETCC, MVT::f32, 1 }, 2447 2448 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 2449 }; 2450 2451 if (ST->isSLM()) 2452 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2453 return LT.first * (ExtraCost + Entry->Cost); 2454 2455 if (ST->hasBWI()) 2456 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2457 return LT.first * (ExtraCost + Entry->Cost); 2458 2459 if (ST->hasAVX512()) 2460 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2461 return LT.first * (ExtraCost + Entry->Cost); 2462 2463 if (ST->hasAVX2()) 2464 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2465 return LT.first * (ExtraCost + Entry->Cost); 2466 2467 if (ST->hasAVX()) 2468 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2469 return LT.first * (ExtraCost + Entry->Cost); 2470 2471 if (ST->hasSSE42()) 2472 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2473 return LT.first * (ExtraCost + Entry->Cost); 2474 2475 if (ST->hasSSE41()) 2476 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2477 return LT.first * (ExtraCost + Entry->Cost); 2478 2479 if (ST->hasSSE2()) 2480 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2481 return LT.first * (ExtraCost + Entry->Cost); 2482 2483 if (ST->hasSSE1()) 2484 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2485 return LT.first * (ExtraCost + Entry->Cost); 2486 2487 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I); 2488 } 2489 2490 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2491 2492 InstructionCost 2493 X86TTIImpl::getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 2494 TTI::TargetCostKind CostKind) { 2495 2496 // Costs should match the codegen from: 2497 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2498 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2499 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2500 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2501 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2502 2503 // TODO: Overflow intrinsics (*ADDO, *SUBO, *MULO) with vector types are not 2504 // specialized in these tables yet. 2505 static const CostTblEntry AVX512CDCostTbl[] = { 2506 { ISD::CTLZ, MVT::v8i64, 1 }, 2507 { ISD::CTLZ, MVT::v16i32, 1 }, 2508 { ISD::CTLZ, MVT::v32i16, 8 }, 2509 { ISD::CTLZ, MVT::v64i8, 20 }, 2510 { ISD::CTLZ, MVT::v4i64, 1 }, 2511 { ISD::CTLZ, MVT::v8i32, 1 }, 2512 { ISD::CTLZ, MVT::v16i16, 4 }, 2513 { ISD::CTLZ, MVT::v32i8, 10 }, 2514 { ISD::CTLZ, MVT::v2i64, 1 }, 2515 { ISD::CTLZ, MVT::v4i32, 1 }, 2516 { ISD::CTLZ, MVT::v8i16, 4 }, 2517 { ISD::CTLZ, MVT::v16i8, 4 }, 2518 }; 2519 static const CostTblEntry AVX512BWCostTbl[] = { 2520 { ISD::ABS, MVT::v32i16, 1 }, 2521 { ISD::ABS, MVT::v64i8, 1 }, 2522 { ISD::BITREVERSE, MVT::v8i64, 5 }, 2523 { ISD::BITREVERSE, MVT::v16i32, 5 }, 2524 { ISD::BITREVERSE, MVT::v32i16, 5 }, 2525 { ISD::BITREVERSE, MVT::v64i8, 5 }, 2526 { ISD::BSWAP, MVT::v8i64, 1 }, 2527 { ISD::BSWAP, MVT::v16i32, 1 }, 2528 { ISD::BSWAP, MVT::v32i16, 1 }, 2529 { ISD::CTLZ, MVT::v8i64, 23 }, 2530 { ISD::CTLZ, MVT::v16i32, 22 }, 2531 { ISD::CTLZ, MVT::v32i16, 18 }, 2532 { ISD::CTLZ, MVT::v64i8, 17 }, 2533 { ISD::CTPOP, MVT::v8i64, 7 }, 2534 { ISD::CTPOP, MVT::v16i32, 11 }, 2535 { ISD::CTPOP, MVT::v32i16, 9 }, 2536 { ISD::CTPOP, MVT::v64i8, 6 }, 2537 { ISD::CTTZ, MVT::v8i64, 10 }, 2538 { ISD::CTTZ, MVT::v16i32, 14 }, 2539 { ISD::CTTZ, MVT::v32i16, 12 }, 2540 { ISD::CTTZ, MVT::v64i8, 9 }, 2541 { ISD::SADDSAT, MVT::v32i16, 1 }, 2542 { ISD::SADDSAT, MVT::v64i8, 1 }, 2543 { ISD::SMAX, MVT::v32i16, 1 }, 2544 { ISD::SMAX, MVT::v64i8, 1 }, 2545 { ISD::SMIN, MVT::v32i16, 1 }, 2546 { ISD::SMIN, MVT::v64i8, 1 }, 2547 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2548 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2549 { ISD::UADDSAT, MVT::v32i16, 1 }, 2550 { ISD::UADDSAT, MVT::v64i8, 1 }, 2551 { ISD::UMAX, MVT::v32i16, 1 }, 2552 { ISD::UMAX, MVT::v64i8, 1 }, 2553 { ISD::UMIN, MVT::v32i16, 1 }, 2554 { ISD::UMIN, MVT::v64i8, 1 }, 2555 { ISD::USUBSAT, MVT::v32i16, 1 }, 2556 { ISD::USUBSAT, MVT::v64i8, 1 }, 2557 }; 2558 static const CostTblEntry AVX512CostTbl[] = { 2559 { ISD::ABS, MVT::v8i64, 1 }, 2560 { ISD::ABS, MVT::v16i32, 1 }, 2561 { ISD::ABS, MVT::v32i16, 2 }, // FIXME: include split 2562 { ISD::ABS, MVT::v64i8, 2 }, // FIXME: include split 2563 { ISD::ABS, MVT::v4i64, 1 }, 2564 { ISD::ABS, MVT::v2i64, 1 }, 2565 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2566 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2567 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2568 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2569 { ISD::BSWAP, MVT::v8i64, 4 }, 2570 { ISD::BSWAP, MVT::v16i32, 4 }, 2571 { ISD::BSWAP, MVT::v32i16, 4 }, 2572 { ISD::CTLZ, MVT::v8i64, 29 }, 2573 { ISD::CTLZ, MVT::v16i32, 35 }, 2574 { ISD::CTLZ, MVT::v32i16, 28 }, 2575 { ISD::CTLZ, MVT::v64i8, 18 }, 2576 { ISD::CTPOP, MVT::v8i64, 16 }, 2577 { ISD::CTPOP, MVT::v16i32, 24 }, 2578 { ISD::CTPOP, MVT::v32i16, 18 }, 2579 { ISD::CTPOP, MVT::v64i8, 12 }, 2580 { ISD::CTTZ, MVT::v8i64, 20 }, 2581 { ISD::CTTZ, MVT::v16i32, 28 }, 2582 { ISD::CTTZ, MVT::v32i16, 24 }, 2583 { ISD::CTTZ, MVT::v64i8, 18 }, 2584 { ISD::SMAX, MVT::v8i64, 1 }, 2585 { ISD::SMAX, MVT::v16i32, 1 }, 2586 { ISD::SMAX, MVT::v32i16, 2 }, // FIXME: include split 2587 { ISD::SMAX, MVT::v64i8, 2 }, // FIXME: include split 2588 { ISD::SMAX, MVT::v4i64, 1 }, 2589 { ISD::SMAX, MVT::v2i64, 1 }, 2590 { ISD::SMIN, MVT::v8i64, 1 }, 2591 { ISD::SMIN, MVT::v16i32, 1 }, 2592 { ISD::SMIN, MVT::v32i16, 2 }, // FIXME: include split 2593 { ISD::SMIN, MVT::v64i8, 2 }, // FIXME: include split 2594 { ISD::SMIN, MVT::v4i64, 1 }, 2595 { ISD::SMIN, MVT::v2i64, 1 }, 2596 { ISD::UMAX, MVT::v8i64, 1 }, 2597 { ISD::UMAX, MVT::v16i32, 1 }, 2598 { ISD::UMAX, MVT::v32i16, 2 }, // FIXME: include split 2599 { ISD::UMAX, MVT::v64i8, 2 }, // FIXME: include split 2600 { ISD::UMAX, MVT::v4i64, 1 }, 2601 { ISD::UMAX, MVT::v2i64, 1 }, 2602 { ISD::UMIN, MVT::v8i64, 1 }, 2603 { ISD::UMIN, MVT::v16i32, 1 }, 2604 { ISD::UMIN, MVT::v32i16, 2 }, // FIXME: include split 2605 { ISD::UMIN, MVT::v64i8, 2 }, // FIXME: include split 2606 { ISD::UMIN, MVT::v4i64, 1 }, 2607 { ISD::UMIN, MVT::v2i64, 1 }, 2608 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2609 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2610 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2611 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2612 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2613 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2614 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2615 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2616 { ISD::SADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2617 { ISD::SADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2618 { ISD::SSUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2619 { ISD::SSUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2620 { ISD::UADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2621 { ISD::UADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2622 { ISD::USUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2623 { ISD::USUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2624 { ISD::FMAXNUM, MVT::f32, 2 }, 2625 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2626 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2627 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2628 { ISD::FMAXNUM, MVT::f64, 2 }, 2629 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2630 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2631 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2632 }; 2633 static const CostTblEntry XOPCostTbl[] = { 2634 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2635 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2636 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2637 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2638 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2639 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2640 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2641 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2642 { ISD::BITREVERSE, MVT::i64, 3 }, 2643 { ISD::BITREVERSE, MVT::i32, 3 }, 2644 { ISD::BITREVERSE, MVT::i16, 3 }, 2645 { ISD::BITREVERSE, MVT::i8, 3 } 2646 }; 2647 static const CostTblEntry AVX2CostTbl[] = { 2648 { ISD::ABS, MVT::v4i64, 2 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2649 { ISD::ABS, MVT::v8i32, 1 }, 2650 { ISD::ABS, MVT::v16i16, 1 }, 2651 { ISD::ABS, MVT::v32i8, 1 }, 2652 { ISD::BITREVERSE, MVT::v4i64, 5 }, 2653 { ISD::BITREVERSE, MVT::v8i32, 5 }, 2654 { ISD::BITREVERSE, MVT::v16i16, 5 }, 2655 { ISD::BITREVERSE, MVT::v32i8, 5 }, 2656 { ISD::BSWAP, MVT::v4i64, 1 }, 2657 { ISD::BSWAP, MVT::v8i32, 1 }, 2658 { ISD::BSWAP, MVT::v16i16, 1 }, 2659 { ISD::CTLZ, MVT::v4i64, 23 }, 2660 { ISD::CTLZ, MVT::v8i32, 18 }, 2661 { ISD::CTLZ, MVT::v16i16, 14 }, 2662 { ISD::CTLZ, MVT::v32i8, 9 }, 2663 { ISD::CTPOP, MVT::v4i64, 7 }, 2664 { ISD::CTPOP, MVT::v8i32, 11 }, 2665 { ISD::CTPOP, MVT::v16i16, 9 }, 2666 { ISD::CTPOP, MVT::v32i8, 6 }, 2667 { ISD::CTTZ, MVT::v4i64, 10 }, 2668 { ISD::CTTZ, MVT::v8i32, 14 }, 2669 { ISD::CTTZ, MVT::v16i16, 12 }, 2670 { ISD::CTTZ, MVT::v32i8, 9 }, 2671 { ISD::SADDSAT, MVT::v16i16, 1 }, 2672 { ISD::SADDSAT, MVT::v32i8, 1 }, 2673 { ISD::SMAX, MVT::v8i32, 1 }, 2674 { ISD::SMAX, MVT::v16i16, 1 }, 2675 { ISD::SMAX, MVT::v32i8, 1 }, 2676 { ISD::SMIN, MVT::v8i32, 1 }, 2677 { ISD::SMIN, MVT::v16i16, 1 }, 2678 { ISD::SMIN, MVT::v32i8, 1 }, 2679 { ISD::SSUBSAT, MVT::v16i16, 1 }, 2680 { ISD::SSUBSAT, MVT::v32i8, 1 }, 2681 { ISD::UADDSAT, MVT::v16i16, 1 }, 2682 { ISD::UADDSAT, MVT::v32i8, 1 }, 2683 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 2684 { ISD::UMAX, MVT::v8i32, 1 }, 2685 { ISD::UMAX, MVT::v16i16, 1 }, 2686 { ISD::UMAX, MVT::v32i8, 1 }, 2687 { ISD::UMIN, MVT::v8i32, 1 }, 2688 { ISD::UMIN, MVT::v16i16, 1 }, 2689 { ISD::UMIN, MVT::v32i8, 1 }, 2690 { ISD::USUBSAT, MVT::v16i16, 1 }, 2691 { ISD::USUBSAT, MVT::v32i8, 1 }, 2692 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2693 { ISD::FMAXNUM, MVT::v8f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2694 { ISD::FMAXNUM, MVT::v4f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2695 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2696 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2697 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2698 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2699 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2700 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2701 }; 2702 static const CostTblEntry AVX1CostTbl[] = { 2703 { ISD::ABS, MVT::v4i64, 5 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2704 { ISD::ABS, MVT::v8i32, 3 }, 2705 { ISD::ABS, MVT::v16i16, 3 }, 2706 { ISD::ABS, MVT::v32i8, 3 }, 2707 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 2708 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 2709 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 2710 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 2711 { ISD::BSWAP, MVT::v4i64, 4 }, 2712 { ISD::BSWAP, MVT::v8i32, 4 }, 2713 { ISD::BSWAP, MVT::v16i16, 4 }, 2714 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 2715 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 2716 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 2717 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2718 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 2719 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 2720 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 2721 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 2722 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 2723 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 2724 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 2725 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2726 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2727 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2728 { ISD::SMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2729 { ISD::SMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2730 { ISD::SMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2731 { ISD::SMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2732 { ISD::SMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2733 { ISD::SMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2734 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2735 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2736 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2737 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2738 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 2739 { ISD::UMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2740 { ISD::UMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2741 { ISD::UMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2742 { ISD::UMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2743 { ISD::UMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2744 { ISD::UMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2745 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2746 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2747 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 2748 { ISD::FMAXNUM, MVT::f32, 3 }, // MAXSS + CMPUNORDSS + BLENDVPS 2749 { ISD::FMAXNUM, MVT::v4f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2750 { ISD::FMAXNUM, MVT::v8f32, 5 }, // MAXPS + CMPUNORDPS + BLENDVPS + ? 2751 { ISD::FMAXNUM, MVT::f64, 3 }, // MAXSD + CMPUNORDSD + BLENDVPD 2752 { ISD::FMAXNUM, MVT::v2f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2753 { ISD::FMAXNUM, MVT::v4f64, 5 }, // MAXPD + CMPUNORDPD + BLENDVPD + ? 2754 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 2755 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 2756 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 2757 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 2758 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 2759 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 2760 }; 2761 static const CostTblEntry GLMCostTbl[] = { 2762 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 2763 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 2764 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 2765 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 2766 }; 2767 static const CostTblEntry SLMCostTbl[] = { 2768 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 2769 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 2770 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 2771 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 2772 }; 2773 static const CostTblEntry SSE42CostTbl[] = { 2774 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 2775 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 2776 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 2777 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 2778 }; 2779 static const CostTblEntry SSE41CostTbl[] = { 2780 { ISD::ABS, MVT::v2i64, 2 }, // BLENDVPD(X,PSUBQ(0,X),X) 2781 { ISD::SMAX, MVT::v4i32, 1 }, 2782 { ISD::SMAX, MVT::v16i8, 1 }, 2783 { ISD::SMIN, MVT::v4i32, 1 }, 2784 { ISD::SMIN, MVT::v16i8, 1 }, 2785 { ISD::UMAX, MVT::v4i32, 1 }, 2786 { ISD::UMAX, MVT::v8i16, 1 }, 2787 { ISD::UMIN, MVT::v4i32, 1 }, 2788 { ISD::UMIN, MVT::v8i16, 1 }, 2789 }; 2790 static const CostTblEntry SSSE3CostTbl[] = { 2791 { ISD::ABS, MVT::v4i32, 1 }, 2792 { ISD::ABS, MVT::v8i16, 1 }, 2793 { ISD::ABS, MVT::v16i8, 1 }, 2794 { ISD::BITREVERSE, MVT::v2i64, 5 }, 2795 { ISD::BITREVERSE, MVT::v4i32, 5 }, 2796 { ISD::BITREVERSE, MVT::v8i16, 5 }, 2797 { ISD::BITREVERSE, MVT::v16i8, 5 }, 2798 { ISD::BSWAP, MVT::v2i64, 1 }, 2799 { ISD::BSWAP, MVT::v4i32, 1 }, 2800 { ISD::BSWAP, MVT::v8i16, 1 }, 2801 { ISD::CTLZ, MVT::v2i64, 23 }, 2802 { ISD::CTLZ, MVT::v4i32, 18 }, 2803 { ISD::CTLZ, MVT::v8i16, 14 }, 2804 { ISD::CTLZ, MVT::v16i8, 9 }, 2805 { ISD::CTPOP, MVT::v2i64, 7 }, 2806 { ISD::CTPOP, MVT::v4i32, 11 }, 2807 { ISD::CTPOP, MVT::v8i16, 9 }, 2808 { ISD::CTPOP, MVT::v16i8, 6 }, 2809 { ISD::CTTZ, MVT::v2i64, 10 }, 2810 { ISD::CTTZ, MVT::v4i32, 14 }, 2811 { ISD::CTTZ, MVT::v8i16, 12 }, 2812 { ISD::CTTZ, MVT::v16i8, 9 } 2813 }; 2814 static const CostTblEntry SSE2CostTbl[] = { 2815 { ISD::ABS, MVT::v2i64, 4 }, 2816 { ISD::ABS, MVT::v4i32, 3 }, 2817 { ISD::ABS, MVT::v8i16, 2 }, 2818 { ISD::ABS, MVT::v16i8, 2 }, 2819 { ISD::BITREVERSE, MVT::v2i64, 29 }, 2820 { ISD::BITREVERSE, MVT::v4i32, 27 }, 2821 { ISD::BITREVERSE, MVT::v8i16, 27 }, 2822 { ISD::BITREVERSE, MVT::v16i8, 20 }, 2823 { ISD::BSWAP, MVT::v2i64, 7 }, 2824 { ISD::BSWAP, MVT::v4i32, 7 }, 2825 { ISD::BSWAP, MVT::v8i16, 7 }, 2826 { ISD::CTLZ, MVT::v2i64, 25 }, 2827 { ISD::CTLZ, MVT::v4i32, 26 }, 2828 { ISD::CTLZ, MVT::v8i16, 20 }, 2829 { ISD::CTLZ, MVT::v16i8, 17 }, 2830 { ISD::CTPOP, MVT::v2i64, 12 }, 2831 { ISD::CTPOP, MVT::v4i32, 15 }, 2832 { ISD::CTPOP, MVT::v8i16, 13 }, 2833 { ISD::CTPOP, MVT::v16i8, 10 }, 2834 { ISD::CTTZ, MVT::v2i64, 14 }, 2835 { ISD::CTTZ, MVT::v4i32, 18 }, 2836 { ISD::CTTZ, MVT::v8i16, 16 }, 2837 { ISD::CTTZ, MVT::v16i8, 13 }, 2838 { ISD::SADDSAT, MVT::v8i16, 1 }, 2839 { ISD::SADDSAT, MVT::v16i8, 1 }, 2840 { ISD::SMAX, MVT::v8i16, 1 }, 2841 { ISD::SMIN, MVT::v8i16, 1 }, 2842 { ISD::SSUBSAT, MVT::v8i16, 1 }, 2843 { ISD::SSUBSAT, MVT::v16i8, 1 }, 2844 { ISD::UADDSAT, MVT::v8i16, 1 }, 2845 { ISD::UADDSAT, MVT::v16i8, 1 }, 2846 { ISD::UMAX, MVT::v8i16, 2 }, 2847 { ISD::UMAX, MVT::v16i8, 1 }, 2848 { ISD::UMIN, MVT::v8i16, 2 }, 2849 { ISD::UMIN, MVT::v16i8, 1 }, 2850 { ISD::USUBSAT, MVT::v8i16, 1 }, 2851 { ISD::USUBSAT, MVT::v16i8, 1 }, 2852 { ISD::FMAXNUM, MVT::f64, 4 }, 2853 { ISD::FMAXNUM, MVT::v2f64, 4 }, 2854 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 2855 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 2856 }; 2857 static const CostTblEntry SSE1CostTbl[] = { 2858 { ISD::FMAXNUM, MVT::f32, 4 }, 2859 { ISD::FMAXNUM, MVT::v4f32, 4 }, 2860 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 2861 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 2862 }; 2863 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 2864 { ISD::CTTZ, MVT::i64, 1 }, 2865 }; 2866 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 2867 { ISD::CTTZ, MVT::i32, 1 }, 2868 { ISD::CTTZ, MVT::i16, 1 }, 2869 { ISD::CTTZ, MVT::i8, 1 }, 2870 }; 2871 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 2872 { ISD::CTLZ, MVT::i64, 1 }, 2873 }; 2874 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 2875 { ISD::CTLZ, MVT::i32, 1 }, 2876 { ISD::CTLZ, MVT::i16, 1 }, 2877 { ISD::CTLZ, MVT::i8, 1 }, 2878 }; 2879 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 2880 { ISD::CTPOP, MVT::i64, 1 }, 2881 }; 2882 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 2883 { ISD::CTPOP, MVT::i32, 1 }, 2884 { ISD::CTPOP, MVT::i16, 1 }, 2885 { ISD::CTPOP, MVT::i8, 1 }, 2886 }; 2887 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2888 { ISD::ABS, MVT::i64, 2 }, // SUB+CMOV 2889 { ISD::BITREVERSE, MVT::i64, 14 }, 2890 { ISD::BSWAP, MVT::i64, 1 }, 2891 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 2892 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 2893 { ISD::CTPOP, MVT::i64, 10 }, 2894 { ISD::SADDO, MVT::i64, 1 }, 2895 { ISD::UADDO, MVT::i64, 1 }, 2896 { ISD::UMULO, MVT::i64, 2 }, // mulq + seto 2897 }; 2898 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2899 { ISD::ABS, MVT::i32, 2 }, // SUB+CMOV 2900 { ISD::ABS, MVT::i16, 2 }, // SUB+CMOV 2901 { ISD::BITREVERSE, MVT::i32, 14 }, 2902 { ISD::BITREVERSE, MVT::i16, 14 }, 2903 { ISD::BITREVERSE, MVT::i8, 11 }, 2904 { ISD::BSWAP, MVT::i32, 1 }, 2905 { ISD::BSWAP, MVT::i16, 1 }, // ROL 2906 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 2907 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 2908 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 2909 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 2910 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 2911 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 2912 { ISD::CTPOP, MVT::i32, 8 }, 2913 { ISD::CTPOP, MVT::i16, 9 }, 2914 { ISD::CTPOP, MVT::i8, 7 }, 2915 { ISD::SADDO, MVT::i32, 1 }, 2916 { ISD::SADDO, MVT::i16, 1 }, 2917 { ISD::SADDO, MVT::i8, 1 }, 2918 { ISD::UADDO, MVT::i32, 1 }, 2919 { ISD::UADDO, MVT::i16, 1 }, 2920 { ISD::UADDO, MVT::i8, 1 }, 2921 { ISD::UMULO, MVT::i32, 2 }, // mul + seto 2922 { ISD::UMULO, MVT::i16, 2 }, 2923 { ISD::UMULO, MVT::i8, 2 }, 2924 }; 2925 2926 Type *RetTy = ICA.getReturnType(); 2927 Type *OpTy = RetTy; 2928 Intrinsic::ID IID = ICA.getID(); 2929 unsigned ISD = ISD::DELETED_NODE; 2930 switch (IID) { 2931 default: 2932 break; 2933 case Intrinsic::abs: 2934 ISD = ISD::ABS; 2935 break; 2936 case Intrinsic::bitreverse: 2937 ISD = ISD::BITREVERSE; 2938 break; 2939 case Intrinsic::bswap: 2940 ISD = ISD::BSWAP; 2941 break; 2942 case Intrinsic::ctlz: 2943 ISD = ISD::CTLZ; 2944 break; 2945 case Intrinsic::ctpop: 2946 ISD = ISD::CTPOP; 2947 break; 2948 case Intrinsic::cttz: 2949 ISD = ISD::CTTZ; 2950 break; 2951 case Intrinsic::maxnum: 2952 case Intrinsic::minnum: 2953 // FMINNUM has same costs so don't duplicate. 2954 ISD = ISD::FMAXNUM; 2955 break; 2956 case Intrinsic::sadd_sat: 2957 ISD = ISD::SADDSAT; 2958 break; 2959 case Intrinsic::smax: 2960 ISD = ISD::SMAX; 2961 break; 2962 case Intrinsic::smin: 2963 ISD = ISD::SMIN; 2964 break; 2965 case Intrinsic::ssub_sat: 2966 ISD = ISD::SSUBSAT; 2967 break; 2968 case Intrinsic::uadd_sat: 2969 ISD = ISD::UADDSAT; 2970 break; 2971 case Intrinsic::umax: 2972 ISD = ISD::UMAX; 2973 break; 2974 case Intrinsic::umin: 2975 ISD = ISD::UMIN; 2976 break; 2977 case Intrinsic::usub_sat: 2978 ISD = ISD::USUBSAT; 2979 break; 2980 case Intrinsic::sqrt: 2981 ISD = ISD::FSQRT; 2982 break; 2983 case Intrinsic::sadd_with_overflow: 2984 case Intrinsic::ssub_with_overflow: 2985 // SSUBO has same costs so don't duplicate. 2986 ISD = ISD::SADDO; 2987 OpTy = RetTy->getContainedType(0); 2988 break; 2989 case Intrinsic::uadd_with_overflow: 2990 case Intrinsic::usub_with_overflow: 2991 // USUBO has same costs so don't duplicate. 2992 ISD = ISD::UADDO; 2993 OpTy = RetTy->getContainedType(0); 2994 break; 2995 case Intrinsic::umul_with_overflow: 2996 case Intrinsic::smul_with_overflow: 2997 // SMULO has same costs so don't duplicate. 2998 ISD = ISD::UMULO; 2999 OpTy = RetTy->getContainedType(0); 3000 break; 3001 } 3002 3003 if (ISD != ISD::DELETED_NODE) { 3004 // Legalize the type. 3005 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 3006 MVT MTy = LT.second; 3007 3008 // Attempt to lookup cost. 3009 if (ISD == ISD::BITREVERSE && ST->hasGFNI() && ST->hasSSSE3() && 3010 MTy.isVector()) { 3011 // With PSHUFB the code is very similar for all types. If we have integer 3012 // byte operations, we just need a GF2P8AFFINEQB for vXi8. For other types 3013 // we also need a PSHUFB. 3014 unsigned Cost = MTy.getVectorElementType() == MVT::i8 ? 1 : 2; 3015 3016 // Without byte operations, we need twice as many GF2P8AFFINEQB and PSHUFB 3017 // instructions. We also need an extract and an insert. 3018 if (!(MTy.is128BitVector() || (ST->hasAVX2() && MTy.is256BitVector()) || 3019 (ST->hasBWI() && MTy.is512BitVector()))) 3020 Cost = Cost * 2 + 2; 3021 3022 return LT.first * Cost; 3023 } 3024 3025 auto adjustTableCost = [](const CostTblEntry &Entry, 3026 InstructionCost LegalizationCost, 3027 FastMathFlags FMF) { 3028 // If there are no NANs to deal with, then these are reduced to a 3029 // single MIN** or MAX** instruction instead of the MIN/CMP/SELECT that we 3030 // assume is used in the non-fast case. 3031 if (Entry.ISD == ISD::FMAXNUM || Entry.ISD == ISD::FMINNUM) { 3032 if (FMF.noNaNs()) 3033 return LegalizationCost * 1; 3034 } 3035 return LegalizationCost * (int)Entry.Cost; 3036 }; 3037 3038 if (ST->useGLMDivSqrtCosts()) 3039 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 3040 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3041 3042 if (ST->isSLM()) 3043 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 3044 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3045 3046 if (ST->hasCDI()) 3047 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 3048 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3049 3050 if (ST->hasBWI()) 3051 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3052 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3053 3054 if (ST->hasAVX512()) 3055 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3056 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3057 3058 if (ST->hasXOP()) 3059 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3060 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3061 3062 if (ST->hasAVX2()) 3063 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3064 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3065 3066 if (ST->hasAVX()) 3067 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3068 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3069 3070 if (ST->hasSSE42()) 3071 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3072 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3073 3074 if (ST->hasSSE41()) 3075 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3076 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3077 3078 if (ST->hasSSSE3()) 3079 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 3080 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3081 3082 if (ST->hasSSE2()) 3083 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3084 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3085 3086 if (ST->hasSSE1()) 3087 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3088 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3089 3090 if (ST->hasBMI()) { 3091 if (ST->is64Bit()) 3092 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 3093 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3094 3095 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 3096 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3097 } 3098 3099 if (ST->hasLZCNT()) { 3100 if (ST->is64Bit()) 3101 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 3102 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3103 3104 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 3105 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3106 } 3107 3108 if (ST->hasPOPCNT()) { 3109 if (ST->is64Bit()) 3110 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 3111 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3112 3113 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 3114 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3115 } 3116 3117 if (ISD == ISD::BSWAP && ST->hasMOVBE() && ST->hasFastMOVBE()) { 3118 if (const Instruction *II = ICA.getInst()) { 3119 if (II->hasOneUse() && isa<StoreInst>(II->user_back())) 3120 return TTI::TCC_Free; 3121 if (auto *LI = dyn_cast<LoadInst>(II->getOperand(0))) { 3122 if (LI->hasOneUse()) 3123 return TTI::TCC_Free; 3124 } 3125 } 3126 } 3127 3128 // TODO - add BMI (TZCNT) scalar handling 3129 3130 if (ST->is64Bit()) 3131 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3132 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3133 3134 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3135 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3136 } 3137 3138 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3139 } 3140 3141 InstructionCost 3142 X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 3143 TTI::TargetCostKind CostKind) { 3144 if (ICA.isTypeBasedOnly()) 3145 return getTypeBasedIntrinsicInstrCost(ICA, CostKind); 3146 3147 static const CostTblEntry AVX512CostTbl[] = { 3148 { ISD::ROTL, MVT::v8i64, 1 }, 3149 { ISD::ROTL, MVT::v4i64, 1 }, 3150 { ISD::ROTL, MVT::v2i64, 1 }, 3151 { ISD::ROTL, MVT::v16i32, 1 }, 3152 { ISD::ROTL, MVT::v8i32, 1 }, 3153 { ISD::ROTL, MVT::v4i32, 1 }, 3154 { ISD::ROTR, MVT::v8i64, 1 }, 3155 { ISD::ROTR, MVT::v4i64, 1 }, 3156 { ISD::ROTR, MVT::v2i64, 1 }, 3157 { ISD::ROTR, MVT::v16i32, 1 }, 3158 { ISD::ROTR, MVT::v8i32, 1 }, 3159 { ISD::ROTR, MVT::v4i32, 1 } 3160 }; 3161 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 3162 static const CostTblEntry XOPCostTbl[] = { 3163 { ISD::ROTL, MVT::v4i64, 4 }, 3164 { ISD::ROTL, MVT::v8i32, 4 }, 3165 { ISD::ROTL, MVT::v16i16, 4 }, 3166 { ISD::ROTL, MVT::v32i8, 4 }, 3167 { ISD::ROTL, MVT::v2i64, 1 }, 3168 { ISD::ROTL, MVT::v4i32, 1 }, 3169 { ISD::ROTL, MVT::v8i16, 1 }, 3170 { ISD::ROTL, MVT::v16i8, 1 }, 3171 { ISD::ROTR, MVT::v4i64, 6 }, 3172 { ISD::ROTR, MVT::v8i32, 6 }, 3173 { ISD::ROTR, MVT::v16i16, 6 }, 3174 { ISD::ROTR, MVT::v32i8, 6 }, 3175 { ISD::ROTR, MVT::v2i64, 2 }, 3176 { ISD::ROTR, MVT::v4i32, 2 }, 3177 { ISD::ROTR, MVT::v8i16, 2 }, 3178 { ISD::ROTR, MVT::v16i8, 2 } 3179 }; 3180 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 3181 { ISD::ROTL, MVT::i64, 1 }, 3182 { ISD::ROTR, MVT::i64, 1 }, 3183 { ISD::FSHL, MVT::i64, 4 } 3184 }; 3185 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 3186 { ISD::ROTL, MVT::i32, 1 }, 3187 { ISD::ROTL, MVT::i16, 1 }, 3188 { ISD::ROTL, MVT::i8, 1 }, 3189 { ISD::ROTR, MVT::i32, 1 }, 3190 { ISD::ROTR, MVT::i16, 1 }, 3191 { ISD::ROTR, MVT::i8, 1 }, 3192 { ISD::FSHL, MVT::i32, 4 }, 3193 { ISD::FSHL, MVT::i16, 4 }, 3194 { ISD::FSHL, MVT::i8, 4 } 3195 }; 3196 3197 Intrinsic::ID IID = ICA.getID(); 3198 Type *RetTy = ICA.getReturnType(); 3199 const SmallVectorImpl<const Value *> &Args = ICA.getArgs(); 3200 unsigned ISD = ISD::DELETED_NODE; 3201 switch (IID) { 3202 default: 3203 break; 3204 case Intrinsic::fshl: 3205 ISD = ISD::FSHL; 3206 if (Args[0] == Args[1]) 3207 ISD = ISD::ROTL; 3208 break; 3209 case Intrinsic::fshr: 3210 // FSHR has same costs so don't duplicate. 3211 ISD = ISD::FSHL; 3212 if (Args[0] == Args[1]) 3213 ISD = ISD::ROTR; 3214 break; 3215 } 3216 3217 if (ISD != ISD::DELETED_NODE) { 3218 // Legalize the type. 3219 std::pair<InstructionCost, MVT> LT = 3220 TLI->getTypeLegalizationCost(DL, RetTy); 3221 MVT MTy = LT.second; 3222 3223 // Attempt to lookup cost. 3224 if (ST->hasAVX512()) 3225 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3226 return LT.first * Entry->Cost; 3227 3228 if (ST->hasXOP()) 3229 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3230 return LT.first * Entry->Cost; 3231 3232 if (ST->is64Bit()) 3233 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3234 return LT.first * Entry->Cost; 3235 3236 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3237 return LT.first * Entry->Cost; 3238 } 3239 3240 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3241 } 3242 3243 InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, 3244 unsigned Index) { 3245 static const CostTblEntry SLMCostTbl[] = { 3246 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 3247 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 3248 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 3249 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 3250 }; 3251 3252 assert(Val->isVectorTy() && "This must be a vector type"); 3253 Type *ScalarType = Val->getScalarType(); 3254 int RegisterFileMoveCost = 0; 3255 3256 if (Index != -1U && (Opcode == Instruction::ExtractElement || 3257 Opcode == Instruction::InsertElement)) { 3258 // Legalize the type. 3259 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 3260 3261 // This type is legalized to a scalar type. 3262 if (!LT.second.isVector()) 3263 return 0; 3264 3265 // The type may be split. Normalize the index to the new type. 3266 unsigned NumElts = LT.second.getVectorNumElements(); 3267 unsigned SubNumElts = NumElts; 3268 Index = Index % NumElts; 3269 3270 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 3271 // For inserts, we also need to insert the subvector back. 3272 if (LT.second.getSizeInBits() > 128) { 3273 assert((LT.second.getSizeInBits() % 128) == 0 && "Illegal vector"); 3274 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 3275 SubNumElts = NumElts / NumSubVecs; 3276 if (SubNumElts <= Index) { 3277 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 3278 Index %= SubNumElts; 3279 } 3280 } 3281 3282 if (Index == 0) { 3283 // Floating point scalars are already located in index #0. 3284 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 3285 // true for all. 3286 if (ScalarType->isFloatingPointTy()) 3287 return RegisterFileMoveCost; 3288 3289 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 3290 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 3291 return 1 + RegisterFileMoveCost; 3292 } 3293 3294 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3295 assert(ISD && "Unexpected vector opcode"); 3296 MVT MScalarTy = LT.second.getScalarType(); 3297 if (ST->isSLM()) 3298 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 3299 return Entry->Cost + RegisterFileMoveCost; 3300 3301 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 3302 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3303 (MScalarTy.isInteger() && ST->hasSSE41())) 3304 return 1 + RegisterFileMoveCost; 3305 3306 // Assume insertps is relatively cheap on all targets. 3307 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 3308 Opcode == Instruction::InsertElement) 3309 return 1 + RegisterFileMoveCost; 3310 3311 // For extractions we just need to shuffle the element to index 0, which 3312 // should be very cheap (assume cost = 1). For insertions we need to shuffle 3313 // the elements to its destination. In both cases we must handle the 3314 // subvector move(s). 3315 // If the vector type is already less than 128-bits then don't reduce it. 3316 // TODO: Under what circumstances should we shuffle using the full width? 3317 InstructionCost ShuffleCost = 1; 3318 if (Opcode == Instruction::InsertElement) { 3319 auto *SubTy = cast<VectorType>(Val); 3320 EVT VT = TLI->getValueType(DL, Val); 3321 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 3322 SubTy = FixedVectorType::get(ScalarType, SubNumElts); 3323 ShuffleCost = 3324 getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, None, 0, SubTy); 3325 } 3326 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 3327 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 3328 } 3329 3330 // Add to the base cost if we know that the extracted element of a vector is 3331 // destined to be moved to and used in the integer register file. 3332 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 3333 RegisterFileMoveCost += 1; 3334 3335 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 3336 } 3337 3338 InstructionCost X86TTIImpl::getScalarizationOverhead(VectorType *Ty, 3339 const APInt &DemandedElts, 3340 bool Insert, 3341 bool Extract) { 3342 InstructionCost Cost = 0; 3343 3344 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much 3345 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT. 3346 if (Insert) { 3347 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3348 MVT MScalarTy = LT.second.getScalarType(); 3349 3350 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3351 (MScalarTy.isInteger() && ST->hasSSE41()) || 3352 (MScalarTy == MVT::f32 && ST->hasSSE41())) { 3353 // For types we can insert directly, insertion into 128-bit sub vectors is 3354 // cheap, followed by a cheap chain of concatenations. 3355 if (LT.second.getSizeInBits() <= 128) { 3356 Cost += 3357 BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, false); 3358 } else { 3359 // In each 128-lane, if at least one index is demanded but not all 3360 // indices are demanded and this 128-lane is not the first 128-lane of 3361 // the legalized-vector, then this 128-lane needs a extracti128; If in 3362 // each 128-lane, there is at least one demanded index, this 128-lane 3363 // needs a inserti128. 3364 3365 // The following cases will help you build a better understanding: 3366 // Assume we insert several elements into a v8i32 vector in avx2, 3367 // Case#1: inserting into 1th index needs vpinsrd + inserti128. 3368 // Case#2: inserting into 5th index needs extracti128 + vpinsrd + 3369 // inserti128. 3370 // Case#3: inserting into 4,5,6,7 index needs 4*vpinsrd + inserti128. 3371 const int CostValue = *LT.first.getValue(); 3372 assert(CostValue >= 0 && "Negative cost!"); 3373 unsigned Num128Lanes = LT.second.getSizeInBits() / 128 * CostValue; 3374 unsigned NumElts = LT.second.getVectorNumElements() * CostValue; 3375 APInt WidenedDemandedElts = DemandedElts.zextOrSelf(NumElts); 3376 unsigned Scale = NumElts / Num128Lanes; 3377 // We iterate each 128-lane, and check if we need a 3378 // extracti128/inserti128 for this 128-lane. 3379 for (unsigned I = 0; I < NumElts; I += Scale) { 3380 APInt Mask = WidenedDemandedElts.getBitsSet(NumElts, I, I + Scale); 3381 APInt MaskedDE = Mask & WidenedDemandedElts; 3382 unsigned Population = MaskedDE.countPopulation(); 3383 Cost += (Population > 0 && Population != Scale && 3384 I % LT.second.getVectorNumElements() != 0); 3385 Cost += Population > 0; 3386 } 3387 Cost += DemandedElts.countPopulation(); 3388 3389 // For vXf32 cases, insertion into the 0'th index in each v4f32 3390 // 128-bit vector is free. 3391 // NOTE: This assumes legalization widens vXf32 vectors. 3392 if (MScalarTy == MVT::f32) 3393 for (unsigned i = 0, e = cast<FixedVectorType>(Ty)->getNumElements(); 3394 i < e; i += 4) 3395 if (DemandedElts[i]) 3396 Cost--; 3397 } 3398 } else if (LT.second.isVector()) { 3399 // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded 3400 // integer element as a SCALAR_TO_VECTOR, then we build the vector as a 3401 // series of UNPCK followed by CONCAT_VECTORS - all of these can be 3402 // considered cheap. 3403 if (Ty->isIntOrIntVectorTy()) 3404 Cost += DemandedElts.countPopulation(); 3405 3406 // Get the smaller of the legalized or original pow2-extended number of 3407 // vector elements, which represents the number of unpacks we'll end up 3408 // performing. 3409 unsigned NumElts = LT.second.getVectorNumElements(); 3410 unsigned Pow2Elts = 3411 PowerOf2Ceil(cast<FixedVectorType>(Ty)->getNumElements()); 3412 Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first; 3413 } 3414 } 3415 3416 // TODO: Use default extraction for now, but we should investigate extending this 3417 // to handle repeated subvector extraction. 3418 if (Extract) 3419 Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, false, Extract); 3420 3421 return Cost; 3422 } 3423 3424 InstructionCost X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 3425 MaybeAlign Alignment, 3426 unsigned AddressSpace, 3427 TTI::TargetCostKind CostKind, 3428 const Instruction *I) { 3429 // TODO: Handle other cost kinds. 3430 if (CostKind != TTI::TCK_RecipThroughput) { 3431 if (auto *SI = dyn_cast_or_null<StoreInst>(I)) { 3432 // Store instruction with index and scale costs 2 Uops. 3433 // Check the preceding GEP to identify non-const indices. 3434 if (auto *GEP = dyn_cast<GetElementPtrInst>(SI->getPointerOperand())) { 3435 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3436 return TTI::TCC_Basic * 2; 3437 } 3438 } 3439 return TTI::TCC_Basic; 3440 } 3441 3442 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 3443 "Invalid Opcode"); 3444 // Type legalization can't handle structs 3445 if (TLI->getValueType(DL, Src, true) == MVT::Other) 3446 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3447 CostKind); 3448 3449 // Legalize the type. 3450 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 3451 3452 auto *VTy = dyn_cast<FixedVectorType>(Src); 3453 3454 // Handle the simple case of non-vectors. 3455 // NOTE: this assumes that legalization never creates vector from scalars! 3456 if (!VTy || !LT.second.isVector()) 3457 // Each load/store unit costs 1. 3458 return LT.first * 1; 3459 3460 bool IsLoad = Opcode == Instruction::Load; 3461 3462 Type *EltTy = VTy->getElementType(); 3463 3464 const int EltTyBits = DL.getTypeSizeInBits(EltTy); 3465 3466 InstructionCost Cost = 0; 3467 3468 // Source of truth: how many elements were there in the original IR vector? 3469 const unsigned SrcNumElt = VTy->getNumElements(); 3470 3471 // How far have we gotten? 3472 int NumEltRemaining = SrcNumElt; 3473 // Note that we intentionally capture by-reference, NumEltRemaining changes. 3474 auto NumEltDone = [&]() { return SrcNumElt - NumEltRemaining; }; 3475 3476 const int MaxLegalOpSizeBytes = divideCeil(LT.second.getSizeInBits(), 8); 3477 3478 // Note that even if we can store 64 bits of an XMM, we still operate on XMM. 3479 const unsigned XMMBits = 128; 3480 if (XMMBits % EltTyBits != 0) 3481 // Vector size must be a multiple of the element size. I.e. no padding. 3482 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3483 CostKind); 3484 const int NumEltPerXMM = XMMBits / EltTyBits; 3485 3486 auto *XMMVecTy = FixedVectorType::get(EltTy, NumEltPerXMM); 3487 3488 for (int CurrOpSizeBytes = MaxLegalOpSizeBytes, SubVecEltsLeft = 0; 3489 NumEltRemaining > 0; CurrOpSizeBytes /= 2) { 3490 // How many elements would a single op deal with at once? 3491 if ((8 * CurrOpSizeBytes) % EltTyBits != 0) 3492 // Vector size must be a multiple of the element size. I.e. no padding. 3493 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3494 CostKind); 3495 int CurrNumEltPerOp = (8 * CurrOpSizeBytes) / EltTyBits; 3496 3497 assert(CurrOpSizeBytes > 0 && CurrNumEltPerOp > 0 && "How'd we get here?"); 3498 assert((((NumEltRemaining * EltTyBits) < (2 * 8 * CurrOpSizeBytes)) || 3499 (CurrOpSizeBytes == MaxLegalOpSizeBytes)) && 3500 "Unless we haven't halved the op size yet, " 3501 "we have less than two op's sized units of work left."); 3502 3503 auto *CurrVecTy = CurrNumEltPerOp > NumEltPerXMM 3504 ? FixedVectorType::get(EltTy, CurrNumEltPerOp) 3505 : XMMVecTy; 3506 3507 assert(CurrVecTy->getNumElements() % CurrNumEltPerOp == 0 && 3508 "After halving sizes, the vector elt count is no longer a multiple " 3509 "of number of elements per operation?"); 3510 auto *CoalescedVecTy = 3511 CurrNumEltPerOp == 1 3512 ? CurrVecTy 3513 : FixedVectorType::get( 3514 IntegerType::get(Src->getContext(), 3515 EltTyBits * CurrNumEltPerOp), 3516 CurrVecTy->getNumElements() / CurrNumEltPerOp); 3517 assert(DL.getTypeSizeInBits(CoalescedVecTy) == 3518 DL.getTypeSizeInBits(CurrVecTy) && 3519 "coalesciing elements doesn't change vector width."); 3520 3521 while (NumEltRemaining > 0) { 3522 assert(SubVecEltsLeft >= 0 && "Subreg element count overconsumtion?"); 3523 3524 // Can we use this vector size, as per the remaining element count? 3525 // Iff the vector is naturally aligned, we can do a wide load regardless. 3526 if (NumEltRemaining < CurrNumEltPerOp && 3527 (!IsLoad || Alignment.valueOrOne() < CurrOpSizeBytes) && 3528 CurrOpSizeBytes != 1) 3529 break; // Try smalled vector size. 3530 3531 bool Is0thSubVec = (NumEltDone() % LT.second.getVectorNumElements()) == 0; 3532 3533 // If we have fully processed the previous reg, we need to replenish it. 3534 if (SubVecEltsLeft == 0) { 3535 SubVecEltsLeft += CurrVecTy->getNumElements(); 3536 // And that's free only for the 0'th subvector of a legalized vector. 3537 if (!Is0thSubVec) 3538 Cost += getShuffleCost(IsLoad ? TTI::ShuffleKind::SK_InsertSubvector 3539 : TTI::ShuffleKind::SK_ExtractSubvector, 3540 VTy, None, NumEltDone(), CurrVecTy); 3541 } 3542 3543 // While we can directly load/store ZMM, YMM, and 64-bit halves of XMM, 3544 // for smaller widths (32/16/8) we have to insert/extract them separately. 3545 // Again, it's free for the 0'th subreg (if op is 32/64 bit wide, 3546 // but let's pretend that it is also true for 16/8 bit wide ops...) 3547 if (CurrOpSizeBytes <= 32 / 8 && !Is0thSubVec) { 3548 int NumEltDoneInCurrXMM = NumEltDone() % NumEltPerXMM; 3549 assert(NumEltDoneInCurrXMM % CurrNumEltPerOp == 0 && ""); 3550 int CoalescedVecEltIdx = NumEltDoneInCurrXMM / CurrNumEltPerOp; 3551 APInt DemandedElts = 3552 APInt::getBitsSet(CoalescedVecTy->getNumElements(), 3553 CoalescedVecEltIdx, CoalescedVecEltIdx + 1); 3554 assert(DemandedElts.countPopulation() == 1 && "Inserting single value"); 3555 Cost += getScalarizationOverhead(CoalescedVecTy, DemandedElts, IsLoad, 3556 !IsLoad); 3557 } 3558 3559 // This isn't exactly right. We're using slow unaligned 32-byte accesses 3560 // as a proxy for a double-pumped AVX memory interface such as on 3561 // Sandybridge. 3562 if (CurrOpSizeBytes == 32 && ST->isUnalignedMem32Slow()) 3563 Cost += 2; 3564 else 3565 Cost += 1; 3566 3567 SubVecEltsLeft -= CurrNumEltPerOp; 3568 NumEltRemaining -= CurrNumEltPerOp; 3569 Alignment = commonAlignment(Alignment.valueOrOne(), CurrOpSizeBytes); 3570 } 3571 } 3572 3573 assert(NumEltRemaining <= 0 && "Should have processed all the elements."); 3574 3575 return Cost; 3576 } 3577 3578 InstructionCost 3579 X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, Align Alignment, 3580 unsigned AddressSpace, 3581 TTI::TargetCostKind CostKind) { 3582 bool IsLoad = (Instruction::Load == Opcode); 3583 bool IsStore = (Instruction::Store == Opcode); 3584 3585 auto *SrcVTy = dyn_cast<FixedVectorType>(SrcTy); 3586 if (!SrcVTy) 3587 // To calculate scalar take the regular cost, without mask 3588 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace, CostKind); 3589 3590 unsigned NumElem = SrcVTy->getNumElements(); 3591 auto *MaskTy = 3592 FixedVectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 3593 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, Alignment)) || 3594 (IsStore && !isLegalMaskedStore(SrcVTy, Alignment))) { 3595 // Scalarization 3596 APInt DemandedElts = APInt::getAllOnesValue(NumElem); 3597 InstructionCost MaskSplitCost = 3598 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 3599 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 3600 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr, 3601 CmpInst::BAD_ICMP_PREDICATE, CostKind); 3602 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 3603 InstructionCost MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 3604 InstructionCost ValueSplitCost = 3605 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore); 3606 InstructionCost MemopCost = 3607 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3608 Alignment, AddressSpace, CostKind); 3609 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 3610 } 3611 3612 // Legalize the type. 3613 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3614 auto VT = TLI->getValueType(DL, SrcVTy); 3615 InstructionCost Cost = 0; 3616 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 3617 LT.second.getVectorNumElements() == NumElem) 3618 // Promotion requires extend/truncate for data and a shuffle for mask. 3619 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, None, 0, nullptr) + 3620 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, None, 0, nullptr); 3621 3622 else if (LT.first * LT.second.getVectorNumElements() > NumElem) { 3623 auto *NewMaskTy = FixedVectorType::get(MaskTy->getElementType(), 3624 LT.second.getVectorNumElements()); 3625 // Expanding requires fill mask with zeroes 3626 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, None, 0, MaskTy); 3627 } 3628 3629 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 3630 if (!ST->hasAVX512()) 3631 return Cost + LT.first * (IsLoad ? 2 : 8); 3632 3633 // AVX-512 masked load/store is cheapper 3634 return Cost + LT.first; 3635 } 3636 3637 InstructionCost X86TTIImpl::getAddressComputationCost(Type *Ty, 3638 ScalarEvolution *SE, 3639 const SCEV *Ptr) { 3640 // Address computations in vectorized code with non-consecutive addresses will 3641 // likely result in more instructions compared to scalar code where the 3642 // computation can more often be merged into the index mode. The resulting 3643 // extra micro-ops can significantly decrease throughput. 3644 const unsigned NumVectorInstToHideOverhead = 10; 3645 3646 // Cost modeling of Strided Access Computation is hidden by the indexing 3647 // modes of X86 regardless of the stride value. We dont believe that there 3648 // is a difference between constant strided access in gerenal and constant 3649 // strided value which is less than or equal to 64. 3650 // Even in the case of (loop invariant) stride whose value is not known at 3651 // compile time, the address computation will not incur more than one extra 3652 // ADD instruction. 3653 if (Ty->isVectorTy() && SE) { 3654 if (!BaseT::isStridedAccess(Ptr)) 3655 return NumVectorInstToHideOverhead; 3656 if (!BaseT::getConstantStrideStep(SE, Ptr)) 3657 return 1; 3658 } 3659 3660 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 3661 } 3662 3663 InstructionCost 3664 X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 3665 bool IsPairwise, 3666 TTI::TargetCostKind CostKind) { 3667 // Just use the default implementation for pair reductions. 3668 if (IsPairwise) 3669 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise, CostKind); 3670 3671 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3672 // and make it as the cost. 3673 3674 static const CostTblEntry SLMCostTblNoPairWise[] = { 3675 { ISD::FADD, MVT::v2f64, 3 }, 3676 { ISD::ADD, MVT::v2i64, 5 }, 3677 }; 3678 3679 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3680 { ISD::FADD, MVT::v2f64, 2 }, 3681 { ISD::FADD, MVT::v2f32, 2 }, 3682 { ISD::FADD, MVT::v4f32, 4 }, 3683 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 3684 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 3685 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 3686 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 3687 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 3688 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 3689 { ISD::ADD, MVT::v2i8, 2 }, 3690 { ISD::ADD, MVT::v4i8, 2 }, 3691 { ISD::ADD, MVT::v8i8, 2 }, 3692 { ISD::ADD, MVT::v16i8, 3 }, 3693 }; 3694 3695 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3696 { ISD::FADD, MVT::v4f64, 3 }, 3697 { ISD::FADD, MVT::v4f32, 3 }, 3698 { ISD::FADD, MVT::v8f32, 4 }, 3699 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 3700 { ISD::ADD, MVT::v4i64, 3 }, 3701 { ISD::ADD, MVT::v8i32, 5 }, 3702 { ISD::ADD, MVT::v16i16, 5 }, 3703 { ISD::ADD, MVT::v32i8, 4 }, 3704 }; 3705 3706 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3707 assert(ISD && "Invalid opcode"); 3708 3709 // Before legalizing the type, give a chance to look up illegal narrow types 3710 // in the table. 3711 // FIXME: Is there a better way to do this? 3712 EVT VT = TLI->getValueType(DL, ValTy); 3713 if (VT.isSimple()) { 3714 MVT MTy = VT.getSimpleVT(); 3715 if (ST->isSLM()) 3716 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3717 return Entry->Cost; 3718 3719 if (ST->hasAVX()) 3720 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3721 return Entry->Cost; 3722 3723 if (ST->hasSSE2()) 3724 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3725 return Entry->Cost; 3726 } 3727 3728 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3729 3730 MVT MTy = LT.second; 3731 3732 auto *ValVTy = cast<FixedVectorType>(ValTy); 3733 3734 // Special case: vXi8 mul reductions are performed as vXi16. 3735 if (ISD == ISD::MUL && MTy.getScalarType() == MVT::i8) { 3736 auto *WideSclTy = IntegerType::get(ValVTy->getContext(), 16); 3737 auto *WideVecTy = FixedVectorType::get(WideSclTy, ValVTy->getNumElements()); 3738 return getCastInstrCost(Instruction::ZExt, WideVecTy, ValTy, 3739 TargetTransformInfo::CastContextHint::None, 3740 CostKind) + 3741 getArithmeticReductionCost(Opcode, WideVecTy, IsPairwise, CostKind); 3742 } 3743 3744 InstructionCost ArithmeticCost = 0; 3745 if (LT.first != 1 && MTy.isVector() && 3746 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3747 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3748 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3749 MTy.getVectorNumElements()); 3750 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3751 ArithmeticCost *= LT.first - 1; 3752 } 3753 3754 if (ST->isSLM()) 3755 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3756 return ArithmeticCost + Entry->Cost; 3757 3758 if (ST->hasAVX()) 3759 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3760 return ArithmeticCost + Entry->Cost; 3761 3762 if (ST->hasSSE2()) 3763 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3764 return ArithmeticCost + Entry->Cost; 3765 3766 // FIXME: These assume a naive kshift+binop lowering, which is probably 3767 // conservative in most cases. 3768 static const CostTblEntry AVX512BoolReduction[] = { 3769 { ISD::AND, MVT::v2i1, 3 }, 3770 { ISD::AND, MVT::v4i1, 5 }, 3771 { ISD::AND, MVT::v8i1, 7 }, 3772 { ISD::AND, MVT::v16i1, 9 }, 3773 { ISD::AND, MVT::v32i1, 11 }, 3774 { ISD::AND, MVT::v64i1, 13 }, 3775 { ISD::OR, MVT::v2i1, 3 }, 3776 { ISD::OR, MVT::v4i1, 5 }, 3777 { ISD::OR, MVT::v8i1, 7 }, 3778 { ISD::OR, MVT::v16i1, 9 }, 3779 { ISD::OR, MVT::v32i1, 11 }, 3780 { ISD::OR, MVT::v64i1, 13 }, 3781 }; 3782 3783 static const CostTblEntry AVX2BoolReduction[] = { 3784 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 3785 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 3786 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 3787 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 3788 }; 3789 3790 static const CostTblEntry AVX1BoolReduction[] = { 3791 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 3792 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 3793 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3794 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3795 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 3796 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 3797 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3798 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3799 }; 3800 3801 static const CostTblEntry SSE2BoolReduction[] = { 3802 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 3803 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 3804 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 3805 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 3806 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 3807 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 3808 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 3809 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 3810 }; 3811 3812 // Handle bool allof/anyof patterns. 3813 if (ValVTy->getElementType()->isIntegerTy(1)) { 3814 InstructionCost ArithmeticCost = 0; 3815 if (LT.first != 1 && MTy.isVector() && 3816 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3817 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3818 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3819 MTy.getVectorNumElements()); 3820 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3821 ArithmeticCost *= LT.first - 1; 3822 } 3823 3824 if (ST->hasAVX512()) 3825 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 3826 return ArithmeticCost + Entry->Cost; 3827 if (ST->hasAVX2()) 3828 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 3829 return ArithmeticCost + Entry->Cost; 3830 if (ST->hasAVX()) 3831 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 3832 return ArithmeticCost + Entry->Cost; 3833 if (ST->hasSSE2()) 3834 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 3835 return ArithmeticCost + Entry->Cost; 3836 3837 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise, 3838 CostKind); 3839 } 3840 3841 unsigned NumVecElts = ValVTy->getNumElements(); 3842 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 3843 3844 // Special case power of 2 reductions where the scalar type isn't changed 3845 // by type legalization. 3846 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 3847 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise, 3848 CostKind); 3849 3850 InstructionCost ReductionCost = 0; 3851 3852 auto *Ty = ValVTy; 3853 if (LT.first != 1 && MTy.isVector() && 3854 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3855 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3856 Ty = FixedVectorType::get(ValVTy->getElementType(), 3857 MTy.getVectorNumElements()); 3858 ReductionCost = getArithmeticInstrCost(Opcode, Ty, CostKind); 3859 ReductionCost *= LT.first - 1; 3860 NumVecElts = MTy.getVectorNumElements(); 3861 } 3862 3863 // Now handle reduction with the legal type, taking into account size changes 3864 // at each level. 3865 while (NumVecElts > 1) { 3866 // Determine the size of the remaining vector we need to reduce. 3867 unsigned Size = NumVecElts * ScalarSize; 3868 NumVecElts /= 2; 3869 // If we're reducing from 256/512 bits, use an extract_subvector. 3870 if (Size > 128) { 3871 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 3872 ReductionCost += 3873 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 3874 Ty = SubTy; 3875 } else if (Size == 128) { 3876 // Reducing from 128 bits is a permute of v2f64/v2i64. 3877 FixedVectorType *ShufTy; 3878 if (ValVTy->isFloatingPointTy()) 3879 ShufTy = 3880 FixedVectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 3881 else 3882 ShufTy = 3883 FixedVectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 3884 ReductionCost += 3885 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3886 } else if (Size == 64) { 3887 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3888 FixedVectorType *ShufTy; 3889 if (ValVTy->isFloatingPointTy()) 3890 ShufTy = 3891 FixedVectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 3892 else 3893 ShufTy = 3894 FixedVectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 3895 ReductionCost += 3896 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3897 } else { 3898 // Reducing from smaller size is a shift by immediate. 3899 auto *ShiftTy = FixedVectorType::get( 3900 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 3901 ReductionCost += getArithmeticInstrCost( 3902 Instruction::LShr, ShiftTy, CostKind, 3903 TargetTransformInfo::OK_AnyValue, 3904 TargetTransformInfo::OK_UniformConstantValue, 3905 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3906 } 3907 3908 // Add the arithmetic op for this level. 3909 ReductionCost += getArithmeticInstrCost(Opcode, Ty, CostKind); 3910 } 3911 3912 // Add the final extract element to the cost. 3913 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3914 } 3915 3916 InstructionCost X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, 3917 bool IsUnsigned) { 3918 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3919 3920 MVT MTy = LT.second; 3921 3922 int ISD; 3923 if (Ty->isIntOrIntVectorTy()) { 3924 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3925 } else { 3926 assert(Ty->isFPOrFPVectorTy() && 3927 "Expected float point or integer vector type."); 3928 ISD = ISD::FMINNUM; 3929 } 3930 3931 static const CostTblEntry SSE1CostTbl[] = { 3932 {ISD::FMINNUM, MVT::v4f32, 1}, 3933 }; 3934 3935 static const CostTblEntry SSE2CostTbl[] = { 3936 {ISD::FMINNUM, MVT::v2f64, 1}, 3937 {ISD::SMIN, MVT::v8i16, 1}, 3938 {ISD::UMIN, MVT::v16i8, 1}, 3939 }; 3940 3941 static const CostTblEntry SSE41CostTbl[] = { 3942 {ISD::SMIN, MVT::v4i32, 1}, 3943 {ISD::UMIN, MVT::v4i32, 1}, 3944 {ISD::UMIN, MVT::v8i16, 1}, 3945 {ISD::SMIN, MVT::v16i8, 1}, 3946 }; 3947 3948 static const CostTblEntry SSE42CostTbl[] = { 3949 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 3950 }; 3951 3952 static const CostTblEntry AVX1CostTbl[] = { 3953 {ISD::FMINNUM, MVT::v8f32, 1}, 3954 {ISD::FMINNUM, MVT::v4f64, 1}, 3955 {ISD::SMIN, MVT::v8i32, 3}, 3956 {ISD::UMIN, MVT::v8i32, 3}, 3957 {ISD::SMIN, MVT::v16i16, 3}, 3958 {ISD::UMIN, MVT::v16i16, 3}, 3959 {ISD::SMIN, MVT::v32i8, 3}, 3960 {ISD::UMIN, MVT::v32i8, 3}, 3961 }; 3962 3963 static const CostTblEntry AVX2CostTbl[] = { 3964 {ISD::SMIN, MVT::v8i32, 1}, 3965 {ISD::UMIN, MVT::v8i32, 1}, 3966 {ISD::SMIN, MVT::v16i16, 1}, 3967 {ISD::UMIN, MVT::v16i16, 1}, 3968 {ISD::SMIN, MVT::v32i8, 1}, 3969 {ISD::UMIN, MVT::v32i8, 1}, 3970 }; 3971 3972 static const CostTblEntry AVX512CostTbl[] = { 3973 {ISD::FMINNUM, MVT::v16f32, 1}, 3974 {ISD::FMINNUM, MVT::v8f64, 1}, 3975 {ISD::SMIN, MVT::v2i64, 1}, 3976 {ISD::UMIN, MVT::v2i64, 1}, 3977 {ISD::SMIN, MVT::v4i64, 1}, 3978 {ISD::UMIN, MVT::v4i64, 1}, 3979 {ISD::SMIN, MVT::v8i64, 1}, 3980 {ISD::UMIN, MVT::v8i64, 1}, 3981 {ISD::SMIN, MVT::v16i32, 1}, 3982 {ISD::UMIN, MVT::v16i32, 1}, 3983 }; 3984 3985 static const CostTblEntry AVX512BWCostTbl[] = { 3986 {ISD::SMIN, MVT::v32i16, 1}, 3987 {ISD::UMIN, MVT::v32i16, 1}, 3988 {ISD::SMIN, MVT::v64i8, 1}, 3989 {ISD::UMIN, MVT::v64i8, 1}, 3990 }; 3991 3992 // If we have a native MIN/MAX instruction for this type, use it. 3993 if (ST->hasBWI()) 3994 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3995 return LT.first * Entry->Cost; 3996 3997 if (ST->hasAVX512()) 3998 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3999 return LT.first * Entry->Cost; 4000 4001 if (ST->hasAVX2()) 4002 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 4003 return LT.first * Entry->Cost; 4004 4005 if (ST->hasAVX()) 4006 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 4007 return LT.first * Entry->Cost; 4008 4009 if (ST->hasSSE42()) 4010 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 4011 return LT.first * Entry->Cost; 4012 4013 if (ST->hasSSE41()) 4014 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 4015 return LT.first * Entry->Cost; 4016 4017 if (ST->hasSSE2()) 4018 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 4019 return LT.first * Entry->Cost; 4020 4021 if (ST->hasSSE1()) 4022 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 4023 return LT.first * Entry->Cost; 4024 4025 unsigned CmpOpcode; 4026 if (Ty->isFPOrFPVectorTy()) { 4027 CmpOpcode = Instruction::FCmp; 4028 } else { 4029 assert(Ty->isIntOrIntVectorTy() && 4030 "expecting floating point or integer type for min/max reduction"); 4031 CmpOpcode = Instruction::ICmp; 4032 } 4033 4034 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4035 // Otherwise fall back to cmp+select. 4036 InstructionCost Result = 4037 getCmpSelInstrCost(CmpOpcode, Ty, CondTy, CmpInst::BAD_ICMP_PREDICATE, 4038 CostKind) + 4039 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, 4040 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4041 return Result; 4042 } 4043 4044 InstructionCost 4045 X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 4046 bool IsPairwise, bool IsUnsigned, 4047 TTI::TargetCostKind CostKind) { 4048 // Just use the default implementation for pair reductions. 4049 if (IsPairwise) 4050 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned, 4051 CostKind); 4052 4053 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 4054 4055 MVT MTy = LT.second; 4056 4057 int ISD; 4058 if (ValTy->isIntOrIntVectorTy()) { 4059 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 4060 } else { 4061 assert(ValTy->isFPOrFPVectorTy() && 4062 "Expected float point or integer vector type."); 4063 ISD = ISD::FMINNUM; 4064 } 4065 4066 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 4067 // and make it as the cost. 4068 4069 static const CostTblEntry SSE2CostTblNoPairWise[] = { 4070 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 4071 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 4072 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 4073 }; 4074 4075 static const CostTblEntry SSE41CostTblNoPairWise[] = { 4076 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 4077 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 4078 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 4079 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 4080 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 4081 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 4082 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 4083 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 4084 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 4085 {ISD::SMIN, MVT::v16i8, 6}, 4086 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 4087 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 4088 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 4089 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 4090 }; 4091 4092 static const CostTblEntry AVX1CostTblNoPairWise[] = { 4093 {ISD::SMIN, MVT::v16i16, 6}, 4094 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 4095 {ISD::SMIN, MVT::v32i8, 8}, 4096 {ISD::UMIN, MVT::v32i8, 8}, 4097 }; 4098 4099 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 4100 {ISD::SMIN, MVT::v32i16, 8}, 4101 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 4102 {ISD::SMIN, MVT::v64i8, 10}, 4103 {ISD::UMIN, MVT::v64i8, 10}, 4104 }; 4105 4106 // Before legalizing the type, give a chance to look up illegal narrow types 4107 // in the table. 4108 // FIXME: Is there a better way to do this? 4109 EVT VT = TLI->getValueType(DL, ValTy); 4110 if (VT.isSimple()) { 4111 MVT MTy = VT.getSimpleVT(); 4112 if (ST->hasBWI()) 4113 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4114 return Entry->Cost; 4115 4116 if (ST->hasAVX()) 4117 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4118 return Entry->Cost; 4119 4120 if (ST->hasSSE41()) 4121 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4122 return Entry->Cost; 4123 4124 if (ST->hasSSE2()) 4125 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4126 return Entry->Cost; 4127 } 4128 4129 auto *ValVTy = cast<FixedVectorType>(ValTy); 4130 unsigned NumVecElts = ValVTy->getNumElements(); 4131 4132 auto *Ty = ValVTy; 4133 InstructionCost MinMaxCost = 0; 4134 if (LT.first != 1 && MTy.isVector() && 4135 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4136 // Type needs to be split. We need LT.first - 1 operations ops. 4137 Ty = FixedVectorType::get(ValVTy->getElementType(), 4138 MTy.getVectorNumElements()); 4139 auto *SubCondTy = FixedVectorType::get(CondTy->getElementType(), 4140 MTy.getVectorNumElements()); 4141 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4142 MinMaxCost *= LT.first - 1; 4143 NumVecElts = MTy.getVectorNumElements(); 4144 } 4145 4146 if (ST->hasBWI()) 4147 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4148 return MinMaxCost + Entry->Cost; 4149 4150 if (ST->hasAVX()) 4151 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4152 return MinMaxCost + Entry->Cost; 4153 4154 if (ST->hasSSE41()) 4155 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4156 return MinMaxCost + Entry->Cost; 4157 4158 if (ST->hasSSE2()) 4159 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4160 return MinMaxCost + Entry->Cost; 4161 4162 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 4163 4164 // Special case power of 2 reductions where the scalar type isn't changed 4165 // by type legalization. 4166 if (!isPowerOf2_32(ValVTy->getNumElements()) || 4167 ScalarSize != MTy.getScalarSizeInBits()) 4168 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned, 4169 CostKind); 4170 4171 // Now handle reduction with the legal type, taking into account size changes 4172 // at each level. 4173 while (NumVecElts > 1) { 4174 // Determine the size of the remaining vector we need to reduce. 4175 unsigned Size = NumVecElts * ScalarSize; 4176 NumVecElts /= 2; 4177 // If we're reducing from 256/512 bits, use an extract_subvector. 4178 if (Size > 128) { 4179 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 4180 MinMaxCost += 4181 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 4182 Ty = SubTy; 4183 } else if (Size == 128) { 4184 // Reducing from 128 bits is a permute of v2f64/v2i64. 4185 VectorType *ShufTy; 4186 if (ValTy->isFloatingPointTy()) 4187 ShufTy = 4188 FixedVectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 4189 else 4190 ShufTy = FixedVectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 4191 MinMaxCost += 4192 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4193 } else if (Size == 64) { 4194 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 4195 FixedVectorType *ShufTy; 4196 if (ValTy->isFloatingPointTy()) 4197 ShufTy = FixedVectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 4198 else 4199 ShufTy = FixedVectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 4200 MinMaxCost += 4201 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4202 } else { 4203 // Reducing from smaller size is a shift by immediate. 4204 auto *ShiftTy = FixedVectorType::get( 4205 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 4206 MinMaxCost += getArithmeticInstrCost( 4207 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, 4208 TargetTransformInfo::OK_AnyValue, 4209 TargetTransformInfo::OK_UniformConstantValue, 4210 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 4211 } 4212 4213 // Add the arithmetic op for this level. 4214 auto *SubCondTy = 4215 FixedVectorType::get(CondTy->getElementType(), Ty->getNumElements()); 4216 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4217 } 4218 4219 // Add the final extract element to the cost. 4220 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 4221 } 4222 4223 /// Calculate the cost of materializing a 64-bit value. This helper 4224 /// method might only calculate a fraction of a larger immediate. Therefore it 4225 /// is valid to return a cost of ZERO. 4226 InstructionCost X86TTIImpl::getIntImmCost(int64_t Val) { 4227 if (Val == 0) 4228 return TTI::TCC_Free; 4229 4230 if (isInt<32>(Val)) 4231 return TTI::TCC_Basic; 4232 4233 return 2 * TTI::TCC_Basic; 4234 } 4235 4236 InstructionCost X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 4237 TTI::TargetCostKind CostKind) { 4238 assert(Ty->isIntegerTy()); 4239 4240 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4241 if (BitSize == 0) 4242 return ~0U; 4243 4244 // Never hoist constants larger than 128bit, because this might lead to 4245 // incorrect code generation or assertions in codegen. 4246 // Fixme: Create a cost model for types larger than i128 once the codegen 4247 // issues have been fixed. 4248 if (BitSize > 128) 4249 return TTI::TCC_Free; 4250 4251 if (Imm == 0) 4252 return TTI::TCC_Free; 4253 4254 // Sign-extend all constants to a multiple of 64-bit. 4255 APInt ImmVal = Imm; 4256 if (BitSize % 64 != 0) 4257 ImmVal = Imm.sext(alignTo(BitSize, 64)); 4258 4259 // Split the constant into 64-bit chunks and calculate the cost for each 4260 // chunk. 4261 InstructionCost Cost = 0; 4262 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 4263 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 4264 int64_t Val = Tmp.getSExtValue(); 4265 Cost += getIntImmCost(Val); 4266 } 4267 // We need at least one instruction to materialize the constant. 4268 return std::max<InstructionCost>(1, Cost); 4269 } 4270 4271 InstructionCost X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, 4272 const APInt &Imm, Type *Ty, 4273 TTI::TargetCostKind CostKind, 4274 Instruction *Inst) { 4275 assert(Ty->isIntegerTy()); 4276 4277 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4278 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4279 // here, so that constant hoisting will ignore this constant. 4280 if (BitSize == 0) 4281 return TTI::TCC_Free; 4282 4283 unsigned ImmIdx = ~0U; 4284 switch (Opcode) { 4285 default: 4286 return TTI::TCC_Free; 4287 case Instruction::GetElementPtr: 4288 // Always hoist the base address of a GetElementPtr. This prevents the 4289 // creation of new constants for every base constant that gets constant 4290 // folded with the offset. 4291 if (Idx == 0) 4292 return 2 * TTI::TCC_Basic; 4293 return TTI::TCC_Free; 4294 case Instruction::Store: 4295 ImmIdx = 0; 4296 break; 4297 case Instruction::ICmp: 4298 // This is an imperfect hack to prevent constant hoisting of 4299 // compares that might be trying to check if a 64-bit value fits in 4300 // 32-bits. The backend can optimize these cases using a right shift by 32. 4301 // Ideally we would check the compare predicate here. There also other 4302 // similar immediates the backend can use shifts for. 4303 if (Idx == 1 && Imm.getBitWidth() == 64) { 4304 uint64_t ImmVal = Imm.getZExtValue(); 4305 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 4306 return TTI::TCC_Free; 4307 } 4308 ImmIdx = 1; 4309 break; 4310 case Instruction::And: 4311 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 4312 // by using a 32-bit operation with implicit zero extension. Detect such 4313 // immediates here as the normal path expects bit 31 to be sign extended. 4314 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 4315 return TTI::TCC_Free; 4316 ImmIdx = 1; 4317 break; 4318 case Instruction::Add: 4319 case Instruction::Sub: 4320 // For add/sub, we can use the opposite instruction for INT32_MIN. 4321 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 4322 return TTI::TCC_Free; 4323 ImmIdx = 1; 4324 break; 4325 case Instruction::UDiv: 4326 case Instruction::SDiv: 4327 case Instruction::URem: 4328 case Instruction::SRem: 4329 // Division by constant is typically expanded later into a different 4330 // instruction sequence. This completely changes the constants. 4331 // Report them as "free" to stop ConstantHoist from marking them as opaque. 4332 return TTI::TCC_Free; 4333 case Instruction::Mul: 4334 case Instruction::Or: 4335 case Instruction::Xor: 4336 ImmIdx = 1; 4337 break; 4338 // Always return TCC_Free for the shift value of a shift instruction. 4339 case Instruction::Shl: 4340 case Instruction::LShr: 4341 case Instruction::AShr: 4342 if (Idx == 1) 4343 return TTI::TCC_Free; 4344 break; 4345 case Instruction::Trunc: 4346 case Instruction::ZExt: 4347 case Instruction::SExt: 4348 case Instruction::IntToPtr: 4349 case Instruction::PtrToInt: 4350 case Instruction::BitCast: 4351 case Instruction::PHI: 4352 case Instruction::Call: 4353 case Instruction::Select: 4354 case Instruction::Ret: 4355 case Instruction::Load: 4356 break; 4357 } 4358 4359 if (Idx == ImmIdx) { 4360 int NumConstants = divideCeil(BitSize, 64); 4361 InstructionCost Cost = X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4362 return (Cost <= NumConstants * TTI::TCC_Basic) 4363 ? static_cast<int>(TTI::TCC_Free) 4364 : Cost; 4365 } 4366 4367 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4368 } 4369 4370 InstructionCost X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 4371 const APInt &Imm, Type *Ty, 4372 TTI::TargetCostKind CostKind) { 4373 assert(Ty->isIntegerTy()); 4374 4375 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4376 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4377 // here, so that constant hoisting will ignore this constant. 4378 if (BitSize == 0) 4379 return TTI::TCC_Free; 4380 4381 switch (IID) { 4382 default: 4383 return TTI::TCC_Free; 4384 case Intrinsic::sadd_with_overflow: 4385 case Intrinsic::uadd_with_overflow: 4386 case Intrinsic::ssub_with_overflow: 4387 case Intrinsic::usub_with_overflow: 4388 case Intrinsic::smul_with_overflow: 4389 case Intrinsic::umul_with_overflow: 4390 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 4391 return TTI::TCC_Free; 4392 break; 4393 case Intrinsic::experimental_stackmap: 4394 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4395 return TTI::TCC_Free; 4396 break; 4397 case Intrinsic::experimental_patchpoint_void: 4398 case Intrinsic::experimental_patchpoint_i64: 4399 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4400 return TTI::TCC_Free; 4401 break; 4402 } 4403 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4404 } 4405 4406 InstructionCost X86TTIImpl::getCFInstrCost(unsigned Opcode, 4407 TTI::TargetCostKind CostKind, 4408 const Instruction *I) { 4409 if (CostKind != TTI::TCK_RecipThroughput) 4410 return Opcode == Instruction::PHI ? 0 : 1; 4411 // Branches are assumed to be predicted. 4412 return 0; 4413 } 4414 4415 int X86TTIImpl::getGatherOverhead() const { 4416 // Some CPUs have more overhead for gather. The specified overhead is relative 4417 // to the Load operation. "2" is the number provided by Intel architects. This 4418 // parameter is used for cost estimation of Gather Op and comparison with 4419 // other alternatives. 4420 // TODO: Remove the explicit hasAVX512()?, That would mean we would only 4421 // enable gather with a -march. 4422 if (ST->hasAVX512() || (ST->hasAVX2() && ST->hasFastGather())) 4423 return 2; 4424 4425 return 1024; 4426 } 4427 4428 int X86TTIImpl::getScatterOverhead() const { 4429 if (ST->hasAVX512()) 4430 return 2; 4431 4432 return 1024; 4433 } 4434 4435 // Return an average cost of Gather / Scatter instruction, maybe improved later. 4436 // FIXME: Add TargetCostKind support. 4437 InstructionCost X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, 4438 const Value *Ptr, Align Alignment, 4439 unsigned AddressSpace) { 4440 4441 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 4442 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4443 4444 // Try to reduce index size from 64 bit (default for GEP) 4445 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 4446 // operation will use 16 x 64 indices which do not fit in a zmm and needs 4447 // to split. Also check that the base pointer is the same for all lanes, 4448 // and that there's at most one variable index. 4449 auto getIndexSizeInBits = [](const Value *Ptr, const DataLayout &DL) { 4450 unsigned IndexSize = DL.getPointerSizeInBits(); 4451 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 4452 if (IndexSize < 64 || !GEP) 4453 return IndexSize; 4454 4455 unsigned NumOfVarIndices = 0; 4456 const Value *Ptrs = GEP->getPointerOperand(); 4457 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 4458 return IndexSize; 4459 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 4460 if (isa<Constant>(GEP->getOperand(i))) 4461 continue; 4462 Type *IndxTy = GEP->getOperand(i)->getType(); 4463 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 4464 IndxTy = IndexVTy->getElementType(); 4465 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 4466 !isa<SExtInst>(GEP->getOperand(i))) || 4467 ++NumOfVarIndices > 1) 4468 return IndexSize; // 64 4469 } 4470 return (unsigned)32; 4471 }; 4472 4473 // Trying to reduce IndexSize to 32 bits for vector 16. 4474 // By default the IndexSize is equal to pointer size. 4475 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 4476 ? getIndexSizeInBits(Ptr, DL) 4477 : DL.getPointerSizeInBits(); 4478 4479 auto *IndexVTy = FixedVectorType::get( 4480 IntegerType::get(SrcVTy->getContext(), IndexSize), VF); 4481 std::pair<InstructionCost, MVT> IdxsLT = 4482 TLI->getTypeLegalizationCost(DL, IndexVTy); 4483 std::pair<InstructionCost, MVT> SrcLT = 4484 TLI->getTypeLegalizationCost(DL, SrcVTy); 4485 InstructionCost::CostType SplitFactor = 4486 *std::max(IdxsLT.first, SrcLT.first).getValue(); 4487 if (SplitFactor > 1) { 4488 // Handle splitting of vector of pointers 4489 auto *SplitSrcTy = 4490 FixedVectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 4491 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 4492 AddressSpace); 4493 } 4494 4495 // The gather / scatter cost is given by Intel architects. It is a rough 4496 // number since we are looking at one instruction in a time. 4497 const int GSOverhead = (Opcode == Instruction::Load) 4498 ? getGatherOverhead() 4499 : getScatterOverhead(); 4500 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4501 MaybeAlign(Alignment), AddressSpace, 4502 TTI::TCK_RecipThroughput); 4503 } 4504 4505 /// Return the cost of full scalarization of gather / scatter operation. 4506 /// 4507 /// Opcode - Load or Store instruction. 4508 /// SrcVTy - The type of the data vector that should be gathered or scattered. 4509 /// VariableMask - The mask is non-constant at compile time. 4510 /// Alignment - Alignment for one element. 4511 /// AddressSpace - pointer[s] address space. 4512 /// 4513 /// FIXME: Add TargetCostKind support. 4514 InstructionCost X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 4515 bool VariableMask, Align Alignment, 4516 unsigned AddressSpace) { 4517 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4518 APInt DemandedElts = APInt::getAllOnesValue(VF); 4519 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4520 4521 InstructionCost MaskUnpackCost = 0; 4522 if (VariableMask) { 4523 auto *MaskTy = 4524 FixedVectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 4525 MaskUnpackCost = 4526 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 4527 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 4528 Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), nullptr, 4529 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4530 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 4531 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 4532 } 4533 4534 // The cost of the scalar loads/stores. 4535 InstructionCost MemoryOpCost = 4536 VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4537 MaybeAlign(Alignment), AddressSpace, CostKind); 4538 4539 InstructionCost InsertExtractCost = 0; 4540 if (Opcode == Instruction::Load) 4541 for (unsigned i = 0; i < VF; ++i) 4542 // Add the cost of inserting each scalar load into the vector 4543 InsertExtractCost += 4544 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 4545 else 4546 for (unsigned i = 0; i < VF; ++i) 4547 // Add the cost of extracting each element out of the data vector 4548 InsertExtractCost += 4549 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 4550 4551 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 4552 } 4553 4554 /// Calculate the cost of Gather / Scatter operation 4555 InstructionCost X86TTIImpl::getGatherScatterOpCost( 4556 unsigned Opcode, Type *SrcVTy, const Value *Ptr, bool VariableMask, 4557 Align Alignment, TTI::TargetCostKind CostKind, 4558 const Instruction *I = nullptr) { 4559 if (CostKind != TTI::TCK_RecipThroughput) { 4560 if ((Opcode == Instruction::Load && 4561 isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4562 (Opcode == Instruction::Store && 4563 isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4564 return 1; 4565 return BaseT::getGatherScatterOpCost(Opcode, SrcVTy, Ptr, VariableMask, 4566 Alignment, CostKind, I); 4567 } 4568 4569 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 4570 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4571 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 4572 if (!PtrTy && Ptr->getType()->isVectorTy()) 4573 PtrTy = dyn_cast<PointerType>( 4574 cast<VectorType>(Ptr->getType())->getElementType()); 4575 assert(PtrTy && "Unexpected type for Ptr argument"); 4576 unsigned AddressSpace = PtrTy->getAddressSpace(); 4577 4578 bool Scalarize = false; 4579 if ((Opcode == Instruction::Load && 4580 !isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4581 (Opcode == Instruction::Store && 4582 !isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4583 Scalarize = true; 4584 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 4585 // Vector-4 of gather/scatter instruction does not exist on KNL. 4586 // We can extend it to 8 elements, but zeroing upper bits of 4587 // the mask vector will add more instructions. Right now we give the scalar 4588 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 4589 // is better in the VariableMask case. 4590 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 4591 Scalarize = true; 4592 4593 if (Scalarize) 4594 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 4595 AddressSpace); 4596 4597 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 4598 } 4599 4600 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 4601 TargetTransformInfo::LSRCost &C2) { 4602 // X86 specific here are "instruction number 1st priority". 4603 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 4604 C1.NumIVMuls, C1.NumBaseAdds, 4605 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 4606 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 4607 C2.NumIVMuls, C2.NumBaseAdds, 4608 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 4609 } 4610 4611 bool X86TTIImpl::canMacroFuseCmp() { 4612 return ST->hasMacroFusion() || ST->hasBranchFusion(); 4613 } 4614 4615 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, Align Alignment) { 4616 if (!ST->hasAVX()) 4617 return false; 4618 4619 // The backend can't handle a single element vector. 4620 if (isa<VectorType>(DataTy) && 4621 cast<FixedVectorType>(DataTy)->getNumElements() == 1) 4622 return false; 4623 Type *ScalarTy = DataTy->getScalarType(); 4624 4625 if (ScalarTy->isPointerTy()) 4626 return true; 4627 4628 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4629 return true; 4630 4631 if (!ScalarTy->isIntegerTy()) 4632 return false; 4633 4634 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4635 return IntWidth == 32 || IntWidth == 64 || 4636 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 4637 } 4638 4639 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, Align Alignment) { 4640 return isLegalMaskedLoad(DataType, Alignment); 4641 } 4642 4643 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 4644 unsigned DataSize = DL.getTypeStoreSize(DataType); 4645 // The only supported nontemporal loads are for aligned vectors of 16 or 32 4646 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 4647 // (the equivalent stores only require AVX). 4648 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 4649 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 4650 4651 return false; 4652 } 4653 4654 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 4655 unsigned DataSize = DL.getTypeStoreSize(DataType); 4656 4657 // SSE4A supports nontemporal stores of float and double at arbitrary 4658 // alignment. 4659 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 4660 return true; 4661 4662 // Besides the SSE4A subtarget exception above, only aligned stores are 4663 // available nontemporaly on any other subtarget. And only stores with a size 4664 // of 4..32 bytes (powers of 2, only) are permitted. 4665 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 4666 !isPowerOf2_32(DataSize)) 4667 return false; 4668 4669 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 4670 // loads require AVX2). 4671 if (DataSize == 32) 4672 return ST->hasAVX(); 4673 else if (DataSize == 16) 4674 return ST->hasSSE1(); 4675 return true; 4676 } 4677 4678 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 4679 if (!isa<VectorType>(DataTy)) 4680 return false; 4681 4682 if (!ST->hasAVX512()) 4683 return false; 4684 4685 // The backend can't handle a single element vector. 4686 if (cast<FixedVectorType>(DataTy)->getNumElements() == 1) 4687 return false; 4688 4689 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 4690 4691 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4692 return true; 4693 4694 if (!ScalarTy->isIntegerTy()) 4695 return false; 4696 4697 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4698 return IntWidth == 32 || IntWidth == 64 || 4699 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 4700 } 4701 4702 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 4703 return isLegalMaskedExpandLoad(DataTy); 4704 } 4705 4706 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, Align Alignment) { 4707 // Some CPUs have better gather performance than others. 4708 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 4709 // enable gather with a -march. 4710 if (!(ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()))) 4711 return false; 4712 4713 // This function is called now in two cases: from the Loop Vectorizer 4714 // and from the Scalarizer. 4715 // When the Loop Vectorizer asks about legality of the feature, 4716 // the vectorization factor is not calculated yet. The Loop Vectorizer 4717 // sends a scalar type and the decision is based on the width of the 4718 // scalar element. 4719 // Later on, the cost model will estimate usage this intrinsic based on 4720 // the vector type. 4721 // The Scalarizer asks again about legality. It sends a vector type. 4722 // In this case we can reject non-power-of-2 vectors. 4723 // We also reject single element vectors as the type legalizer can't 4724 // scalarize it. 4725 if (auto *DataVTy = dyn_cast<FixedVectorType>(DataTy)) { 4726 unsigned NumElts = DataVTy->getNumElements(); 4727 if (NumElts == 1) 4728 return false; 4729 } 4730 Type *ScalarTy = DataTy->getScalarType(); 4731 if (ScalarTy->isPointerTy()) 4732 return true; 4733 4734 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4735 return true; 4736 4737 if (!ScalarTy->isIntegerTy()) 4738 return false; 4739 4740 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4741 return IntWidth == 32 || IntWidth == 64; 4742 } 4743 4744 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, Align Alignment) { 4745 // AVX2 doesn't support scatter 4746 if (!ST->hasAVX512()) 4747 return false; 4748 return isLegalMaskedGather(DataType, Alignment); 4749 } 4750 4751 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 4752 EVT VT = TLI->getValueType(DL, DataType); 4753 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 4754 } 4755 4756 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 4757 return false; 4758 } 4759 4760 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 4761 const Function *Callee) const { 4762 const TargetMachine &TM = getTLI()->getTargetMachine(); 4763 4764 // Work this as a subsetting of subtarget features. 4765 const FeatureBitset &CallerBits = 4766 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 4767 const FeatureBitset &CalleeBits = 4768 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 4769 4770 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 4771 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 4772 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 4773 } 4774 4775 bool X86TTIImpl::areFunctionArgsABICompatible( 4776 const Function *Caller, const Function *Callee, 4777 SmallPtrSetImpl<Argument *> &Args) const { 4778 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args)) 4779 return false; 4780 4781 // If we get here, we know the target features match. If one function 4782 // considers 512-bit vectors legal and the other does not, consider them 4783 // incompatible. 4784 const TargetMachine &TM = getTLI()->getTargetMachine(); 4785 4786 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 4787 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs()) 4788 return true; 4789 4790 // Consider the arguments compatible if they aren't vectors or aggregates. 4791 // FIXME: Look at the size of vectors. 4792 // FIXME: Look at the element types of aggregates to see if there are vectors. 4793 // FIXME: The API of this function seems intended to allow arguments 4794 // to be removed from the set, but the caller doesn't check if the set 4795 // becomes empty so that may not work in practice. 4796 return llvm::none_of(Args, [](Argument *A) { 4797 auto *EltTy = cast<PointerType>(A->getType())->getElementType(); 4798 return EltTy->isVectorTy() || EltTy->isAggregateType(); 4799 }); 4800 } 4801 4802 X86TTIImpl::TTI::MemCmpExpansionOptions 4803 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 4804 TTI::MemCmpExpansionOptions Options; 4805 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 4806 Options.NumLoadsPerBlock = 2; 4807 // All GPR and vector loads can be unaligned. 4808 Options.AllowOverlappingLoads = true; 4809 if (IsZeroCmp) { 4810 // Only enable vector loads for equality comparison. Right now the vector 4811 // version is not as fast for three way compare (see #33329). 4812 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 4813 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 4814 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 4815 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 4816 } 4817 if (ST->is64Bit()) { 4818 Options.LoadSizes.push_back(8); 4819 } 4820 Options.LoadSizes.push_back(4); 4821 Options.LoadSizes.push_back(2); 4822 Options.LoadSizes.push_back(1); 4823 return Options; 4824 } 4825 4826 bool X86TTIImpl::enableInterleavedAccessVectorization() { 4827 // TODO: We expect this to be beneficial regardless of arch, 4828 // but there are currently some unexplained performance artifacts on Atom. 4829 // As a temporary solution, disable on Atom. 4830 return !(ST->isAtom()); 4831 } 4832 4833 // Get estimation for interleaved load/store operations for AVX2. 4834 // \p Factor is the interleaved-access factor (stride) - number of 4835 // (interleaved) elements in the group. 4836 // \p Indices contains the indices for a strided load: when the 4837 // interleaved load has gaps they indicate which elements are used. 4838 // If Indices is empty (or if the number of indices is equal to the size 4839 // of the interleaved-access as given in \p Factor) the access has no gaps. 4840 // 4841 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 4842 // computing the cost using a generic formula as a function of generic 4843 // shuffles. We therefore use a lookup table instead, filled according to 4844 // the instruction sequences that codegen currently generates. 4845 InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2( 4846 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 4847 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 4848 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 4849 4850 if (UseMaskForCond || UseMaskForGaps) 4851 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4852 Alignment, AddressSpace, CostKind, 4853 UseMaskForCond, UseMaskForGaps); 4854 4855 // We currently Support only fully-interleaved groups, with no gaps. 4856 // TODO: Support also strided loads (interleaved-groups with gaps). 4857 if (Indices.size() && Indices.size() != Factor) 4858 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4859 Alignment, AddressSpace, CostKind); 4860 4861 // VecTy for interleave memop is <VF*Factor x Elt>. 4862 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4863 // VecTy = <12 x i32>. 4864 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4865 4866 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 4867 // the VF=2, while v2i128 is an unsupported MVT vector type 4868 // (see MachineValueType.h::getVectorVT()). 4869 if (!LegalVT.isVector()) 4870 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4871 Alignment, AddressSpace, CostKind); 4872 4873 unsigned VF = VecTy->getNumElements() / Factor; 4874 Type *ScalarTy = VecTy->getElementType(); 4875 // Deduplicate entries, model floats/pointers as appropriately-sized integers. 4876 if (!ScalarTy->isIntegerTy()) 4877 ScalarTy = 4878 Type::getIntNTy(ScalarTy->getContext(), DL.getTypeSizeInBits(ScalarTy)); 4879 4880 // Get the cost of all the memory operations. 4881 InstructionCost MemOpCosts = getMemoryOpCost( 4882 Opcode, VecTy, MaybeAlign(Alignment), AddressSpace, CostKind); 4883 4884 auto *VT = FixedVectorType::get(ScalarTy, VF); 4885 EVT ETy = TLI->getValueType(DL, VT); 4886 if (!ETy.isSimple()) 4887 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4888 Alignment, AddressSpace, CostKind); 4889 4890 // TODO: Complete for other data-types and strides. 4891 // Each combination of Stride, element bit width and VF results in a different 4892 // sequence; The cost tables are therefore accessed with: 4893 // Factor (stride) and VectorType=VFxiN. 4894 // The Cost accounts only for the shuffle sequence; 4895 // The cost of the loads/stores is accounted for separately. 4896 // 4897 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 4898 {2, MVT::v4i64, 6}, // (load 8i64 and) deinterleave into 2 x 4i64 4899 4900 {3, MVT::v2i8, 10}, // (load 6i8 and) deinterleave into 3 x 2i8 4901 {3, MVT::v4i8, 4}, // (load 12i8 and) deinterleave into 3 x 4i8 4902 {3, MVT::v8i8, 9}, // (load 24i8 and) deinterleave into 3 x 8i8 4903 {3, MVT::v16i8, 11}, // (load 48i8 and) deinterleave into 3 x 16i8 4904 {3, MVT::v32i8, 13}, // (load 96i8 and) deinterleave into 3 x 32i8 4905 4906 {3, MVT::v8i32, 17}, // (load 24i32 and) deinterleave into 3 x 8i32 4907 4908 {4, MVT::v2i8, 12}, // (load 8i8 and) deinterleave into 4 x 2i8 4909 {4, MVT::v4i8, 4}, // (load 16i8 and) deinterleave into 4 x 4i8 4910 {4, MVT::v8i8, 20}, // (load 32i8 and) deinterleave into 4 x 8i8 4911 {4, MVT::v16i8, 39}, // (load 64i8 and) deinterleave into 4 x 16i8 4912 {4, MVT::v32i8, 80}, // (load 128i8 and) deinterleave into 4 x 32i8 4913 4914 {8, MVT::v8i32, 40} // (load 64i32 and) deinterleave into 8 x 8i32 4915 }; 4916 4917 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 4918 {2, MVT::v4i64, 6}, // interleave 2 x 4i64 into 8i64 (and store) 4919 4920 {3, MVT::v2i8, 7}, // interleave 3 x 2i8 into 6i8 (and store) 4921 {3, MVT::v4i8, 8}, // interleave 3 x 4i8 into 12i8 (and store) 4922 {3, MVT::v8i8, 11}, // interleave 3 x 8i8 into 24i8 (and store) 4923 {3, MVT::v16i8, 11}, // interleave 3 x 16i8 into 48i8 (and store) 4924 {3, MVT::v32i8, 13}, // interleave 3 x 32i8 into 96i8 (and store) 4925 4926 {4, MVT::v2i8, 12}, // interleave 4 x 2i8 into 8i8 (and store) 4927 {4, MVT::v4i8, 9}, // interleave 4 x 4i8 into 16i8 (and store) 4928 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 4929 {4, MVT::v16i8, 10}, // interleave 4 x 16i8 into 64i8 (and store) 4930 {4, MVT::v32i8, 12} // interleave 4 x 32i8 into 128i8 (and store) 4931 }; 4932 4933 if (Opcode == Instruction::Load) { 4934 if (const auto *Entry = 4935 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 4936 return MemOpCosts + Entry->Cost; 4937 } else { 4938 assert(Opcode == Instruction::Store && 4939 "Expected Store Instruction at this point"); 4940 if (const auto *Entry = 4941 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 4942 return MemOpCosts + Entry->Cost; 4943 } 4944 4945 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4946 Alignment, AddressSpace, CostKind); 4947 } 4948 4949 // Get estimation for interleaved load/store operations and strided load. 4950 // \p Indices contains indices for strided load. 4951 // \p Factor - the factor of interleaving. 4952 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 4953 InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX512( 4954 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 4955 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 4956 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 4957 4958 if (UseMaskForCond || UseMaskForGaps) 4959 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4960 Alignment, AddressSpace, CostKind, 4961 UseMaskForCond, UseMaskForGaps); 4962 4963 // VecTy for interleave memop is <VF*Factor x Elt>. 4964 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4965 // VecTy = <12 x i32>. 4966 4967 // Calculate the number of memory operations (NumOfMemOps), required 4968 // for load/store the VecTy. 4969 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4970 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4971 unsigned LegalVTSize = LegalVT.getStoreSize(); 4972 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4973 4974 // Get the cost of one memory operation. 4975 auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(), 4976 LegalVT.getVectorNumElements()); 4977 InstructionCost MemOpCost = getMemoryOpCost( 4978 Opcode, SingleMemOpTy, MaybeAlign(Alignment), AddressSpace, CostKind); 4979 4980 unsigned VF = VecTy->getNumElements() / Factor; 4981 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 4982 4983 if (Opcode == Instruction::Load) { 4984 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 4985 // contain the cost of the optimized shuffle sequence that the 4986 // X86InterleavedAccess pass will generate. 4987 // The cost of loads and stores are computed separately from the table. 4988 4989 // X86InterleavedAccess support only the following interleaved-access group. 4990 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 4991 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 4992 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 4993 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 4994 }; 4995 4996 if (const auto *Entry = 4997 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 4998 return NumOfMemOps * MemOpCost + Entry->Cost; 4999 //If an entry does not exist, fallback to the default implementation. 5000 5001 // Kind of shuffle depends on number of loaded values. 5002 // If we load the entire data in one register, we can use a 1-src shuffle. 5003 // Otherwise, we'll merge 2 sources in each operation. 5004 TTI::ShuffleKind ShuffleKind = 5005 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 5006 5007 InstructionCost ShuffleCost = 5008 getShuffleCost(ShuffleKind, SingleMemOpTy, None, 0, nullptr); 5009 5010 unsigned NumOfLoadsInInterleaveGrp = 5011 Indices.size() ? Indices.size() : Factor; 5012 auto *ResultTy = FixedVectorType::get(VecTy->getElementType(), 5013 VecTy->getNumElements() / Factor); 5014 InstructionCost NumOfResults = 5015 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 5016 NumOfLoadsInInterleaveGrp; 5017 5018 // About a half of the loads may be folded in shuffles when we have only 5019 // one result. If we have more than one result, we do not fold loads at all. 5020 unsigned NumOfUnfoldedLoads = 5021 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 5022 5023 // Get a number of shuffle operations per result. 5024 unsigned NumOfShufflesPerResult = 5025 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 5026 5027 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 5028 // When we have more than one destination, we need additional instructions 5029 // to keep sources. 5030 InstructionCost NumOfMoves = 0; 5031 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 5032 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 5033 5034 InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 5035 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 5036 5037 return Cost; 5038 } 5039 5040 // Store. 5041 assert(Opcode == Instruction::Store && 5042 "Expected Store Instruction at this point"); 5043 // X86InterleavedAccess support only the following interleaved-access group. 5044 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 5045 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 5046 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 5047 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 5048 5049 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 5050 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 5051 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 5052 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 5053 }; 5054 5055 if (const auto *Entry = 5056 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 5057 return NumOfMemOps * MemOpCost + Entry->Cost; 5058 //If an entry does not exist, fallback to the default implementation. 5059 5060 // There is no strided stores meanwhile. And store can't be folded in 5061 // shuffle. 5062 unsigned NumOfSources = Factor; // The number of values to be merged. 5063 InstructionCost ShuffleCost = 5064 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, None, 0, nullptr); 5065 unsigned NumOfShufflesPerStore = NumOfSources - 1; 5066 5067 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 5068 // We need additional instructions to keep sources. 5069 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 5070 InstructionCost Cost = 5071 NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 5072 NumOfMoves; 5073 return Cost; 5074 } 5075 5076 InstructionCost X86TTIImpl::getInterleavedMemoryOpCost( 5077 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, 5078 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, 5079 bool UseMaskForCond, bool UseMaskForGaps) { 5080 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 5081 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 5082 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 5083 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 5084 return true; 5085 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 5086 return HasBW; 5087 return false; 5088 }; 5089 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 5090 return getInterleavedMemoryOpCostAVX512( 5091 Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment, 5092 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 5093 if (ST->hasAVX2()) 5094 return getInterleavedMemoryOpCostAVX2( 5095 Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment, 5096 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 5097 5098 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5099 Alignment, AddressSpace, CostKind, 5100 UseMaskForCond, UseMaskForGaps); 5101 } 5102