1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // X86 cost model. 56 // 57 //===----------------------------------------------------------------------===// 58 59 TargetTransformInfo::PopcntSupportKind 60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 61 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 62 // TODO: Currently the __builtin_popcount() implementation using SSE3 63 // instructions is inefficient. Once the problem is fixed, we should 64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 66 } 67 68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 69 TargetTransformInfo::CacheLevel Level) const { 70 switch (Level) { 71 case TargetTransformInfo::CacheLevel::L1D: 72 // - Penryn 73 // - Nehalem 74 // - Westmere 75 // - Sandy Bridge 76 // - Ivy Bridge 77 // - Haswell 78 // - Broadwell 79 // - Skylake 80 // - Kabylake 81 return 32 * 1024; // 32 KByte 82 case TargetTransformInfo::CacheLevel::L2D: 83 // - Penryn 84 // - Nehalem 85 // - Westmere 86 // - Sandy Bridge 87 // - Ivy Bridge 88 // - Haswell 89 // - Broadwell 90 // - Skylake 91 // - Kabylake 92 return 256 * 1024; // 256 KByte 93 } 94 95 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 96 } 97 98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 99 TargetTransformInfo::CacheLevel Level) const { 100 // - Penryn 101 // - Nehalem 102 // - Westmere 103 // - Sandy Bridge 104 // - Ivy Bridge 105 // - Haswell 106 // - Broadwell 107 // - Skylake 108 // - Kabylake 109 switch (Level) { 110 case TargetTransformInfo::CacheLevel::L1D: 111 LLVM_FALLTHROUGH; 112 case TargetTransformInfo::CacheLevel::L2D: 113 return 8; 114 } 115 116 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 117 } 118 119 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 120 bool Vector = (ClassID == 1); 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 TypeSize 133 X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { 134 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 135 switch (K) { 136 case TargetTransformInfo::RGK_Scalar: 137 return TypeSize::getFixed(ST->is64Bit() ? 64 : 32); 138 case TargetTransformInfo::RGK_FixedWidthVector: 139 if (ST->hasAVX512() && PreferVectorWidth >= 512) 140 return TypeSize::getFixed(512); 141 if (ST->hasAVX() && PreferVectorWidth >= 256) 142 return TypeSize::getFixed(256); 143 if (ST->hasSSE1() && PreferVectorWidth >= 128) 144 return TypeSize::getFixed(128); 145 return TypeSize::getFixed(0); 146 case TargetTransformInfo::RGK_ScalableVector: 147 return TypeSize::getScalable(0); 148 } 149 150 llvm_unreachable("Unsupported register kind"); 151 } 152 153 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 154 return getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector) 155 .getFixedSize(); 156 } 157 158 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 159 // If the loop will not be vectorized, don't interleave the loop. 160 // Let regular unroll to unroll the loop, which saves the overflow 161 // check and memory check cost. 162 if (VF == 1) 163 return 1; 164 165 if (ST->isAtom()) 166 return 1; 167 168 // Sandybridge and Haswell have multiple execution ports and pipelined 169 // vector units. 170 if (ST->hasAVX()) 171 return 4; 172 173 return 2; 174 } 175 176 int X86TTIImpl::getArithmeticInstrCost(unsigned Opcode, Type *Ty, 177 TTI::TargetCostKind CostKind, 178 TTI::OperandValueKind Op1Info, 179 TTI::OperandValueKind Op2Info, 180 TTI::OperandValueProperties Opd1PropInfo, 181 TTI::OperandValueProperties Opd2PropInfo, 182 ArrayRef<const Value *> Args, 183 const Instruction *CxtI) { 184 // TODO: Handle more cost kinds. 185 if (CostKind != TTI::TCK_RecipThroughput) 186 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, 187 Op2Info, Opd1PropInfo, 188 Opd2PropInfo, Args, CxtI); 189 // Legalize the type. 190 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 191 192 int ISD = TLI->InstructionOpcodeToISD(Opcode); 193 assert(ISD && "Invalid opcode"); 194 195 static const CostTblEntry GLMCostTable[] = { 196 { ISD::FDIV, MVT::f32, 18 }, // divss 197 { ISD::FDIV, MVT::v4f32, 35 }, // divps 198 { ISD::FDIV, MVT::f64, 33 }, // divsd 199 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 200 }; 201 202 if (ST->useGLMDivSqrtCosts()) 203 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 204 LT.second)) 205 return LT.first * Entry->Cost; 206 207 static const CostTblEntry SLMCostTable[] = { 208 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 209 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 210 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. 211 { ISD::FMUL, MVT::f64, 2 }, // mulsd 212 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 213 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 214 { ISD::FDIV, MVT::f32, 17 }, // divss 215 { ISD::FDIV, MVT::v4f32, 39 }, // divps 216 { ISD::FDIV, MVT::f64, 32 }, // divsd 217 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 218 { ISD::FADD, MVT::v2f64, 2 }, // addpd 219 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 220 // v2i64/v4i64 mul is custom lowered as a series of long: 221 // multiplies(3), shifts(3) and adds(2) 222 // slm muldq version throughput is 2 and addq throughput 4 223 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 224 // 3X4 (addq throughput) = 17 225 { ISD::MUL, MVT::v2i64, 17 }, 226 // slm addq\subq throughput is 4 227 { ISD::ADD, MVT::v2i64, 4 }, 228 { ISD::SUB, MVT::v2i64, 4 }, 229 }; 230 231 if (ST->isSLM()) { 232 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 233 // Check if the operands can be shrinked into a smaller datatype. 234 bool Op1Signed = false; 235 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 236 bool Op2Signed = false; 237 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 238 239 bool SignedMode = Op1Signed || Op2Signed; 240 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 241 242 if (OpMinSize <= 7) 243 return LT.first * 3; // pmullw/sext 244 if (!SignedMode && OpMinSize <= 8) 245 return LT.first * 3; // pmullw/zext 246 if (OpMinSize <= 15) 247 return LT.first * 5; // pmullw/pmulhw/pshuf 248 if (!SignedMode && OpMinSize <= 16) 249 return LT.first * 5; // pmullw/pmulhw/pshuf 250 } 251 252 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 253 LT.second)) { 254 return LT.first * Entry->Cost; 255 } 256 } 257 258 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 259 ISD == ISD::UREM) && 260 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 261 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 262 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 263 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 264 // On X86, vector signed division by constants power-of-two are 265 // normally expanded to the sequence SRA + SRL + ADD + SRA. 266 // The OperandValue properties may not be the same as that of the previous 267 // operation; conservatively assume OP_None. 268 int Cost = 269 2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Op1Info, 270 Op2Info, 271 TargetTransformInfo::OP_None, 272 TargetTransformInfo::OP_None); 273 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 274 Op2Info, 275 TargetTransformInfo::OP_None, 276 TargetTransformInfo::OP_None); 277 Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind, Op1Info, 278 Op2Info, 279 TargetTransformInfo::OP_None, 280 TargetTransformInfo::OP_None); 281 282 if (ISD == ISD::SREM) { 283 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 284 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info, 285 Op2Info); 286 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info, 287 Op2Info); 288 } 289 290 return Cost; 291 } 292 293 // Vector unsigned division/remainder will be simplified to shifts/masks. 294 if (ISD == ISD::UDIV) 295 return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, 296 Op1Info, Op2Info, 297 TargetTransformInfo::OP_None, 298 TargetTransformInfo::OP_None); 299 300 else // UREM 301 return getArithmeticInstrCost(Instruction::And, Ty, CostKind, 302 Op1Info, Op2Info, 303 TargetTransformInfo::OP_None, 304 TargetTransformInfo::OP_None); 305 } 306 307 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 308 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 309 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 310 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 311 }; 312 313 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 314 ST->hasBWI()) { 315 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 316 LT.second)) 317 return LT.first * Entry->Cost; 318 } 319 320 static const CostTblEntry AVX512UniformConstCostTable[] = { 321 { ISD::SRA, MVT::v2i64, 1 }, 322 { ISD::SRA, MVT::v4i64, 1 }, 323 { ISD::SRA, MVT::v8i64, 1 }, 324 325 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 326 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 327 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 328 329 { ISD::SDIV, MVT::v16i32, 6 }, // pmuludq sequence 330 { ISD::SREM, MVT::v16i32, 8 }, // pmuludq+mul+sub sequence 331 { ISD::UDIV, MVT::v16i32, 5 }, // pmuludq sequence 332 { ISD::UREM, MVT::v16i32, 7 }, // pmuludq+mul+sub sequence 333 }; 334 335 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 336 ST->hasAVX512()) { 337 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 338 LT.second)) 339 return LT.first * Entry->Cost; 340 } 341 342 static const CostTblEntry AVX2UniformConstCostTable[] = { 343 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 344 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 345 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 346 347 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 348 349 { ISD::SDIV, MVT::v8i32, 6 }, // pmuludq sequence 350 { ISD::SREM, MVT::v8i32, 8 }, // pmuludq+mul+sub sequence 351 { ISD::UDIV, MVT::v8i32, 5 }, // pmuludq sequence 352 { ISD::UREM, MVT::v8i32, 7 }, // pmuludq+mul+sub sequence 353 }; 354 355 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 356 ST->hasAVX2()) { 357 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 358 LT.second)) 359 return LT.first * Entry->Cost; 360 } 361 362 static const CostTblEntry SSE2UniformConstCostTable[] = { 363 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 364 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 365 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 366 367 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 368 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 369 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 370 371 { ISD::SDIV, MVT::v8i32, 12+2 }, // 2*pmuludq sequence + split. 372 { ISD::SREM, MVT::v8i32, 16+2 }, // 2*pmuludq+mul+sub sequence + split. 373 { ISD::SDIV, MVT::v4i32, 6 }, // pmuludq sequence 374 { ISD::SREM, MVT::v4i32, 8 }, // pmuludq+mul+sub sequence 375 { ISD::UDIV, MVT::v8i32, 10+2 }, // 2*pmuludq sequence + split. 376 { ISD::UREM, MVT::v8i32, 14+2 }, // 2*pmuludq+mul+sub sequence + split. 377 { ISD::UDIV, MVT::v4i32, 5 }, // pmuludq sequence 378 { ISD::UREM, MVT::v4i32, 7 }, // pmuludq+mul+sub sequence 379 }; 380 381 // XOP has faster vXi8 shifts. 382 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 383 ST->hasSSE2() && !ST->hasXOP()) { 384 if (const auto *Entry = 385 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 386 return LT.first * Entry->Cost; 387 } 388 389 static const CostTblEntry AVX512BWConstCostTable[] = { 390 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 391 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 392 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 393 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 394 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 395 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 396 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 397 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 398 }; 399 400 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 401 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 402 ST->hasBWI()) { 403 if (const auto *Entry = 404 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 405 return LT.first * Entry->Cost; 406 } 407 408 static const CostTblEntry AVX512ConstCostTable[] = { 409 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 410 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 411 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 412 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 413 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 414 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 415 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 416 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 417 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 418 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 419 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 420 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 421 }; 422 423 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 424 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 425 ST->hasAVX512()) { 426 if (const auto *Entry = 427 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 428 return LT.first * Entry->Cost; 429 } 430 431 static const CostTblEntry AVX2ConstCostTable[] = { 432 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 433 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 434 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 435 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 436 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 437 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 438 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 439 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 440 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 441 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 442 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 443 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 444 }; 445 446 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 447 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 448 ST->hasAVX2()) { 449 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 450 return LT.first * Entry->Cost; 451 } 452 453 static const CostTblEntry SSE2ConstCostTable[] = { 454 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 455 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 456 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 457 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 458 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 459 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 460 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 461 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 462 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 463 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 464 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 465 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 466 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 467 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 468 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 469 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 470 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 471 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 472 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 473 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 474 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 475 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 476 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 477 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 478 }; 479 480 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 481 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 482 ST->hasSSE2()) { 483 // pmuldq sequence. 484 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 485 return LT.first * 32; 486 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 487 return LT.first * 38; 488 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 489 return LT.first * 15; 490 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 491 return LT.first * 20; 492 493 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 494 return LT.first * Entry->Cost; 495 } 496 497 static const CostTblEntry AVX512BWShiftCostTable[] = { 498 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 499 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 500 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 501 502 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 503 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 504 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 505 506 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 507 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 508 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 509 }; 510 511 if (ST->hasBWI()) 512 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 513 return LT.first * Entry->Cost; 514 515 static const CostTblEntry AVX2UniformCostTable[] = { 516 // Uniform splats are cheaper for the following instructions. 517 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 518 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 519 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 520 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 521 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 522 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 523 }; 524 525 if (ST->hasAVX2() && 526 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 527 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 528 if (const auto *Entry = 529 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 530 return LT.first * Entry->Cost; 531 } 532 533 static const CostTblEntry SSE2UniformCostTable[] = { 534 // Uniform splats are cheaper for the following instructions. 535 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 536 { ISD::SHL, MVT::v4i32, 1 }, // pslld 537 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 538 539 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 540 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 541 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 542 543 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 544 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 545 }; 546 547 if (ST->hasSSE2() && 548 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 549 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 550 if (const auto *Entry = 551 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 552 return LT.first * Entry->Cost; 553 } 554 555 static const CostTblEntry AVX512DQCostTable[] = { 556 { ISD::MUL, MVT::v2i64, 1 }, 557 { ISD::MUL, MVT::v4i64, 1 }, 558 { ISD::MUL, MVT::v8i64, 1 } 559 }; 560 561 // Look for AVX512DQ lowering tricks for custom cases. 562 if (ST->hasDQI()) 563 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 564 return LT.first * Entry->Cost; 565 566 static const CostTblEntry AVX512BWCostTable[] = { 567 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 568 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 569 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 570 571 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence. 572 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence. 573 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence. 574 }; 575 576 // Look for AVX512BW lowering tricks for custom cases. 577 if (ST->hasBWI()) 578 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 579 return LT.first * Entry->Cost; 580 581 static const CostTblEntry AVX512CostTable[] = { 582 { ISD::SHL, MVT::v16i32, 1 }, 583 { ISD::SRL, MVT::v16i32, 1 }, 584 { ISD::SRA, MVT::v16i32, 1 }, 585 586 { ISD::SHL, MVT::v8i64, 1 }, 587 { ISD::SRL, MVT::v8i64, 1 }, 588 589 { ISD::SRA, MVT::v2i64, 1 }, 590 { ISD::SRA, MVT::v4i64, 1 }, 591 { ISD::SRA, MVT::v8i64, 1 }, 592 593 { ISD::MUL, MVT::v64i8, 26 }, // extend/pmullw/trunc sequence. 594 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence. 595 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence. 596 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 597 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 598 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 599 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add 600 601 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 602 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 603 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 604 605 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 606 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 607 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 608 }; 609 610 if (ST->hasAVX512()) 611 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 612 return LT.first * Entry->Cost; 613 614 static const CostTblEntry AVX2ShiftCostTable[] = { 615 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 616 // customize them to detect the cases where shift amount is a scalar one. 617 { ISD::SHL, MVT::v4i32, 1 }, 618 { ISD::SRL, MVT::v4i32, 1 }, 619 { ISD::SRA, MVT::v4i32, 1 }, 620 { ISD::SHL, MVT::v8i32, 1 }, 621 { ISD::SRL, MVT::v8i32, 1 }, 622 { ISD::SRA, MVT::v8i32, 1 }, 623 { ISD::SHL, MVT::v2i64, 1 }, 624 { ISD::SRL, MVT::v2i64, 1 }, 625 { ISD::SHL, MVT::v4i64, 1 }, 626 { ISD::SRL, MVT::v4i64, 1 }, 627 }; 628 629 if (ST->hasAVX512()) { 630 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 631 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 632 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 633 // On AVX512, a packed v32i16 shift left by a constant build_vector 634 // is lowered into a vector multiply (vpmullw). 635 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 636 Op1Info, Op2Info, 637 TargetTransformInfo::OP_None, 638 TargetTransformInfo::OP_None); 639 } 640 641 // Look for AVX2 lowering tricks. 642 if (ST->hasAVX2()) { 643 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 644 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 645 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 646 // On AVX2, a packed v16i16 shift left by a constant build_vector 647 // is lowered into a vector multiply (vpmullw). 648 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 649 Op1Info, Op2Info, 650 TargetTransformInfo::OP_None, 651 TargetTransformInfo::OP_None); 652 653 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 654 return LT.first * Entry->Cost; 655 } 656 657 static const CostTblEntry XOPShiftCostTable[] = { 658 // 128bit shifts take 1cy, but right shifts require negation beforehand. 659 { ISD::SHL, MVT::v16i8, 1 }, 660 { ISD::SRL, MVT::v16i8, 2 }, 661 { ISD::SRA, MVT::v16i8, 2 }, 662 { ISD::SHL, MVT::v8i16, 1 }, 663 { ISD::SRL, MVT::v8i16, 2 }, 664 { ISD::SRA, MVT::v8i16, 2 }, 665 { ISD::SHL, MVT::v4i32, 1 }, 666 { ISD::SRL, MVT::v4i32, 2 }, 667 { ISD::SRA, MVT::v4i32, 2 }, 668 { ISD::SHL, MVT::v2i64, 1 }, 669 { ISD::SRL, MVT::v2i64, 2 }, 670 { ISD::SRA, MVT::v2i64, 2 }, 671 // 256bit shifts require splitting if AVX2 didn't catch them above. 672 { ISD::SHL, MVT::v32i8, 2+2 }, 673 { ISD::SRL, MVT::v32i8, 4+2 }, 674 { ISD::SRA, MVT::v32i8, 4+2 }, 675 { ISD::SHL, MVT::v16i16, 2+2 }, 676 { ISD::SRL, MVT::v16i16, 4+2 }, 677 { ISD::SRA, MVT::v16i16, 4+2 }, 678 { ISD::SHL, MVT::v8i32, 2+2 }, 679 { ISD::SRL, MVT::v8i32, 4+2 }, 680 { ISD::SRA, MVT::v8i32, 4+2 }, 681 { ISD::SHL, MVT::v4i64, 2+2 }, 682 { ISD::SRL, MVT::v4i64, 4+2 }, 683 { ISD::SRA, MVT::v4i64, 4+2 }, 684 }; 685 686 // Look for XOP lowering tricks. 687 if (ST->hasXOP()) { 688 // If the right shift is constant then we'll fold the negation so 689 // it's as cheap as a left shift. 690 int ShiftISD = ISD; 691 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 692 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 693 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 694 ShiftISD = ISD::SHL; 695 if (const auto *Entry = 696 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 697 return LT.first * Entry->Cost; 698 } 699 700 static const CostTblEntry SSE2UniformShiftCostTable[] = { 701 // Uniform splats are cheaper for the following instructions. 702 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 703 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 704 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 705 706 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 707 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 708 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 709 710 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 711 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 712 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 713 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 714 }; 715 716 if (ST->hasSSE2() && 717 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 718 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 719 720 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 721 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 722 return LT.first * 4; // 2*psrad + shuffle. 723 724 if (const auto *Entry = 725 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 726 return LT.first * Entry->Cost; 727 } 728 729 if (ISD == ISD::SHL && 730 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 731 MVT VT = LT.second; 732 // Vector shift left by non uniform constant can be lowered 733 // into vector multiply. 734 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 735 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 736 ISD = ISD::MUL; 737 } 738 739 static const CostTblEntry AVX2CostTable[] = { 740 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. 741 { ISD::SHL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. 742 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 743 { ISD::SHL, MVT::v32i16, 20 }, // 2*extend/vpsrlvd/pack sequence. 744 745 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. 746 { ISD::SRL, MVT::v64i8, 22 }, // 2*vpblendvb sequence. 747 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 748 { ISD::SRL, MVT::v32i16, 20 }, // 2*extend/vpsrlvd/pack sequence. 749 750 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. 751 { ISD::SRA, MVT::v64i8, 48 }, // 2*vpblendvb sequence. 752 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. 753 { ISD::SRA, MVT::v32i16, 20 }, // 2*extend/vpsravd/pack sequence. 754 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. 755 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 756 757 { ISD::SUB, MVT::v32i8, 1 }, // psubb 758 { ISD::ADD, MVT::v32i8, 1 }, // paddb 759 { ISD::SUB, MVT::v16i16, 1 }, // psubw 760 { ISD::ADD, MVT::v16i16, 1 }, // paddw 761 { ISD::SUB, MVT::v8i32, 1 }, // psubd 762 { ISD::ADD, MVT::v8i32, 1 }, // paddd 763 { ISD::SUB, MVT::v4i64, 1 }, // psubq 764 { ISD::ADD, MVT::v4i64, 1 }, // paddq 765 766 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence. 767 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence. 768 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 769 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 770 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add 771 772 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 773 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 774 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 775 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 776 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 777 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 778 779 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 780 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 781 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 782 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 783 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 784 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 785 }; 786 787 // Look for AVX2 lowering tricks for custom cases. 788 if (ST->hasAVX2()) 789 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 790 return LT.first * Entry->Cost; 791 792 static const CostTblEntry AVX1CostTable[] = { 793 // We don't have to scalarize unsupported ops. We can issue two half-sized 794 // operations and we only need to extract the upper YMM half. 795 // Two ops + 1 extract + 1 insert = 4. 796 { ISD::MUL, MVT::v16i16, 4 }, 797 { ISD::MUL, MVT::v8i32, 4 }, 798 { ISD::SUB, MVT::v32i8, 4 }, 799 { ISD::ADD, MVT::v32i8, 4 }, 800 { ISD::SUB, MVT::v16i16, 4 }, 801 { ISD::ADD, MVT::v16i16, 4 }, 802 { ISD::SUB, MVT::v8i32, 4 }, 803 { ISD::ADD, MVT::v8i32, 4 }, 804 { ISD::SUB, MVT::v4i64, 4 }, 805 { ISD::ADD, MVT::v4i64, 4 }, 806 807 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 808 // are lowered as a series of long multiplies(3), shifts(3) and adds(2) 809 // Because we believe v4i64 to be a legal type, we must also include the 810 // extract+insert in the cost table. Therefore, the cost here is 18 811 // instead of 8. 812 { ISD::MUL, MVT::v4i64, 18 }, 813 814 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence. 815 816 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 817 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 818 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 819 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 820 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 821 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 822 }; 823 824 if (ST->hasAVX()) 825 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 826 return LT.first * Entry->Cost; 827 828 static const CostTblEntry SSE42CostTable[] = { 829 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 830 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 831 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 832 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 833 834 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 835 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 836 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 837 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 838 839 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 840 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 841 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 842 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 843 844 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 845 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 846 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 847 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 848 }; 849 850 if (ST->hasSSE42()) 851 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 852 return LT.first * Entry->Cost; 853 854 static const CostTblEntry SSE41CostTable[] = { 855 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 856 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split. 857 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 858 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 859 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 860 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split 861 862 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 863 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split. 864 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 865 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 866 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 867 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split. 868 869 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 870 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split. 871 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 872 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 873 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 874 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split. 875 876 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 877 }; 878 879 if (ST->hasSSE41()) 880 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 881 return LT.first * Entry->Cost; 882 883 static const CostTblEntry SSE2CostTable[] = { 884 // We don't correctly identify costs of casts because they are marked as 885 // custom. 886 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 887 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 888 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 889 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 890 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 891 892 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 893 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 894 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 895 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 896 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 897 898 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 899 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 900 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 901 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 902 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split. 903 904 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence. 905 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 906 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 907 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 908 909 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 910 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 911 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 912 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 913 914 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 915 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 916 917 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 918 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 919 }; 920 921 if (ST->hasSSE2()) 922 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 923 return LT.first * Entry->Cost; 924 925 static const CostTblEntry SSE1CostTable[] = { 926 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 927 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 928 929 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 930 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 931 932 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 933 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 934 935 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 936 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 937 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 938 939 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 940 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 941 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 942 }; 943 944 if (ST->hasSSE1()) 945 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 946 return LT.first * Entry->Cost; 947 948 // It is not a good idea to vectorize division. We have to scalarize it and 949 // in the process we will often end up having to spilling regular 950 // registers. The overhead of division is going to dominate most kernels 951 // anyways so try hard to prevent vectorization of division - it is 952 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 953 // to hide "20 cycles" for each lane. 954 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 955 ISD == ISD::UDIV || ISD == ISD::UREM)) { 956 int ScalarCost = getArithmeticInstrCost( 957 Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info, 958 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 959 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 960 } 961 962 // Fallback to the default implementation. 963 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info); 964 } 965 966 int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, VectorType *BaseTp, 967 ArrayRef<int> Mask, int Index, 968 VectorType *SubTp) { 969 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 970 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 971 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 972 973 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 974 if (Kind == TTI::SK_Transpose) 975 Kind = TTI::SK_PermuteTwoSrc; 976 977 // For Broadcasts we are splatting the first element from the first input 978 // register, so only need to reference that input and all the output 979 // registers are the same. 980 if (Kind == TTI::SK_Broadcast) 981 LT.first = 1; 982 983 // Subvector extractions are free if they start at the beginning of a 984 // vector and cheap if the subvectors are aligned. 985 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 986 int NumElts = LT.second.getVectorNumElements(); 987 if ((Index % NumElts) == 0) 988 return 0; 989 std::pair<int, MVT> SubLT = TLI->getTypeLegalizationCost(DL, SubTp); 990 if (SubLT.second.isVector()) { 991 int NumSubElts = SubLT.second.getVectorNumElements(); 992 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 993 return SubLT.first; 994 // Handle some cases for widening legalization. For now we only handle 995 // cases where the original subvector was naturally aligned and evenly 996 // fit in its legalized subvector type. 997 // FIXME: Remove some of the alignment restrictions. 998 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 999 // vectors. 1000 int OrigSubElts = cast<FixedVectorType>(SubTp)->getNumElements(); 1001 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 1002 (NumSubElts % OrigSubElts) == 0 && 1003 LT.second.getVectorElementType() == 1004 SubLT.second.getVectorElementType() && 1005 LT.second.getVectorElementType().getSizeInBits() == 1006 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 1007 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 1008 "Unexpected number of elements!"); 1009 auto *VecTy = FixedVectorType::get(BaseTp->getElementType(), 1010 LT.second.getVectorNumElements()); 1011 auto *SubTy = FixedVectorType::get(BaseTp->getElementType(), 1012 SubLT.second.getVectorNumElements()); 1013 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 1014 int ExtractCost = getShuffleCost(TTI::SK_ExtractSubvector, VecTy, None, 1015 ExtractIndex, SubTy); 1016 1017 // If the original size is 32-bits or more, we can use pshufd. Otherwise 1018 // if we have SSSE3 we can use pshufb. 1019 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 1020 return ExtractCost + 1; // pshufd or pshufb 1021 1022 assert(SubTp->getPrimitiveSizeInBits() == 16 && 1023 "Unexpected vector size"); 1024 1025 return ExtractCost + 2; // worst case pshufhw + pshufd 1026 } 1027 } 1028 } 1029 1030 // Handle some common (illegal) sub-vector types as they are often very cheap 1031 // to shuffle even on targets without PSHUFB. 1032 EVT VT = TLI->getValueType(DL, BaseTp); 1033 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 1034 !ST->hasSSSE3()) { 1035 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 1036 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 1037 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1038 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1039 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1040 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1041 1042 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1043 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1044 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1045 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1046 1047 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1048 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1049 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1050 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1051 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1052 1053 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1054 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1055 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1056 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1057 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1058 }; 1059 1060 if (ST->hasSSE2()) 1061 if (const auto *Entry = 1062 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1063 return Entry->Cost; 1064 } 1065 1066 // We are going to permute multiple sources and the result will be in multiple 1067 // destinations. Providing an accurate cost only for splits where the element 1068 // type remains the same. 1069 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1070 MVT LegalVT = LT.second; 1071 if (LegalVT.isVector() && 1072 LegalVT.getVectorElementType().getSizeInBits() == 1073 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1074 LegalVT.getVectorNumElements() < 1075 cast<FixedVectorType>(BaseTp)->getNumElements()) { 1076 1077 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1078 unsigned LegalVTSize = LegalVT.getStoreSize(); 1079 // Number of source vectors after legalization: 1080 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1081 // Number of destination vectors after legalization: 1082 unsigned NumOfDests = LT.first; 1083 1084 auto *SingleOpTy = FixedVectorType::get(BaseTp->getElementType(), 1085 LegalVT.getVectorNumElements()); 1086 1087 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1088 return NumOfShuffles * getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 1089 None, 0, nullptr); 1090 } 1091 1092 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1093 } 1094 1095 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1096 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1097 // We assume that source and destination have the same vector type. 1098 int NumOfDests = LT.first; 1099 int NumOfShufflesPerDest = LT.first * 2 - 1; 1100 LT.first = NumOfDests * NumOfShufflesPerDest; 1101 } 1102 1103 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1104 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1105 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1106 1107 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1108 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1109 1110 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b 1111 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b 1112 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2} // vpermt2b 1113 }; 1114 1115 if (ST->hasVBMI()) 1116 if (const auto *Entry = 1117 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1118 return LT.first * Entry->Cost; 1119 1120 static const CostTblEntry AVX512BWShuffleTbl[] = { 1121 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1122 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1123 1124 {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw 1125 {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw 1126 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1127 1128 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw 1129 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw 1130 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1131 1132 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w 1133 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w 1134 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2}, // vpermt2w 1135 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1136 1137 {TTI::SK_Select, MVT::v32i16, 1}, // vblendmw 1138 {TTI::SK_Select, MVT::v64i8, 1}, // vblendmb 1139 }; 1140 1141 if (ST->hasBWI()) 1142 if (const auto *Entry = 1143 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1144 return LT.first * Entry->Cost; 1145 1146 static const CostTblEntry AVX512ShuffleTbl[] = { 1147 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1148 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1149 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1150 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1151 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1152 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1153 1154 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1155 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1156 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1157 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1158 1159 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1160 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1161 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1162 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1163 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1164 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1165 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1166 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1167 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1168 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1169 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1170 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1171 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1172 1173 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1174 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1175 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1176 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1177 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1178 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1179 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1180 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1181 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1182 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1183 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1184 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1185 1186 // FIXME: This just applies the type legalization cost rules above 1187 // assuming these completely split. 1188 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1189 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1190 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1191 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1192 1193 {TTI::SK_Select, MVT::v32i16, 1}, // vpternlogq 1194 {TTI::SK_Select, MVT::v64i8, 1}, // vpternlogq 1195 {TTI::SK_Select, MVT::v8f64, 1}, // vblendmpd 1196 {TTI::SK_Select, MVT::v16f32, 1}, // vblendmps 1197 {TTI::SK_Select, MVT::v8i64, 1}, // vblendmq 1198 {TTI::SK_Select, MVT::v16i32, 1}, // vblendmd 1199 }; 1200 1201 if (ST->hasAVX512()) 1202 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1203 return LT.first * Entry->Cost; 1204 1205 static const CostTblEntry AVX2ShuffleTbl[] = { 1206 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1207 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1208 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1209 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1210 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1211 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1212 1213 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1214 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1215 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1216 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1217 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1218 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1219 1220 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1221 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1222 1223 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1224 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1225 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1226 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1227 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1228 // + vpblendvb 1229 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1230 // + vpblendvb 1231 1232 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1233 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1234 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1235 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1236 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1237 // + vpblendvb 1238 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1239 // + vpblendvb 1240 }; 1241 1242 if (ST->hasAVX2()) 1243 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1244 return LT.first * Entry->Cost; 1245 1246 static const CostTblEntry XOPShuffleTbl[] = { 1247 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1248 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1249 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1250 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1251 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1252 // + vinsertf128 1253 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1254 // + vinsertf128 1255 1256 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1257 // + vinsertf128 1258 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1259 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1260 // + vinsertf128 1261 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1262 }; 1263 1264 if (ST->hasXOP()) 1265 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1266 return LT.first * Entry->Cost; 1267 1268 static const CostTblEntry AVX1ShuffleTbl[] = { 1269 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1270 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1271 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1272 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1273 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1274 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1275 1276 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1277 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1278 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1279 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1280 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1281 // + vinsertf128 1282 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1283 // + vinsertf128 1284 1285 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1286 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1287 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1288 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1289 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1290 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1291 1292 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1293 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1294 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1295 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1296 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1297 // + 2*por + vinsertf128 1298 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1299 // + 2*por + vinsertf128 1300 1301 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1302 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1303 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1304 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1305 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1306 // + 4*por + vinsertf128 1307 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1308 // + 4*por + vinsertf128 1309 }; 1310 1311 if (ST->hasAVX()) 1312 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1313 return LT.first * Entry->Cost; 1314 1315 static const CostTblEntry SSE41ShuffleTbl[] = { 1316 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1317 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1318 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1319 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1320 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1321 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1322 }; 1323 1324 if (ST->hasSSE41()) 1325 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1326 return LT.first * Entry->Cost; 1327 1328 static const CostTblEntry SSSE3ShuffleTbl[] = { 1329 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1330 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1331 1332 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1333 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1334 1335 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1336 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1337 1338 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1339 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1340 1341 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1342 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1343 }; 1344 1345 if (ST->hasSSSE3()) 1346 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1347 return LT.first * Entry->Cost; 1348 1349 static const CostTblEntry SSE2ShuffleTbl[] = { 1350 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1351 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1352 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1353 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1354 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1355 1356 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1357 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1358 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1359 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1360 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1361 // + 2*pshufd + 2*unpck + packus 1362 1363 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1364 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1365 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1366 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1367 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1368 1369 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1370 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1371 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1372 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1373 // + pshufd/unpck 1374 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1375 // + 2*pshufd + 2*unpck + 2*packus 1376 1377 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1378 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1379 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1380 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1381 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1382 }; 1383 1384 if (ST->hasSSE2()) 1385 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1386 return LT.first * Entry->Cost; 1387 1388 static const CostTblEntry SSE1ShuffleTbl[] = { 1389 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1390 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1391 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1392 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1393 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1394 }; 1395 1396 if (ST->hasSSE1()) 1397 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1398 return LT.first * Entry->Cost; 1399 1400 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1401 } 1402 1403 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 1404 TTI::CastContextHint CCH, 1405 TTI::TargetCostKind CostKind, 1406 const Instruction *I) { 1407 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1408 assert(ISD && "Invalid opcode"); 1409 1410 // TODO: Allow non-throughput costs that aren't binary. 1411 auto AdjustCost = [&CostKind](int Cost) { 1412 if (CostKind != TTI::TCK_RecipThroughput) 1413 return Cost == 0 ? 0 : 1; 1414 return Cost; 1415 }; 1416 1417 // FIXME: Need a better design of the cost table to handle non-simple types of 1418 // potential massive combinations (elem_num x src_type x dst_type). 1419 1420 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1421 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1422 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1423 1424 // Mask sign extend has an instruction. 1425 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1426 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1427 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1428 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1429 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1430 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1431 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1432 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1433 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1434 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1435 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1436 1437 // Mask zero extend is a sext + shift. 1438 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1439 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1440 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1441 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1442 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1443 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1444 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1445 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1446 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1447 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1448 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1449 1450 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, 1451 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm 1452 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // widen to zmm 1453 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // widen to zmm 1454 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // widen to zmm 1455 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // widen to zmm 1456 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // widen to zmm 1457 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // widen to zmm 1458 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // widen to zmm 1459 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // widen to zmm 1460 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // widen to zmm 1461 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, 1462 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, 1463 }; 1464 1465 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1466 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1467 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1468 1469 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1470 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1471 1472 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1473 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1474 1475 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1476 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1477 }; 1478 1479 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1480 // 256-bit wide vectors. 1481 1482 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1483 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1484 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1485 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1486 1487 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1488 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1489 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1490 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd 1491 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1492 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1493 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1494 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd 1495 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd 1496 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd 1497 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd 1498 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd 1499 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq 1500 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq 1501 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq 1502 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, 1503 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, 1504 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, 1505 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, 1506 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 1507 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd 1508 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb 1509 1510 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32 1511 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, 1512 1513 // Sign extend is zmm vpternlogd+vptruncdb. 1514 // Zero extend is zmm broadcast load+vptruncdw. 1515 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 }, 1516 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 }, 1517 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, 1518 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, 1519 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, 1520 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, 1521 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 }, 1522 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 }, 1523 1524 // Sign extend is zmm vpternlogd+vptruncdw. 1525 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw. 1526 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 }, 1527 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1528 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 }, 1529 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1530 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 }, 1531 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1532 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 }, 1533 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1534 1535 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd 1536 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld 1537 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd 1538 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld 1539 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd 1540 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld 1541 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq 1542 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq 1543 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq 1544 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq 1545 1546 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd 1547 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld 1548 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq 1549 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq 1550 1551 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1552 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1553 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1554 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1555 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1556 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1557 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1558 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1559 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1560 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1561 1562 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1563 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1564 1565 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1566 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1567 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1568 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1569 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1570 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1571 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1572 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1573 1574 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1575 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1576 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1577 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1578 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1579 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1580 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1581 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1582 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1583 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1584 1585 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f64, 3 }, 1586 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, 1587 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 3 }, 1588 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 3 }, 1589 1590 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1591 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, 1592 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, 1593 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1594 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, 1595 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, 1596 }; 1597 1598 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1599 // Mask sign extend has an instruction. 1600 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1601 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1602 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1603 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1604 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1605 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1606 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1607 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1608 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1609 1610 // Mask zero extend is a sext + shift. 1611 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1612 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1613 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1614 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1615 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1616 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1617 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1618 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1619 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1620 1621 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, 1622 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, // vpsllw+vptestmb 1623 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // vpsllw+vptestmw 1624 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // vpsllw+vptestmb 1625 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, // vpsllw+vptestmw 1626 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // vpsllw+vptestmb 1627 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // vpsllw+vptestmw 1628 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // vpsllw+vptestmb 1629 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, // vpsllw+vptestmw 1630 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // vpsllw+vptestmb 1631 }; 1632 1633 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1634 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1635 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1636 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1637 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1638 1639 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1640 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1641 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1642 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1643 1644 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1645 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1646 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1647 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1648 1649 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1650 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1651 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1652 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1653 }; 1654 1655 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 1656 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1657 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1658 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1659 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 8 }, // split+2*v8i8 1660 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1661 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1662 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1663 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16 1664 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // vpslld+vptestmd 1665 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd 1666 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // vpslld+vptestmd 1667 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // vpsllq+vptestmq 1668 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // vpsllq+vptestmq 1669 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // vpmovqd 1670 1671 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb 1672 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb 1673 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 }, 1674 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 }, 1675 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 }, 1676 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 }, 1677 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 }, 1678 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 }, 1679 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 }, 1680 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 }, 1681 1682 // sign extend is vpcmpeq+maskedmove+vpmovdw 1683 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw 1684 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1685 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 }, 1686 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1687 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 }, 1688 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1689 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 }, 1690 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 }, 1691 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 }, 1692 1693 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd 1694 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld 1695 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd 1696 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld 1697 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd 1698 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld 1699 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq 1700 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq 1701 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq 1702 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq 1703 1704 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1705 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1706 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1707 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1708 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1709 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1710 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1711 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1712 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1713 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1714 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1715 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1716 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1717 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1718 1719 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 1720 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1721 1722 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 3 }, 1723 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 3 }, 1724 1725 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 1726 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 1727 1728 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1729 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1730 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 1 }, 1731 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1732 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1733 }; 1734 1735 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1736 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1737 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1738 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1739 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1740 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1741 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1742 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1743 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1744 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1745 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1746 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1747 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1748 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1749 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1750 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1751 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1752 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1753 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1754 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1755 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1756 1757 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1758 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1759 1760 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 1761 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 1762 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 1763 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1764 1765 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1766 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1767 1768 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1769 }; 1770 1771 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1772 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1773 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1774 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1775 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1776 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1777 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1778 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1779 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1780 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1781 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1782 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1783 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1784 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 4 }, 1785 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1786 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1787 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1788 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1789 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1790 1791 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 4 }, 1792 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 5 }, 1793 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 4 }, 1794 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 9 }, 1795 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, 11 }, 1796 1797 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 1798 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1799 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1800 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1801 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 1802 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1803 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 11 }, 1804 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 9 }, 1805 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 }, 1806 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 11 }, 1807 1808 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1809 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1810 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1811 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1812 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1813 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1814 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1815 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1816 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1817 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1818 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1819 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1820 1821 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1822 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1823 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1824 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1825 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1826 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1827 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1828 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1829 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1830 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 }, 1831 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 1832 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1833 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 1834 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1835 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1836 // The generic code to compute the scalar overhead is currently broken. 1837 // Workaround this limitation by estimating the scalarization overhead 1838 // here. We have roughly 10 instructions per scalar element. 1839 // Multiply that by the vector width. 1840 // FIXME: remove that when PR19268 is fixed. 1841 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1842 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1843 1844 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 4 }, 1845 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f64, 3 }, 1846 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f64, 2 }, 1847 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 3 }, 1848 1849 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f64, 3 }, 1850 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f64, 2 }, 1851 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f32, 4 }, 1852 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 3 }, 1853 // This node is expanded into scalarized operations but BasicTTI is overly 1854 // optimistic estimating its cost. It computes 3 per element (one 1855 // vector-extract, one scalar conversion and one vector-insert). The 1856 // problem is that the inserts form a read-modify-write chain so latency 1857 // should be factored in too. Inflating the cost per element by 1. 1858 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, 1859 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 1860 1861 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 1862 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 1863 }; 1864 1865 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 1866 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1867 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1868 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1869 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1870 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1871 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1872 1873 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1874 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 }, 1875 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1876 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1877 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1878 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1879 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1880 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1881 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1882 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1883 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1884 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1885 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1886 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1887 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1888 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1889 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1890 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1891 1892 // These truncates end up widening elements. 1893 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 1 }, // PMOVXZBQ 1894 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 1 }, // PMOVXZWQ 1895 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 1 }, // PMOVXZBD 1896 1897 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 1 }, 1898 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 1 }, 1899 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 1900 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 1901 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 1902 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 1903 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 1904 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 1905 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 1 }, // PSHUFB 1906 1907 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 1908 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 1909 1910 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 3 }, 1911 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 3 }, 1912 1913 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 3 }, 1914 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 3 }, 1915 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, 1916 }; 1917 1918 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 1919 // These are somewhat magic numbers justified by looking at the output of 1920 // Intel's IACA, running some kernels and making sure when we take 1921 // legalization into account the throughput will be overestimated. 1922 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1923 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1924 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1925 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1926 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1927 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 2*10 }, 1928 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2*10 }, 1929 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1930 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 1931 1932 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1933 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1934 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1935 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1936 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1937 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, 1938 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 }, 1939 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1940 1941 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 4 }, 1942 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 2 }, 1943 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, 1944 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, 1945 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, 1946 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 4 }, 1947 1948 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 1 }, 1949 1950 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 6 }, 1951 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 }, 1952 1953 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 1954 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 1955 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 4 }, 1956 { ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 4 }, 1957 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 }, 1958 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 2 }, 1959 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 }, 1960 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 4 }, 1961 1962 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1963 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 1964 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 1965 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 1966 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1967 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 1968 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1969 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 1970 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1971 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1972 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1973 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1974 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 1975 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 1976 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1977 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 1978 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1979 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 1980 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1981 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1982 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 1983 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 1984 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1985 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 1986 1987 // These truncates are really widening elements. 1988 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 1 }, // PSHUFD 1989 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // PUNPCKLWD+DQ 1990 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // PUNPCKLBW+WD+PSHUFD 1991 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 1 }, // PUNPCKLWD 1992 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // PUNPCKLBW+WD 1993 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 1 }, // PUNPCKLBW 1994 1995 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // PAND+PACKUSWB 1996 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // PAND+PACKUSWB 1997 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // PAND+PACKUSWB 1998 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 1999 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 3 }, // PAND+2*PACKUSWB 2000 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 2001 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 2002 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 2003 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 2004 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 2005 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2006 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 2007 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 2008 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 2009 { ISD::TRUNCATE, MVT::v2i32, MVT::v2i64, 1 }, // PSHUFD 2010 }; 2011 2012 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 2013 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst); 2014 2015 if (ST->hasSSE2() && !ST->hasAVX()) { 2016 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2017 LTDest.second, LTSrc.second)) 2018 return AdjustCost(LTSrc.first * Entry->Cost); 2019 } 2020 2021 EVT SrcTy = TLI->getValueType(DL, Src); 2022 EVT DstTy = TLI->getValueType(DL, Dst); 2023 2024 // The function getSimpleVT only handles simple value types. 2025 if (!SrcTy.isSimple() || !DstTy.isSimple()) 2026 return AdjustCost(BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind)); 2027 2028 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 2029 MVT SimpleDstTy = DstTy.getSimpleVT(); 2030 2031 if (ST->useAVX512Regs()) { 2032 if (ST->hasBWI()) 2033 if (const auto *Entry = ConvertCostTableLookup(AVX512BWConversionTbl, ISD, 2034 SimpleDstTy, SimpleSrcTy)) 2035 return AdjustCost(Entry->Cost); 2036 2037 if (ST->hasDQI()) 2038 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 2039 SimpleDstTy, SimpleSrcTy)) 2040 return AdjustCost(Entry->Cost); 2041 2042 if (ST->hasAVX512()) 2043 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 2044 SimpleDstTy, SimpleSrcTy)) 2045 return AdjustCost(Entry->Cost); 2046 } 2047 2048 if (ST->hasBWI()) 2049 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 2050 SimpleDstTy, SimpleSrcTy)) 2051 return AdjustCost(Entry->Cost); 2052 2053 if (ST->hasDQI()) 2054 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 2055 SimpleDstTy, SimpleSrcTy)) 2056 return AdjustCost(Entry->Cost); 2057 2058 if (ST->hasAVX512()) 2059 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2060 SimpleDstTy, SimpleSrcTy)) 2061 return AdjustCost(Entry->Cost); 2062 2063 if (ST->hasAVX2()) { 2064 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2065 SimpleDstTy, SimpleSrcTy)) 2066 return AdjustCost(Entry->Cost); 2067 } 2068 2069 if (ST->hasAVX()) { 2070 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2071 SimpleDstTy, SimpleSrcTy)) 2072 return AdjustCost(Entry->Cost); 2073 } 2074 2075 if (ST->hasSSE41()) { 2076 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2077 SimpleDstTy, SimpleSrcTy)) 2078 return AdjustCost(Entry->Cost); 2079 } 2080 2081 if (ST->hasSSE2()) { 2082 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2083 SimpleDstTy, SimpleSrcTy)) 2084 return AdjustCost(Entry->Cost); 2085 } 2086 2087 return AdjustCost( 2088 BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I)); 2089 } 2090 2091 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 2092 CmpInst::Predicate VecPred, 2093 TTI::TargetCostKind CostKind, 2094 const Instruction *I) { 2095 // TODO: Handle other cost kinds. 2096 if (CostKind != TTI::TCK_RecipThroughput) 2097 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, 2098 I); 2099 2100 // Legalize the type. 2101 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2102 2103 MVT MTy = LT.second; 2104 2105 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2106 assert(ISD && "Invalid opcode"); 2107 2108 unsigned ExtraCost = 0; 2109 if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) { 2110 // Some vector comparison predicates cost extra instructions. 2111 if (MTy.isVector() && 2112 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 2113 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 2114 ST->hasBWI())) { 2115 switch (cast<CmpInst>(I)->getPredicate()) { 2116 case CmpInst::Predicate::ICMP_NE: 2117 // xor(cmpeq(x,y),-1) 2118 ExtraCost = 1; 2119 break; 2120 case CmpInst::Predicate::ICMP_SGE: 2121 case CmpInst::Predicate::ICMP_SLE: 2122 // xor(cmpgt(x,y),-1) 2123 ExtraCost = 1; 2124 break; 2125 case CmpInst::Predicate::ICMP_ULT: 2126 case CmpInst::Predicate::ICMP_UGT: 2127 // cmpgt(xor(x,signbit),xor(y,signbit)) 2128 // xor(cmpeq(pmaxu(x,y),x),-1) 2129 ExtraCost = 2; 2130 break; 2131 case CmpInst::Predicate::ICMP_ULE: 2132 case CmpInst::Predicate::ICMP_UGE: 2133 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 2134 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 2135 // cmpeq(psubus(x,y),0) 2136 // cmpeq(pminu(x,y),x) 2137 ExtraCost = 1; 2138 } else { 2139 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 2140 ExtraCost = 3; 2141 } 2142 break; 2143 default: 2144 break; 2145 } 2146 } 2147 } 2148 2149 static const CostTblEntry SLMCostTbl[] = { 2150 // slm pcmpeq/pcmpgt throughput is 2 2151 { ISD::SETCC, MVT::v2i64, 2 }, 2152 }; 2153 2154 static const CostTblEntry AVX512BWCostTbl[] = { 2155 { ISD::SETCC, MVT::v32i16, 1 }, 2156 { ISD::SETCC, MVT::v64i8, 1 }, 2157 2158 { ISD::SELECT, MVT::v32i16, 1 }, 2159 { ISD::SELECT, MVT::v64i8, 1 }, 2160 }; 2161 2162 static const CostTblEntry AVX512CostTbl[] = { 2163 { ISD::SETCC, MVT::v8i64, 1 }, 2164 { ISD::SETCC, MVT::v16i32, 1 }, 2165 { ISD::SETCC, MVT::v8f64, 1 }, 2166 { ISD::SETCC, MVT::v16f32, 1 }, 2167 2168 { ISD::SELECT, MVT::v8i64, 1 }, 2169 { ISD::SELECT, MVT::v16i32, 1 }, 2170 { ISD::SELECT, MVT::v8f64, 1 }, 2171 { ISD::SELECT, MVT::v16f32, 1 }, 2172 2173 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 2174 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 2175 2176 { ISD::SELECT, MVT::v32i16, 2 }, // FIXME: should be 3 2177 { ISD::SELECT, MVT::v64i8, 2 }, // FIXME: should be 3 2178 }; 2179 2180 static const CostTblEntry AVX2CostTbl[] = { 2181 { ISD::SETCC, MVT::v4i64, 1 }, 2182 { ISD::SETCC, MVT::v8i32, 1 }, 2183 { ISD::SETCC, MVT::v16i16, 1 }, 2184 { ISD::SETCC, MVT::v32i8, 1 }, 2185 2186 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 2187 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 2188 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 2189 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 2190 }; 2191 2192 static const CostTblEntry AVX1CostTbl[] = { 2193 { ISD::SETCC, MVT::v4f64, 1 }, 2194 { ISD::SETCC, MVT::v8f32, 1 }, 2195 // AVX1 does not support 8-wide integer compare. 2196 { ISD::SETCC, MVT::v4i64, 4 }, 2197 { ISD::SETCC, MVT::v8i32, 4 }, 2198 { ISD::SETCC, MVT::v16i16, 4 }, 2199 { ISD::SETCC, MVT::v32i8, 4 }, 2200 2201 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 2202 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 2203 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 2204 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 2205 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 2206 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 2207 }; 2208 2209 static const CostTblEntry SSE42CostTbl[] = { 2210 { ISD::SETCC, MVT::v2f64, 1 }, 2211 { ISD::SETCC, MVT::v4f32, 1 }, 2212 { ISD::SETCC, MVT::v2i64, 1 }, 2213 }; 2214 2215 static const CostTblEntry SSE41CostTbl[] = { 2216 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 2217 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 2218 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 2219 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 2220 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 2221 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 2222 }; 2223 2224 static const CostTblEntry SSE2CostTbl[] = { 2225 { ISD::SETCC, MVT::v2f64, 2 }, 2226 { ISD::SETCC, MVT::f64, 1 }, 2227 { ISD::SETCC, MVT::v2i64, 8 }, 2228 { ISD::SETCC, MVT::v4i32, 1 }, 2229 { ISD::SETCC, MVT::v8i16, 1 }, 2230 { ISD::SETCC, MVT::v16i8, 1 }, 2231 2232 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 2233 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 2234 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 2235 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 2236 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 2237 }; 2238 2239 static const CostTblEntry SSE1CostTbl[] = { 2240 { ISD::SETCC, MVT::v4f32, 2 }, 2241 { ISD::SETCC, MVT::f32, 1 }, 2242 2243 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 2244 }; 2245 2246 if (ST->isSLM()) 2247 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2248 return LT.first * (ExtraCost + Entry->Cost); 2249 2250 if (ST->hasBWI()) 2251 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2252 return LT.first * (ExtraCost + Entry->Cost); 2253 2254 if (ST->hasAVX512()) 2255 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2256 return LT.first * (ExtraCost + Entry->Cost); 2257 2258 if (ST->hasAVX2()) 2259 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2260 return LT.first * (ExtraCost + Entry->Cost); 2261 2262 if (ST->hasAVX()) 2263 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2264 return LT.first * (ExtraCost + Entry->Cost); 2265 2266 if (ST->hasSSE42()) 2267 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2268 return LT.first * (ExtraCost + Entry->Cost); 2269 2270 if (ST->hasSSE41()) 2271 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2272 return LT.first * (ExtraCost + Entry->Cost); 2273 2274 if (ST->hasSSE2()) 2275 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2276 return LT.first * (ExtraCost + Entry->Cost); 2277 2278 if (ST->hasSSE1()) 2279 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2280 return LT.first * (ExtraCost + Entry->Cost); 2281 2282 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I); 2283 } 2284 2285 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2286 2287 InstructionCost 2288 X86TTIImpl::getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 2289 TTI::TargetCostKind CostKind) { 2290 2291 // Costs should match the codegen from: 2292 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2293 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2294 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2295 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2296 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2297 2298 // TODO: Overflow intrinsics (*ADDO, *SUBO, *MULO) with vector types are not 2299 // specialized in these tables yet. 2300 static const CostTblEntry AVX512CDCostTbl[] = { 2301 { ISD::CTLZ, MVT::v8i64, 1 }, 2302 { ISD::CTLZ, MVT::v16i32, 1 }, 2303 { ISD::CTLZ, MVT::v32i16, 8 }, 2304 { ISD::CTLZ, MVT::v64i8, 20 }, 2305 { ISD::CTLZ, MVT::v4i64, 1 }, 2306 { ISD::CTLZ, MVT::v8i32, 1 }, 2307 { ISD::CTLZ, MVT::v16i16, 4 }, 2308 { ISD::CTLZ, MVT::v32i8, 10 }, 2309 { ISD::CTLZ, MVT::v2i64, 1 }, 2310 { ISD::CTLZ, MVT::v4i32, 1 }, 2311 { ISD::CTLZ, MVT::v8i16, 4 }, 2312 { ISD::CTLZ, MVT::v16i8, 4 }, 2313 }; 2314 static const CostTblEntry AVX512BWCostTbl[] = { 2315 { ISD::ABS, MVT::v32i16, 1 }, 2316 { ISD::ABS, MVT::v64i8, 1 }, 2317 { ISD::BITREVERSE, MVT::v8i64, 5 }, 2318 { ISD::BITREVERSE, MVT::v16i32, 5 }, 2319 { ISD::BITREVERSE, MVT::v32i16, 5 }, 2320 { ISD::BITREVERSE, MVT::v64i8, 5 }, 2321 { ISD::CTLZ, MVT::v8i64, 23 }, 2322 { ISD::CTLZ, MVT::v16i32, 22 }, 2323 { ISD::CTLZ, MVT::v32i16, 18 }, 2324 { ISD::CTLZ, MVT::v64i8, 17 }, 2325 { ISD::CTPOP, MVT::v8i64, 7 }, 2326 { ISD::CTPOP, MVT::v16i32, 11 }, 2327 { ISD::CTPOP, MVT::v32i16, 9 }, 2328 { ISD::CTPOP, MVT::v64i8, 6 }, 2329 { ISD::CTTZ, MVT::v8i64, 10 }, 2330 { ISD::CTTZ, MVT::v16i32, 14 }, 2331 { ISD::CTTZ, MVT::v32i16, 12 }, 2332 { ISD::CTTZ, MVT::v64i8, 9 }, 2333 { ISD::SADDSAT, MVT::v32i16, 1 }, 2334 { ISD::SADDSAT, MVT::v64i8, 1 }, 2335 { ISD::SMAX, MVT::v32i16, 1 }, 2336 { ISD::SMAX, MVT::v64i8, 1 }, 2337 { ISD::SMIN, MVT::v32i16, 1 }, 2338 { ISD::SMIN, MVT::v64i8, 1 }, 2339 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2340 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2341 { ISD::UADDSAT, MVT::v32i16, 1 }, 2342 { ISD::UADDSAT, MVT::v64i8, 1 }, 2343 { ISD::UMAX, MVT::v32i16, 1 }, 2344 { ISD::UMAX, MVT::v64i8, 1 }, 2345 { ISD::UMIN, MVT::v32i16, 1 }, 2346 { ISD::UMIN, MVT::v64i8, 1 }, 2347 { ISD::USUBSAT, MVT::v32i16, 1 }, 2348 { ISD::USUBSAT, MVT::v64i8, 1 }, 2349 }; 2350 static const CostTblEntry AVX512CostTbl[] = { 2351 { ISD::ABS, MVT::v8i64, 1 }, 2352 { ISD::ABS, MVT::v16i32, 1 }, 2353 { ISD::ABS, MVT::v32i16, 2 }, // FIXME: include split 2354 { ISD::ABS, MVT::v64i8, 2 }, // FIXME: include split 2355 { ISD::ABS, MVT::v4i64, 1 }, 2356 { ISD::ABS, MVT::v2i64, 1 }, 2357 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2358 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2359 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2360 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2361 { ISD::CTLZ, MVT::v8i64, 29 }, 2362 { ISD::CTLZ, MVT::v16i32, 35 }, 2363 { ISD::CTLZ, MVT::v32i16, 28 }, 2364 { ISD::CTLZ, MVT::v64i8, 18 }, 2365 { ISD::CTPOP, MVT::v8i64, 16 }, 2366 { ISD::CTPOP, MVT::v16i32, 24 }, 2367 { ISD::CTPOP, MVT::v32i16, 18 }, 2368 { ISD::CTPOP, MVT::v64i8, 12 }, 2369 { ISD::CTTZ, MVT::v8i64, 20 }, 2370 { ISD::CTTZ, MVT::v16i32, 28 }, 2371 { ISD::CTTZ, MVT::v32i16, 24 }, 2372 { ISD::CTTZ, MVT::v64i8, 18 }, 2373 { ISD::SMAX, MVT::v8i64, 1 }, 2374 { ISD::SMAX, MVT::v16i32, 1 }, 2375 { ISD::SMAX, MVT::v32i16, 2 }, // FIXME: include split 2376 { ISD::SMAX, MVT::v64i8, 2 }, // FIXME: include split 2377 { ISD::SMAX, MVT::v4i64, 1 }, 2378 { ISD::SMAX, MVT::v2i64, 1 }, 2379 { ISD::SMIN, MVT::v8i64, 1 }, 2380 { ISD::SMIN, MVT::v16i32, 1 }, 2381 { ISD::SMIN, MVT::v32i16, 2 }, // FIXME: include split 2382 { ISD::SMIN, MVT::v64i8, 2 }, // FIXME: include split 2383 { ISD::SMIN, MVT::v4i64, 1 }, 2384 { ISD::SMIN, MVT::v2i64, 1 }, 2385 { ISD::UMAX, MVT::v8i64, 1 }, 2386 { ISD::UMAX, MVT::v16i32, 1 }, 2387 { ISD::UMAX, MVT::v32i16, 2 }, // FIXME: include split 2388 { ISD::UMAX, MVT::v64i8, 2 }, // FIXME: include split 2389 { ISD::UMAX, MVT::v4i64, 1 }, 2390 { ISD::UMAX, MVT::v2i64, 1 }, 2391 { ISD::UMIN, MVT::v8i64, 1 }, 2392 { ISD::UMIN, MVT::v16i32, 1 }, 2393 { ISD::UMIN, MVT::v32i16, 2 }, // FIXME: include split 2394 { ISD::UMIN, MVT::v64i8, 2 }, // FIXME: include split 2395 { ISD::UMIN, MVT::v4i64, 1 }, 2396 { ISD::UMIN, MVT::v2i64, 1 }, 2397 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2398 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2399 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2400 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2401 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2402 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2403 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2404 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2405 { ISD::SADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2406 { ISD::SADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2407 { ISD::SSUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2408 { ISD::SSUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2409 { ISD::UADDSAT, MVT::v32i16, 2 }, // FIXME: include split 2410 { ISD::UADDSAT, MVT::v64i8, 2 }, // FIXME: include split 2411 { ISD::USUBSAT, MVT::v32i16, 2 }, // FIXME: include split 2412 { ISD::USUBSAT, MVT::v64i8, 2 }, // FIXME: include split 2413 { ISD::FMAXNUM, MVT::f32, 2 }, 2414 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2415 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2416 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2417 { ISD::FMAXNUM, MVT::f64, 2 }, 2418 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2419 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2420 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2421 }; 2422 static const CostTblEntry XOPCostTbl[] = { 2423 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2424 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2425 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2426 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2427 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2428 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2429 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2430 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2431 { ISD::BITREVERSE, MVT::i64, 3 }, 2432 { ISD::BITREVERSE, MVT::i32, 3 }, 2433 { ISD::BITREVERSE, MVT::i16, 3 }, 2434 { ISD::BITREVERSE, MVT::i8, 3 } 2435 }; 2436 static const CostTblEntry AVX2CostTbl[] = { 2437 { ISD::ABS, MVT::v4i64, 2 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2438 { ISD::ABS, MVT::v8i32, 1 }, 2439 { ISD::ABS, MVT::v16i16, 1 }, 2440 { ISD::ABS, MVT::v32i8, 1 }, 2441 { ISD::BITREVERSE, MVT::v4i64, 5 }, 2442 { ISD::BITREVERSE, MVT::v8i32, 5 }, 2443 { ISD::BITREVERSE, MVT::v16i16, 5 }, 2444 { ISD::BITREVERSE, MVT::v32i8, 5 }, 2445 { ISD::BSWAP, MVT::v4i64, 1 }, 2446 { ISD::BSWAP, MVT::v8i32, 1 }, 2447 { ISD::BSWAP, MVT::v16i16, 1 }, 2448 { ISD::CTLZ, MVT::v4i64, 23 }, 2449 { ISD::CTLZ, MVT::v8i32, 18 }, 2450 { ISD::CTLZ, MVT::v16i16, 14 }, 2451 { ISD::CTLZ, MVT::v32i8, 9 }, 2452 { ISD::CTPOP, MVT::v4i64, 7 }, 2453 { ISD::CTPOP, MVT::v8i32, 11 }, 2454 { ISD::CTPOP, MVT::v16i16, 9 }, 2455 { ISD::CTPOP, MVT::v32i8, 6 }, 2456 { ISD::CTTZ, MVT::v4i64, 10 }, 2457 { ISD::CTTZ, MVT::v8i32, 14 }, 2458 { ISD::CTTZ, MVT::v16i16, 12 }, 2459 { ISD::CTTZ, MVT::v32i8, 9 }, 2460 { ISD::SADDSAT, MVT::v16i16, 1 }, 2461 { ISD::SADDSAT, MVT::v32i8, 1 }, 2462 { ISD::SMAX, MVT::v8i32, 1 }, 2463 { ISD::SMAX, MVT::v16i16, 1 }, 2464 { ISD::SMAX, MVT::v32i8, 1 }, 2465 { ISD::SMIN, MVT::v8i32, 1 }, 2466 { ISD::SMIN, MVT::v16i16, 1 }, 2467 { ISD::SMIN, MVT::v32i8, 1 }, 2468 { ISD::SSUBSAT, MVT::v16i16, 1 }, 2469 { ISD::SSUBSAT, MVT::v32i8, 1 }, 2470 { ISD::UADDSAT, MVT::v16i16, 1 }, 2471 { ISD::UADDSAT, MVT::v32i8, 1 }, 2472 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 2473 { ISD::UMAX, MVT::v8i32, 1 }, 2474 { ISD::UMAX, MVT::v16i16, 1 }, 2475 { ISD::UMAX, MVT::v32i8, 1 }, 2476 { ISD::UMIN, MVT::v8i32, 1 }, 2477 { ISD::UMIN, MVT::v16i16, 1 }, 2478 { ISD::UMIN, MVT::v32i8, 1 }, 2479 { ISD::USUBSAT, MVT::v16i16, 1 }, 2480 { ISD::USUBSAT, MVT::v32i8, 1 }, 2481 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2482 { ISD::FMAXNUM, MVT::v8f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2483 { ISD::FMAXNUM, MVT::v4f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2484 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2485 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2486 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2487 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2488 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2489 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2490 }; 2491 static const CostTblEntry AVX1CostTbl[] = { 2492 { ISD::ABS, MVT::v4i64, 5 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2493 { ISD::ABS, MVT::v8i32, 3 }, 2494 { ISD::ABS, MVT::v16i16, 3 }, 2495 { ISD::ABS, MVT::v32i8, 3 }, 2496 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 2497 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 2498 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 2499 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 2500 { ISD::BSWAP, MVT::v4i64, 4 }, 2501 { ISD::BSWAP, MVT::v8i32, 4 }, 2502 { ISD::BSWAP, MVT::v16i16, 4 }, 2503 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 2504 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 2505 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 2506 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2507 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 2508 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 2509 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 2510 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 2511 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 2512 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 2513 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 2514 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2515 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2516 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2517 { ISD::SMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2518 { ISD::SMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2519 { ISD::SMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2520 { ISD::SMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2521 { ISD::SMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2522 { ISD::SMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2523 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2524 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2525 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2526 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2527 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 2528 { ISD::UMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2529 { ISD::UMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2530 { ISD::UMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2531 { ISD::UMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 2532 { ISD::UMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2533 { ISD::UMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2534 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2535 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2536 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 2537 { ISD::FMAXNUM, MVT::f32, 3 }, // MAXSS + CMPUNORDSS + BLENDVPS 2538 { ISD::FMAXNUM, MVT::v4f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 2539 { ISD::FMAXNUM, MVT::v8f32, 5 }, // MAXPS + CMPUNORDPS + BLENDVPS + ? 2540 { ISD::FMAXNUM, MVT::f64, 3 }, // MAXSD + CMPUNORDSD + BLENDVPD 2541 { ISD::FMAXNUM, MVT::v2f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 2542 { ISD::FMAXNUM, MVT::v4f64, 5 }, // MAXPD + CMPUNORDPD + BLENDVPD + ? 2543 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 2544 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 2545 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 2546 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 2547 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 2548 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 2549 }; 2550 static const CostTblEntry GLMCostTbl[] = { 2551 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 2552 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 2553 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 2554 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 2555 }; 2556 static const CostTblEntry SLMCostTbl[] = { 2557 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 2558 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 2559 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 2560 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 2561 }; 2562 static const CostTblEntry SSE42CostTbl[] = { 2563 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 2564 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 2565 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 2566 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 2567 }; 2568 static const CostTblEntry SSE41CostTbl[] = { 2569 { ISD::ABS, MVT::v2i64, 2 }, // BLENDVPD(X,PSUBQ(0,X),X) 2570 { ISD::SMAX, MVT::v4i32, 1 }, 2571 { ISD::SMAX, MVT::v16i8, 1 }, 2572 { ISD::SMIN, MVT::v4i32, 1 }, 2573 { ISD::SMIN, MVT::v16i8, 1 }, 2574 { ISD::UMAX, MVT::v4i32, 1 }, 2575 { ISD::UMAX, MVT::v8i16, 1 }, 2576 { ISD::UMIN, MVT::v4i32, 1 }, 2577 { ISD::UMIN, MVT::v8i16, 1 }, 2578 }; 2579 static const CostTblEntry SSSE3CostTbl[] = { 2580 { ISD::ABS, MVT::v4i32, 1 }, 2581 { ISD::ABS, MVT::v8i16, 1 }, 2582 { ISD::ABS, MVT::v16i8, 1 }, 2583 { ISD::BITREVERSE, MVT::v2i64, 5 }, 2584 { ISD::BITREVERSE, MVT::v4i32, 5 }, 2585 { ISD::BITREVERSE, MVT::v8i16, 5 }, 2586 { ISD::BITREVERSE, MVT::v16i8, 5 }, 2587 { ISD::BSWAP, MVT::v2i64, 1 }, 2588 { ISD::BSWAP, MVT::v4i32, 1 }, 2589 { ISD::BSWAP, MVT::v8i16, 1 }, 2590 { ISD::CTLZ, MVT::v2i64, 23 }, 2591 { ISD::CTLZ, MVT::v4i32, 18 }, 2592 { ISD::CTLZ, MVT::v8i16, 14 }, 2593 { ISD::CTLZ, MVT::v16i8, 9 }, 2594 { ISD::CTPOP, MVT::v2i64, 7 }, 2595 { ISD::CTPOP, MVT::v4i32, 11 }, 2596 { ISD::CTPOP, MVT::v8i16, 9 }, 2597 { ISD::CTPOP, MVT::v16i8, 6 }, 2598 { ISD::CTTZ, MVT::v2i64, 10 }, 2599 { ISD::CTTZ, MVT::v4i32, 14 }, 2600 { ISD::CTTZ, MVT::v8i16, 12 }, 2601 { ISD::CTTZ, MVT::v16i8, 9 } 2602 }; 2603 static const CostTblEntry SSE2CostTbl[] = { 2604 { ISD::ABS, MVT::v2i64, 4 }, 2605 { ISD::ABS, MVT::v4i32, 3 }, 2606 { ISD::ABS, MVT::v8i16, 2 }, 2607 { ISD::ABS, MVT::v16i8, 2 }, 2608 { ISD::BITREVERSE, MVT::v2i64, 29 }, 2609 { ISD::BITREVERSE, MVT::v4i32, 27 }, 2610 { ISD::BITREVERSE, MVT::v8i16, 27 }, 2611 { ISD::BITREVERSE, MVT::v16i8, 20 }, 2612 { ISD::BSWAP, MVT::v2i64, 7 }, 2613 { ISD::BSWAP, MVT::v4i32, 7 }, 2614 { ISD::BSWAP, MVT::v8i16, 7 }, 2615 { ISD::CTLZ, MVT::v2i64, 25 }, 2616 { ISD::CTLZ, MVT::v4i32, 26 }, 2617 { ISD::CTLZ, MVT::v8i16, 20 }, 2618 { ISD::CTLZ, MVT::v16i8, 17 }, 2619 { ISD::CTPOP, MVT::v2i64, 12 }, 2620 { ISD::CTPOP, MVT::v4i32, 15 }, 2621 { ISD::CTPOP, MVT::v8i16, 13 }, 2622 { ISD::CTPOP, MVT::v16i8, 10 }, 2623 { ISD::CTTZ, MVT::v2i64, 14 }, 2624 { ISD::CTTZ, MVT::v4i32, 18 }, 2625 { ISD::CTTZ, MVT::v8i16, 16 }, 2626 { ISD::CTTZ, MVT::v16i8, 13 }, 2627 { ISD::SADDSAT, MVT::v8i16, 1 }, 2628 { ISD::SADDSAT, MVT::v16i8, 1 }, 2629 { ISD::SMAX, MVT::v8i16, 1 }, 2630 { ISD::SMIN, MVT::v8i16, 1 }, 2631 { ISD::SSUBSAT, MVT::v8i16, 1 }, 2632 { ISD::SSUBSAT, MVT::v16i8, 1 }, 2633 { ISD::UADDSAT, MVT::v8i16, 1 }, 2634 { ISD::UADDSAT, MVT::v16i8, 1 }, 2635 { ISD::UMAX, MVT::v8i16, 2 }, 2636 { ISD::UMAX, MVT::v16i8, 1 }, 2637 { ISD::UMIN, MVT::v8i16, 2 }, 2638 { ISD::UMIN, MVT::v16i8, 1 }, 2639 { ISD::USUBSAT, MVT::v8i16, 1 }, 2640 { ISD::USUBSAT, MVT::v16i8, 1 }, 2641 { ISD::FMAXNUM, MVT::f64, 4 }, 2642 { ISD::FMAXNUM, MVT::v2f64, 4 }, 2643 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 2644 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 2645 }; 2646 static const CostTblEntry SSE1CostTbl[] = { 2647 { ISD::FMAXNUM, MVT::f32, 4 }, 2648 { ISD::FMAXNUM, MVT::v4f32, 4 }, 2649 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 2650 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 2651 }; 2652 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 2653 { ISD::CTTZ, MVT::i64, 1 }, 2654 }; 2655 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 2656 { ISD::CTTZ, MVT::i32, 1 }, 2657 { ISD::CTTZ, MVT::i16, 1 }, 2658 { ISD::CTTZ, MVT::i8, 1 }, 2659 }; 2660 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 2661 { ISD::CTLZ, MVT::i64, 1 }, 2662 }; 2663 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 2664 { ISD::CTLZ, MVT::i32, 1 }, 2665 { ISD::CTLZ, MVT::i16, 1 }, 2666 { ISD::CTLZ, MVT::i8, 1 }, 2667 }; 2668 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 2669 { ISD::CTPOP, MVT::i64, 1 }, 2670 }; 2671 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 2672 { ISD::CTPOP, MVT::i32, 1 }, 2673 { ISD::CTPOP, MVT::i16, 1 }, 2674 { ISD::CTPOP, MVT::i8, 1 }, 2675 }; 2676 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2677 { ISD::ABS, MVT::i64, 2 }, // SUB+CMOV 2678 { ISD::BITREVERSE, MVT::i64, 14 }, 2679 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 2680 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 2681 { ISD::CTPOP, MVT::i64, 10 }, 2682 { ISD::SADDO, MVT::i64, 1 }, 2683 { ISD::UADDO, MVT::i64, 1 }, 2684 { ISD::UMULO, MVT::i64, 2 }, // mulq + seto 2685 }; 2686 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2687 { ISD::ABS, MVT::i32, 2 }, // SUB+CMOV 2688 { ISD::ABS, MVT::i16, 2 }, // SUB+CMOV 2689 { ISD::BITREVERSE, MVT::i32, 14 }, 2690 { ISD::BITREVERSE, MVT::i16, 14 }, 2691 { ISD::BITREVERSE, MVT::i8, 11 }, 2692 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 2693 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 2694 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 2695 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 2696 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 2697 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 2698 { ISD::CTPOP, MVT::i32, 8 }, 2699 { ISD::CTPOP, MVT::i16, 9 }, 2700 { ISD::CTPOP, MVT::i8, 7 }, 2701 { ISD::SADDO, MVT::i32, 1 }, 2702 { ISD::SADDO, MVT::i16, 1 }, 2703 { ISD::SADDO, MVT::i8, 1 }, 2704 { ISD::UADDO, MVT::i32, 1 }, 2705 { ISD::UADDO, MVT::i16, 1 }, 2706 { ISD::UADDO, MVT::i8, 1 }, 2707 { ISD::UMULO, MVT::i32, 2 }, // mul + seto 2708 { ISD::UMULO, MVT::i16, 2 }, 2709 { ISD::UMULO, MVT::i8, 2 }, 2710 }; 2711 2712 Type *RetTy = ICA.getReturnType(); 2713 Type *OpTy = RetTy; 2714 Intrinsic::ID IID = ICA.getID(); 2715 unsigned ISD = ISD::DELETED_NODE; 2716 switch (IID) { 2717 default: 2718 break; 2719 case Intrinsic::abs: 2720 ISD = ISD::ABS; 2721 break; 2722 case Intrinsic::bitreverse: 2723 ISD = ISD::BITREVERSE; 2724 break; 2725 case Intrinsic::bswap: 2726 ISD = ISD::BSWAP; 2727 break; 2728 case Intrinsic::ctlz: 2729 ISD = ISD::CTLZ; 2730 break; 2731 case Intrinsic::ctpop: 2732 ISD = ISD::CTPOP; 2733 break; 2734 case Intrinsic::cttz: 2735 ISD = ISD::CTTZ; 2736 break; 2737 case Intrinsic::maxnum: 2738 case Intrinsic::minnum: 2739 // FMINNUM has same costs so don't duplicate. 2740 ISD = ISD::FMAXNUM; 2741 break; 2742 case Intrinsic::sadd_sat: 2743 ISD = ISD::SADDSAT; 2744 break; 2745 case Intrinsic::smax: 2746 ISD = ISD::SMAX; 2747 break; 2748 case Intrinsic::smin: 2749 ISD = ISD::SMIN; 2750 break; 2751 case Intrinsic::ssub_sat: 2752 ISD = ISD::SSUBSAT; 2753 break; 2754 case Intrinsic::uadd_sat: 2755 ISD = ISD::UADDSAT; 2756 break; 2757 case Intrinsic::umax: 2758 ISD = ISD::UMAX; 2759 break; 2760 case Intrinsic::umin: 2761 ISD = ISD::UMIN; 2762 break; 2763 case Intrinsic::usub_sat: 2764 ISD = ISD::USUBSAT; 2765 break; 2766 case Intrinsic::sqrt: 2767 ISD = ISD::FSQRT; 2768 break; 2769 case Intrinsic::sadd_with_overflow: 2770 case Intrinsic::ssub_with_overflow: 2771 // SSUBO has same costs so don't duplicate. 2772 ISD = ISD::SADDO; 2773 OpTy = RetTy->getContainedType(0); 2774 break; 2775 case Intrinsic::uadd_with_overflow: 2776 case Intrinsic::usub_with_overflow: 2777 // USUBO has same costs so don't duplicate. 2778 ISD = ISD::UADDO; 2779 OpTy = RetTy->getContainedType(0); 2780 break; 2781 case Intrinsic::umul_with_overflow: 2782 case Intrinsic::smul_with_overflow: 2783 // SMULO has same costs so don't duplicate. 2784 ISD = ISD::UMULO; 2785 OpTy = RetTy->getContainedType(0); 2786 break; 2787 } 2788 2789 if (ISD != ISD::DELETED_NODE) { 2790 // Legalize the type. 2791 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 2792 MVT MTy = LT.second; 2793 2794 // Attempt to lookup cost. 2795 if (ISD == ISD::BITREVERSE && ST->hasGFNI() && ST->hasSSSE3() && 2796 MTy.isVector()) { 2797 // With PSHUFB the code is very similar for all types. If we have integer 2798 // byte operations, we just need a GF2P8AFFINEQB for vXi8. For other types 2799 // we also need a PSHUFB. 2800 unsigned Cost = MTy.getVectorElementType() == MVT::i8 ? 1 : 2; 2801 2802 // Without byte operations, we need twice as many GF2P8AFFINEQB and PSHUFB 2803 // instructions. We also need an extract and an insert. 2804 if (!(MTy.is128BitVector() || (ST->hasAVX2() && MTy.is256BitVector()) || 2805 (ST->hasBWI() && MTy.is512BitVector()))) 2806 Cost = Cost * 2 + 2; 2807 2808 return LT.first * Cost; 2809 } 2810 2811 auto adjustTableCost = [](const CostTblEntry &Entry, int LegalizationCost, 2812 FastMathFlags FMF) { 2813 // If there are no NANs to deal with, then these are reduced to a 2814 // single MIN** or MAX** instruction instead of the MIN/CMP/SELECT that we 2815 // assume is used in the non-fast case. 2816 if (Entry.ISD == ISD::FMAXNUM || Entry.ISD == ISD::FMINNUM) { 2817 if (FMF.noNaNs()) 2818 return LegalizationCost * 1; 2819 } 2820 return LegalizationCost * (int)Entry.Cost; 2821 }; 2822 2823 if (ST->useGLMDivSqrtCosts()) 2824 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 2825 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2826 2827 if (ST->isSLM()) 2828 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2829 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2830 2831 if (ST->hasCDI()) 2832 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 2833 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2834 2835 if (ST->hasBWI()) 2836 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2837 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2838 2839 if (ST->hasAVX512()) 2840 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2841 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2842 2843 if (ST->hasXOP()) 2844 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2845 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2846 2847 if (ST->hasAVX2()) 2848 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2849 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2850 2851 if (ST->hasAVX()) 2852 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2853 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2854 2855 if (ST->hasSSE42()) 2856 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2857 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2858 2859 if (ST->hasSSE41()) 2860 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2861 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2862 2863 if (ST->hasSSSE3()) 2864 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 2865 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2866 2867 if (ST->hasSSE2()) 2868 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2869 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2870 2871 if (ST->hasSSE1()) 2872 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2873 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2874 2875 if (ST->hasBMI()) { 2876 if (ST->is64Bit()) 2877 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 2878 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2879 2880 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 2881 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2882 } 2883 2884 if (ST->hasLZCNT()) { 2885 if (ST->is64Bit()) 2886 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 2887 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2888 2889 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 2890 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2891 } 2892 2893 if (ST->hasPOPCNT()) { 2894 if (ST->is64Bit()) 2895 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 2896 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2897 2898 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 2899 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2900 } 2901 2902 // TODO - add BMI (TZCNT) scalar handling 2903 2904 if (ST->is64Bit()) 2905 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2906 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2907 2908 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2909 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 2910 } 2911 2912 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 2913 } 2914 2915 InstructionCost 2916 X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 2917 TTI::TargetCostKind CostKind) { 2918 if (ICA.isTypeBasedOnly()) 2919 return getTypeBasedIntrinsicInstrCost(ICA, CostKind); 2920 2921 static const CostTblEntry AVX512CostTbl[] = { 2922 { ISD::ROTL, MVT::v8i64, 1 }, 2923 { ISD::ROTL, MVT::v4i64, 1 }, 2924 { ISD::ROTL, MVT::v2i64, 1 }, 2925 { ISD::ROTL, MVT::v16i32, 1 }, 2926 { ISD::ROTL, MVT::v8i32, 1 }, 2927 { ISD::ROTL, MVT::v4i32, 1 }, 2928 { ISD::ROTR, MVT::v8i64, 1 }, 2929 { ISD::ROTR, MVT::v4i64, 1 }, 2930 { ISD::ROTR, MVT::v2i64, 1 }, 2931 { ISD::ROTR, MVT::v16i32, 1 }, 2932 { ISD::ROTR, MVT::v8i32, 1 }, 2933 { ISD::ROTR, MVT::v4i32, 1 } 2934 }; 2935 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 2936 static const CostTblEntry XOPCostTbl[] = { 2937 { ISD::ROTL, MVT::v4i64, 4 }, 2938 { ISD::ROTL, MVT::v8i32, 4 }, 2939 { ISD::ROTL, MVT::v16i16, 4 }, 2940 { ISD::ROTL, MVT::v32i8, 4 }, 2941 { ISD::ROTL, MVT::v2i64, 1 }, 2942 { ISD::ROTL, MVT::v4i32, 1 }, 2943 { ISD::ROTL, MVT::v8i16, 1 }, 2944 { ISD::ROTL, MVT::v16i8, 1 }, 2945 { ISD::ROTR, MVT::v4i64, 6 }, 2946 { ISD::ROTR, MVT::v8i32, 6 }, 2947 { ISD::ROTR, MVT::v16i16, 6 }, 2948 { ISD::ROTR, MVT::v32i8, 6 }, 2949 { ISD::ROTR, MVT::v2i64, 2 }, 2950 { ISD::ROTR, MVT::v4i32, 2 }, 2951 { ISD::ROTR, MVT::v8i16, 2 }, 2952 { ISD::ROTR, MVT::v16i8, 2 } 2953 }; 2954 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2955 { ISD::ROTL, MVT::i64, 1 }, 2956 { ISD::ROTR, MVT::i64, 1 }, 2957 { ISD::FSHL, MVT::i64, 4 } 2958 }; 2959 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2960 { ISD::ROTL, MVT::i32, 1 }, 2961 { ISD::ROTL, MVT::i16, 1 }, 2962 { ISD::ROTL, MVT::i8, 1 }, 2963 { ISD::ROTR, MVT::i32, 1 }, 2964 { ISD::ROTR, MVT::i16, 1 }, 2965 { ISD::ROTR, MVT::i8, 1 }, 2966 { ISD::FSHL, MVT::i32, 4 }, 2967 { ISD::FSHL, MVT::i16, 4 }, 2968 { ISD::FSHL, MVT::i8, 4 } 2969 }; 2970 2971 Intrinsic::ID IID = ICA.getID(); 2972 Type *RetTy = ICA.getReturnType(); 2973 const SmallVectorImpl<const Value *> &Args = ICA.getArgs(); 2974 unsigned ISD = ISD::DELETED_NODE; 2975 switch (IID) { 2976 default: 2977 break; 2978 case Intrinsic::fshl: 2979 ISD = ISD::FSHL; 2980 if (Args[0] == Args[1]) 2981 ISD = ISD::ROTL; 2982 break; 2983 case Intrinsic::fshr: 2984 // FSHR has same costs so don't duplicate. 2985 ISD = ISD::FSHL; 2986 if (Args[0] == Args[1]) 2987 ISD = ISD::ROTR; 2988 break; 2989 } 2990 2991 if (ISD != ISD::DELETED_NODE) { 2992 // Legalize the type. 2993 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 2994 MVT MTy = LT.second; 2995 2996 // Attempt to lookup cost. 2997 if (ST->hasAVX512()) 2998 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2999 return LT.first * Entry->Cost; 3000 3001 if (ST->hasXOP()) 3002 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3003 return LT.first * Entry->Cost; 3004 3005 if (ST->is64Bit()) 3006 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3007 return LT.first * Entry->Cost; 3008 3009 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3010 return LT.first * Entry->Cost; 3011 } 3012 3013 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3014 } 3015 3016 int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { 3017 static const CostTblEntry SLMCostTbl[] = { 3018 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 3019 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 3020 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 3021 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 3022 }; 3023 3024 assert(Val->isVectorTy() && "This must be a vector type"); 3025 Type *ScalarType = Val->getScalarType(); 3026 int RegisterFileMoveCost = 0; 3027 3028 if (Index != -1U && (Opcode == Instruction::ExtractElement || 3029 Opcode == Instruction::InsertElement)) { 3030 // Legalize the type. 3031 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 3032 3033 // This type is legalized to a scalar type. 3034 if (!LT.second.isVector()) 3035 return 0; 3036 3037 // The type may be split. Normalize the index to the new type. 3038 unsigned NumElts = LT.second.getVectorNumElements(); 3039 unsigned SubNumElts = NumElts; 3040 Index = Index % NumElts; 3041 3042 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 3043 // For inserts, we also need to insert the subvector back. 3044 if (LT.second.getSizeInBits() > 128) { 3045 assert((LT.second.getSizeInBits() % 128) == 0 && "Illegal vector"); 3046 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 3047 SubNumElts = NumElts / NumSubVecs; 3048 if (SubNumElts <= Index) { 3049 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 3050 Index %= SubNumElts; 3051 } 3052 } 3053 3054 if (Index == 0) { 3055 // Floating point scalars are already located in index #0. 3056 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 3057 // true for all. 3058 if (ScalarType->isFloatingPointTy()) 3059 return RegisterFileMoveCost; 3060 3061 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 3062 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 3063 return 1 + RegisterFileMoveCost; 3064 } 3065 3066 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3067 assert(ISD && "Unexpected vector opcode"); 3068 MVT MScalarTy = LT.second.getScalarType(); 3069 if (ST->isSLM()) 3070 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 3071 return Entry->Cost + RegisterFileMoveCost; 3072 3073 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 3074 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3075 (MScalarTy.isInteger() && ST->hasSSE41())) 3076 return 1 + RegisterFileMoveCost; 3077 3078 // Assume insertps is relatively cheap on all targets. 3079 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 3080 Opcode == Instruction::InsertElement) 3081 return 1 + RegisterFileMoveCost; 3082 3083 // For extractions we just need to shuffle the element to index 0, which 3084 // should be very cheap (assume cost = 1). For insertions we need to shuffle 3085 // the elements to its destination. In both cases we must handle the 3086 // subvector move(s). 3087 // If the vector type is already less than 128-bits then don't reduce it. 3088 // TODO: Under what circumstances should we shuffle using the full width? 3089 int ShuffleCost = 1; 3090 if (Opcode == Instruction::InsertElement) { 3091 auto *SubTy = cast<VectorType>(Val); 3092 EVT VT = TLI->getValueType(DL, Val); 3093 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 3094 SubTy = FixedVectorType::get(ScalarType, SubNumElts); 3095 ShuffleCost = 3096 getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, None, 0, SubTy); 3097 } 3098 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 3099 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 3100 } 3101 3102 // Add to the base cost if we know that the extracted element of a vector is 3103 // destined to be moved to and used in the integer register file. 3104 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 3105 RegisterFileMoveCost += 1; 3106 3107 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 3108 } 3109 3110 unsigned X86TTIImpl::getScalarizationOverhead(VectorType *Ty, 3111 const APInt &DemandedElts, 3112 bool Insert, bool Extract) { 3113 unsigned Cost = 0; 3114 3115 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much 3116 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT. 3117 if (Insert) { 3118 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3119 MVT MScalarTy = LT.second.getScalarType(); 3120 3121 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3122 (MScalarTy.isInteger() && ST->hasSSE41()) || 3123 (MScalarTy == MVT::f32 && ST->hasSSE41())) { 3124 // For types we can insert directly, insertion into 128-bit sub vectors is 3125 // cheap, followed by a cheap chain of concatenations. 3126 if (LT.second.getSizeInBits() <= 128) { 3127 Cost += 3128 BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, false); 3129 } else { 3130 // In each 128-lane, if at least one index is demanded but not all 3131 // indices are demanded and this 128-lane is not the first 128-lane of 3132 // the legalized-vector, then this 128-lane needs a extracti128; If in 3133 // each 128-lane, there is at least one demanded index, this 128-lane 3134 // needs a inserti128. 3135 3136 // The following cases will help you build a better understanding: 3137 // Assume we insert several elements into a v8i32 vector in avx2, 3138 // Case#1: inserting into 1th index needs vpinsrd + inserti128. 3139 // Case#2: inserting into 5th index needs extracti128 + vpinsrd + 3140 // inserti128. 3141 // Case#3: inserting into 4,5,6,7 index needs 4*vpinsrd + inserti128. 3142 unsigned Num128Lanes = LT.second.getSizeInBits() / 128 * LT.first; 3143 unsigned NumElts = LT.second.getVectorNumElements() * LT.first; 3144 APInt WidenedDemandedElts = DemandedElts.zextOrSelf(NumElts); 3145 unsigned Scale = NumElts / Num128Lanes; 3146 // We iterate each 128-lane, and check if we need a 3147 // extracti128/inserti128 for this 128-lane. 3148 for (unsigned I = 0; I < NumElts; I += Scale) { 3149 APInt Mask = WidenedDemandedElts.getBitsSet(NumElts, I, I + Scale); 3150 APInt MaskedDE = Mask & WidenedDemandedElts; 3151 unsigned Population = MaskedDE.countPopulation(); 3152 Cost += (Population > 0 && Population != Scale && 3153 I % LT.second.getVectorNumElements() != 0); 3154 Cost += Population > 0; 3155 } 3156 Cost += DemandedElts.countPopulation(); 3157 3158 // For vXf32 cases, insertion into the 0'th index in each v4f32 3159 // 128-bit vector is free. 3160 // NOTE: This assumes legalization widens vXf32 vectors. 3161 if (MScalarTy == MVT::f32) 3162 for (unsigned i = 0, e = cast<FixedVectorType>(Ty)->getNumElements(); 3163 i < e; i += 4) 3164 if (DemandedElts[i]) 3165 Cost--; 3166 } 3167 } else if (LT.second.isVector()) { 3168 // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded 3169 // integer element as a SCALAR_TO_VECTOR, then we build the vector as a 3170 // series of UNPCK followed by CONCAT_VECTORS - all of these can be 3171 // considered cheap. 3172 if (Ty->isIntOrIntVectorTy()) 3173 Cost += DemandedElts.countPopulation(); 3174 3175 // Get the smaller of the legalized or original pow2-extended number of 3176 // vector elements, which represents the number of unpacks we'll end up 3177 // performing. 3178 unsigned NumElts = LT.second.getVectorNumElements(); 3179 unsigned Pow2Elts = 3180 PowerOf2Ceil(cast<FixedVectorType>(Ty)->getNumElements()); 3181 Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first; 3182 } 3183 } 3184 3185 // TODO: Use default extraction for now, but we should investigate extending this 3186 // to handle repeated subvector extraction. 3187 if (Extract) 3188 Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, false, Extract); 3189 3190 return Cost; 3191 } 3192 3193 int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 3194 MaybeAlign Alignment, unsigned AddressSpace, 3195 TTI::TargetCostKind CostKind, 3196 const Instruction *I) { 3197 // TODO: Handle other cost kinds. 3198 if (CostKind != TTI::TCK_RecipThroughput) { 3199 if (auto *SI = dyn_cast_or_null<StoreInst>(I)) { 3200 // Store instruction with index and scale costs 2 Uops. 3201 // Check the preceding GEP to identify non-const indices. 3202 if (auto *GEP = dyn_cast<GetElementPtrInst>(SI->getPointerOperand())) { 3203 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3204 return TTI::TCC_Basic * 2; 3205 } 3206 } 3207 return TTI::TCC_Basic; 3208 } 3209 3210 // Handle non-power-of-two vectors such as <3 x float> 3211 if (auto *VTy = dyn_cast<FixedVectorType>(Src)) { 3212 unsigned NumElem = VTy->getNumElements(); 3213 3214 // Handle a few common cases: 3215 // <3 x float> 3216 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 3217 // Cost = 64 bit store + extract + 32 bit store. 3218 return 3; 3219 3220 // <3 x double> 3221 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 3222 // Cost = 128 bit store + unpack + 64 bit store. 3223 return 3; 3224 3225 // Assume that all other non-power-of-two numbers are scalarized. 3226 if (!isPowerOf2_32(NumElem)) { 3227 APInt DemandedElts = APInt::getAllOnesValue(NumElem); 3228 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment, 3229 AddressSpace, CostKind); 3230 int SplitCost = getScalarizationOverhead(VTy, DemandedElts, 3231 Opcode == Instruction::Load, 3232 Opcode == Instruction::Store); 3233 return NumElem * Cost + SplitCost; 3234 } 3235 } 3236 3237 // Type legalization can't handle structs 3238 if (TLI->getValueType(DL, Src, true) == MVT::Other) 3239 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3240 CostKind); 3241 3242 // Legalize the type. 3243 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 3244 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 3245 "Invalid Opcode"); 3246 3247 // Each load/store unit costs 1. 3248 int Cost = LT.first * 1; 3249 3250 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a 3251 // proxy for a double-pumped AVX memory interface such as on Sandybridge. 3252 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow()) 3253 Cost *= 2; 3254 3255 return Cost; 3256 } 3257 3258 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, 3259 Align Alignment, unsigned AddressSpace, 3260 TTI::TargetCostKind CostKind) { 3261 bool IsLoad = (Instruction::Load == Opcode); 3262 bool IsStore = (Instruction::Store == Opcode); 3263 3264 auto *SrcVTy = dyn_cast<FixedVectorType>(SrcTy); 3265 if (!SrcVTy) 3266 // To calculate scalar take the regular cost, without mask 3267 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace, CostKind); 3268 3269 unsigned NumElem = SrcVTy->getNumElements(); 3270 auto *MaskTy = 3271 FixedVectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 3272 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, Alignment)) || 3273 (IsStore && !isLegalMaskedStore(SrcVTy, Alignment)) || 3274 !isPowerOf2_32(NumElem)) { 3275 // Scalarization 3276 APInt DemandedElts = APInt::getAllOnesValue(NumElem); 3277 int MaskSplitCost = 3278 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 3279 int ScalarCompareCost = getCmpSelInstrCost( 3280 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr, 3281 CmpInst::BAD_ICMP_PREDICATE, CostKind); 3282 int BranchCost = getCFInstrCost(Instruction::Br, CostKind); 3283 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 3284 int ValueSplitCost = 3285 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore); 3286 int MemopCost = 3287 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3288 Alignment, AddressSpace, CostKind); 3289 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 3290 } 3291 3292 // Legalize the type. 3293 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3294 auto VT = TLI->getValueType(DL, SrcVTy); 3295 int Cost = 0; 3296 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 3297 LT.second.getVectorNumElements() == NumElem) 3298 // Promotion requires expand/truncate for data and a shuffle for mask. 3299 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, None, 0, nullptr) + 3300 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, None, 0, nullptr); 3301 3302 else if (LT.second.getVectorNumElements() > NumElem) { 3303 auto *NewMaskTy = FixedVectorType::get(MaskTy->getElementType(), 3304 LT.second.getVectorNumElements()); 3305 // Expanding requires fill mask with zeroes 3306 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, None, 0, MaskTy); 3307 } 3308 3309 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 3310 if (!ST->hasAVX512()) 3311 return Cost + LT.first * (IsLoad ? 2 : 8); 3312 3313 // AVX-512 masked load/store is cheapper 3314 return Cost + LT.first; 3315 } 3316 3317 int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE, 3318 const SCEV *Ptr) { 3319 // Address computations in vectorized code with non-consecutive addresses will 3320 // likely result in more instructions compared to scalar code where the 3321 // computation can more often be merged into the index mode. The resulting 3322 // extra micro-ops can significantly decrease throughput. 3323 const unsigned NumVectorInstToHideOverhead = 10; 3324 3325 // Cost modeling of Strided Access Computation is hidden by the indexing 3326 // modes of X86 regardless of the stride value. We dont believe that there 3327 // is a difference between constant strided access in gerenal and constant 3328 // strided value which is less than or equal to 64. 3329 // Even in the case of (loop invariant) stride whose value is not known at 3330 // compile time, the address computation will not incur more than one extra 3331 // ADD instruction. 3332 if (Ty->isVectorTy() && SE) { 3333 if (!BaseT::isStridedAccess(Ptr)) 3334 return NumVectorInstToHideOverhead; 3335 if (!BaseT::getConstantStrideStep(SE, Ptr)) 3336 return 1; 3337 } 3338 3339 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 3340 } 3341 3342 int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 3343 bool IsPairwise, 3344 TTI::TargetCostKind CostKind) { 3345 // Just use the default implementation for pair reductions. 3346 if (IsPairwise) 3347 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise, CostKind); 3348 3349 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3350 // and make it as the cost. 3351 3352 static const CostTblEntry SLMCostTblNoPairWise[] = { 3353 { ISD::FADD, MVT::v2f64, 3 }, 3354 { ISD::ADD, MVT::v2i64, 5 }, 3355 }; 3356 3357 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3358 { ISD::FADD, MVT::v2f64, 2 }, 3359 { ISD::FADD, MVT::v4f32, 4 }, 3360 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 3361 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 3362 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 3363 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 3364 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 3365 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 3366 { ISD::ADD, MVT::v2i8, 2 }, 3367 { ISD::ADD, MVT::v4i8, 2 }, 3368 { ISD::ADD, MVT::v8i8, 2 }, 3369 { ISD::ADD, MVT::v16i8, 3 }, 3370 }; 3371 3372 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3373 { ISD::FADD, MVT::v4f64, 3 }, 3374 { ISD::FADD, MVT::v4f32, 3 }, 3375 { ISD::FADD, MVT::v8f32, 4 }, 3376 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 3377 { ISD::ADD, MVT::v4i64, 3 }, 3378 { ISD::ADD, MVT::v8i32, 5 }, 3379 { ISD::ADD, MVT::v16i16, 5 }, 3380 { ISD::ADD, MVT::v32i8, 4 }, 3381 }; 3382 3383 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3384 assert(ISD && "Invalid opcode"); 3385 3386 // Before legalizing the type, give a chance to look up illegal narrow types 3387 // in the table. 3388 // FIXME: Is there a better way to do this? 3389 EVT VT = TLI->getValueType(DL, ValTy); 3390 if (VT.isSimple()) { 3391 MVT MTy = VT.getSimpleVT(); 3392 if (ST->isSLM()) 3393 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3394 return Entry->Cost; 3395 3396 if (ST->hasAVX()) 3397 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3398 return Entry->Cost; 3399 3400 if (ST->hasSSE2()) 3401 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3402 return Entry->Cost; 3403 } 3404 3405 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3406 3407 MVT MTy = LT.second; 3408 3409 auto *ValVTy = cast<FixedVectorType>(ValTy); 3410 3411 // Special case: vXi8 mul reductions are performed as vXi16. 3412 if (ISD == ISD::MUL && MTy.getScalarType() == MVT::i8) { 3413 auto *WideSclTy = IntegerType::get(ValVTy->getContext(), 16); 3414 auto *WideVecTy = FixedVectorType::get(WideSclTy, ValVTy->getNumElements()); 3415 return getCastInstrCost(Instruction::ZExt, WideVecTy, ValTy, 3416 TargetTransformInfo::CastContextHint::None, 3417 CostKind) + 3418 getArithmeticReductionCost(Opcode, WideVecTy, IsPairwise, CostKind); 3419 } 3420 3421 unsigned ArithmeticCost = 0; 3422 if (LT.first != 1 && MTy.isVector() && 3423 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3424 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3425 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3426 MTy.getVectorNumElements()); 3427 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3428 ArithmeticCost *= LT.first - 1; 3429 } 3430 3431 if (ST->isSLM()) 3432 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 3433 return ArithmeticCost + Entry->Cost; 3434 3435 if (ST->hasAVX()) 3436 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3437 return ArithmeticCost + Entry->Cost; 3438 3439 if (ST->hasSSE2()) 3440 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3441 return ArithmeticCost + Entry->Cost; 3442 3443 // FIXME: These assume a naive kshift+binop lowering, which is probably 3444 // conservative in most cases. 3445 static const CostTblEntry AVX512BoolReduction[] = { 3446 { ISD::AND, MVT::v2i1, 3 }, 3447 { ISD::AND, MVT::v4i1, 5 }, 3448 { ISD::AND, MVT::v8i1, 7 }, 3449 { ISD::AND, MVT::v16i1, 9 }, 3450 { ISD::AND, MVT::v32i1, 11 }, 3451 { ISD::AND, MVT::v64i1, 13 }, 3452 { ISD::OR, MVT::v2i1, 3 }, 3453 { ISD::OR, MVT::v4i1, 5 }, 3454 { ISD::OR, MVT::v8i1, 7 }, 3455 { ISD::OR, MVT::v16i1, 9 }, 3456 { ISD::OR, MVT::v32i1, 11 }, 3457 { ISD::OR, MVT::v64i1, 13 }, 3458 }; 3459 3460 static const CostTblEntry AVX2BoolReduction[] = { 3461 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 3462 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 3463 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 3464 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 3465 }; 3466 3467 static const CostTblEntry AVX1BoolReduction[] = { 3468 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 3469 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 3470 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3471 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 3472 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 3473 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 3474 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3475 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 3476 }; 3477 3478 static const CostTblEntry SSE2BoolReduction[] = { 3479 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 3480 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 3481 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 3482 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 3483 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 3484 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 3485 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 3486 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 3487 }; 3488 3489 // Handle bool allof/anyof patterns. 3490 if (ValVTy->getElementType()->isIntegerTy(1)) { 3491 unsigned ArithmeticCost = 0; 3492 if (LT.first != 1 && MTy.isVector() && 3493 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3494 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3495 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 3496 MTy.getVectorNumElements()); 3497 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 3498 ArithmeticCost *= LT.first - 1; 3499 } 3500 3501 if (ST->hasAVX512()) 3502 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 3503 return ArithmeticCost + Entry->Cost; 3504 if (ST->hasAVX2()) 3505 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 3506 return ArithmeticCost + Entry->Cost; 3507 if (ST->hasAVX()) 3508 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 3509 return ArithmeticCost + Entry->Cost; 3510 if (ST->hasSSE2()) 3511 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 3512 return ArithmeticCost + Entry->Cost; 3513 3514 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise, 3515 CostKind); 3516 } 3517 3518 unsigned NumVecElts = ValVTy->getNumElements(); 3519 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 3520 3521 // Special case power of 2 reductions where the scalar type isn't changed 3522 // by type legalization. 3523 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 3524 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, IsPairwise, 3525 CostKind); 3526 3527 unsigned ReductionCost = 0; 3528 3529 auto *Ty = ValVTy; 3530 if (LT.first != 1 && MTy.isVector() && 3531 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3532 // Type needs to be split. We need LT.first - 1 arithmetic ops. 3533 Ty = FixedVectorType::get(ValVTy->getElementType(), 3534 MTy.getVectorNumElements()); 3535 ReductionCost = getArithmeticInstrCost(Opcode, Ty, CostKind); 3536 ReductionCost *= LT.first - 1; 3537 NumVecElts = MTy.getVectorNumElements(); 3538 } 3539 3540 // Now handle reduction with the legal type, taking into account size changes 3541 // at each level. 3542 while (NumVecElts > 1) { 3543 // Determine the size of the remaining vector we need to reduce. 3544 unsigned Size = NumVecElts * ScalarSize; 3545 NumVecElts /= 2; 3546 // If we're reducing from 256/512 bits, use an extract_subvector. 3547 if (Size > 128) { 3548 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 3549 ReductionCost += 3550 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 3551 Ty = SubTy; 3552 } else if (Size == 128) { 3553 // Reducing from 128 bits is a permute of v2f64/v2i64. 3554 FixedVectorType *ShufTy; 3555 if (ValVTy->isFloatingPointTy()) 3556 ShufTy = 3557 FixedVectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 3558 else 3559 ShufTy = 3560 FixedVectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 3561 ReductionCost += 3562 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3563 } else if (Size == 64) { 3564 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3565 FixedVectorType *ShufTy; 3566 if (ValVTy->isFloatingPointTy()) 3567 ShufTy = 3568 FixedVectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 3569 else 3570 ShufTy = 3571 FixedVectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 3572 ReductionCost += 3573 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3574 } else { 3575 // Reducing from smaller size is a shift by immediate. 3576 auto *ShiftTy = FixedVectorType::get( 3577 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 3578 ReductionCost += getArithmeticInstrCost( 3579 Instruction::LShr, ShiftTy, CostKind, 3580 TargetTransformInfo::OK_AnyValue, 3581 TargetTransformInfo::OK_UniformConstantValue, 3582 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3583 } 3584 3585 // Add the arithmetic op for this level. 3586 ReductionCost += getArithmeticInstrCost(Opcode, Ty, CostKind); 3587 } 3588 3589 // Add the final extract element to the cost. 3590 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3591 } 3592 3593 int X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, bool IsUnsigned) { 3594 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3595 3596 MVT MTy = LT.second; 3597 3598 int ISD; 3599 if (Ty->isIntOrIntVectorTy()) { 3600 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3601 } else { 3602 assert(Ty->isFPOrFPVectorTy() && 3603 "Expected float point or integer vector type."); 3604 ISD = ISD::FMINNUM; 3605 } 3606 3607 static const CostTblEntry SSE1CostTbl[] = { 3608 {ISD::FMINNUM, MVT::v4f32, 1}, 3609 }; 3610 3611 static const CostTblEntry SSE2CostTbl[] = { 3612 {ISD::FMINNUM, MVT::v2f64, 1}, 3613 {ISD::SMIN, MVT::v8i16, 1}, 3614 {ISD::UMIN, MVT::v16i8, 1}, 3615 }; 3616 3617 static const CostTblEntry SSE41CostTbl[] = { 3618 {ISD::SMIN, MVT::v4i32, 1}, 3619 {ISD::UMIN, MVT::v4i32, 1}, 3620 {ISD::UMIN, MVT::v8i16, 1}, 3621 {ISD::SMIN, MVT::v16i8, 1}, 3622 }; 3623 3624 static const CostTblEntry SSE42CostTbl[] = { 3625 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 3626 }; 3627 3628 static const CostTblEntry AVX1CostTbl[] = { 3629 {ISD::FMINNUM, MVT::v8f32, 1}, 3630 {ISD::FMINNUM, MVT::v4f64, 1}, 3631 {ISD::SMIN, MVT::v8i32, 3}, 3632 {ISD::UMIN, MVT::v8i32, 3}, 3633 {ISD::SMIN, MVT::v16i16, 3}, 3634 {ISD::UMIN, MVT::v16i16, 3}, 3635 {ISD::SMIN, MVT::v32i8, 3}, 3636 {ISD::UMIN, MVT::v32i8, 3}, 3637 }; 3638 3639 static const CostTblEntry AVX2CostTbl[] = { 3640 {ISD::SMIN, MVT::v8i32, 1}, 3641 {ISD::UMIN, MVT::v8i32, 1}, 3642 {ISD::SMIN, MVT::v16i16, 1}, 3643 {ISD::UMIN, MVT::v16i16, 1}, 3644 {ISD::SMIN, MVT::v32i8, 1}, 3645 {ISD::UMIN, MVT::v32i8, 1}, 3646 }; 3647 3648 static const CostTblEntry AVX512CostTbl[] = { 3649 {ISD::FMINNUM, MVT::v16f32, 1}, 3650 {ISD::FMINNUM, MVT::v8f64, 1}, 3651 {ISD::SMIN, MVT::v2i64, 1}, 3652 {ISD::UMIN, MVT::v2i64, 1}, 3653 {ISD::SMIN, MVT::v4i64, 1}, 3654 {ISD::UMIN, MVT::v4i64, 1}, 3655 {ISD::SMIN, MVT::v8i64, 1}, 3656 {ISD::UMIN, MVT::v8i64, 1}, 3657 {ISD::SMIN, MVT::v16i32, 1}, 3658 {ISD::UMIN, MVT::v16i32, 1}, 3659 }; 3660 3661 static const CostTblEntry AVX512BWCostTbl[] = { 3662 {ISD::SMIN, MVT::v32i16, 1}, 3663 {ISD::UMIN, MVT::v32i16, 1}, 3664 {ISD::SMIN, MVT::v64i8, 1}, 3665 {ISD::UMIN, MVT::v64i8, 1}, 3666 }; 3667 3668 // If we have a native MIN/MAX instruction for this type, use it. 3669 if (ST->hasBWI()) 3670 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3671 return LT.first * Entry->Cost; 3672 3673 if (ST->hasAVX512()) 3674 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3675 return LT.first * Entry->Cost; 3676 3677 if (ST->hasAVX2()) 3678 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3679 return LT.first * Entry->Cost; 3680 3681 if (ST->hasAVX()) 3682 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3683 return LT.first * Entry->Cost; 3684 3685 if (ST->hasSSE42()) 3686 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3687 return LT.first * Entry->Cost; 3688 3689 if (ST->hasSSE41()) 3690 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3691 return LT.first * Entry->Cost; 3692 3693 if (ST->hasSSE2()) 3694 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3695 return LT.first * Entry->Cost; 3696 3697 if (ST->hasSSE1()) 3698 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3699 return LT.first * Entry->Cost; 3700 3701 unsigned CmpOpcode; 3702 if (Ty->isFPOrFPVectorTy()) { 3703 CmpOpcode = Instruction::FCmp; 3704 } else { 3705 assert(Ty->isIntOrIntVectorTy() && 3706 "expecting floating point or integer type for min/max reduction"); 3707 CmpOpcode = Instruction::ICmp; 3708 } 3709 3710 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 3711 // Otherwise fall back to cmp+select. 3712 return getCmpSelInstrCost(CmpOpcode, Ty, CondTy, CmpInst::BAD_ICMP_PREDICATE, 3713 CostKind) + 3714 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, 3715 CmpInst::BAD_ICMP_PREDICATE, CostKind); 3716 } 3717 3718 int X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 3719 bool IsPairwise, bool IsUnsigned, 3720 TTI::TargetCostKind CostKind) { 3721 // Just use the default implementation for pair reductions. 3722 if (IsPairwise) 3723 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned, 3724 CostKind); 3725 3726 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 3727 3728 MVT MTy = LT.second; 3729 3730 int ISD; 3731 if (ValTy->isIntOrIntVectorTy()) { 3732 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 3733 } else { 3734 assert(ValTy->isFPOrFPVectorTy() && 3735 "Expected float point or integer vector type."); 3736 ISD = ISD::FMINNUM; 3737 } 3738 3739 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 3740 // and make it as the cost. 3741 3742 static const CostTblEntry SSE2CostTblNoPairWise[] = { 3743 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 3744 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 3745 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 3746 }; 3747 3748 static const CostTblEntry SSE41CostTblNoPairWise[] = { 3749 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 3750 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 3751 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 3752 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 3753 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 3754 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 3755 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 3756 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 3757 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 3758 {ISD::SMIN, MVT::v16i8, 6}, 3759 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 3760 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 3761 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 3762 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 3763 }; 3764 3765 static const CostTblEntry AVX1CostTblNoPairWise[] = { 3766 {ISD::SMIN, MVT::v16i16, 6}, 3767 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 3768 {ISD::SMIN, MVT::v32i8, 8}, 3769 {ISD::UMIN, MVT::v32i8, 8}, 3770 }; 3771 3772 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 3773 {ISD::SMIN, MVT::v32i16, 8}, 3774 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 3775 {ISD::SMIN, MVT::v64i8, 10}, 3776 {ISD::UMIN, MVT::v64i8, 10}, 3777 }; 3778 3779 // Before legalizing the type, give a chance to look up illegal narrow types 3780 // in the table. 3781 // FIXME: Is there a better way to do this? 3782 EVT VT = TLI->getValueType(DL, ValTy); 3783 if (VT.isSimple()) { 3784 MVT MTy = VT.getSimpleVT(); 3785 if (ST->hasBWI()) 3786 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3787 return Entry->Cost; 3788 3789 if (ST->hasAVX()) 3790 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3791 return Entry->Cost; 3792 3793 if (ST->hasSSE41()) 3794 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3795 return Entry->Cost; 3796 3797 if (ST->hasSSE2()) 3798 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3799 return Entry->Cost; 3800 } 3801 3802 auto *ValVTy = cast<FixedVectorType>(ValTy); 3803 unsigned NumVecElts = ValVTy->getNumElements(); 3804 3805 auto *Ty = ValVTy; 3806 unsigned MinMaxCost = 0; 3807 if (LT.first != 1 && MTy.isVector() && 3808 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 3809 // Type needs to be split. We need LT.first - 1 operations ops. 3810 Ty = FixedVectorType::get(ValVTy->getElementType(), 3811 MTy.getVectorNumElements()); 3812 auto *SubCondTy = FixedVectorType::get(CondTy->getElementType(), 3813 MTy.getVectorNumElements()); 3814 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3815 MinMaxCost *= LT.first - 1; 3816 NumVecElts = MTy.getVectorNumElements(); 3817 } 3818 3819 if (ST->hasBWI()) 3820 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 3821 return MinMaxCost + Entry->Cost; 3822 3823 if (ST->hasAVX()) 3824 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3825 return MinMaxCost + Entry->Cost; 3826 3827 if (ST->hasSSE41()) 3828 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3829 return MinMaxCost + Entry->Cost; 3830 3831 if (ST->hasSSE2()) 3832 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3833 return MinMaxCost + Entry->Cost; 3834 3835 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 3836 3837 // Special case power of 2 reductions where the scalar type isn't changed 3838 // by type legalization. 3839 if (!isPowerOf2_32(ValVTy->getNumElements()) || 3840 ScalarSize != MTy.getScalarSizeInBits()) 3841 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned, 3842 CostKind); 3843 3844 // Now handle reduction with the legal type, taking into account size changes 3845 // at each level. 3846 while (NumVecElts > 1) { 3847 // Determine the size of the remaining vector we need to reduce. 3848 unsigned Size = NumVecElts * ScalarSize; 3849 NumVecElts /= 2; 3850 // If we're reducing from 256/512 bits, use an extract_subvector. 3851 if (Size > 128) { 3852 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 3853 MinMaxCost += 3854 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 3855 Ty = SubTy; 3856 } else if (Size == 128) { 3857 // Reducing from 128 bits is a permute of v2f64/v2i64. 3858 VectorType *ShufTy; 3859 if (ValTy->isFloatingPointTy()) 3860 ShufTy = 3861 FixedVectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 3862 else 3863 ShufTy = FixedVectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 3864 MinMaxCost += 3865 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3866 } else if (Size == 64) { 3867 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 3868 FixedVectorType *ShufTy; 3869 if (ValTy->isFloatingPointTy()) 3870 ShufTy = FixedVectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 3871 else 3872 ShufTy = FixedVectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 3873 MinMaxCost += 3874 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 3875 } else { 3876 // Reducing from smaller size is a shift by immediate. 3877 auto *ShiftTy = FixedVectorType::get( 3878 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 3879 MinMaxCost += getArithmeticInstrCost( 3880 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, 3881 TargetTransformInfo::OK_AnyValue, 3882 TargetTransformInfo::OK_UniformConstantValue, 3883 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 3884 } 3885 3886 // Add the arithmetic op for this level. 3887 auto *SubCondTy = 3888 FixedVectorType::get(CondTy->getElementType(), Ty->getNumElements()); 3889 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 3890 } 3891 3892 // Add the final extract element to the cost. 3893 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 3894 } 3895 3896 /// Calculate the cost of materializing a 64-bit value. This helper 3897 /// method might only calculate a fraction of a larger immediate. Therefore it 3898 /// is valid to return a cost of ZERO. 3899 int X86TTIImpl::getIntImmCost(int64_t Val) { 3900 if (Val == 0) 3901 return TTI::TCC_Free; 3902 3903 if (isInt<32>(Val)) 3904 return TTI::TCC_Basic; 3905 3906 return 2 * TTI::TCC_Basic; 3907 } 3908 3909 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 3910 TTI::TargetCostKind CostKind) { 3911 assert(Ty->isIntegerTy()); 3912 3913 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3914 if (BitSize == 0) 3915 return ~0U; 3916 3917 // Never hoist constants larger than 128bit, because this might lead to 3918 // incorrect code generation or assertions in codegen. 3919 // Fixme: Create a cost model for types larger than i128 once the codegen 3920 // issues have been fixed. 3921 if (BitSize > 128) 3922 return TTI::TCC_Free; 3923 3924 if (Imm == 0) 3925 return TTI::TCC_Free; 3926 3927 // Sign-extend all constants to a multiple of 64-bit. 3928 APInt ImmVal = Imm; 3929 if (BitSize % 64 != 0) 3930 ImmVal = Imm.sext(alignTo(BitSize, 64)); 3931 3932 // Split the constant into 64-bit chunks and calculate the cost for each 3933 // chunk. 3934 int Cost = 0; 3935 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 3936 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 3937 int64_t Val = Tmp.getSExtValue(); 3938 Cost += getIntImmCost(Val); 3939 } 3940 // We need at least one instruction to materialize the constant. 3941 return std::max(1, Cost); 3942 } 3943 3944 int X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, 3945 const APInt &Imm, Type *Ty, 3946 TTI::TargetCostKind CostKind, 3947 Instruction *Inst) { 3948 assert(Ty->isIntegerTy()); 3949 3950 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3951 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3952 // here, so that constant hoisting will ignore this constant. 3953 if (BitSize == 0) 3954 return TTI::TCC_Free; 3955 3956 unsigned ImmIdx = ~0U; 3957 switch (Opcode) { 3958 default: 3959 return TTI::TCC_Free; 3960 case Instruction::GetElementPtr: 3961 // Always hoist the base address of a GetElementPtr. This prevents the 3962 // creation of new constants for every base constant that gets constant 3963 // folded with the offset. 3964 if (Idx == 0) 3965 return 2 * TTI::TCC_Basic; 3966 return TTI::TCC_Free; 3967 case Instruction::Store: 3968 ImmIdx = 0; 3969 break; 3970 case Instruction::ICmp: 3971 // This is an imperfect hack to prevent constant hoisting of 3972 // compares that might be trying to check if a 64-bit value fits in 3973 // 32-bits. The backend can optimize these cases using a right shift by 32. 3974 // Ideally we would check the compare predicate here. There also other 3975 // similar immediates the backend can use shifts for. 3976 if (Idx == 1 && Imm.getBitWidth() == 64) { 3977 uint64_t ImmVal = Imm.getZExtValue(); 3978 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 3979 return TTI::TCC_Free; 3980 } 3981 ImmIdx = 1; 3982 break; 3983 case Instruction::And: 3984 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 3985 // by using a 32-bit operation with implicit zero extension. Detect such 3986 // immediates here as the normal path expects bit 31 to be sign extended. 3987 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 3988 return TTI::TCC_Free; 3989 ImmIdx = 1; 3990 break; 3991 case Instruction::Add: 3992 case Instruction::Sub: 3993 // For add/sub, we can use the opposite instruction for INT32_MIN. 3994 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 3995 return TTI::TCC_Free; 3996 ImmIdx = 1; 3997 break; 3998 case Instruction::UDiv: 3999 case Instruction::SDiv: 4000 case Instruction::URem: 4001 case Instruction::SRem: 4002 // Division by constant is typically expanded later into a different 4003 // instruction sequence. This completely changes the constants. 4004 // Report them as "free" to stop ConstantHoist from marking them as opaque. 4005 return TTI::TCC_Free; 4006 case Instruction::Mul: 4007 case Instruction::Or: 4008 case Instruction::Xor: 4009 ImmIdx = 1; 4010 break; 4011 // Always return TCC_Free for the shift value of a shift instruction. 4012 case Instruction::Shl: 4013 case Instruction::LShr: 4014 case Instruction::AShr: 4015 if (Idx == 1) 4016 return TTI::TCC_Free; 4017 break; 4018 case Instruction::Trunc: 4019 case Instruction::ZExt: 4020 case Instruction::SExt: 4021 case Instruction::IntToPtr: 4022 case Instruction::PtrToInt: 4023 case Instruction::BitCast: 4024 case Instruction::PHI: 4025 case Instruction::Call: 4026 case Instruction::Select: 4027 case Instruction::Ret: 4028 case Instruction::Load: 4029 break; 4030 } 4031 4032 if (Idx == ImmIdx) { 4033 int NumConstants = divideCeil(BitSize, 64); 4034 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4035 return (Cost <= NumConstants * TTI::TCC_Basic) 4036 ? static_cast<int>(TTI::TCC_Free) 4037 : Cost; 4038 } 4039 4040 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4041 } 4042 4043 int X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 4044 const APInt &Imm, Type *Ty, 4045 TTI::TargetCostKind CostKind) { 4046 assert(Ty->isIntegerTy()); 4047 4048 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4049 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4050 // here, so that constant hoisting will ignore this constant. 4051 if (BitSize == 0) 4052 return TTI::TCC_Free; 4053 4054 switch (IID) { 4055 default: 4056 return TTI::TCC_Free; 4057 case Intrinsic::sadd_with_overflow: 4058 case Intrinsic::uadd_with_overflow: 4059 case Intrinsic::ssub_with_overflow: 4060 case Intrinsic::usub_with_overflow: 4061 case Intrinsic::smul_with_overflow: 4062 case Intrinsic::umul_with_overflow: 4063 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 4064 return TTI::TCC_Free; 4065 break; 4066 case Intrinsic::experimental_stackmap: 4067 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4068 return TTI::TCC_Free; 4069 break; 4070 case Intrinsic::experimental_patchpoint_void: 4071 case Intrinsic::experimental_patchpoint_i64: 4072 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4073 return TTI::TCC_Free; 4074 break; 4075 } 4076 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4077 } 4078 4079 unsigned X86TTIImpl::getCFInstrCost(unsigned Opcode, 4080 TTI::TargetCostKind CostKind, 4081 const Instruction *I) { 4082 if (CostKind != TTI::TCK_RecipThroughput) 4083 return Opcode == Instruction::PHI ? 0 : 1; 4084 // Branches are assumed to be predicted. 4085 return 0; 4086 } 4087 4088 int X86TTIImpl::getGatherOverhead() const { 4089 // Some CPUs have more overhead for gather. The specified overhead is relative 4090 // to the Load operation. "2" is the number provided by Intel architects. This 4091 // parameter is used for cost estimation of Gather Op and comparison with 4092 // other alternatives. 4093 // TODO: Remove the explicit hasAVX512()?, That would mean we would only 4094 // enable gather with a -march. 4095 if (ST->hasAVX512() || (ST->hasAVX2() && ST->hasFastGather())) 4096 return 2; 4097 4098 return 1024; 4099 } 4100 4101 int X86TTIImpl::getScatterOverhead() const { 4102 if (ST->hasAVX512()) 4103 return 2; 4104 4105 return 1024; 4106 } 4107 4108 // Return an average cost of Gather / Scatter instruction, maybe improved later. 4109 // FIXME: Add TargetCostKind support. 4110 int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, const Value *Ptr, 4111 Align Alignment, unsigned AddressSpace) { 4112 4113 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 4114 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4115 4116 // Try to reduce index size from 64 bit (default for GEP) 4117 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 4118 // operation will use 16 x 64 indices which do not fit in a zmm and needs 4119 // to split. Also check that the base pointer is the same for all lanes, 4120 // and that there's at most one variable index. 4121 auto getIndexSizeInBits = [](const Value *Ptr, const DataLayout &DL) { 4122 unsigned IndexSize = DL.getPointerSizeInBits(); 4123 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 4124 if (IndexSize < 64 || !GEP) 4125 return IndexSize; 4126 4127 unsigned NumOfVarIndices = 0; 4128 const Value *Ptrs = GEP->getPointerOperand(); 4129 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 4130 return IndexSize; 4131 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 4132 if (isa<Constant>(GEP->getOperand(i))) 4133 continue; 4134 Type *IndxTy = GEP->getOperand(i)->getType(); 4135 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 4136 IndxTy = IndexVTy->getElementType(); 4137 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 4138 !isa<SExtInst>(GEP->getOperand(i))) || 4139 ++NumOfVarIndices > 1) 4140 return IndexSize; // 64 4141 } 4142 return (unsigned)32; 4143 }; 4144 4145 // Trying to reduce IndexSize to 32 bits for vector 16. 4146 // By default the IndexSize is equal to pointer size. 4147 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 4148 ? getIndexSizeInBits(Ptr, DL) 4149 : DL.getPointerSizeInBits(); 4150 4151 auto *IndexVTy = FixedVectorType::get( 4152 IntegerType::get(SrcVTy->getContext(), IndexSize), VF); 4153 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy); 4154 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy); 4155 int SplitFactor = std::max(IdxsLT.first, SrcLT.first); 4156 if (SplitFactor > 1) { 4157 // Handle splitting of vector of pointers 4158 auto *SplitSrcTy = 4159 FixedVectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 4160 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 4161 AddressSpace); 4162 } 4163 4164 // The gather / scatter cost is given by Intel architects. It is a rough 4165 // number since we are looking at one instruction in a time. 4166 const int GSOverhead = (Opcode == Instruction::Load) 4167 ? getGatherOverhead() 4168 : getScatterOverhead(); 4169 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4170 MaybeAlign(Alignment), AddressSpace, 4171 TTI::TCK_RecipThroughput); 4172 } 4173 4174 /// Return the cost of full scalarization of gather / scatter operation. 4175 /// 4176 /// Opcode - Load or Store instruction. 4177 /// SrcVTy - The type of the data vector that should be gathered or scattered. 4178 /// VariableMask - The mask is non-constant at compile time. 4179 /// Alignment - Alignment for one element. 4180 /// AddressSpace - pointer[s] address space. 4181 /// 4182 /// FIXME: Add TargetCostKind support. 4183 int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 4184 bool VariableMask, Align Alignment, 4185 unsigned AddressSpace) { 4186 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4187 APInt DemandedElts = APInt::getAllOnesValue(VF); 4188 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4189 4190 int MaskUnpackCost = 0; 4191 if (VariableMask) { 4192 auto *MaskTy = 4193 FixedVectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 4194 MaskUnpackCost = 4195 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 4196 int ScalarCompareCost = getCmpSelInstrCost( 4197 Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), nullptr, 4198 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4199 int BranchCost = getCFInstrCost(Instruction::Br, CostKind); 4200 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 4201 } 4202 4203 // The cost of the scalar loads/stores. 4204 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4205 MaybeAlign(Alignment), AddressSpace, 4206 CostKind); 4207 4208 int InsertExtractCost = 0; 4209 if (Opcode == Instruction::Load) 4210 for (unsigned i = 0; i < VF; ++i) 4211 // Add the cost of inserting each scalar load into the vector 4212 InsertExtractCost += 4213 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 4214 else 4215 for (unsigned i = 0; i < VF; ++i) 4216 // Add the cost of extracting each element out of the data vector 4217 InsertExtractCost += 4218 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 4219 4220 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 4221 } 4222 4223 /// Calculate the cost of Gather / Scatter operation 4224 int X86TTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *SrcVTy, 4225 const Value *Ptr, bool VariableMask, 4226 Align Alignment, 4227 TTI::TargetCostKind CostKind, 4228 const Instruction *I = nullptr) { 4229 if (CostKind != TTI::TCK_RecipThroughput) { 4230 if ((Opcode == Instruction::Load && 4231 isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4232 (Opcode == Instruction::Store && 4233 isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4234 return 1; 4235 return BaseT::getGatherScatterOpCost(Opcode, SrcVTy, Ptr, VariableMask, 4236 Alignment, CostKind, I); 4237 } 4238 4239 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 4240 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4241 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 4242 if (!PtrTy && Ptr->getType()->isVectorTy()) 4243 PtrTy = dyn_cast<PointerType>( 4244 cast<VectorType>(Ptr->getType())->getElementType()); 4245 assert(PtrTy && "Unexpected type for Ptr argument"); 4246 unsigned AddressSpace = PtrTy->getAddressSpace(); 4247 4248 bool Scalarize = false; 4249 if ((Opcode == Instruction::Load && 4250 !isLegalMaskedGather(SrcVTy, Align(Alignment))) || 4251 (Opcode == Instruction::Store && 4252 !isLegalMaskedScatter(SrcVTy, Align(Alignment)))) 4253 Scalarize = true; 4254 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 4255 // Vector-4 of gather/scatter instruction does not exist on KNL. 4256 // We can extend it to 8 elements, but zeroing upper bits of 4257 // the mask vector will add more instructions. Right now we give the scalar 4258 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 4259 // is better in the VariableMask case. 4260 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 4261 Scalarize = true; 4262 4263 if (Scalarize) 4264 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 4265 AddressSpace); 4266 4267 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 4268 } 4269 4270 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 4271 TargetTransformInfo::LSRCost &C2) { 4272 // X86 specific here are "instruction number 1st priority". 4273 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 4274 C1.NumIVMuls, C1.NumBaseAdds, 4275 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 4276 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 4277 C2.NumIVMuls, C2.NumBaseAdds, 4278 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 4279 } 4280 4281 bool X86TTIImpl::canMacroFuseCmp() { 4282 return ST->hasMacroFusion() || ST->hasBranchFusion(); 4283 } 4284 4285 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, Align Alignment) { 4286 if (!ST->hasAVX()) 4287 return false; 4288 4289 // The backend can't handle a single element vector. 4290 if (isa<VectorType>(DataTy) && 4291 cast<FixedVectorType>(DataTy)->getNumElements() == 1) 4292 return false; 4293 Type *ScalarTy = DataTy->getScalarType(); 4294 4295 if (ScalarTy->isPointerTy()) 4296 return true; 4297 4298 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4299 return true; 4300 4301 if (!ScalarTy->isIntegerTy()) 4302 return false; 4303 4304 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4305 return IntWidth == 32 || IntWidth == 64 || 4306 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 4307 } 4308 4309 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, Align Alignment) { 4310 return isLegalMaskedLoad(DataType, Alignment); 4311 } 4312 4313 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 4314 unsigned DataSize = DL.getTypeStoreSize(DataType); 4315 // The only supported nontemporal loads are for aligned vectors of 16 or 32 4316 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 4317 // (the equivalent stores only require AVX). 4318 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 4319 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 4320 4321 return false; 4322 } 4323 4324 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 4325 unsigned DataSize = DL.getTypeStoreSize(DataType); 4326 4327 // SSE4A supports nontemporal stores of float and double at arbitrary 4328 // alignment. 4329 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 4330 return true; 4331 4332 // Besides the SSE4A subtarget exception above, only aligned stores are 4333 // available nontemporaly on any other subtarget. And only stores with a size 4334 // of 4..32 bytes (powers of 2, only) are permitted. 4335 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 4336 !isPowerOf2_32(DataSize)) 4337 return false; 4338 4339 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 4340 // loads require AVX2). 4341 if (DataSize == 32) 4342 return ST->hasAVX(); 4343 else if (DataSize == 16) 4344 return ST->hasSSE1(); 4345 return true; 4346 } 4347 4348 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 4349 if (!isa<VectorType>(DataTy)) 4350 return false; 4351 4352 if (!ST->hasAVX512()) 4353 return false; 4354 4355 // The backend can't handle a single element vector. 4356 if (cast<FixedVectorType>(DataTy)->getNumElements() == 1) 4357 return false; 4358 4359 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 4360 4361 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4362 return true; 4363 4364 if (!ScalarTy->isIntegerTy()) 4365 return false; 4366 4367 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4368 return IntWidth == 32 || IntWidth == 64 || 4369 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 4370 } 4371 4372 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 4373 return isLegalMaskedExpandLoad(DataTy); 4374 } 4375 4376 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, Align Alignment) { 4377 // Some CPUs have better gather performance than others. 4378 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 4379 // enable gather with a -march. 4380 if (!(ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()))) 4381 return false; 4382 4383 // This function is called now in two cases: from the Loop Vectorizer 4384 // and from the Scalarizer. 4385 // When the Loop Vectorizer asks about legality of the feature, 4386 // the vectorization factor is not calculated yet. The Loop Vectorizer 4387 // sends a scalar type and the decision is based on the width of the 4388 // scalar element. 4389 // Later on, the cost model will estimate usage this intrinsic based on 4390 // the vector type. 4391 // The Scalarizer asks again about legality. It sends a vector type. 4392 // In this case we can reject non-power-of-2 vectors. 4393 // We also reject single element vectors as the type legalizer can't 4394 // scalarize it. 4395 if (auto *DataVTy = dyn_cast<FixedVectorType>(DataTy)) { 4396 unsigned NumElts = DataVTy->getNumElements(); 4397 if (NumElts == 1) 4398 return false; 4399 } 4400 Type *ScalarTy = DataTy->getScalarType(); 4401 if (ScalarTy->isPointerTy()) 4402 return true; 4403 4404 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 4405 return true; 4406 4407 if (!ScalarTy->isIntegerTy()) 4408 return false; 4409 4410 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 4411 return IntWidth == 32 || IntWidth == 64; 4412 } 4413 4414 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, Align Alignment) { 4415 // AVX2 doesn't support scatter 4416 if (!ST->hasAVX512()) 4417 return false; 4418 return isLegalMaskedGather(DataType, Alignment); 4419 } 4420 4421 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 4422 EVT VT = TLI->getValueType(DL, DataType); 4423 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 4424 } 4425 4426 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 4427 return false; 4428 } 4429 4430 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 4431 const Function *Callee) const { 4432 const TargetMachine &TM = getTLI()->getTargetMachine(); 4433 4434 // Work this as a subsetting of subtarget features. 4435 const FeatureBitset &CallerBits = 4436 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 4437 const FeatureBitset &CalleeBits = 4438 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 4439 4440 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 4441 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 4442 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 4443 } 4444 4445 bool X86TTIImpl::areFunctionArgsABICompatible( 4446 const Function *Caller, const Function *Callee, 4447 SmallPtrSetImpl<Argument *> &Args) const { 4448 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args)) 4449 return false; 4450 4451 // If we get here, we know the target features match. If one function 4452 // considers 512-bit vectors legal and the other does not, consider them 4453 // incompatible. 4454 const TargetMachine &TM = getTLI()->getTargetMachine(); 4455 4456 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 4457 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs()) 4458 return true; 4459 4460 // Consider the arguments compatible if they aren't vectors or aggregates. 4461 // FIXME: Look at the size of vectors. 4462 // FIXME: Look at the element types of aggregates to see if there are vectors. 4463 // FIXME: The API of this function seems intended to allow arguments 4464 // to be removed from the set, but the caller doesn't check if the set 4465 // becomes empty so that may not work in practice. 4466 return llvm::none_of(Args, [](Argument *A) { 4467 auto *EltTy = cast<PointerType>(A->getType())->getElementType(); 4468 return EltTy->isVectorTy() || EltTy->isAggregateType(); 4469 }); 4470 } 4471 4472 X86TTIImpl::TTI::MemCmpExpansionOptions 4473 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 4474 TTI::MemCmpExpansionOptions Options; 4475 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 4476 Options.NumLoadsPerBlock = 2; 4477 // All GPR and vector loads can be unaligned. 4478 Options.AllowOverlappingLoads = true; 4479 if (IsZeroCmp) { 4480 // Only enable vector loads for equality comparison. Right now the vector 4481 // version is not as fast for three way compare (see #33329). 4482 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 4483 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 4484 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 4485 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 4486 } 4487 if (ST->is64Bit()) { 4488 Options.LoadSizes.push_back(8); 4489 } 4490 Options.LoadSizes.push_back(4); 4491 Options.LoadSizes.push_back(2); 4492 Options.LoadSizes.push_back(1); 4493 return Options; 4494 } 4495 4496 bool X86TTIImpl::enableInterleavedAccessVectorization() { 4497 // TODO: We expect this to be beneficial regardless of arch, 4498 // but there are currently some unexplained performance artifacts on Atom. 4499 // As a temporary solution, disable on Atom. 4500 return !(ST->isAtom()); 4501 } 4502 4503 // Get estimation for interleaved load/store operations for AVX2. 4504 // \p Factor is the interleaved-access factor (stride) - number of 4505 // (interleaved) elements in the group. 4506 // \p Indices contains the indices for a strided load: when the 4507 // interleaved load has gaps they indicate which elements are used. 4508 // If Indices is empty (or if the number of indices is equal to the size 4509 // of the interleaved-access as given in \p Factor) the access has no gaps. 4510 // 4511 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 4512 // computing the cost using a generic formula as a function of generic 4513 // shuffles. We therefore use a lookup table instead, filled according to 4514 // the instruction sequences that codegen currently generates. 4515 int X86TTIImpl::getInterleavedMemoryOpCostAVX2( 4516 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 4517 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 4518 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 4519 4520 if (UseMaskForCond || UseMaskForGaps) 4521 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4522 Alignment, AddressSpace, CostKind, 4523 UseMaskForCond, UseMaskForGaps); 4524 4525 // We currently Support only fully-interleaved groups, with no gaps. 4526 // TODO: Support also strided loads (interleaved-groups with gaps). 4527 if (Indices.size() && Indices.size() != Factor) 4528 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4529 Alignment, AddressSpace, 4530 CostKind); 4531 4532 // VecTy for interleave memop is <VF*Factor x Elt>. 4533 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4534 // VecTy = <12 x i32>. 4535 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4536 4537 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 4538 // the VF=2, while v2i128 is an unsupported MVT vector type 4539 // (see MachineValueType.h::getVectorVT()). 4540 if (!LegalVT.isVector()) 4541 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4542 Alignment, AddressSpace, 4543 CostKind); 4544 4545 unsigned VF = VecTy->getNumElements() / Factor; 4546 Type *ScalarTy = VecTy->getElementType(); 4547 4548 // Calculate the number of memory operations (NumOfMemOps), required 4549 // for load/store the VecTy. 4550 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4551 unsigned LegalVTSize = LegalVT.getStoreSize(); 4552 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4553 4554 // Get the cost of one memory operation. 4555 auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(), 4556 LegalVT.getVectorNumElements()); 4557 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 4558 MaybeAlign(Alignment), AddressSpace, 4559 CostKind); 4560 4561 auto *VT = FixedVectorType::get(ScalarTy, VF); 4562 EVT ETy = TLI->getValueType(DL, VT); 4563 if (!ETy.isSimple()) 4564 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4565 Alignment, AddressSpace, 4566 CostKind); 4567 4568 // TODO: Complete for other data-types and strides. 4569 // Each combination of Stride, ElementTy and VF results in a different 4570 // sequence; The cost tables are therefore accessed with: 4571 // Factor (stride) and VectorType=VFxElemType. 4572 // The Cost accounts only for the shuffle sequence; 4573 // The cost of the loads/stores is accounted for separately. 4574 // 4575 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 4576 { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64 4577 { 2, MVT::v4f64, 6 }, //(load 8f64 and) deinterleave into 2 x 4f64 4578 4579 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8 4580 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8 4581 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8 4582 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8 4583 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8 4584 { 3, MVT::v8f32, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32 4585 4586 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8 4587 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8 4588 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8 4589 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8 4590 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8 4591 4592 { 8, MVT::v8f32, 40 } //(load 64f32 and)deinterleave into 8 x 8f32 4593 }; 4594 4595 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 4596 { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store) 4597 { 2, MVT::v4f64, 6 }, //interleave into 2 x 4f64 into 8f64 (and store) 4598 4599 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store) 4600 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store) 4601 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store) 4602 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store) 4603 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store) 4604 4605 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store) 4606 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store) 4607 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store) 4608 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store) 4609 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store) 4610 }; 4611 4612 if (Opcode == Instruction::Load) { 4613 if (const auto *Entry = 4614 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 4615 return NumOfMemOps * MemOpCost + Entry->Cost; 4616 } else { 4617 assert(Opcode == Instruction::Store && 4618 "Expected Store Instruction at this point"); 4619 if (const auto *Entry = 4620 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 4621 return NumOfMemOps * MemOpCost + Entry->Cost; 4622 } 4623 4624 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4625 Alignment, AddressSpace, CostKind); 4626 } 4627 4628 // Get estimation for interleaved load/store operations and strided load. 4629 // \p Indices contains indices for strided load. 4630 // \p Factor - the factor of interleaving. 4631 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 4632 int X86TTIImpl::getInterleavedMemoryOpCostAVX512( 4633 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 4634 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 4635 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 4636 4637 if (UseMaskForCond || UseMaskForGaps) 4638 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4639 Alignment, AddressSpace, CostKind, 4640 UseMaskForCond, UseMaskForGaps); 4641 4642 // VecTy for interleave memop is <VF*Factor x Elt>. 4643 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 4644 // VecTy = <12 x i32>. 4645 4646 // Calculate the number of memory operations (NumOfMemOps), required 4647 // for load/store the VecTy. 4648 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 4649 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 4650 unsigned LegalVTSize = LegalVT.getStoreSize(); 4651 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 4652 4653 // Get the cost of one memory operation. 4654 auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(), 4655 LegalVT.getVectorNumElements()); 4656 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 4657 MaybeAlign(Alignment), AddressSpace, 4658 CostKind); 4659 4660 unsigned VF = VecTy->getNumElements() / Factor; 4661 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 4662 4663 if (Opcode == Instruction::Load) { 4664 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 4665 // contain the cost of the optimized shuffle sequence that the 4666 // X86InterleavedAccess pass will generate. 4667 // The cost of loads and stores are computed separately from the table. 4668 4669 // X86InterleavedAccess support only the following interleaved-access group. 4670 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 4671 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 4672 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 4673 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 4674 }; 4675 4676 if (const auto *Entry = 4677 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 4678 return NumOfMemOps * MemOpCost + Entry->Cost; 4679 //If an entry does not exist, fallback to the default implementation. 4680 4681 // Kind of shuffle depends on number of loaded values. 4682 // If we load the entire data in one register, we can use a 1-src shuffle. 4683 // Otherwise, we'll merge 2 sources in each operation. 4684 TTI::ShuffleKind ShuffleKind = 4685 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 4686 4687 unsigned ShuffleCost = 4688 getShuffleCost(ShuffleKind, SingleMemOpTy, None, 0, nullptr); 4689 4690 unsigned NumOfLoadsInInterleaveGrp = 4691 Indices.size() ? Indices.size() : Factor; 4692 auto *ResultTy = FixedVectorType::get(VecTy->getElementType(), 4693 VecTy->getNumElements() / Factor); 4694 unsigned NumOfResults = 4695 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 4696 NumOfLoadsInInterleaveGrp; 4697 4698 // About a half of the loads may be folded in shuffles when we have only 4699 // one result. If we have more than one result, we do not fold loads at all. 4700 unsigned NumOfUnfoldedLoads = 4701 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 4702 4703 // Get a number of shuffle operations per result. 4704 unsigned NumOfShufflesPerResult = 4705 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 4706 4707 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4708 // When we have more than one destination, we need additional instructions 4709 // to keep sources. 4710 unsigned NumOfMoves = 0; 4711 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 4712 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 4713 4714 int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 4715 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 4716 4717 return Cost; 4718 } 4719 4720 // Store. 4721 assert(Opcode == Instruction::Store && 4722 "Expected Store Instruction at this point"); 4723 // X86InterleavedAccess support only the following interleaved-access group. 4724 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 4725 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 4726 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 4727 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 4728 4729 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 4730 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 4731 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 4732 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 4733 }; 4734 4735 if (const auto *Entry = 4736 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 4737 return NumOfMemOps * MemOpCost + Entry->Cost; 4738 //If an entry does not exist, fallback to the default implementation. 4739 4740 // There is no strided stores meanwhile. And store can't be folded in 4741 // shuffle. 4742 unsigned NumOfSources = Factor; // The number of values to be merged. 4743 unsigned ShuffleCost = 4744 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, None, 0, nullptr); 4745 unsigned NumOfShufflesPerStore = NumOfSources - 1; 4746 4747 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 4748 // We need additional instructions to keep sources. 4749 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 4750 int Cost = NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 4751 NumOfMoves; 4752 return Cost; 4753 } 4754 4755 int X86TTIImpl::getInterleavedMemoryOpCost( 4756 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, 4757 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, 4758 bool UseMaskForCond, bool UseMaskForGaps) { 4759 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 4760 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 4761 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 4762 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 4763 return true; 4764 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 4765 return HasBW; 4766 return false; 4767 }; 4768 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 4769 return getInterleavedMemoryOpCostAVX512( 4770 Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment, 4771 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 4772 if (ST->hasAVX2()) 4773 return getInterleavedMemoryOpCostAVX2( 4774 Opcode, cast<FixedVectorType>(VecTy), Factor, Indices, Alignment, 4775 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 4776 4777 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 4778 Alignment, AddressSpace, CostKind, 4779 UseMaskForCond, UseMaskForGaps); 4780 } 4781