1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // X86 cost model. 56 // 57 //===----------------------------------------------------------------------===// 58 59 TargetTransformInfo::PopcntSupportKind 60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 61 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 62 // TODO: Currently the __builtin_popcount() implementation using SSE3 63 // instructions is inefficient. Once the problem is fixed, we should 64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 66 } 67 68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 69 TargetTransformInfo::CacheLevel Level) const { 70 switch (Level) { 71 case TargetTransformInfo::CacheLevel::L1D: 72 // - Penryn 73 // - Nehalem 74 // - Westmere 75 // - Sandy Bridge 76 // - Ivy Bridge 77 // - Haswell 78 // - Broadwell 79 // - Skylake 80 // - Kabylake 81 return 32 * 1024; // 32 KByte 82 case TargetTransformInfo::CacheLevel::L2D: 83 // - Penryn 84 // - Nehalem 85 // - Westmere 86 // - Sandy Bridge 87 // - Ivy Bridge 88 // - Haswell 89 // - Broadwell 90 // - Skylake 91 // - Kabylake 92 return 256 * 1024; // 256 KByte 93 } 94 95 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 96 } 97 98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 99 TargetTransformInfo::CacheLevel Level) const { 100 // - Penryn 101 // - Nehalem 102 // - Westmere 103 // - Sandy Bridge 104 // - Ivy Bridge 105 // - Haswell 106 // - Broadwell 107 // - Skylake 108 // - Kabylake 109 switch (Level) { 110 case TargetTransformInfo::CacheLevel::L1D: 111 LLVM_FALLTHROUGH; 112 case TargetTransformInfo::CacheLevel::L2D: 113 return 8; 114 } 115 116 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 117 } 118 119 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 120 bool Vector = (ClassID == 1); 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const { 133 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 134 if (Vector) { 135 if (ST->hasAVX512() && PreferVectorWidth >= 512) 136 return 512; 137 if (ST->hasAVX() && PreferVectorWidth >= 256) 138 return 256; 139 if (ST->hasSSE1() && PreferVectorWidth >= 128) 140 return 128; 141 return 0; 142 } 143 144 if (ST->is64Bit()) 145 return 64; 146 147 return 32; 148 } 149 150 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 151 return getRegisterBitWidth(true); 152 } 153 154 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 155 // If the loop will not be vectorized, don't interleave the loop. 156 // Let regular unroll to unroll the loop, which saves the overflow 157 // check and memory check cost. 158 if (VF == 1) 159 return 1; 160 161 if (ST->isAtom()) 162 return 1; 163 164 // Sandybridge and Haswell have multiple execution ports and pipelined 165 // vector units. 166 if (ST->hasAVX()) 167 return 4; 168 169 return 2; 170 } 171 172 int X86TTIImpl::getArithmeticInstrCost(unsigned Opcode, Type *Ty, 173 TTI::OperandValueKind Op1Info, 174 TTI::OperandValueKind Op2Info, 175 TTI::OperandValueProperties Opd1PropInfo, 176 TTI::OperandValueProperties Opd2PropInfo, 177 ArrayRef<const Value *> Args, 178 const Instruction *CxtI) { 179 // Legalize the type. 180 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 181 182 int ISD = TLI->InstructionOpcodeToISD(Opcode); 183 assert(ISD && "Invalid opcode"); 184 185 static const CostTblEntry GLMCostTable[] = { 186 { ISD::FDIV, MVT::f32, 18 }, // divss 187 { ISD::FDIV, MVT::v4f32, 35 }, // divps 188 { ISD::FDIV, MVT::f64, 33 }, // divsd 189 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 190 }; 191 192 if (ST->useGLMDivSqrtCosts()) 193 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 194 LT.second)) 195 return LT.first * Entry->Cost; 196 197 static const CostTblEntry SLMCostTable[] = { 198 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 199 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 200 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. 201 { ISD::FMUL, MVT::f64, 2 }, // mulsd 202 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 203 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 204 { ISD::FDIV, MVT::f32, 17 }, // divss 205 { ISD::FDIV, MVT::v4f32, 39 }, // divps 206 { ISD::FDIV, MVT::f64, 32 }, // divsd 207 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 208 { ISD::FADD, MVT::v2f64, 2 }, // addpd 209 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 210 // v2i64/v4i64 mul is custom lowered as a series of long: 211 // multiplies(3), shifts(3) and adds(2) 212 // slm muldq version throughput is 2 and addq throughput 4 213 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 214 // 3X4 (addq throughput) = 17 215 { ISD::MUL, MVT::v2i64, 17 }, 216 // slm addq\subq throughput is 4 217 { ISD::ADD, MVT::v2i64, 4 }, 218 { ISD::SUB, MVT::v2i64, 4 }, 219 }; 220 221 if (ST->isSLM()) { 222 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 223 // Check if the operands can be shrinked into a smaller datatype. 224 bool Op1Signed = false; 225 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 226 bool Op2Signed = false; 227 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 228 229 bool signedMode = Op1Signed | Op2Signed; 230 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 231 232 if (OpMinSize <= 7) 233 return LT.first * 3; // pmullw/sext 234 if (!signedMode && OpMinSize <= 8) 235 return LT.first * 3; // pmullw/zext 236 if (OpMinSize <= 15) 237 return LT.first * 5; // pmullw/pmulhw/pshuf 238 if (!signedMode && OpMinSize <= 16) 239 return LT.first * 5; // pmullw/pmulhw/pshuf 240 } 241 242 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 243 LT.second)) { 244 return LT.first * Entry->Cost; 245 } 246 } 247 248 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 249 ISD == ISD::UREM) && 250 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 251 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 252 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 253 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 254 // On X86, vector signed division by constants power-of-two are 255 // normally expanded to the sequence SRA + SRL + ADD + SRA. 256 // The OperandValue properties may not be the same as that of the previous 257 // operation; conservatively assume OP_None. 258 int Cost = 259 2 * getArithmeticInstrCost(Instruction::AShr, Ty, Op1Info, Op2Info, 260 TargetTransformInfo::OP_None, 261 TargetTransformInfo::OP_None); 262 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 263 TargetTransformInfo::OP_None, 264 TargetTransformInfo::OP_None); 265 Cost += getArithmeticInstrCost(Instruction::Add, Ty, Op1Info, Op2Info, 266 TargetTransformInfo::OP_None, 267 TargetTransformInfo::OP_None); 268 269 if (ISD == ISD::SREM) { 270 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 271 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info); 272 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, Op1Info, Op2Info); 273 } 274 275 return Cost; 276 } 277 278 // Vector unsigned division/remainder will be simplified to shifts/masks. 279 if (ISD == ISD::UDIV) 280 return getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 281 TargetTransformInfo::OP_None, 282 TargetTransformInfo::OP_None); 283 284 else // UREM 285 return getArithmeticInstrCost(Instruction::And, Ty, Op1Info, Op2Info, 286 TargetTransformInfo::OP_None, 287 TargetTransformInfo::OP_None); 288 } 289 290 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 291 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 292 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 293 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 294 }; 295 296 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 297 ST->hasBWI()) { 298 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 299 LT.second)) 300 return LT.first * Entry->Cost; 301 } 302 303 static const CostTblEntry AVX512UniformConstCostTable[] = { 304 { ISD::SRA, MVT::v2i64, 1 }, 305 { ISD::SRA, MVT::v4i64, 1 }, 306 { ISD::SRA, MVT::v8i64, 1 }, 307 }; 308 309 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 310 ST->hasAVX512()) { 311 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 312 LT.second)) 313 return LT.first * Entry->Cost; 314 } 315 316 static const CostTblEntry AVX2UniformConstCostTable[] = { 317 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 318 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 319 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 320 321 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 322 }; 323 324 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 325 ST->hasAVX2()) { 326 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 327 LT.second)) 328 return LT.first * Entry->Cost; 329 } 330 331 static const CostTblEntry SSE2UniformConstCostTable[] = { 332 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 333 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 334 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 335 336 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 337 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 338 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 339 }; 340 341 // XOP has faster vXi8 shifts. 342 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 343 ST->hasSSE2() && !ST->hasXOP()) { 344 if (const auto *Entry = 345 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 346 return LT.first * Entry->Cost; 347 } 348 349 static const CostTblEntry AVX512BWConstCostTable[] = { 350 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 351 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 352 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 353 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 354 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 355 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 356 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 357 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 358 }; 359 360 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 361 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 362 ST->hasBWI()) { 363 if (const auto *Entry = 364 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 365 return LT.first * Entry->Cost; 366 } 367 368 static const CostTblEntry AVX512ConstCostTable[] = { 369 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 370 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 371 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 372 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 373 }; 374 375 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 376 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 377 ST->hasAVX512()) { 378 if (const auto *Entry = 379 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 380 return LT.first * Entry->Cost; 381 } 382 383 static const CostTblEntry AVX2ConstCostTable[] = { 384 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 385 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 386 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 387 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 388 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 389 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 390 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 391 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 392 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 393 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 394 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 395 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 396 }; 397 398 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 399 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 400 ST->hasAVX2()) { 401 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 402 return LT.first * Entry->Cost; 403 } 404 405 static const CostTblEntry SSE2ConstCostTable[] = { 406 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 407 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 408 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 409 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 410 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 411 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 412 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 413 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 414 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 415 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 416 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 417 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 418 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 419 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 420 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 421 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 422 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 423 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 424 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 425 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 426 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 427 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 428 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 429 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 430 }; 431 432 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 433 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 434 ST->hasSSE2()) { 435 // pmuldq sequence. 436 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 437 return LT.first * 32; 438 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 439 return LT.first * 38; 440 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 441 return LT.first * 15; 442 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 443 return LT.first * 20; 444 445 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 446 return LT.first * Entry->Cost; 447 } 448 449 static const CostTblEntry AVX2UniformCostTable[] = { 450 // Uniform splats are cheaper for the following instructions. 451 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 452 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 453 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 454 }; 455 456 if (ST->hasAVX2() && 457 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 458 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 459 if (const auto *Entry = 460 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 461 return LT.first * Entry->Cost; 462 } 463 464 static const CostTblEntry SSE2UniformCostTable[] = { 465 // Uniform splats are cheaper for the following instructions. 466 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 467 { ISD::SHL, MVT::v4i32, 1 }, // pslld 468 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 469 470 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 471 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 472 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 473 474 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 475 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 476 }; 477 478 if (ST->hasSSE2() && 479 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 480 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 481 if (const auto *Entry = 482 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 483 return LT.first * Entry->Cost; 484 } 485 486 static const CostTblEntry AVX512DQCostTable[] = { 487 { ISD::MUL, MVT::v2i64, 1 }, 488 { ISD::MUL, MVT::v4i64, 1 }, 489 { ISD::MUL, MVT::v8i64, 1 } 490 }; 491 492 // Look for AVX512DQ lowering tricks for custom cases. 493 if (ST->hasDQI()) 494 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 495 return LT.first * Entry->Cost; 496 497 static const CostTblEntry AVX512BWCostTable[] = { 498 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 499 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 500 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 501 502 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 503 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 504 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 505 506 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 507 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 508 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 509 510 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 511 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 512 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 513 514 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence. 515 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence. 516 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence. 517 }; 518 519 // Look for AVX512BW lowering tricks for custom cases. 520 if (ST->hasBWI()) 521 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 522 return LT.first * Entry->Cost; 523 524 static const CostTblEntry AVX512CostTable[] = { 525 { ISD::SHL, MVT::v16i32, 1 }, 526 { ISD::SRL, MVT::v16i32, 1 }, 527 { ISD::SRA, MVT::v16i32, 1 }, 528 529 { ISD::SHL, MVT::v8i64, 1 }, 530 { ISD::SRL, MVT::v8i64, 1 }, 531 532 { ISD::SRA, MVT::v2i64, 1 }, 533 { ISD::SRA, MVT::v4i64, 1 }, 534 { ISD::SRA, MVT::v8i64, 1 }, 535 536 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence. 537 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence. 538 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 539 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 540 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 541 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add 542 543 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 544 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 545 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 546 547 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 548 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 549 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 550 }; 551 552 if (ST->hasAVX512()) 553 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 554 return LT.first * Entry->Cost; 555 556 static const CostTblEntry AVX2ShiftCostTable[] = { 557 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 558 // customize them to detect the cases where shift amount is a scalar one. 559 { ISD::SHL, MVT::v4i32, 1 }, 560 { ISD::SRL, MVT::v4i32, 1 }, 561 { ISD::SRA, MVT::v4i32, 1 }, 562 { ISD::SHL, MVT::v8i32, 1 }, 563 { ISD::SRL, MVT::v8i32, 1 }, 564 { ISD::SRA, MVT::v8i32, 1 }, 565 { ISD::SHL, MVT::v2i64, 1 }, 566 { ISD::SRL, MVT::v2i64, 1 }, 567 { ISD::SHL, MVT::v4i64, 1 }, 568 { ISD::SRL, MVT::v4i64, 1 }, 569 }; 570 571 // Look for AVX2 lowering tricks. 572 if (ST->hasAVX2()) { 573 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 574 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 575 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 576 // On AVX2, a packed v16i16 shift left by a constant build_vector 577 // is lowered into a vector multiply (vpmullw). 578 return getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info, 579 TargetTransformInfo::OP_None, 580 TargetTransformInfo::OP_None); 581 582 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 583 return LT.first * Entry->Cost; 584 } 585 586 static const CostTblEntry XOPShiftCostTable[] = { 587 // 128bit shifts take 1cy, but right shifts require negation beforehand. 588 { ISD::SHL, MVT::v16i8, 1 }, 589 { ISD::SRL, MVT::v16i8, 2 }, 590 { ISD::SRA, MVT::v16i8, 2 }, 591 { ISD::SHL, MVT::v8i16, 1 }, 592 { ISD::SRL, MVT::v8i16, 2 }, 593 { ISD::SRA, MVT::v8i16, 2 }, 594 { ISD::SHL, MVT::v4i32, 1 }, 595 { ISD::SRL, MVT::v4i32, 2 }, 596 { ISD::SRA, MVT::v4i32, 2 }, 597 { ISD::SHL, MVT::v2i64, 1 }, 598 { ISD::SRL, MVT::v2i64, 2 }, 599 { ISD::SRA, MVT::v2i64, 2 }, 600 // 256bit shifts require splitting if AVX2 didn't catch them above. 601 { ISD::SHL, MVT::v32i8, 2+2 }, 602 { ISD::SRL, MVT::v32i8, 4+2 }, 603 { ISD::SRA, MVT::v32i8, 4+2 }, 604 { ISD::SHL, MVT::v16i16, 2+2 }, 605 { ISD::SRL, MVT::v16i16, 4+2 }, 606 { ISD::SRA, MVT::v16i16, 4+2 }, 607 { ISD::SHL, MVT::v8i32, 2+2 }, 608 { ISD::SRL, MVT::v8i32, 4+2 }, 609 { ISD::SRA, MVT::v8i32, 4+2 }, 610 { ISD::SHL, MVT::v4i64, 2+2 }, 611 { ISD::SRL, MVT::v4i64, 4+2 }, 612 { ISD::SRA, MVT::v4i64, 4+2 }, 613 }; 614 615 // Look for XOP lowering tricks. 616 if (ST->hasXOP()) { 617 // If the right shift is constant then we'll fold the negation so 618 // it's as cheap as a left shift. 619 int ShiftISD = ISD; 620 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 621 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 622 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 623 ShiftISD = ISD::SHL; 624 if (const auto *Entry = 625 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 626 return LT.first * Entry->Cost; 627 } 628 629 static const CostTblEntry SSE2UniformShiftCostTable[] = { 630 // Uniform splats are cheaper for the following instructions. 631 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 632 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 633 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 634 635 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 636 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 637 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 638 639 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 640 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 641 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 642 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 643 }; 644 645 if (ST->hasSSE2() && 646 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 647 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 648 649 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 650 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 651 return LT.first * 4; // 2*psrad + shuffle. 652 653 if (const auto *Entry = 654 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 655 return LT.first * Entry->Cost; 656 } 657 658 if (ISD == ISD::SHL && 659 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 660 MVT VT = LT.second; 661 // Vector shift left by non uniform constant can be lowered 662 // into vector multiply. 663 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 664 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 665 ISD = ISD::MUL; 666 } 667 668 static const CostTblEntry AVX2CostTable[] = { 669 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. 670 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 671 672 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. 673 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 674 675 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. 676 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. 677 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. 678 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 679 680 { ISD::SUB, MVT::v32i8, 1 }, // psubb 681 { ISD::ADD, MVT::v32i8, 1 }, // paddb 682 { ISD::SUB, MVT::v16i16, 1 }, // psubw 683 { ISD::ADD, MVT::v16i16, 1 }, // paddw 684 { ISD::SUB, MVT::v8i32, 1 }, // psubd 685 { ISD::ADD, MVT::v8i32, 1 }, // paddd 686 { ISD::SUB, MVT::v4i64, 1 }, // psubq 687 { ISD::ADD, MVT::v4i64, 1 }, // paddq 688 689 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence. 690 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence. 691 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 692 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 693 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add 694 695 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 696 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 697 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 698 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 699 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 700 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 701 702 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 703 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 704 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 705 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 706 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 707 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 708 }; 709 710 // Look for AVX2 lowering tricks for custom cases. 711 if (ST->hasAVX2()) 712 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 713 return LT.first * Entry->Cost; 714 715 static const CostTblEntry AVX1CostTable[] = { 716 // We don't have to scalarize unsupported ops. We can issue two half-sized 717 // operations and we only need to extract the upper YMM half. 718 // Two ops + 1 extract + 1 insert = 4. 719 { ISD::MUL, MVT::v16i16, 4 }, 720 { ISD::MUL, MVT::v8i32, 4 }, 721 { ISD::SUB, MVT::v32i8, 4 }, 722 { ISD::ADD, MVT::v32i8, 4 }, 723 { ISD::SUB, MVT::v16i16, 4 }, 724 { ISD::ADD, MVT::v16i16, 4 }, 725 { ISD::SUB, MVT::v8i32, 4 }, 726 { ISD::ADD, MVT::v8i32, 4 }, 727 { ISD::SUB, MVT::v4i64, 4 }, 728 { ISD::ADD, MVT::v4i64, 4 }, 729 730 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 731 // are lowered as a series of long multiplies(3), shifts(3) and adds(2) 732 // Because we believe v4i64 to be a legal type, we must also include the 733 // extract+insert in the cost table. Therefore, the cost here is 18 734 // instead of 8. 735 { ISD::MUL, MVT::v4i64, 18 }, 736 737 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence. 738 739 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 740 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 741 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 742 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 743 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 744 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 745 }; 746 747 if (ST->hasAVX()) 748 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 749 return LT.first * Entry->Cost; 750 751 static const CostTblEntry SSE42CostTable[] = { 752 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 753 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 754 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 755 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 756 757 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 758 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 759 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 760 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 761 762 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 763 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 764 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 765 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 766 767 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 768 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 769 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 770 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 771 }; 772 773 if (ST->hasSSE42()) 774 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 775 return LT.first * Entry->Cost; 776 777 static const CostTblEntry SSE41CostTable[] = { 778 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 779 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split. 780 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 781 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 782 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 783 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split 784 785 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 786 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split. 787 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 788 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 789 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 790 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split. 791 792 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 793 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split. 794 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 795 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 796 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 797 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split. 798 799 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 800 }; 801 802 if (ST->hasSSE41()) 803 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 804 return LT.first * Entry->Cost; 805 806 static const CostTblEntry SSE2CostTable[] = { 807 // We don't correctly identify costs of casts because they are marked as 808 // custom. 809 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 810 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 811 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 812 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 813 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 814 815 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 816 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 817 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 818 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 819 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 820 821 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 822 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 823 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 824 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 825 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split. 826 827 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence. 828 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 829 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 830 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 831 832 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 833 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 834 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 835 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 836 837 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 838 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 839 840 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 841 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 842 }; 843 844 if (ST->hasSSE2()) 845 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 846 return LT.first * Entry->Cost; 847 848 static const CostTblEntry SSE1CostTable[] = { 849 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 850 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 851 852 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 853 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 854 855 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 856 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 857 858 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 859 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 860 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 861 862 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 863 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 864 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 865 }; 866 867 if (ST->hasSSE1()) 868 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 869 return LT.first * Entry->Cost; 870 871 // It is not a good idea to vectorize division. We have to scalarize it and 872 // in the process we will often end up having to spilling regular 873 // registers. The overhead of division is going to dominate most kernels 874 // anyways so try hard to prevent vectorization of division - it is 875 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 876 // to hide "20 cycles" for each lane. 877 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 878 ISD == ISD::UDIV || ISD == ISD::UREM)) { 879 int ScalarCost = getArithmeticInstrCost( 880 Opcode, Ty->getScalarType(), Op1Info, Op2Info, 881 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 882 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 883 } 884 885 // Fallback to the default implementation. 886 return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info); 887 } 888 889 int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, 890 Type *SubTp) { 891 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 892 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 893 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp); 894 895 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 896 if (Kind == TTI::SK_Transpose) 897 Kind = TTI::SK_PermuteTwoSrc; 898 899 // For Broadcasts we are splatting the first element from the first input 900 // register, so only need to reference that input and all the output 901 // registers are the same. 902 if (Kind == TTI::SK_Broadcast) 903 LT.first = 1; 904 905 // Subvector extractions are free if they start at the beginning of a 906 // vector and cheap if the subvectors are aligned. 907 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 908 int NumElts = LT.second.getVectorNumElements(); 909 if ((Index % NumElts) == 0) 910 return 0; 911 std::pair<int, MVT> SubLT = TLI->getTypeLegalizationCost(DL, SubTp); 912 if (SubLT.second.isVector()) { 913 int NumSubElts = SubLT.second.getVectorNumElements(); 914 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 915 return SubLT.first; 916 // Handle some cases for widening legalization. For now we only handle 917 // cases where the original subvector was naturally aligned and evenly 918 // fit in its legalized subvector type. 919 // FIXME: Remove some of the alignment restrictions. 920 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 921 // vectors. 922 int OrigSubElts = SubTp->getVectorNumElements(); 923 if (NumSubElts > OrigSubElts && 924 (Index % OrigSubElts) == 0 && (NumSubElts % OrigSubElts) == 0 && 925 LT.second.getVectorElementType() == 926 SubLT.second.getVectorElementType() && 927 LT.second.getVectorElementType().getSizeInBits() == 928 Tp->getVectorElementType()->getPrimitiveSizeInBits()) { 929 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 930 "Unexpected number of elements!"); 931 Type *VecTy = VectorType::get(Tp->getVectorElementType(), 932 LT.second.getVectorNumElements()); 933 Type *SubTy = VectorType::get(Tp->getVectorElementType(), 934 SubLT.second.getVectorNumElements()); 935 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 936 int ExtractCost = getShuffleCost(TTI::SK_ExtractSubvector, VecTy, 937 ExtractIndex, SubTy); 938 939 // If the original size is 32-bits or more, we can use pshufd. Otherwise 940 // if we have SSSE3 we can use pshufb. 941 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 942 return ExtractCost + 1; // pshufd or pshufb 943 944 assert(SubTp->getPrimitiveSizeInBits() == 16 && 945 "Unexpected vector size"); 946 947 return ExtractCost + 2; // worst case pshufhw + pshufd 948 } 949 } 950 } 951 952 // We are going to permute multiple sources and the result will be in multiple 953 // destinations. Providing an accurate cost only for splits where the element 954 // type remains the same. 955 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 956 MVT LegalVT = LT.second; 957 if (LegalVT.isVector() && 958 LegalVT.getVectorElementType().getSizeInBits() == 959 Tp->getVectorElementType()->getPrimitiveSizeInBits() && 960 LegalVT.getVectorNumElements() < Tp->getVectorNumElements()) { 961 962 unsigned VecTySize = DL.getTypeStoreSize(Tp); 963 unsigned LegalVTSize = LegalVT.getStoreSize(); 964 // Number of source vectors after legalization: 965 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 966 // Number of destination vectors after legalization: 967 unsigned NumOfDests = LT.first; 968 969 Type *SingleOpTy = VectorType::get(Tp->getVectorElementType(), 970 LegalVT.getVectorNumElements()); 971 972 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 973 return NumOfShuffles * 974 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 0, nullptr); 975 } 976 977 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 978 } 979 980 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 981 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 982 // We assume that source and destination have the same vector type. 983 int NumOfDests = LT.first; 984 int NumOfShufflesPerDest = LT.first * 2 - 1; 985 LT.first = NumOfDests * NumOfShufflesPerDest; 986 } 987 988 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 989 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 990 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 991 992 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 993 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 994 995 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 1}, // vpermt2b 996 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 1}, // vpermt2b 997 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1} // vpermt2b 998 }; 999 1000 if (ST->hasVBMI()) 1001 if (const auto *Entry = 1002 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1003 return LT.first * Entry->Cost; 1004 1005 static const CostTblEntry AVX512BWShuffleTbl[] = { 1006 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1007 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1008 1009 {TTI::SK_Reverse, MVT::v32i16, 1}, // vpermw 1010 {TTI::SK_Reverse, MVT::v16i16, 1}, // vpermw 1011 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1012 1013 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 1}, // vpermw 1014 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 1}, // vpermw 1015 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // vpermw 1016 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1017 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 3}, // vpermw + zext/trunc 1018 1019 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 1}, // vpermt2w 1020 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 1}, // vpermt2w 1021 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpermt2w 1022 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 3}, // zext + vpermt2w + trunc 1023 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1024 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3} // zext + vpermt2w + trunc 1025 }; 1026 1027 if (ST->hasBWI()) 1028 if (const auto *Entry = 1029 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1030 return LT.first * Entry->Cost; 1031 1032 static const CostTblEntry AVX512ShuffleTbl[] = { 1033 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1034 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1035 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1036 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1037 1038 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1039 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1040 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1041 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1042 1043 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1044 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1045 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1046 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1047 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1048 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1049 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1050 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1051 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1052 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1053 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1054 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1055 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1056 1057 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1058 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1059 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1060 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1061 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1062 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1063 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1064 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1065 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1066 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1067 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1068 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1} // vpermt2d 1069 }; 1070 1071 if (ST->hasAVX512()) 1072 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1073 return LT.first * Entry->Cost; 1074 1075 static const CostTblEntry AVX2ShuffleTbl[] = { 1076 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1077 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1078 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1079 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1080 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1081 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1082 1083 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1084 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1085 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1086 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1087 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1088 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1089 1090 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1091 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1092 1093 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1094 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1095 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1096 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1097 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1098 // + vpblendvb 1099 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1100 // + vpblendvb 1101 1102 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1103 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1104 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1105 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1106 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1107 // + vpblendvb 1108 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1109 // + vpblendvb 1110 }; 1111 1112 if (ST->hasAVX2()) 1113 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1114 return LT.first * Entry->Cost; 1115 1116 static const CostTblEntry XOPShuffleTbl[] = { 1117 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1118 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1119 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1120 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1121 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1122 // + vinsertf128 1123 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1124 // + vinsertf128 1125 1126 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1127 // + vinsertf128 1128 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1129 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1130 // + vinsertf128 1131 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1132 }; 1133 1134 if (ST->hasXOP()) 1135 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1136 return LT.first * Entry->Cost; 1137 1138 static const CostTblEntry AVX1ShuffleTbl[] = { 1139 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1140 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1141 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1142 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1143 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1144 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1145 1146 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1147 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1148 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1149 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1150 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1151 // + vinsertf128 1152 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1153 // + vinsertf128 1154 1155 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1156 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1157 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1158 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1159 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1160 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1161 1162 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1163 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1164 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1165 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1166 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1167 // + 2*por + vinsertf128 1168 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1169 // + 2*por + vinsertf128 1170 1171 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1172 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1173 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1174 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1175 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1176 // + 4*por + vinsertf128 1177 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1178 // + 4*por + vinsertf128 1179 }; 1180 1181 if (ST->hasAVX()) 1182 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1183 return LT.first * Entry->Cost; 1184 1185 static const CostTblEntry SSE41ShuffleTbl[] = { 1186 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1187 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1188 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1189 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1190 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1191 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1192 }; 1193 1194 if (ST->hasSSE41()) 1195 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1196 return LT.first * Entry->Cost; 1197 1198 static const CostTblEntry SSSE3ShuffleTbl[] = { 1199 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1200 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1201 1202 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1203 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1204 1205 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1206 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1207 1208 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1209 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1210 1211 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1212 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1213 }; 1214 1215 if (ST->hasSSSE3()) 1216 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1217 return LT.first * Entry->Cost; 1218 1219 static const CostTblEntry SSE2ShuffleTbl[] = { 1220 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1221 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1222 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1223 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1224 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1225 1226 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1227 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1228 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1229 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1230 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1231 // + 2*pshufd + 2*unpck + packus 1232 1233 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1234 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1235 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1236 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1237 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1238 1239 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1240 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1241 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1242 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1243 // + pshufd/unpck 1244 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1245 // + 2*pshufd + 2*unpck + 2*packus 1246 1247 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1248 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1249 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1250 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1251 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1252 }; 1253 1254 if (ST->hasSSE2()) 1255 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1256 return LT.first * Entry->Cost; 1257 1258 static const CostTblEntry SSE1ShuffleTbl[] = { 1259 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1260 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1261 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1262 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1263 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1264 }; 1265 1266 if (ST->hasSSE1()) 1267 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1268 return LT.first * Entry->Cost; 1269 1270 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 1271 } 1272 1273 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 1274 const Instruction *I) { 1275 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1276 assert(ISD && "Invalid opcode"); 1277 1278 // FIXME: Need a better design of the cost table to handle non-simple types of 1279 // potential massive combinations (elem_num x src_type x dst_type). 1280 1281 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1282 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1283 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1284 1285 // Mask sign extend has an instruction. 1286 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1287 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1288 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1289 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1290 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1291 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1292 1293 // Mask zero extend is a load + broadcast. 1294 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1295 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1296 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1297 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1298 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1299 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1300 }; 1301 1302 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1303 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1304 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1305 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1306 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1307 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1308 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1309 1310 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1311 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1312 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1313 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1314 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1315 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1316 1317 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1318 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1319 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1320 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1321 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1322 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1323 1324 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1325 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1326 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1327 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1328 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1329 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1330 }; 1331 1332 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1333 // 256-bit wide vectors. 1334 1335 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1336 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1337 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1338 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1339 1340 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 }, 1341 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 }, 1342 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 }, 1343 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 1344 1345 // v16i1 -> v16i32 - load + broadcast 1346 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1347 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1348 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1349 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1350 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1351 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1352 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1353 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1354 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1355 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1356 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1357 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1358 1359 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1360 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1361 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1362 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1363 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1364 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1365 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1366 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1367 1368 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1369 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1370 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1371 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1372 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1373 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1374 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1375 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1376 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1377 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1378 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1379 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1380 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1381 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1382 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1383 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1384 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1385 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1386 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1387 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1388 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1389 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1390 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1391 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1392 1393 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 1394 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1395 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 1396 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 1397 1398 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1399 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1400 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1401 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1402 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1403 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 2 }, 1404 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 2 }, 1405 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1406 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 2 }, 1407 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 2 }, 1408 }; 1409 1410 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1411 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1412 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1413 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1414 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1415 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1416 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1417 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1418 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1419 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1420 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1421 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1422 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1423 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1424 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1425 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1426 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1427 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1428 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 1429 1430 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 1431 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 1432 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1433 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 1434 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1435 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 }, 1436 1437 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1438 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1439 1440 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1441 }; 1442 1443 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1444 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1445 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1446 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1447 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1448 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1449 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1450 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1451 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1452 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1453 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1454 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 4 }, 1455 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1456 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1457 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1458 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1459 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1460 1461 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 1462 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1463 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1464 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1465 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 1466 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 }, 1467 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 11 }, 1468 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 9 }, 1469 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 }, 1470 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 11 }, 1471 1472 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1473 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1474 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1475 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1476 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1477 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1478 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1479 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1480 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1481 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1482 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1483 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1484 1485 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1486 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1487 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1488 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1489 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1490 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1491 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1492 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1493 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1494 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 }, 1495 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 1496 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1497 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 1498 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1499 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1500 // The generic code to compute the scalar overhead is currently broken. 1501 // Workaround this limitation by estimating the scalarization overhead 1502 // here. We have roughly 10 instructions per scalar element. 1503 // Multiply that by the vector width. 1504 // FIXME: remove that when PR19268 is fixed. 1505 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1506 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1507 1508 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 }, 1509 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 }, 1510 // This node is expanded into scalarized operations but BasicTTI is overly 1511 // optimistic estimating its cost. It computes 3 per element (one 1512 // vector-extract, one scalar conversion and one vector-insert). The 1513 // problem is that the inserts form a read-modify-write chain so latency 1514 // should be factored in too. Inflating the cost per element by 1. 1515 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, 1516 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 1517 1518 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 1519 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 1520 }; 1521 1522 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 1523 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1524 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1525 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1526 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1527 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1528 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1529 1530 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1531 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 }, 1532 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1533 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1534 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1535 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1536 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1537 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1538 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1539 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1540 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1541 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1542 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1543 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1544 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1545 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1546 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1547 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1548 1549 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, 1550 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 1551 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 1552 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 1553 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 1554 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 1555 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 1556 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 1 }, // PSHUFB 1557 1558 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 1559 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 1560 }; 1561 1562 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 1563 // These are somewhat magic numbers justified by looking at the output of 1564 // Intel's IACA, running some kernels and making sure when we take 1565 // legalization into account the throughput will be overestimated. 1566 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1567 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1568 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1569 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1570 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1571 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 2*10 }, 1572 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2*10 }, 1573 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1574 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 1575 1576 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1577 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1578 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1579 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1580 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1581 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, 1582 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 }, 1583 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1584 1585 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, 1586 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, 1587 1588 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 3 }, 1589 1590 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 6 }, 1591 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 }, 1592 1593 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 1594 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 1595 1596 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1597 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 1598 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 1599 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 1600 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1601 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 1602 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1603 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 1604 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1605 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1606 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1607 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1608 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 1609 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 1610 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1611 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 1612 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1613 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 1614 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1615 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1616 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 1617 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 1618 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1619 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 1620 1621 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // PAND+PACKUSWB 1622 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 4 }, 1623 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, 1624 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 1625 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 3 }, // PAND+3*PACKUSWB 1626 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 1627 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 1628 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 1629 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1630 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 1631 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1632 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 1633 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 1634 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 1635 { ISD::TRUNCATE, MVT::v2i32, MVT::v2i64, 1 }, // PSHUFD 1636 }; 1637 1638 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 1639 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst); 1640 1641 if (ST->hasSSE2() && !ST->hasAVX()) { 1642 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1643 LTDest.second, LTSrc.second)) 1644 return LTSrc.first * Entry->Cost; 1645 } 1646 1647 EVT SrcTy = TLI->getValueType(DL, Src); 1648 EVT DstTy = TLI->getValueType(DL, Dst); 1649 1650 // The function getSimpleVT only handles simple value types. 1651 if (!SrcTy.isSimple() || !DstTy.isSimple()) 1652 return BaseT::getCastInstrCost(Opcode, Dst, Src); 1653 1654 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 1655 MVT SimpleDstTy = DstTy.getSimpleVT(); 1656 1657 // Make sure that neither type is going to be split before using the 1658 // AVX512 tables. This handles -mprefer-vector-width=256 1659 // with -min-legal-vector-width<=256 1660 if (TLI->getTypeAction(SimpleSrcTy) != TargetLowering::TypeSplitVector && 1661 TLI->getTypeAction(SimpleDstTy) != TargetLowering::TypeSplitVector) { 1662 if (ST->hasBWI()) 1663 if (const auto *Entry = ConvertCostTableLookup(AVX512BWConversionTbl, ISD, 1664 SimpleDstTy, SimpleSrcTy)) 1665 return Entry->Cost; 1666 1667 if (ST->hasDQI()) 1668 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 1669 SimpleDstTy, SimpleSrcTy)) 1670 return Entry->Cost; 1671 1672 if (ST->hasAVX512()) 1673 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 1674 SimpleDstTy, SimpleSrcTy)) 1675 return Entry->Cost; 1676 } 1677 1678 if (ST->hasAVX2()) { 1679 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 1680 SimpleDstTy, SimpleSrcTy)) 1681 return Entry->Cost; 1682 } 1683 1684 if (ST->hasAVX()) { 1685 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 1686 SimpleDstTy, SimpleSrcTy)) 1687 return Entry->Cost; 1688 } 1689 1690 if (ST->hasSSE41()) { 1691 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 1692 SimpleDstTy, SimpleSrcTy)) 1693 return Entry->Cost; 1694 } 1695 1696 if (ST->hasSSE2()) { 1697 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1698 SimpleDstTy, SimpleSrcTy)) 1699 return Entry->Cost; 1700 } 1701 1702 return BaseT::getCastInstrCost(Opcode, Dst, Src, I); 1703 } 1704 1705 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 1706 const Instruction *I) { 1707 // Legalize the type. 1708 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 1709 1710 MVT MTy = LT.second; 1711 1712 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1713 assert(ISD && "Invalid opcode"); 1714 1715 unsigned ExtraCost = 0; 1716 if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) { 1717 // Some vector comparison predicates cost extra instructions. 1718 if (MTy.isVector() && 1719 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 1720 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 1721 ST->hasBWI())) { 1722 switch (cast<CmpInst>(I)->getPredicate()) { 1723 case CmpInst::Predicate::ICMP_NE: 1724 // xor(cmpeq(x,y),-1) 1725 ExtraCost = 1; 1726 break; 1727 case CmpInst::Predicate::ICMP_SGE: 1728 case CmpInst::Predicate::ICMP_SLE: 1729 // xor(cmpgt(x,y),-1) 1730 ExtraCost = 1; 1731 break; 1732 case CmpInst::Predicate::ICMP_ULT: 1733 case CmpInst::Predicate::ICMP_UGT: 1734 // cmpgt(xor(x,signbit),xor(y,signbit)) 1735 // xor(cmpeq(pmaxu(x,y),x),-1) 1736 ExtraCost = 2; 1737 break; 1738 case CmpInst::Predicate::ICMP_ULE: 1739 case CmpInst::Predicate::ICMP_UGE: 1740 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 1741 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 1742 // cmpeq(psubus(x,y),0) 1743 // cmpeq(pminu(x,y),x) 1744 ExtraCost = 1; 1745 } else { 1746 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 1747 ExtraCost = 3; 1748 } 1749 break; 1750 default: 1751 break; 1752 } 1753 } 1754 } 1755 1756 static const CostTblEntry SLMCostTbl[] = { 1757 // slm pcmpeq/pcmpgt throughput is 2 1758 { ISD::SETCC, MVT::v2i64, 2 }, 1759 }; 1760 1761 static const CostTblEntry AVX512BWCostTbl[] = { 1762 { ISD::SETCC, MVT::v32i16, 1 }, 1763 { ISD::SETCC, MVT::v64i8, 1 }, 1764 1765 { ISD::SELECT, MVT::v32i16, 1 }, 1766 { ISD::SELECT, MVT::v64i8, 1 }, 1767 }; 1768 1769 static const CostTblEntry AVX512CostTbl[] = { 1770 { ISD::SETCC, MVT::v8i64, 1 }, 1771 { ISD::SETCC, MVT::v16i32, 1 }, 1772 { ISD::SETCC, MVT::v8f64, 1 }, 1773 { ISD::SETCC, MVT::v16f32, 1 }, 1774 1775 { ISD::SELECT, MVT::v8i64, 1 }, 1776 { ISD::SELECT, MVT::v16i32, 1 }, 1777 { ISD::SELECT, MVT::v8f64, 1 }, 1778 { ISD::SELECT, MVT::v16f32, 1 }, 1779 }; 1780 1781 static const CostTblEntry AVX2CostTbl[] = { 1782 { ISD::SETCC, MVT::v4i64, 1 }, 1783 { ISD::SETCC, MVT::v8i32, 1 }, 1784 { ISD::SETCC, MVT::v16i16, 1 }, 1785 { ISD::SETCC, MVT::v32i8, 1 }, 1786 1787 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 1788 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 1789 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 1790 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 1791 }; 1792 1793 static const CostTblEntry AVX1CostTbl[] = { 1794 { ISD::SETCC, MVT::v4f64, 1 }, 1795 { ISD::SETCC, MVT::v8f32, 1 }, 1796 // AVX1 does not support 8-wide integer compare. 1797 { ISD::SETCC, MVT::v4i64, 4 }, 1798 { ISD::SETCC, MVT::v8i32, 4 }, 1799 { ISD::SETCC, MVT::v16i16, 4 }, 1800 { ISD::SETCC, MVT::v32i8, 4 }, 1801 1802 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 1803 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 1804 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 1805 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 1806 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 1807 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 1808 }; 1809 1810 static const CostTblEntry SSE42CostTbl[] = { 1811 { ISD::SETCC, MVT::v2f64, 1 }, 1812 { ISD::SETCC, MVT::v4f32, 1 }, 1813 { ISD::SETCC, MVT::v2i64, 1 }, 1814 }; 1815 1816 static const CostTblEntry SSE41CostTbl[] = { 1817 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 1818 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 1819 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 1820 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 1821 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 1822 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 1823 }; 1824 1825 static const CostTblEntry SSE2CostTbl[] = { 1826 { ISD::SETCC, MVT::v2f64, 2 }, 1827 { ISD::SETCC, MVT::f64, 1 }, 1828 { ISD::SETCC, MVT::v2i64, 8 }, 1829 { ISD::SETCC, MVT::v4i32, 1 }, 1830 { ISD::SETCC, MVT::v8i16, 1 }, 1831 { ISD::SETCC, MVT::v16i8, 1 }, 1832 1833 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 1834 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 1835 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 1836 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 1837 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 1838 }; 1839 1840 static const CostTblEntry SSE1CostTbl[] = { 1841 { ISD::SETCC, MVT::v4f32, 2 }, 1842 { ISD::SETCC, MVT::f32, 1 }, 1843 1844 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 1845 }; 1846 1847 if (ST->isSLM()) 1848 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 1849 return LT.first * (ExtraCost + Entry->Cost); 1850 1851 if (ST->hasBWI()) 1852 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 1853 return LT.first * (ExtraCost + Entry->Cost); 1854 1855 if (ST->hasAVX512()) 1856 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 1857 return LT.first * (ExtraCost + Entry->Cost); 1858 1859 if (ST->hasAVX2()) 1860 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 1861 return LT.first * (ExtraCost + Entry->Cost); 1862 1863 if (ST->hasAVX()) 1864 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 1865 return LT.first * (ExtraCost + Entry->Cost); 1866 1867 if (ST->hasSSE42()) 1868 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 1869 return LT.first * (ExtraCost + Entry->Cost); 1870 1871 if (ST->hasSSE41()) 1872 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 1873 return LT.first * (ExtraCost + Entry->Cost); 1874 1875 if (ST->hasSSE2()) 1876 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 1877 return LT.first * (ExtraCost + Entry->Cost); 1878 1879 if (ST->hasSSE1()) 1880 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 1881 return LT.first * (ExtraCost + Entry->Cost); 1882 1883 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I); 1884 } 1885 1886 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 1887 1888 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 1889 ArrayRef<Type *> Tys, FastMathFlags FMF, 1890 unsigned ScalarizationCostPassed, 1891 const Instruction *I) { 1892 // Costs should match the codegen from: 1893 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 1894 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 1895 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 1896 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 1897 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 1898 static const CostTblEntry AVX512CDCostTbl[] = { 1899 { ISD::CTLZ, MVT::v8i64, 1 }, 1900 { ISD::CTLZ, MVT::v16i32, 1 }, 1901 { ISD::CTLZ, MVT::v32i16, 8 }, 1902 { ISD::CTLZ, MVT::v64i8, 20 }, 1903 { ISD::CTLZ, MVT::v4i64, 1 }, 1904 { ISD::CTLZ, MVT::v8i32, 1 }, 1905 { ISD::CTLZ, MVT::v16i16, 4 }, 1906 { ISD::CTLZ, MVT::v32i8, 10 }, 1907 { ISD::CTLZ, MVT::v2i64, 1 }, 1908 { ISD::CTLZ, MVT::v4i32, 1 }, 1909 { ISD::CTLZ, MVT::v8i16, 4 }, 1910 { ISD::CTLZ, MVT::v16i8, 4 }, 1911 }; 1912 static const CostTblEntry AVX512BWCostTbl[] = { 1913 { ISD::BITREVERSE, MVT::v8i64, 5 }, 1914 { ISD::BITREVERSE, MVT::v16i32, 5 }, 1915 { ISD::BITREVERSE, MVT::v32i16, 5 }, 1916 { ISD::BITREVERSE, MVT::v64i8, 5 }, 1917 { ISD::CTLZ, MVT::v8i64, 23 }, 1918 { ISD::CTLZ, MVT::v16i32, 22 }, 1919 { ISD::CTLZ, MVT::v32i16, 18 }, 1920 { ISD::CTLZ, MVT::v64i8, 17 }, 1921 { ISD::CTPOP, MVT::v8i64, 7 }, 1922 { ISD::CTPOP, MVT::v16i32, 11 }, 1923 { ISD::CTPOP, MVT::v32i16, 9 }, 1924 { ISD::CTPOP, MVT::v64i8, 6 }, 1925 { ISD::CTTZ, MVT::v8i64, 10 }, 1926 { ISD::CTTZ, MVT::v16i32, 14 }, 1927 { ISD::CTTZ, MVT::v32i16, 12 }, 1928 { ISD::CTTZ, MVT::v64i8, 9 }, 1929 { ISD::SADDSAT, MVT::v32i16, 1 }, 1930 { ISD::SADDSAT, MVT::v64i8, 1 }, 1931 { ISD::SSUBSAT, MVT::v32i16, 1 }, 1932 { ISD::SSUBSAT, MVT::v64i8, 1 }, 1933 { ISD::UADDSAT, MVT::v32i16, 1 }, 1934 { ISD::UADDSAT, MVT::v64i8, 1 }, 1935 { ISD::USUBSAT, MVT::v32i16, 1 }, 1936 { ISD::USUBSAT, MVT::v64i8, 1 }, 1937 }; 1938 static const CostTblEntry AVX512CostTbl[] = { 1939 { ISD::BITREVERSE, MVT::v8i64, 36 }, 1940 { ISD::BITREVERSE, MVT::v16i32, 24 }, 1941 { ISD::CTLZ, MVT::v8i64, 29 }, 1942 { ISD::CTLZ, MVT::v16i32, 35 }, 1943 { ISD::CTPOP, MVT::v8i64, 16 }, 1944 { ISD::CTPOP, MVT::v16i32, 24 }, 1945 { ISD::CTTZ, MVT::v8i64, 20 }, 1946 { ISD::CTTZ, MVT::v16i32, 28 }, 1947 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 1948 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 1949 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 1950 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 1951 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 1952 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 1953 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 1954 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 1955 { ISD::FMAXNUM, MVT::f32, 2 }, 1956 { ISD::FMAXNUM, MVT::v4f32, 2 }, 1957 { ISD::FMAXNUM, MVT::v8f32, 2 }, 1958 { ISD::FMAXNUM, MVT::v16f32, 2 }, 1959 { ISD::FMAXNUM, MVT::f64, 2 }, 1960 { ISD::FMAXNUM, MVT::v2f64, 2 }, 1961 { ISD::FMAXNUM, MVT::v4f64, 2 }, 1962 { ISD::FMAXNUM, MVT::v8f64, 2 }, 1963 }; 1964 static const CostTblEntry XOPCostTbl[] = { 1965 { ISD::BITREVERSE, MVT::v4i64, 4 }, 1966 { ISD::BITREVERSE, MVT::v8i32, 4 }, 1967 { ISD::BITREVERSE, MVT::v16i16, 4 }, 1968 { ISD::BITREVERSE, MVT::v32i8, 4 }, 1969 { ISD::BITREVERSE, MVT::v2i64, 1 }, 1970 { ISD::BITREVERSE, MVT::v4i32, 1 }, 1971 { ISD::BITREVERSE, MVT::v8i16, 1 }, 1972 { ISD::BITREVERSE, MVT::v16i8, 1 }, 1973 { ISD::BITREVERSE, MVT::i64, 3 }, 1974 { ISD::BITREVERSE, MVT::i32, 3 }, 1975 { ISD::BITREVERSE, MVT::i16, 3 }, 1976 { ISD::BITREVERSE, MVT::i8, 3 } 1977 }; 1978 static const CostTblEntry AVX2CostTbl[] = { 1979 { ISD::BITREVERSE, MVT::v4i64, 5 }, 1980 { ISD::BITREVERSE, MVT::v8i32, 5 }, 1981 { ISD::BITREVERSE, MVT::v16i16, 5 }, 1982 { ISD::BITREVERSE, MVT::v32i8, 5 }, 1983 { ISD::BSWAP, MVT::v4i64, 1 }, 1984 { ISD::BSWAP, MVT::v8i32, 1 }, 1985 { ISD::BSWAP, MVT::v16i16, 1 }, 1986 { ISD::CTLZ, MVT::v4i64, 23 }, 1987 { ISD::CTLZ, MVT::v8i32, 18 }, 1988 { ISD::CTLZ, MVT::v16i16, 14 }, 1989 { ISD::CTLZ, MVT::v32i8, 9 }, 1990 { ISD::CTPOP, MVT::v4i64, 7 }, 1991 { ISD::CTPOP, MVT::v8i32, 11 }, 1992 { ISD::CTPOP, MVT::v16i16, 9 }, 1993 { ISD::CTPOP, MVT::v32i8, 6 }, 1994 { ISD::CTTZ, MVT::v4i64, 10 }, 1995 { ISD::CTTZ, MVT::v8i32, 14 }, 1996 { ISD::CTTZ, MVT::v16i16, 12 }, 1997 { ISD::CTTZ, MVT::v32i8, 9 }, 1998 { ISD::SADDSAT, MVT::v16i16, 1 }, 1999 { ISD::SADDSAT, MVT::v32i8, 1 }, 2000 { ISD::SSUBSAT, MVT::v16i16, 1 }, 2001 { ISD::SSUBSAT, MVT::v32i8, 1 }, 2002 { ISD::UADDSAT, MVT::v16i16, 1 }, 2003 { ISD::UADDSAT, MVT::v32i8, 1 }, 2004 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 2005 { ISD::USUBSAT, MVT::v16i16, 1 }, 2006 { ISD::USUBSAT, MVT::v32i8, 1 }, 2007 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2008 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2009 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2010 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2011 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2012 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2013 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2014 }; 2015 static const CostTblEntry AVX1CostTbl[] = { 2016 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 2017 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 2018 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 2019 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 2020 { ISD::BSWAP, MVT::v4i64, 4 }, 2021 { ISD::BSWAP, MVT::v8i32, 4 }, 2022 { ISD::BSWAP, MVT::v16i16, 4 }, 2023 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 2024 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 2025 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 2026 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2027 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 2028 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 2029 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 2030 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 2031 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 2032 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 2033 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 2034 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2035 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2036 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2037 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2038 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2039 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2040 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2041 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 2042 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2043 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2044 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 2045 { ISD::FMAXNUM, MVT::f32, 3 }, 2046 { ISD::FMAXNUM, MVT::v4f32, 3 }, 2047 { ISD::FMAXNUM, MVT::v8f32, 5 }, 2048 { ISD::FMAXNUM, MVT::f64, 3 }, 2049 { ISD::FMAXNUM, MVT::v2f64, 3 }, 2050 { ISD::FMAXNUM, MVT::v4f64, 5 }, 2051 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 2052 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 2053 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 2054 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 2055 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 2056 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 2057 }; 2058 static const CostTblEntry GLMCostTbl[] = { 2059 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 2060 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 2061 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 2062 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 2063 }; 2064 static const CostTblEntry SLMCostTbl[] = { 2065 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 2066 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 2067 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 2068 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 2069 }; 2070 static const CostTblEntry SSE42CostTbl[] = { 2071 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 2072 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 2073 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 2074 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 2075 }; 2076 static const CostTblEntry SSSE3CostTbl[] = { 2077 { ISD::BITREVERSE, MVT::v2i64, 5 }, 2078 { ISD::BITREVERSE, MVT::v4i32, 5 }, 2079 { ISD::BITREVERSE, MVT::v8i16, 5 }, 2080 { ISD::BITREVERSE, MVT::v16i8, 5 }, 2081 { ISD::BSWAP, MVT::v2i64, 1 }, 2082 { ISD::BSWAP, MVT::v4i32, 1 }, 2083 { ISD::BSWAP, MVT::v8i16, 1 }, 2084 { ISD::CTLZ, MVT::v2i64, 23 }, 2085 { ISD::CTLZ, MVT::v4i32, 18 }, 2086 { ISD::CTLZ, MVT::v8i16, 14 }, 2087 { ISD::CTLZ, MVT::v16i8, 9 }, 2088 { ISD::CTPOP, MVT::v2i64, 7 }, 2089 { ISD::CTPOP, MVT::v4i32, 11 }, 2090 { ISD::CTPOP, MVT::v8i16, 9 }, 2091 { ISD::CTPOP, MVT::v16i8, 6 }, 2092 { ISD::CTTZ, MVT::v2i64, 10 }, 2093 { ISD::CTTZ, MVT::v4i32, 14 }, 2094 { ISD::CTTZ, MVT::v8i16, 12 }, 2095 { ISD::CTTZ, MVT::v16i8, 9 } 2096 }; 2097 static const CostTblEntry SSE2CostTbl[] = { 2098 { ISD::BITREVERSE, MVT::v2i64, 29 }, 2099 { ISD::BITREVERSE, MVT::v4i32, 27 }, 2100 { ISD::BITREVERSE, MVT::v8i16, 27 }, 2101 { ISD::BITREVERSE, MVT::v16i8, 20 }, 2102 { ISD::BSWAP, MVT::v2i64, 7 }, 2103 { ISD::BSWAP, MVT::v4i32, 7 }, 2104 { ISD::BSWAP, MVT::v8i16, 7 }, 2105 { ISD::CTLZ, MVT::v2i64, 25 }, 2106 { ISD::CTLZ, MVT::v4i32, 26 }, 2107 { ISD::CTLZ, MVT::v8i16, 20 }, 2108 { ISD::CTLZ, MVT::v16i8, 17 }, 2109 { ISD::CTPOP, MVT::v2i64, 12 }, 2110 { ISD::CTPOP, MVT::v4i32, 15 }, 2111 { ISD::CTPOP, MVT::v8i16, 13 }, 2112 { ISD::CTPOP, MVT::v16i8, 10 }, 2113 { ISD::CTTZ, MVT::v2i64, 14 }, 2114 { ISD::CTTZ, MVT::v4i32, 18 }, 2115 { ISD::CTTZ, MVT::v8i16, 16 }, 2116 { ISD::CTTZ, MVT::v16i8, 13 }, 2117 { ISD::SADDSAT, MVT::v8i16, 1 }, 2118 { ISD::SADDSAT, MVT::v16i8, 1 }, 2119 { ISD::SSUBSAT, MVT::v8i16, 1 }, 2120 { ISD::SSUBSAT, MVT::v16i8, 1 }, 2121 { ISD::UADDSAT, MVT::v8i16, 1 }, 2122 { ISD::UADDSAT, MVT::v16i8, 1 }, 2123 { ISD::USUBSAT, MVT::v8i16, 1 }, 2124 { ISD::USUBSAT, MVT::v16i8, 1 }, 2125 { ISD::FMAXNUM, MVT::f64, 4 }, 2126 { ISD::FMAXNUM, MVT::v2f64, 4 }, 2127 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 2128 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 2129 }; 2130 static const CostTblEntry SSE1CostTbl[] = { 2131 { ISD::FMAXNUM, MVT::f32, 4 }, 2132 { ISD::FMAXNUM, MVT::v4f32, 4 }, 2133 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 2134 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 2135 }; 2136 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 2137 { ISD::CTLZ, MVT::i64, 1 }, 2138 }; 2139 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 2140 { ISD::CTLZ, MVT::i32, 1 }, 2141 { ISD::CTLZ, MVT::i16, 1 }, 2142 { ISD::CTLZ, MVT::i8, 1 }, 2143 }; 2144 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 2145 { ISD::CTPOP, MVT::i64, 1 }, 2146 }; 2147 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 2148 { ISD::CTPOP, MVT::i32, 1 }, 2149 { ISD::CTPOP, MVT::i16, 1 }, 2150 { ISD::CTPOP, MVT::i8, 1 }, 2151 }; 2152 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2153 { ISD::BITREVERSE, MVT::i64, 14 }, 2154 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 2155 { ISD::CTPOP, MVT::i64, 10 }, 2156 { ISD::SADDO, MVT::i64, 1 }, 2157 { ISD::UADDO, MVT::i64, 1 }, 2158 }; 2159 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2160 { ISD::BITREVERSE, MVT::i32, 14 }, 2161 { ISD::BITREVERSE, MVT::i16, 14 }, 2162 { ISD::BITREVERSE, MVT::i8, 11 }, 2163 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 2164 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 2165 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 2166 { ISD::CTPOP, MVT::i32, 8 }, 2167 { ISD::CTPOP, MVT::i16, 9 }, 2168 { ISD::CTPOP, MVT::i8, 7 }, 2169 { ISD::SADDO, MVT::i32, 1 }, 2170 { ISD::SADDO, MVT::i16, 1 }, 2171 { ISD::SADDO, MVT::i8, 1 }, 2172 { ISD::UADDO, MVT::i32, 1 }, 2173 { ISD::UADDO, MVT::i16, 1 }, 2174 { ISD::UADDO, MVT::i8, 1 }, 2175 }; 2176 2177 Type *OpTy = RetTy; 2178 unsigned ISD = ISD::DELETED_NODE; 2179 switch (IID) { 2180 default: 2181 break; 2182 case Intrinsic::bitreverse: 2183 ISD = ISD::BITREVERSE; 2184 break; 2185 case Intrinsic::bswap: 2186 ISD = ISD::BSWAP; 2187 break; 2188 case Intrinsic::ctlz: 2189 ISD = ISD::CTLZ; 2190 break; 2191 case Intrinsic::ctpop: 2192 ISD = ISD::CTPOP; 2193 break; 2194 case Intrinsic::cttz: 2195 ISD = ISD::CTTZ; 2196 break; 2197 case Intrinsic::maxnum: 2198 case Intrinsic::minnum: 2199 // FMINNUM has same costs so don't duplicate. 2200 ISD = ISD::FMAXNUM; 2201 break; 2202 case Intrinsic::sadd_sat: 2203 ISD = ISD::SADDSAT; 2204 break; 2205 case Intrinsic::ssub_sat: 2206 ISD = ISD::SSUBSAT; 2207 break; 2208 case Intrinsic::uadd_sat: 2209 ISD = ISD::UADDSAT; 2210 break; 2211 case Intrinsic::usub_sat: 2212 ISD = ISD::USUBSAT; 2213 break; 2214 case Intrinsic::sqrt: 2215 ISD = ISD::FSQRT; 2216 break; 2217 case Intrinsic::sadd_with_overflow: 2218 case Intrinsic::ssub_with_overflow: 2219 // SSUBO has same costs so don't duplicate. 2220 ISD = ISD::SADDO; 2221 OpTy = RetTy->getContainedType(0); 2222 break; 2223 case Intrinsic::uadd_with_overflow: 2224 case Intrinsic::usub_with_overflow: 2225 // USUBO has same costs so don't duplicate. 2226 ISD = ISD::UADDO; 2227 OpTy = RetTy->getContainedType(0); 2228 break; 2229 } 2230 2231 if (ISD != ISD::DELETED_NODE) { 2232 // Legalize the type. 2233 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 2234 MVT MTy = LT.second; 2235 2236 // Attempt to lookup cost. 2237 if (ST->useGLMDivSqrtCosts()) 2238 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 2239 return LT.first * Entry->Cost; 2240 2241 if (ST->isSLM()) 2242 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2243 return LT.first * Entry->Cost; 2244 2245 if (ST->hasCDI()) 2246 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 2247 return LT.first * Entry->Cost; 2248 2249 if (ST->hasBWI()) 2250 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2251 return LT.first * Entry->Cost; 2252 2253 if (ST->hasAVX512()) 2254 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2255 return LT.first * Entry->Cost; 2256 2257 if (ST->hasXOP()) 2258 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2259 return LT.first * Entry->Cost; 2260 2261 if (ST->hasAVX2()) 2262 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2263 return LT.first * Entry->Cost; 2264 2265 if (ST->hasAVX()) 2266 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2267 return LT.first * Entry->Cost; 2268 2269 if (ST->hasSSE42()) 2270 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2271 return LT.first * Entry->Cost; 2272 2273 if (ST->hasSSSE3()) 2274 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 2275 return LT.first * Entry->Cost; 2276 2277 if (ST->hasSSE2()) 2278 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2279 return LT.first * Entry->Cost; 2280 2281 if (ST->hasSSE1()) 2282 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2283 return LT.first * Entry->Cost; 2284 2285 if (ST->hasLZCNT()) { 2286 if (ST->is64Bit()) 2287 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 2288 return LT.first * Entry->Cost; 2289 2290 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 2291 return LT.first * Entry->Cost; 2292 } 2293 2294 if (ST->hasPOPCNT()) { 2295 if (ST->is64Bit()) 2296 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 2297 return LT.first * Entry->Cost; 2298 2299 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 2300 return LT.first * Entry->Cost; 2301 } 2302 2303 // TODO - add BMI (TZCNT) scalar handling 2304 2305 if (ST->is64Bit()) 2306 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2307 return LT.first * Entry->Cost; 2308 2309 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2310 return LT.first * Entry->Cost; 2311 } 2312 2313 return BaseT::getIntrinsicInstrCost(IID, RetTy, Tys, FMF, 2314 ScalarizationCostPassed, I); 2315 } 2316 2317 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 2318 ArrayRef<Value *> Args, FastMathFlags FMF, 2319 unsigned VF, const Instruction *I) { 2320 static const CostTblEntry AVX512CostTbl[] = { 2321 { ISD::ROTL, MVT::v8i64, 1 }, 2322 { ISD::ROTL, MVT::v4i64, 1 }, 2323 { ISD::ROTL, MVT::v2i64, 1 }, 2324 { ISD::ROTL, MVT::v16i32, 1 }, 2325 { ISD::ROTL, MVT::v8i32, 1 }, 2326 { ISD::ROTL, MVT::v4i32, 1 }, 2327 { ISD::ROTR, MVT::v8i64, 1 }, 2328 { ISD::ROTR, MVT::v4i64, 1 }, 2329 { ISD::ROTR, MVT::v2i64, 1 }, 2330 { ISD::ROTR, MVT::v16i32, 1 }, 2331 { ISD::ROTR, MVT::v8i32, 1 }, 2332 { ISD::ROTR, MVT::v4i32, 1 } 2333 }; 2334 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 2335 static const CostTblEntry XOPCostTbl[] = { 2336 { ISD::ROTL, MVT::v4i64, 4 }, 2337 { ISD::ROTL, MVT::v8i32, 4 }, 2338 { ISD::ROTL, MVT::v16i16, 4 }, 2339 { ISD::ROTL, MVT::v32i8, 4 }, 2340 { ISD::ROTL, MVT::v2i64, 1 }, 2341 { ISD::ROTL, MVT::v4i32, 1 }, 2342 { ISD::ROTL, MVT::v8i16, 1 }, 2343 { ISD::ROTL, MVT::v16i8, 1 }, 2344 { ISD::ROTR, MVT::v4i64, 6 }, 2345 { ISD::ROTR, MVT::v8i32, 6 }, 2346 { ISD::ROTR, MVT::v16i16, 6 }, 2347 { ISD::ROTR, MVT::v32i8, 6 }, 2348 { ISD::ROTR, MVT::v2i64, 2 }, 2349 { ISD::ROTR, MVT::v4i32, 2 }, 2350 { ISD::ROTR, MVT::v8i16, 2 }, 2351 { ISD::ROTR, MVT::v16i8, 2 } 2352 }; 2353 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2354 { ISD::ROTL, MVT::i64, 1 }, 2355 { ISD::ROTR, MVT::i64, 1 }, 2356 { ISD::FSHL, MVT::i64, 4 } 2357 }; 2358 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2359 { ISD::ROTL, MVT::i32, 1 }, 2360 { ISD::ROTL, MVT::i16, 1 }, 2361 { ISD::ROTL, MVT::i8, 1 }, 2362 { ISD::ROTR, MVT::i32, 1 }, 2363 { ISD::ROTR, MVT::i16, 1 }, 2364 { ISD::ROTR, MVT::i8, 1 }, 2365 { ISD::FSHL, MVT::i32, 4 }, 2366 { ISD::FSHL, MVT::i16, 4 }, 2367 { ISD::FSHL, MVT::i8, 4 } 2368 }; 2369 2370 unsigned ISD = ISD::DELETED_NODE; 2371 switch (IID) { 2372 default: 2373 break; 2374 case Intrinsic::fshl: 2375 ISD = ISD::FSHL; 2376 if (Args[0] == Args[1]) 2377 ISD = ISD::ROTL; 2378 break; 2379 case Intrinsic::fshr: 2380 // FSHR has same costs so don't duplicate. 2381 ISD = ISD::FSHL; 2382 if (Args[0] == Args[1]) 2383 ISD = ISD::ROTR; 2384 break; 2385 } 2386 2387 if (ISD != ISD::DELETED_NODE) { 2388 // Legalize the type. 2389 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 2390 MVT MTy = LT.second; 2391 2392 // Attempt to lookup cost. 2393 if (ST->hasAVX512()) 2394 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2395 return LT.first * Entry->Cost; 2396 2397 if (ST->hasXOP()) 2398 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2399 return LT.first * Entry->Cost; 2400 2401 if (ST->is64Bit()) 2402 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2403 return LT.first * Entry->Cost; 2404 2405 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2406 return LT.first * Entry->Cost; 2407 } 2408 2409 return BaseT::getIntrinsicInstrCost(IID, RetTy, Args, FMF, VF, I); 2410 } 2411 2412 int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { 2413 static const CostTblEntry SLMCostTbl[] = { 2414 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 2415 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 2416 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 2417 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 2418 }; 2419 2420 assert(Val->isVectorTy() && "This must be a vector type"); 2421 Type *ScalarType = Val->getScalarType(); 2422 int RegisterFileMoveCost = 0; 2423 2424 if (Index != -1U && (Opcode == Instruction::ExtractElement || 2425 Opcode == Instruction::InsertElement)) { 2426 // Legalize the type. 2427 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 2428 2429 // This type is legalized to a scalar type. 2430 if (!LT.second.isVector()) 2431 return 0; 2432 2433 // The type may be split. Normalize the index to the new type. 2434 unsigned NumElts = LT.second.getVectorNumElements(); 2435 unsigned SubNumElts = NumElts; 2436 Index = Index % NumElts; 2437 2438 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 2439 // For inserts, we also need to insert the subvector back. 2440 if (LT.second.getSizeInBits() > 128) { 2441 assert((LT.second.getSizeInBits() % 128) == 0 && "Illegal vector"); 2442 unsigned NumSubVecs = LT.second.getSizeInBits() / 128; 2443 SubNumElts = NumElts / NumSubVecs; 2444 if (SubNumElts <= Index) { 2445 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 2446 Index %= SubNumElts; 2447 } 2448 } 2449 2450 if (Index == 0) { 2451 // Floating point scalars are already located in index #0. 2452 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 2453 // true for all. 2454 if (ScalarType->isFloatingPointTy()) 2455 return RegisterFileMoveCost; 2456 2457 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 2458 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 2459 return 1 + RegisterFileMoveCost; 2460 } 2461 2462 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2463 assert(ISD && "Unexpected vector opcode"); 2464 MVT MScalarTy = LT.second.getScalarType(); 2465 if (ST->isSLM()) 2466 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 2467 return Entry->Cost + RegisterFileMoveCost; 2468 2469 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 2470 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 2471 (MScalarTy.isInteger() && ST->hasSSE41())) 2472 return 1 + RegisterFileMoveCost; 2473 2474 // Assume insertps is relatively cheap on all targets. 2475 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 2476 Opcode == Instruction::InsertElement) 2477 return 1 + RegisterFileMoveCost; 2478 2479 // For extractions we just need to shuffle the element to index 0, which 2480 // should be very cheap (assume cost = 1). For insertions we need to shuffle 2481 // the elements to its destination. In both cases we must handle the 2482 // subvector move(s). 2483 // TODO: Under what circumstances should we shuffle using the full width? 2484 int ShuffleCost = 1; 2485 if (Opcode == Instruction::InsertElement) { 2486 Type *SubTy = VectorType::get(Val->getVectorElementType(), SubNumElts); 2487 ShuffleCost = getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, 0, SubTy); 2488 } 2489 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 2490 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 2491 } 2492 2493 // Add to the base cost if we know that the extracted element of a vector is 2494 // destined to be moved to and used in the integer register file. 2495 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 2496 RegisterFileMoveCost += 1; 2497 2498 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 2499 } 2500 2501 int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 2502 MaybeAlign Alignment, unsigned AddressSpace, 2503 const Instruction *I) { 2504 // Handle non-power-of-two vectors such as <3 x float> 2505 if (VectorType *VTy = dyn_cast<VectorType>(Src)) { 2506 unsigned NumElem = VTy->getVectorNumElements(); 2507 2508 // Handle a few common cases: 2509 // <3 x float> 2510 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 2511 // Cost = 64 bit store + extract + 32 bit store. 2512 return 3; 2513 2514 // <3 x double> 2515 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 2516 // Cost = 128 bit store + unpack + 64 bit store. 2517 return 3; 2518 2519 // Assume that all other non-power-of-two numbers are scalarized. 2520 if (!isPowerOf2_32(NumElem)) { 2521 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment, 2522 AddressSpace); 2523 int SplitCost = getScalarizationOverhead(Src, Opcode == Instruction::Load, 2524 Opcode == Instruction::Store); 2525 return NumElem * Cost + SplitCost; 2526 } 2527 } 2528 2529 // Legalize the type. 2530 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 2531 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 2532 "Invalid Opcode"); 2533 2534 // Each load/store unit costs 1. 2535 int Cost = LT.first * 1; 2536 2537 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a 2538 // proxy for a double-pumped AVX memory interface such as on Sandybridge. 2539 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow()) 2540 Cost *= 2; 2541 2542 return Cost; 2543 } 2544 2545 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, 2546 unsigned Alignment, 2547 unsigned AddressSpace) { 2548 bool IsLoad = (Instruction::Load == Opcode); 2549 bool IsStore = (Instruction::Store == Opcode); 2550 2551 VectorType *SrcVTy = dyn_cast<VectorType>(SrcTy); 2552 if (!SrcVTy) 2553 // To calculate scalar take the regular cost, without mask 2554 return getMemoryOpCost(Opcode, SrcTy, MaybeAlign(Alignment), AddressSpace); 2555 2556 unsigned NumElem = SrcVTy->getVectorNumElements(); 2557 VectorType *MaskTy = 2558 VectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 2559 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, MaybeAlign(Alignment))) || 2560 (IsStore && !isLegalMaskedStore(SrcVTy, MaybeAlign(Alignment))) || 2561 !isPowerOf2_32(NumElem)) { 2562 // Scalarization 2563 int MaskSplitCost = getScalarizationOverhead(MaskTy, false, true); 2564 int ScalarCompareCost = getCmpSelInstrCost( 2565 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr); 2566 int BranchCost = getCFInstrCost(Instruction::Br); 2567 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 2568 2569 int ValueSplitCost = getScalarizationOverhead(SrcVTy, IsLoad, IsStore); 2570 int MemopCost = 2571 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2572 MaybeAlign(Alignment), AddressSpace); 2573 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 2574 } 2575 2576 // Legalize the type. 2577 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 2578 auto VT = TLI->getValueType(DL, SrcVTy); 2579 int Cost = 0; 2580 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 2581 LT.second.getVectorNumElements() == NumElem) 2582 // Promotion requires expand/truncate for data and a shuffle for mask. 2583 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, 0, nullptr) + 2584 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, 0, nullptr); 2585 2586 else if (LT.second.getVectorNumElements() > NumElem) { 2587 VectorType *NewMaskTy = VectorType::get(MaskTy->getVectorElementType(), 2588 LT.second.getVectorNumElements()); 2589 // Expanding requires fill mask with zeroes 2590 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, 0, MaskTy); 2591 } 2592 2593 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 2594 if (!ST->hasAVX512()) 2595 return Cost + LT.first * (IsLoad ? 2 : 8); 2596 2597 // AVX-512 masked load/store is cheapper 2598 return Cost + LT.first; 2599 } 2600 2601 int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE, 2602 const SCEV *Ptr) { 2603 // Address computations in vectorized code with non-consecutive addresses will 2604 // likely result in more instructions compared to scalar code where the 2605 // computation can more often be merged into the index mode. The resulting 2606 // extra micro-ops can significantly decrease throughput. 2607 const unsigned NumVectorInstToHideOverhead = 10; 2608 2609 // Cost modeling of Strided Access Computation is hidden by the indexing 2610 // modes of X86 regardless of the stride value. We dont believe that there 2611 // is a difference between constant strided access in gerenal and constant 2612 // strided value which is less than or equal to 64. 2613 // Even in the case of (loop invariant) stride whose value is not known at 2614 // compile time, the address computation will not incur more than one extra 2615 // ADD instruction. 2616 if (Ty->isVectorTy() && SE) { 2617 if (!BaseT::isStridedAccess(Ptr)) 2618 return NumVectorInstToHideOverhead; 2619 if (!BaseT::getConstantStrideStep(SE, Ptr)) 2620 return 1; 2621 } 2622 2623 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 2624 } 2625 2626 int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, Type *ValTy, 2627 bool IsPairwise) { 2628 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 2629 // and make it as the cost. 2630 2631 static const CostTblEntry SLMCostTblPairWise[] = { 2632 { ISD::FADD, MVT::v2f64, 3 }, 2633 { ISD::ADD, MVT::v2i64, 5 }, 2634 }; 2635 2636 static const CostTblEntry SSE2CostTblPairWise[] = { 2637 { ISD::FADD, MVT::v2f64, 2 }, 2638 { ISD::FADD, MVT::v4f32, 4 }, 2639 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 2640 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32. 2641 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5". 2642 { ISD::ADD, MVT::v2i16, 3 }, // FIXME: chosen to be less than v4i16 2643 { ISD::ADD, MVT::v4i16, 4 }, // FIXME: chosen to be less than v8i16 2644 { ISD::ADD, MVT::v8i16, 5 }, 2645 { ISD::ADD, MVT::v2i8, 2 }, 2646 { ISD::ADD, MVT::v4i8, 2 }, 2647 { ISD::ADD, MVT::v8i8, 2 }, 2648 { ISD::ADD, MVT::v16i8, 3 }, 2649 }; 2650 2651 static const CostTblEntry AVX1CostTblPairWise[] = { 2652 { ISD::FADD, MVT::v4f64, 5 }, 2653 { ISD::FADD, MVT::v8f32, 7 }, 2654 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 2655 { ISD::ADD, MVT::v4i64, 5 }, // The data reported by the IACA tool is "4.8". 2656 { ISD::ADD, MVT::v8i32, 5 }, 2657 { ISD::ADD, MVT::v16i16, 6 }, 2658 { ISD::ADD, MVT::v32i8, 4 }, 2659 }; 2660 2661 static const CostTblEntry SLMCostTblNoPairWise[] = { 2662 { ISD::FADD, MVT::v2f64, 3 }, 2663 { ISD::ADD, MVT::v2i64, 5 }, 2664 }; 2665 2666 static const CostTblEntry SSE2CostTblNoPairWise[] = { 2667 { ISD::FADD, MVT::v2f64, 2 }, 2668 { ISD::FADD, MVT::v4f32, 4 }, 2669 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 2670 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 2671 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 2672 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 2673 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 2674 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 2675 { ISD::ADD, MVT::v2i8, 2 }, 2676 { ISD::ADD, MVT::v4i8, 2 }, 2677 { ISD::ADD, MVT::v8i8, 2 }, 2678 { ISD::ADD, MVT::v16i8, 3 }, 2679 }; 2680 2681 static const CostTblEntry AVX1CostTblNoPairWise[] = { 2682 { ISD::FADD, MVT::v4f64, 3 }, 2683 { ISD::FADD, MVT::v4f32, 3 }, 2684 { ISD::FADD, MVT::v8f32, 4 }, 2685 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 2686 { ISD::ADD, MVT::v4i64, 3 }, 2687 { ISD::ADD, MVT::v8i32, 5 }, 2688 { ISD::ADD, MVT::v16i16, 5 }, 2689 { ISD::ADD, MVT::v32i8, 4 }, 2690 }; 2691 2692 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2693 assert(ISD && "Invalid opcode"); 2694 2695 // Before legalizing the type, give a chance to look up illegal narrow types 2696 // in the table. 2697 // FIXME: Is there a better way to do this? 2698 EVT VT = TLI->getValueType(DL, ValTy); 2699 if (VT.isSimple()) { 2700 MVT MTy = VT.getSimpleVT(); 2701 if (IsPairwise) { 2702 if (ST->isSLM()) 2703 if (const auto *Entry = CostTableLookup(SLMCostTblPairWise, ISD, MTy)) 2704 return Entry->Cost; 2705 2706 if (ST->hasAVX()) 2707 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy)) 2708 return Entry->Cost; 2709 2710 if (ST->hasSSE2()) 2711 if (const auto *Entry = CostTableLookup(SSE2CostTblPairWise, ISD, MTy)) 2712 return Entry->Cost; 2713 } else { 2714 if (ST->isSLM()) 2715 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 2716 return Entry->Cost; 2717 2718 if (ST->hasAVX()) 2719 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 2720 return Entry->Cost; 2721 2722 if (ST->hasSSE2()) 2723 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 2724 return Entry->Cost; 2725 } 2726 } 2727 2728 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2729 2730 MVT MTy = LT.second; 2731 2732 if (IsPairwise) { 2733 if (ST->isSLM()) 2734 if (const auto *Entry = CostTableLookup(SLMCostTblPairWise, ISD, MTy)) 2735 return LT.first * Entry->Cost; 2736 2737 if (ST->hasAVX()) 2738 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy)) 2739 return LT.first * Entry->Cost; 2740 2741 if (ST->hasSSE2()) 2742 if (const auto *Entry = CostTableLookup(SSE2CostTblPairWise, ISD, MTy)) 2743 return LT.first * Entry->Cost; 2744 } else { 2745 if (ST->isSLM()) 2746 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 2747 return LT.first * Entry->Cost; 2748 2749 if (ST->hasAVX()) 2750 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 2751 return LT.first * Entry->Cost; 2752 2753 if (ST->hasSSE2()) 2754 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 2755 return LT.first * Entry->Cost; 2756 } 2757 2758 // FIXME: These assume a naive kshift+binop lowering, which is probably 2759 // conservative in most cases. 2760 // FIXME: This doesn't cost large types like v128i1 correctly. 2761 static const CostTblEntry AVX512BoolReduction[] = { 2762 { ISD::AND, MVT::v2i1, 3 }, 2763 { ISD::AND, MVT::v4i1, 5 }, 2764 { ISD::AND, MVT::v8i1, 7 }, 2765 { ISD::AND, MVT::v16i1, 9 }, 2766 { ISD::AND, MVT::v32i1, 11 }, 2767 { ISD::AND, MVT::v64i1, 13 }, 2768 { ISD::OR, MVT::v2i1, 3 }, 2769 { ISD::OR, MVT::v4i1, 5 }, 2770 { ISD::OR, MVT::v8i1, 7 }, 2771 { ISD::OR, MVT::v16i1, 9 }, 2772 { ISD::OR, MVT::v32i1, 11 }, 2773 { ISD::OR, MVT::v64i1, 13 }, 2774 }; 2775 2776 static const CostTblEntry AVX2BoolReduction[] = { 2777 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 2778 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 2779 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 2780 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 2781 }; 2782 2783 static const CostTblEntry AVX1BoolReduction[] = { 2784 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 2785 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 2786 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 2787 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 2788 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 2789 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 2790 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 2791 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 2792 }; 2793 2794 static const CostTblEntry SSE2BoolReduction[] = { 2795 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 2796 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 2797 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 2798 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 2799 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 2800 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 2801 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 2802 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 2803 }; 2804 2805 // Handle bool allof/anyof patterns. 2806 if (!IsPairwise && ValTy->getVectorElementType()->isIntegerTy(1)) { 2807 if (ST->hasAVX512()) 2808 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 2809 return LT.first * Entry->Cost; 2810 if (ST->hasAVX2()) 2811 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 2812 return LT.first * Entry->Cost; 2813 if (ST->hasAVX()) 2814 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 2815 return LT.first * Entry->Cost; 2816 if (ST->hasSSE2()) 2817 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 2818 return LT.first * Entry->Cost; 2819 } 2820 2821 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise); 2822 } 2823 2824 int X86TTIImpl::getMinMaxReductionCost(Type *ValTy, Type *CondTy, 2825 bool IsPairwise, bool IsUnsigned) { 2826 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2827 2828 MVT MTy = LT.second; 2829 2830 int ISD; 2831 if (ValTy->isIntOrIntVectorTy()) { 2832 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 2833 } else { 2834 assert(ValTy->isFPOrFPVectorTy() && 2835 "Expected float point or integer vector type."); 2836 ISD = ISD::FMINNUM; 2837 } 2838 2839 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 2840 // and make it as the cost. 2841 2842 static const CostTblEntry SSE1CostTblPairWise[] = { 2843 {ISD::FMINNUM, MVT::v4f32, 4}, 2844 }; 2845 2846 static const CostTblEntry SSE2CostTblPairWise[] = { 2847 {ISD::FMINNUM, MVT::v2f64, 3}, 2848 {ISD::SMIN, MVT::v2i64, 6}, 2849 {ISD::UMIN, MVT::v2i64, 8}, 2850 {ISD::SMIN, MVT::v4i32, 6}, 2851 {ISD::UMIN, MVT::v4i32, 8}, 2852 {ISD::SMIN, MVT::v8i16, 4}, 2853 {ISD::UMIN, MVT::v8i16, 6}, 2854 {ISD::SMIN, MVT::v16i8, 8}, 2855 {ISD::UMIN, MVT::v16i8, 6}, 2856 }; 2857 2858 static const CostTblEntry SSE41CostTblPairWise[] = { 2859 {ISD::FMINNUM, MVT::v4f32, 2}, 2860 {ISD::SMIN, MVT::v2i64, 9}, 2861 {ISD::UMIN, MVT::v2i64,10}, 2862 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5" 2863 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8" 2864 {ISD::SMIN, MVT::v8i16, 2}, 2865 {ISD::UMIN, MVT::v8i16, 2}, 2866 {ISD::SMIN, MVT::v16i8, 3}, 2867 {ISD::UMIN, MVT::v16i8, 3}, 2868 }; 2869 2870 static const CostTblEntry SSE42CostTblPairWise[] = { 2871 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8" 2872 {ISD::UMIN, MVT::v2i64, 8}, // The data reported by the IACA is "8.6" 2873 }; 2874 2875 static const CostTblEntry AVX1CostTblPairWise[] = { 2876 {ISD::FMINNUM, MVT::v4f32, 1}, 2877 {ISD::FMINNUM, MVT::v4f64, 1}, 2878 {ISD::FMINNUM, MVT::v8f32, 2}, 2879 {ISD::SMIN, MVT::v2i64, 3}, 2880 {ISD::UMIN, MVT::v2i64, 3}, 2881 {ISD::SMIN, MVT::v4i32, 1}, 2882 {ISD::UMIN, MVT::v4i32, 1}, 2883 {ISD::SMIN, MVT::v8i16, 1}, 2884 {ISD::UMIN, MVT::v8i16, 1}, 2885 {ISD::SMIN, MVT::v16i8, 2}, 2886 {ISD::UMIN, MVT::v16i8, 2}, 2887 {ISD::SMIN, MVT::v4i64, 7}, 2888 {ISD::UMIN, MVT::v4i64, 7}, 2889 {ISD::SMIN, MVT::v8i32, 3}, 2890 {ISD::UMIN, MVT::v8i32, 3}, 2891 {ISD::SMIN, MVT::v16i16, 3}, 2892 {ISD::UMIN, MVT::v16i16, 3}, 2893 {ISD::SMIN, MVT::v32i8, 3}, 2894 {ISD::UMIN, MVT::v32i8, 3}, 2895 }; 2896 2897 static const CostTblEntry AVX2CostTblPairWise[] = { 2898 {ISD::SMIN, MVT::v4i64, 2}, 2899 {ISD::UMIN, MVT::v4i64, 2}, 2900 {ISD::SMIN, MVT::v8i32, 1}, 2901 {ISD::UMIN, MVT::v8i32, 1}, 2902 {ISD::SMIN, MVT::v16i16, 1}, 2903 {ISD::UMIN, MVT::v16i16, 1}, 2904 {ISD::SMIN, MVT::v32i8, 2}, 2905 {ISD::UMIN, MVT::v32i8, 2}, 2906 }; 2907 2908 static const CostTblEntry AVX512CostTblPairWise[] = { 2909 {ISD::FMINNUM, MVT::v8f64, 1}, 2910 {ISD::FMINNUM, MVT::v16f32, 2}, 2911 {ISD::SMIN, MVT::v8i64, 2}, 2912 {ISD::UMIN, MVT::v8i64, 2}, 2913 {ISD::SMIN, MVT::v16i32, 1}, 2914 {ISD::UMIN, MVT::v16i32, 1}, 2915 }; 2916 2917 static const CostTblEntry SSE1CostTblNoPairWise[] = { 2918 {ISD::FMINNUM, MVT::v4f32, 4}, 2919 }; 2920 2921 static const CostTblEntry SSE2CostTblNoPairWise[] = { 2922 {ISD::FMINNUM, MVT::v2f64, 3}, 2923 {ISD::SMIN, MVT::v2i64, 6}, 2924 {ISD::UMIN, MVT::v2i64, 8}, 2925 {ISD::SMIN, MVT::v4i32, 6}, 2926 {ISD::UMIN, MVT::v4i32, 8}, 2927 {ISD::SMIN, MVT::v8i16, 4}, 2928 {ISD::UMIN, MVT::v8i16, 6}, 2929 {ISD::SMIN, MVT::v16i8, 8}, 2930 {ISD::UMIN, MVT::v16i8, 6}, 2931 }; 2932 2933 static const CostTblEntry SSE41CostTblNoPairWise[] = { 2934 {ISD::FMINNUM, MVT::v4f32, 3}, 2935 {ISD::SMIN, MVT::v2i64, 9}, 2936 {ISD::UMIN, MVT::v2i64,11}, 2937 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5" 2938 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8" 2939 {ISD::SMIN, MVT::v8i16, 1}, // The data reported by the IACA is "1.5" 2940 {ISD::UMIN, MVT::v8i16, 2}, // The data reported by the IACA is "1.8" 2941 {ISD::SMIN, MVT::v16i8, 3}, 2942 {ISD::UMIN, MVT::v16i8, 3}, 2943 }; 2944 2945 static const CostTblEntry SSE42CostTblNoPairWise[] = { 2946 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8" 2947 {ISD::UMIN, MVT::v2i64, 9}, // The data reported by the IACA is "8.6" 2948 }; 2949 2950 static const CostTblEntry AVX1CostTblNoPairWise[] = { 2951 {ISD::FMINNUM, MVT::v4f32, 1}, 2952 {ISD::FMINNUM, MVT::v4f64, 1}, 2953 {ISD::FMINNUM, MVT::v8f32, 1}, 2954 {ISD::SMIN, MVT::v2i64, 3}, 2955 {ISD::UMIN, MVT::v2i64, 3}, 2956 {ISD::SMIN, MVT::v4i32, 1}, 2957 {ISD::UMIN, MVT::v4i32, 1}, 2958 {ISD::SMIN, MVT::v8i16, 1}, 2959 {ISD::UMIN, MVT::v8i16, 1}, 2960 {ISD::SMIN, MVT::v16i8, 2}, 2961 {ISD::UMIN, MVT::v16i8, 2}, 2962 {ISD::SMIN, MVT::v4i64, 7}, 2963 {ISD::UMIN, MVT::v4i64, 7}, 2964 {ISD::SMIN, MVT::v8i32, 2}, 2965 {ISD::UMIN, MVT::v8i32, 2}, 2966 {ISD::SMIN, MVT::v16i16, 2}, 2967 {ISD::UMIN, MVT::v16i16, 2}, 2968 {ISD::SMIN, MVT::v32i8, 2}, 2969 {ISD::UMIN, MVT::v32i8, 2}, 2970 }; 2971 2972 static const CostTblEntry AVX2CostTblNoPairWise[] = { 2973 {ISD::SMIN, MVT::v4i64, 1}, 2974 {ISD::UMIN, MVT::v4i64, 1}, 2975 {ISD::SMIN, MVT::v8i32, 1}, 2976 {ISD::UMIN, MVT::v8i32, 1}, 2977 {ISD::SMIN, MVT::v16i16, 1}, 2978 {ISD::UMIN, MVT::v16i16, 1}, 2979 {ISD::SMIN, MVT::v32i8, 1}, 2980 {ISD::UMIN, MVT::v32i8, 1}, 2981 }; 2982 2983 static const CostTblEntry AVX512CostTblNoPairWise[] = { 2984 {ISD::FMINNUM, MVT::v8f64, 1}, 2985 {ISD::FMINNUM, MVT::v16f32, 2}, 2986 {ISD::SMIN, MVT::v8i64, 1}, 2987 {ISD::UMIN, MVT::v8i64, 1}, 2988 {ISD::SMIN, MVT::v16i32, 1}, 2989 {ISD::UMIN, MVT::v16i32, 1}, 2990 }; 2991 2992 if (IsPairwise) { 2993 if (ST->hasAVX512()) 2994 if (const auto *Entry = CostTableLookup(AVX512CostTblPairWise, ISD, MTy)) 2995 return LT.first * Entry->Cost; 2996 2997 if (ST->hasAVX2()) 2998 if (const auto *Entry = CostTableLookup(AVX2CostTblPairWise, ISD, MTy)) 2999 return LT.first * Entry->Cost; 3000 3001 if (ST->hasAVX()) 3002 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy)) 3003 return LT.first * Entry->Cost; 3004 3005 if (ST->hasSSE42()) 3006 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy)) 3007 return LT.first * Entry->Cost; 3008 3009 if (ST->hasSSE41()) 3010 if (const auto *Entry = CostTableLookup(SSE41CostTblPairWise, ISD, MTy)) 3011 return LT.first * Entry->Cost; 3012 3013 if (ST->hasSSE2()) 3014 if (const auto *Entry = CostTableLookup(SSE2CostTblPairWise, ISD, MTy)) 3015 return LT.first * Entry->Cost; 3016 3017 if (ST->hasSSE1()) 3018 if (const auto *Entry = CostTableLookup(SSE1CostTblPairWise, ISD, MTy)) 3019 return LT.first * Entry->Cost; 3020 } else { 3021 if (ST->hasAVX512()) 3022 if (const auto *Entry = 3023 CostTableLookup(AVX512CostTblNoPairWise, ISD, MTy)) 3024 return LT.first * Entry->Cost; 3025 3026 if (ST->hasAVX2()) 3027 if (const auto *Entry = CostTableLookup(AVX2CostTblNoPairWise, ISD, MTy)) 3028 return LT.first * Entry->Cost; 3029 3030 if (ST->hasAVX()) 3031 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 3032 return LT.first * Entry->Cost; 3033 3034 if (ST->hasSSE42()) 3035 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy)) 3036 return LT.first * Entry->Cost; 3037 3038 if (ST->hasSSE41()) 3039 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 3040 return LT.first * Entry->Cost; 3041 3042 if (ST->hasSSE2()) 3043 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 3044 return LT.first * Entry->Cost; 3045 3046 if (ST->hasSSE1()) 3047 if (const auto *Entry = CostTableLookup(SSE1CostTblNoPairWise, ISD, MTy)) 3048 return LT.first * Entry->Cost; 3049 } 3050 3051 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned); 3052 } 3053 3054 /// Calculate the cost of materializing a 64-bit value. This helper 3055 /// method might only calculate a fraction of a larger immediate. Therefore it 3056 /// is valid to return a cost of ZERO. 3057 int X86TTIImpl::getIntImmCost(int64_t Val) { 3058 if (Val == 0) 3059 return TTI::TCC_Free; 3060 3061 if (isInt<32>(Val)) 3062 return TTI::TCC_Basic; 3063 3064 return 2 * TTI::TCC_Basic; 3065 } 3066 3067 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { 3068 assert(Ty->isIntegerTy()); 3069 3070 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3071 if (BitSize == 0) 3072 return ~0U; 3073 3074 // Never hoist constants larger than 128bit, because this might lead to 3075 // incorrect code generation or assertions in codegen. 3076 // Fixme: Create a cost model for types larger than i128 once the codegen 3077 // issues have been fixed. 3078 if (BitSize > 128) 3079 return TTI::TCC_Free; 3080 3081 if (Imm == 0) 3082 return TTI::TCC_Free; 3083 3084 // Sign-extend all constants to a multiple of 64-bit. 3085 APInt ImmVal = Imm; 3086 if (BitSize % 64 != 0) 3087 ImmVal = Imm.sext(alignTo(BitSize, 64)); 3088 3089 // Split the constant into 64-bit chunks and calculate the cost for each 3090 // chunk. 3091 int Cost = 0; 3092 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 3093 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 3094 int64_t Val = Tmp.getSExtValue(); 3095 Cost += getIntImmCost(Val); 3096 } 3097 // We need at least one instruction to materialize the constant. 3098 return std::max(1, Cost); 3099 } 3100 3101 int X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, 3102 Type *Ty) { 3103 assert(Ty->isIntegerTy()); 3104 3105 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3106 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3107 // here, so that constant hoisting will ignore this constant. 3108 if (BitSize == 0) 3109 return TTI::TCC_Free; 3110 3111 unsigned ImmIdx = ~0U; 3112 switch (Opcode) { 3113 default: 3114 return TTI::TCC_Free; 3115 case Instruction::GetElementPtr: 3116 // Always hoist the base address of a GetElementPtr. This prevents the 3117 // creation of new constants for every base constant that gets constant 3118 // folded with the offset. 3119 if (Idx == 0) 3120 return 2 * TTI::TCC_Basic; 3121 return TTI::TCC_Free; 3122 case Instruction::Store: 3123 ImmIdx = 0; 3124 break; 3125 case Instruction::ICmp: 3126 // This is an imperfect hack to prevent constant hoisting of 3127 // compares that might be trying to check if a 64-bit value fits in 3128 // 32-bits. The backend can optimize these cases using a right shift by 32. 3129 // Ideally we would check the compare predicate here. There also other 3130 // similar immediates the backend can use shifts for. 3131 if (Idx == 1 && Imm.getBitWidth() == 64) { 3132 uint64_t ImmVal = Imm.getZExtValue(); 3133 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 3134 return TTI::TCC_Free; 3135 } 3136 ImmIdx = 1; 3137 break; 3138 case Instruction::And: 3139 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 3140 // by using a 32-bit operation with implicit zero extension. Detect such 3141 // immediates here as the normal path expects bit 31 to be sign extended. 3142 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 3143 return TTI::TCC_Free; 3144 ImmIdx = 1; 3145 break; 3146 case Instruction::Add: 3147 case Instruction::Sub: 3148 // For add/sub, we can use the opposite instruction for INT32_MIN. 3149 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 3150 return TTI::TCC_Free; 3151 ImmIdx = 1; 3152 break; 3153 case Instruction::UDiv: 3154 case Instruction::SDiv: 3155 case Instruction::URem: 3156 case Instruction::SRem: 3157 // Division by constant is typically expanded later into a different 3158 // instruction sequence. This completely changes the constants. 3159 // Report them as "free" to stop ConstantHoist from marking them as opaque. 3160 return TTI::TCC_Free; 3161 case Instruction::Mul: 3162 case Instruction::Or: 3163 case Instruction::Xor: 3164 ImmIdx = 1; 3165 break; 3166 // Always return TCC_Free for the shift value of a shift instruction. 3167 case Instruction::Shl: 3168 case Instruction::LShr: 3169 case Instruction::AShr: 3170 if (Idx == 1) 3171 return TTI::TCC_Free; 3172 break; 3173 case Instruction::Trunc: 3174 case Instruction::ZExt: 3175 case Instruction::SExt: 3176 case Instruction::IntToPtr: 3177 case Instruction::PtrToInt: 3178 case Instruction::BitCast: 3179 case Instruction::PHI: 3180 case Instruction::Call: 3181 case Instruction::Select: 3182 case Instruction::Ret: 3183 case Instruction::Load: 3184 break; 3185 } 3186 3187 if (Idx == ImmIdx) { 3188 int NumConstants = divideCeil(BitSize, 64); 3189 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty); 3190 return (Cost <= NumConstants * TTI::TCC_Basic) 3191 ? static_cast<int>(TTI::TCC_Free) 3192 : Cost; 3193 } 3194 3195 return X86TTIImpl::getIntImmCost(Imm, Ty); 3196 } 3197 3198 int X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 3199 const APInt &Imm, Type *Ty) { 3200 assert(Ty->isIntegerTy()); 3201 3202 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3203 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3204 // here, so that constant hoisting will ignore this constant. 3205 if (BitSize == 0) 3206 return TTI::TCC_Free; 3207 3208 switch (IID) { 3209 default: 3210 return TTI::TCC_Free; 3211 case Intrinsic::sadd_with_overflow: 3212 case Intrinsic::uadd_with_overflow: 3213 case Intrinsic::ssub_with_overflow: 3214 case Intrinsic::usub_with_overflow: 3215 case Intrinsic::smul_with_overflow: 3216 case Intrinsic::umul_with_overflow: 3217 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 3218 return TTI::TCC_Free; 3219 break; 3220 case Intrinsic::experimental_stackmap: 3221 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 3222 return TTI::TCC_Free; 3223 break; 3224 case Intrinsic::experimental_patchpoint_void: 3225 case Intrinsic::experimental_patchpoint_i64: 3226 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 3227 return TTI::TCC_Free; 3228 break; 3229 } 3230 return X86TTIImpl::getIntImmCost(Imm, Ty); 3231 } 3232 3233 unsigned X86TTIImpl::getUserCost(const User *U, 3234 ArrayRef<const Value *> Operands) { 3235 if (isa<StoreInst>(U)) { 3236 Value *Ptr = U->getOperand(1); 3237 // Store instruction with index and scale costs 2 Uops. 3238 // Check the preceding GEP to identify non-const indices. 3239 if (auto GEP = dyn_cast<GetElementPtrInst>(Ptr)) { 3240 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3241 return TTI::TCC_Basic * 2; 3242 } 3243 return TTI::TCC_Basic; 3244 } 3245 return BaseT::getUserCost(U, Operands); 3246 } 3247 3248 // Return an average cost of Gather / Scatter instruction, maybe improved later 3249 int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, Value *Ptr, 3250 unsigned Alignment, unsigned AddressSpace) { 3251 3252 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 3253 unsigned VF = SrcVTy->getVectorNumElements(); 3254 3255 // Try to reduce index size from 64 bit (default for GEP) 3256 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 3257 // operation will use 16 x 64 indices which do not fit in a zmm and needs 3258 // to split. Also check that the base pointer is the same for all lanes, 3259 // and that there's at most one variable index. 3260 auto getIndexSizeInBits = [](Value *Ptr, const DataLayout& DL) { 3261 unsigned IndexSize = DL.getPointerSizeInBits(); 3262 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 3263 if (IndexSize < 64 || !GEP) 3264 return IndexSize; 3265 3266 unsigned NumOfVarIndices = 0; 3267 Value *Ptrs = GEP->getPointerOperand(); 3268 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 3269 return IndexSize; 3270 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 3271 if (isa<Constant>(GEP->getOperand(i))) 3272 continue; 3273 Type *IndxTy = GEP->getOperand(i)->getType(); 3274 if (IndxTy->isVectorTy()) 3275 IndxTy = IndxTy->getVectorElementType(); 3276 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 3277 !isa<SExtInst>(GEP->getOperand(i))) || 3278 ++NumOfVarIndices > 1) 3279 return IndexSize; // 64 3280 } 3281 return (unsigned)32; 3282 }; 3283 3284 3285 // Trying to reduce IndexSize to 32 bits for vector 16. 3286 // By default the IndexSize is equal to pointer size. 3287 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 3288 ? getIndexSizeInBits(Ptr, DL) 3289 : DL.getPointerSizeInBits(); 3290 3291 Type *IndexVTy = VectorType::get(IntegerType::get(SrcVTy->getContext(), 3292 IndexSize), VF); 3293 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy); 3294 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3295 int SplitFactor = std::max(IdxsLT.first, SrcLT.first); 3296 if (SplitFactor > 1) { 3297 // Handle splitting of vector of pointers 3298 Type *SplitSrcTy = VectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 3299 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 3300 AddressSpace); 3301 } 3302 3303 // The gather / scatter cost is given by Intel architects. It is a rough 3304 // number since we are looking at one instruction in a time. 3305 const int GSOverhead = (Opcode == Instruction::Load) 3306 ? ST->getGatherOverhead() 3307 : ST->getScatterOverhead(); 3308 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3309 MaybeAlign(Alignment), AddressSpace); 3310 } 3311 3312 /// Return the cost of full scalarization of gather / scatter operation. 3313 /// 3314 /// Opcode - Load or Store instruction. 3315 /// SrcVTy - The type of the data vector that should be gathered or scattered. 3316 /// VariableMask - The mask is non-constant at compile time. 3317 /// Alignment - Alignment for one element. 3318 /// AddressSpace - pointer[s] address space. 3319 /// 3320 int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 3321 bool VariableMask, unsigned Alignment, 3322 unsigned AddressSpace) { 3323 unsigned VF = SrcVTy->getVectorNumElements(); 3324 3325 int MaskUnpackCost = 0; 3326 if (VariableMask) { 3327 VectorType *MaskTy = 3328 VectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 3329 MaskUnpackCost = getScalarizationOverhead(MaskTy, false, true); 3330 int ScalarCompareCost = 3331 getCmpSelInstrCost(Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), 3332 nullptr); 3333 int BranchCost = getCFInstrCost(Instruction::Br); 3334 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 3335 } 3336 3337 // The cost of the scalar loads/stores. 3338 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3339 MaybeAlign(Alignment), AddressSpace); 3340 3341 int InsertExtractCost = 0; 3342 if (Opcode == Instruction::Load) 3343 for (unsigned i = 0; i < VF; ++i) 3344 // Add the cost of inserting each scalar load into the vector 3345 InsertExtractCost += 3346 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 3347 else 3348 for (unsigned i = 0; i < VF; ++i) 3349 // Add the cost of extracting each element out of the data vector 3350 InsertExtractCost += 3351 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 3352 3353 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 3354 } 3355 3356 /// Calculate the cost of Gather / Scatter operation 3357 int X86TTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *SrcVTy, 3358 Value *Ptr, bool VariableMask, 3359 unsigned Alignment, 3360 const Instruction *I = nullptr) { 3361 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 3362 unsigned VF = SrcVTy->getVectorNumElements(); 3363 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 3364 if (!PtrTy && Ptr->getType()->isVectorTy()) 3365 PtrTy = dyn_cast<PointerType>(Ptr->getType()->getVectorElementType()); 3366 assert(PtrTy && "Unexpected type for Ptr argument"); 3367 unsigned AddressSpace = PtrTy->getAddressSpace(); 3368 3369 bool Scalarize = false; 3370 if ((Opcode == Instruction::Load && 3371 !isLegalMaskedGather(SrcVTy, MaybeAlign(Alignment))) || 3372 (Opcode == Instruction::Store && 3373 !isLegalMaskedScatter(SrcVTy, MaybeAlign(Alignment)))) 3374 Scalarize = true; 3375 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 3376 // Vector-4 of gather/scatter instruction does not exist on KNL. 3377 // We can extend it to 8 elements, but zeroing upper bits of 3378 // the mask vector will add more instructions. Right now we give the scalar 3379 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 3380 // is better in the VariableMask case. 3381 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 3382 Scalarize = true; 3383 3384 if (Scalarize) 3385 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 3386 AddressSpace); 3387 3388 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 3389 } 3390 3391 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 3392 TargetTransformInfo::LSRCost &C2) { 3393 // X86 specific here are "instruction number 1st priority". 3394 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 3395 C1.NumIVMuls, C1.NumBaseAdds, 3396 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 3397 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 3398 C2.NumIVMuls, C2.NumBaseAdds, 3399 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 3400 } 3401 3402 bool X86TTIImpl::canMacroFuseCmp() { 3403 return ST->hasMacroFusion() || ST->hasBranchFusion(); 3404 } 3405 3406 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, MaybeAlign Alignment) { 3407 if (!ST->hasAVX()) 3408 return false; 3409 3410 // The backend can't handle a single element vector. 3411 if (isa<VectorType>(DataTy) && DataTy->getVectorNumElements() == 1) 3412 return false; 3413 Type *ScalarTy = DataTy->getScalarType(); 3414 3415 if (ScalarTy->isPointerTy()) 3416 return true; 3417 3418 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 3419 return true; 3420 3421 if (!ScalarTy->isIntegerTy()) 3422 return false; 3423 3424 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 3425 return IntWidth == 32 || IntWidth == 64 || 3426 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 3427 } 3428 3429 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, MaybeAlign Alignment) { 3430 return isLegalMaskedLoad(DataType, Alignment); 3431 } 3432 3433 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 3434 unsigned DataSize = DL.getTypeStoreSize(DataType); 3435 // The only supported nontemporal loads are for aligned vectors of 16 or 32 3436 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 3437 // (the equivalent stores only require AVX). 3438 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 3439 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 3440 3441 return false; 3442 } 3443 3444 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 3445 unsigned DataSize = DL.getTypeStoreSize(DataType); 3446 3447 // SSE4A supports nontemporal stores of float and double at arbitrary 3448 // alignment. 3449 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 3450 return true; 3451 3452 // Besides the SSE4A subtarget exception above, only aligned stores are 3453 // available nontemporaly on any other subtarget. And only stores with a size 3454 // of 4..32 bytes (powers of 2, only) are permitted. 3455 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 3456 !isPowerOf2_32(DataSize)) 3457 return false; 3458 3459 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 3460 // loads require AVX2). 3461 if (DataSize == 32) 3462 return ST->hasAVX(); 3463 else if (DataSize == 16) 3464 return ST->hasSSE1(); 3465 return true; 3466 } 3467 3468 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 3469 if (!isa<VectorType>(DataTy)) 3470 return false; 3471 3472 if (!ST->hasAVX512()) 3473 return false; 3474 3475 // The backend can't handle a single element vector. 3476 if (DataTy->getVectorNumElements() == 1) 3477 return false; 3478 3479 Type *ScalarTy = DataTy->getVectorElementType(); 3480 3481 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 3482 return true; 3483 3484 if (!ScalarTy->isIntegerTy()) 3485 return false; 3486 3487 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 3488 return IntWidth == 32 || IntWidth == 64 || 3489 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 3490 } 3491 3492 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 3493 return isLegalMaskedExpandLoad(DataTy); 3494 } 3495 3496 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, MaybeAlign Alignment) { 3497 // Some CPUs have better gather performance than others. 3498 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 3499 // enable gather with a -march. 3500 if (!(ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()))) 3501 return false; 3502 3503 // This function is called now in two cases: from the Loop Vectorizer 3504 // and from the Scalarizer. 3505 // When the Loop Vectorizer asks about legality of the feature, 3506 // the vectorization factor is not calculated yet. The Loop Vectorizer 3507 // sends a scalar type and the decision is based on the width of the 3508 // scalar element. 3509 // Later on, the cost model will estimate usage this intrinsic based on 3510 // the vector type. 3511 // The Scalarizer asks again about legality. It sends a vector type. 3512 // In this case we can reject non-power-of-2 vectors. 3513 // We also reject single element vectors as the type legalizer can't 3514 // scalarize it. 3515 if (isa<VectorType>(DataTy)) { 3516 unsigned NumElts = DataTy->getVectorNumElements(); 3517 if (NumElts == 1 || !isPowerOf2_32(NumElts)) 3518 return false; 3519 } 3520 Type *ScalarTy = DataTy->getScalarType(); 3521 if (ScalarTy->isPointerTy()) 3522 return true; 3523 3524 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 3525 return true; 3526 3527 if (!ScalarTy->isIntegerTy()) 3528 return false; 3529 3530 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 3531 return IntWidth == 32 || IntWidth == 64; 3532 } 3533 3534 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, MaybeAlign Alignment) { 3535 // AVX2 doesn't support scatter 3536 if (!ST->hasAVX512()) 3537 return false; 3538 return isLegalMaskedGather(DataType, Alignment); 3539 } 3540 3541 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 3542 EVT VT = TLI->getValueType(DL, DataType); 3543 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 3544 } 3545 3546 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 3547 return false; 3548 } 3549 3550 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 3551 const Function *Callee) const { 3552 const TargetMachine &TM = getTLI()->getTargetMachine(); 3553 3554 // Work this as a subsetting of subtarget features. 3555 const FeatureBitset &CallerBits = 3556 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 3557 const FeatureBitset &CalleeBits = 3558 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 3559 3560 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 3561 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 3562 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 3563 } 3564 3565 bool X86TTIImpl::areFunctionArgsABICompatible( 3566 const Function *Caller, const Function *Callee, 3567 SmallPtrSetImpl<Argument *> &Args) const { 3568 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args)) 3569 return false; 3570 3571 // If we get here, we know the target features match. If one function 3572 // considers 512-bit vectors legal and the other does not, consider them 3573 // incompatible. 3574 // FIXME Look at the arguments and only consider 512 bit or larger vectors? 3575 const TargetMachine &TM = getTLI()->getTargetMachine(); 3576 3577 return TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 3578 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs(); 3579 } 3580 3581 X86TTIImpl::TTI::MemCmpExpansionOptions 3582 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 3583 TTI::MemCmpExpansionOptions Options; 3584 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 3585 Options.NumLoadsPerBlock = 2; 3586 if (IsZeroCmp) { 3587 // Only enable vector loads for equality comparison. Right now the vector 3588 // version is not as fast for three way compare (see #33329). 3589 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 3590 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 3591 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 3592 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 3593 // All GPR and vector loads can be unaligned. 3594 Options.AllowOverlappingLoads = true; 3595 } 3596 if (ST->is64Bit()) { 3597 Options.LoadSizes.push_back(8); 3598 } 3599 Options.LoadSizes.push_back(4); 3600 Options.LoadSizes.push_back(2); 3601 Options.LoadSizes.push_back(1); 3602 return Options; 3603 } 3604 3605 bool X86TTIImpl::enableInterleavedAccessVectorization() { 3606 // TODO: We expect this to be beneficial regardless of arch, 3607 // but there are currently some unexplained performance artifacts on Atom. 3608 // As a temporary solution, disable on Atom. 3609 return !(ST->isAtom()); 3610 } 3611 3612 // Get estimation for interleaved load/store operations for AVX2. 3613 // \p Factor is the interleaved-access factor (stride) - number of 3614 // (interleaved) elements in the group. 3615 // \p Indices contains the indices for a strided load: when the 3616 // interleaved load has gaps they indicate which elements are used. 3617 // If Indices is empty (or if the number of indices is equal to the size 3618 // of the interleaved-access as given in \p Factor) the access has no gaps. 3619 // 3620 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 3621 // computing the cost using a generic formula as a function of generic 3622 // shuffles. We therefore use a lookup table instead, filled according to 3623 // the instruction sequences that codegen currently generates. 3624 int X86TTIImpl::getInterleavedMemoryOpCostAVX2(unsigned Opcode, Type *VecTy, 3625 unsigned Factor, 3626 ArrayRef<unsigned> Indices, 3627 unsigned Alignment, 3628 unsigned AddressSpace, 3629 bool UseMaskForCond, 3630 bool UseMaskForGaps) { 3631 3632 if (UseMaskForCond || UseMaskForGaps) 3633 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3634 Alignment, AddressSpace, 3635 UseMaskForCond, UseMaskForGaps); 3636 3637 // We currently Support only fully-interleaved groups, with no gaps. 3638 // TODO: Support also strided loads (interleaved-groups with gaps). 3639 if (Indices.size() && Indices.size() != Factor) 3640 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3641 Alignment, AddressSpace); 3642 3643 // VecTy for interleave memop is <VF*Factor x Elt>. 3644 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 3645 // VecTy = <12 x i32>. 3646 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 3647 3648 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 3649 // the VF=2, while v2i128 is an unsupported MVT vector type 3650 // (see MachineValueType.h::getVectorVT()). 3651 if (!LegalVT.isVector()) 3652 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3653 Alignment, AddressSpace); 3654 3655 unsigned VF = VecTy->getVectorNumElements() / Factor; 3656 Type *ScalarTy = VecTy->getVectorElementType(); 3657 3658 // Calculate the number of memory operations (NumOfMemOps), required 3659 // for load/store the VecTy. 3660 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 3661 unsigned LegalVTSize = LegalVT.getStoreSize(); 3662 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 3663 3664 // Get the cost of one memory operation. 3665 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(), 3666 LegalVT.getVectorNumElements()); 3667 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 3668 MaybeAlign(Alignment), AddressSpace); 3669 3670 VectorType *VT = VectorType::get(ScalarTy, VF); 3671 EVT ETy = TLI->getValueType(DL, VT); 3672 if (!ETy.isSimple()) 3673 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3674 Alignment, AddressSpace); 3675 3676 // TODO: Complete for other data-types and strides. 3677 // Each combination of Stride, ElementTy and VF results in a different 3678 // sequence; The cost tables are therefore accessed with: 3679 // Factor (stride) and VectorType=VFxElemType. 3680 // The Cost accounts only for the shuffle sequence; 3681 // The cost of the loads/stores is accounted for separately. 3682 // 3683 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 3684 { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64 3685 { 2, MVT::v4f64, 6 }, //(load 8f64 and) deinterleave into 2 x 4f64 3686 3687 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8 3688 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8 3689 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8 3690 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8 3691 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8 3692 { 3, MVT::v8f32, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32 3693 3694 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8 3695 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8 3696 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8 3697 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8 3698 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8 3699 3700 { 8, MVT::v8f32, 40 } //(load 64f32 and)deinterleave into 8 x 8f32 3701 }; 3702 3703 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 3704 { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store) 3705 { 2, MVT::v4f64, 6 }, //interleave into 2 x 4f64 into 8f64 (and store) 3706 3707 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store) 3708 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store) 3709 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store) 3710 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store) 3711 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store) 3712 3713 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store) 3714 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store) 3715 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store) 3716 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store) 3717 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store) 3718 }; 3719 3720 if (Opcode == Instruction::Load) { 3721 if (const auto *Entry = 3722 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 3723 return NumOfMemOps * MemOpCost + Entry->Cost; 3724 } else { 3725 assert(Opcode == Instruction::Store && 3726 "Expected Store Instruction at this point"); 3727 if (const auto *Entry = 3728 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 3729 return NumOfMemOps * MemOpCost + Entry->Cost; 3730 } 3731 3732 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3733 Alignment, AddressSpace); 3734 } 3735 3736 // Get estimation for interleaved load/store operations and strided load. 3737 // \p Indices contains indices for strided load. 3738 // \p Factor - the factor of interleaving. 3739 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 3740 int X86TTIImpl::getInterleavedMemoryOpCostAVX512(unsigned Opcode, Type *VecTy, 3741 unsigned Factor, 3742 ArrayRef<unsigned> Indices, 3743 unsigned Alignment, 3744 unsigned AddressSpace, 3745 bool UseMaskForCond, 3746 bool UseMaskForGaps) { 3747 3748 if (UseMaskForCond || UseMaskForGaps) 3749 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3750 Alignment, AddressSpace, 3751 UseMaskForCond, UseMaskForGaps); 3752 3753 // VecTy for interleave memop is <VF*Factor x Elt>. 3754 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 3755 // VecTy = <12 x i32>. 3756 3757 // Calculate the number of memory operations (NumOfMemOps), required 3758 // for load/store the VecTy. 3759 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 3760 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 3761 unsigned LegalVTSize = LegalVT.getStoreSize(); 3762 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 3763 3764 // Get the cost of one memory operation. 3765 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(), 3766 LegalVT.getVectorNumElements()); 3767 unsigned MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, 3768 MaybeAlign(Alignment), AddressSpace); 3769 3770 unsigned VF = VecTy->getVectorNumElements() / Factor; 3771 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 3772 3773 if (Opcode == Instruction::Load) { 3774 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 3775 // contain the cost of the optimized shuffle sequence that the 3776 // X86InterleavedAccess pass will generate. 3777 // The cost of loads and stores are computed separately from the table. 3778 3779 // X86InterleavedAccess support only the following interleaved-access group. 3780 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 3781 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 3782 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 3783 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 3784 }; 3785 3786 if (const auto *Entry = 3787 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 3788 return NumOfMemOps * MemOpCost + Entry->Cost; 3789 //If an entry does not exist, fallback to the default implementation. 3790 3791 // Kind of shuffle depends on number of loaded values. 3792 // If we load the entire data in one register, we can use a 1-src shuffle. 3793 // Otherwise, we'll merge 2 sources in each operation. 3794 TTI::ShuffleKind ShuffleKind = 3795 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 3796 3797 unsigned ShuffleCost = 3798 getShuffleCost(ShuffleKind, SingleMemOpTy, 0, nullptr); 3799 3800 unsigned NumOfLoadsInInterleaveGrp = 3801 Indices.size() ? Indices.size() : Factor; 3802 Type *ResultTy = VectorType::get(VecTy->getVectorElementType(), 3803 VecTy->getVectorNumElements() / Factor); 3804 unsigned NumOfResults = 3805 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 3806 NumOfLoadsInInterleaveGrp; 3807 3808 // About a half of the loads may be folded in shuffles when we have only 3809 // one result. If we have more than one result, we do not fold loads at all. 3810 unsigned NumOfUnfoldedLoads = 3811 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 3812 3813 // Get a number of shuffle operations per result. 3814 unsigned NumOfShufflesPerResult = 3815 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 3816 3817 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 3818 // When we have more than one destination, we need additional instructions 3819 // to keep sources. 3820 unsigned NumOfMoves = 0; 3821 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 3822 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 3823 3824 int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 3825 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 3826 3827 return Cost; 3828 } 3829 3830 // Store. 3831 assert(Opcode == Instruction::Store && 3832 "Expected Store Instruction at this point"); 3833 // X86InterleavedAccess support only the following interleaved-access group. 3834 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 3835 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 3836 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 3837 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 3838 3839 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 3840 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 3841 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 3842 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 3843 }; 3844 3845 if (const auto *Entry = 3846 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 3847 return NumOfMemOps * MemOpCost + Entry->Cost; 3848 //If an entry does not exist, fallback to the default implementation. 3849 3850 // There is no strided stores meanwhile. And store can't be folded in 3851 // shuffle. 3852 unsigned NumOfSources = Factor; // The number of values to be merged. 3853 unsigned ShuffleCost = 3854 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, 0, nullptr); 3855 unsigned NumOfShufflesPerStore = NumOfSources - 1; 3856 3857 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 3858 // We need additional instructions to keep sources. 3859 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 3860 int Cost = NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 3861 NumOfMoves; 3862 return Cost; 3863 } 3864 3865 int X86TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, 3866 unsigned Factor, 3867 ArrayRef<unsigned> Indices, 3868 unsigned Alignment, 3869 unsigned AddressSpace, 3870 bool UseMaskForCond, 3871 bool UseMaskForGaps) { 3872 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 3873 Type *EltTy = VecTy->getVectorElementType(); 3874 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 3875 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 3876 return true; 3877 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 3878 return HasBW; 3879 return false; 3880 }; 3881 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 3882 return getInterleavedMemoryOpCostAVX512(Opcode, VecTy, Factor, Indices, 3883 Alignment, AddressSpace, 3884 UseMaskForCond, UseMaskForGaps); 3885 if (ST->hasAVX2()) 3886 return getInterleavedMemoryOpCostAVX2(Opcode, VecTy, Factor, Indices, 3887 Alignment, AddressSpace, 3888 UseMaskForCond, UseMaskForGaps); 3889 3890 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3891 Alignment, AddressSpace, 3892 UseMaskForCond, UseMaskForGaps); 3893 } 3894