1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// \file 10 /// This file implements a TargetTransformInfo analysis pass specific to the 11 /// X86 target machine. It uses the target's detailed information to provide 12 /// more precise answers to certain TTI queries, while letting the target 13 /// independent and default TTI implementations handle the rest. 14 /// 15 //===----------------------------------------------------------------------===// 16 /// About Cost Model numbers used below it's necessary to say the following: 17 /// the numbers correspond to some "generic" X86 CPU instead of usage of 18 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 19 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 20 /// the lookups below the cost is based on Nehalem as that was the first CPU 21 /// to support that feature level and thus has most likely the worst case cost. 22 /// Some examples of other technologies/CPUs: 23 /// SSE 3 - Pentium4 / Athlon64 24 /// SSE 4.1 - Penryn 25 /// SSE 4.2 - Nehalem 26 /// AVX - Sandy Bridge 27 /// AVX2 - Haswell 28 /// AVX-512 - Xeon Phi / Skylake 29 /// And some examples of instruction target dependent costs (latency) 30 /// divss sqrtss rsqrtss 31 /// AMD K7 11-16 19 3 32 /// Piledriver 9-24 13-15 5 33 /// Jaguar 14 16 2 34 /// Pentium II,III 18 30 2 35 /// Nehalem 7-14 7-18 3 36 /// Haswell 10-13 11 5 37 /// TODO: Develop and implement the target dependent cost model and 38 /// specialize cost numbers for different Cost Model Targets such as throughput, 39 /// code size, latency and uop count. 40 //===----------------------------------------------------------------------===// 41 42 #include "X86TargetTransformInfo.h" 43 #include "llvm/Analysis/TargetTransformInfo.h" 44 #include "llvm/CodeGen/BasicTTIImpl.h" 45 #include "llvm/CodeGen/CostTable.h" 46 #include "llvm/CodeGen/TargetLowering.h" 47 #include "llvm/IR/IntrinsicInst.h" 48 #include "llvm/Support/Debug.h" 49 50 using namespace llvm; 51 52 #define DEBUG_TYPE "x86tti" 53 54 //===----------------------------------------------------------------------===// 55 // 56 // X86 cost model. 57 // 58 //===----------------------------------------------------------------------===// 59 60 TargetTransformInfo::PopcntSupportKind 61 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 62 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 63 // TODO: Currently the __builtin_popcount() implementation using SSE3 64 // instructions is inefficient. Once the problem is fixed, we should 65 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 66 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 67 } 68 69 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 70 TargetTransformInfo::CacheLevel Level) const { 71 switch (Level) { 72 case TargetTransformInfo::CacheLevel::L1D: 73 // - Penryn 74 // - Nehalem 75 // - Westmere 76 // - Sandy Bridge 77 // - Ivy Bridge 78 // - Haswell 79 // - Broadwell 80 // - Skylake 81 // - Kabylake 82 return 32 * 1024; // 32 KByte 83 case TargetTransformInfo::CacheLevel::L2D: 84 // - Penryn 85 // - Nehalem 86 // - Westmere 87 // - Sandy Bridge 88 // - Ivy Bridge 89 // - Haswell 90 // - Broadwell 91 // - Skylake 92 // - Kabylake 93 return 256 * 1024; // 256 KByte 94 } 95 96 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 97 } 98 99 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 100 TargetTransformInfo::CacheLevel Level) const { 101 // - Penryn 102 // - Nehalem 103 // - Westmere 104 // - Sandy Bridge 105 // - Ivy Bridge 106 // - Haswell 107 // - Broadwell 108 // - Skylake 109 // - Kabylake 110 switch (Level) { 111 case TargetTransformInfo::CacheLevel::L1D: 112 LLVM_FALLTHROUGH; 113 case TargetTransformInfo::CacheLevel::L2D: 114 return 8; 115 } 116 117 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 118 } 119 120 unsigned X86TTIImpl::getNumberOfRegisters(bool Vector) { 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const { 133 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 134 if (Vector) { 135 if (ST->hasAVX512() && PreferVectorWidth >= 512) 136 return 512; 137 if (ST->hasAVX() && PreferVectorWidth >= 256) 138 return 256; 139 if (ST->hasSSE1() && PreferVectorWidth >= 128) 140 return 128; 141 return 0; 142 } 143 144 if (ST->is64Bit()) 145 return 64; 146 147 return 32; 148 } 149 150 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 151 return getRegisterBitWidth(true); 152 } 153 154 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 155 // If the loop will not be vectorized, don't interleave the loop. 156 // Let regular unroll to unroll the loop, which saves the overflow 157 // check and memory check cost. 158 if (VF == 1) 159 return 1; 160 161 if (ST->isAtom()) 162 return 1; 163 164 // Sandybridge and Haswell have multiple execution ports and pipelined 165 // vector units. 166 if (ST->hasAVX()) 167 return 4; 168 169 return 2; 170 } 171 172 int X86TTIImpl::getArithmeticInstrCost( 173 unsigned Opcode, Type *Ty, 174 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 175 TTI::OperandValueProperties Opd1PropInfo, 176 TTI::OperandValueProperties Opd2PropInfo, 177 ArrayRef<const Value *> Args) { 178 // Legalize the type. 179 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 180 181 int ISD = TLI->InstructionOpcodeToISD(Opcode); 182 assert(ISD && "Invalid opcode"); 183 184 static const CostTblEntry GLMCostTable[] = { 185 { ISD::FDIV, MVT::f32, 18 }, // divss 186 { ISD::FDIV, MVT::v4f32, 35 }, // divps 187 { ISD::FDIV, MVT::f64, 33 }, // divsd 188 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 189 }; 190 191 if (ST->isGLM()) 192 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 193 LT.second)) 194 return LT.first * Entry->Cost; 195 196 static const CostTblEntry SLMCostTable[] = { 197 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 198 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 199 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. 200 { ISD::FMUL, MVT::f64, 2 }, // mulsd 201 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 202 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 203 { ISD::FDIV, MVT::f32, 17 }, // divss 204 { ISD::FDIV, MVT::v4f32, 39 }, // divps 205 { ISD::FDIV, MVT::f64, 32 }, // divsd 206 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 207 { ISD::FADD, MVT::v2f64, 2 }, // addpd 208 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 209 // v2i64/v4i64 mul is custom lowered as a series of long: 210 // multiplies(3), shifts(3) and adds(2) 211 // slm muldq version throughput is 2 and addq throughput 4 212 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 213 // 3X4 (addq throughput) = 17 214 { ISD::MUL, MVT::v2i64, 17 }, 215 // slm addq\subq throughput is 4 216 { ISD::ADD, MVT::v2i64, 4 }, 217 { ISD::SUB, MVT::v2i64, 4 }, 218 }; 219 220 if (ST->isSLM()) { 221 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 222 // Check if the operands can be shrinked into a smaller datatype. 223 bool Op1Signed = false; 224 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 225 bool Op2Signed = false; 226 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 227 228 bool signedMode = Op1Signed | Op2Signed; 229 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 230 231 if (OpMinSize <= 7) 232 return LT.first * 3; // pmullw/sext 233 if (!signedMode && OpMinSize <= 8) 234 return LT.first * 3; // pmullw/zext 235 if (OpMinSize <= 15) 236 return LT.first * 5; // pmullw/pmulhw/pshuf 237 if (!signedMode && OpMinSize <= 16) 238 return LT.first * 5; // pmullw/pmulhw/pshuf 239 } 240 241 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 242 LT.second)) { 243 return LT.first * Entry->Cost; 244 } 245 } 246 247 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 248 ISD == ISD::UREM) && 249 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 250 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 251 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 252 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 253 // On X86, vector signed division by constants power-of-two are 254 // normally expanded to the sequence SRA + SRL + ADD + SRA. 255 // The OperandValue properties may not be the same as that of the previous 256 // operation; conservatively assume OP_None. 257 int Cost = 258 2 * getArithmeticInstrCost(Instruction::AShr, Ty, Op1Info, Op2Info, 259 TargetTransformInfo::OP_None, 260 TargetTransformInfo::OP_None); 261 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 262 TargetTransformInfo::OP_None, 263 TargetTransformInfo::OP_None); 264 Cost += getArithmeticInstrCost(Instruction::Add, Ty, Op1Info, Op2Info, 265 TargetTransformInfo::OP_None, 266 TargetTransformInfo::OP_None); 267 268 if (ISD == ISD::SREM) { 269 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 270 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info); 271 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, Op1Info, Op2Info); 272 } 273 274 return Cost; 275 } 276 277 // Vector unsigned division/remainder will be simplified to shifts/masks. 278 if (ISD == ISD::UDIV) 279 return getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 280 TargetTransformInfo::OP_None, 281 TargetTransformInfo::OP_None); 282 283 if (ISD == ISD::UREM) 284 return getArithmeticInstrCost(Instruction::And, Ty, Op1Info, Op2Info, 285 TargetTransformInfo::OP_None, 286 TargetTransformInfo::OP_None); 287 } 288 289 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 290 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 291 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 292 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 293 }; 294 295 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 296 ST->hasBWI()) { 297 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 298 LT.second)) 299 return LT.first * Entry->Cost; 300 } 301 302 static const CostTblEntry AVX512UniformConstCostTable[] = { 303 { ISD::SRA, MVT::v2i64, 1 }, 304 { ISD::SRA, MVT::v4i64, 1 }, 305 { ISD::SRA, MVT::v8i64, 1 }, 306 }; 307 308 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 309 ST->hasAVX512()) { 310 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 311 LT.second)) 312 return LT.first * Entry->Cost; 313 } 314 315 static const CostTblEntry AVX2UniformConstCostTable[] = { 316 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 317 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 318 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 319 320 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 321 }; 322 323 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 324 ST->hasAVX2()) { 325 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 326 LT.second)) 327 return LT.first * Entry->Cost; 328 } 329 330 static const CostTblEntry SSE2UniformConstCostTable[] = { 331 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 332 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 333 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 334 335 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 336 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 337 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 338 }; 339 340 // XOP has faster vXi8 shifts. 341 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 342 ST->hasSSE2() && !ST->hasXOP()) { 343 if (const auto *Entry = 344 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 345 return LT.first * Entry->Cost; 346 } 347 348 static const CostTblEntry AVX512BWConstCostTable[] = { 349 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 350 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 351 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 352 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 353 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 354 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 355 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 356 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 357 }; 358 359 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 360 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 361 ST->hasBWI()) { 362 if (const auto *Entry = 363 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 364 return LT.first * Entry->Cost; 365 } 366 367 static const CostTblEntry AVX512ConstCostTable[] = { 368 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 369 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 370 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 371 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 372 }; 373 374 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 375 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 376 ST->hasAVX512()) { 377 if (const auto *Entry = 378 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 379 return LT.first * Entry->Cost; 380 } 381 382 static const CostTblEntry AVX2ConstCostTable[] = { 383 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 384 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 385 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 386 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 387 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 388 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 389 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 390 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 391 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 392 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 393 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 394 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 395 }; 396 397 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 398 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 399 ST->hasAVX2()) { 400 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 401 return LT.first * Entry->Cost; 402 } 403 404 static const CostTblEntry SSE2ConstCostTable[] = { 405 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 406 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 407 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 408 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 409 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 410 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 411 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 412 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 413 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 414 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 415 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 416 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 417 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 418 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 419 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 420 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 421 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 422 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 423 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 424 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 425 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 426 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 427 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 428 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 429 }; 430 431 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 432 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 433 ST->hasSSE2()) { 434 // pmuldq sequence. 435 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 436 return LT.first * 32; 437 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 438 return LT.first * 38; 439 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 440 return LT.first * 15; 441 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 442 return LT.first * 20; 443 444 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 445 return LT.first * Entry->Cost; 446 } 447 448 static const CostTblEntry AVX2UniformCostTable[] = { 449 // Uniform splats are cheaper for the following instructions. 450 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 451 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 452 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 453 }; 454 455 if (ST->hasAVX2() && 456 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 457 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 458 if (const auto *Entry = 459 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 460 return LT.first * Entry->Cost; 461 } 462 463 static const CostTblEntry SSE2UniformCostTable[] = { 464 // Uniform splats are cheaper for the following instructions. 465 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 466 { ISD::SHL, MVT::v4i32, 1 }, // pslld 467 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 468 469 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 470 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 471 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 472 473 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 474 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 475 }; 476 477 if (ST->hasSSE2() && 478 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 479 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 480 if (const auto *Entry = 481 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 482 return LT.first * Entry->Cost; 483 } 484 485 static const CostTblEntry AVX512DQCostTable[] = { 486 { ISD::MUL, MVT::v2i64, 1 }, 487 { ISD::MUL, MVT::v4i64, 1 }, 488 { ISD::MUL, MVT::v8i64, 1 } 489 }; 490 491 // Look for AVX512DQ lowering tricks for custom cases. 492 if (ST->hasDQI()) 493 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 494 return LT.first * Entry->Cost; 495 496 static const CostTblEntry AVX512BWCostTable[] = { 497 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 498 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 499 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 500 501 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 502 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 503 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 504 505 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 506 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 507 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 508 509 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 510 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 511 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 512 513 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence. 514 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence. 515 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence. 516 }; 517 518 // Look for AVX512BW lowering tricks for custom cases. 519 if (ST->hasBWI()) 520 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 521 return LT.first * Entry->Cost; 522 523 static const CostTblEntry AVX512CostTable[] = { 524 { ISD::SHL, MVT::v16i32, 1 }, 525 { ISD::SRL, MVT::v16i32, 1 }, 526 { ISD::SRA, MVT::v16i32, 1 }, 527 528 { ISD::SHL, MVT::v8i64, 1 }, 529 { ISD::SRL, MVT::v8i64, 1 }, 530 531 { ISD::SRA, MVT::v2i64, 1 }, 532 { ISD::SRA, MVT::v4i64, 1 }, 533 { ISD::SRA, MVT::v8i64, 1 }, 534 535 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence. 536 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence. 537 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 538 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 539 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 540 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add 541 542 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 543 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 544 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 545 546 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 547 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 548 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 549 }; 550 551 if (ST->hasAVX512()) 552 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 553 return LT.first * Entry->Cost; 554 555 static const CostTblEntry AVX2ShiftCostTable[] = { 556 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 557 // customize them to detect the cases where shift amount is a scalar one. 558 { ISD::SHL, MVT::v4i32, 1 }, 559 { ISD::SRL, MVT::v4i32, 1 }, 560 { ISD::SRA, MVT::v4i32, 1 }, 561 { ISD::SHL, MVT::v8i32, 1 }, 562 { ISD::SRL, MVT::v8i32, 1 }, 563 { ISD::SRA, MVT::v8i32, 1 }, 564 { ISD::SHL, MVT::v2i64, 1 }, 565 { ISD::SRL, MVT::v2i64, 1 }, 566 { ISD::SHL, MVT::v4i64, 1 }, 567 { ISD::SRL, MVT::v4i64, 1 }, 568 }; 569 570 // Look for AVX2 lowering tricks. 571 if (ST->hasAVX2()) { 572 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 573 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 574 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 575 // On AVX2, a packed v16i16 shift left by a constant build_vector 576 // is lowered into a vector multiply (vpmullw). 577 return getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info, 578 TargetTransformInfo::OP_None, 579 TargetTransformInfo::OP_None); 580 581 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 582 return LT.first * Entry->Cost; 583 } 584 585 static const CostTblEntry XOPShiftCostTable[] = { 586 // 128bit shifts take 1cy, but right shifts require negation beforehand. 587 { ISD::SHL, MVT::v16i8, 1 }, 588 { ISD::SRL, MVT::v16i8, 2 }, 589 { ISD::SRA, MVT::v16i8, 2 }, 590 { ISD::SHL, MVT::v8i16, 1 }, 591 { ISD::SRL, MVT::v8i16, 2 }, 592 { ISD::SRA, MVT::v8i16, 2 }, 593 { ISD::SHL, MVT::v4i32, 1 }, 594 { ISD::SRL, MVT::v4i32, 2 }, 595 { ISD::SRA, MVT::v4i32, 2 }, 596 { ISD::SHL, MVT::v2i64, 1 }, 597 { ISD::SRL, MVT::v2i64, 2 }, 598 { ISD::SRA, MVT::v2i64, 2 }, 599 // 256bit shifts require splitting if AVX2 didn't catch them above. 600 { ISD::SHL, MVT::v32i8, 2+2 }, 601 { ISD::SRL, MVT::v32i8, 4+2 }, 602 { ISD::SRA, MVT::v32i8, 4+2 }, 603 { ISD::SHL, MVT::v16i16, 2+2 }, 604 { ISD::SRL, MVT::v16i16, 4+2 }, 605 { ISD::SRA, MVT::v16i16, 4+2 }, 606 { ISD::SHL, MVT::v8i32, 2+2 }, 607 { ISD::SRL, MVT::v8i32, 4+2 }, 608 { ISD::SRA, MVT::v8i32, 4+2 }, 609 { ISD::SHL, MVT::v4i64, 2+2 }, 610 { ISD::SRL, MVT::v4i64, 4+2 }, 611 { ISD::SRA, MVT::v4i64, 4+2 }, 612 }; 613 614 // Look for XOP lowering tricks. 615 if (ST->hasXOP()) { 616 // If the right shift is constant then we'll fold the negation so 617 // it's as cheap as a left shift. 618 int ShiftISD = ISD; 619 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 620 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 621 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 622 ShiftISD = ISD::SHL; 623 if (const auto *Entry = 624 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 625 return LT.first * Entry->Cost; 626 } 627 628 static const CostTblEntry SSE2UniformShiftCostTable[] = { 629 // Uniform splats are cheaper for the following instructions. 630 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 631 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 632 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 633 634 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 635 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 636 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 637 638 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 639 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 640 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 641 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 642 }; 643 644 if (ST->hasSSE2() && 645 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 646 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 647 648 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 649 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 650 return LT.first * 4; // 2*psrad + shuffle. 651 652 if (const auto *Entry = 653 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 654 return LT.first * Entry->Cost; 655 } 656 657 if (ISD == ISD::SHL && 658 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 659 MVT VT = LT.second; 660 // Vector shift left by non uniform constant can be lowered 661 // into vector multiply. 662 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 663 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 664 ISD = ISD::MUL; 665 } 666 667 static const CostTblEntry AVX2CostTable[] = { 668 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. 669 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 670 671 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. 672 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 673 674 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. 675 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. 676 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. 677 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 678 679 { ISD::SUB, MVT::v32i8, 1 }, // psubb 680 { ISD::ADD, MVT::v32i8, 1 }, // paddb 681 { ISD::SUB, MVT::v16i16, 1 }, // psubw 682 { ISD::ADD, MVT::v16i16, 1 }, // paddw 683 { ISD::SUB, MVT::v8i32, 1 }, // psubd 684 { ISD::ADD, MVT::v8i32, 1 }, // paddd 685 { ISD::SUB, MVT::v4i64, 1 }, // psubq 686 { ISD::ADD, MVT::v4i64, 1 }, // paddq 687 688 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence. 689 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence. 690 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 691 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 692 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add 693 694 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 695 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 696 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 697 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 698 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 699 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 700 701 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 702 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 703 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 704 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 705 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 706 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 707 }; 708 709 // Look for AVX2 lowering tricks for custom cases. 710 if (ST->hasAVX2()) 711 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 712 return LT.first * Entry->Cost; 713 714 static const CostTblEntry AVX1CostTable[] = { 715 // We don't have to scalarize unsupported ops. We can issue two half-sized 716 // operations and we only need to extract the upper YMM half. 717 // Two ops + 1 extract + 1 insert = 4. 718 { ISD::MUL, MVT::v16i16, 4 }, 719 { ISD::MUL, MVT::v8i32, 4 }, 720 { ISD::SUB, MVT::v32i8, 4 }, 721 { ISD::ADD, MVT::v32i8, 4 }, 722 { ISD::SUB, MVT::v16i16, 4 }, 723 { ISD::ADD, MVT::v16i16, 4 }, 724 { ISD::SUB, MVT::v8i32, 4 }, 725 { ISD::ADD, MVT::v8i32, 4 }, 726 { ISD::SUB, MVT::v4i64, 4 }, 727 { ISD::ADD, MVT::v4i64, 4 }, 728 729 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 730 // are lowered as a series of long multiplies(3), shifts(3) and adds(2) 731 // Because we believe v4i64 to be a legal type, we must also include the 732 // extract+insert in the cost table. Therefore, the cost here is 18 733 // instead of 8. 734 { ISD::MUL, MVT::v4i64, 18 }, 735 736 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence. 737 738 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 739 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 740 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 741 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 742 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 743 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 744 }; 745 746 if (ST->hasAVX()) 747 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 748 return LT.first * Entry->Cost; 749 750 static const CostTblEntry SSE42CostTable[] = { 751 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 752 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 753 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 754 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 755 756 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 757 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 758 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 759 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 760 761 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 762 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 763 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 764 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 765 766 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 767 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 768 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 769 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 770 }; 771 772 if (ST->hasSSE42()) 773 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 774 return LT.first * Entry->Cost; 775 776 static const CostTblEntry SSE41CostTable[] = { 777 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 778 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split. 779 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 780 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 781 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 782 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split 783 784 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 785 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split. 786 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 787 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 788 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 789 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split. 790 791 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 792 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split. 793 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 794 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 795 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 796 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split. 797 798 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 799 }; 800 801 if (ST->hasSSE41()) 802 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 803 return LT.first * Entry->Cost; 804 805 static const CostTblEntry SSE2CostTable[] = { 806 // We don't correctly identify costs of casts because they are marked as 807 // custom. 808 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 809 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 810 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 811 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 812 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 813 814 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 815 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 816 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 817 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 818 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 819 820 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 821 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 822 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 823 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 824 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split. 825 826 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence. 827 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 828 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 829 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 830 831 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 832 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 833 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 834 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 835 }; 836 837 if (ST->hasSSE2()) 838 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 839 return LT.first * Entry->Cost; 840 841 static const CostTblEntry SSE1CostTable[] = { 842 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 843 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 844 }; 845 846 if (ST->hasSSE1()) 847 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 848 return LT.first * Entry->Cost; 849 850 // It is not a good idea to vectorize division. We have to scalarize it and 851 // in the process we will often end up having to spilling regular 852 // registers. The overhead of division is going to dominate most kernels 853 // anyways so try hard to prevent vectorization of division - it is 854 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 855 // to hide "20 cycles" for each lane. 856 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 857 ISD == ISD::UDIV || ISD == ISD::UREM)) { 858 int ScalarCost = getArithmeticInstrCost( 859 Opcode, Ty->getScalarType(), Op1Info, Op2Info, 860 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 861 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 862 } 863 864 // Fallback to the default implementation. 865 return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info); 866 } 867 868 int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, 869 Type *SubTp) { 870 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 871 // 64-bit packed integer vectors (v2i32) are promoted to type v2i64. 872 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp); 873 874 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 875 if (Kind == TTI::SK_Transpose) 876 Kind = TTI::SK_PermuteTwoSrc; 877 878 // For Broadcasts we are splatting the first element from the first input 879 // register, so only need to reference that input and all the output 880 // registers are the same. 881 if (Kind == TTI::SK_Broadcast) 882 LT.first = 1; 883 884 // Subvector extractions are free if they start at the beginning of a 885 // vector and cheap if the subvectors are aligned. 886 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 887 int NumElts = LT.second.getVectorNumElements(); 888 if ((Index % NumElts) == 0) 889 return 0; 890 std::pair<int, MVT> SubLT = TLI->getTypeLegalizationCost(DL, SubTp); 891 if (SubLT.second.isVector()) { 892 int NumSubElts = SubLT.second.getVectorNumElements(); 893 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 894 return SubLT.first; 895 } 896 } 897 898 // We are going to permute multiple sources and the result will be in multiple 899 // destinations. Providing an accurate cost only for splits where the element 900 // type remains the same. 901 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 902 MVT LegalVT = LT.second; 903 if (LegalVT.isVector() && 904 LegalVT.getVectorElementType().getSizeInBits() == 905 Tp->getVectorElementType()->getPrimitiveSizeInBits() && 906 LegalVT.getVectorNumElements() < Tp->getVectorNumElements()) { 907 908 unsigned VecTySize = DL.getTypeStoreSize(Tp); 909 unsigned LegalVTSize = LegalVT.getStoreSize(); 910 // Number of source vectors after legalization: 911 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 912 // Number of destination vectors after legalization: 913 unsigned NumOfDests = LT.first; 914 915 Type *SingleOpTy = VectorType::get(Tp->getVectorElementType(), 916 LegalVT.getVectorNumElements()); 917 918 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 919 return NumOfShuffles * 920 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 0, nullptr); 921 } 922 923 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 924 } 925 926 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 927 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 928 // We assume that source and destination have the same vector type. 929 int NumOfDests = LT.first; 930 int NumOfShufflesPerDest = LT.first * 2 - 1; 931 LT.first = NumOfDests * NumOfShufflesPerDest; 932 } 933 934 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 935 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 936 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 937 938 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 939 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 940 941 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 1}, // vpermt2b 942 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 1}, // vpermt2b 943 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1} // vpermt2b 944 }; 945 946 if (ST->hasVBMI()) 947 if (const auto *Entry = 948 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 949 return LT.first * Entry->Cost; 950 951 static const CostTblEntry AVX512BWShuffleTbl[] = { 952 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 953 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 954 955 {TTI::SK_Reverse, MVT::v32i16, 1}, // vpermw 956 {TTI::SK_Reverse, MVT::v16i16, 1}, // vpermw 957 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 958 959 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 1}, // vpermw 960 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 1}, // vpermw 961 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // vpermw 962 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 963 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 3}, // vpermw + zext/trunc 964 965 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 1}, // vpermt2w 966 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 1}, // vpermt2w 967 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpermt2w 968 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 3}, // zext + vpermt2w + trunc 969 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 970 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3} // zext + vpermt2w + trunc 971 }; 972 973 if (ST->hasBWI()) 974 if (const auto *Entry = 975 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 976 return LT.first * Entry->Cost; 977 978 static const CostTblEntry AVX512ShuffleTbl[] = { 979 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 980 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 981 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 982 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 983 984 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 985 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 986 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 987 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 988 989 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 990 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 991 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 992 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 993 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 994 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 995 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 996 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 997 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 998 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 999 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1000 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1001 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1002 1003 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1004 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1005 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1006 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1007 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1008 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1009 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1010 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1011 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1012 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1013 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1014 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1} // vpermt2d 1015 }; 1016 1017 if (ST->hasAVX512()) 1018 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1019 return LT.first * Entry->Cost; 1020 1021 static const CostTblEntry AVX2ShuffleTbl[] = { 1022 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1023 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1024 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1025 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1026 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1027 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1028 1029 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1030 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1031 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1032 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1033 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1034 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1035 1036 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1037 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1038 1039 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1040 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1041 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1042 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1043 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1044 // + vpblendvb 1045 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1046 // + vpblendvb 1047 1048 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1049 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1050 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1051 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1052 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1053 // + vpblendvb 1054 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1055 // + vpblendvb 1056 }; 1057 1058 if (ST->hasAVX2()) 1059 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1060 return LT.first * Entry->Cost; 1061 1062 static const CostTblEntry XOPShuffleTbl[] = { 1063 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1064 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1065 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1066 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1067 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1068 // + vinsertf128 1069 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1070 // + vinsertf128 1071 1072 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1073 // + vinsertf128 1074 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1075 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1076 // + vinsertf128 1077 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1078 }; 1079 1080 if (ST->hasXOP()) 1081 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1082 return LT.first * Entry->Cost; 1083 1084 static const CostTblEntry AVX1ShuffleTbl[] = { 1085 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1086 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1087 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1088 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1089 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1090 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1091 1092 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1093 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1094 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1095 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1096 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1097 // + vinsertf128 1098 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1099 // + vinsertf128 1100 1101 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1102 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1103 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1104 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1105 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1106 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1107 1108 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1109 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1110 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1111 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1112 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1113 // + 2*por + vinsertf128 1114 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1115 // + 2*por + vinsertf128 1116 1117 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1118 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1119 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1120 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1121 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1122 // + 4*por + vinsertf128 1123 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1124 // + 4*por + vinsertf128 1125 }; 1126 1127 if (ST->hasAVX()) 1128 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1129 return LT.first * Entry->Cost; 1130 1131 static const CostTblEntry SSE41ShuffleTbl[] = { 1132 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1133 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1134 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1135 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1136 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1137 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1138 }; 1139 1140 if (ST->hasSSE41()) 1141 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1142 return LT.first * Entry->Cost; 1143 1144 static const CostTblEntry SSSE3ShuffleTbl[] = { 1145 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1146 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1147 1148 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1149 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1150 1151 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1152 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1153 1154 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1155 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1156 1157 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1158 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1159 }; 1160 1161 if (ST->hasSSSE3()) 1162 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1163 return LT.first * Entry->Cost; 1164 1165 static const CostTblEntry SSE2ShuffleTbl[] = { 1166 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1167 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1168 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1169 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1170 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1171 1172 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1173 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1174 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1175 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1176 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1177 // + 2*pshufd + 2*unpck + packus 1178 1179 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1180 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1181 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1182 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1183 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1184 1185 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1186 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1187 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1188 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1189 // + pshufd/unpck 1190 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1191 // + 2*pshufd + 2*unpck + 2*packus 1192 1193 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1194 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1195 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1196 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1197 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1198 }; 1199 1200 if (ST->hasSSE2()) 1201 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1202 return LT.first * Entry->Cost; 1203 1204 static const CostTblEntry SSE1ShuffleTbl[] = { 1205 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1206 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1207 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1208 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1209 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1210 }; 1211 1212 if (ST->hasSSE1()) 1213 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1214 return LT.first * Entry->Cost; 1215 1216 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 1217 } 1218 1219 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 1220 const Instruction *I) { 1221 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1222 assert(ISD && "Invalid opcode"); 1223 1224 // FIXME: Need a better design of the cost table to handle non-simple types of 1225 // potential massive combinations (elem_num x src_type x dst_type). 1226 1227 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1228 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1229 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1230 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1231 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1232 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1233 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1234 1235 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1236 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1237 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1238 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1239 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1240 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1241 1242 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1243 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1244 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1245 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1246 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1247 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1248 1249 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1250 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1251 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1252 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1253 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1254 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1255 }; 1256 1257 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1258 // 256-bit wide vectors. 1259 1260 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1261 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1262 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1263 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1264 1265 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 }, 1266 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 }, 1267 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 }, 1268 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 1269 1270 // v16i1 -> v16i32 - load + broadcast 1271 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1272 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1273 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1274 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1275 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1276 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1277 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1278 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1279 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1280 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1281 1282 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1283 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1284 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1285 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1286 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1287 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1288 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1289 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1290 1291 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1292 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1293 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1294 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1295 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1296 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1297 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1298 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1299 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1300 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1301 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1302 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1303 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1304 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1305 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1306 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1307 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1308 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1309 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1310 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1311 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1312 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1313 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1314 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1315 1316 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1317 1318 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1319 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1320 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1321 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1322 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 2 }, 1323 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 2 }, 1324 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1325 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 2 }, 1326 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 2 }, 1327 }; 1328 1329 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1330 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1331 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1332 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1333 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1334 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 1335 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 1336 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 1337 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 1338 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1339 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1340 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1341 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1342 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1343 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1344 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1345 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1346 1347 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 1348 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 1349 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1350 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 1351 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1352 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 }, 1353 1354 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1355 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1356 1357 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1358 }; 1359 1360 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1361 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1362 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1363 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1364 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1365 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 }, 1366 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1367 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 7 }, 1368 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1369 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1370 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1371 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 }, 1372 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1373 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1374 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1375 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1376 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1377 1378 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 1379 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1380 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1381 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1382 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 1383 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 }, 1384 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 }, 1385 1386 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1387 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1388 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1389 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1390 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1391 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1392 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1393 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1394 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1395 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1396 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1397 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1398 1399 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1400 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1401 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1402 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1403 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1404 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1405 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1406 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1407 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1408 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 }, 1409 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 1410 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1411 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 1412 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1413 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1414 // The generic code to compute the scalar overhead is currently broken. 1415 // Workaround this limitation by estimating the scalarization overhead 1416 // here. We have roughly 10 instructions per scalar element. 1417 // Multiply that by the vector width. 1418 // FIXME: remove that when PR19268 is fixed. 1419 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1420 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1421 1422 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 }, 1423 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 }, 1424 // This node is expanded into scalarized operations but BasicTTI is overly 1425 // optimistic estimating its cost. It computes 3 per element (one 1426 // vector-extract, one scalar conversion and one vector-insert). The 1427 // problem is that the inserts form a read-modify-write chain so latency 1428 // should be factored in too. Inflating the cost per element by 1. 1429 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, 1430 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 1431 1432 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 1433 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 1434 }; 1435 1436 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 1437 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1438 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1439 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1440 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1441 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1442 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1443 1444 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1445 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 }, 1446 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1447 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1448 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1449 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1450 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1451 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1452 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1453 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1454 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1455 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1456 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1457 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1458 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1459 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1460 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1461 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1462 1463 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, 1464 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 1465 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 1466 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 1467 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 1468 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 1469 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 1470 1471 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 1472 }; 1473 1474 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 1475 // These are somewhat magic numbers justified by looking at the output of 1476 // Intel's IACA, running some kernels and making sure when we take 1477 // legalization into account the throughput will be overestimated. 1478 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1479 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1480 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1481 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1482 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1483 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1484 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1485 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 1486 1487 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1488 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1489 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1490 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1491 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1492 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, 1493 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 }, 1494 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1495 1496 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 3 }, 1497 1498 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 }, 1499 1500 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1501 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 1502 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 1503 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 1504 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1505 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 1506 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1507 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 1508 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1509 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1510 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1511 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1512 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 1513 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 1514 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1515 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 1516 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1517 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 1518 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1519 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1520 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 1521 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 1522 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1523 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 1524 1525 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 4 }, 1526 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, 1527 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 1528 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 1529 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 1530 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1531 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 1532 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1533 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 1534 }; 1535 1536 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 1537 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst); 1538 1539 if (ST->hasSSE2() && !ST->hasAVX()) { 1540 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1541 LTDest.second, LTSrc.second)) 1542 return LTSrc.first * Entry->Cost; 1543 } 1544 1545 EVT SrcTy = TLI->getValueType(DL, Src); 1546 EVT DstTy = TLI->getValueType(DL, Dst); 1547 1548 // The function getSimpleVT only handles simple value types. 1549 if (!SrcTy.isSimple() || !DstTy.isSimple()) 1550 return BaseT::getCastInstrCost(Opcode, Dst, Src); 1551 1552 if (ST->hasDQI()) 1553 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 1554 DstTy.getSimpleVT(), 1555 SrcTy.getSimpleVT())) 1556 return Entry->Cost; 1557 1558 if (ST->hasAVX512()) 1559 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 1560 DstTy.getSimpleVT(), 1561 SrcTy.getSimpleVT())) 1562 return Entry->Cost; 1563 1564 if (ST->hasAVX2()) { 1565 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 1566 DstTy.getSimpleVT(), 1567 SrcTy.getSimpleVT())) 1568 return Entry->Cost; 1569 } 1570 1571 if (ST->hasAVX()) { 1572 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 1573 DstTy.getSimpleVT(), 1574 SrcTy.getSimpleVT())) 1575 return Entry->Cost; 1576 } 1577 1578 if (ST->hasSSE41()) { 1579 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 1580 DstTy.getSimpleVT(), 1581 SrcTy.getSimpleVT())) 1582 return Entry->Cost; 1583 } 1584 1585 if (ST->hasSSE2()) { 1586 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1587 DstTy.getSimpleVT(), 1588 SrcTy.getSimpleVT())) 1589 return Entry->Cost; 1590 } 1591 1592 return BaseT::getCastInstrCost(Opcode, Dst, Src, I); 1593 } 1594 1595 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 1596 const Instruction *I) { 1597 // Legalize the type. 1598 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 1599 1600 MVT MTy = LT.second; 1601 1602 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1603 assert(ISD && "Invalid opcode"); 1604 1605 static const CostTblEntry SSE2CostTbl[] = { 1606 { ISD::SETCC, MVT::v2i64, 8 }, 1607 { ISD::SETCC, MVT::v4i32, 1 }, 1608 { ISD::SETCC, MVT::v8i16, 1 }, 1609 { ISD::SETCC, MVT::v16i8, 1 }, 1610 }; 1611 1612 static const CostTblEntry SSE42CostTbl[] = { 1613 { ISD::SETCC, MVT::v2f64, 1 }, 1614 { ISD::SETCC, MVT::v4f32, 1 }, 1615 { ISD::SETCC, MVT::v2i64, 1 }, 1616 }; 1617 1618 static const CostTblEntry AVX1CostTbl[] = { 1619 { ISD::SETCC, MVT::v4f64, 1 }, 1620 { ISD::SETCC, MVT::v8f32, 1 }, 1621 // AVX1 does not support 8-wide integer compare. 1622 { ISD::SETCC, MVT::v4i64, 4 }, 1623 { ISD::SETCC, MVT::v8i32, 4 }, 1624 { ISD::SETCC, MVT::v16i16, 4 }, 1625 { ISD::SETCC, MVT::v32i8, 4 }, 1626 }; 1627 1628 static const CostTblEntry AVX2CostTbl[] = { 1629 { ISD::SETCC, MVT::v4i64, 1 }, 1630 { ISD::SETCC, MVT::v8i32, 1 }, 1631 { ISD::SETCC, MVT::v16i16, 1 }, 1632 { ISD::SETCC, MVT::v32i8, 1 }, 1633 }; 1634 1635 static const CostTblEntry AVX512CostTbl[] = { 1636 { ISD::SETCC, MVT::v8i64, 1 }, 1637 { ISD::SETCC, MVT::v16i32, 1 }, 1638 { ISD::SETCC, MVT::v8f64, 1 }, 1639 { ISD::SETCC, MVT::v16f32, 1 }, 1640 }; 1641 1642 static const CostTblEntry AVX512BWCostTbl[] = { 1643 { ISD::SETCC, MVT::v32i16, 1 }, 1644 { ISD::SETCC, MVT::v64i8, 1 }, 1645 }; 1646 1647 if (ST->hasBWI()) 1648 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 1649 return LT.first * Entry->Cost; 1650 1651 if (ST->hasAVX512()) 1652 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 1653 return LT.first * Entry->Cost; 1654 1655 if (ST->hasAVX2()) 1656 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 1657 return LT.first * Entry->Cost; 1658 1659 if (ST->hasAVX()) 1660 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 1661 return LT.first * Entry->Cost; 1662 1663 if (ST->hasSSE42()) 1664 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 1665 return LT.first * Entry->Cost; 1666 1667 if (ST->hasSSE2()) 1668 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 1669 return LT.first * Entry->Cost; 1670 1671 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I); 1672 } 1673 1674 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 1675 1676 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 1677 ArrayRef<Type *> Tys, FastMathFlags FMF, 1678 unsigned ScalarizationCostPassed) { 1679 // Costs should match the codegen from: 1680 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 1681 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 1682 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 1683 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 1684 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 1685 static const CostTblEntry AVX512CDCostTbl[] = { 1686 { ISD::CTLZ, MVT::v8i64, 1 }, 1687 { ISD::CTLZ, MVT::v16i32, 1 }, 1688 { ISD::CTLZ, MVT::v32i16, 8 }, 1689 { ISD::CTLZ, MVT::v64i8, 20 }, 1690 { ISD::CTLZ, MVT::v4i64, 1 }, 1691 { ISD::CTLZ, MVT::v8i32, 1 }, 1692 { ISD::CTLZ, MVT::v16i16, 4 }, 1693 { ISD::CTLZ, MVT::v32i8, 10 }, 1694 { ISD::CTLZ, MVT::v2i64, 1 }, 1695 { ISD::CTLZ, MVT::v4i32, 1 }, 1696 { ISD::CTLZ, MVT::v8i16, 4 }, 1697 { ISD::CTLZ, MVT::v16i8, 4 }, 1698 }; 1699 static const CostTblEntry AVX512BWCostTbl[] = { 1700 { ISD::BITREVERSE, MVT::v8i64, 5 }, 1701 { ISD::BITREVERSE, MVT::v16i32, 5 }, 1702 { ISD::BITREVERSE, MVT::v32i16, 5 }, 1703 { ISD::BITREVERSE, MVT::v64i8, 5 }, 1704 { ISD::CTLZ, MVT::v8i64, 23 }, 1705 { ISD::CTLZ, MVT::v16i32, 22 }, 1706 { ISD::CTLZ, MVT::v32i16, 18 }, 1707 { ISD::CTLZ, MVT::v64i8, 17 }, 1708 { ISD::CTPOP, MVT::v8i64, 7 }, 1709 { ISD::CTPOP, MVT::v16i32, 11 }, 1710 { ISD::CTPOP, MVT::v32i16, 9 }, 1711 { ISD::CTPOP, MVT::v64i8, 6 }, 1712 { ISD::CTTZ, MVT::v8i64, 10 }, 1713 { ISD::CTTZ, MVT::v16i32, 14 }, 1714 { ISD::CTTZ, MVT::v32i16, 12 }, 1715 { ISD::CTTZ, MVT::v64i8, 9 }, 1716 }; 1717 static const CostTblEntry AVX512CostTbl[] = { 1718 { ISD::BITREVERSE, MVT::v8i64, 36 }, 1719 { ISD::BITREVERSE, MVT::v16i32, 24 }, 1720 { ISD::CTLZ, MVT::v8i64, 29 }, 1721 { ISD::CTLZ, MVT::v16i32, 35 }, 1722 { ISD::CTPOP, MVT::v8i64, 16 }, 1723 { ISD::CTPOP, MVT::v16i32, 24 }, 1724 { ISD::CTTZ, MVT::v8i64, 20 }, 1725 { ISD::CTTZ, MVT::v16i32, 28 }, 1726 }; 1727 static const CostTblEntry XOPCostTbl[] = { 1728 { ISD::BITREVERSE, MVT::v4i64, 4 }, 1729 { ISD::BITREVERSE, MVT::v8i32, 4 }, 1730 { ISD::BITREVERSE, MVT::v16i16, 4 }, 1731 { ISD::BITREVERSE, MVT::v32i8, 4 }, 1732 { ISD::BITREVERSE, MVT::v2i64, 1 }, 1733 { ISD::BITREVERSE, MVT::v4i32, 1 }, 1734 { ISD::BITREVERSE, MVT::v8i16, 1 }, 1735 { ISD::BITREVERSE, MVT::v16i8, 1 }, 1736 { ISD::BITREVERSE, MVT::i64, 3 }, 1737 { ISD::BITREVERSE, MVT::i32, 3 }, 1738 { ISD::BITREVERSE, MVT::i16, 3 }, 1739 { ISD::BITREVERSE, MVT::i8, 3 } 1740 }; 1741 static const CostTblEntry AVX2CostTbl[] = { 1742 { ISD::BITREVERSE, MVT::v4i64, 5 }, 1743 { ISD::BITREVERSE, MVT::v8i32, 5 }, 1744 { ISD::BITREVERSE, MVT::v16i16, 5 }, 1745 { ISD::BITREVERSE, MVT::v32i8, 5 }, 1746 { ISD::BSWAP, MVT::v4i64, 1 }, 1747 { ISD::BSWAP, MVT::v8i32, 1 }, 1748 { ISD::BSWAP, MVT::v16i16, 1 }, 1749 { ISD::CTLZ, MVT::v4i64, 23 }, 1750 { ISD::CTLZ, MVT::v8i32, 18 }, 1751 { ISD::CTLZ, MVT::v16i16, 14 }, 1752 { ISD::CTLZ, MVT::v32i8, 9 }, 1753 { ISD::CTPOP, MVT::v4i64, 7 }, 1754 { ISD::CTPOP, MVT::v8i32, 11 }, 1755 { ISD::CTPOP, MVT::v16i16, 9 }, 1756 { ISD::CTPOP, MVT::v32i8, 6 }, 1757 { ISD::CTTZ, MVT::v4i64, 10 }, 1758 { ISD::CTTZ, MVT::v8i32, 14 }, 1759 { ISD::CTTZ, MVT::v16i16, 12 }, 1760 { ISD::CTTZ, MVT::v32i8, 9 }, 1761 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 1762 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 1763 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 1764 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 1765 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 1766 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 1767 }; 1768 static const CostTblEntry AVX1CostTbl[] = { 1769 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 1770 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 1771 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 1772 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 1773 { ISD::BSWAP, MVT::v4i64, 4 }, 1774 { ISD::BSWAP, MVT::v8i32, 4 }, 1775 { ISD::BSWAP, MVT::v16i16, 4 }, 1776 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 1777 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 1778 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 1779 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 1780 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 1781 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 1782 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 1783 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 1784 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 1785 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 1786 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 1787 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 1788 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 1789 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 1790 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 1791 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 1792 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 1793 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 1794 }; 1795 static const CostTblEntry GLMCostTbl[] = { 1796 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 1797 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 1798 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 1799 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 1800 }; 1801 static const CostTblEntry SLMCostTbl[] = { 1802 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 1803 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 1804 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 1805 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 1806 }; 1807 static const CostTblEntry SSE42CostTbl[] = { 1808 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 1809 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 1810 }; 1811 static const CostTblEntry SSSE3CostTbl[] = { 1812 { ISD::BITREVERSE, MVT::v2i64, 5 }, 1813 { ISD::BITREVERSE, MVT::v4i32, 5 }, 1814 { ISD::BITREVERSE, MVT::v8i16, 5 }, 1815 { ISD::BITREVERSE, MVT::v16i8, 5 }, 1816 { ISD::BSWAP, MVT::v2i64, 1 }, 1817 { ISD::BSWAP, MVT::v4i32, 1 }, 1818 { ISD::BSWAP, MVT::v8i16, 1 }, 1819 { ISD::CTLZ, MVT::v2i64, 23 }, 1820 { ISD::CTLZ, MVT::v4i32, 18 }, 1821 { ISD::CTLZ, MVT::v8i16, 14 }, 1822 { ISD::CTLZ, MVT::v16i8, 9 }, 1823 { ISD::CTPOP, MVT::v2i64, 7 }, 1824 { ISD::CTPOP, MVT::v4i32, 11 }, 1825 { ISD::CTPOP, MVT::v8i16, 9 }, 1826 { ISD::CTPOP, MVT::v16i8, 6 }, 1827 { ISD::CTTZ, MVT::v2i64, 10 }, 1828 { ISD::CTTZ, MVT::v4i32, 14 }, 1829 { ISD::CTTZ, MVT::v8i16, 12 }, 1830 { ISD::CTTZ, MVT::v16i8, 9 } 1831 }; 1832 static const CostTblEntry SSE2CostTbl[] = { 1833 { ISD::BITREVERSE, MVT::v2i64, 29 }, 1834 { ISD::BITREVERSE, MVT::v4i32, 27 }, 1835 { ISD::BITREVERSE, MVT::v8i16, 27 }, 1836 { ISD::BITREVERSE, MVT::v16i8, 20 }, 1837 { ISD::BSWAP, MVT::v2i64, 7 }, 1838 { ISD::BSWAP, MVT::v4i32, 7 }, 1839 { ISD::BSWAP, MVT::v8i16, 7 }, 1840 { ISD::CTLZ, MVT::v2i64, 25 }, 1841 { ISD::CTLZ, MVT::v4i32, 26 }, 1842 { ISD::CTLZ, MVT::v8i16, 20 }, 1843 { ISD::CTLZ, MVT::v16i8, 17 }, 1844 { ISD::CTPOP, MVT::v2i64, 12 }, 1845 { ISD::CTPOP, MVT::v4i32, 15 }, 1846 { ISD::CTPOP, MVT::v8i16, 13 }, 1847 { ISD::CTPOP, MVT::v16i8, 10 }, 1848 { ISD::CTTZ, MVT::v2i64, 14 }, 1849 { ISD::CTTZ, MVT::v4i32, 18 }, 1850 { ISD::CTTZ, MVT::v8i16, 16 }, 1851 { ISD::CTTZ, MVT::v16i8, 13 }, 1852 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 1853 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 1854 }; 1855 static const CostTblEntry SSE1CostTbl[] = { 1856 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 1857 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 1858 }; 1859 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 1860 { ISD::BITREVERSE, MVT::i64, 14 } 1861 }; 1862 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 1863 { ISD::BITREVERSE, MVT::i32, 14 }, 1864 { ISD::BITREVERSE, MVT::i16, 14 }, 1865 { ISD::BITREVERSE, MVT::i8, 11 } 1866 }; 1867 1868 unsigned ISD = ISD::DELETED_NODE; 1869 switch (IID) { 1870 default: 1871 break; 1872 case Intrinsic::bitreverse: 1873 ISD = ISD::BITREVERSE; 1874 break; 1875 case Intrinsic::bswap: 1876 ISD = ISD::BSWAP; 1877 break; 1878 case Intrinsic::ctlz: 1879 ISD = ISD::CTLZ; 1880 break; 1881 case Intrinsic::ctpop: 1882 ISD = ISD::CTPOP; 1883 break; 1884 case Intrinsic::cttz: 1885 ISD = ISD::CTTZ; 1886 break; 1887 case Intrinsic::sqrt: 1888 ISD = ISD::FSQRT; 1889 break; 1890 } 1891 1892 // Legalize the type. 1893 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 1894 MVT MTy = LT.second; 1895 1896 // Attempt to lookup cost. 1897 if (ST->isGLM()) 1898 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 1899 return LT.first * Entry->Cost; 1900 1901 if (ST->isSLM()) 1902 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 1903 return LT.first * Entry->Cost; 1904 1905 if (ST->hasCDI()) 1906 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 1907 return LT.first * Entry->Cost; 1908 1909 if (ST->hasBWI()) 1910 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 1911 return LT.first * Entry->Cost; 1912 1913 if (ST->hasAVX512()) 1914 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 1915 return LT.first * Entry->Cost; 1916 1917 if (ST->hasXOP()) 1918 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 1919 return LT.first * Entry->Cost; 1920 1921 if (ST->hasAVX2()) 1922 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 1923 return LT.first * Entry->Cost; 1924 1925 if (ST->hasAVX()) 1926 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 1927 return LT.first * Entry->Cost; 1928 1929 if (ST->hasSSE42()) 1930 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 1931 return LT.first * Entry->Cost; 1932 1933 if (ST->hasSSSE3()) 1934 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 1935 return LT.first * Entry->Cost; 1936 1937 if (ST->hasSSE2()) 1938 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 1939 return LT.first * Entry->Cost; 1940 1941 if (ST->hasSSE1()) 1942 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 1943 return LT.first * Entry->Cost; 1944 1945 if (ST->is64Bit()) 1946 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 1947 return LT.first * Entry->Cost; 1948 1949 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 1950 return LT.first * Entry->Cost; 1951 1952 return BaseT::getIntrinsicInstrCost(IID, RetTy, Tys, FMF, ScalarizationCostPassed); 1953 } 1954 1955 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 1956 ArrayRef<Value *> Args, FastMathFlags FMF, 1957 unsigned VF) { 1958 static const CostTblEntry AVX512CostTbl[] = { 1959 { ISD::ROTL, MVT::v8i64, 1 }, 1960 { ISD::ROTL, MVT::v4i64, 1 }, 1961 { ISD::ROTL, MVT::v2i64, 1 }, 1962 { ISD::ROTL, MVT::v16i32, 1 }, 1963 { ISD::ROTL, MVT::v8i32, 1 }, 1964 { ISD::ROTL, MVT::v4i32, 1 }, 1965 { ISD::ROTR, MVT::v8i64, 1 }, 1966 { ISD::ROTR, MVT::v4i64, 1 }, 1967 { ISD::ROTR, MVT::v2i64, 1 }, 1968 { ISD::ROTR, MVT::v16i32, 1 }, 1969 { ISD::ROTR, MVT::v8i32, 1 }, 1970 { ISD::ROTR, MVT::v4i32, 1 } 1971 }; 1972 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 1973 static const CostTblEntry XOPCostTbl[] = { 1974 { ISD::ROTL, MVT::v4i64, 4 }, 1975 { ISD::ROTL, MVT::v8i32, 4 }, 1976 { ISD::ROTL, MVT::v16i16, 4 }, 1977 { ISD::ROTL, MVT::v32i8, 4 }, 1978 { ISD::ROTL, MVT::v2i64, 1 }, 1979 { ISD::ROTL, MVT::v4i32, 1 }, 1980 { ISD::ROTL, MVT::v8i16, 1 }, 1981 { ISD::ROTL, MVT::v16i8, 1 }, 1982 { ISD::ROTR, MVT::v4i64, 6 }, 1983 { ISD::ROTR, MVT::v8i32, 6 }, 1984 { ISD::ROTR, MVT::v16i16, 6 }, 1985 { ISD::ROTR, MVT::v32i8, 6 }, 1986 { ISD::ROTR, MVT::v2i64, 2 }, 1987 { ISD::ROTR, MVT::v4i32, 2 }, 1988 { ISD::ROTR, MVT::v8i16, 2 }, 1989 { ISD::ROTR, MVT::v16i8, 2 } 1990 }; 1991 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 1992 { ISD::ROTL, MVT::i64, 1 }, 1993 { ISD::ROTR, MVT::i64, 1 }, 1994 { X86ISD::SHLD, MVT::i64, 4 } 1995 }; 1996 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 1997 { ISD::ROTL, MVT::i32, 1 }, 1998 { ISD::ROTL, MVT::i16, 1 }, 1999 { ISD::ROTL, MVT::i8, 1 }, 2000 { ISD::ROTR, MVT::i32, 1 }, 2001 { ISD::ROTR, MVT::i16, 1 }, 2002 { ISD::ROTR, MVT::i8, 1 }, 2003 { X86ISD::SHLD, MVT::i32, 4 }, 2004 { X86ISD::SHLD, MVT::i16, 4 }, 2005 { X86ISD::SHLD, MVT::i8, 4 } 2006 }; 2007 2008 unsigned ISD = ISD::DELETED_NODE; 2009 switch (IID) { 2010 default: 2011 break; 2012 case Intrinsic::fshl: 2013 ISD = X86ISD::SHLD; 2014 if (Args[0] == Args[1]) 2015 ISD = ISD::ROTL; 2016 break; 2017 case Intrinsic::fshr: 2018 // SHRD has same costs so don't duplicate. 2019 ISD = X86ISD::SHLD; 2020 if (Args[0] == Args[1]) 2021 ISD = ISD::ROTR; 2022 break; 2023 } 2024 2025 // Legalize the type. 2026 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 2027 MVT MTy = LT.second; 2028 2029 // Attempt to lookup cost. 2030 if (ST->hasAVX512()) 2031 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2032 return LT.first * Entry->Cost; 2033 2034 if (ST->hasXOP()) 2035 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2036 return LT.first * Entry->Cost; 2037 2038 if (ST->is64Bit()) 2039 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2040 return LT.first * Entry->Cost; 2041 2042 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2043 return LT.first * Entry->Cost; 2044 2045 return BaseT::getIntrinsicInstrCost(IID, RetTy, Args, FMF, VF); 2046 } 2047 2048 int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { 2049 assert(Val->isVectorTy() && "This must be a vector type"); 2050 2051 Type *ScalarType = Val->getScalarType(); 2052 2053 if (Index != -1U) { 2054 // Legalize the type. 2055 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 2056 2057 // This type is legalized to a scalar type. 2058 if (!LT.second.isVector()) 2059 return 0; 2060 2061 // The type may be split. Normalize the index to the new type. 2062 unsigned Width = LT.second.getVectorNumElements(); 2063 Index = Index % Width; 2064 2065 // Floating point scalars are already located in index #0. 2066 if (ScalarType->isFloatingPointTy() && Index == 0) 2067 return 0; 2068 } 2069 2070 // Add to the base cost if we know that the extracted element of a vector is 2071 // destined to be moved to and used in the integer register file. 2072 int RegisterFileMoveCost = 0; 2073 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 2074 RegisterFileMoveCost = 1; 2075 2076 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 2077 } 2078 2079 int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, 2080 unsigned AddressSpace, const Instruction *I) { 2081 // Handle non-power-of-two vectors such as <3 x float> 2082 if (VectorType *VTy = dyn_cast<VectorType>(Src)) { 2083 unsigned NumElem = VTy->getVectorNumElements(); 2084 2085 // Handle a few common cases: 2086 // <3 x float> 2087 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 2088 // Cost = 64 bit store + extract + 32 bit store. 2089 return 3; 2090 2091 // <3 x double> 2092 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 2093 // Cost = 128 bit store + unpack + 64 bit store. 2094 return 3; 2095 2096 // Assume that all other non-power-of-two numbers are scalarized. 2097 if (!isPowerOf2_32(NumElem)) { 2098 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment, 2099 AddressSpace); 2100 int SplitCost = getScalarizationOverhead(Src, Opcode == Instruction::Load, 2101 Opcode == Instruction::Store); 2102 return NumElem * Cost + SplitCost; 2103 } 2104 } 2105 2106 // Legalize the type. 2107 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 2108 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 2109 "Invalid Opcode"); 2110 2111 // Each load/store unit costs 1. 2112 int Cost = LT.first * 1; 2113 2114 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a 2115 // proxy for a double-pumped AVX memory interface such as on Sandybridge. 2116 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow()) 2117 Cost *= 2; 2118 2119 return Cost; 2120 } 2121 2122 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, 2123 unsigned Alignment, 2124 unsigned AddressSpace) { 2125 VectorType *SrcVTy = dyn_cast<VectorType>(SrcTy); 2126 if (!SrcVTy) 2127 // To calculate scalar take the regular cost, without mask 2128 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace); 2129 2130 unsigned NumElem = SrcVTy->getVectorNumElements(); 2131 VectorType *MaskTy = 2132 VectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 2133 if ((Opcode == Instruction::Load && !isLegalMaskedLoad(SrcVTy)) || 2134 (Opcode == Instruction::Store && !isLegalMaskedStore(SrcVTy)) || 2135 !isPowerOf2_32(NumElem)) { 2136 // Scalarization 2137 int MaskSplitCost = getScalarizationOverhead(MaskTy, false, true); 2138 int ScalarCompareCost = getCmpSelInstrCost( 2139 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr); 2140 int BranchCost = getCFInstrCost(Instruction::Br); 2141 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 2142 2143 int ValueSplitCost = getScalarizationOverhead( 2144 SrcVTy, Opcode == Instruction::Load, Opcode == Instruction::Store); 2145 int MemopCost = 2146 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2147 Alignment, AddressSpace); 2148 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 2149 } 2150 2151 // Legalize the type. 2152 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 2153 auto VT = TLI->getValueType(DL, SrcVTy); 2154 int Cost = 0; 2155 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 2156 LT.second.getVectorNumElements() == NumElem) 2157 // Promotion requires expand/truncate for data and a shuffle for mask. 2158 Cost += getShuffleCost(TTI::SK_Select, SrcVTy, 0, nullptr) + 2159 getShuffleCost(TTI::SK_Select, MaskTy, 0, nullptr); 2160 2161 else if (LT.second.getVectorNumElements() > NumElem) { 2162 VectorType *NewMaskTy = VectorType::get(MaskTy->getVectorElementType(), 2163 LT.second.getVectorNumElements()); 2164 // Expanding requires fill mask with zeroes 2165 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, 0, MaskTy); 2166 } 2167 if (!ST->hasAVX512()) 2168 return Cost + LT.first*4; // Each maskmov costs 4 2169 2170 // AVX-512 masked load/store is cheapper 2171 return Cost+LT.first; 2172 } 2173 2174 int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE, 2175 const SCEV *Ptr) { 2176 // Address computations in vectorized code with non-consecutive addresses will 2177 // likely result in more instructions compared to scalar code where the 2178 // computation can more often be merged into the index mode. The resulting 2179 // extra micro-ops can significantly decrease throughput. 2180 unsigned NumVectorInstToHideOverhead = 10; 2181 2182 // Cost modeling of Strided Access Computation is hidden by the indexing 2183 // modes of X86 regardless of the stride value. We dont believe that there 2184 // is a difference between constant strided access in gerenal and constant 2185 // strided value which is less than or equal to 64. 2186 // Even in the case of (loop invariant) stride whose value is not known at 2187 // compile time, the address computation will not incur more than one extra 2188 // ADD instruction. 2189 if (Ty->isVectorTy() && SE) { 2190 if (!BaseT::isStridedAccess(Ptr)) 2191 return NumVectorInstToHideOverhead; 2192 if (!BaseT::getConstantStrideStep(SE, Ptr)) 2193 return 1; 2194 } 2195 2196 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 2197 } 2198 2199 int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, Type *ValTy, 2200 bool IsPairwise) { 2201 2202 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2203 2204 MVT MTy = LT.second; 2205 2206 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2207 assert(ISD && "Invalid opcode"); 2208 2209 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 2210 // and make it as the cost. 2211 2212 static const CostTblEntry SSE42CostTblPairWise[] = { 2213 { ISD::FADD, MVT::v2f64, 2 }, 2214 { ISD::FADD, MVT::v4f32, 4 }, 2215 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 2216 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5". 2217 { ISD::ADD, MVT::v8i16, 5 }, 2218 }; 2219 2220 static const CostTblEntry AVX1CostTblPairWise[] = { 2221 { ISD::FADD, MVT::v4f32, 4 }, 2222 { ISD::FADD, MVT::v4f64, 5 }, 2223 { ISD::FADD, MVT::v8f32, 7 }, 2224 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 2225 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5". 2226 { ISD::ADD, MVT::v4i64, 5 }, // The data reported by the IACA tool is "4.8". 2227 { ISD::ADD, MVT::v8i16, 5 }, 2228 { ISD::ADD, MVT::v8i32, 5 }, 2229 }; 2230 2231 static const CostTblEntry SSE42CostTblNoPairWise[] = { 2232 { ISD::FADD, MVT::v2f64, 2 }, 2233 { ISD::FADD, MVT::v4f32, 4 }, 2234 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 2235 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 2236 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 2237 }; 2238 2239 static const CostTblEntry AVX1CostTblNoPairWise[] = { 2240 { ISD::FADD, MVT::v4f32, 3 }, 2241 { ISD::FADD, MVT::v4f64, 3 }, 2242 { ISD::FADD, MVT::v8f32, 4 }, 2243 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 2244 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "2.8". 2245 { ISD::ADD, MVT::v4i64, 3 }, 2246 { ISD::ADD, MVT::v8i16, 4 }, 2247 { ISD::ADD, MVT::v8i32, 5 }, 2248 }; 2249 2250 if (IsPairwise) { 2251 if (ST->hasAVX()) 2252 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy)) 2253 return LT.first * Entry->Cost; 2254 2255 if (ST->hasSSE42()) 2256 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy)) 2257 return LT.first * Entry->Cost; 2258 } else { 2259 if (ST->hasAVX()) 2260 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 2261 return LT.first * Entry->Cost; 2262 2263 if (ST->hasSSE42()) 2264 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy)) 2265 return LT.first * Entry->Cost; 2266 } 2267 2268 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise); 2269 } 2270 2271 int X86TTIImpl::getMinMaxReductionCost(Type *ValTy, Type *CondTy, 2272 bool IsPairwise, bool IsUnsigned) { 2273 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2274 2275 MVT MTy = LT.second; 2276 2277 int ISD; 2278 if (ValTy->isIntOrIntVectorTy()) { 2279 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 2280 } else { 2281 assert(ValTy->isFPOrFPVectorTy() && 2282 "Expected float point or integer vector type."); 2283 ISD = ISD::FMINNUM; 2284 } 2285 2286 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 2287 // and make it as the cost. 2288 2289 static const CostTblEntry SSE42CostTblPairWise[] = { 2290 {ISD::FMINNUM, MVT::v2f64, 3}, 2291 {ISD::FMINNUM, MVT::v4f32, 2}, 2292 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8" 2293 {ISD::UMIN, MVT::v2i64, 8}, // The data reported by the IACA is "8.6" 2294 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5" 2295 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8" 2296 {ISD::SMIN, MVT::v8i16, 2}, 2297 {ISD::UMIN, MVT::v8i16, 2}, 2298 }; 2299 2300 static const CostTblEntry AVX1CostTblPairWise[] = { 2301 {ISD::FMINNUM, MVT::v4f32, 1}, 2302 {ISD::FMINNUM, MVT::v4f64, 1}, 2303 {ISD::FMINNUM, MVT::v8f32, 2}, 2304 {ISD::SMIN, MVT::v2i64, 3}, 2305 {ISD::UMIN, MVT::v2i64, 3}, 2306 {ISD::SMIN, MVT::v4i32, 1}, 2307 {ISD::UMIN, MVT::v4i32, 1}, 2308 {ISD::SMIN, MVT::v8i16, 1}, 2309 {ISD::UMIN, MVT::v8i16, 1}, 2310 {ISD::SMIN, MVT::v8i32, 3}, 2311 {ISD::UMIN, MVT::v8i32, 3}, 2312 }; 2313 2314 static const CostTblEntry AVX2CostTblPairWise[] = { 2315 {ISD::SMIN, MVT::v4i64, 2}, 2316 {ISD::UMIN, MVT::v4i64, 2}, 2317 {ISD::SMIN, MVT::v8i32, 1}, 2318 {ISD::UMIN, MVT::v8i32, 1}, 2319 {ISD::SMIN, MVT::v16i16, 1}, 2320 {ISD::UMIN, MVT::v16i16, 1}, 2321 {ISD::SMIN, MVT::v32i8, 2}, 2322 {ISD::UMIN, MVT::v32i8, 2}, 2323 }; 2324 2325 static const CostTblEntry AVX512CostTblPairWise[] = { 2326 {ISD::FMINNUM, MVT::v8f64, 1}, 2327 {ISD::FMINNUM, MVT::v16f32, 2}, 2328 {ISD::SMIN, MVT::v8i64, 2}, 2329 {ISD::UMIN, MVT::v8i64, 2}, 2330 {ISD::SMIN, MVT::v16i32, 1}, 2331 {ISD::UMIN, MVT::v16i32, 1}, 2332 }; 2333 2334 static const CostTblEntry SSE42CostTblNoPairWise[] = { 2335 {ISD::FMINNUM, MVT::v2f64, 3}, 2336 {ISD::FMINNUM, MVT::v4f32, 3}, 2337 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8" 2338 {ISD::UMIN, MVT::v2i64, 9}, // The data reported by the IACA is "8.6" 2339 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5" 2340 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8" 2341 {ISD::SMIN, MVT::v8i16, 1}, // The data reported by the IACA is "1.5" 2342 {ISD::UMIN, MVT::v8i16, 2}, // The data reported by the IACA is "1.8" 2343 }; 2344 2345 static const CostTblEntry AVX1CostTblNoPairWise[] = { 2346 {ISD::FMINNUM, MVT::v4f32, 1}, 2347 {ISD::FMINNUM, MVT::v4f64, 1}, 2348 {ISD::FMINNUM, MVT::v8f32, 1}, 2349 {ISD::SMIN, MVT::v2i64, 3}, 2350 {ISD::UMIN, MVT::v2i64, 3}, 2351 {ISD::SMIN, MVT::v4i32, 1}, 2352 {ISD::UMIN, MVT::v4i32, 1}, 2353 {ISD::SMIN, MVT::v8i16, 1}, 2354 {ISD::UMIN, MVT::v8i16, 1}, 2355 {ISD::SMIN, MVT::v8i32, 2}, 2356 {ISD::UMIN, MVT::v8i32, 2}, 2357 }; 2358 2359 static const CostTblEntry AVX2CostTblNoPairWise[] = { 2360 {ISD::SMIN, MVT::v4i64, 1}, 2361 {ISD::UMIN, MVT::v4i64, 1}, 2362 {ISD::SMIN, MVT::v8i32, 1}, 2363 {ISD::UMIN, MVT::v8i32, 1}, 2364 {ISD::SMIN, MVT::v16i16, 1}, 2365 {ISD::UMIN, MVT::v16i16, 1}, 2366 {ISD::SMIN, MVT::v32i8, 1}, 2367 {ISD::UMIN, MVT::v32i8, 1}, 2368 }; 2369 2370 static const CostTblEntry AVX512CostTblNoPairWise[] = { 2371 {ISD::FMINNUM, MVT::v8f64, 1}, 2372 {ISD::FMINNUM, MVT::v16f32, 2}, 2373 {ISD::SMIN, MVT::v8i64, 1}, 2374 {ISD::UMIN, MVT::v8i64, 1}, 2375 {ISD::SMIN, MVT::v16i32, 1}, 2376 {ISD::UMIN, MVT::v16i32, 1}, 2377 }; 2378 2379 if (IsPairwise) { 2380 if (ST->hasAVX512()) 2381 if (const auto *Entry = CostTableLookup(AVX512CostTblPairWise, ISD, MTy)) 2382 return LT.first * Entry->Cost; 2383 2384 if (ST->hasAVX2()) 2385 if (const auto *Entry = CostTableLookup(AVX2CostTblPairWise, ISD, MTy)) 2386 return LT.first * Entry->Cost; 2387 2388 if (ST->hasAVX()) 2389 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy)) 2390 return LT.first * Entry->Cost; 2391 2392 if (ST->hasSSE42()) 2393 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy)) 2394 return LT.first * Entry->Cost; 2395 } else { 2396 if (ST->hasAVX512()) 2397 if (const auto *Entry = 2398 CostTableLookup(AVX512CostTblNoPairWise, ISD, MTy)) 2399 return LT.first * Entry->Cost; 2400 2401 if (ST->hasAVX2()) 2402 if (const auto *Entry = CostTableLookup(AVX2CostTblNoPairWise, ISD, MTy)) 2403 return LT.first * Entry->Cost; 2404 2405 if (ST->hasAVX()) 2406 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 2407 return LT.first * Entry->Cost; 2408 2409 if (ST->hasSSE42()) 2410 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy)) 2411 return LT.first * Entry->Cost; 2412 } 2413 2414 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned); 2415 } 2416 2417 /// Calculate the cost of materializing a 64-bit value. This helper 2418 /// method might only calculate a fraction of a larger immediate. Therefore it 2419 /// is valid to return a cost of ZERO. 2420 int X86TTIImpl::getIntImmCost(int64_t Val) { 2421 if (Val == 0) 2422 return TTI::TCC_Free; 2423 2424 if (isInt<32>(Val)) 2425 return TTI::TCC_Basic; 2426 2427 return 2 * TTI::TCC_Basic; 2428 } 2429 2430 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { 2431 assert(Ty->isIntegerTy()); 2432 2433 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 2434 if (BitSize == 0) 2435 return ~0U; 2436 2437 // Never hoist constants larger than 128bit, because this might lead to 2438 // incorrect code generation or assertions in codegen. 2439 // Fixme: Create a cost model for types larger than i128 once the codegen 2440 // issues have been fixed. 2441 if (BitSize > 128) 2442 return TTI::TCC_Free; 2443 2444 if (Imm == 0) 2445 return TTI::TCC_Free; 2446 2447 // Sign-extend all constants to a multiple of 64-bit. 2448 APInt ImmVal = Imm; 2449 if (BitSize % 64 != 0) 2450 ImmVal = Imm.sext(alignTo(BitSize, 64)); 2451 2452 // Split the constant into 64-bit chunks and calculate the cost for each 2453 // chunk. 2454 int Cost = 0; 2455 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 2456 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 2457 int64_t Val = Tmp.getSExtValue(); 2458 Cost += getIntImmCost(Val); 2459 } 2460 // We need at least one instruction to materialize the constant. 2461 return std::max(1, Cost); 2462 } 2463 2464 int X86TTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, 2465 Type *Ty) { 2466 assert(Ty->isIntegerTy()); 2467 2468 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 2469 // There is no cost model for constants with a bit size of 0. Return TCC_Free 2470 // here, so that constant hoisting will ignore this constant. 2471 if (BitSize == 0) 2472 return TTI::TCC_Free; 2473 2474 unsigned ImmIdx = ~0U; 2475 switch (Opcode) { 2476 default: 2477 return TTI::TCC_Free; 2478 case Instruction::GetElementPtr: 2479 // Always hoist the base address of a GetElementPtr. This prevents the 2480 // creation of new constants for every base constant that gets constant 2481 // folded with the offset. 2482 if (Idx == 0) 2483 return 2 * TTI::TCC_Basic; 2484 return TTI::TCC_Free; 2485 case Instruction::Store: 2486 ImmIdx = 0; 2487 break; 2488 case Instruction::ICmp: 2489 // This is an imperfect hack to prevent constant hoisting of 2490 // compares that might be trying to check if a 64-bit value fits in 2491 // 32-bits. The backend can optimize these cases using a right shift by 32. 2492 // Ideally we would check the compare predicate here. There also other 2493 // similar immediates the backend can use shifts for. 2494 if (Idx == 1 && Imm.getBitWidth() == 64) { 2495 uint64_t ImmVal = Imm.getZExtValue(); 2496 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 2497 return TTI::TCC_Free; 2498 } 2499 ImmIdx = 1; 2500 break; 2501 case Instruction::And: 2502 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 2503 // by using a 32-bit operation with implicit zero extension. Detect such 2504 // immediates here as the normal path expects bit 31 to be sign extended. 2505 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 2506 return TTI::TCC_Free; 2507 ImmIdx = 1; 2508 break; 2509 case Instruction::Add: 2510 case Instruction::Sub: 2511 // For add/sub, we can use the opposite instruction for INT32_MIN. 2512 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 2513 return TTI::TCC_Free; 2514 ImmIdx = 1; 2515 break; 2516 case Instruction::UDiv: 2517 case Instruction::SDiv: 2518 case Instruction::URem: 2519 case Instruction::SRem: 2520 // Division by constant is typically expanded later into a different 2521 // instruction sequence. This completely changes the constants. 2522 // Report them as "free" to stop ConstantHoist from marking them as opaque. 2523 return TTI::TCC_Free; 2524 case Instruction::Mul: 2525 case Instruction::Or: 2526 case Instruction::Xor: 2527 ImmIdx = 1; 2528 break; 2529 // Always return TCC_Free for the shift value of a shift instruction. 2530 case Instruction::Shl: 2531 case Instruction::LShr: 2532 case Instruction::AShr: 2533 if (Idx == 1) 2534 return TTI::TCC_Free; 2535 break; 2536 case Instruction::Trunc: 2537 case Instruction::ZExt: 2538 case Instruction::SExt: 2539 case Instruction::IntToPtr: 2540 case Instruction::PtrToInt: 2541 case Instruction::BitCast: 2542 case Instruction::PHI: 2543 case Instruction::Call: 2544 case Instruction::Select: 2545 case Instruction::Ret: 2546 case Instruction::Load: 2547 break; 2548 } 2549 2550 if (Idx == ImmIdx) { 2551 int NumConstants = divideCeil(BitSize, 64); 2552 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty); 2553 return (Cost <= NumConstants * TTI::TCC_Basic) 2554 ? static_cast<int>(TTI::TCC_Free) 2555 : Cost; 2556 } 2557 2558 return X86TTIImpl::getIntImmCost(Imm, Ty); 2559 } 2560 2561 int X86TTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, 2562 Type *Ty) { 2563 assert(Ty->isIntegerTy()); 2564 2565 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 2566 // There is no cost model for constants with a bit size of 0. Return TCC_Free 2567 // here, so that constant hoisting will ignore this constant. 2568 if (BitSize == 0) 2569 return TTI::TCC_Free; 2570 2571 switch (IID) { 2572 default: 2573 return TTI::TCC_Free; 2574 case Intrinsic::sadd_with_overflow: 2575 case Intrinsic::uadd_with_overflow: 2576 case Intrinsic::ssub_with_overflow: 2577 case Intrinsic::usub_with_overflow: 2578 case Intrinsic::smul_with_overflow: 2579 case Intrinsic::umul_with_overflow: 2580 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 2581 return TTI::TCC_Free; 2582 break; 2583 case Intrinsic::experimental_stackmap: 2584 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 2585 return TTI::TCC_Free; 2586 break; 2587 case Intrinsic::experimental_patchpoint_void: 2588 case Intrinsic::experimental_patchpoint_i64: 2589 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 2590 return TTI::TCC_Free; 2591 break; 2592 } 2593 return X86TTIImpl::getIntImmCost(Imm, Ty); 2594 } 2595 2596 unsigned X86TTIImpl::getUserCost(const User *U, 2597 ArrayRef<const Value *> Operands) { 2598 if (isa<StoreInst>(U)) { 2599 Value *Ptr = U->getOperand(1); 2600 // Store instruction with index and scale costs 2 Uops. 2601 // Check the preceding GEP to identify non-const indices. 2602 if (auto GEP = dyn_cast<GetElementPtrInst>(Ptr)) { 2603 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 2604 return TTI::TCC_Basic * 2; 2605 } 2606 return TTI::TCC_Basic; 2607 } 2608 return BaseT::getUserCost(U, Operands); 2609 } 2610 2611 // Return an average cost of Gather / Scatter instruction, maybe improved later 2612 int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, Value *Ptr, 2613 unsigned Alignment, unsigned AddressSpace) { 2614 2615 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 2616 unsigned VF = SrcVTy->getVectorNumElements(); 2617 2618 // Try to reduce index size from 64 bit (default for GEP) 2619 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 2620 // operation will use 16 x 64 indices which do not fit in a zmm and needs 2621 // to split. Also check that the base pointer is the same for all lanes, 2622 // and that there's at most one variable index. 2623 auto getIndexSizeInBits = [](Value *Ptr, const DataLayout& DL) { 2624 unsigned IndexSize = DL.getPointerSizeInBits(); 2625 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 2626 if (IndexSize < 64 || !GEP) 2627 return IndexSize; 2628 2629 unsigned NumOfVarIndices = 0; 2630 Value *Ptrs = GEP->getPointerOperand(); 2631 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 2632 return IndexSize; 2633 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 2634 if (isa<Constant>(GEP->getOperand(i))) 2635 continue; 2636 Type *IndxTy = GEP->getOperand(i)->getType(); 2637 if (IndxTy->isVectorTy()) 2638 IndxTy = IndxTy->getVectorElementType(); 2639 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 2640 !isa<SExtInst>(GEP->getOperand(i))) || 2641 ++NumOfVarIndices > 1) 2642 return IndexSize; // 64 2643 } 2644 return (unsigned)32; 2645 }; 2646 2647 2648 // Trying to reduce IndexSize to 32 bits for vector 16. 2649 // By default the IndexSize is equal to pointer size. 2650 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 2651 ? getIndexSizeInBits(Ptr, DL) 2652 : DL.getPointerSizeInBits(); 2653 2654 Type *IndexVTy = VectorType::get(IntegerType::get(SrcVTy->getContext(), 2655 IndexSize), VF); 2656 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy); 2657 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy); 2658 int SplitFactor = std::max(IdxsLT.first, SrcLT.first); 2659 if (SplitFactor > 1) { 2660 // Handle splitting of vector of pointers 2661 Type *SplitSrcTy = VectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 2662 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 2663 AddressSpace); 2664 } 2665 2666 // The gather / scatter cost is given by Intel architects. It is a rough 2667 // number since we are looking at one instruction in a time. 2668 const int GSOverhead = (Opcode == Instruction::Load) 2669 ? ST->getGatherOverhead() 2670 : ST->getScatterOverhead(); 2671 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2672 Alignment, AddressSpace); 2673 } 2674 2675 /// Return the cost of full scalarization of gather / scatter operation. 2676 /// 2677 /// Opcode - Load or Store instruction. 2678 /// SrcVTy - The type of the data vector that should be gathered or scattered. 2679 /// VariableMask - The mask is non-constant at compile time. 2680 /// Alignment - Alignment for one element. 2681 /// AddressSpace - pointer[s] address space. 2682 /// 2683 int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 2684 bool VariableMask, unsigned Alignment, 2685 unsigned AddressSpace) { 2686 unsigned VF = SrcVTy->getVectorNumElements(); 2687 2688 int MaskUnpackCost = 0; 2689 if (VariableMask) { 2690 VectorType *MaskTy = 2691 VectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 2692 MaskUnpackCost = getScalarizationOverhead(MaskTy, false, true); 2693 int ScalarCompareCost = 2694 getCmpSelInstrCost(Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), 2695 nullptr); 2696 int BranchCost = getCFInstrCost(Instruction::Br); 2697 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 2698 } 2699 2700 // The cost of the scalar loads/stores. 2701 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2702 Alignment, AddressSpace); 2703 2704 int InsertExtractCost = 0; 2705 if (Opcode == Instruction::Load) 2706 for (unsigned i = 0; i < VF; ++i) 2707 // Add the cost of inserting each scalar load into the vector 2708 InsertExtractCost += 2709 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 2710 else 2711 for (unsigned i = 0; i < VF; ++i) 2712 // Add the cost of extracting each element out of the data vector 2713 InsertExtractCost += 2714 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 2715 2716 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 2717 } 2718 2719 /// Calculate the cost of Gather / Scatter operation 2720 int X86TTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *SrcVTy, 2721 Value *Ptr, bool VariableMask, 2722 unsigned Alignment) { 2723 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 2724 unsigned VF = SrcVTy->getVectorNumElements(); 2725 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 2726 if (!PtrTy && Ptr->getType()->isVectorTy()) 2727 PtrTy = dyn_cast<PointerType>(Ptr->getType()->getVectorElementType()); 2728 assert(PtrTy && "Unexpected type for Ptr argument"); 2729 unsigned AddressSpace = PtrTy->getAddressSpace(); 2730 2731 bool Scalarize = false; 2732 if ((Opcode == Instruction::Load && !isLegalMaskedGather(SrcVTy)) || 2733 (Opcode == Instruction::Store && !isLegalMaskedScatter(SrcVTy))) 2734 Scalarize = true; 2735 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 2736 // Vector-4 of gather/scatter instruction does not exist on KNL. 2737 // We can extend it to 8 elements, but zeroing upper bits of 2738 // the mask vector will add more instructions. Right now we give the scalar 2739 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 2740 // is better in the VariableMask case. 2741 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 2742 Scalarize = true; 2743 2744 if (Scalarize) 2745 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 2746 AddressSpace); 2747 2748 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 2749 } 2750 2751 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 2752 TargetTransformInfo::LSRCost &C2) { 2753 // X86 specific here are "instruction number 1st priority". 2754 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 2755 C1.NumIVMuls, C1.NumBaseAdds, 2756 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 2757 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 2758 C2.NumIVMuls, C2.NumBaseAdds, 2759 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 2760 } 2761 2762 bool X86TTIImpl::canMacroFuseCmp() { 2763 return ST->hasMacroFusion(); 2764 } 2765 2766 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy) { 2767 // The backend can't handle a single element vector. 2768 if (isa<VectorType>(DataTy) && DataTy->getVectorNumElements() == 1) 2769 return false; 2770 Type *ScalarTy = DataTy->getScalarType(); 2771 int DataWidth = isa<PointerType>(ScalarTy) ? 2772 DL.getPointerSizeInBits() : ScalarTy->getPrimitiveSizeInBits(); 2773 2774 return ((DataWidth == 32 || DataWidth == 64) && ST->hasAVX()) || 2775 ((DataWidth == 8 || DataWidth == 16) && ST->hasBWI()); 2776 } 2777 2778 bool X86TTIImpl::isLegalMaskedStore(Type *DataType) { 2779 return isLegalMaskedLoad(DataType); 2780 } 2781 2782 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy) { 2783 // This function is called now in two cases: from the Loop Vectorizer 2784 // and from the Scalarizer. 2785 // When the Loop Vectorizer asks about legality of the feature, 2786 // the vectorization factor is not calculated yet. The Loop Vectorizer 2787 // sends a scalar type and the decision is based on the width of the 2788 // scalar element. 2789 // Later on, the cost model will estimate usage this intrinsic based on 2790 // the vector type. 2791 // The Scalarizer asks again about legality. It sends a vector type. 2792 // In this case we can reject non-power-of-2 vectors. 2793 // We also reject single element vectors as the type legalizer can't 2794 // scalarize it. 2795 if (isa<VectorType>(DataTy)) { 2796 unsigned NumElts = DataTy->getVectorNumElements(); 2797 if (NumElts == 1 || !isPowerOf2_32(NumElts)) 2798 return false; 2799 } 2800 Type *ScalarTy = DataTy->getScalarType(); 2801 int DataWidth = isa<PointerType>(ScalarTy) ? 2802 DL.getPointerSizeInBits() : ScalarTy->getPrimitiveSizeInBits(); 2803 2804 // Some CPUs have better gather performance than others. 2805 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 2806 // enable gather with a -march. 2807 return (DataWidth == 32 || DataWidth == 64) && 2808 (ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2())); 2809 } 2810 2811 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType) { 2812 // AVX2 doesn't support scatter 2813 if (!ST->hasAVX512()) 2814 return false; 2815 return isLegalMaskedGather(DataType); 2816 } 2817 2818 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 2819 EVT VT = TLI->getValueType(DL, DataType); 2820 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 2821 } 2822 2823 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 2824 return false; 2825 } 2826 2827 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 2828 const Function *Callee) const { 2829 const TargetMachine &TM = getTLI()->getTargetMachine(); 2830 2831 // Work this as a subsetting of subtarget features. 2832 const FeatureBitset &CallerBits = 2833 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 2834 const FeatureBitset &CalleeBits = 2835 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 2836 2837 // FIXME: This is likely too limiting as it will include subtarget features 2838 // that we might not care about for inlining, but it is conservatively 2839 // correct. 2840 return (CallerBits & CalleeBits) == CalleeBits; 2841 } 2842 2843 const X86TTIImpl::TTI::MemCmpExpansionOptions * 2844 X86TTIImpl::enableMemCmpExpansion(bool IsZeroCmp) const { 2845 // Only enable vector loads for equality comparison. 2846 // Right now the vector version is not as fast, see #33329. 2847 static const auto ThreeWayOptions = [this]() { 2848 TTI::MemCmpExpansionOptions Options; 2849 if (ST->is64Bit()) { 2850 Options.LoadSizes.push_back(8); 2851 } 2852 Options.LoadSizes.push_back(4); 2853 Options.LoadSizes.push_back(2); 2854 Options.LoadSizes.push_back(1); 2855 return Options; 2856 }(); 2857 static const auto EqZeroOptions = [this]() { 2858 TTI::MemCmpExpansionOptions Options; 2859 // TODO: enable AVX512 when the DAG is ready. 2860 // if (ST->hasAVX512()) Options.LoadSizes.push_back(64); 2861 if (ST->hasAVX2()) Options.LoadSizes.push_back(32); 2862 if (ST->hasSSE2()) Options.LoadSizes.push_back(16); 2863 if (ST->is64Bit()) { 2864 Options.LoadSizes.push_back(8); 2865 } 2866 Options.LoadSizes.push_back(4); 2867 Options.LoadSizes.push_back(2); 2868 Options.LoadSizes.push_back(1); 2869 return Options; 2870 }(); 2871 return IsZeroCmp ? &EqZeroOptions : &ThreeWayOptions; 2872 } 2873 2874 bool X86TTIImpl::enableInterleavedAccessVectorization() { 2875 // TODO: We expect this to be beneficial regardless of arch, 2876 // but there are currently some unexplained performance artifacts on Atom. 2877 // As a temporary solution, disable on Atom. 2878 return !(ST->isAtom()); 2879 } 2880 2881 // Get estimation for interleaved load/store operations for AVX2. 2882 // \p Factor is the interleaved-access factor (stride) - number of 2883 // (interleaved) elements in the group. 2884 // \p Indices contains the indices for a strided load: when the 2885 // interleaved load has gaps they indicate which elements are used. 2886 // If Indices is empty (or if the number of indices is equal to the size 2887 // of the interleaved-access as given in \p Factor) the access has no gaps. 2888 // 2889 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 2890 // computing the cost using a generic formula as a function of generic 2891 // shuffles. We therefore use a lookup table instead, filled according to 2892 // the instruction sequences that codegen currently generates. 2893 int X86TTIImpl::getInterleavedMemoryOpCostAVX2(unsigned Opcode, Type *VecTy, 2894 unsigned Factor, 2895 ArrayRef<unsigned> Indices, 2896 unsigned Alignment, 2897 unsigned AddressSpace, 2898 bool UseMaskForCond, 2899 bool UseMaskForGaps) { 2900 2901 if (UseMaskForCond || UseMaskForGaps) 2902 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 2903 Alignment, AddressSpace, 2904 UseMaskForCond, UseMaskForGaps); 2905 2906 // We currently Support only fully-interleaved groups, with no gaps. 2907 // TODO: Support also strided loads (interleaved-groups with gaps). 2908 if (Indices.size() && Indices.size() != Factor) 2909 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 2910 Alignment, AddressSpace); 2911 2912 // VecTy for interleave memop is <VF*Factor x Elt>. 2913 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 2914 // VecTy = <12 x i32>. 2915 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 2916 2917 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 2918 // the VF=2, while v2i128 is an unsupported MVT vector type 2919 // (see MachineValueType.h::getVectorVT()). 2920 if (!LegalVT.isVector()) 2921 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 2922 Alignment, AddressSpace); 2923 2924 unsigned VF = VecTy->getVectorNumElements() / Factor; 2925 Type *ScalarTy = VecTy->getVectorElementType(); 2926 2927 // Calculate the number of memory operations (NumOfMemOps), required 2928 // for load/store the VecTy. 2929 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 2930 unsigned LegalVTSize = LegalVT.getStoreSize(); 2931 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 2932 2933 // Get the cost of one memory operation. 2934 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(), 2935 LegalVT.getVectorNumElements()); 2936 unsigned MemOpCost = 2937 getMemoryOpCost(Opcode, SingleMemOpTy, Alignment, AddressSpace); 2938 2939 VectorType *VT = VectorType::get(ScalarTy, VF); 2940 EVT ETy = TLI->getValueType(DL, VT); 2941 if (!ETy.isSimple()) 2942 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 2943 Alignment, AddressSpace); 2944 2945 // TODO: Complete for other data-types and strides. 2946 // Each combination of Stride, ElementTy and VF results in a different 2947 // sequence; The cost tables are therefore accessed with: 2948 // Factor (stride) and VectorType=VFxElemType. 2949 // The Cost accounts only for the shuffle sequence; 2950 // The cost of the loads/stores is accounted for separately. 2951 // 2952 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 2953 { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64 2954 { 2, MVT::v4f64, 6 }, //(load 8f64 and) deinterleave into 2 x 4f64 2955 2956 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8 2957 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8 2958 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8 2959 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8 2960 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8 2961 { 3, MVT::v8f32, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32 2962 2963 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8 2964 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8 2965 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8 2966 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8 2967 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8 2968 2969 { 8, MVT::v8f32, 40 } //(load 64f32 and)deinterleave into 8 x 8f32 2970 }; 2971 2972 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 2973 { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store) 2974 { 2, MVT::v4f64, 6 }, //interleave into 2 x 4f64 into 8f64 (and store) 2975 2976 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store) 2977 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store) 2978 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store) 2979 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store) 2980 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store) 2981 2982 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store) 2983 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store) 2984 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store) 2985 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store) 2986 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store) 2987 }; 2988 2989 if (Opcode == Instruction::Load) { 2990 if (const auto *Entry = 2991 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 2992 return NumOfMemOps * MemOpCost + Entry->Cost; 2993 } else { 2994 assert(Opcode == Instruction::Store && 2995 "Expected Store Instruction at this point"); 2996 if (const auto *Entry = 2997 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 2998 return NumOfMemOps * MemOpCost + Entry->Cost; 2999 } 3000 3001 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3002 Alignment, AddressSpace); 3003 } 3004 3005 // Get estimation for interleaved load/store operations and strided load. 3006 // \p Indices contains indices for strided load. 3007 // \p Factor - the factor of interleaving. 3008 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 3009 int X86TTIImpl::getInterleavedMemoryOpCostAVX512(unsigned Opcode, Type *VecTy, 3010 unsigned Factor, 3011 ArrayRef<unsigned> Indices, 3012 unsigned Alignment, 3013 unsigned AddressSpace, 3014 bool UseMaskForCond, 3015 bool UseMaskForGaps) { 3016 3017 if (UseMaskForCond || UseMaskForGaps) 3018 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3019 Alignment, AddressSpace, 3020 UseMaskForCond, UseMaskForGaps); 3021 3022 // VecTy for interleave memop is <VF*Factor x Elt>. 3023 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 3024 // VecTy = <12 x i32>. 3025 3026 // Calculate the number of memory operations (NumOfMemOps), required 3027 // for load/store the VecTy. 3028 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 3029 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 3030 unsigned LegalVTSize = LegalVT.getStoreSize(); 3031 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 3032 3033 // Get the cost of one memory operation. 3034 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(), 3035 LegalVT.getVectorNumElements()); 3036 unsigned MemOpCost = 3037 getMemoryOpCost(Opcode, SingleMemOpTy, Alignment, AddressSpace); 3038 3039 unsigned VF = VecTy->getVectorNumElements() / Factor; 3040 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 3041 3042 if (Opcode == Instruction::Load) { 3043 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 3044 // contain the cost of the optimized shuffle sequence that the 3045 // X86InterleavedAccess pass will generate. 3046 // The cost of loads and stores are computed separately from the table. 3047 3048 // X86InterleavedAccess support only the following interleaved-access group. 3049 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 3050 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 3051 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 3052 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 3053 }; 3054 3055 if (const auto *Entry = 3056 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 3057 return NumOfMemOps * MemOpCost + Entry->Cost; 3058 //If an entry does not exist, fallback to the default implementation. 3059 3060 // Kind of shuffle depends on number of loaded values. 3061 // If we load the entire data in one register, we can use a 1-src shuffle. 3062 // Otherwise, we'll merge 2 sources in each operation. 3063 TTI::ShuffleKind ShuffleKind = 3064 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 3065 3066 unsigned ShuffleCost = 3067 getShuffleCost(ShuffleKind, SingleMemOpTy, 0, nullptr); 3068 3069 unsigned NumOfLoadsInInterleaveGrp = 3070 Indices.size() ? Indices.size() : Factor; 3071 Type *ResultTy = VectorType::get(VecTy->getVectorElementType(), 3072 VecTy->getVectorNumElements() / Factor); 3073 unsigned NumOfResults = 3074 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 3075 NumOfLoadsInInterleaveGrp; 3076 3077 // About a half of the loads may be folded in shuffles when we have only 3078 // one result. If we have more than one result, we do not fold loads at all. 3079 unsigned NumOfUnfoldedLoads = 3080 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 3081 3082 // Get a number of shuffle operations per result. 3083 unsigned NumOfShufflesPerResult = 3084 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 3085 3086 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 3087 // When we have more than one destination, we need additional instructions 3088 // to keep sources. 3089 unsigned NumOfMoves = 0; 3090 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 3091 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 3092 3093 int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 3094 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 3095 3096 return Cost; 3097 } 3098 3099 // Store. 3100 assert(Opcode == Instruction::Store && 3101 "Expected Store Instruction at this point"); 3102 // X86InterleavedAccess support only the following interleaved-access group. 3103 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 3104 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 3105 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 3106 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 3107 3108 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 3109 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 3110 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 3111 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 3112 }; 3113 3114 if (const auto *Entry = 3115 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 3116 return NumOfMemOps * MemOpCost + Entry->Cost; 3117 //If an entry does not exist, fallback to the default implementation. 3118 3119 // There is no strided stores meanwhile. And store can't be folded in 3120 // shuffle. 3121 unsigned NumOfSources = Factor; // The number of values to be merged. 3122 unsigned ShuffleCost = 3123 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, 0, nullptr); 3124 unsigned NumOfShufflesPerStore = NumOfSources - 1; 3125 3126 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 3127 // We need additional instructions to keep sources. 3128 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 3129 int Cost = NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 3130 NumOfMoves; 3131 return Cost; 3132 } 3133 3134 int X86TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, 3135 unsigned Factor, 3136 ArrayRef<unsigned> Indices, 3137 unsigned Alignment, 3138 unsigned AddressSpace, 3139 bool UseMaskForCond, 3140 bool UseMaskForGaps) { 3141 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 3142 Type *EltTy = VecTy->getVectorElementType(); 3143 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 3144 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 3145 return true; 3146 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 3147 return HasBW; 3148 return false; 3149 }; 3150 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 3151 return getInterleavedMemoryOpCostAVX512(Opcode, VecTy, Factor, Indices, 3152 Alignment, AddressSpace, 3153 UseMaskForCond, UseMaskForGaps); 3154 if (ST->hasAVX2()) 3155 return getInterleavedMemoryOpCostAVX2(Opcode, VecTy, Factor, Indices, 3156 Alignment, AddressSpace, 3157 UseMaskForCond, UseMaskForGaps); 3158 3159 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3160 Alignment, AddressSpace, 3161 UseMaskForCond, UseMaskForGaps); 3162 } 3163