1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// \file 10 /// This file implements a TargetTransformInfo analysis pass specific to the 11 /// X86 target machine. It uses the target's detailed information to provide 12 /// more precise answers to certain TTI queries, while letting the target 13 /// independent and default TTI implementations handle the rest. 14 /// 15 //===----------------------------------------------------------------------===// 16 /// About Cost Model numbers used below it's necessary to say the following: 17 /// the numbers correspond to some "generic" X86 CPU instead of usage of 18 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 19 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 20 /// the lookups below the cost is based on Nehalem as that was the first CPU 21 /// to support that feature level and thus has most likely the worst case cost. 22 /// Some examples of other technologies/CPUs: 23 /// SSE 3 - Pentium4 / Athlon64 24 /// SSE 4.1 - Penryn 25 /// SSE 4.2 - Nehalem 26 /// AVX - Sandy Bridge 27 /// AVX2 - Haswell 28 /// AVX-512 - Xeon Phi / Skylake 29 /// And some examples of instruction target dependent costs (latency) 30 /// divss sqrtss rsqrtss 31 /// AMD K7 11-16 19 3 32 /// Piledriver 9-24 13-15 5 33 /// Jaguar 14 16 2 34 /// Pentium II,III 18 30 2 35 /// Nehalem 7-14 7-18 3 36 /// Haswell 10-13 11 5 37 /// TODO: Develop and implement the target dependent cost model and 38 /// specialize cost numbers for different Cost Model Targets such as throughput, 39 /// code size, latency and uop count. 40 //===----------------------------------------------------------------------===// 41 42 #include "X86TargetTransformInfo.h" 43 #include "llvm/Analysis/TargetTransformInfo.h" 44 #include "llvm/CodeGen/BasicTTIImpl.h" 45 #include "llvm/IR/IntrinsicInst.h" 46 #include "llvm/Support/Debug.h" 47 #include "llvm/Target/CostTable.h" 48 #include "llvm/Target/TargetLowering.h" 49 50 using namespace llvm; 51 52 #define DEBUG_TYPE "x86tti" 53 54 //===----------------------------------------------------------------------===// 55 // 56 // X86 cost model. 57 // 58 //===----------------------------------------------------------------------===// 59 60 TargetTransformInfo::PopcntSupportKind 61 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 62 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 63 // TODO: Currently the __builtin_popcount() implementation using SSE3 64 // instructions is inefficient. Once the problem is fixed, we should 65 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 66 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 67 } 68 69 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 70 TargetTransformInfo::CacheLevel Level) const { 71 switch (Level) { 72 case TargetTransformInfo::CacheLevel::L1D: 73 // - Penry 74 // - Nehalem 75 // - Westmere 76 // - Sandy Bridge 77 // - Ivy Bridge 78 // - Haswell 79 // - Broadwell 80 // - Skylake 81 // - Kabylake 82 return 32 * 1024; // 32 KByte 83 case TargetTransformInfo::CacheLevel::L2D: 84 // - Penry 85 // - Nehalem 86 // - Westmere 87 // - Sandy Bridge 88 // - Ivy Bridge 89 // - Haswell 90 // - Broadwell 91 // - Skylake 92 // - Kabylake 93 return 256 * 1024; // 256 KByte 94 } 95 96 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 97 } 98 99 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 100 TargetTransformInfo::CacheLevel Level) const { 101 // - Penry 102 // - Nehalem 103 // - Westmere 104 // - Sandy Bridge 105 // - Ivy Bridge 106 // - Haswell 107 // - Broadwell 108 // - Skylake 109 // - Kabylake 110 switch (Level) { 111 case TargetTransformInfo::CacheLevel::L1D: 112 LLVM_FALLTHROUGH; 113 case TargetTransformInfo::CacheLevel::L2D: 114 return 8; 115 } 116 117 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 118 } 119 120 unsigned X86TTIImpl::getNumberOfRegisters(bool Vector) { 121 if (Vector && !ST->hasSSE1()) 122 return 0; 123 124 if (ST->is64Bit()) { 125 if (Vector && ST->hasAVX512()) 126 return 32; 127 return 16; 128 } 129 return 8; 130 } 131 132 unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const { 133 if (Vector) { 134 if (ST->hasAVX512()) 135 return 512; 136 if (ST->hasAVX()) 137 return 256; 138 if (ST->hasSSE1()) 139 return 128; 140 return 0; 141 } 142 143 if (ST->is64Bit()) 144 return 64; 145 146 return 32; 147 } 148 149 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 150 return getRegisterBitWidth(true); 151 } 152 153 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 154 // If the loop will not be vectorized, don't interleave the loop. 155 // Let regular unroll to unroll the loop, which saves the overflow 156 // check and memory check cost. 157 if (VF == 1) 158 return 1; 159 160 if (ST->isAtom()) 161 return 1; 162 163 // Sandybridge and Haswell have multiple execution ports and pipelined 164 // vector units. 165 if (ST->hasAVX()) 166 return 4; 167 168 return 2; 169 } 170 171 int X86TTIImpl::getArithmeticInstrCost( 172 unsigned Opcode, Type *Ty, 173 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 174 TTI::OperandValueProperties Opd1PropInfo, 175 TTI::OperandValueProperties Opd2PropInfo, 176 ArrayRef<const Value *> Args) { 177 // Legalize the type. 178 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 179 180 int ISD = TLI->InstructionOpcodeToISD(Opcode); 181 assert(ISD && "Invalid opcode"); 182 183 static const CostTblEntry SLMCostTable[] = { 184 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 185 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 186 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. 187 { ISD::FMUL, MVT::f64, 2 }, // mulsd 188 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 189 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 190 { ISD::FDIV, MVT::f32, 17 }, // divss 191 { ISD::FDIV, MVT::v4f32, 39 }, // divps 192 { ISD::FDIV, MVT::f64, 32 }, // divsd 193 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 194 { ISD::FADD, MVT::v2f64, 2 }, // addpd 195 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 196 // v2i64/v4i64 mul is custom lowered as a series of long: 197 // multiplies(3), shifts(3) and adds(2) 198 // slm muldq version throughput is 2 and addq throughput 4 199 // thus: 3X2 (muldq throughput) + 3X1 (shift throuput) + 200 // 3X4 (addq throughput) = 17 201 { ISD::MUL, MVT::v2i64, 17 }, 202 // slm addq\subq throughput is 4 203 { ISD::ADD, MVT::v2i64, 4 }, 204 { ISD::SUB, MVT::v2i64, 4 }, 205 }; 206 207 if (ST->isSLM()) { 208 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 209 // Check if the operands can be shrinked into a smaller datatype. 210 bool Op1Signed = false; 211 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 212 bool Op2Signed = false; 213 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 214 215 bool signedMode = Op1Signed | Op2Signed; 216 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 217 218 if (OpMinSize <= 7) 219 return LT.first * 3; // pmullw/sext 220 if (!signedMode && OpMinSize <= 8) 221 return LT.first * 3; // pmullw/zext 222 if (OpMinSize <= 15) 223 return LT.first * 5; // pmullw/pmulhw/pshuf 224 if (!signedMode && OpMinSize <= 16) 225 return LT.first * 5; // pmullw/pmulhw/pshuf 226 } 227 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 228 LT.second)) { 229 return LT.first * Entry->Cost; 230 } 231 } 232 233 if (ISD == ISD::SDIV && 234 Op2Info == TargetTransformInfo::OK_UniformConstantValue && 235 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 236 // On X86, vector signed division by constants power-of-two are 237 // normally expanded to the sequence SRA + SRL + ADD + SRA. 238 // The OperandValue properties many not be same as that of previous 239 // operation;conservatively assume OP_None. 240 int Cost = 2 * getArithmeticInstrCost(Instruction::AShr, Ty, Op1Info, 241 Op2Info, TargetTransformInfo::OP_None, 242 TargetTransformInfo::OP_None); 243 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 244 TargetTransformInfo::OP_None, 245 TargetTransformInfo::OP_None); 246 Cost += getArithmeticInstrCost(Instruction::Add, Ty, Op1Info, Op2Info, 247 TargetTransformInfo::OP_None, 248 TargetTransformInfo::OP_None); 249 250 return Cost; 251 } 252 253 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 254 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 255 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 256 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 257 258 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 259 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 260 }; 261 262 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 263 ST->hasBWI()) { 264 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 265 LT.second)) 266 return LT.first * Entry->Cost; 267 } 268 269 static const CostTblEntry AVX512UniformConstCostTable[] = { 270 { ISD::SRA, MVT::v2i64, 1 }, 271 { ISD::SRA, MVT::v4i64, 1 }, 272 { ISD::SRA, MVT::v8i64, 1 }, 273 274 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 275 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 276 }; 277 278 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 279 ST->hasAVX512()) { 280 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 281 LT.second)) 282 return LT.first * Entry->Cost; 283 } 284 285 static const CostTblEntry AVX2UniformConstCostTable[] = { 286 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 287 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 288 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 289 290 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 291 292 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 293 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 294 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 295 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 296 }; 297 298 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 299 ST->hasAVX2()) { 300 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 301 LT.second)) 302 return LT.first * Entry->Cost; 303 } 304 305 static const CostTblEntry SSE2UniformConstCostTable[] = { 306 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 307 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 308 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 309 310 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 311 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 312 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 313 314 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 315 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 316 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 317 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 318 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 319 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 320 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 321 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 322 }; 323 324 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 325 ST->hasSSE2()) { 326 // pmuldq sequence. 327 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 328 return LT.first * 32; 329 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 330 return LT.first * 15; 331 332 // XOP has faster vXi8 shifts. 333 if ((ISD != ISD::SHL && ISD != ISD::SRL && ISD != ISD::SRA) || 334 !ST->hasXOP()) 335 if (const auto *Entry = 336 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 337 return LT.first * Entry->Cost; 338 } 339 340 static const CostTblEntry AVX2UniformCostTable[] = { 341 // Uniform splats are cheaper for the following instructions. 342 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 343 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 344 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 345 }; 346 347 if (ST->hasAVX2() && 348 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 349 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 350 if (const auto *Entry = 351 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 352 return LT.first * Entry->Cost; 353 } 354 355 static const CostTblEntry SSE2UniformCostTable[] = { 356 // Uniform splats are cheaper for the following instructions. 357 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 358 { ISD::SHL, MVT::v4i32, 1 }, // pslld 359 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 360 361 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 362 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 363 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 364 365 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 366 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 367 }; 368 369 if (ST->hasSSE2() && 370 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 371 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 372 if (const auto *Entry = 373 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 374 return LT.first * Entry->Cost; 375 } 376 377 static const CostTblEntry AVX512DQCostTable[] = { 378 { ISD::MUL, MVT::v2i64, 1 }, 379 { ISD::MUL, MVT::v4i64, 1 }, 380 { ISD::MUL, MVT::v8i64, 1 } 381 }; 382 383 // Look for AVX512DQ lowering tricks for custom cases. 384 if (ST->hasDQI()) 385 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 386 return LT.first * Entry->Cost; 387 388 static const CostTblEntry AVX512BWCostTable[] = { 389 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 390 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 391 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 392 393 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 394 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 395 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 396 397 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 398 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 399 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 400 401 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 402 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 403 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 404 405 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence. 406 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence. 407 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence. 408 409 // Vectorizing division is a bad idea. See the SSE2 table for more comments. 410 { ISD::SDIV, MVT::v64i8, 64*20 }, 411 { ISD::SDIV, MVT::v32i16, 32*20 }, 412 { ISD::UDIV, MVT::v64i8, 64*20 }, 413 { ISD::UDIV, MVT::v32i16, 32*20 } 414 }; 415 416 // Look for AVX512BW lowering tricks for custom cases. 417 if (ST->hasBWI()) 418 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 419 return LT.first * Entry->Cost; 420 421 static const CostTblEntry AVX512CostTable[] = { 422 { ISD::SHL, MVT::v16i32, 1 }, 423 { ISD::SRL, MVT::v16i32, 1 }, 424 { ISD::SRA, MVT::v16i32, 1 }, 425 426 { ISD::SHL, MVT::v8i64, 1 }, 427 { ISD::SRL, MVT::v8i64, 1 }, 428 429 { ISD::SRA, MVT::v2i64, 1 }, 430 { ISD::SRA, MVT::v4i64, 1 }, 431 { ISD::SRA, MVT::v8i64, 1 }, 432 433 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence. 434 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence. 435 { ISD::MUL, MVT::v16i32, 1 }, // pmulld 436 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add 437 438 // Vectorizing division is a bad idea. See the SSE2 table for more comments. 439 { ISD::SDIV, MVT::v16i32, 16*20 }, 440 { ISD::SDIV, MVT::v8i64, 8*20 }, 441 { ISD::UDIV, MVT::v16i32, 16*20 }, 442 { ISD::UDIV, MVT::v8i64, 8*20 } 443 }; 444 445 if (ST->hasAVX512()) 446 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 447 return LT.first * Entry->Cost; 448 449 static const CostTblEntry AVX2ShiftCostTable[] = { 450 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 451 // customize them to detect the cases where shift amount is a scalar one. 452 { ISD::SHL, MVT::v4i32, 1 }, 453 { ISD::SRL, MVT::v4i32, 1 }, 454 { ISD::SRA, MVT::v4i32, 1 }, 455 { ISD::SHL, MVT::v8i32, 1 }, 456 { ISD::SRL, MVT::v8i32, 1 }, 457 { ISD::SRA, MVT::v8i32, 1 }, 458 { ISD::SHL, MVT::v2i64, 1 }, 459 { ISD::SRL, MVT::v2i64, 1 }, 460 { ISD::SHL, MVT::v4i64, 1 }, 461 { ISD::SRL, MVT::v4i64, 1 }, 462 }; 463 464 // Look for AVX2 lowering tricks. 465 if (ST->hasAVX2()) { 466 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 467 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 468 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 469 // On AVX2, a packed v16i16 shift left by a constant build_vector 470 // is lowered into a vector multiply (vpmullw). 471 return LT.first; 472 473 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 474 return LT.first * Entry->Cost; 475 } 476 477 static const CostTblEntry XOPShiftCostTable[] = { 478 // 128bit shifts take 1cy, but right shifts require negation beforehand. 479 { ISD::SHL, MVT::v16i8, 1 }, 480 { ISD::SRL, MVT::v16i8, 2 }, 481 { ISD::SRA, MVT::v16i8, 2 }, 482 { ISD::SHL, MVT::v8i16, 1 }, 483 { ISD::SRL, MVT::v8i16, 2 }, 484 { ISD::SRA, MVT::v8i16, 2 }, 485 { ISD::SHL, MVT::v4i32, 1 }, 486 { ISD::SRL, MVT::v4i32, 2 }, 487 { ISD::SRA, MVT::v4i32, 2 }, 488 { ISD::SHL, MVT::v2i64, 1 }, 489 { ISD::SRL, MVT::v2i64, 2 }, 490 { ISD::SRA, MVT::v2i64, 2 }, 491 // 256bit shifts require splitting if AVX2 didn't catch them above. 492 { ISD::SHL, MVT::v32i8, 2+2 }, 493 { ISD::SRL, MVT::v32i8, 4+2 }, 494 { ISD::SRA, MVT::v32i8, 4+2 }, 495 { ISD::SHL, MVT::v16i16, 2+2 }, 496 { ISD::SRL, MVT::v16i16, 4+2 }, 497 { ISD::SRA, MVT::v16i16, 4+2 }, 498 { ISD::SHL, MVT::v8i32, 2+2 }, 499 { ISD::SRL, MVT::v8i32, 4+2 }, 500 { ISD::SRA, MVT::v8i32, 4+2 }, 501 { ISD::SHL, MVT::v4i64, 2+2 }, 502 { ISD::SRL, MVT::v4i64, 4+2 }, 503 { ISD::SRA, MVT::v4i64, 4+2 }, 504 }; 505 506 // Look for XOP lowering tricks. 507 if (ST->hasXOP()) 508 if (const auto *Entry = CostTableLookup(XOPShiftCostTable, ISD, LT.second)) 509 return LT.first * Entry->Cost; 510 511 static const CostTblEntry SSE2UniformShiftCostTable[] = { 512 // Uniform splats are cheaper for the following instructions. 513 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 514 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 515 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 516 517 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 518 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 519 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 520 521 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 522 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 523 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 524 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 525 }; 526 527 if (ST->hasSSE2() && 528 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 529 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 530 531 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 532 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 533 return LT.first * 4; // 2*psrad + shuffle. 534 535 if (const auto *Entry = 536 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 537 return LT.first * Entry->Cost; 538 } 539 540 if (ISD == ISD::SHL && 541 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 542 MVT VT = LT.second; 543 // Vector shift left by non uniform constant can be lowered 544 // into vector multiply. 545 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 546 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 547 ISD = ISD::MUL; 548 } 549 550 static const CostTblEntry AVX2CostTable[] = { 551 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. 552 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 553 554 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. 555 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 556 557 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. 558 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. 559 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. 560 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 561 562 { ISD::SUB, MVT::v32i8, 1 }, // psubb 563 { ISD::ADD, MVT::v32i8, 1 }, // paddb 564 { ISD::SUB, MVT::v16i16, 1 }, // psubw 565 { ISD::ADD, MVT::v16i16, 1 }, // paddw 566 { ISD::SUB, MVT::v8i32, 1 }, // psubd 567 { ISD::ADD, MVT::v8i32, 1 }, // paddd 568 { ISD::SUB, MVT::v4i64, 1 }, // psubq 569 { ISD::ADD, MVT::v4i64, 1 }, // paddq 570 571 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence. 572 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence. 573 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 574 { ISD::MUL, MVT::v8i32, 1 }, // pmulld 575 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add 576 577 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 578 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 579 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 580 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 581 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 582 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 583 }; 584 585 // Look for AVX2 lowering tricks for custom cases. 586 if (ST->hasAVX2()) 587 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 588 return LT.first * Entry->Cost; 589 590 static const CostTblEntry AVX1CostTable[] = { 591 // We don't have to scalarize unsupported ops. We can issue two half-sized 592 // operations and we only need to extract the upper YMM half. 593 // Two ops + 1 extract + 1 insert = 4. 594 { ISD::MUL, MVT::v16i16, 4 }, 595 { ISD::MUL, MVT::v8i32, 4 }, 596 { ISD::SUB, MVT::v32i8, 4 }, 597 { ISD::ADD, MVT::v32i8, 4 }, 598 { ISD::SUB, MVT::v16i16, 4 }, 599 { ISD::ADD, MVT::v16i16, 4 }, 600 { ISD::SUB, MVT::v8i32, 4 }, 601 { ISD::ADD, MVT::v8i32, 4 }, 602 { ISD::SUB, MVT::v4i64, 4 }, 603 { ISD::ADD, MVT::v4i64, 4 }, 604 605 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 606 // are lowered as a series of long multiplies(3), shifts(3) and adds(2) 607 // Because we believe v4i64 to be a legal type, we must also include the 608 // extract+insert in the cost table. Therefore, the cost here is 18 609 // instead of 8. 610 { ISD::MUL, MVT::v4i64, 18 }, 611 612 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence. 613 614 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 615 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 616 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 617 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 618 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 619 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 620 621 // Vectorizing division is a bad idea. See the SSE2 table for more comments. 622 { ISD::SDIV, MVT::v32i8, 32*20 }, 623 { ISD::SDIV, MVT::v16i16, 16*20 }, 624 { ISD::SDIV, MVT::v8i32, 8*20 }, 625 { ISD::SDIV, MVT::v4i64, 4*20 }, 626 { ISD::UDIV, MVT::v32i8, 32*20 }, 627 { ISD::UDIV, MVT::v16i16, 16*20 }, 628 { ISD::UDIV, MVT::v8i32, 8*20 }, 629 { ISD::UDIV, MVT::v4i64, 4*20 }, 630 }; 631 632 if (ST->hasAVX()) 633 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 634 return LT.first * Entry->Cost; 635 636 static const CostTblEntry SSE42CostTable[] = { 637 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 638 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 639 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 640 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 641 }; 642 643 if (ST->hasSSE42()) 644 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 645 return LT.first * Entry->Cost; 646 647 static const CostTblEntry SSE41CostTable[] = { 648 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 649 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split. 650 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 651 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 652 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 653 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split 654 655 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 656 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split. 657 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 658 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 659 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 660 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split. 661 662 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 663 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split. 664 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 665 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 666 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 667 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split. 668 669 { ISD::MUL, MVT::v4i32, 1 } // pmulld 670 }; 671 672 if (ST->hasSSE41()) 673 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 674 return LT.first * Entry->Cost; 675 676 static const CostTblEntry SSE2CostTable[] = { 677 // We don't correctly identify costs of casts because they are marked as 678 // custom. 679 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 680 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 681 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 682 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 683 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 684 685 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 686 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 687 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 688 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 689 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 690 691 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 692 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 693 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 694 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 695 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split. 696 697 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence. 698 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 699 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 700 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 701 702 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 703 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 704 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 705 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 706 707 // It is not a good idea to vectorize division. We have to scalarize it and 708 // in the process we will often end up having to spilling regular 709 // registers. The overhead of division is going to dominate most kernels 710 // anyways so try hard to prevent vectorization of division - it is 711 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 712 // to hide "20 cycles" for each lane. 713 { ISD::SDIV, MVT::v16i8, 16*20 }, 714 { ISD::SDIV, MVT::v8i16, 8*20 }, 715 { ISD::SDIV, MVT::v4i32, 4*20 }, 716 { ISD::SDIV, MVT::v2i64, 2*20 }, 717 { ISD::UDIV, MVT::v16i8, 16*20 }, 718 { ISD::UDIV, MVT::v8i16, 8*20 }, 719 { ISD::UDIV, MVT::v4i32, 4*20 }, 720 { ISD::UDIV, MVT::v2i64, 2*20 }, 721 }; 722 723 if (ST->hasSSE2()) 724 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 725 return LT.first * Entry->Cost; 726 727 static const CostTblEntry SSE1CostTable[] = { 728 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 729 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 730 }; 731 732 if (ST->hasSSE1()) 733 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 734 return LT.first * Entry->Cost; 735 736 // Fallback to the default implementation. 737 return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info); 738 } 739 740 int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, 741 Type *SubTp) { 742 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 743 // 64-bit packed integer vectors (v2i32) are promoted to type v2i64. 744 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp); 745 746 // For Broadcasts we are splatting the first element from the first input 747 // register, so only need to reference that input and all the output 748 // registers are the same. 749 if (Kind == TTI::SK_Broadcast) 750 LT.first = 1; 751 752 // We are going to permute multiple sources and the result will be in multiple 753 // destinations. Providing an accurate cost only for splits where the element 754 // type remains the same. 755 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 756 MVT LegalVT = LT.second; 757 if (LegalVT.getVectorElementType().getSizeInBits() == 758 Tp->getVectorElementType()->getPrimitiveSizeInBits() && 759 LegalVT.getVectorNumElements() < Tp->getVectorNumElements()) { 760 761 unsigned VecTySize = DL.getTypeStoreSize(Tp); 762 unsigned LegalVTSize = LegalVT.getStoreSize(); 763 // Number of source vectors after legalization: 764 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 765 // Number of destination vectors after legalization: 766 unsigned NumOfDests = LT.first; 767 768 Type *SingleOpTy = VectorType::get(Tp->getVectorElementType(), 769 LegalVT.getVectorNumElements()); 770 771 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 772 return NumOfShuffles * 773 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 0, nullptr); 774 } 775 776 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 777 } 778 779 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 780 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 781 // We assume that source and destination have the same vector type. 782 int NumOfDests = LT.first; 783 int NumOfShufflesPerDest = LT.first * 2 - 1; 784 LT.first = NumOfDests * NumOfShufflesPerDest; 785 } 786 787 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 788 { TTI::SK_Reverse, MVT::v64i8, 1 }, // vpermb 789 { TTI::SK_Reverse, MVT::v32i8, 1 }, // vpermb 790 791 { TTI::SK_PermuteSingleSrc, MVT::v64i8, 1 }, // vpermb 792 { TTI::SK_PermuteSingleSrc, MVT::v32i8, 1 }, // vpermb 793 794 { TTI::SK_PermuteTwoSrc, MVT::v64i8, 1 }, // vpermt2b 795 { TTI::SK_PermuteTwoSrc, MVT::v32i8, 1 }, // vpermt2b 796 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 1 } // vpermt2b 797 }; 798 799 if (ST->hasVBMI()) 800 if (const auto *Entry = 801 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 802 return LT.first * Entry->Cost; 803 804 static const CostTblEntry AVX512BWShuffleTbl[] = { 805 { TTI::SK_Broadcast, MVT::v32i16, 1 }, // vpbroadcastw 806 { TTI::SK_Broadcast, MVT::v64i8, 1 }, // vpbroadcastb 807 808 { TTI::SK_Reverse, MVT::v32i16, 1 }, // vpermw 809 { TTI::SK_Reverse, MVT::v16i16, 1 }, // vpermw 810 { TTI::SK_Reverse, MVT::v64i8, 2 }, // pshufb + vshufi64x2 811 812 { TTI::SK_PermuteSingleSrc, MVT::v32i16, 1 }, // vpermw 813 { TTI::SK_PermuteSingleSrc, MVT::v16i16, 1 }, // vpermw 814 { TTI::SK_PermuteSingleSrc, MVT::v8i16, 1 }, // vpermw 815 { TTI::SK_PermuteSingleSrc, MVT::v64i8, 8 }, // extend to v32i16 816 { TTI::SK_PermuteSingleSrc, MVT::v32i8, 3 }, // vpermw + zext/trunc 817 818 { TTI::SK_PermuteTwoSrc, MVT::v32i16, 1 }, // vpermt2w 819 { TTI::SK_PermuteTwoSrc, MVT::v16i16, 1 }, // vpermt2w 820 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 1 }, // vpermt2w 821 { TTI::SK_PermuteTwoSrc, MVT::v32i8, 3 }, // zext + vpermt2w + trunc 822 { TTI::SK_PermuteTwoSrc, MVT::v64i8, 19 }, // 6 * v32i8 + 1 823 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 3 } // zext + vpermt2w + trunc 824 }; 825 826 if (ST->hasBWI()) 827 if (const auto *Entry = 828 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 829 return LT.first * Entry->Cost; 830 831 static const CostTblEntry AVX512ShuffleTbl[] = { 832 { TTI::SK_Broadcast, MVT::v8f64, 1 }, // vbroadcastpd 833 { TTI::SK_Broadcast, MVT::v16f32, 1 }, // vbroadcastps 834 { TTI::SK_Broadcast, MVT::v8i64, 1 }, // vpbroadcastq 835 { TTI::SK_Broadcast, MVT::v16i32, 1 }, // vpbroadcastd 836 837 { TTI::SK_Reverse, MVT::v8f64, 1 }, // vpermpd 838 { TTI::SK_Reverse, MVT::v16f32, 1 }, // vpermps 839 { TTI::SK_Reverse, MVT::v8i64, 1 }, // vpermq 840 { TTI::SK_Reverse, MVT::v16i32, 1 }, // vpermd 841 842 { TTI::SK_PermuteSingleSrc, MVT::v8f64, 1 }, // vpermpd 843 { TTI::SK_PermuteSingleSrc, MVT::v4f64, 1 }, // vpermpd 844 { TTI::SK_PermuteSingleSrc, MVT::v2f64, 1 }, // vpermpd 845 { TTI::SK_PermuteSingleSrc, MVT::v16f32, 1 }, // vpermps 846 { TTI::SK_PermuteSingleSrc, MVT::v8f32, 1 }, // vpermps 847 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // vpermps 848 { TTI::SK_PermuteSingleSrc, MVT::v8i64, 1 }, // vpermq 849 { TTI::SK_PermuteSingleSrc, MVT::v4i64, 1 }, // vpermq 850 { TTI::SK_PermuteSingleSrc, MVT::v2i64, 1 }, // vpermq 851 { TTI::SK_PermuteSingleSrc, MVT::v16i32, 1 }, // vpermd 852 { TTI::SK_PermuteSingleSrc, MVT::v8i32, 1 }, // vpermd 853 { TTI::SK_PermuteSingleSrc, MVT::v4i32, 1 }, // vpermd 854 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 1 }, // pshufb 855 856 { TTI::SK_PermuteTwoSrc, MVT::v8f64, 1 }, // vpermt2pd 857 { TTI::SK_PermuteTwoSrc, MVT::v16f32, 1 }, // vpermt2ps 858 { TTI::SK_PermuteTwoSrc, MVT::v8i64, 1 }, // vpermt2q 859 { TTI::SK_PermuteTwoSrc, MVT::v16i32, 1 }, // vpermt2d 860 { TTI::SK_PermuteTwoSrc, MVT::v4f64, 1 }, // vpermt2pd 861 { TTI::SK_PermuteTwoSrc, MVT::v8f32, 1 }, // vpermt2ps 862 { TTI::SK_PermuteTwoSrc, MVT::v4i64, 1 }, // vpermt2q 863 { TTI::SK_PermuteTwoSrc, MVT::v8i32, 1 }, // vpermt2d 864 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // vpermt2pd 865 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 1 }, // vpermt2ps 866 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // vpermt2q 867 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 1 } // vpermt2d 868 }; 869 870 if (ST->hasAVX512()) 871 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 872 return LT.first * Entry->Cost; 873 874 static const CostTblEntry AVX2ShuffleTbl[] = { 875 { TTI::SK_Broadcast, MVT::v4f64, 1 }, // vbroadcastpd 876 { TTI::SK_Broadcast, MVT::v8f32, 1 }, // vbroadcastps 877 { TTI::SK_Broadcast, MVT::v4i64, 1 }, // vpbroadcastq 878 { TTI::SK_Broadcast, MVT::v8i32, 1 }, // vpbroadcastd 879 { TTI::SK_Broadcast, MVT::v16i16, 1 }, // vpbroadcastw 880 { TTI::SK_Broadcast, MVT::v32i8, 1 }, // vpbroadcastb 881 882 { TTI::SK_Reverse, MVT::v4f64, 1 }, // vpermpd 883 { TTI::SK_Reverse, MVT::v8f32, 1 }, // vpermps 884 { TTI::SK_Reverse, MVT::v4i64, 1 }, // vpermq 885 { TTI::SK_Reverse, MVT::v8i32, 1 }, // vpermd 886 { TTI::SK_Reverse, MVT::v16i16, 2 }, // vperm2i128 + pshufb 887 { TTI::SK_Reverse, MVT::v32i8, 2 }, // vperm2i128 + pshufb 888 889 { TTI::SK_Alternate, MVT::v16i16, 1 }, // vpblendw 890 { TTI::SK_Alternate, MVT::v32i8, 1 }, // vpblendvb 891 892 { TTI::SK_PermuteSingleSrc, MVT::v4f64, 1 }, // vpermpd 893 { TTI::SK_PermuteSingleSrc, MVT::v8f32, 1 }, // vpermps 894 { TTI::SK_PermuteSingleSrc, MVT::v4i64, 1 }, // vpermq 895 { TTI::SK_PermuteSingleSrc, MVT::v8i32, 1 }, // vpermd 896 { TTI::SK_PermuteSingleSrc, MVT::v16i16, 4 }, // vperm2i128 + 2*vpshufb 897 // + vpblendvb 898 { TTI::SK_PermuteSingleSrc, MVT::v32i8, 4 }, // vperm2i128 + 2*vpshufb 899 // + vpblendvb 900 901 { TTI::SK_PermuteTwoSrc, MVT::v4f64, 3 }, // 2*vpermpd + vblendpd 902 { TTI::SK_PermuteTwoSrc, MVT::v8f32, 3 }, // 2*vpermps + vblendps 903 { TTI::SK_PermuteTwoSrc, MVT::v4i64, 3 }, // 2*vpermq + vpblendd 904 { TTI::SK_PermuteTwoSrc, MVT::v8i32, 3 }, // 2*vpermd + vpblendd 905 { TTI::SK_PermuteTwoSrc, MVT::v16i16, 7 }, // 2*vperm2i128 + 4*vpshufb 906 // + vpblendvb 907 { TTI::SK_PermuteTwoSrc, MVT::v32i8, 7 }, // 2*vperm2i128 + 4*vpshufb 908 // + vpblendvb 909 }; 910 911 if (ST->hasAVX2()) 912 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 913 return LT.first * Entry->Cost; 914 915 static const CostTblEntry XOPShuffleTbl[] = { 916 { TTI::SK_PermuteSingleSrc, MVT::v4f64, 2 }, // vperm2f128 + vpermil2pd 917 { TTI::SK_PermuteSingleSrc, MVT::v8f32, 2 }, // vperm2f128 + vpermil2ps 918 { TTI::SK_PermuteSingleSrc, MVT::v4i64, 2 }, // vperm2f128 + vpermil2pd 919 { TTI::SK_PermuteSingleSrc, MVT::v8i32, 2 }, // vperm2f128 + vpermil2ps 920 { TTI::SK_PermuteSingleSrc, MVT::v16i16, 4 }, // vextractf128 + 2*vpperm 921 // + vinsertf128 922 { TTI::SK_PermuteSingleSrc, MVT::v32i8, 4 }, // vextractf128 + 2*vpperm 923 // + vinsertf128 924 925 { TTI::SK_PermuteTwoSrc, MVT::v16i16, 9 }, // 2*vextractf128 + 6*vpperm 926 // + vinsertf128 927 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 1 }, // vpperm 928 { TTI::SK_PermuteTwoSrc, MVT::v32i8, 9 }, // 2*vextractf128 + 6*vpperm 929 // + vinsertf128 930 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 1 }, // vpperm 931 }; 932 933 if (ST->hasXOP()) 934 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 935 return LT.first * Entry->Cost; 936 937 static const CostTblEntry AVX1ShuffleTbl[] = { 938 { TTI::SK_Broadcast, MVT::v4f64, 2 }, // vperm2f128 + vpermilpd 939 { TTI::SK_Broadcast, MVT::v8f32, 2 }, // vperm2f128 + vpermilps 940 { TTI::SK_Broadcast, MVT::v4i64, 2 }, // vperm2f128 + vpermilpd 941 { TTI::SK_Broadcast, MVT::v8i32, 2 }, // vperm2f128 + vpermilps 942 { TTI::SK_Broadcast, MVT::v16i16, 3 }, // vpshuflw + vpshufd + vinsertf128 943 { TTI::SK_Broadcast, MVT::v32i8, 2 }, // vpshufb + vinsertf128 944 945 { TTI::SK_Reverse, MVT::v4f64, 2 }, // vperm2f128 + vpermilpd 946 { TTI::SK_Reverse, MVT::v8f32, 2 }, // vperm2f128 + vpermilps 947 { TTI::SK_Reverse, MVT::v4i64, 2 }, // vperm2f128 + vpermilpd 948 { TTI::SK_Reverse, MVT::v8i32, 2 }, // vperm2f128 + vpermilps 949 { TTI::SK_Reverse, MVT::v16i16, 4 }, // vextractf128 + 2*pshufb 950 // + vinsertf128 951 { TTI::SK_Reverse, MVT::v32i8, 4 }, // vextractf128 + 2*pshufb 952 // + vinsertf128 953 954 { TTI::SK_Alternate, MVT::v4i64, 1 }, // vblendpd 955 { TTI::SK_Alternate, MVT::v4f64, 1 }, // vblendpd 956 { TTI::SK_Alternate, MVT::v8i32, 1 }, // vblendps 957 { TTI::SK_Alternate, MVT::v8f32, 1 }, // vblendps 958 { TTI::SK_Alternate, MVT::v16i16, 3 }, // vpand + vpandn + vpor 959 { TTI::SK_Alternate, MVT::v32i8, 3 }, // vpand + vpandn + vpor 960 961 { TTI::SK_PermuteSingleSrc, MVT::v4f64, 3 }, // 2*vperm2f128 + vshufpd 962 { TTI::SK_PermuteSingleSrc, MVT::v4i64, 3 }, // 2*vperm2f128 + vshufpd 963 { TTI::SK_PermuteSingleSrc, MVT::v8f32, 4 }, // 2*vperm2f128 + 2*vshufps 964 { TTI::SK_PermuteSingleSrc, MVT::v8i32, 4 }, // 2*vperm2f128 + 2*vshufps 965 { TTI::SK_PermuteSingleSrc, MVT::v16i16, 8 }, // vextractf128 + 4*pshufb 966 // + 2*por + vinsertf128 967 { TTI::SK_PermuteSingleSrc, MVT::v32i8, 8 }, // vextractf128 + 4*pshufb 968 // + 2*por + vinsertf128 969 970 { TTI::SK_PermuteTwoSrc, MVT::v4f64, 4 }, // 2*vperm2f128 + 2*vshufpd 971 { TTI::SK_PermuteTwoSrc, MVT::v8f32, 4 }, // 2*vperm2f128 + 2*vshufps 972 { TTI::SK_PermuteTwoSrc, MVT::v4i64, 4 }, // 2*vperm2f128 + 2*vshufpd 973 { TTI::SK_PermuteTwoSrc, MVT::v8i32, 4 }, // 2*vperm2f128 + 2*vshufps 974 { TTI::SK_PermuteTwoSrc, MVT::v16i16, 15 }, // 2*vextractf128 + 8*pshufb 975 // + 4*por + vinsertf128 976 { TTI::SK_PermuteTwoSrc, MVT::v32i8, 15 }, // 2*vextractf128 + 8*pshufb 977 // + 4*por + vinsertf128 978 }; 979 980 if (ST->hasAVX()) 981 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 982 return LT.first * Entry->Cost; 983 984 static const CostTblEntry SSE41ShuffleTbl[] = { 985 { TTI::SK_Alternate, MVT::v2i64, 1 }, // pblendw 986 { TTI::SK_Alternate, MVT::v2f64, 1 }, // movsd 987 { TTI::SK_Alternate, MVT::v4i32, 1 }, // pblendw 988 { TTI::SK_Alternate, MVT::v4f32, 1 }, // blendps 989 { TTI::SK_Alternate, MVT::v8i16, 1 }, // pblendw 990 { TTI::SK_Alternate, MVT::v16i8, 1 } // pblendvb 991 }; 992 993 if (ST->hasSSE41()) 994 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 995 return LT.first * Entry->Cost; 996 997 static const CostTblEntry SSSE3ShuffleTbl[] = { 998 { TTI::SK_Broadcast, MVT::v8i16, 1 }, // pshufb 999 { TTI::SK_Broadcast, MVT::v16i8, 1 }, // pshufb 1000 1001 { TTI::SK_Reverse, MVT::v8i16, 1 }, // pshufb 1002 { TTI::SK_Reverse, MVT::v16i8, 1 }, // pshufb 1003 1004 { TTI::SK_Alternate, MVT::v8i16, 3 }, // 2*pshufb + por 1005 { TTI::SK_Alternate, MVT::v16i8, 3 }, // 2*pshufb + por 1006 1007 { TTI::SK_PermuteSingleSrc, MVT::v8i16, 1 }, // pshufb 1008 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 1 }, // pshufb 1009 1010 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 3 }, // 2*pshufb + por 1011 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 3 }, // 2*pshufb + por 1012 }; 1013 1014 if (ST->hasSSSE3()) 1015 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1016 return LT.first * Entry->Cost; 1017 1018 static const CostTblEntry SSE2ShuffleTbl[] = { 1019 { TTI::SK_Broadcast, MVT::v2f64, 1 }, // shufpd 1020 { TTI::SK_Broadcast, MVT::v2i64, 1 }, // pshufd 1021 { TTI::SK_Broadcast, MVT::v4i32, 1 }, // pshufd 1022 { TTI::SK_Broadcast, MVT::v8i16, 2 }, // pshuflw + pshufd 1023 { TTI::SK_Broadcast, MVT::v16i8, 3 }, // unpck + pshuflw + pshufd 1024 1025 { TTI::SK_Reverse, MVT::v2f64, 1 }, // shufpd 1026 { TTI::SK_Reverse, MVT::v2i64, 1 }, // pshufd 1027 { TTI::SK_Reverse, MVT::v4i32, 1 }, // pshufd 1028 { TTI::SK_Reverse, MVT::v8i16, 3 }, // pshuflw + pshufhw + pshufd 1029 { TTI::SK_Reverse, MVT::v16i8, 9 }, // 2*pshuflw + 2*pshufhw 1030 // + 2*pshufd + 2*unpck + packus 1031 1032 { TTI::SK_Alternate, MVT::v2i64, 1 }, // movsd 1033 { TTI::SK_Alternate, MVT::v2f64, 1 }, // movsd 1034 { TTI::SK_Alternate, MVT::v4i32, 2 }, // 2*shufps 1035 { TTI::SK_Alternate, MVT::v8i16, 3 }, // pand + pandn + por 1036 { TTI::SK_Alternate, MVT::v16i8, 3 }, // pand + pandn + por 1037 1038 { TTI::SK_PermuteSingleSrc, MVT::v2f64, 1 }, // shufpd 1039 { TTI::SK_PermuteSingleSrc, MVT::v2i64, 1 }, // pshufd 1040 { TTI::SK_PermuteSingleSrc, MVT::v4i32, 1 }, // pshufd 1041 { TTI::SK_PermuteSingleSrc, MVT::v8i16, 5 }, // 2*pshuflw + 2*pshufhw 1042 // + pshufd/unpck 1043 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1044 // + 2*pshufd + 2*unpck + 2*packus 1045 1046 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1047 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1048 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1049 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1050 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1051 }; 1052 1053 if (ST->hasSSE2()) 1054 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1055 return LT.first * Entry->Cost; 1056 1057 static const CostTblEntry SSE1ShuffleTbl[] = { 1058 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1059 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1060 { TTI::SK_Alternate, MVT::v4f32, 2 }, // 2*shufps 1061 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1062 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1063 }; 1064 1065 if (ST->hasSSE1()) 1066 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1067 return LT.first * Entry->Cost; 1068 1069 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 1070 } 1071 1072 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 1073 const Instruction *I) { 1074 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1075 assert(ISD && "Invalid opcode"); 1076 1077 // FIXME: Need a better design of the cost table to handle non-simple types of 1078 // potential massive combinations (elem_num x src_type x dst_type). 1079 1080 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1081 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1082 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1083 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1084 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1085 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1086 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1087 1088 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1089 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1090 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1091 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1092 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1093 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1094 1095 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1096 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1097 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1098 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1099 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1100 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1101 1102 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1103 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1104 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1105 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1106 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1107 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1108 }; 1109 1110 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1111 // 256-bit wide vectors. 1112 1113 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1114 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1115 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1116 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1117 1118 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 }, 1119 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 }, 1120 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 }, 1121 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 1122 1123 // v16i1 -> v16i32 - load + broadcast 1124 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1125 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1126 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1127 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1128 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1129 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1130 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1131 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1132 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1133 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1134 1135 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1136 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1137 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1138 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1139 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1140 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1141 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1142 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1143 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1144 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 26 }, 1145 1146 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1147 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1148 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1149 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1150 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1151 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1152 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1153 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1154 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1155 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1156 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1157 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1158 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1159 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1160 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1161 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1162 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1163 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1164 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1165 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1166 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1167 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 12 }, 1168 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 26 }, 1169 1170 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1171 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1172 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1173 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1174 }; 1175 1176 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1177 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1178 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1179 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1180 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1181 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 1182 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 1183 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 1184 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 1185 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1186 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1187 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1188 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1189 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1190 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1191 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1192 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1193 1194 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 1195 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 1196 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1197 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 1198 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1199 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 }, 1200 1201 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1202 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1203 1204 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1205 }; 1206 1207 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1208 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1209 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1210 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1211 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1212 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 }, 1213 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1214 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 7 }, 1215 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1216 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1217 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1218 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 }, 1219 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1220 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1221 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1222 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1223 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1224 1225 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 1226 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1227 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1228 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1229 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 1230 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 }, 1231 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 }, 1232 1233 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1234 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1235 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1236 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1237 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1238 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1239 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1240 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1241 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1242 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1243 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1244 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1245 1246 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1247 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1248 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1249 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1250 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1251 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1252 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1253 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1254 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1255 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 }, 1256 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 1257 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1258 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 1259 // The generic code to compute the scalar overhead is currently broken. 1260 // Workaround this limitation by estimating the scalarization overhead 1261 // here. We have roughly 10 instructions per scalar element. 1262 // Multiply that by the vector width. 1263 // FIXME: remove that when PR19268 is fixed. 1264 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 10 }, 1265 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 20 }, 1266 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1267 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1268 1269 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 }, 1270 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 }, 1271 // This node is expanded into scalarized operations but BasicTTI is overly 1272 // optimistic estimating its cost. It computes 3 per element (one 1273 // vector-extract, one scalar conversion and one vector-insert). The 1274 // problem is that the inserts form a read-modify-write chain so latency 1275 // should be factored in too. Inflating the cost per element by 1. 1276 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, 1277 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 1278 1279 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 1280 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 1281 }; 1282 1283 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 1284 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1285 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1286 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1287 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1288 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1289 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1290 1291 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1292 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 }, 1293 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1294 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1295 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1296 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1297 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1298 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1299 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1300 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1301 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1302 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1303 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1304 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1305 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1306 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1307 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1308 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1309 1310 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, 1311 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 1312 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 1313 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 1314 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 1315 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 1316 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 1317 1318 }; 1319 1320 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 1321 // These are somewhat magic numbers justified by looking at the output of 1322 // Intel's IACA, running some kernels and making sure when we take 1323 // legalization into account the throughput will be overestimated. 1324 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1325 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1326 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1327 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1328 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1329 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1330 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1331 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 1332 1333 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1334 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1335 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1336 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1337 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1338 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, 1339 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 1340 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1341 1342 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 3 }, 1343 1344 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1345 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 1346 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 1347 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 1348 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1349 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 1350 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1351 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 1352 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1353 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1354 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1355 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1356 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 1357 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 1358 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1359 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 1360 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1361 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 1362 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1363 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1364 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 1365 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 1366 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1367 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 1368 1369 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 4 }, 1370 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, 1371 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 1372 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 1373 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 1374 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1375 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 1376 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1377 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 1378 }; 1379 1380 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 1381 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst); 1382 1383 if (ST->hasSSE2() && !ST->hasAVX()) { 1384 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1385 LTDest.second, LTSrc.second)) 1386 return LTSrc.first * Entry->Cost; 1387 } 1388 1389 EVT SrcTy = TLI->getValueType(DL, Src); 1390 EVT DstTy = TLI->getValueType(DL, Dst); 1391 1392 // The function getSimpleVT only handles simple value types. 1393 if (!SrcTy.isSimple() || !DstTy.isSimple()) 1394 return BaseT::getCastInstrCost(Opcode, Dst, Src); 1395 1396 if (ST->hasDQI()) 1397 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 1398 DstTy.getSimpleVT(), 1399 SrcTy.getSimpleVT())) 1400 return Entry->Cost; 1401 1402 if (ST->hasAVX512()) 1403 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 1404 DstTy.getSimpleVT(), 1405 SrcTy.getSimpleVT())) 1406 return Entry->Cost; 1407 1408 if (ST->hasAVX2()) { 1409 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 1410 DstTy.getSimpleVT(), 1411 SrcTy.getSimpleVT())) 1412 return Entry->Cost; 1413 } 1414 1415 if (ST->hasAVX()) { 1416 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 1417 DstTy.getSimpleVT(), 1418 SrcTy.getSimpleVT())) 1419 return Entry->Cost; 1420 } 1421 1422 if (ST->hasSSE41()) { 1423 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 1424 DstTy.getSimpleVT(), 1425 SrcTy.getSimpleVT())) 1426 return Entry->Cost; 1427 } 1428 1429 if (ST->hasSSE2()) { 1430 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1431 DstTy.getSimpleVT(), 1432 SrcTy.getSimpleVT())) 1433 return Entry->Cost; 1434 } 1435 1436 return BaseT::getCastInstrCost(Opcode, Dst, Src); 1437 } 1438 1439 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 1440 const Instruction *I) { 1441 // Legalize the type. 1442 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 1443 1444 MVT MTy = LT.second; 1445 1446 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1447 assert(ISD && "Invalid opcode"); 1448 1449 static const CostTblEntry SSE2CostTbl[] = { 1450 { ISD::SETCC, MVT::v2i64, 8 }, 1451 { ISD::SETCC, MVT::v4i32, 1 }, 1452 { ISD::SETCC, MVT::v8i16, 1 }, 1453 { ISD::SETCC, MVT::v16i8, 1 }, 1454 }; 1455 1456 static const CostTblEntry SSE42CostTbl[] = { 1457 { ISD::SETCC, MVT::v2f64, 1 }, 1458 { ISD::SETCC, MVT::v4f32, 1 }, 1459 { ISD::SETCC, MVT::v2i64, 1 }, 1460 }; 1461 1462 static const CostTblEntry AVX1CostTbl[] = { 1463 { ISD::SETCC, MVT::v4f64, 1 }, 1464 { ISD::SETCC, MVT::v8f32, 1 }, 1465 // AVX1 does not support 8-wide integer compare. 1466 { ISD::SETCC, MVT::v4i64, 4 }, 1467 { ISD::SETCC, MVT::v8i32, 4 }, 1468 { ISD::SETCC, MVT::v16i16, 4 }, 1469 { ISD::SETCC, MVT::v32i8, 4 }, 1470 }; 1471 1472 static const CostTblEntry AVX2CostTbl[] = { 1473 { ISD::SETCC, MVT::v4i64, 1 }, 1474 { ISD::SETCC, MVT::v8i32, 1 }, 1475 { ISD::SETCC, MVT::v16i16, 1 }, 1476 { ISD::SETCC, MVT::v32i8, 1 }, 1477 }; 1478 1479 static const CostTblEntry AVX512CostTbl[] = { 1480 { ISD::SETCC, MVT::v8i64, 1 }, 1481 { ISD::SETCC, MVT::v16i32, 1 }, 1482 { ISD::SETCC, MVT::v8f64, 1 }, 1483 { ISD::SETCC, MVT::v16f32, 1 }, 1484 }; 1485 1486 if (ST->hasAVX512()) 1487 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 1488 return LT.first * Entry->Cost; 1489 1490 if (ST->hasAVX2()) 1491 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 1492 return LT.first * Entry->Cost; 1493 1494 if (ST->hasAVX()) 1495 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 1496 return LT.first * Entry->Cost; 1497 1498 if (ST->hasSSE42()) 1499 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 1500 return LT.first * Entry->Cost; 1501 1502 if (ST->hasSSE2()) 1503 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 1504 return LT.first * Entry->Cost; 1505 1506 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I); 1507 } 1508 1509 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 1510 1511 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 1512 ArrayRef<Type *> Tys, FastMathFlags FMF, 1513 unsigned ScalarizationCostPassed) { 1514 // Costs should match the codegen from: 1515 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 1516 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 1517 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 1518 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 1519 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 1520 static const CostTblEntry AVX512CDCostTbl[] = { 1521 { ISD::CTLZ, MVT::v8i64, 1 }, 1522 { ISD::CTLZ, MVT::v16i32, 1 }, 1523 { ISD::CTLZ, MVT::v32i16, 8 }, 1524 { ISD::CTLZ, MVT::v64i8, 20 }, 1525 { ISD::CTLZ, MVT::v4i64, 1 }, 1526 { ISD::CTLZ, MVT::v8i32, 1 }, 1527 { ISD::CTLZ, MVT::v16i16, 4 }, 1528 { ISD::CTLZ, MVT::v32i8, 10 }, 1529 { ISD::CTLZ, MVT::v2i64, 1 }, 1530 { ISD::CTLZ, MVT::v4i32, 1 }, 1531 { ISD::CTLZ, MVT::v8i16, 4 }, 1532 { ISD::CTLZ, MVT::v16i8, 4 }, 1533 }; 1534 static const CostTblEntry AVX512BWCostTbl[] = { 1535 { ISD::BITREVERSE, MVT::v8i64, 5 }, 1536 { ISD::BITREVERSE, MVT::v16i32, 5 }, 1537 { ISD::BITREVERSE, MVT::v32i16, 5 }, 1538 { ISD::BITREVERSE, MVT::v64i8, 5 }, 1539 { ISD::CTLZ, MVT::v8i64, 23 }, 1540 { ISD::CTLZ, MVT::v16i32, 22 }, 1541 { ISD::CTLZ, MVT::v32i16, 18 }, 1542 { ISD::CTLZ, MVT::v64i8, 17 }, 1543 { ISD::CTPOP, MVT::v8i64, 7 }, 1544 { ISD::CTPOP, MVT::v16i32, 11 }, 1545 { ISD::CTPOP, MVT::v32i16, 9 }, 1546 { ISD::CTPOP, MVT::v64i8, 6 }, 1547 { ISD::CTTZ, MVT::v8i64, 10 }, 1548 { ISD::CTTZ, MVT::v16i32, 14 }, 1549 { ISD::CTTZ, MVT::v32i16, 12 }, 1550 { ISD::CTTZ, MVT::v64i8, 9 }, 1551 }; 1552 static const CostTblEntry AVX512CostTbl[] = { 1553 { ISD::BITREVERSE, MVT::v8i64, 36 }, 1554 { ISD::BITREVERSE, MVT::v16i32, 24 }, 1555 { ISD::CTLZ, MVT::v8i64, 29 }, 1556 { ISD::CTLZ, MVT::v16i32, 35 }, 1557 { ISD::CTPOP, MVT::v8i64, 16 }, 1558 { ISD::CTPOP, MVT::v16i32, 24 }, 1559 { ISD::CTTZ, MVT::v8i64, 20 }, 1560 { ISD::CTTZ, MVT::v16i32, 28 }, 1561 }; 1562 static const CostTblEntry XOPCostTbl[] = { 1563 { ISD::BITREVERSE, MVT::v4i64, 4 }, 1564 { ISD::BITREVERSE, MVT::v8i32, 4 }, 1565 { ISD::BITREVERSE, MVT::v16i16, 4 }, 1566 { ISD::BITREVERSE, MVT::v32i8, 4 }, 1567 { ISD::BITREVERSE, MVT::v2i64, 1 }, 1568 { ISD::BITREVERSE, MVT::v4i32, 1 }, 1569 { ISD::BITREVERSE, MVT::v8i16, 1 }, 1570 { ISD::BITREVERSE, MVT::v16i8, 1 }, 1571 { ISD::BITREVERSE, MVT::i64, 3 }, 1572 { ISD::BITREVERSE, MVT::i32, 3 }, 1573 { ISD::BITREVERSE, MVT::i16, 3 }, 1574 { ISD::BITREVERSE, MVT::i8, 3 } 1575 }; 1576 static const CostTblEntry AVX2CostTbl[] = { 1577 { ISD::BITREVERSE, MVT::v4i64, 5 }, 1578 { ISD::BITREVERSE, MVT::v8i32, 5 }, 1579 { ISD::BITREVERSE, MVT::v16i16, 5 }, 1580 { ISD::BITREVERSE, MVT::v32i8, 5 }, 1581 { ISD::BSWAP, MVT::v4i64, 1 }, 1582 { ISD::BSWAP, MVT::v8i32, 1 }, 1583 { ISD::BSWAP, MVT::v16i16, 1 }, 1584 { ISD::CTLZ, MVT::v4i64, 23 }, 1585 { ISD::CTLZ, MVT::v8i32, 18 }, 1586 { ISD::CTLZ, MVT::v16i16, 14 }, 1587 { ISD::CTLZ, MVT::v32i8, 9 }, 1588 { ISD::CTPOP, MVT::v4i64, 7 }, 1589 { ISD::CTPOP, MVT::v8i32, 11 }, 1590 { ISD::CTPOP, MVT::v16i16, 9 }, 1591 { ISD::CTPOP, MVT::v32i8, 6 }, 1592 { ISD::CTTZ, MVT::v4i64, 10 }, 1593 { ISD::CTTZ, MVT::v8i32, 14 }, 1594 { ISD::CTTZ, MVT::v16i16, 12 }, 1595 { ISD::CTTZ, MVT::v32i8, 9 }, 1596 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 1597 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 1598 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 1599 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 1600 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 1601 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 1602 }; 1603 static const CostTblEntry AVX1CostTbl[] = { 1604 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 1605 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 1606 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 1607 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 1608 { ISD::BSWAP, MVT::v4i64, 4 }, 1609 { ISD::BSWAP, MVT::v8i32, 4 }, 1610 { ISD::BSWAP, MVT::v16i16, 4 }, 1611 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 1612 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 1613 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 1614 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 1615 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 1616 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 1617 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 1618 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 1619 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 1620 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 1621 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 1622 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 1623 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 1624 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 1625 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 1626 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 1627 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 1628 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 1629 }; 1630 static const CostTblEntry SSE42CostTbl[] = { 1631 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 1632 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 1633 }; 1634 static const CostTblEntry SSSE3CostTbl[] = { 1635 { ISD::BITREVERSE, MVT::v2i64, 5 }, 1636 { ISD::BITREVERSE, MVT::v4i32, 5 }, 1637 { ISD::BITREVERSE, MVT::v8i16, 5 }, 1638 { ISD::BITREVERSE, MVT::v16i8, 5 }, 1639 { ISD::BSWAP, MVT::v2i64, 1 }, 1640 { ISD::BSWAP, MVT::v4i32, 1 }, 1641 { ISD::BSWAP, MVT::v8i16, 1 }, 1642 { ISD::CTLZ, MVT::v2i64, 23 }, 1643 { ISD::CTLZ, MVT::v4i32, 18 }, 1644 { ISD::CTLZ, MVT::v8i16, 14 }, 1645 { ISD::CTLZ, MVT::v16i8, 9 }, 1646 { ISD::CTPOP, MVT::v2i64, 7 }, 1647 { ISD::CTPOP, MVT::v4i32, 11 }, 1648 { ISD::CTPOP, MVT::v8i16, 9 }, 1649 { ISD::CTPOP, MVT::v16i8, 6 }, 1650 { ISD::CTTZ, MVT::v2i64, 10 }, 1651 { ISD::CTTZ, MVT::v4i32, 14 }, 1652 { ISD::CTTZ, MVT::v8i16, 12 }, 1653 { ISD::CTTZ, MVT::v16i8, 9 } 1654 }; 1655 static const CostTblEntry SSE2CostTbl[] = { 1656 { ISD::BITREVERSE, MVT::v2i64, 29 }, 1657 { ISD::BITREVERSE, MVT::v4i32, 27 }, 1658 { ISD::BITREVERSE, MVT::v8i16, 27 }, 1659 { ISD::BITREVERSE, MVT::v16i8, 20 }, 1660 { ISD::BSWAP, MVT::v2i64, 7 }, 1661 { ISD::BSWAP, MVT::v4i32, 7 }, 1662 { ISD::BSWAP, MVT::v8i16, 7 }, 1663 { ISD::CTLZ, MVT::v2i64, 25 }, 1664 { ISD::CTLZ, MVT::v4i32, 26 }, 1665 { ISD::CTLZ, MVT::v8i16, 20 }, 1666 { ISD::CTLZ, MVT::v16i8, 17 }, 1667 { ISD::CTPOP, MVT::v2i64, 12 }, 1668 { ISD::CTPOP, MVT::v4i32, 15 }, 1669 { ISD::CTPOP, MVT::v8i16, 13 }, 1670 { ISD::CTPOP, MVT::v16i8, 10 }, 1671 { ISD::CTTZ, MVT::v2i64, 14 }, 1672 { ISD::CTTZ, MVT::v4i32, 18 }, 1673 { ISD::CTTZ, MVT::v8i16, 16 }, 1674 { ISD::CTTZ, MVT::v16i8, 13 }, 1675 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 1676 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 1677 }; 1678 static const CostTblEntry SSE1CostTbl[] = { 1679 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 1680 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 1681 }; 1682 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 1683 { ISD::BITREVERSE, MVT::i64, 14 } 1684 }; 1685 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 1686 { ISD::BITREVERSE, MVT::i32, 14 }, 1687 { ISD::BITREVERSE, MVT::i16, 14 }, 1688 { ISD::BITREVERSE, MVT::i8, 11 } 1689 }; 1690 1691 unsigned ISD = ISD::DELETED_NODE; 1692 switch (IID) { 1693 default: 1694 break; 1695 case Intrinsic::bitreverse: 1696 ISD = ISD::BITREVERSE; 1697 break; 1698 case Intrinsic::bswap: 1699 ISD = ISD::BSWAP; 1700 break; 1701 case Intrinsic::ctlz: 1702 ISD = ISD::CTLZ; 1703 break; 1704 case Intrinsic::ctpop: 1705 ISD = ISD::CTPOP; 1706 break; 1707 case Intrinsic::cttz: 1708 ISD = ISD::CTTZ; 1709 break; 1710 case Intrinsic::sqrt: 1711 ISD = ISD::FSQRT; 1712 break; 1713 } 1714 1715 // Legalize the type. 1716 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 1717 MVT MTy = LT.second; 1718 1719 // Attempt to lookup cost. 1720 if (ST->hasCDI()) 1721 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 1722 return LT.first * Entry->Cost; 1723 1724 if (ST->hasBWI()) 1725 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 1726 return LT.first * Entry->Cost; 1727 1728 if (ST->hasAVX512()) 1729 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 1730 return LT.first * Entry->Cost; 1731 1732 if (ST->hasXOP()) 1733 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 1734 return LT.first * Entry->Cost; 1735 1736 if (ST->hasAVX2()) 1737 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 1738 return LT.first * Entry->Cost; 1739 1740 if (ST->hasAVX()) 1741 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 1742 return LT.first * Entry->Cost; 1743 1744 if (ST->hasSSE42()) 1745 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 1746 return LT.first * Entry->Cost; 1747 1748 if (ST->hasSSSE3()) 1749 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 1750 return LT.first * Entry->Cost; 1751 1752 if (ST->hasSSE2()) 1753 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 1754 return LT.first * Entry->Cost; 1755 1756 if (ST->hasSSE1()) 1757 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 1758 return LT.first * Entry->Cost; 1759 1760 if (ST->is64Bit()) 1761 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 1762 return LT.first * Entry->Cost; 1763 1764 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 1765 return LT.first * Entry->Cost; 1766 1767 return BaseT::getIntrinsicInstrCost(IID, RetTy, Tys, FMF, ScalarizationCostPassed); 1768 } 1769 1770 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 1771 ArrayRef<Value *> Args, FastMathFlags FMF, unsigned VF) { 1772 return BaseT::getIntrinsicInstrCost(IID, RetTy, Args, FMF, VF); 1773 } 1774 1775 int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { 1776 assert(Val->isVectorTy() && "This must be a vector type"); 1777 1778 Type *ScalarType = Val->getScalarType(); 1779 1780 if (Index != -1U) { 1781 // Legalize the type. 1782 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 1783 1784 // This type is legalized to a scalar type. 1785 if (!LT.second.isVector()) 1786 return 0; 1787 1788 // The type may be split. Normalize the index to the new type. 1789 unsigned Width = LT.second.getVectorNumElements(); 1790 Index = Index % Width; 1791 1792 // Floating point scalars are already located in index #0. 1793 if (ScalarType->isFloatingPointTy() && Index == 0) 1794 return 0; 1795 } 1796 1797 // Add to the base cost if we know that the extracted element of a vector is 1798 // destined to be moved to and used in the integer register file. 1799 int RegisterFileMoveCost = 0; 1800 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 1801 RegisterFileMoveCost = 1; 1802 1803 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 1804 } 1805 1806 int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, 1807 unsigned AddressSpace, const Instruction *I) { 1808 // Handle non-power-of-two vectors such as <3 x float> 1809 if (VectorType *VTy = dyn_cast<VectorType>(Src)) { 1810 unsigned NumElem = VTy->getVectorNumElements(); 1811 1812 // Handle a few common cases: 1813 // <3 x float> 1814 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 1815 // Cost = 64 bit store + extract + 32 bit store. 1816 return 3; 1817 1818 // <3 x double> 1819 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 1820 // Cost = 128 bit store + unpack + 64 bit store. 1821 return 3; 1822 1823 // Assume that all other non-power-of-two numbers are scalarized. 1824 if (!isPowerOf2_32(NumElem)) { 1825 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment, 1826 AddressSpace); 1827 int SplitCost = getScalarizationOverhead(Src, Opcode == Instruction::Load, 1828 Opcode == Instruction::Store); 1829 return NumElem * Cost + SplitCost; 1830 } 1831 } 1832 1833 // Legalize the type. 1834 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 1835 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 1836 "Invalid Opcode"); 1837 1838 // Each load/store unit costs 1. 1839 int Cost = LT.first * 1; 1840 1841 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a 1842 // proxy for a double-pumped AVX memory interface such as on Sandybridge. 1843 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow()) 1844 Cost *= 2; 1845 1846 return Cost; 1847 } 1848 1849 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, 1850 unsigned Alignment, 1851 unsigned AddressSpace) { 1852 VectorType *SrcVTy = dyn_cast<VectorType>(SrcTy); 1853 if (!SrcVTy) 1854 // To calculate scalar take the regular cost, without mask 1855 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace); 1856 1857 unsigned NumElem = SrcVTy->getVectorNumElements(); 1858 VectorType *MaskTy = 1859 VectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 1860 if ((Opcode == Instruction::Load && !isLegalMaskedLoad(SrcVTy)) || 1861 (Opcode == Instruction::Store && !isLegalMaskedStore(SrcVTy)) || 1862 !isPowerOf2_32(NumElem)) { 1863 // Scalarization 1864 int MaskSplitCost = getScalarizationOverhead(MaskTy, false, true); 1865 int ScalarCompareCost = getCmpSelInstrCost( 1866 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr); 1867 int BranchCost = getCFInstrCost(Instruction::Br); 1868 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 1869 1870 int ValueSplitCost = getScalarizationOverhead( 1871 SrcVTy, Opcode == Instruction::Load, Opcode == Instruction::Store); 1872 int MemopCost = 1873 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 1874 Alignment, AddressSpace); 1875 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 1876 } 1877 1878 // Legalize the type. 1879 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 1880 auto VT = TLI->getValueType(DL, SrcVTy); 1881 int Cost = 0; 1882 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 1883 LT.second.getVectorNumElements() == NumElem) 1884 // Promotion requires expand/truncate for data and a shuffle for mask. 1885 Cost += getShuffleCost(TTI::SK_Alternate, SrcVTy, 0, nullptr) + 1886 getShuffleCost(TTI::SK_Alternate, MaskTy, 0, nullptr); 1887 1888 else if (LT.second.getVectorNumElements() > NumElem) { 1889 VectorType *NewMaskTy = VectorType::get(MaskTy->getVectorElementType(), 1890 LT.second.getVectorNumElements()); 1891 // Expanding requires fill mask with zeroes 1892 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, 0, MaskTy); 1893 } 1894 if (!ST->hasAVX512()) 1895 return Cost + LT.first*4; // Each maskmov costs 4 1896 1897 // AVX-512 masked load/store is cheapper 1898 return Cost+LT.first; 1899 } 1900 1901 int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE, 1902 const SCEV *Ptr) { 1903 // Address computations in vectorized code with non-consecutive addresses will 1904 // likely result in more instructions compared to scalar code where the 1905 // computation can more often be merged into the index mode. The resulting 1906 // extra micro-ops can significantly decrease throughput. 1907 unsigned NumVectorInstToHideOverhead = 10; 1908 1909 // Cost modeling of Strided Access Computation is hidden by the indexing 1910 // modes of X86 regardless of the stride value. We dont believe that there 1911 // is a difference between constant strided access in gerenal and constant 1912 // strided value which is less than or equal to 64. 1913 // Even in the case of (loop invariant) stride whose value is not known at 1914 // compile time, the address computation will not incur more than one extra 1915 // ADD instruction. 1916 if (Ty->isVectorTy() && SE) { 1917 if (!BaseT::isStridedAccess(Ptr)) 1918 return NumVectorInstToHideOverhead; 1919 if (!BaseT::getConstantStrideStep(SE, Ptr)) 1920 return 1; 1921 } 1922 1923 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 1924 } 1925 1926 int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, Type *ValTy, 1927 bool IsPairwise) { 1928 1929 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 1930 1931 MVT MTy = LT.second; 1932 1933 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1934 assert(ISD && "Invalid opcode"); 1935 1936 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 1937 // and make it as the cost. 1938 1939 static const CostTblEntry SSE42CostTblPairWise[] = { 1940 { ISD::FADD, MVT::v2f64, 2 }, 1941 { ISD::FADD, MVT::v4f32, 4 }, 1942 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 1943 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5". 1944 { ISD::ADD, MVT::v8i16, 5 }, 1945 }; 1946 1947 static const CostTblEntry AVX1CostTblPairWise[] = { 1948 { ISD::FADD, MVT::v4f32, 4 }, 1949 { ISD::FADD, MVT::v4f64, 5 }, 1950 { ISD::FADD, MVT::v8f32, 7 }, 1951 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 1952 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5". 1953 { ISD::ADD, MVT::v4i64, 5 }, // The data reported by the IACA tool is "4.8". 1954 { ISD::ADD, MVT::v8i16, 5 }, 1955 { ISD::ADD, MVT::v8i32, 5 }, 1956 }; 1957 1958 static const CostTblEntry SSE42CostTblNoPairWise[] = { 1959 { ISD::FADD, MVT::v2f64, 2 }, 1960 { ISD::FADD, MVT::v4f32, 4 }, 1961 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 1962 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 1963 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 1964 }; 1965 1966 static const CostTblEntry AVX1CostTblNoPairWise[] = { 1967 { ISD::FADD, MVT::v4f32, 3 }, 1968 { ISD::FADD, MVT::v4f64, 3 }, 1969 { ISD::FADD, MVT::v8f32, 4 }, 1970 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 1971 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "2.8". 1972 { ISD::ADD, MVT::v4i64, 3 }, 1973 { ISD::ADD, MVT::v8i16, 4 }, 1974 { ISD::ADD, MVT::v8i32, 5 }, 1975 }; 1976 1977 if (IsPairwise) { 1978 if (ST->hasAVX()) 1979 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy)) 1980 return LT.first * Entry->Cost; 1981 1982 if (ST->hasSSE42()) 1983 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy)) 1984 return LT.first * Entry->Cost; 1985 } else { 1986 if (ST->hasAVX()) 1987 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 1988 return LT.first * Entry->Cost; 1989 1990 if (ST->hasSSE42()) 1991 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy)) 1992 return LT.first * Entry->Cost; 1993 } 1994 1995 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise); 1996 } 1997 1998 /// \brief Calculate the cost of materializing a 64-bit value. This helper 1999 /// method might only calculate a fraction of a larger immediate. Therefore it 2000 /// is valid to return a cost of ZERO. 2001 int X86TTIImpl::getIntImmCost(int64_t Val) { 2002 if (Val == 0) 2003 return TTI::TCC_Free; 2004 2005 if (isInt<32>(Val)) 2006 return TTI::TCC_Basic; 2007 2008 return 2 * TTI::TCC_Basic; 2009 } 2010 2011 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { 2012 assert(Ty->isIntegerTy()); 2013 2014 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 2015 if (BitSize == 0) 2016 return ~0U; 2017 2018 // Never hoist constants larger than 128bit, because this might lead to 2019 // incorrect code generation or assertions in codegen. 2020 // Fixme: Create a cost model for types larger than i128 once the codegen 2021 // issues have been fixed. 2022 if (BitSize > 128) 2023 return TTI::TCC_Free; 2024 2025 if (Imm == 0) 2026 return TTI::TCC_Free; 2027 2028 // Sign-extend all constants to a multiple of 64-bit. 2029 APInt ImmVal = Imm; 2030 if (BitSize & 0x3f) 2031 ImmVal = Imm.sext((BitSize + 63) & ~0x3fU); 2032 2033 // Split the constant into 64-bit chunks and calculate the cost for each 2034 // chunk. 2035 int Cost = 0; 2036 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 2037 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 2038 int64_t Val = Tmp.getSExtValue(); 2039 Cost += getIntImmCost(Val); 2040 } 2041 // We need at least one instruction to materialize the constant. 2042 return std::max(1, Cost); 2043 } 2044 2045 int X86TTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, 2046 Type *Ty) { 2047 assert(Ty->isIntegerTy()); 2048 2049 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 2050 // There is no cost model for constants with a bit size of 0. Return TCC_Free 2051 // here, so that constant hoisting will ignore this constant. 2052 if (BitSize == 0) 2053 return TTI::TCC_Free; 2054 2055 unsigned ImmIdx = ~0U; 2056 switch (Opcode) { 2057 default: 2058 return TTI::TCC_Free; 2059 case Instruction::GetElementPtr: 2060 // Always hoist the base address of a GetElementPtr. This prevents the 2061 // creation of new constants for every base constant that gets constant 2062 // folded with the offset. 2063 if (Idx == 0) 2064 return 2 * TTI::TCC_Basic; 2065 return TTI::TCC_Free; 2066 case Instruction::Store: 2067 ImmIdx = 0; 2068 break; 2069 case Instruction::ICmp: 2070 // This is an imperfect hack to prevent constant hoisting of 2071 // compares that might be trying to check if a 64-bit value fits in 2072 // 32-bits. The backend can optimize these cases using a right shift by 32. 2073 // Ideally we would check the compare predicate here. There also other 2074 // similar immediates the backend can use shifts for. 2075 if (Idx == 1 && Imm.getBitWidth() == 64) { 2076 uint64_t ImmVal = Imm.getZExtValue(); 2077 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 2078 return TTI::TCC_Free; 2079 } 2080 ImmIdx = 1; 2081 break; 2082 case Instruction::And: 2083 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 2084 // by using a 32-bit operation with implicit zero extension. Detect such 2085 // immediates here as the normal path expects bit 31 to be sign extended. 2086 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 2087 return TTI::TCC_Free; 2088 LLVM_FALLTHROUGH; 2089 case Instruction::Add: 2090 case Instruction::Sub: 2091 case Instruction::Mul: 2092 case Instruction::UDiv: 2093 case Instruction::SDiv: 2094 case Instruction::URem: 2095 case Instruction::SRem: 2096 case Instruction::Or: 2097 case Instruction::Xor: 2098 ImmIdx = 1; 2099 break; 2100 // Always return TCC_Free for the shift value of a shift instruction. 2101 case Instruction::Shl: 2102 case Instruction::LShr: 2103 case Instruction::AShr: 2104 if (Idx == 1) 2105 return TTI::TCC_Free; 2106 break; 2107 case Instruction::Trunc: 2108 case Instruction::ZExt: 2109 case Instruction::SExt: 2110 case Instruction::IntToPtr: 2111 case Instruction::PtrToInt: 2112 case Instruction::BitCast: 2113 case Instruction::PHI: 2114 case Instruction::Call: 2115 case Instruction::Select: 2116 case Instruction::Ret: 2117 case Instruction::Load: 2118 break; 2119 } 2120 2121 if (Idx == ImmIdx) { 2122 int NumConstants = (BitSize + 63) / 64; 2123 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty); 2124 return (Cost <= NumConstants * TTI::TCC_Basic) 2125 ? static_cast<int>(TTI::TCC_Free) 2126 : Cost; 2127 } 2128 2129 return X86TTIImpl::getIntImmCost(Imm, Ty); 2130 } 2131 2132 int X86TTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, 2133 Type *Ty) { 2134 assert(Ty->isIntegerTy()); 2135 2136 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 2137 // There is no cost model for constants with a bit size of 0. Return TCC_Free 2138 // here, so that constant hoisting will ignore this constant. 2139 if (BitSize == 0) 2140 return TTI::TCC_Free; 2141 2142 switch (IID) { 2143 default: 2144 return TTI::TCC_Free; 2145 case Intrinsic::sadd_with_overflow: 2146 case Intrinsic::uadd_with_overflow: 2147 case Intrinsic::ssub_with_overflow: 2148 case Intrinsic::usub_with_overflow: 2149 case Intrinsic::smul_with_overflow: 2150 case Intrinsic::umul_with_overflow: 2151 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 2152 return TTI::TCC_Free; 2153 break; 2154 case Intrinsic::experimental_stackmap: 2155 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 2156 return TTI::TCC_Free; 2157 break; 2158 case Intrinsic::experimental_patchpoint_void: 2159 case Intrinsic::experimental_patchpoint_i64: 2160 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 2161 return TTI::TCC_Free; 2162 break; 2163 } 2164 return X86TTIImpl::getIntImmCost(Imm, Ty); 2165 } 2166 2167 unsigned X86TTIImpl::getUserCost(const User *U, 2168 ArrayRef<const Value *> Operands) { 2169 if (isa<StoreInst>(U)) { 2170 Value *Ptr = U->getOperand(1); 2171 // Store instruction with index and scale costs 2 Uops. 2172 // Check the preceding GEP to identify non-const indices. 2173 if (auto GEP = dyn_cast<GetElementPtrInst>(Ptr)) { 2174 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 2175 return TTI::TCC_Basic * 2; 2176 } 2177 return TTI::TCC_Basic; 2178 } 2179 return BaseT::getUserCost(U, Operands); 2180 } 2181 2182 // Return an average cost of Gather / Scatter instruction, maybe improved later 2183 int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, Value *Ptr, 2184 unsigned Alignment, unsigned AddressSpace) { 2185 2186 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 2187 unsigned VF = SrcVTy->getVectorNumElements(); 2188 2189 // Try to reduce index size from 64 bit (default for GEP) 2190 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 2191 // operation will use 16 x 64 indices which do not fit in a zmm and needs 2192 // to split. Also check that the base pointer is the same for all lanes, 2193 // and that there's at most one variable index. 2194 auto getIndexSizeInBits = [](Value *Ptr, const DataLayout& DL) { 2195 unsigned IndexSize = DL.getPointerSizeInBits(); 2196 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 2197 if (IndexSize < 64 || !GEP) 2198 return IndexSize; 2199 2200 unsigned NumOfVarIndices = 0; 2201 Value *Ptrs = GEP->getPointerOperand(); 2202 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 2203 return IndexSize; 2204 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 2205 if (isa<Constant>(GEP->getOperand(i))) 2206 continue; 2207 Type *IndxTy = GEP->getOperand(i)->getType(); 2208 if (IndxTy->isVectorTy()) 2209 IndxTy = IndxTy->getVectorElementType(); 2210 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 2211 !isa<SExtInst>(GEP->getOperand(i))) || 2212 ++NumOfVarIndices > 1) 2213 return IndexSize; // 64 2214 } 2215 return (unsigned)32; 2216 }; 2217 2218 2219 // Trying to reduce IndexSize to 32 bits for vector 16. 2220 // By default the IndexSize is equal to pointer size. 2221 unsigned IndexSize = (VF >= 16) ? getIndexSizeInBits(Ptr, DL) : 2222 DL.getPointerSizeInBits(); 2223 2224 Type *IndexVTy = VectorType::get(IntegerType::get(SrcVTy->getContext(), 2225 IndexSize), VF); 2226 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy); 2227 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy); 2228 int SplitFactor = std::max(IdxsLT.first, SrcLT.first); 2229 if (SplitFactor > 1) { 2230 // Handle splitting of vector of pointers 2231 Type *SplitSrcTy = VectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 2232 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 2233 AddressSpace); 2234 } 2235 2236 // The gather / scatter cost is given by Intel architects. It is a rough 2237 // number since we are looking at one instruction in a time. 2238 const int GSOverhead = 2; 2239 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2240 Alignment, AddressSpace); 2241 } 2242 2243 /// Return the cost of full scalarization of gather / scatter operation. 2244 /// 2245 /// Opcode - Load or Store instruction. 2246 /// SrcVTy - The type of the data vector that should be gathered or scattered. 2247 /// VariableMask - The mask is non-constant at compile time. 2248 /// Alignment - Alignment for one element. 2249 /// AddressSpace - pointer[s] address space. 2250 /// 2251 int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 2252 bool VariableMask, unsigned Alignment, 2253 unsigned AddressSpace) { 2254 unsigned VF = SrcVTy->getVectorNumElements(); 2255 2256 int MaskUnpackCost = 0; 2257 if (VariableMask) { 2258 VectorType *MaskTy = 2259 VectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 2260 MaskUnpackCost = getScalarizationOverhead(MaskTy, false, true); 2261 int ScalarCompareCost = 2262 getCmpSelInstrCost(Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), 2263 nullptr); 2264 int BranchCost = getCFInstrCost(Instruction::Br); 2265 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 2266 } 2267 2268 // The cost of the scalar loads/stores. 2269 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2270 Alignment, AddressSpace); 2271 2272 int InsertExtractCost = 0; 2273 if (Opcode == Instruction::Load) 2274 for (unsigned i = 0; i < VF; ++i) 2275 // Add the cost of inserting each scalar load into the vector 2276 InsertExtractCost += 2277 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 2278 else 2279 for (unsigned i = 0; i < VF; ++i) 2280 // Add the cost of extracting each element out of the data vector 2281 InsertExtractCost += 2282 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 2283 2284 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 2285 } 2286 2287 /// Calculate the cost of Gather / Scatter operation 2288 int X86TTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *SrcVTy, 2289 Value *Ptr, bool VariableMask, 2290 unsigned Alignment) { 2291 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 2292 unsigned VF = SrcVTy->getVectorNumElements(); 2293 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 2294 if (!PtrTy && Ptr->getType()->isVectorTy()) 2295 PtrTy = dyn_cast<PointerType>(Ptr->getType()->getVectorElementType()); 2296 assert(PtrTy && "Unexpected type for Ptr argument"); 2297 unsigned AddressSpace = PtrTy->getAddressSpace(); 2298 2299 bool Scalarize = false; 2300 if ((Opcode == Instruction::Load && !isLegalMaskedGather(SrcVTy)) || 2301 (Opcode == Instruction::Store && !isLegalMaskedScatter(SrcVTy))) 2302 Scalarize = true; 2303 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 2304 // Vector-4 of gather/scatter instruction does not exist on KNL. 2305 // We can extend it to 8 elements, but zeroing upper bits of 2306 // the mask vector will add more instructions. Right now we give the scalar 2307 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 2308 // is better in the VariableMask case. 2309 if (VF == 2 || (VF == 4 && !ST->hasVLX())) 2310 Scalarize = true; 2311 2312 if (Scalarize) 2313 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 2314 AddressSpace); 2315 2316 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 2317 } 2318 2319 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 2320 TargetTransformInfo::LSRCost &C2) { 2321 // X86 specific here are "instruction number 1st priority". 2322 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 2323 C1.NumIVMuls, C1.NumBaseAdds, 2324 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 2325 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 2326 C2.NumIVMuls, C2.NumBaseAdds, 2327 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 2328 } 2329 2330 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy) { 2331 Type *ScalarTy = DataTy->getScalarType(); 2332 int DataWidth = isa<PointerType>(ScalarTy) ? 2333 DL.getPointerSizeInBits() : ScalarTy->getPrimitiveSizeInBits(); 2334 2335 return ((DataWidth == 32 || DataWidth == 64) && ST->hasAVX()) || 2336 ((DataWidth == 8 || DataWidth == 16) && ST->hasBWI()); 2337 } 2338 2339 bool X86TTIImpl::isLegalMaskedStore(Type *DataType) { 2340 return isLegalMaskedLoad(DataType); 2341 } 2342 2343 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy) { 2344 // This function is called now in two cases: from the Loop Vectorizer 2345 // and from the Scalarizer. 2346 // When the Loop Vectorizer asks about legality of the feature, 2347 // the vectorization factor is not calculated yet. The Loop Vectorizer 2348 // sends a scalar type and the decision is based on the width of the 2349 // scalar element. 2350 // Later on, the cost model will estimate usage this intrinsic based on 2351 // the vector type. 2352 // The Scalarizer asks again about legality. It sends a vector type. 2353 // In this case we can reject non-power-of-2 vectors. 2354 if (isa<VectorType>(DataTy) && !isPowerOf2_32(DataTy->getVectorNumElements())) 2355 return false; 2356 Type *ScalarTy = DataTy->getScalarType(); 2357 int DataWidth = isa<PointerType>(ScalarTy) ? 2358 DL.getPointerSizeInBits() : ScalarTy->getPrimitiveSizeInBits(); 2359 2360 // AVX-512 allows gather and scatter 2361 return (DataWidth == 32 || DataWidth == 64) && ST->hasAVX512(); 2362 } 2363 2364 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType) { 2365 return isLegalMaskedGather(DataType); 2366 } 2367 2368 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 2369 const Function *Callee) const { 2370 const TargetMachine &TM = getTLI()->getTargetMachine(); 2371 2372 // Work this as a subsetting of subtarget features. 2373 const FeatureBitset &CallerBits = 2374 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 2375 const FeatureBitset &CalleeBits = 2376 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 2377 2378 // FIXME: This is likely too limiting as it will include subtarget features 2379 // that we might not care about for inlining, but it is conservatively 2380 // correct. 2381 return (CallerBits & CalleeBits) == CalleeBits; 2382 } 2383 2384 bool X86TTIImpl::expandMemCmp(Instruction *I, unsigned &MaxLoadSize) { 2385 // TODO: We can increase these based on available vector ops. 2386 MaxLoadSize = ST->is64Bit() ? 8 : 4; 2387 return true; 2388 } 2389 2390 bool X86TTIImpl::enableInterleavedAccessVectorization() { 2391 // TODO: We expect this to be beneficial regardless of arch, 2392 // but there are currently some unexplained performance artifacts on Atom. 2393 // As a temporary solution, disable on Atom. 2394 return !(ST->isAtom()); 2395 } 2396 2397 // Get estimation for interleaved load/store operations for AVX2. 2398 // \p Factor is the interleaved-access factor (stride) - number of 2399 // (interleaved) elements in the group. 2400 // \p Indices contains the indices for a strided load: when the 2401 // interleaved load has gaps they indicate which elements are used. 2402 // If Indices is empty (or if the number of indices is equal to the size 2403 // of the interleaved-access as given in \p Factor) the access has no gaps. 2404 // 2405 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 2406 // computing the cost using a generic formula as a function of generic 2407 // shuffles. We therefore use a lookup table instead, filled according to 2408 // the instruction sequences that codegen currently generates. 2409 int X86TTIImpl::getInterleavedMemoryOpCostAVX2(unsigned Opcode, Type *VecTy, 2410 unsigned Factor, 2411 ArrayRef<unsigned> Indices, 2412 unsigned Alignment, 2413 unsigned AddressSpace) { 2414 2415 // We currently Support only fully-interleaved groups, with no gaps. 2416 // TODO: Support also strided loads (interleaved-groups with gaps). 2417 if (Indices.size() && Indices.size() != Factor) 2418 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 2419 Alignment, AddressSpace); 2420 2421 // VecTy for interleave memop is <VF*Factor x Elt>. 2422 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 2423 // VecTy = <12 x i32>. 2424 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 2425 2426 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 2427 // the VF=2, while v2i128 is an unsupported MVT vector type 2428 // (see MachineValueType.h::getVectorVT()). 2429 if (!LegalVT.isVector()) 2430 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 2431 Alignment, AddressSpace); 2432 2433 unsigned VF = VecTy->getVectorNumElements() / Factor; 2434 Type *ScalarTy = VecTy->getVectorElementType(); 2435 2436 // Calculate the number of memory operations (NumOfMemOps), required 2437 // for load/store the VecTy. 2438 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 2439 unsigned LegalVTSize = LegalVT.getStoreSize(); 2440 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 2441 2442 // Get the cost of one memory operation. 2443 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(), 2444 LegalVT.getVectorNumElements()); 2445 unsigned MemOpCost = 2446 getMemoryOpCost(Opcode, SingleMemOpTy, Alignment, AddressSpace); 2447 2448 VectorType *VT = VectorType::get(ScalarTy, VF); 2449 EVT ETy = TLI->getValueType(DL, VT); 2450 if (!ETy.isSimple()) 2451 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 2452 Alignment, AddressSpace); 2453 2454 // TODO: Complete for other data-types and strides. 2455 // Each combination of Stride, ElementTy and VF results in a different 2456 // sequence; The cost tables are therefore accessed with: 2457 // Factor (stride) and VectorType=VFxElemType. 2458 // The Cost accounts only for the shuffle sequence; 2459 // The cost of the loads/stores is accounted for separately. 2460 // 2461 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 2462 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8 2463 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8 2464 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8 2465 { 3, MVT::v16i8, 18}, //(load 48i8 and) deinterleave into 3 x 16i8 2466 { 3, MVT::v32i8, 42 }, //(load 96i8 and) deinterleave into 3 x 32i8 2467 2468 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8 2469 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8 2470 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8 2471 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8 2472 { 4, MVT::v32i8, 80 } //(load 128i8 and) deinterleave into 4 x 32i8 2473 }; 2474 2475 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 2476 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store) 2477 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store) 2478 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store) 2479 { 3, MVT::v16i8, 17 }, //interleave 3 x 16i8 into 48i8 (and store) 2480 { 3, MVT::v32i8, 32 }, //interleave 3 x 32i8 into 96i8 (and store) 2481 2482 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store) 2483 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store) 2484 { 4, MVT::v8i8, 16 }, //interleave 4 x 8i8 into 32i8 (and store) 2485 { 4, MVT::v16i8, 20 }, //interleave 4 x 16i8 into 64i8 (and store) 2486 { 4, MVT::v32i8, 40 } //interleave 4 x 32i8 into 128i8 (and store) 2487 }; 2488 2489 if (Opcode == Instruction::Load) { 2490 if (const auto *Entry = 2491 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 2492 return NumOfMemOps * MemOpCost + Entry->Cost; 2493 } else { 2494 assert(Opcode == Instruction::Store && 2495 "Expected Store Instruction at this point"); 2496 if (const auto *Entry = 2497 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 2498 return NumOfMemOps * MemOpCost + Entry->Cost; 2499 } 2500 2501 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 2502 Alignment, AddressSpace); 2503 } 2504 2505 // Get estimation for interleaved load/store operations and strided load. 2506 // \p Indices contains indices for strided load. 2507 // \p Factor - the factor of interleaving. 2508 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 2509 int X86TTIImpl::getInterleavedMemoryOpCostAVX512(unsigned Opcode, Type *VecTy, 2510 unsigned Factor, 2511 ArrayRef<unsigned> Indices, 2512 unsigned Alignment, 2513 unsigned AddressSpace) { 2514 2515 // VecTy for interleave memop is <VF*Factor x Elt>. 2516 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 2517 // VecTy = <12 x i32>. 2518 2519 // Calculate the number of memory operations (NumOfMemOps), required 2520 // for load/store the VecTy. 2521 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 2522 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 2523 unsigned LegalVTSize = LegalVT.getStoreSize(); 2524 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 2525 2526 // Get the cost of one memory operation. 2527 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(), 2528 LegalVT.getVectorNumElements()); 2529 unsigned MemOpCost = 2530 getMemoryOpCost(Opcode, SingleMemOpTy, Alignment, AddressSpace); 2531 2532 if (Opcode == Instruction::Load) { 2533 // Kind of shuffle depends on number of loaded values. 2534 // If we load the entire data in one register, we can use a 1-src shuffle. 2535 // Otherwise, we'll merge 2 sources in each operation. 2536 TTI::ShuffleKind ShuffleKind = 2537 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 2538 2539 unsigned ShuffleCost = 2540 getShuffleCost(ShuffleKind, SingleMemOpTy, 0, nullptr); 2541 2542 unsigned NumOfLoadsInInterleaveGrp = 2543 Indices.size() ? Indices.size() : Factor; 2544 Type *ResultTy = VectorType::get(VecTy->getVectorElementType(), 2545 VecTy->getVectorNumElements() / Factor); 2546 unsigned NumOfResults = 2547 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 2548 NumOfLoadsInInterleaveGrp; 2549 2550 // About a half of the loads may be folded in shuffles when we have only 2551 // one result. If we have more than one result, we do not fold loads at all. 2552 unsigned NumOfUnfoldedLoads = 2553 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 2554 2555 // Get a number of shuffle operations per result. 2556 unsigned NumOfShufflesPerResult = 2557 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 2558 2559 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 2560 // When we have more than one destination, we need additional instructions 2561 // to keep sources. 2562 unsigned NumOfMoves = 0; 2563 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 2564 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 2565 2566 int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 2567 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 2568 2569 return Cost; 2570 } 2571 2572 // Store. 2573 assert(Opcode == Instruction::Store && 2574 "Expected Store Instruction at this point"); 2575 2576 // There is no strided stores meanwhile. And store can't be folded in 2577 // shuffle. 2578 unsigned NumOfSources = Factor; // The number of values to be merged. 2579 unsigned ShuffleCost = 2580 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, 0, nullptr); 2581 unsigned NumOfShufflesPerStore = NumOfSources - 1; 2582 2583 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 2584 // We need additional instructions to keep sources. 2585 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 2586 int Cost = NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 2587 NumOfMoves; 2588 return Cost; 2589 } 2590 2591 int X86TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, 2592 unsigned Factor, 2593 ArrayRef<unsigned> Indices, 2594 unsigned Alignment, 2595 unsigned AddressSpace) { 2596 auto isSupportedOnAVX512 = [](Type *VecTy, bool &RequiresBW) { 2597 RequiresBW = false; 2598 Type *EltTy = VecTy->getVectorElementType(); 2599 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 2600 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 2601 return true; 2602 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) { 2603 RequiresBW = true; 2604 return true; 2605 } 2606 return false; 2607 }; 2608 bool RequiresBW; 2609 bool HasAVX512Solution = isSupportedOnAVX512(VecTy, RequiresBW); 2610 if (ST->hasAVX512() && HasAVX512Solution && (!RequiresBW || ST->hasBWI())) 2611 return getInterleavedMemoryOpCostAVX512(Opcode, VecTy, Factor, Indices, 2612 Alignment, AddressSpace); 2613 if (ST->hasAVX2()) 2614 return getInterleavedMemoryOpCostAVX2(Opcode, VecTy, Factor, Indices, 2615 Alignment, AddressSpace); 2616 2617 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 2618 Alignment, AddressSpace); 2619 } 2620