1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 //===----------------------------------------------------------------------===// 54 // 55 // X86 cost model. 56 // 57 //===----------------------------------------------------------------------===// 58 59 TargetTransformInfo::PopcntSupportKind 60 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 61 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 62 // TODO: Currently the __builtin_popcount() implementation using SSE3 63 // instructions is inefficient. Once the problem is fixed, we should 64 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 65 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 66 } 67 68 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 69 TargetTransformInfo::CacheLevel Level) const { 70 switch (Level) { 71 case TargetTransformInfo::CacheLevel::L1D: 72 // - Penryn 73 // - Nehalem 74 // - Westmere 75 // - Sandy Bridge 76 // - Ivy Bridge 77 // - Haswell 78 // - Broadwell 79 // - Skylake 80 // - Kabylake 81 return 32 * 1024; // 32 KByte 82 case TargetTransformInfo::CacheLevel::L2D: 83 // - Penryn 84 // - Nehalem 85 // - Westmere 86 // - Sandy Bridge 87 // - Ivy Bridge 88 // - Haswell 89 // - Broadwell 90 // - Skylake 91 // - Kabylake 92 return 256 * 1024; // 256 KByte 93 } 94 95 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 96 } 97 98 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 99 TargetTransformInfo::CacheLevel Level) const { 100 // - Penryn 101 // - Nehalem 102 // - Westmere 103 // - Sandy Bridge 104 // - Ivy Bridge 105 // - Haswell 106 // - Broadwell 107 // - Skylake 108 // - Kabylake 109 switch (Level) { 110 case TargetTransformInfo::CacheLevel::L1D: 111 LLVM_FALLTHROUGH; 112 case TargetTransformInfo::CacheLevel::L2D: 113 return 8; 114 } 115 116 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 117 } 118 119 unsigned X86TTIImpl::getNumberOfRegisters(bool Vector) { 120 if (Vector && !ST->hasSSE1()) 121 return 0; 122 123 if (ST->is64Bit()) { 124 if (Vector && ST->hasAVX512()) 125 return 32; 126 return 16; 127 } 128 return 8; 129 } 130 131 unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const { 132 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 133 if (Vector) { 134 if (ST->hasAVX512() && PreferVectorWidth >= 512) 135 return 512; 136 if (ST->hasAVX() && PreferVectorWidth >= 256) 137 return 256; 138 if (ST->hasSSE1() && PreferVectorWidth >= 128) 139 return 128; 140 return 0; 141 } 142 143 if (ST->is64Bit()) 144 return 64; 145 146 return 32; 147 } 148 149 // Use horizontal 128-bit operations, which use low and high 150 // 64-bit parts of vector register. This also allows vectorizer 151 // to use partial vector operations. 152 unsigned X86TTIImpl::getMinVectorRegisterBitWidth() const { 153 return 64; 154 } 155 156 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 157 return getRegisterBitWidth(true); 158 } 159 160 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 161 // If the loop will not be vectorized, don't interleave the loop. 162 // Let regular unroll to unroll the loop, which saves the overflow 163 // check and memory check cost. 164 if (VF == 1) 165 return 1; 166 167 if (ST->isAtom()) 168 return 1; 169 170 // Sandybridge and Haswell have multiple execution ports and pipelined 171 // vector units. 172 if (ST->hasAVX()) 173 return 4; 174 175 return 2; 176 } 177 178 int X86TTIImpl::getArithmeticInstrCost( 179 unsigned Opcode, Type *Ty, 180 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 181 TTI::OperandValueProperties Opd1PropInfo, 182 TTI::OperandValueProperties Opd2PropInfo, 183 ArrayRef<const Value *> Args) { 184 // Legalize the type. 185 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 186 187 int ISD = TLI->InstructionOpcodeToISD(Opcode); 188 assert(ISD && "Invalid opcode"); 189 190 static const CostTblEntry GLMCostTable[] = { 191 { ISD::FDIV, MVT::f32, 18 }, // divss 192 { ISD::FDIV, MVT::v4f32, 35 }, // divps 193 { ISD::FDIV, MVT::f64, 33 }, // divsd 194 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 195 }; 196 197 if (ST->isGLM()) 198 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 199 LT.second)) 200 return LT.first * Entry->Cost; 201 202 static const CostTblEntry SLMCostTable[] = { 203 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 204 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 205 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. 206 { ISD::FMUL, MVT::f64, 2 }, // mulsd 207 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 208 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 209 { ISD::FDIV, MVT::f32, 17 }, // divss 210 { ISD::FDIV, MVT::v4f32, 39 }, // divps 211 { ISD::FDIV, MVT::f64, 32 }, // divsd 212 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 213 { ISD::FADD, MVT::v2f64, 2 }, // addpd 214 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 215 // v2i64/v4i64 mul is custom lowered as a series of long: 216 // multiplies(3), shifts(3) and adds(2) 217 // slm muldq version throughput is 2 and addq throughput 4 218 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 219 // 3X4 (addq throughput) = 17 220 { ISD::MUL, MVT::v2i64, 17 }, 221 // slm addq\subq throughput is 4 222 { ISD::ADD, MVT::v2i64, 4 }, 223 { ISD::SUB, MVT::v2i64, 4 }, 224 }; 225 226 if (ST->isSLM()) { 227 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 228 // Check if the operands can be shrinked into a smaller datatype. 229 bool Op1Signed = false; 230 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 231 bool Op2Signed = false; 232 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 233 234 bool signedMode = Op1Signed | Op2Signed; 235 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 236 237 if (OpMinSize <= 7) 238 return LT.first * 3; // pmullw/sext 239 if (!signedMode && OpMinSize <= 8) 240 return LT.first * 3; // pmullw/zext 241 if (OpMinSize <= 15) 242 return LT.first * 5; // pmullw/pmulhw/pshuf 243 if (!signedMode && OpMinSize <= 16) 244 return LT.first * 5; // pmullw/pmulhw/pshuf 245 } 246 247 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 248 LT.second)) { 249 return LT.first * Entry->Cost; 250 } 251 } 252 253 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 254 ISD == ISD::UREM) && 255 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 256 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 257 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 258 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 259 // On X86, vector signed division by constants power-of-two are 260 // normally expanded to the sequence SRA + SRL + ADD + SRA. 261 // The OperandValue properties may not be the same as that of the previous 262 // operation; conservatively assume OP_None. 263 int Cost = 264 2 * getArithmeticInstrCost(Instruction::AShr, Ty, Op1Info, Op2Info, 265 TargetTransformInfo::OP_None, 266 TargetTransformInfo::OP_None); 267 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 268 TargetTransformInfo::OP_None, 269 TargetTransformInfo::OP_None); 270 Cost += getArithmeticInstrCost(Instruction::Add, Ty, Op1Info, Op2Info, 271 TargetTransformInfo::OP_None, 272 TargetTransformInfo::OP_None); 273 274 if (ISD == ISD::SREM) { 275 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 276 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info); 277 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, Op1Info, Op2Info); 278 } 279 280 return Cost; 281 } 282 283 // Vector unsigned division/remainder will be simplified to shifts/masks. 284 if (ISD == ISD::UDIV) 285 return getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 286 TargetTransformInfo::OP_None, 287 TargetTransformInfo::OP_None); 288 289 if (ISD == ISD::UREM) 290 return getArithmeticInstrCost(Instruction::And, Ty, Op1Info, Op2Info, 291 TargetTransformInfo::OP_None, 292 TargetTransformInfo::OP_None); 293 } 294 295 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 296 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 297 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 298 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 299 }; 300 301 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 302 ST->hasBWI()) { 303 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 304 LT.second)) 305 return LT.first * Entry->Cost; 306 } 307 308 static const CostTblEntry AVX512UniformConstCostTable[] = { 309 { ISD::SRA, MVT::v2i64, 1 }, 310 { ISD::SRA, MVT::v4i64, 1 }, 311 { ISD::SRA, MVT::v8i64, 1 }, 312 }; 313 314 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 315 ST->hasAVX512()) { 316 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 317 LT.second)) 318 return LT.first * Entry->Cost; 319 } 320 321 static const CostTblEntry AVX2UniformConstCostTable[] = { 322 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 323 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 324 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 325 326 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 327 }; 328 329 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 330 ST->hasAVX2()) { 331 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 332 LT.second)) 333 return LT.first * Entry->Cost; 334 } 335 336 static const CostTblEntry SSE2UniformConstCostTable[] = { 337 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 338 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 339 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 340 341 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 342 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 343 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 344 }; 345 346 // XOP has faster vXi8 shifts. 347 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 348 ST->hasSSE2() && !ST->hasXOP()) { 349 if (const auto *Entry = 350 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 351 return LT.first * Entry->Cost; 352 } 353 354 static const CostTblEntry AVX512BWConstCostTable[] = { 355 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 356 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 357 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 358 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 359 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 360 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 361 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 362 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 363 }; 364 365 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 366 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 367 ST->hasBWI()) { 368 if (const auto *Entry = 369 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 370 return LT.first * Entry->Cost; 371 } 372 373 static const CostTblEntry AVX512ConstCostTable[] = { 374 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 375 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 376 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 377 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 378 }; 379 380 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 381 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 382 ST->hasAVX512()) { 383 if (const auto *Entry = 384 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 385 return LT.first * Entry->Cost; 386 } 387 388 static const CostTblEntry AVX2ConstCostTable[] = { 389 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 390 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 391 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 392 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 393 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 394 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 395 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 396 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 397 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 398 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 399 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 400 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 401 }; 402 403 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 404 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 405 ST->hasAVX2()) { 406 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 407 return LT.first * Entry->Cost; 408 } 409 410 static const CostTblEntry SSE2ConstCostTable[] = { 411 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 412 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 413 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 414 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 415 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 416 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 417 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 418 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 419 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 420 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 421 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 422 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 423 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 424 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 425 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 426 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 427 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 428 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 429 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 430 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 431 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 432 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 433 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 434 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 435 }; 436 437 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 438 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 439 ST->hasSSE2()) { 440 // pmuldq sequence. 441 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 442 return LT.first * 32; 443 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 444 return LT.first * 38; 445 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 446 return LT.first * 15; 447 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 448 return LT.first * 20; 449 450 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 451 return LT.first * Entry->Cost; 452 } 453 454 static const CostTblEntry AVX2UniformCostTable[] = { 455 // Uniform splats are cheaper for the following instructions. 456 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 457 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 458 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 459 }; 460 461 if (ST->hasAVX2() && 462 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 463 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 464 if (const auto *Entry = 465 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 466 return LT.first * Entry->Cost; 467 } 468 469 static const CostTblEntry SSE2UniformCostTable[] = { 470 // Uniform splats are cheaper for the following instructions. 471 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 472 { ISD::SHL, MVT::v4i32, 1 }, // pslld 473 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 474 475 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 476 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 477 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 478 479 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 480 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 481 }; 482 483 if (ST->hasSSE2() && 484 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 485 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 486 if (const auto *Entry = 487 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 488 return LT.first * Entry->Cost; 489 } 490 491 static const CostTblEntry AVX512DQCostTable[] = { 492 { ISD::MUL, MVT::v2i64, 1 }, 493 { ISD::MUL, MVT::v4i64, 1 }, 494 { ISD::MUL, MVT::v8i64, 1 } 495 }; 496 497 // Look for AVX512DQ lowering tricks for custom cases. 498 if (ST->hasDQI()) 499 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 500 return LT.first * Entry->Cost; 501 502 static const CostTblEntry AVX512BWCostTable[] = { 503 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 504 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 505 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 506 507 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 508 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 509 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 510 511 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 512 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 513 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 514 515 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 516 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 517 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 518 519 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence. 520 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence. 521 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence. 522 }; 523 524 // Look for AVX512BW lowering tricks for custom cases. 525 if (ST->hasBWI()) 526 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 527 return LT.first * Entry->Cost; 528 529 static const CostTblEntry AVX512CostTable[] = { 530 { ISD::SHL, MVT::v16i32, 1 }, 531 { ISD::SRL, MVT::v16i32, 1 }, 532 { ISD::SRA, MVT::v16i32, 1 }, 533 534 { ISD::SHL, MVT::v8i64, 1 }, 535 { ISD::SRL, MVT::v8i64, 1 }, 536 537 { ISD::SRA, MVT::v2i64, 1 }, 538 { ISD::SRA, MVT::v4i64, 1 }, 539 { ISD::SRA, MVT::v8i64, 1 }, 540 541 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence. 542 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence. 543 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 544 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 545 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 546 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add 547 548 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 549 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 550 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 551 552 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 553 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 554 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 555 }; 556 557 if (ST->hasAVX512()) 558 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 559 return LT.first * Entry->Cost; 560 561 static const CostTblEntry AVX2ShiftCostTable[] = { 562 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 563 // customize them to detect the cases where shift amount is a scalar one. 564 { ISD::SHL, MVT::v4i32, 1 }, 565 { ISD::SRL, MVT::v4i32, 1 }, 566 { ISD::SRA, MVT::v4i32, 1 }, 567 { ISD::SHL, MVT::v8i32, 1 }, 568 { ISD::SRL, MVT::v8i32, 1 }, 569 { ISD::SRA, MVT::v8i32, 1 }, 570 { ISD::SHL, MVT::v2i64, 1 }, 571 { ISD::SRL, MVT::v2i64, 1 }, 572 { ISD::SHL, MVT::v4i64, 1 }, 573 { ISD::SRL, MVT::v4i64, 1 }, 574 }; 575 576 // Look for AVX2 lowering tricks. 577 if (ST->hasAVX2()) { 578 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 579 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 580 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 581 // On AVX2, a packed v16i16 shift left by a constant build_vector 582 // is lowered into a vector multiply (vpmullw). 583 return getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info, 584 TargetTransformInfo::OP_None, 585 TargetTransformInfo::OP_None); 586 587 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 588 return LT.first * Entry->Cost; 589 } 590 591 static const CostTblEntry XOPShiftCostTable[] = { 592 // 128bit shifts take 1cy, but right shifts require negation beforehand. 593 { ISD::SHL, MVT::v16i8, 1 }, 594 { ISD::SRL, MVT::v16i8, 2 }, 595 { ISD::SRA, MVT::v16i8, 2 }, 596 { ISD::SHL, MVT::v8i16, 1 }, 597 { ISD::SRL, MVT::v8i16, 2 }, 598 { ISD::SRA, MVT::v8i16, 2 }, 599 { ISD::SHL, MVT::v4i32, 1 }, 600 { ISD::SRL, MVT::v4i32, 2 }, 601 { ISD::SRA, MVT::v4i32, 2 }, 602 { ISD::SHL, MVT::v2i64, 1 }, 603 { ISD::SRL, MVT::v2i64, 2 }, 604 { ISD::SRA, MVT::v2i64, 2 }, 605 // 256bit shifts require splitting if AVX2 didn't catch them above. 606 { ISD::SHL, MVT::v32i8, 2+2 }, 607 { ISD::SRL, MVT::v32i8, 4+2 }, 608 { ISD::SRA, MVT::v32i8, 4+2 }, 609 { ISD::SHL, MVT::v16i16, 2+2 }, 610 { ISD::SRL, MVT::v16i16, 4+2 }, 611 { ISD::SRA, MVT::v16i16, 4+2 }, 612 { ISD::SHL, MVT::v8i32, 2+2 }, 613 { ISD::SRL, MVT::v8i32, 4+2 }, 614 { ISD::SRA, MVT::v8i32, 4+2 }, 615 { ISD::SHL, MVT::v4i64, 2+2 }, 616 { ISD::SRL, MVT::v4i64, 4+2 }, 617 { ISD::SRA, MVT::v4i64, 4+2 }, 618 }; 619 620 // Look for XOP lowering tricks. 621 if (ST->hasXOP()) { 622 // If the right shift is constant then we'll fold the negation so 623 // it's as cheap as a left shift. 624 int ShiftISD = ISD; 625 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 626 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 627 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 628 ShiftISD = ISD::SHL; 629 if (const auto *Entry = 630 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 631 return LT.first * Entry->Cost; 632 } 633 634 static const CostTblEntry SSE2UniformShiftCostTable[] = { 635 // Uniform splats are cheaper for the following instructions. 636 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 637 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 638 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 639 640 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 641 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 642 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 643 644 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 645 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 646 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 647 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 648 }; 649 650 if (ST->hasSSE2() && 651 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 652 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 653 654 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 655 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 656 return LT.first * 4; // 2*psrad + shuffle. 657 658 if (const auto *Entry = 659 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 660 return LT.first * Entry->Cost; 661 } 662 663 if (ISD == ISD::SHL && 664 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 665 MVT VT = LT.second; 666 // Vector shift left by non uniform constant can be lowered 667 // into vector multiply. 668 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 669 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 670 ISD = ISD::MUL; 671 } 672 673 static const CostTblEntry AVX2CostTable[] = { 674 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. 675 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 676 677 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. 678 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 679 680 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. 681 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. 682 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. 683 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 684 685 { ISD::SUB, MVT::v32i8, 1 }, // psubb 686 { ISD::ADD, MVT::v32i8, 1 }, // paddb 687 { ISD::SUB, MVT::v16i16, 1 }, // psubw 688 { ISD::ADD, MVT::v16i16, 1 }, // paddw 689 { ISD::SUB, MVT::v8i32, 1 }, // psubd 690 { ISD::ADD, MVT::v8i32, 1 }, // paddd 691 { ISD::SUB, MVT::v4i64, 1 }, // psubq 692 { ISD::ADD, MVT::v4i64, 1 }, // paddq 693 694 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence. 695 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence. 696 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 697 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 698 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add 699 700 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 701 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 702 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 703 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 704 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 705 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 706 707 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 708 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 709 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 710 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 711 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 712 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 713 }; 714 715 // Look for AVX2 lowering tricks for custom cases. 716 if (ST->hasAVX2()) 717 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 718 return LT.first * Entry->Cost; 719 720 static const CostTblEntry AVX1CostTable[] = { 721 // We don't have to scalarize unsupported ops. We can issue two half-sized 722 // operations and we only need to extract the upper YMM half. 723 // Two ops + 1 extract + 1 insert = 4. 724 { ISD::MUL, MVT::v16i16, 4 }, 725 { ISD::MUL, MVT::v8i32, 4 }, 726 { ISD::SUB, MVT::v32i8, 4 }, 727 { ISD::ADD, MVT::v32i8, 4 }, 728 { ISD::SUB, MVT::v16i16, 4 }, 729 { ISD::ADD, MVT::v16i16, 4 }, 730 { ISD::SUB, MVT::v8i32, 4 }, 731 { ISD::ADD, MVT::v8i32, 4 }, 732 { ISD::SUB, MVT::v4i64, 4 }, 733 { ISD::ADD, MVT::v4i64, 4 }, 734 735 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 736 // are lowered as a series of long multiplies(3), shifts(3) and adds(2) 737 // Because we believe v4i64 to be a legal type, we must also include the 738 // extract+insert in the cost table. Therefore, the cost here is 18 739 // instead of 8. 740 { ISD::MUL, MVT::v4i64, 18 }, 741 742 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence. 743 744 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 745 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 746 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 747 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 748 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 749 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 750 }; 751 752 if (ST->hasAVX()) 753 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 754 return LT.first * Entry->Cost; 755 756 static const CostTblEntry SSE42CostTable[] = { 757 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 758 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 759 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 760 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 761 762 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 763 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 764 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 765 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 766 767 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 768 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 769 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 770 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 771 772 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 773 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 774 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 775 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 776 }; 777 778 if (ST->hasSSE42()) 779 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 780 return LT.first * Entry->Cost; 781 782 static const CostTblEntry SSE41CostTable[] = { 783 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 784 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split. 785 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 786 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 787 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 788 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split 789 790 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 791 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split. 792 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 793 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 794 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 795 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split. 796 797 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 798 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split. 799 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 800 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 801 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 802 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split. 803 804 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 805 }; 806 807 if (ST->hasSSE41()) 808 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 809 return LT.first * Entry->Cost; 810 811 static const CostTblEntry SSE2CostTable[] = { 812 // We don't correctly identify costs of casts because they are marked as 813 // custom. 814 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 815 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 816 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 817 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 818 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 819 820 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 821 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 822 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 823 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 824 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 825 826 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 827 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 828 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 829 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 830 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split. 831 832 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence. 833 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 834 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 835 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 836 837 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 838 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 839 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 840 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 841 842 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 843 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 844 845 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 846 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 847 }; 848 849 if (ST->hasSSE2()) 850 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 851 return LT.first * Entry->Cost; 852 853 static const CostTblEntry SSE1CostTable[] = { 854 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 855 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 856 857 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 858 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 859 860 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 861 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 862 863 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 864 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 865 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 866 867 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 868 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 869 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 870 }; 871 872 if (ST->hasSSE1()) 873 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 874 return LT.first * Entry->Cost; 875 876 // It is not a good idea to vectorize division. We have to scalarize it and 877 // in the process we will often end up having to spilling regular 878 // registers. The overhead of division is going to dominate most kernels 879 // anyways so try hard to prevent vectorization of division - it is 880 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 881 // to hide "20 cycles" for each lane. 882 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 883 ISD == ISD::UDIV || ISD == ISD::UREM)) { 884 int ScalarCost = getArithmeticInstrCost( 885 Opcode, Ty->getScalarType(), Op1Info, Op2Info, 886 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 887 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 888 } 889 890 // Fallback to the default implementation. 891 return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info); 892 } 893 894 int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, 895 Type *SubTp) { 896 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 897 // 64-bit packed integer vectors (v2i32) are promoted to type v2i64. 898 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp); 899 900 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 901 if (Kind == TTI::SK_Transpose) 902 Kind = TTI::SK_PermuteTwoSrc; 903 904 // For Broadcasts we are splatting the first element from the first input 905 // register, so only need to reference that input and all the output 906 // registers are the same. 907 if (Kind == TTI::SK_Broadcast) 908 LT.first = 1; 909 910 // Subvector extractions are free if they start at the beginning of a 911 // vector and cheap if the subvectors are aligned. 912 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 913 int NumElts = LT.second.getVectorNumElements(); 914 if ((Index % NumElts) == 0) 915 return 0; 916 std::pair<int, MVT> SubLT = TLI->getTypeLegalizationCost(DL, SubTp); 917 if (SubLT.second.isVector()) { 918 int NumSubElts = SubLT.second.getVectorNumElements(); 919 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 920 return SubLT.first; 921 } 922 } 923 924 // We are going to permute multiple sources and the result will be in multiple 925 // destinations. Providing an accurate cost only for splits where the element 926 // type remains the same. 927 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 928 MVT LegalVT = LT.second; 929 if (LegalVT.isVector() && 930 LegalVT.getVectorElementType().getSizeInBits() == 931 Tp->getVectorElementType()->getPrimitiveSizeInBits() && 932 LegalVT.getVectorNumElements() < Tp->getVectorNumElements()) { 933 934 unsigned VecTySize = DL.getTypeStoreSize(Tp); 935 unsigned LegalVTSize = LegalVT.getStoreSize(); 936 // Number of source vectors after legalization: 937 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 938 // Number of destination vectors after legalization: 939 unsigned NumOfDests = LT.first; 940 941 Type *SingleOpTy = VectorType::get(Tp->getVectorElementType(), 942 LegalVT.getVectorNumElements()); 943 944 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 945 return NumOfShuffles * 946 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 0, nullptr); 947 } 948 949 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 950 } 951 952 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 953 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 954 // We assume that source and destination have the same vector type. 955 int NumOfDests = LT.first; 956 int NumOfShufflesPerDest = LT.first * 2 - 1; 957 LT.first = NumOfDests * NumOfShufflesPerDest; 958 } 959 960 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 961 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 962 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 963 964 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 965 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 966 967 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 1}, // vpermt2b 968 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 1}, // vpermt2b 969 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1} // vpermt2b 970 }; 971 972 if (ST->hasVBMI()) 973 if (const auto *Entry = 974 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 975 return LT.first * Entry->Cost; 976 977 static const CostTblEntry AVX512BWShuffleTbl[] = { 978 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 979 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 980 981 {TTI::SK_Reverse, MVT::v32i16, 1}, // vpermw 982 {TTI::SK_Reverse, MVT::v16i16, 1}, // vpermw 983 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 984 985 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 1}, // vpermw 986 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 1}, // vpermw 987 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // vpermw 988 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 989 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 3}, // vpermw + zext/trunc 990 991 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 1}, // vpermt2w 992 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 1}, // vpermt2w 993 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpermt2w 994 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 3}, // zext + vpermt2w + trunc 995 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 996 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3} // zext + vpermt2w + trunc 997 }; 998 999 if (ST->hasBWI()) 1000 if (const auto *Entry = 1001 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1002 return LT.first * Entry->Cost; 1003 1004 static const CostTblEntry AVX512ShuffleTbl[] = { 1005 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1006 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1007 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1008 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1009 1010 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1011 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1012 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1013 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1014 1015 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1016 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1017 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1018 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1019 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1020 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1021 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1022 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1023 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1024 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1025 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1026 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1027 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1028 1029 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1030 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1031 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1032 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1033 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1034 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1035 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1036 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1037 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1038 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1039 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1040 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1} // vpermt2d 1041 }; 1042 1043 if (ST->hasAVX512()) 1044 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1045 return LT.first * Entry->Cost; 1046 1047 static const CostTblEntry AVX2ShuffleTbl[] = { 1048 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1049 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1050 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1051 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1052 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1053 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1054 1055 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1056 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1057 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1058 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1059 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1060 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1061 1062 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1063 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1064 1065 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1066 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1067 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1068 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1069 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1070 // + vpblendvb 1071 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1072 // + vpblendvb 1073 1074 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1075 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1076 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1077 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1078 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1079 // + vpblendvb 1080 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1081 // + vpblendvb 1082 }; 1083 1084 if (ST->hasAVX2()) 1085 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1086 return LT.first * Entry->Cost; 1087 1088 static const CostTblEntry XOPShuffleTbl[] = { 1089 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1090 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1091 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1092 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1093 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1094 // + vinsertf128 1095 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1096 // + vinsertf128 1097 1098 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1099 // + vinsertf128 1100 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1101 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1102 // + vinsertf128 1103 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1104 }; 1105 1106 if (ST->hasXOP()) 1107 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1108 return LT.first * Entry->Cost; 1109 1110 static const CostTblEntry AVX1ShuffleTbl[] = { 1111 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1112 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1113 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1114 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1115 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1116 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1117 1118 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1119 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1120 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1121 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1122 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1123 // + vinsertf128 1124 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1125 // + vinsertf128 1126 1127 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1128 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1129 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1130 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1131 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1132 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1133 1134 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1135 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1136 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1137 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1138 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1139 // + 2*por + vinsertf128 1140 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1141 // + 2*por + vinsertf128 1142 1143 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1144 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1145 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1146 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1147 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1148 // + 4*por + vinsertf128 1149 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1150 // + 4*por + vinsertf128 1151 }; 1152 1153 if (ST->hasAVX()) 1154 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1155 return LT.first * Entry->Cost; 1156 1157 static const CostTblEntry SSE41ShuffleTbl[] = { 1158 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1159 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1160 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1161 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1162 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1163 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1164 }; 1165 1166 if (ST->hasSSE41()) 1167 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1168 return LT.first * Entry->Cost; 1169 1170 static const CostTblEntry SSSE3ShuffleTbl[] = { 1171 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1172 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1173 1174 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1175 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1176 1177 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1178 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1179 1180 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1181 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1182 1183 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1184 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1185 }; 1186 1187 if (ST->hasSSSE3()) 1188 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1189 return LT.first * Entry->Cost; 1190 1191 static const CostTblEntry SSE2ShuffleTbl[] = { 1192 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1193 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1194 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1195 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1196 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1197 1198 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1199 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1200 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1201 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1202 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1203 // + 2*pshufd + 2*unpck + packus 1204 1205 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1206 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1207 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1208 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1209 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1210 1211 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1212 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1213 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1214 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1215 // + pshufd/unpck 1216 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1217 // + 2*pshufd + 2*unpck + 2*packus 1218 1219 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1220 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1221 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1222 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1223 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1224 }; 1225 1226 if (ST->hasSSE2()) 1227 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1228 return LT.first * Entry->Cost; 1229 1230 static const CostTblEntry SSE1ShuffleTbl[] = { 1231 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1232 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1233 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1234 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1235 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1236 }; 1237 1238 if (ST->hasSSE1()) 1239 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1240 return LT.first * Entry->Cost; 1241 1242 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 1243 } 1244 1245 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 1246 const Instruction *I) { 1247 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1248 assert(ISD && "Invalid opcode"); 1249 1250 // FIXME: Need a better design of the cost table to handle non-simple types of 1251 // potential massive combinations (elem_num x src_type x dst_type). 1252 1253 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1254 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1255 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1256 1257 // Mask sign extend has an instruction. 1258 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1259 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1260 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1261 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1262 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1263 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1264 1265 // Mask zero extend is a load + broadcast. 1266 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1267 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1268 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1269 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1270 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1271 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1272 }; 1273 1274 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1275 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1276 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1277 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1278 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1279 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1280 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1281 1282 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1283 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1284 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1285 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1286 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1287 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1288 1289 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1290 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1291 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1292 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1293 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1294 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1295 1296 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1297 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1298 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1299 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1300 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1301 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1302 }; 1303 1304 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1305 // 256-bit wide vectors. 1306 1307 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1308 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1309 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1310 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1311 1312 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 }, 1313 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 }, 1314 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 }, 1315 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 1316 1317 // v16i1 -> v16i32 - load + broadcast 1318 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1319 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1320 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1321 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1322 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1323 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1324 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1325 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1326 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1327 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1328 1329 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1330 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1331 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1332 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1333 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1334 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1335 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1336 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1337 1338 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1339 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1340 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1341 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1342 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1343 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1344 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1345 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1346 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1347 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1348 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1349 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1350 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1351 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1352 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1353 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1354 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1355 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1356 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1357 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1358 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1359 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1360 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1361 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1362 1363 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1364 1365 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1366 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1367 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1368 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1369 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 2 }, 1370 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 2 }, 1371 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1372 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 2 }, 1373 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 2 }, 1374 }; 1375 1376 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1377 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1378 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1379 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1380 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1381 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 1382 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 1383 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 1384 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 1385 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1386 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1387 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1388 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1389 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1390 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1391 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1392 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1393 1394 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 1395 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 1396 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1397 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 1398 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1399 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 }, 1400 1401 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1402 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1403 1404 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1405 }; 1406 1407 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1408 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1409 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1410 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1411 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1412 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 }, 1413 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1414 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 7 }, 1415 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1416 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1417 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1418 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 }, 1419 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1420 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1421 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1422 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1423 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1424 1425 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 1426 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1427 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1428 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1429 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 1430 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 }, 1431 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 }, 1432 1433 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1434 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1435 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1436 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1437 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1438 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1439 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1440 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1441 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1442 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1443 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1444 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1445 1446 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1447 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1448 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1449 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1450 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1451 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1452 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1453 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1454 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1455 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 }, 1456 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 1457 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1458 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 1459 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1460 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1461 // The generic code to compute the scalar overhead is currently broken. 1462 // Workaround this limitation by estimating the scalarization overhead 1463 // here. We have roughly 10 instructions per scalar element. 1464 // Multiply that by the vector width. 1465 // FIXME: remove that when PR19268 is fixed. 1466 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1467 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1468 1469 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 }, 1470 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 }, 1471 // This node is expanded into scalarized operations but BasicTTI is overly 1472 // optimistic estimating its cost. It computes 3 per element (one 1473 // vector-extract, one scalar conversion and one vector-insert). The 1474 // problem is that the inserts form a read-modify-write chain so latency 1475 // should be factored in too. Inflating the cost per element by 1. 1476 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, 1477 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 1478 1479 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 1480 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 1481 }; 1482 1483 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 1484 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1485 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1486 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1487 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1488 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1489 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1490 1491 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1492 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 }, 1493 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1494 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1495 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1496 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1497 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1498 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1499 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1500 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1501 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1502 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1503 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1504 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1505 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1506 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1507 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1508 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1509 1510 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, 1511 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 1512 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 1513 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 1514 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 1515 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 1516 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 1517 1518 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 1519 }; 1520 1521 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 1522 // These are somewhat magic numbers justified by looking at the output of 1523 // Intel's IACA, running some kernels and making sure when we take 1524 // legalization into account the throughput will be overestimated. 1525 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1526 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1527 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1528 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1529 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1530 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1531 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1532 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 1533 1534 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1535 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1536 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1537 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1538 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1539 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, 1540 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 }, 1541 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1542 1543 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 3 }, 1544 1545 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 }, 1546 1547 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1548 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 1549 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 1550 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 1551 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1552 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 1553 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1554 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 1555 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1556 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1557 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1558 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1559 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 1560 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 1561 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1562 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 1563 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1564 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 1565 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1566 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1567 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 1568 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 1569 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1570 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 1571 1572 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 4 }, 1573 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, 1574 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 1575 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 1576 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 1577 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1578 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 1579 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1580 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 1581 }; 1582 1583 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 1584 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst); 1585 1586 if (ST->hasSSE2() && !ST->hasAVX()) { 1587 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1588 LTDest.second, LTSrc.second)) 1589 return LTSrc.first * Entry->Cost; 1590 } 1591 1592 EVT SrcTy = TLI->getValueType(DL, Src); 1593 EVT DstTy = TLI->getValueType(DL, Dst); 1594 1595 // The function getSimpleVT only handles simple value types. 1596 if (!SrcTy.isSimple() || !DstTy.isSimple()) 1597 return BaseT::getCastInstrCost(Opcode, Dst, Src); 1598 1599 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 1600 MVT SimpleDstTy = DstTy.getSimpleVT(); 1601 1602 // Make sure that neither type is going to be split before using the 1603 // AVX512 tables. This handles -mprefer-vector-width=256 1604 // with -min-legal-vector-width<=256 1605 if (TLI->getTypeAction(SimpleSrcTy) != TargetLowering::TypeSplitVector && 1606 TLI->getTypeAction(SimpleDstTy) != TargetLowering::TypeSplitVector) { 1607 if (ST->hasBWI()) 1608 if (const auto *Entry = ConvertCostTableLookup(AVX512BWConversionTbl, ISD, 1609 SimpleDstTy, SimpleSrcTy)) 1610 return Entry->Cost; 1611 1612 if (ST->hasDQI()) 1613 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 1614 SimpleDstTy, SimpleSrcTy)) 1615 return Entry->Cost; 1616 1617 if (ST->hasAVX512()) 1618 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 1619 SimpleDstTy, SimpleSrcTy)) 1620 return Entry->Cost; 1621 } 1622 1623 if (ST->hasAVX2()) { 1624 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 1625 SimpleDstTy, SimpleSrcTy)) 1626 return Entry->Cost; 1627 } 1628 1629 if (ST->hasAVX()) { 1630 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 1631 SimpleDstTy, SimpleSrcTy)) 1632 return Entry->Cost; 1633 } 1634 1635 if (ST->hasSSE41()) { 1636 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 1637 SimpleDstTy, SimpleSrcTy)) 1638 return Entry->Cost; 1639 } 1640 1641 if (ST->hasSSE2()) { 1642 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1643 SimpleDstTy, SimpleSrcTy)) 1644 return Entry->Cost; 1645 } 1646 1647 return BaseT::getCastInstrCost(Opcode, Dst, Src, I); 1648 } 1649 1650 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 1651 const Instruction *I) { 1652 // Legalize the type. 1653 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 1654 1655 MVT MTy = LT.second; 1656 1657 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1658 assert(ISD && "Invalid opcode"); 1659 1660 unsigned ExtraCost = 0; 1661 if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) { 1662 // Some vector comparison predicates cost extra instructions. 1663 if (MTy.isVector() && 1664 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 1665 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 1666 ST->hasBWI())) { 1667 switch (cast<CmpInst>(I)->getPredicate()) { 1668 case CmpInst::Predicate::ICMP_NE: 1669 // xor(cmpeq(x,y),-1) 1670 ExtraCost = 1; 1671 break; 1672 case CmpInst::Predicate::ICMP_SGE: 1673 case CmpInst::Predicate::ICMP_SLE: 1674 // xor(cmpgt(x,y),-1) 1675 ExtraCost = 1; 1676 break; 1677 case CmpInst::Predicate::ICMP_ULT: 1678 case CmpInst::Predicate::ICMP_UGT: 1679 // cmpgt(xor(x,signbit),xor(y,signbit)) 1680 // xor(cmpeq(pmaxu(x,y),x),-1) 1681 ExtraCost = 2; 1682 break; 1683 case CmpInst::Predicate::ICMP_ULE: 1684 case CmpInst::Predicate::ICMP_UGE: 1685 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 1686 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 1687 // cmpeq(psubus(x,y),0) 1688 // cmpeq(pminu(x,y),x) 1689 ExtraCost = 1; 1690 } else { 1691 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 1692 ExtraCost = 3; 1693 } 1694 break; 1695 default: 1696 break; 1697 } 1698 } 1699 } 1700 1701 static const CostTblEntry AVX512BWCostTbl[] = { 1702 { ISD::SETCC, MVT::v32i16, 1 }, 1703 { ISD::SETCC, MVT::v64i8, 1 }, 1704 1705 { ISD::SELECT, MVT::v32i16, 1 }, 1706 { ISD::SELECT, MVT::v64i8, 1 }, 1707 }; 1708 1709 static const CostTblEntry AVX512CostTbl[] = { 1710 { ISD::SETCC, MVT::v8i64, 1 }, 1711 { ISD::SETCC, MVT::v16i32, 1 }, 1712 { ISD::SETCC, MVT::v8f64, 1 }, 1713 { ISD::SETCC, MVT::v16f32, 1 }, 1714 1715 { ISD::SELECT, MVT::v8i64, 1 }, 1716 { ISD::SELECT, MVT::v16i32, 1 }, 1717 { ISD::SELECT, MVT::v8f64, 1 }, 1718 { ISD::SELECT, MVT::v16f32, 1 }, 1719 }; 1720 1721 static const CostTblEntry AVX2CostTbl[] = { 1722 { ISD::SETCC, MVT::v4i64, 1 }, 1723 { ISD::SETCC, MVT::v8i32, 1 }, 1724 { ISD::SETCC, MVT::v16i16, 1 }, 1725 { ISD::SETCC, MVT::v32i8, 1 }, 1726 1727 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 1728 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 1729 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 1730 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 1731 }; 1732 1733 static const CostTblEntry AVX1CostTbl[] = { 1734 { ISD::SETCC, MVT::v4f64, 1 }, 1735 { ISD::SETCC, MVT::v8f32, 1 }, 1736 // AVX1 does not support 8-wide integer compare. 1737 { ISD::SETCC, MVT::v4i64, 4 }, 1738 { ISD::SETCC, MVT::v8i32, 4 }, 1739 { ISD::SETCC, MVT::v16i16, 4 }, 1740 { ISD::SETCC, MVT::v32i8, 4 }, 1741 1742 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 1743 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 1744 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 1745 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 1746 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 1747 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 1748 }; 1749 1750 static const CostTblEntry SSE42CostTbl[] = { 1751 { ISD::SETCC, MVT::v2f64, 1 }, 1752 { ISD::SETCC, MVT::v4f32, 1 }, 1753 { ISD::SETCC, MVT::v2i64, 1 }, 1754 }; 1755 1756 static const CostTblEntry SSE41CostTbl[] = { 1757 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 1758 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 1759 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 1760 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 1761 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 1762 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 1763 }; 1764 1765 static const CostTblEntry SSE2CostTbl[] = { 1766 { ISD::SETCC, MVT::v2f64, 2 }, 1767 { ISD::SETCC, MVT::f64, 1 }, 1768 { ISD::SETCC, MVT::v2i64, 8 }, 1769 { ISD::SETCC, MVT::v4i32, 1 }, 1770 { ISD::SETCC, MVT::v8i16, 1 }, 1771 { ISD::SETCC, MVT::v16i8, 1 }, 1772 1773 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 1774 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 1775 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 1776 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 1777 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 1778 }; 1779 1780 static const CostTblEntry SSE1CostTbl[] = { 1781 { ISD::SETCC, MVT::v4f32, 2 }, 1782 { ISD::SETCC, MVT::f32, 1 }, 1783 1784 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 1785 }; 1786 1787 if (ST->hasBWI()) 1788 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 1789 return LT.first * (ExtraCost + Entry->Cost); 1790 1791 if (ST->hasAVX512()) 1792 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 1793 return LT.first * (ExtraCost + Entry->Cost); 1794 1795 if (ST->hasAVX2()) 1796 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 1797 return LT.first * (ExtraCost + Entry->Cost); 1798 1799 if (ST->hasAVX()) 1800 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 1801 return LT.first * (ExtraCost + Entry->Cost); 1802 1803 if (ST->hasSSE42()) 1804 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 1805 return LT.first * (ExtraCost + Entry->Cost); 1806 1807 if (ST->hasSSE41()) 1808 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 1809 return LT.first * (ExtraCost + Entry->Cost); 1810 1811 if (ST->hasSSE2()) 1812 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 1813 return LT.first * (ExtraCost + Entry->Cost); 1814 1815 if (ST->hasSSE1()) 1816 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 1817 return LT.first * (ExtraCost + Entry->Cost); 1818 1819 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I); 1820 } 1821 1822 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 1823 1824 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 1825 ArrayRef<Type *> Tys, FastMathFlags FMF, 1826 unsigned ScalarizationCostPassed) { 1827 // Costs should match the codegen from: 1828 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 1829 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 1830 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 1831 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 1832 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 1833 static const CostTblEntry AVX512CDCostTbl[] = { 1834 { ISD::CTLZ, MVT::v8i64, 1 }, 1835 { ISD::CTLZ, MVT::v16i32, 1 }, 1836 { ISD::CTLZ, MVT::v32i16, 8 }, 1837 { ISD::CTLZ, MVT::v64i8, 20 }, 1838 { ISD::CTLZ, MVT::v4i64, 1 }, 1839 { ISD::CTLZ, MVT::v8i32, 1 }, 1840 { ISD::CTLZ, MVT::v16i16, 4 }, 1841 { ISD::CTLZ, MVT::v32i8, 10 }, 1842 { ISD::CTLZ, MVT::v2i64, 1 }, 1843 { ISD::CTLZ, MVT::v4i32, 1 }, 1844 { ISD::CTLZ, MVT::v8i16, 4 }, 1845 { ISD::CTLZ, MVT::v16i8, 4 }, 1846 }; 1847 static const CostTblEntry AVX512BWCostTbl[] = { 1848 { ISD::BITREVERSE, MVT::v8i64, 5 }, 1849 { ISD::BITREVERSE, MVT::v16i32, 5 }, 1850 { ISD::BITREVERSE, MVT::v32i16, 5 }, 1851 { ISD::BITREVERSE, MVT::v64i8, 5 }, 1852 { ISD::CTLZ, MVT::v8i64, 23 }, 1853 { ISD::CTLZ, MVT::v16i32, 22 }, 1854 { ISD::CTLZ, MVT::v32i16, 18 }, 1855 { ISD::CTLZ, MVT::v64i8, 17 }, 1856 { ISD::CTPOP, MVT::v8i64, 7 }, 1857 { ISD::CTPOP, MVT::v16i32, 11 }, 1858 { ISD::CTPOP, MVT::v32i16, 9 }, 1859 { ISD::CTPOP, MVT::v64i8, 6 }, 1860 { ISD::CTTZ, MVT::v8i64, 10 }, 1861 { ISD::CTTZ, MVT::v16i32, 14 }, 1862 { ISD::CTTZ, MVT::v32i16, 12 }, 1863 { ISD::CTTZ, MVT::v64i8, 9 }, 1864 { ISD::SADDSAT, MVT::v32i16, 1 }, 1865 { ISD::SADDSAT, MVT::v64i8, 1 }, 1866 { ISD::SSUBSAT, MVT::v32i16, 1 }, 1867 { ISD::SSUBSAT, MVT::v64i8, 1 }, 1868 { ISD::UADDSAT, MVT::v32i16, 1 }, 1869 { ISD::UADDSAT, MVT::v64i8, 1 }, 1870 { ISD::USUBSAT, MVT::v32i16, 1 }, 1871 { ISD::USUBSAT, MVT::v64i8, 1 }, 1872 }; 1873 static const CostTblEntry AVX512CostTbl[] = { 1874 { ISD::BITREVERSE, MVT::v8i64, 36 }, 1875 { ISD::BITREVERSE, MVT::v16i32, 24 }, 1876 { ISD::CTLZ, MVT::v8i64, 29 }, 1877 { ISD::CTLZ, MVT::v16i32, 35 }, 1878 { ISD::CTPOP, MVT::v8i64, 16 }, 1879 { ISD::CTPOP, MVT::v16i32, 24 }, 1880 { ISD::CTTZ, MVT::v8i64, 20 }, 1881 { ISD::CTTZ, MVT::v16i32, 28 }, 1882 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 1883 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 1884 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 1885 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 1886 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 1887 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 1888 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 1889 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 1890 }; 1891 static const CostTblEntry XOPCostTbl[] = { 1892 { ISD::BITREVERSE, MVT::v4i64, 4 }, 1893 { ISD::BITREVERSE, MVT::v8i32, 4 }, 1894 { ISD::BITREVERSE, MVT::v16i16, 4 }, 1895 { ISD::BITREVERSE, MVT::v32i8, 4 }, 1896 { ISD::BITREVERSE, MVT::v2i64, 1 }, 1897 { ISD::BITREVERSE, MVT::v4i32, 1 }, 1898 { ISD::BITREVERSE, MVT::v8i16, 1 }, 1899 { ISD::BITREVERSE, MVT::v16i8, 1 }, 1900 { ISD::BITREVERSE, MVT::i64, 3 }, 1901 { ISD::BITREVERSE, MVT::i32, 3 }, 1902 { ISD::BITREVERSE, MVT::i16, 3 }, 1903 { ISD::BITREVERSE, MVT::i8, 3 } 1904 }; 1905 static const CostTblEntry AVX2CostTbl[] = { 1906 { ISD::BITREVERSE, MVT::v4i64, 5 }, 1907 { ISD::BITREVERSE, MVT::v8i32, 5 }, 1908 { ISD::BITREVERSE, MVT::v16i16, 5 }, 1909 { ISD::BITREVERSE, MVT::v32i8, 5 }, 1910 { ISD::BSWAP, MVT::v4i64, 1 }, 1911 { ISD::BSWAP, MVT::v8i32, 1 }, 1912 { ISD::BSWAP, MVT::v16i16, 1 }, 1913 { ISD::CTLZ, MVT::v4i64, 23 }, 1914 { ISD::CTLZ, MVT::v8i32, 18 }, 1915 { ISD::CTLZ, MVT::v16i16, 14 }, 1916 { ISD::CTLZ, MVT::v32i8, 9 }, 1917 { ISD::CTPOP, MVT::v4i64, 7 }, 1918 { ISD::CTPOP, MVT::v8i32, 11 }, 1919 { ISD::CTPOP, MVT::v16i16, 9 }, 1920 { ISD::CTPOP, MVT::v32i8, 6 }, 1921 { ISD::CTTZ, MVT::v4i64, 10 }, 1922 { ISD::CTTZ, MVT::v8i32, 14 }, 1923 { ISD::CTTZ, MVT::v16i16, 12 }, 1924 { ISD::CTTZ, MVT::v32i8, 9 }, 1925 { ISD::SADDSAT, MVT::v16i16, 1 }, 1926 { ISD::SADDSAT, MVT::v32i8, 1 }, 1927 { ISD::SSUBSAT, MVT::v16i16, 1 }, 1928 { ISD::SSUBSAT, MVT::v32i8, 1 }, 1929 { ISD::UADDSAT, MVT::v16i16, 1 }, 1930 { ISD::UADDSAT, MVT::v32i8, 1 }, 1931 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 1932 { ISD::USUBSAT, MVT::v16i16, 1 }, 1933 { ISD::USUBSAT, MVT::v32i8, 1 }, 1934 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 1935 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 1936 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 1937 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 1938 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 1939 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 1940 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 1941 }; 1942 static const CostTblEntry AVX1CostTbl[] = { 1943 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 1944 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 1945 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 1946 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 1947 { ISD::BSWAP, MVT::v4i64, 4 }, 1948 { ISD::BSWAP, MVT::v8i32, 4 }, 1949 { ISD::BSWAP, MVT::v16i16, 4 }, 1950 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 1951 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 1952 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 1953 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 1954 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 1955 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 1956 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 1957 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 1958 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 1959 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 1960 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 1961 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 1962 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 1963 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 1964 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 1965 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 1966 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 1967 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 1968 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 1969 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 1970 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 1971 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 1972 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 1973 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 1974 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 1975 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 1976 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 1977 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 1978 }; 1979 static const CostTblEntry GLMCostTbl[] = { 1980 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 1981 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 1982 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 1983 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 1984 }; 1985 static const CostTblEntry SLMCostTbl[] = { 1986 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 1987 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 1988 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 1989 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 1990 }; 1991 static const CostTblEntry SSE42CostTbl[] = { 1992 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 1993 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 1994 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 1995 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 1996 }; 1997 static const CostTblEntry SSSE3CostTbl[] = { 1998 { ISD::BITREVERSE, MVT::v2i64, 5 }, 1999 { ISD::BITREVERSE, MVT::v4i32, 5 }, 2000 { ISD::BITREVERSE, MVT::v8i16, 5 }, 2001 { ISD::BITREVERSE, MVT::v16i8, 5 }, 2002 { ISD::BSWAP, MVT::v2i64, 1 }, 2003 { ISD::BSWAP, MVT::v4i32, 1 }, 2004 { ISD::BSWAP, MVT::v8i16, 1 }, 2005 { ISD::CTLZ, MVT::v2i64, 23 }, 2006 { ISD::CTLZ, MVT::v4i32, 18 }, 2007 { ISD::CTLZ, MVT::v8i16, 14 }, 2008 { ISD::CTLZ, MVT::v16i8, 9 }, 2009 { ISD::CTPOP, MVT::v2i64, 7 }, 2010 { ISD::CTPOP, MVT::v4i32, 11 }, 2011 { ISD::CTPOP, MVT::v8i16, 9 }, 2012 { ISD::CTPOP, MVT::v16i8, 6 }, 2013 { ISD::CTTZ, MVT::v2i64, 10 }, 2014 { ISD::CTTZ, MVT::v4i32, 14 }, 2015 { ISD::CTTZ, MVT::v8i16, 12 }, 2016 { ISD::CTTZ, MVT::v16i8, 9 } 2017 }; 2018 static const CostTblEntry SSE2CostTbl[] = { 2019 { ISD::BITREVERSE, MVT::v2i64, 29 }, 2020 { ISD::BITREVERSE, MVT::v4i32, 27 }, 2021 { ISD::BITREVERSE, MVT::v8i16, 27 }, 2022 { ISD::BITREVERSE, MVT::v16i8, 20 }, 2023 { ISD::BSWAP, MVT::v2i64, 7 }, 2024 { ISD::BSWAP, MVT::v4i32, 7 }, 2025 { ISD::BSWAP, MVT::v8i16, 7 }, 2026 { ISD::CTLZ, MVT::v2i64, 25 }, 2027 { ISD::CTLZ, MVT::v4i32, 26 }, 2028 { ISD::CTLZ, MVT::v8i16, 20 }, 2029 { ISD::CTLZ, MVT::v16i8, 17 }, 2030 { ISD::CTPOP, MVT::v2i64, 12 }, 2031 { ISD::CTPOP, MVT::v4i32, 15 }, 2032 { ISD::CTPOP, MVT::v8i16, 13 }, 2033 { ISD::CTPOP, MVT::v16i8, 10 }, 2034 { ISD::CTTZ, MVT::v2i64, 14 }, 2035 { ISD::CTTZ, MVT::v4i32, 18 }, 2036 { ISD::CTTZ, MVT::v8i16, 16 }, 2037 { ISD::CTTZ, MVT::v16i8, 13 }, 2038 { ISD::SADDSAT, MVT::v8i16, 1 }, 2039 { ISD::SADDSAT, MVT::v16i8, 1 }, 2040 { ISD::SSUBSAT, MVT::v8i16, 1 }, 2041 { ISD::SSUBSAT, MVT::v16i8, 1 }, 2042 { ISD::UADDSAT, MVT::v8i16, 1 }, 2043 { ISD::UADDSAT, MVT::v16i8, 1 }, 2044 { ISD::USUBSAT, MVT::v8i16, 1 }, 2045 { ISD::USUBSAT, MVT::v16i8, 1 }, 2046 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 2047 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 2048 }; 2049 static const CostTblEntry SSE1CostTbl[] = { 2050 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 2051 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 2052 }; 2053 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2054 { ISD::BITREVERSE, MVT::i64, 14 }, 2055 { ISD::SADDO, MVT::i64, 1 }, 2056 { ISD::UADDO, MVT::i64, 1 }, 2057 }; 2058 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2059 { ISD::BITREVERSE, MVT::i32, 14 }, 2060 { ISD::BITREVERSE, MVT::i16, 14 }, 2061 { ISD::BITREVERSE, MVT::i8, 11 }, 2062 { ISD::SADDO, MVT::i32, 1 }, 2063 { ISD::SADDO, MVT::i16, 1 }, 2064 { ISD::SADDO, MVT::i8, 1 }, 2065 { ISD::UADDO, MVT::i32, 1 }, 2066 { ISD::UADDO, MVT::i16, 1 }, 2067 { ISD::UADDO, MVT::i8, 1 }, 2068 }; 2069 2070 Type *OpTy = RetTy; 2071 unsigned ISD = ISD::DELETED_NODE; 2072 switch (IID) { 2073 default: 2074 break; 2075 case Intrinsic::bitreverse: 2076 ISD = ISD::BITREVERSE; 2077 break; 2078 case Intrinsic::bswap: 2079 ISD = ISD::BSWAP; 2080 break; 2081 case Intrinsic::ctlz: 2082 ISD = ISD::CTLZ; 2083 break; 2084 case Intrinsic::ctpop: 2085 ISD = ISD::CTPOP; 2086 break; 2087 case Intrinsic::cttz: 2088 ISD = ISD::CTTZ; 2089 break; 2090 case Intrinsic::sadd_sat: 2091 ISD = ISD::SADDSAT; 2092 break; 2093 case Intrinsic::ssub_sat: 2094 ISD = ISD::SSUBSAT; 2095 break; 2096 case Intrinsic::uadd_sat: 2097 ISD = ISD::UADDSAT; 2098 break; 2099 case Intrinsic::usub_sat: 2100 ISD = ISD::USUBSAT; 2101 break; 2102 case Intrinsic::sqrt: 2103 ISD = ISD::FSQRT; 2104 break; 2105 case Intrinsic::sadd_with_overflow: 2106 case Intrinsic::ssub_with_overflow: 2107 // SSUBO has same costs so don't duplicate. 2108 ISD = ISD::SADDO; 2109 OpTy = RetTy->getContainedType(0); 2110 break; 2111 case Intrinsic::uadd_with_overflow: 2112 case Intrinsic::usub_with_overflow: 2113 // USUBO has same costs so don't duplicate. 2114 ISD = ISD::UADDO; 2115 OpTy = RetTy->getContainedType(0); 2116 break; 2117 } 2118 2119 if (ISD != ISD::DELETED_NODE) { 2120 // Legalize the type. 2121 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 2122 MVT MTy = LT.second; 2123 2124 // Attempt to lookup cost. 2125 if (ST->isGLM()) 2126 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 2127 return LT.first * Entry->Cost; 2128 2129 if (ST->isSLM()) 2130 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2131 return LT.first * Entry->Cost; 2132 2133 if (ST->hasCDI()) 2134 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 2135 return LT.first * Entry->Cost; 2136 2137 if (ST->hasBWI()) 2138 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2139 return LT.first * Entry->Cost; 2140 2141 if (ST->hasAVX512()) 2142 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2143 return LT.first * Entry->Cost; 2144 2145 if (ST->hasXOP()) 2146 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2147 return LT.first * Entry->Cost; 2148 2149 if (ST->hasAVX2()) 2150 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2151 return LT.first * Entry->Cost; 2152 2153 if (ST->hasAVX()) 2154 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2155 return LT.first * Entry->Cost; 2156 2157 if (ST->hasSSE42()) 2158 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2159 return LT.first * Entry->Cost; 2160 2161 if (ST->hasSSSE3()) 2162 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 2163 return LT.first * Entry->Cost; 2164 2165 if (ST->hasSSE2()) 2166 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2167 return LT.first * Entry->Cost; 2168 2169 if (ST->hasSSE1()) 2170 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2171 return LT.first * Entry->Cost; 2172 2173 if (ST->is64Bit()) 2174 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2175 return LT.first * Entry->Cost; 2176 2177 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2178 return LT.first * Entry->Cost; 2179 } 2180 2181 return BaseT::getIntrinsicInstrCost(IID, RetTy, Tys, FMF, ScalarizationCostPassed); 2182 } 2183 2184 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 2185 ArrayRef<Value *> Args, FastMathFlags FMF, 2186 unsigned VF) { 2187 static const CostTblEntry AVX512CostTbl[] = { 2188 { ISD::ROTL, MVT::v8i64, 1 }, 2189 { ISD::ROTL, MVT::v4i64, 1 }, 2190 { ISD::ROTL, MVT::v2i64, 1 }, 2191 { ISD::ROTL, MVT::v16i32, 1 }, 2192 { ISD::ROTL, MVT::v8i32, 1 }, 2193 { ISD::ROTL, MVT::v4i32, 1 }, 2194 { ISD::ROTR, MVT::v8i64, 1 }, 2195 { ISD::ROTR, MVT::v4i64, 1 }, 2196 { ISD::ROTR, MVT::v2i64, 1 }, 2197 { ISD::ROTR, MVT::v16i32, 1 }, 2198 { ISD::ROTR, MVT::v8i32, 1 }, 2199 { ISD::ROTR, MVT::v4i32, 1 } 2200 }; 2201 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 2202 static const CostTblEntry XOPCostTbl[] = { 2203 { ISD::ROTL, MVT::v4i64, 4 }, 2204 { ISD::ROTL, MVT::v8i32, 4 }, 2205 { ISD::ROTL, MVT::v16i16, 4 }, 2206 { ISD::ROTL, MVT::v32i8, 4 }, 2207 { ISD::ROTL, MVT::v2i64, 1 }, 2208 { ISD::ROTL, MVT::v4i32, 1 }, 2209 { ISD::ROTL, MVT::v8i16, 1 }, 2210 { ISD::ROTL, MVT::v16i8, 1 }, 2211 { ISD::ROTR, MVT::v4i64, 6 }, 2212 { ISD::ROTR, MVT::v8i32, 6 }, 2213 { ISD::ROTR, MVT::v16i16, 6 }, 2214 { ISD::ROTR, MVT::v32i8, 6 }, 2215 { ISD::ROTR, MVT::v2i64, 2 }, 2216 { ISD::ROTR, MVT::v4i32, 2 }, 2217 { ISD::ROTR, MVT::v8i16, 2 }, 2218 { ISD::ROTR, MVT::v16i8, 2 } 2219 }; 2220 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2221 { ISD::ROTL, MVT::i64, 1 }, 2222 { ISD::ROTR, MVT::i64, 1 }, 2223 { ISD::FSHL, MVT::i64, 4 } 2224 }; 2225 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2226 { ISD::ROTL, MVT::i32, 1 }, 2227 { ISD::ROTL, MVT::i16, 1 }, 2228 { ISD::ROTL, MVT::i8, 1 }, 2229 { ISD::ROTR, MVT::i32, 1 }, 2230 { ISD::ROTR, MVT::i16, 1 }, 2231 { ISD::ROTR, MVT::i8, 1 }, 2232 { ISD::FSHL, MVT::i32, 4 }, 2233 { ISD::FSHL, MVT::i16, 4 }, 2234 { ISD::FSHL, MVT::i8, 4 } 2235 }; 2236 2237 unsigned ISD = ISD::DELETED_NODE; 2238 switch (IID) { 2239 default: 2240 break; 2241 case Intrinsic::fshl: 2242 ISD = ISD::FSHL; 2243 if (Args[0] == Args[1]) 2244 ISD = ISD::ROTL; 2245 break; 2246 case Intrinsic::fshr: 2247 // FSHR has same costs so don't duplicate. 2248 ISD = ISD::FSHL; 2249 if (Args[0] == Args[1]) 2250 ISD = ISD::ROTR; 2251 break; 2252 } 2253 2254 if (ISD != ISD::DELETED_NODE) { 2255 // Legalize the type. 2256 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 2257 MVT MTy = LT.second; 2258 2259 // Attempt to lookup cost. 2260 if (ST->hasAVX512()) 2261 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2262 return LT.first * Entry->Cost; 2263 2264 if (ST->hasXOP()) 2265 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2266 return LT.first * Entry->Cost; 2267 2268 if (ST->is64Bit()) 2269 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2270 return LT.first * Entry->Cost; 2271 2272 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2273 return LT.first * Entry->Cost; 2274 } 2275 2276 return BaseT::getIntrinsicInstrCost(IID, RetTy, Args, FMF, VF); 2277 } 2278 2279 int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { 2280 assert(Val->isVectorTy() && "This must be a vector type"); 2281 2282 Type *ScalarType = Val->getScalarType(); 2283 2284 if (Index != -1U) { 2285 // Legalize the type. 2286 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 2287 2288 // This type is legalized to a scalar type. 2289 if (!LT.second.isVector()) 2290 return 0; 2291 2292 // The type may be split. Normalize the index to the new type. 2293 unsigned Width = LT.second.getVectorNumElements(); 2294 Index = Index % Width; 2295 2296 // Floating point scalars are already located in index #0. 2297 if (ScalarType->isFloatingPointTy() && Index == 0) 2298 return 0; 2299 } 2300 2301 // Add to the base cost if we know that the extracted element of a vector is 2302 // destined to be moved to and used in the integer register file. 2303 int RegisterFileMoveCost = 0; 2304 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 2305 RegisterFileMoveCost = 1; 2306 2307 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 2308 } 2309 2310 int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, 2311 unsigned AddressSpace, const Instruction *I) { 2312 // Handle non-power-of-two vectors such as <3 x float> 2313 if (VectorType *VTy = dyn_cast<VectorType>(Src)) { 2314 unsigned NumElem = VTy->getVectorNumElements(); 2315 2316 // Handle a few common cases: 2317 // <3 x float> 2318 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 2319 // Cost = 64 bit store + extract + 32 bit store. 2320 return 3; 2321 2322 // <3 x double> 2323 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 2324 // Cost = 128 bit store + unpack + 64 bit store. 2325 return 3; 2326 2327 // Assume that all other non-power-of-two numbers are scalarized. 2328 if (!isPowerOf2_32(NumElem)) { 2329 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment, 2330 AddressSpace); 2331 int SplitCost = getScalarizationOverhead(Src, Opcode == Instruction::Load, 2332 Opcode == Instruction::Store); 2333 return NumElem * Cost + SplitCost; 2334 } 2335 } 2336 2337 // Legalize the type. 2338 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 2339 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 2340 "Invalid Opcode"); 2341 2342 // Each load/store unit costs 1. 2343 int Cost = LT.first * 1; 2344 2345 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a 2346 // proxy for a double-pumped AVX memory interface such as on Sandybridge. 2347 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow()) 2348 Cost *= 2; 2349 2350 return Cost; 2351 } 2352 2353 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, 2354 unsigned Alignment, 2355 unsigned AddressSpace) { 2356 VectorType *SrcVTy = dyn_cast<VectorType>(SrcTy); 2357 if (!SrcVTy) 2358 // To calculate scalar take the regular cost, without mask 2359 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace); 2360 2361 unsigned NumElem = SrcVTy->getVectorNumElements(); 2362 VectorType *MaskTy = 2363 VectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 2364 if ((Opcode == Instruction::Load && !isLegalMaskedLoad(SrcVTy)) || 2365 (Opcode == Instruction::Store && !isLegalMaskedStore(SrcVTy)) || 2366 !isPowerOf2_32(NumElem)) { 2367 // Scalarization 2368 int MaskSplitCost = getScalarizationOverhead(MaskTy, false, true); 2369 int ScalarCompareCost = getCmpSelInstrCost( 2370 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr); 2371 int BranchCost = getCFInstrCost(Instruction::Br); 2372 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 2373 2374 int ValueSplitCost = getScalarizationOverhead( 2375 SrcVTy, Opcode == Instruction::Load, Opcode == Instruction::Store); 2376 int MemopCost = 2377 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2378 Alignment, AddressSpace); 2379 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 2380 } 2381 2382 // Legalize the type. 2383 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 2384 auto VT = TLI->getValueType(DL, SrcVTy); 2385 int Cost = 0; 2386 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 2387 LT.second.getVectorNumElements() == NumElem) 2388 // Promotion requires expand/truncate for data and a shuffle for mask. 2389 Cost += getShuffleCost(TTI::SK_Select, SrcVTy, 0, nullptr) + 2390 getShuffleCost(TTI::SK_Select, MaskTy, 0, nullptr); 2391 2392 else if (LT.second.getVectorNumElements() > NumElem) { 2393 VectorType *NewMaskTy = VectorType::get(MaskTy->getVectorElementType(), 2394 LT.second.getVectorNumElements()); 2395 // Expanding requires fill mask with zeroes 2396 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, 0, MaskTy); 2397 } 2398 if (!ST->hasAVX512()) 2399 return Cost + LT.first*4; // Each maskmov costs 4 2400 2401 // AVX-512 masked load/store is cheapper 2402 return Cost+LT.first; 2403 } 2404 2405 int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE, 2406 const SCEV *Ptr) { 2407 // Address computations in vectorized code with non-consecutive addresses will 2408 // likely result in more instructions compared to scalar code where the 2409 // computation can more often be merged into the index mode. The resulting 2410 // extra micro-ops can significantly decrease throughput. 2411 unsigned NumVectorInstToHideOverhead = 10; 2412 2413 // Cost modeling of Strided Access Computation is hidden by the indexing 2414 // modes of X86 regardless of the stride value. We dont believe that there 2415 // is a difference between constant strided access in gerenal and constant 2416 // strided value which is less than or equal to 64. 2417 // Even in the case of (loop invariant) stride whose value is not known at 2418 // compile time, the address computation will not incur more than one extra 2419 // ADD instruction. 2420 if (Ty->isVectorTy() && SE) { 2421 if (!BaseT::isStridedAccess(Ptr)) 2422 return NumVectorInstToHideOverhead; 2423 if (!BaseT::getConstantStrideStep(SE, Ptr)) 2424 return 1; 2425 } 2426 2427 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 2428 } 2429 2430 int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, Type *ValTy, 2431 bool IsPairwise) { 2432 2433 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2434 2435 MVT MTy = LT.second; 2436 2437 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2438 assert(ISD && "Invalid opcode"); 2439 2440 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 2441 // and make it as the cost. 2442 2443 static const CostTblEntry SSE42CostTblPairWise[] = { 2444 { ISD::FADD, MVT::v2f64, 2 }, 2445 { ISD::FADD, MVT::v4f32, 4 }, 2446 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 2447 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5". 2448 { ISD::ADD, MVT::v8i16, 5 }, 2449 }; 2450 2451 static const CostTblEntry AVX1CostTblPairWise[] = { 2452 { ISD::FADD, MVT::v4f32, 4 }, 2453 { ISD::FADD, MVT::v4f64, 5 }, 2454 { ISD::FADD, MVT::v8f32, 7 }, 2455 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 2456 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5". 2457 { ISD::ADD, MVT::v4i64, 5 }, // The data reported by the IACA tool is "4.8". 2458 { ISD::ADD, MVT::v8i16, 5 }, 2459 { ISD::ADD, MVT::v8i32, 5 }, 2460 }; 2461 2462 static const CostTblEntry SSE42CostTblNoPairWise[] = { 2463 { ISD::FADD, MVT::v2f64, 2 }, 2464 { ISD::FADD, MVT::v4f32, 4 }, 2465 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 2466 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 2467 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 2468 }; 2469 2470 static const CostTblEntry AVX1CostTblNoPairWise[] = { 2471 { ISD::FADD, MVT::v4f32, 3 }, 2472 { ISD::FADD, MVT::v4f64, 3 }, 2473 { ISD::FADD, MVT::v8f32, 4 }, 2474 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 2475 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "2.8". 2476 { ISD::ADD, MVT::v4i64, 3 }, 2477 { ISD::ADD, MVT::v8i16, 4 }, 2478 { ISD::ADD, MVT::v8i32, 5 }, 2479 }; 2480 2481 if (IsPairwise) { 2482 if (ST->hasAVX()) 2483 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy)) 2484 return LT.first * Entry->Cost; 2485 2486 if (ST->hasSSE42()) 2487 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy)) 2488 return LT.first * Entry->Cost; 2489 } else { 2490 if (ST->hasAVX()) 2491 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 2492 return LT.first * Entry->Cost; 2493 2494 if (ST->hasSSE42()) 2495 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy)) 2496 return LT.first * Entry->Cost; 2497 } 2498 2499 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise); 2500 } 2501 2502 int X86TTIImpl::getMinMaxReductionCost(Type *ValTy, Type *CondTy, 2503 bool IsPairwise, bool IsUnsigned) { 2504 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2505 2506 MVT MTy = LT.second; 2507 2508 int ISD; 2509 if (ValTy->isIntOrIntVectorTy()) { 2510 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 2511 } else { 2512 assert(ValTy->isFPOrFPVectorTy() && 2513 "Expected float point or integer vector type."); 2514 ISD = ISD::FMINNUM; 2515 } 2516 2517 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 2518 // and make it as the cost. 2519 2520 static const CostTblEntry SSE42CostTblPairWise[] = { 2521 {ISD::FMINNUM, MVT::v2f64, 3}, 2522 {ISD::FMINNUM, MVT::v4f32, 2}, 2523 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8" 2524 {ISD::UMIN, MVT::v2i64, 8}, // The data reported by the IACA is "8.6" 2525 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5" 2526 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8" 2527 {ISD::SMIN, MVT::v8i16, 2}, 2528 {ISD::UMIN, MVT::v8i16, 2}, 2529 }; 2530 2531 static const CostTblEntry AVX1CostTblPairWise[] = { 2532 {ISD::FMINNUM, MVT::v4f32, 1}, 2533 {ISD::FMINNUM, MVT::v4f64, 1}, 2534 {ISD::FMINNUM, MVT::v8f32, 2}, 2535 {ISD::SMIN, MVT::v2i64, 3}, 2536 {ISD::UMIN, MVT::v2i64, 3}, 2537 {ISD::SMIN, MVT::v4i32, 1}, 2538 {ISD::UMIN, MVT::v4i32, 1}, 2539 {ISD::SMIN, MVT::v8i16, 1}, 2540 {ISD::UMIN, MVT::v8i16, 1}, 2541 {ISD::SMIN, MVT::v8i32, 3}, 2542 {ISD::UMIN, MVT::v8i32, 3}, 2543 }; 2544 2545 static const CostTblEntry AVX2CostTblPairWise[] = { 2546 {ISD::SMIN, MVT::v4i64, 2}, 2547 {ISD::UMIN, MVT::v4i64, 2}, 2548 {ISD::SMIN, MVT::v8i32, 1}, 2549 {ISD::UMIN, MVT::v8i32, 1}, 2550 {ISD::SMIN, MVT::v16i16, 1}, 2551 {ISD::UMIN, MVT::v16i16, 1}, 2552 {ISD::SMIN, MVT::v32i8, 2}, 2553 {ISD::UMIN, MVT::v32i8, 2}, 2554 }; 2555 2556 static const CostTblEntry AVX512CostTblPairWise[] = { 2557 {ISD::FMINNUM, MVT::v8f64, 1}, 2558 {ISD::FMINNUM, MVT::v16f32, 2}, 2559 {ISD::SMIN, MVT::v8i64, 2}, 2560 {ISD::UMIN, MVT::v8i64, 2}, 2561 {ISD::SMIN, MVT::v16i32, 1}, 2562 {ISD::UMIN, MVT::v16i32, 1}, 2563 }; 2564 2565 static const CostTblEntry SSE42CostTblNoPairWise[] = { 2566 {ISD::FMINNUM, MVT::v2f64, 3}, 2567 {ISD::FMINNUM, MVT::v4f32, 3}, 2568 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8" 2569 {ISD::UMIN, MVT::v2i64, 9}, // The data reported by the IACA is "8.6" 2570 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5" 2571 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8" 2572 {ISD::SMIN, MVT::v8i16, 1}, // The data reported by the IACA is "1.5" 2573 {ISD::UMIN, MVT::v8i16, 2}, // The data reported by the IACA is "1.8" 2574 }; 2575 2576 static const CostTblEntry AVX1CostTblNoPairWise[] = { 2577 {ISD::FMINNUM, MVT::v4f32, 1}, 2578 {ISD::FMINNUM, MVT::v4f64, 1}, 2579 {ISD::FMINNUM, MVT::v8f32, 1}, 2580 {ISD::SMIN, MVT::v2i64, 3}, 2581 {ISD::UMIN, MVT::v2i64, 3}, 2582 {ISD::SMIN, MVT::v4i32, 1}, 2583 {ISD::UMIN, MVT::v4i32, 1}, 2584 {ISD::SMIN, MVT::v8i16, 1}, 2585 {ISD::UMIN, MVT::v8i16, 1}, 2586 {ISD::SMIN, MVT::v8i32, 2}, 2587 {ISD::UMIN, MVT::v8i32, 2}, 2588 }; 2589 2590 static const CostTblEntry AVX2CostTblNoPairWise[] = { 2591 {ISD::SMIN, MVT::v4i64, 1}, 2592 {ISD::UMIN, MVT::v4i64, 1}, 2593 {ISD::SMIN, MVT::v8i32, 1}, 2594 {ISD::UMIN, MVT::v8i32, 1}, 2595 {ISD::SMIN, MVT::v16i16, 1}, 2596 {ISD::UMIN, MVT::v16i16, 1}, 2597 {ISD::SMIN, MVT::v32i8, 1}, 2598 {ISD::UMIN, MVT::v32i8, 1}, 2599 }; 2600 2601 static const CostTblEntry AVX512CostTblNoPairWise[] = { 2602 {ISD::FMINNUM, MVT::v8f64, 1}, 2603 {ISD::FMINNUM, MVT::v16f32, 2}, 2604 {ISD::SMIN, MVT::v8i64, 1}, 2605 {ISD::UMIN, MVT::v8i64, 1}, 2606 {ISD::SMIN, MVT::v16i32, 1}, 2607 {ISD::UMIN, MVT::v16i32, 1}, 2608 }; 2609 2610 if (IsPairwise) { 2611 if (ST->hasAVX512()) 2612 if (const auto *Entry = CostTableLookup(AVX512CostTblPairWise, ISD, MTy)) 2613 return LT.first * Entry->Cost; 2614 2615 if (ST->hasAVX2()) 2616 if (const auto *Entry = CostTableLookup(AVX2CostTblPairWise, ISD, MTy)) 2617 return LT.first * Entry->Cost; 2618 2619 if (ST->hasAVX()) 2620 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy)) 2621 return LT.first * Entry->Cost; 2622 2623 if (ST->hasSSE42()) 2624 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy)) 2625 return LT.first * Entry->Cost; 2626 } else { 2627 if (ST->hasAVX512()) 2628 if (const auto *Entry = 2629 CostTableLookup(AVX512CostTblNoPairWise, ISD, MTy)) 2630 return LT.first * Entry->Cost; 2631 2632 if (ST->hasAVX2()) 2633 if (const auto *Entry = CostTableLookup(AVX2CostTblNoPairWise, ISD, MTy)) 2634 return LT.first * Entry->Cost; 2635 2636 if (ST->hasAVX()) 2637 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 2638 return LT.first * Entry->Cost; 2639 2640 if (ST->hasSSE42()) 2641 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy)) 2642 return LT.first * Entry->Cost; 2643 } 2644 2645 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned); 2646 } 2647 2648 /// Calculate the cost of materializing a 64-bit value. This helper 2649 /// method might only calculate a fraction of a larger immediate. Therefore it 2650 /// is valid to return a cost of ZERO. 2651 int X86TTIImpl::getIntImmCost(int64_t Val) { 2652 if (Val == 0) 2653 return TTI::TCC_Free; 2654 2655 if (isInt<32>(Val)) 2656 return TTI::TCC_Basic; 2657 2658 return 2 * TTI::TCC_Basic; 2659 } 2660 2661 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { 2662 assert(Ty->isIntegerTy()); 2663 2664 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 2665 if (BitSize == 0) 2666 return ~0U; 2667 2668 // Never hoist constants larger than 128bit, because this might lead to 2669 // incorrect code generation or assertions in codegen. 2670 // Fixme: Create a cost model for types larger than i128 once the codegen 2671 // issues have been fixed. 2672 if (BitSize > 128) 2673 return TTI::TCC_Free; 2674 2675 if (Imm == 0) 2676 return TTI::TCC_Free; 2677 2678 // Sign-extend all constants to a multiple of 64-bit. 2679 APInt ImmVal = Imm; 2680 if (BitSize % 64 != 0) 2681 ImmVal = Imm.sext(alignTo(BitSize, 64)); 2682 2683 // Split the constant into 64-bit chunks and calculate the cost for each 2684 // chunk. 2685 int Cost = 0; 2686 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 2687 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 2688 int64_t Val = Tmp.getSExtValue(); 2689 Cost += getIntImmCost(Val); 2690 } 2691 // We need at least one instruction to materialize the constant. 2692 return std::max(1, Cost); 2693 } 2694 2695 int X86TTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, 2696 Type *Ty) { 2697 assert(Ty->isIntegerTy()); 2698 2699 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 2700 // There is no cost model for constants with a bit size of 0. Return TCC_Free 2701 // here, so that constant hoisting will ignore this constant. 2702 if (BitSize == 0) 2703 return TTI::TCC_Free; 2704 2705 unsigned ImmIdx = ~0U; 2706 switch (Opcode) { 2707 default: 2708 return TTI::TCC_Free; 2709 case Instruction::GetElementPtr: 2710 // Always hoist the base address of a GetElementPtr. This prevents the 2711 // creation of new constants for every base constant that gets constant 2712 // folded with the offset. 2713 if (Idx == 0) 2714 return 2 * TTI::TCC_Basic; 2715 return TTI::TCC_Free; 2716 case Instruction::Store: 2717 ImmIdx = 0; 2718 break; 2719 case Instruction::ICmp: 2720 // This is an imperfect hack to prevent constant hoisting of 2721 // compares that might be trying to check if a 64-bit value fits in 2722 // 32-bits. The backend can optimize these cases using a right shift by 32. 2723 // Ideally we would check the compare predicate here. There also other 2724 // similar immediates the backend can use shifts for. 2725 if (Idx == 1 && Imm.getBitWidth() == 64) { 2726 uint64_t ImmVal = Imm.getZExtValue(); 2727 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 2728 return TTI::TCC_Free; 2729 } 2730 ImmIdx = 1; 2731 break; 2732 case Instruction::And: 2733 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 2734 // by using a 32-bit operation with implicit zero extension. Detect such 2735 // immediates here as the normal path expects bit 31 to be sign extended. 2736 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 2737 return TTI::TCC_Free; 2738 ImmIdx = 1; 2739 break; 2740 case Instruction::Add: 2741 case Instruction::Sub: 2742 // For add/sub, we can use the opposite instruction for INT32_MIN. 2743 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 2744 return TTI::TCC_Free; 2745 ImmIdx = 1; 2746 break; 2747 case Instruction::UDiv: 2748 case Instruction::SDiv: 2749 case Instruction::URem: 2750 case Instruction::SRem: 2751 // Division by constant is typically expanded later into a different 2752 // instruction sequence. This completely changes the constants. 2753 // Report them as "free" to stop ConstantHoist from marking them as opaque. 2754 return TTI::TCC_Free; 2755 case Instruction::Mul: 2756 case Instruction::Or: 2757 case Instruction::Xor: 2758 ImmIdx = 1; 2759 break; 2760 // Always return TCC_Free for the shift value of a shift instruction. 2761 case Instruction::Shl: 2762 case Instruction::LShr: 2763 case Instruction::AShr: 2764 if (Idx == 1) 2765 return TTI::TCC_Free; 2766 break; 2767 case Instruction::Trunc: 2768 case Instruction::ZExt: 2769 case Instruction::SExt: 2770 case Instruction::IntToPtr: 2771 case Instruction::PtrToInt: 2772 case Instruction::BitCast: 2773 case Instruction::PHI: 2774 case Instruction::Call: 2775 case Instruction::Select: 2776 case Instruction::Ret: 2777 case Instruction::Load: 2778 break; 2779 } 2780 2781 if (Idx == ImmIdx) { 2782 int NumConstants = divideCeil(BitSize, 64); 2783 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty); 2784 return (Cost <= NumConstants * TTI::TCC_Basic) 2785 ? static_cast<int>(TTI::TCC_Free) 2786 : Cost; 2787 } 2788 2789 return X86TTIImpl::getIntImmCost(Imm, Ty); 2790 } 2791 2792 int X86TTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, 2793 Type *Ty) { 2794 assert(Ty->isIntegerTy()); 2795 2796 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 2797 // There is no cost model for constants with a bit size of 0. Return TCC_Free 2798 // here, so that constant hoisting will ignore this constant. 2799 if (BitSize == 0) 2800 return TTI::TCC_Free; 2801 2802 switch (IID) { 2803 default: 2804 return TTI::TCC_Free; 2805 case Intrinsic::sadd_with_overflow: 2806 case Intrinsic::uadd_with_overflow: 2807 case Intrinsic::ssub_with_overflow: 2808 case Intrinsic::usub_with_overflow: 2809 case Intrinsic::smul_with_overflow: 2810 case Intrinsic::umul_with_overflow: 2811 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 2812 return TTI::TCC_Free; 2813 break; 2814 case Intrinsic::experimental_stackmap: 2815 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 2816 return TTI::TCC_Free; 2817 break; 2818 case Intrinsic::experimental_patchpoint_void: 2819 case Intrinsic::experimental_patchpoint_i64: 2820 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 2821 return TTI::TCC_Free; 2822 break; 2823 } 2824 return X86TTIImpl::getIntImmCost(Imm, Ty); 2825 } 2826 2827 unsigned X86TTIImpl::getUserCost(const User *U, 2828 ArrayRef<const Value *> Operands) { 2829 if (isa<StoreInst>(U)) { 2830 Value *Ptr = U->getOperand(1); 2831 // Store instruction with index and scale costs 2 Uops. 2832 // Check the preceding GEP to identify non-const indices. 2833 if (auto GEP = dyn_cast<GetElementPtrInst>(Ptr)) { 2834 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 2835 return TTI::TCC_Basic * 2; 2836 } 2837 return TTI::TCC_Basic; 2838 } 2839 return BaseT::getUserCost(U, Operands); 2840 } 2841 2842 // Return an average cost of Gather / Scatter instruction, maybe improved later 2843 int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, Value *Ptr, 2844 unsigned Alignment, unsigned AddressSpace) { 2845 2846 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 2847 unsigned VF = SrcVTy->getVectorNumElements(); 2848 2849 // Try to reduce index size from 64 bit (default for GEP) 2850 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 2851 // operation will use 16 x 64 indices which do not fit in a zmm and needs 2852 // to split. Also check that the base pointer is the same for all lanes, 2853 // and that there's at most one variable index. 2854 auto getIndexSizeInBits = [](Value *Ptr, const DataLayout& DL) { 2855 unsigned IndexSize = DL.getPointerSizeInBits(); 2856 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 2857 if (IndexSize < 64 || !GEP) 2858 return IndexSize; 2859 2860 unsigned NumOfVarIndices = 0; 2861 Value *Ptrs = GEP->getPointerOperand(); 2862 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 2863 return IndexSize; 2864 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 2865 if (isa<Constant>(GEP->getOperand(i))) 2866 continue; 2867 Type *IndxTy = GEP->getOperand(i)->getType(); 2868 if (IndxTy->isVectorTy()) 2869 IndxTy = IndxTy->getVectorElementType(); 2870 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 2871 !isa<SExtInst>(GEP->getOperand(i))) || 2872 ++NumOfVarIndices > 1) 2873 return IndexSize; // 64 2874 } 2875 return (unsigned)32; 2876 }; 2877 2878 2879 // Trying to reduce IndexSize to 32 bits for vector 16. 2880 // By default the IndexSize is equal to pointer size. 2881 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 2882 ? getIndexSizeInBits(Ptr, DL) 2883 : DL.getPointerSizeInBits(); 2884 2885 Type *IndexVTy = VectorType::get(IntegerType::get(SrcVTy->getContext(), 2886 IndexSize), VF); 2887 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy); 2888 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy); 2889 int SplitFactor = std::max(IdxsLT.first, SrcLT.first); 2890 if (SplitFactor > 1) { 2891 // Handle splitting of vector of pointers 2892 Type *SplitSrcTy = VectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 2893 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 2894 AddressSpace); 2895 } 2896 2897 // The gather / scatter cost is given by Intel architects. It is a rough 2898 // number since we are looking at one instruction in a time. 2899 const int GSOverhead = (Opcode == Instruction::Load) 2900 ? ST->getGatherOverhead() 2901 : ST->getScatterOverhead(); 2902 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2903 Alignment, AddressSpace); 2904 } 2905 2906 /// Return the cost of full scalarization of gather / scatter operation. 2907 /// 2908 /// Opcode - Load or Store instruction. 2909 /// SrcVTy - The type of the data vector that should be gathered or scattered. 2910 /// VariableMask - The mask is non-constant at compile time. 2911 /// Alignment - Alignment for one element. 2912 /// AddressSpace - pointer[s] address space. 2913 /// 2914 int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 2915 bool VariableMask, unsigned Alignment, 2916 unsigned AddressSpace) { 2917 unsigned VF = SrcVTy->getVectorNumElements(); 2918 2919 int MaskUnpackCost = 0; 2920 if (VariableMask) { 2921 VectorType *MaskTy = 2922 VectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 2923 MaskUnpackCost = getScalarizationOverhead(MaskTy, false, true); 2924 int ScalarCompareCost = 2925 getCmpSelInstrCost(Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), 2926 nullptr); 2927 int BranchCost = getCFInstrCost(Instruction::Br); 2928 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 2929 } 2930 2931 // The cost of the scalar loads/stores. 2932 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2933 Alignment, AddressSpace); 2934 2935 int InsertExtractCost = 0; 2936 if (Opcode == Instruction::Load) 2937 for (unsigned i = 0; i < VF; ++i) 2938 // Add the cost of inserting each scalar load into the vector 2939 InsertExtractCost += 2940 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 2941 else 2942 for (unsigned i = 0; i < VF; ++i) 2943 // Add the cost of extracting each element out of the data vector 2944 InsertExtractCost += 2945 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 2946 2947 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 2948 } 2949 2950 /// Calculate the cost of Gather / Scatter operation 2951 int X86TTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *SrcVTy, 2952 Value *Ptr, bool VariableMask, 2953 unsigned Alignment) { 2954 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 2955 unsigned VF = SrcVTy->getVectorNumElements(); 2956 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 2957 if (!PtrTy && Ptr->getType()->isVectorTy()) 2958 PtrTy = dyn_cast<PointerType>(Ptr->getType()->getVectorElementType()); 2959 assert(PtrTy && "Unexpected type for Ptr argument"); 2960 unsigned AddressSpace = PtrTy->getAddressSpace(); 2961 2962 bool Scalarize = false; 2963 if ((Opcode == Instruction::Load && !isLegalMaskedGather(SrcVTy)) || 2964 (Opcode == Instruction::Store && !isLegalMaskedScatter(SrcVTy))) 2965 Scalarize = true; 2966 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 2967 // Vector-4 of gather/scatter instruction does not exist on KNL. 2968 // We can extend it to 8 elements, but zeroing upper bits of 2969 // the mask vector will add more instructions. Right now we give the scalar 2970 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 2971 // is better in the VariableMask case. 2972 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 2973 Scalarize = true; 2974 2975 if (Scalarize) 2976 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 2977 AddressSpace); 2978 2979 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 2980 } 2981 2982 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 2983 TargetTransformInfo::LSRCost &C2) { 2984 // X86 specific here are "instruction number 1st priority". 2985 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 2986 C1.NumIVMuls, C1.NumBaseAdds, 2987 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 2988 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 2989 C2.NumIVMuls, C2.NumBaseAdds, 2990 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 2991 } 2992 2993 bool X86TTIImpl::canMacroFuseCmp() { 2994 return ST->hasMacroFusion(); 2995 } 2996 2997 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy) { 2998 // The backend can't handle a single element vector. 2999 if (isa<VectorType>(DataTy) && DataTy->getVectorNumElements() == 1) 3000 return false; 3001 Type *ScalarTy = DataTy->getScalarType(); 3002 int DataWidth = isa<PointerType>(ScalarTy) ? 3003 DL.getPointerSizeInBits() : ScalarTy->getPrimitiveSizeInBits(); 3004 3005 return ((DataWidth == 32 || DataWidth == 64) && ST->hasAVX()) || 3006 ((DataWidth == 8 || DataWidth == 16) && ST->hasBWI()); 3007 } 3008 3009 bool X86TTIImpl::isLegalMaskedStore(Type *DataType) { 3010 return isLegalMaskedLoad(DataType); 3011 } 3012 3013 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy) { 3014 // This function is called now in two cases: from the Loop Vectorizer 3015 // and from the Scalarizer. 3016 // When the Loop Vectorizer asks about legality of the feature, 3017 // the vectorization factor is not calculated yet. The Loop Vectorizer 3018 // sends a scalar type and the decision is based on the width of the 3019 // scalar element. 3020 // Later on, the cost model will estimate usage this intrinsic based on 3021 // the vector type. 3022 // The Scalarizer asks again about legality. It sends a vector type. 3023 // In this case we can reject non-power-of-2 vectors. 3024 // We also reject single element vectors as the type legalizer can't 3025 // scalarize it. 3026 if (isa<VectorType>(DataTy)) { 3027 unsigned NumElts = DataTy->getVectorNumElements(); 3028 if (NumElts == 1 || !isPowerOf2_32(NumElts)) 3029 return false; 3030 } 3031 Type *ScalarTy = DataTy->getScalarType(); 3032 int DataWidth = isa<PointerType>(ScalarTy) ? 3033 DL.getPointerSizeInBits() : ScalarTy->getPrimitiveSizeInBits(); 3034 3035 // Some CPUs have better gather performance than others. 3036 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 3037 // enable gather with a -march. 3038 return (DataWidth == 32 || DataWidth == 64) && 3039 (ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2())); 3040 } 3041 3042 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType) { 3043 // AVX2 doesn't support scatter 3044 if (!ST->hasAVX512()) 3045 return false; 3046 return isLegalMaskedGather(DataType); 3047 } 3048 3049 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 3050 EVT VT = TLI->getValueType(DL, DataType); 3051 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 3052 } 3053 3054 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 3055 return false; 3056 } 3057 3058 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 3059 const Function *Callee) const { 3060 const TargetMachine &TM = getTLI()->getTargetMachine(); 3061 3062 // Work this as a subsetting of subtarget features. 3063 const FeatureBitset &CallerBits = 3064 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 3065 const FeatureBitset &CalleeBits = 3066 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 3067 3068 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 3069 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 3070 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 3071 } 3072 3073 const X86TTIImpl::TTI::MemCmpExpansionOptions * 3074 X86TTIImpl::enableMemCmpExpansion(bool IsZeroCmp) const { 3075 // Only enable vector loads for equality comparison. 3076 // Right now the vector version is not as fast, see #33329. 3077 static const auto ThreeWayOptions = [this]() { 3078 TTI::MemCmpExpansionOptions Options; 3079 if (ST->is64Bit()) { 3080 Options.LoadSizes.push_back(8); 3081 } 3082 Options.LoadSizes.push_back(4); 3083 Options.LoadSizes.push_back(2); 3084 Options.LoadSizes.push_back(1); 3085 return Options; 3086 }(); 3087 static const auto EqZeroOptions = [this]() { 3088 TTI::MemCmpExpansionOptions Options; 3089 // TODO: enable AVX512 when the DAG is ready. 3090 // if (ST->hasAVX512()) Options.LoadSizes.push_back(64); 3091 if (ST->hasAVX2()) Options.LoadSizes.push_back(32); 3092 if (ST->hasSSE2()) Options.LoadSizes.push_back(16); 3093 if (ST->is64Bit()) { 3094 Options.LoadSizes.push_back(8); 3095 } 3096 Options.LoadSizes.push_back(4); 3097 Options.LoadSizes.push_back(2); 3098 Options.LoadSizes.push_back(1); 3099 // All GPR and vector loads can be unaligned. SIMD compare requires integer 3100 // vectors (SSE2/AVX2). 3101 Options.AllowOverlappingLoads = true; 3102 return Options; 3103 }(); 3104 return IsZeroCmp ? &EqZeroOptions : &ThreeWayOptions; 3105 } 3106 3107 bool X86TTIImpl::enableInterleavedAccessVectorization() { 3108 // TODO: We expect this to be beneficial regardless of arch, 3109 // but there are currently some unexplained performance artifacts on Atom. 3110 // As a temporary solution, disable on Atom. 3111 return !(ST->isAtom()); 3112 } 3113 3114 // Get estimation for interleaved load/store operations for AVX2. 3115 // \p Factor is the interleaved-access factor (stride) - number of 3116 // (interleaved) elements in the group. 3117 // \p Indices contains the indices for a strided load: when the 3118 // interleaved load has gaps they indicate which elements are used. 3119 // If Indices is empty (or if the number of indices is equal to the size 3120 // of the interleaved-access as given in \p Factor) the access has no gaps. 3121 // 3122 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 3123 // computing the cost using a generic formula as a function of generic 3124 // shuffles. We therefore use a lookup table instead, filled according to 3125 // the instruction sequences that codegen currently generates. 3126 int X86TTIImpl::getInterleavedMemoryOpCostAVX2(unsigned Opcode, Type *VecTy, 3127 unsigned Factor, 3128 ArrayRef<unsigned> Indices, 3129 unsigned Alignment, 3130 unsigned AddressSpace, 3131 bool UseMaskForCond, 3132 bool UseMaskForGaps) { 3133 3134 if (UseMaskForCond || UseMaskForGaps) 3135 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3136 Alignment, AddressSpace, 3137 UseMaskForCond, UseMaskForGaps); 3138 3139 // We currently Support only fully-interleaved groups, with no gaps. 3140 // TODO: Support also strided loads (interleaved-groups with gaps). 3141 if (Indices.size() && Indices.size() != Factor) 3142 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3143 Alignment, AddressSpace); 3144 3145 // VecTy for interleave memop is <VF*Factor x Elt>. 3146 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 3147 // VecTy = <12 x i32>. 3148 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 3149 3150 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 3151 // the VF=2, while v2i128 is an unsupported MVT vector type 3152 // (see MachineValueType.h::getVectorVT()). 3153 if (!LegalVT.isVector()) 3154 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3155 Alignment, AddressSpace); 3156 3157 unsigned VF = VecTy->getVectorNumElements() / Factor; 3158 Type *ScalarTy = VecTy->getVectorElementType(); 3159 3160 // Calculate the number of memory operations (NumOfMemOps), required 3161 // for load/store the VecTy. 3162 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 3163 unsigned LegalVTSize = LegalVT.getStoreSize(); 3164 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 3165 3166 // Get the cost of one memory operation. 3167 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(), 3168 LegalVT.getVectorNumElements()); 3169 unsigned MemOpCost = 3170 getMemoryOpCost(Opcode, SingleMemOpTy, Alignment, AddressSpace); 3171 3172 VectorType *VT = VectorType::get(ScalarTy, VF); 3173 EVT ETy = TLI->getValueType(DL, VT); 3174 if (!ETy.isSimple()) 3175 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3176 Alignment, AddressSpace); 3177 3178 // TODO: Complete for other data-types and strides. 3179 // Each combination of Stride, ElementTy and VF results in a different 3180 // sequence; The cost tables are therefore accessed with: 3181 // Factor (stride) and VectorType=VFxElemType. 3182 // The Cost accounts only for the shuffle sequence; 3183 // The cost of the loads/stores is accounted for separately. 3184 // 3185 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 3186 { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64 3187 { 2, MVT::v4f64, 6 }, //(load 8f64 and) deinterleave into 2 x 4f64 3188 3189 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8 3190 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8 3191 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8 3192 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8 3193 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8 3194 { 3, MVT::v8f32, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32 3195 3196 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8 3197 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8 3198 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8 3199 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8 3200 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8 3201 3202 { 8, MVT::v8f32, 40 } //(load 64f32 and)deinterleave into 8 x 8f32 3203 }; 3204 3205 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 3206 { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store) 3207 { 2, MVT::v4f64, 6 }, //interleave into 2 x 4f64 into 8f64 (and store) 3208 3209 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store) 3210 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store) 3211 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store) 3212 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store) 3213 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store) 3214 3215 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store) 3216 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store) 3217 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store) 3218 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store) 3219 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store) 3220 }; 3221 3222 if (Opcode == Instruction::Load) { 3223 if (const auto *Entry = 3224 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 3225 return NumOfMemOps * MemOpCost + Entry->Cost; 3226 } else { 3227 assert(Opcode == Instruction::Store && 3228 "Expected Store Instruction at this point"); 3229 if (const auto *Entry = 3230 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 3231 return NumOfMemOps * MemOpCost + Entry->Cost; 3232 } 3233 3234 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3235 Alignment, AddressSpace); 3236 } 3237 3238 // Get estimation for interleaved load/store operations and strided load. 3239 // \p Indices contains indices for strided load. 3240 // \p Factor - the factor of interleaving. 3241 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 3242 int X86TTIImpl::getInterleavedMemoryOpCostAVX512(unsigned Opcode, Type *VecTy, 3243 unsigned Factor, 3244 ArrayRef<unsigned> Indices, 3245 unsigned Alignment, 3246 unsigned AddressSpace, 3247 bool UseMaskForCond, 3248 bool UseMaskForGaps) { 3249 3250 if (UseMaskForCond || UseMaskForGaps) 3251 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3252 Alignment, AddressSpace, 3253 UseMaskForCond, UseMaskForGaps); 3254 3255 // VecTy for interleave memop is <VF*Factor x Elt>. 3256 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 3257 // VecTy = <12 x i32>. 3258 3259 // Calculate the number of memory operations (NumOfMemOps), required 3260 // for load/store the VecTy. 3261 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 3262 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 3263 unsigned LegalVTSize = LegalVT.getStoreSize(); 3264 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 3265 3266 // Get the cost of one memory operation. 3267 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(), 3268 LegalVT.getVectorNumElements()); 3269 unsigned MemOpCost = 3270 getMemoryOpCost(Opcode, SingleMemOpTy, Alignment, AddressSpace); 3271 3272 unsigned VF = VecTy->getVectorNumElements() / Factor; 3273 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 3274 3275 if (Opcode == Instruction::Load) { 3276 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 3277 // contain the cost of the optimized shuffle sequence that the 3278 // X86InterleavedAccess pass will generate. 3279 // The cost of loads and stores are computed separately from the table. 3280 3281 // X86InterleavedAccess support only the following interleaved-access group. 3282 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 3283 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 3284 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 3285 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 3286 }; 3287 3288 if (const auto *Entry = 3289 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 3290 return NumOfMemOps * MemOpCost + Entry->Cost; 3291 //If an entry does not exist, fallback to the default implementation. 3292 3293 // Kind of shuffle depends on number of loaded values. 3294 // If we load the entire data in one register, we can use a 1-src shuffle. 3295 // Otherwise, we'll merge 2 sources in each operation. 3296 TTI::ShuffleKind ShuffleKind = 3297 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 3298 3299 unsigned ShuffleCost = 3300 getShuffleCost(ShuffleKind, SingleMemOpTy, 0, nullptr); 3301 3302 unsigned NumOfLoadsInInterleaveGrp = 3303 Indices.size() ? Indices.size() : Factor; 3304 Type *ResultTy = VectorType::get(VecTy->getVectorElementType(), 3305 VecTy->getVectorNumElements() / Factor); 3306 unsigned NumOfResults = 3307 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 3308 NumOfLoadsInInterleaveGrp; 3309 3310 // About a half of the loads may be folded in shuffles when we have only 3311 // one result. If we have more than one result, we do not fold loads at all. 3312 unsigned NumOfUnfoldedLoads = 3313 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 3314 3315 // Get a number of shuffle operations per result. 3316 unsigned NumOfShufflesPerResult = 3317 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 3318 3319 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 3320 // When we have more than one destination, we need additional instructions 3321 // to keep sources. 3322 unsigned NumOfMoves = 0; 3323 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 3324 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 3325 3326 int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 3327 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 3328 3329 return Cost; 3330 } 3331 3332 // Store. 3333 assert(Opcode == Instruction::Store && 3334 "Expected Store Instruction at this point"); 3335 // X86InterleavedAccess support only the following interleaved-access group. 3336 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 3337 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 3338 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 3339 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 3340 3341 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 3342 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 3343 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 3344 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 3345 }; 3346 3347 if (const auto *Entry = 3348 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 3349 return NumOfMemOps * MemOpCost + Entry->Cost; 3350 //If an entry does not exist, fallback to the default implementation. 3351 3352 // There is no strided stores meanwhile. And store can't be folded in 3353 // shuffle. 3354 unsigned NumOfSources = Factor; // The number of values to be merged. 3355 unsigned ShuffleCost = 3356 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, 0, nullptr); 3357 unsigned NumOfShufflesPerStore = NumOfSources - 1; 3358 3359 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 3360 // We need additional instructions to keep sources. 3361 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 3362 int Cost = NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 3363 NumOfMoves; 3364 return Cost; 3365 } 3366 3367 int X86TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, 3368 unsigned Factor, 3369 ArrayRef<unsigned> Indices, 3370 unsigned Alignment, 3371 unsigned AddressSpace, 3372 bool UseMaskForCond, 3373 bool UseMaskForGaps) { 3374 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 3375 Type *EltTy = VecTy->getVectorElementType(); 3376 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 3377 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 3378 return true; 3379 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 3380 return HasBW; 3381 return false; 3382 }; 3383 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 3384 return getInterleavedMemoryOpCostAVX512(Opcode, VecTy, Factor, Indices, 3385 Alignment, AddressSpace, 3386 UseMaskForCond, UseMaskForGaps); 3387 if (ST->hasAVX2()) 3388 return getInterleavedMemoryOpCostAVX2(Opcode, VecTy, Factor, Indices, 3389 Alignment, AddressSpace, 3390 UseMaskForCond, UseMaskForGaps); 3391 3392 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3393 Alignment, AddressSpace, 3394 UseMaskForCond, UseMaskForGaps); 3395 } 3396